1 /* 2 ******************************************************************************** 3 ** OS : FreeBSD 4 ** FILE NAME : arcmsr.h 5 ** BY : Erich Chen, Ching Huang 6 ** Description: SCSI RAID Device Driver for 7 ** ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x) 8 ** SATA/SAS RAID HOST Adapter 9 ******************************************************************************** 10 ******************************************************************************** 11 ** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved. 12 ** 13 ** Redistribution and use in source and binary forms,with or without 14 ** modification,are permitted provided that the following conditions 15 ** are met: 16 ** 1. Redistributions of source code must retain the above copyright 17 ** notice,this list of conditions and the following disclaimer. 18 ** 2. Redistributions in binary form must reproduce the above copyright 19 ** notice,this list of conditions and the following disclaimer in the 20 ** documentation and/or other materials provided with the distribution. 21 ** 3. The name of the author may not be used to endorse or promote products 22 ** derived from this software without specific prior written permission. 23 ** 24 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 ** IMPLIED WARRANTIES,INCLUDING,BUT NOT LIMITED TO,THE IMPLIED WARRANTIES 26 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,INDIRECT, 28 ** INCIDENTAL,SPECIAL,EXEMPLARY,OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT 29 ** NOT LIMITED TO,PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 ** DATA,OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 31 ** THEORY OF LIABILITY,WHETHER IN CONTRACT,STRICT LIABILITY,OR TORT 32 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 33 ** THIS SOFTWARE,EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 ************************************************************************** 35 * $FreeBSD$ 36 */ 37 #define ARCMSR_SCSI_INITIATOR_ID 255 38 #define ARCMSR_DEV_SECTOR_SIZE 512 39 #define ARCMSR_MAX_XFER_SECTORS 4096 40 #define ARCMSR_MAX_TARGETID 17 /*16 max target id + 1*/ 41 #define ARCMSR_MAX_TARGETLUN 8 /*8*/ 42 #define ARCMSR_MAX_CHIPTYPE_NUM 4 43 #define ARCMSR_MAX_OUTSTANDING_CMD 256 44 #define ARCMSR_MAX_START_JOB 256 45 #define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_OUTSTANDING_CMD 46 #define ARCMSR_MAX_FREESRB_NUM 384 47 #define ARCMSR_MAX_QBUFFER 4096 /* ioctl QBUFFER */ 48 #define ARCMSR_MAX_SG_ENTRIES 38 /* max 38*/ 49 #define ARCMSR_MAX_ADAPTER 4 50 #define ARCMSR_RELEASE_SIMQ_LEVEL 230 51 #define ARCMSR_MAX_HBB_POSTQUEUE 264 /* (ARCMSR_MAX_OUTSTANDING_CMD+8) */ 52 #define ARCMSR_MAX_HBD_POSTQUEUE 256 53 #define ARCMSR_TIMEOUT_DELAY 60 /* in sec */ 54 /* 55 ********************************************************************* 56 */ 57 #ifndef TRUE 58 #define TRUE 1 59 #endif 60 #ifndef FALSE 61 #define FALSE 0 62 #endif 63 #ifndef INTR_ENTROPY 64 # define INTR_ENTROPY 0 65 #endif 66 67 #ifndef offsetof 68 #define offsetof(type, member) ((size_t)(&((type *)0)->member)) 69 #endif 70 71 #if __FreeBSD_version >= 500005 72 #define ARCMSR_LOCK_INIT(l, s) mtx_init(l, s, NULL, MTX_DEF) 73 #define ARCMSR_LOCK_DESTROY(l) mtx_destroy(l) 74 #define ARCMSR_LOCK_ACQUIRE(l) mtx_lock(l) 75 #define ARCMSR_LOCK_RELEASE(l) mtx_unlock(l) 76 #define ARCMSR_LOCK_TRY(l) mtx_trylock(l) 77 #define arcmsr_htole32(x) htole32(x) 78 typedef struct mtx arcmsr_lock_t; 79 #else 80 #define ARCMSR_LOCK_INIT(l, s) simple_lock_init(l) 81 #define ARCMSR_LOCK_DESTROY(l) 82 #define ARCMSR_LOCK_ACQUIRE(l) simple_lock(l) 83 #define ARCMSR_LOCK_RELEASE(l) simple_unlock(l) 84 #define ARCMSR_LOCK_TRY(l) simple_lock_try(l) 85 #define arcmsr_htole32(x) (x) 86 typedef struct simplelock arcmsr_lock_t; 87 #endif 88 89 /* 90 ********************************************************************************** 91 ** 92 ********************************************************************************** 93 */ 94 #define PCI_VENDOR_ID_ARECA 0x17D3 /* Vendor ID */ 95 #define PCI_DEVICE_ID_ARECA_1110 0x1110 /* Device ID */ 96 #define PCI_DEVICE_ID_ARECA_1120 0x1120 /* Device ID */ 97 #define PCI_DEVICE_ID_ARECA_1130 0x1130 /* Device ID */ 98 #define PCI_DEVICE_ID_ARECA_1160 0x1160 /* Device ID */ 99 #define PCI_DEVICE_ID_ARECA_1170 0x1170 /* Device ID */ 100 #define PCI_DEVICE_ID_ARECA_1200 0x1200 /* Device ID */ 101 #define PCI_DEVICE_ID_ARECA_1201 0x1201 /* Device ID */ 102 #define PCI_DEVICE_ID_ARECA_1203 0x1203 /* Device ID */ 103 #define PCI_DEVICE_ID_ARECA_1210 0x1210 /* Device ID */ 104 #define PCI_DEVICE_ID_ARECA_1212 0x1212 /* Device ID */ 105 #define PCI_DEVICE_ID_ARECA_1214 0x1214 /* Device ID */ 106 #define PCI_DEVICE_ID_ARECA_1220 0x1220 /* Device ID */ 107 #define PCI_DEVICE_ID_ARECA_1222 0x1222 /* Device ID */ 108 #define PCI_DEVICE_ID_ARECA_1230 0x1230 /* Device ID */ 109 #define PCI_DEVICE_ID_ARECA_1231 0x1231 /* Device ID */ 110 #define PCI_DEVICE_ID_ARECA_1260 0x1260 /* Device ID */ 111 #define PCI_DEVICE_ID_ARECA_1261 0x1261 /* Device ID */ 112 #define PCI_DEVICE_ID_ARECA_1270 0x1270 /* Device ID */ 113 #define PCI_DEVICE_ID_ARECA_1280 0x1280 /* Device ID */ 114 #define PCI_DEVICE_ID_ARECA_1380 0x1380 /* Device ID */ 115 #define PCI_DEVICE_ID_ARECA_1381 0x1381 /* Device ID */ 116 #define PCI_DEVICE_ID_ARECA_1680 0x1680 /* Device ID */ 117 #define PCI_DEVICE_ID_ARECA_1681 0x1681 /* Device ID */ 118 #define PCI_DEVICE_ID_ARECA_1880 0x1880 /* Device ID */ 119 120 #define ARECA_SUB_DEV_ID_1880 0x1880 /* Subsystem Device ID */ 121 #define ARECA_SUB_DEV_ID_1882 0x1882 /* Subsystem Device ID */ 122 #define ARECA_SUB_DEV_ID_1883 0x1883 /* Subsystem Device ID */ 123 #define ARECA_SUB_DEV_ID_1212 0x1212 /* Subsystem Device ID */ 124 #define ARECA_SUB_DEV_ID_1213 0x1213 /* Subsystem Device ID */ 125 #define ARECA_SUB_DEV_ID_1222 0x1222 /* Subsystem Device ID */ 126 #define ARECA_SUB_DEV_ID_1223 0x1223 /* Subsystem Device ID */ 127 128 #define PCIDevVenIDARC1110 0x111017D3 /* Vendor Device ID */ 129 #define PCIDevVenIDARC1120 0x112017D3 /* Vendor Device ID */ 130 #define PCIDevVenIDARC1130 0x113017D3 /* Vendor Device ID */ 131 #define PCIDevVenIDARC1160 0x116017D3 /* Vendor Device ID */ 132 #define PCIDevVenIDARC1170 0x117017D3 /* Vendor Device ID */ 133 #define PCIDevVenIDARC1200 0x120017D3 /* Vendor Device ID */ 134 #define PCIDevVenIDARC1201 0x120117D3 /* Vendor Device ID */ 135 #define PCIDevVenIDARC1203 0x120317D3 /* Vendor Device ID */ 136 #define PCIDevVenIDARC1210 0x121017D3 /* Vendor Device ID */ 137 #define PCIDevVenIDARC1212 0x121217D3 /* Vendor Device ID */ 138 #define PCIDevVenIDARC1213 0x121317D3 /* Vendor Device ID */ 139 #define PCIDevVenIDARC1214 0x121417D3 /* Vendor Device ID */ 140 #define PCIDevVenIDARC1220 0x122017D3 /* Vendor Device ID */ 141 #define PCIDevVenIDARC1222 0x122217D3 /* Vendor Device ID */ 142 #define PCIDevVenIDARC1223 0x122317D3 /* Vendor Device ID */ 143 #define PCIDevVenIDARC1230 0x123017D3 /* Vendor Device ID */ 144 #define PCIDevVenIDARC1231 0x123117D3 /* Vendor Device ID */ 145 #define PCIDevVenIDARC1260 0x126017D3 /* Vendor Device ID */ 146 #define PCIDevVenIDARC1261 0x126117D3 /* Vendor Device ID */ 147 #define PCIDevVenIDARC1270 0x127017D3 /* Vendor Device ID */ 148 #define PCIDevVenIDARC1280 0x128017D3 /* Vendor Device ID */ 149 #define PCIDevVenIDARC1380 0x138017D3 /* Vendor Device ID */ 150 #define PCIDevVenIDARC1381 0x138117D3 /* Vendor Device ID */ 151 #define PCIDevVenIDARC1680 0x168017D3 /* Vendor Device ID */ 152 #define PCIDevVenIDARC1681 0x168117D3 /* Vendor Device ID */ 153 #define PCIDevVenIDARC1880 0x188017D3 /* Vendor Device ID */ 154 #define PCIDevVenIDARC1882 0x188217D3 /* Vendor Device ID */ 155 156 #ifndef PCIR_BARS 157 #define PCIR_BARS 0x10 158 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4) 159 #endif 160 161 #define PCI_BASE_ADDR0 0x10 162 #define PCI_BASE_ADDR1 0x14 163 #define PCI_BASE_ADDR2 0x18 164 #define PCI_BASE_ADDR3 0x1C 165 #define PCI_BASE_ADDR4 0x20 166 #define PCI_BASE_ADDR5 0x24 167 /* 168 ********************************************************************************** 169 ** 170 ********************************************************************************** 171 */ 172 #define ARCMSR_SCSICMD_IOCTL 0x77 173 #define ARCMSR_CDEVSW_IOCTL 0x88 174 #define ARCMSR_MESSAGE_FAIL 0x0001 175 #define ARCMSR_MESSAGE_SUCCESS 0x0000 176 /* 177 ********************************************************************************** 178 ** 179 ********************************************************************************** 180 */ 181 #define arcmsr_ccbsrb_ptr spriv_ptr0 182 #define arcmsr_ccbacb_ptr spriv_ptr1 183 #define dma_addr_hi32(addr) (u_int32_t) ((addr>>16)>>16) 184 #define dma_addr_lo32(addr) (u_int32_t) (addr & 0xffffffff) 185 #define get_min(x,y) ((x) < (y) ? (x) : (y)) 186 #define get_max(x,y) ((x) < (y) ? (y) : (x)) 187 /* 188 ************************************************************************** 189 ************************************************************************** 190 */ 191 #define CHIP_REG_READ32(s, b, r) bus_space_read_4(acb->btag[b], acb->bhandle[b], offsetof(struct s, r)) 192 #define CHIP_REG_WRITE32(s, b, r, d) bus_space_write_4(acb->btag[b], acb->bhandle[b], offsetof(struct s, r), d) 193 #define READ_CHIP_REG32(b, r) bus_space_read_4(acb->btag[b], acb->bhandle[b], r) 194 #define WRITE_CHIP_REG32(b, r, d) bus_space_write_4(acb->btag[b], acb->bhandle[b], r, d) 195 /* 196 ********************************************************************************** 197 ** IOCTL CONTROL Mail Box 198 ********************************************************************************** 199 */ 200 struct CMD_MESSAGE { 201 u_int32_t HeaderLength; 202 u_int8_t Signature[8]; 203 u_int32_t Timeout; 204 u_int32_t ControlCode; 205 u_int32_t ReturnCode; 206 u_int32_t Length; 207 }; 208 209 struct CMD_MESSAGE_FIELD { 210 struct CMD_MESSAGE cmdmessage; /* ioctl header */ 211 u_int8_t messagedatabuffer[1032]; /* areca gui program does not accept more than 1031 byte */ 212 }; 213 214 /************************************************************************/ 215 /************************************************************************/ 216 217 #define ARCMSR_IOP_ERROR_ILLEGALPCI 0x0001 218 #define ARCMSR_IOP_ERROR_VENDORID 0x0002 219 #define ARCMSR_IOP_ERROR_DEVICEID 0x0002 220 #define ARCMSR_IOP_ERROR_ILLEGALCDB 0x0003 221 #define ARCMSR_IOP_ERROR_UNKNOW_CDBERR 0x0004 222 #define ARCMSR_SYS_ERROR_MEMORY_ALLOCATE 0x0005 223 #define ARCMSR_SYS_ERROR_MEMORY_CROSS4G 0x0006 224 #define ARCMSR_SYS_ERROR_MEMORY_LACK 0x0007 225 #define ARCMSR_SYS_ERROR_MEMORY_RANGE 0x0008 226 #define ARCMSR_SYS_ERROR_DEVICE_BASE 0x0009 227 #define ARCMSR_SYS_ERROR_PORT_VALIDATE 0x000A 228 229 /*DeviceType*/ 230 #define ARECA_SATA_RAID 0x90000000 231 232 /*FunctionCode*/ 233 #define FUNCTION_READ_RQBUFFER 0x0801 234 #define FUNCTION_WRITE_WQBUFFER 0x0802 235 #define FUNCTION_CLEAR_RQBUFFER 0x0803 236 #define FUNCTION_CLEAR_WQBUFFER 0x0804 237 #define FUNCTION_CLEAR_ALLQBUFFER 0x0805 238 #define FUNCTION_REQUEST_RETURNCODE_3F 0x0806 239 #define FUNCTION_SAY_HELLO 0x0807 240 #define FUNCTION_SAY_GOODBYE 0x0808 241 #define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809 242 /* 243 ************************************************************************ 244 ** IOCTL CONTROL CODE 245 ************************************************************************ 246 */ 247 /* ARECA IO CONTROL CODE*/ 248 #define ARCMSR_MESSAGE_READ_RQBUFFER _IOWR('F', FUNCTION_READ_RQBUFFER, struct CMD_MESSAGE_FIELD) 249 #define ARCMSR_MESSAGE_WRITE_WQBUFFER _IOWR('F', FUNCTION_WRITE_WQBUFFER, struct CMD_MESSAGE_FIELD) 250 #define ARCMSR_MESSAGE_CLEAR_RQBUFFER _IOWR('F', FUNCTION_CLEAR_RQBUFFER, struct CMD_MESSAGE_FIELD) 251 #define ARCMSR_MESSAGE_CLEAR_WQBUFFER _IOWR('F', FUNCTION_CLEAR_WQBUFFER, struct CMD_MESSAGE_FIELD) 252 #define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER _IOWR('F', FUNCTION_CLEAR_ALLQBUFFER, struct CMD_MESSAGE_FIELD) 253 #define ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F _IOWR('F', FUNCTION_REQUEST_RETURNCODE_3F, struct CMD_MESSAGE_FIELD) 254 #define ARCMSR_MESSAGE_SAY_HELLO _IOWR('F', FUNCTION_SAY_HELLO, struct CMD_MESSAGE_FIELD) 255 #define ARCMSR_MESSAGE_SAY_GOODBYE _IOWR('F', FUNCTION_SAY_GOODBYE, struct CMD_MESSAGE_FIELD) 256 #define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE _IOWR('F', FUNCTION_FLUSH_ADAPTER_CACHE, struct CMD_MESSAGE_FIELD) 257 258 /* ARECA IOCTL ReturnCode */ 259 #define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001 260 #define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006 261 #define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F 262 #define ARCMSR_IOCTL_RETURNCODE_BUS_HANG_ON 0x00000088 263 /* 264 ************************************************************************ 265 ** SPEC. for Areca HBA adapter 266 ************************************************************************ 267 */ 268 /* signature of set and get firmware config */ 269 #define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060 270 #define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063 271 /* message code of inbound message register */ 272 #define ARCMSR_INBOUND_MESG0_NOP 0x00000000 273 #define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001 274 #define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002 275 #define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003 276 #define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004 277 #define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005 278 #define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006 279 #define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007 280 #define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008 281 /* doorbell interrupt generator */ 282 #define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001 283 #define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002 284 #define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001 285 #define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002 286 /* srb areca cdb flag */ 287 #define ARCMSR_SRBPOST_FLAG_SGL_BSIZE 0x80000000 288 #define ARCMSR_SRBPOST_FLAG_IAM_BIOS 0x40000000 289 #define ARCMSR_SRBREPLY_FLAG_IAM_BIOS 0x40000000 290 #define ARCMSR_SRBREPLY_FLAG_ERROR 0x10000000 291 #define ARCMSR_SRBREPLY_FLAG_ERROR_MODE0 0x10000000 292 #define ARCMSR_SRBREPLY_FLAG_ERROR_MODE1 0x00000001 293 /* outbound firmware ok */ 294 #define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000 295 296 #define ARCMSR_ARC1680_BUS_RESET 0x00000003 297 /* 298 ************************************************************************ 299 ** SPEC. for Areca HBB adapter 300 ************************************************************************ 301 */ 302 /* ARECA HBB COMMAND for its FIRMWARE */ 303 #define ARCMSR_DRV2IOP_DOORBELL 0x00020400 /* window of "instruction flags" from driver to iop */ 304 #define ARCMSR_DRV2IOP_DOORBELL_MASK 0x00020404 305 #define ARCMSR_IOP2DRV_DOORBELL 0x00020408 /* window of "instruction flags" from iop to driver */ 306 #define ARCMSR_IOP2DRV_DOORBELL_MASK 0x0002040C 307 308 #define ARCMSR_IOP2DRV_DOORBELL_1203 0x00021870 /* window of "instruction flags" from iop to driver */ 309 #define ARCMSR_IOP2DRV_DOORBELL_MASK_1203 0x00021874 310 #define ARCMSR_DRV2IOP_DOORBELL_1203 0x00021878 /* window of "instruction flags" from driver to iop */ 311 #define ARCMSR_DRV2IOP_DOORBELL_MASK_1203 0x0002187C 312 313 /* ARECA FLAG LANGUAGE */ 314 #define ARCMSR_IOP2DRV_DATA_WRITE_OK 0x00000001 /* ioctl transfer */ 315 #define ARCMSR_IOP2DRV_DATA_READ_OK 0x00000002 /* ioctl transfer */ 316 #define ARCMSR_IOP2DRV_CDB_DONE 0x00000004 317 #define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 318 319 #define ARCMSR_DOORBELL_HANDLE_INT 0x0000000F 320 #define ARCMSR_DOORBELL_INT_CLEAR_PATTERN 0xFF00FFF0 321 #define ARCMSR_MESSAGE_INT_CLEAR_PATTERN 0xFF00FFF7 322 323 #define ARCMSR_MESSAGE_GET_CONFIG 0x00010008 /* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 324 #define ARCMSR_MESSAGE_SET_CONFIG 0x00020008 /* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 325 #define ARCMSR_MESSAGE_ABORT_CMD 0x00030008 /* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 326 #define ARCMSR_MESSAGE_STOP_BGRB 0x00040008 /* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 327 #define ARCMSR_MESSAGE_FLUSH_CACHE 0x00050008 /* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 328 #define ARCMSR_MESSAGE_START_BGRB 0x00060008 /* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 329 #define ARCMSR_MESSAGE_START_DRIVER_MODE 0x000E0008 330 #define ARCMSR_MESSAGE_SET_POST_WINDOW 0x000F0008 331 #define ARCMSR_MESSAGE_ACTIVE_EOI_MODE 0x00100008 332 #define ARCMSR_MESSAGE_FIRMWARE_OK 0x80000000 /* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */ 333 334 #define ARCMSR_DRV2IOP_DATA_WRITE_OK 0x00000001 /* ioctl transfer */ 335 #define ARCMSR_DRV2IOP_DATA_READ_OK 0x00000002 /* ioctl transfer */ 336 #define ARCMSR_DRV2IOP_CDB_POSTED 0x00000004 337 #define ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED 0x00000008 338 #define ARCMSR_DRV2IOP_END_OF_INTERRUPT 0x00000010 /* */ 339 340 /* data tunnel buffer between user space program and its firmware */ 341 #define ARCMSR_MSGCODE_RWBUFFER 0x0000fa00 /* iop msgcode_rwbuffer for message command */ 342 #define ARCMSR_IOCTL_WBUFFER 0x0000fe00 /* user space data to iop 128bytes */ 343 #define ARCMSR_IOCTL_RBUFFER 0x0000ff00 /* iop data to user space 128bytes */ 344 #define ARCMSR_HBB_BASE0_OFFSET 0x00000010 345 #define ARCMSR_HBB_BASE1_OFFSET 0x00000018 346 #define ARCMSR_HBB_BASE0_LEN 0x00021000 347 #define ARCMSR_HBB_BASE1_LEN 0x00010000 348 /* 349 ************************************************************************ 350 ** SPEC. for Areca HBC adapter 351 ************************************************************************ 352 */ 353 #define ARCMSR_HBC_ISR_THROTTLING_LEVEL 12 354 #define ARCMSR_HBC_ISR_MAX_DONE_QUEUE 20 355 /* Host Interrupt Mask */ 356 #define ARCMSR_HBCMU_UTILITY_A_ISR_MASK 0x00000001 /* When clear, the Utility_A interrupt routes to the host.*/ 357 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK 0x00000004 /* When clear, the General Outbound Doorbell interrupt routes to the host.*/ 358 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK 0x00000008 /* When clear, the Outbound Post List FIFO Not Empty interrupt routes to the host.*/ 359 #define ARCMSR_HBCMU_ALL_INTMASKENABLE 0x0000000D /* disable all ISR */ 360 /* Host Interrupt Status */ 361 #define ARCMSR_HBCMU_UTILITY_A_ISR 0x00000001 362 /* 363 ** Set when the Utility_A Interrupt bit is set in the Outbound Doorbell Register. 364 ** It clears by writing a 1 to the Utility_A bit in the Outbound Doorbell Clear Register or through automatic clearing (if enabled). 365 */ 366 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR 0x00000004 367 /* 368 ** Set if Outbound Doorbell register bits 30:1 have a non-zero 369 ** value. This bit clears only when Outbound Doorbell bits 370 ** 30:1 are ALL clear. Only a write to the Outbound Doorbell 371 ** Clear register clears bits in the Outbound Doorbell register. 372 */ 373 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR 0x00000008 374 /* 375 ** Set whenever the Outbound Post List Producer/Consumer 376 ** Register (FIFO) is not empty. It clears when the Outbound 377 ** Post List FIFO is empty. 378 */ 379 #define ARCMSR_HBCMU_SAS_ALL_INT 0x00000010 380 /* 381 ** This bit indicates a SAS interrupt from a source external to 382 ** the PCIe core. This bit is not maskable. 383 */ 384 /* DoorBell*/ 385 #define ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK 0x00000002/**/ 386 #define ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK 0x00000004/**/ 387 #define ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008/*inbound message 0 ready*/ 388 #define ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING 0x00000010/*more than 12 request completed in a time*/ 389 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK 0x00000002/**/ 390 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR 0x00000002/*outbound DATA WRITE isr door bell clear*/ 391 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK 0x00000004/**/ 392 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR 0x00000004/*outbound DATA READ isr door bell clear*/ 393 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008/*outbound message 0 ready*/ 394 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR 0x00000008/*outbound message cmd isr door bell clear*/ 395 #define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK 0x80000000/*ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK*/ 396 #define ARCMSR_HBCMU_RESET_ADAPTER 0x00000024 397 #define ARCMSR_HBCMU_DiagWrite_ENABLE 0x00000080 398 399 /* 400 ************************************************************************ 401 ** SPEC. for Areca HBD adapter 402 ************************************************************************ 403 */ 404 #define ARCMSR_HBDMU_CHIP_ID 0x00004 405 #define ARCMSR_HBDMU_CPU_MEMORY_CONFIGURATION 0x00008 406 #define ARCMSR_HBDMU_I2_HOST_INTERRUPT_MASK 0x00034 407 #define ARCMSR_HBDMU_MAIN_INTERRUPT_STATUS 0x00200 408 #define ARCMSR_HBDMU_PCIE_F0_INTERRUPT_ENABLE 0x0020C 409 #define ARCMSR_HBDMU_INBOUND_MESSAGE0 0x00400 410 #define ARCMSR_HBDMU_INBOUND_MESSAGE1 0x00404 411 #define ARCMSR_HBDMU_OUTBOUND_MESSAGE0 0x00420 412 #define ARCMSR_HBDMU_OUTBOUND_MESSAGE1 0x00424 413 #define ARCMSR_HBDMU_INBOUND_DOORBELL 0x00460 414 #define ARCMSR_HBDMU_OUTBOUND_DOORBELL 0x00480 415 #define ARCMSR_HBDMU_OUTBOUND_DOORBELL_ENABLE 0x00484 416 #define ARCMSR_HBDMU_INBOUND_LIST_BASE_LOW 0x01000 417 #define ARCMSR_HBDMU_INBOUND_LIST_BASE_HIGH 0x01004 418 #define ARCMSR_HBDMU_INBOUND_LIST_WRITE_POINTER 0x01018 419 #define ARCMSR_HBDMU_OUTBOUND_LIST_BASE_LOW 0x01060 420 #define ARCMSR_HBDMU_OUTBOUND_LIST_BASE_HIGH 0x01064 421 #define ARCMSR_HBDMU_OUTBOUND_LIST_COPY_POINTER 0x0106C 422 #define ARCMSR_HBDMU_OUTBOUND_LIST_READ_POINTER 0x01070 423 #define ARCMSR_HBDMU_OUTBOUND_INTERRUPT_CAUSE 0x01088 424 #define ARCMSR_HBDMU_OUTBOUND_INTERRUPT_ENABLE 0x0108C 425 426 #define ARCMSR_HBDMU_MESSAGE_WBUFFER 0x02000 427 #define ARCMSR_HBDMU_MESSAGE_RBUFFER 0x02100 428 #define ARCMSR_HBDMU_MESSAGE_RWBUFFER 0x02200 429 430 #define ARCMSR_HBDMU_ISR_THROTTLING_LEVEL 16 431 #define ARCMSR_HBDMU_ISR_MAX_DONE_QUEUE 20 432 433 /* Host Interrupt Mask */ 434 #define ARCMSR_HBDMU_ALL_INT_ENABLE 0x00001010 /* enable all ISR */ 435 #define ARCMSR_HBDMU_ALL_INT_DISABLE 0x00000000 /* disable all ISR */ 436 437 /* Host Interrupt Status */ 438 #define ARCMSR_HBDMU_OUTBOUND_INT 0x00001010 439 #define ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT 0x00001000 440 #define ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT 0x00000010 441 442 /* DoorBell*/ 443 #define ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY 0x00000001 444 #define ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ 0x00000002 445 446 #define ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK 0x00000001 447 #define ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK 0x00000002 448 449 /*outbound message 0 ready*/ 450 #define ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE 0x02000000 451 452 #define ARCMSR_HBDMU_F0_DOORBELL_CAUSE 0x02000003 453 454 /*outbound message cmd isr door bell clear*/ 455 #define ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR 0x02000000 456 457 /*outbound list */ 458 #define ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT 0x00000001 459 #define ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR 0x00000001 460 461 /*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/ 462 #define ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK 0x80000000 463 /* 464 ********************************************************************* 465 ** Message Unit structure 466 ********************************************************************* 467 */ 468 struct HBA_MessageUnit 469 { 470 u_int32_t resrved0[4]; /*0000 000F*/ 471 u_int32_t inbound_msgaddr0; /*0010 0013*/ 472 u_int32_t inbound_msgaddr1; /*0014 0017*/ 473 u_int32_t outbound_msgaddr0; /*0018 001B*/ 474 u_int32_t outbound_msgaddr1; /*001C 001F*/ 475 u_int32_t inbound_doorbell; /*0020 0023*/ 476 u_int32_t inbound_intstatus; /*0024 0027*/ 477 u_int32_t inbound_intmask; /*0028 002B*/ 478 u_int32_t outbound_doorbell; /*002C 002F*/ 479 u_int32_t outbound_intstatus; /*0030 0033*/ 480 u_int32_t outbound_intmask; /*0034 0037*/ 481 u_int32_t reserved1[2]; /*0038 003F*/ 482 u_int32_t inbound_queueport; /*0040 0043*/ 483 u_int32_t outbound_queueport; /*0044 0047*/ 484 u_int32_t reserved2[2]; /*0048 004F*/ 485 u_int32_t reserved3[492]; /*0050 07FF ......local_buffer 492*/ 486 u_int32_t reserved4[128]; /*0800 09FF 128*/ 487 u_int32_t msgcode_rwbuffer[256]; /*0a00 0DFF 256*/ 488 u_int32_t message_wbuffer[32]; /*0E00 0E7F 32*/ 489 u_int32_t reserved5[32]; /*0E80 0EFF 32*/ 490 u_int32_t message_rbuffer[32]; /*0F00 0F7F 32*/ 491 u_int32_t reserved6[32]; /*0F80 0FFF 32*/ 492 }; 493 /* 494 ********************************************************************* 495 ** 496 ********************************************************************* 497 */ 498 struct HBB_DOORBELL_1203 499 { 500 u_int8_t doorbell_reserved[ARCMSR_IOP2DRV_DOORBELL_1203]; /*reserved */ 501 u_int32_t iop2drv_doorbell; /*offset 0x00021870:00,01,02,03: window of "instruction flags" from iop to driver */ 502 u_int32_t iop2drv_doorbell_mask; /* 04,05,06,07: doorbell mask */ 503 u_int32_t drv2iop_doorbell; /* 08,09,10,11: window of "instruction flags" from driver to iop */ 504 u_int32_t drv2iop_doorbell_mask; /* 12,13,14,15: doorbell mask */ 505 }; 506 struct HBB_DOORBELL 507 { 508 u_int8_t doorbell_reserved[ARCMSR_DRV2IOP_DOORBELL]; /*reserved */ 509 u_int32_t drv2iop_doorbell; /*offset 0x00020400:00,01,02,03: window of "instruction flags" from driver to iop */ 510 u_int32_t drv2iop_doorbell_mask; /* 04,05,06,07: doorbell mask */ 511 u_int32_t iop2drv_doorbell; /* 08,09,10,11: window of "instruction flags" from iop to driver */ 512 u_int32_t iop2drv_doorbell_mask; /* 12,13,14,15: doorbell mask */ 513 }; 514 /* 515 ********************************************************************* 516 ** 517 ********************************************************************* 518 */ 519 struct HBB_RWBUFFER 520 { 521 u_int8_t message_reserved0[ARCMSR_MSGCODE_RWBUFFER]; /*reserved */ 522 u_int32_t msgcode_rwbuffer[256]; /*offset 0x0000fa00: 0, 1, 2, 3,...,1023: message code read write 1024bytes */ 523 u_int32_t message_wbuffer[32]; /*offset 0x0000fe00:1024,1025,1026,1027,...,1151: user space data to iop 128bytes */ 524 u_int32_t message_reserved1[32]; /* 1152,1153,1154,1155,...,1279: message reserved*/ 525 u_int32_t message_rbuffer[32]; /*offset 0x0000ff00:1280,1281,1282,1283,...,1407: iop data to user space 128bytes */ 526 }; 527 /* 528 ********************************************************************* 529 ** 530 ********************************************************************* 531 */ 532 struct HBB_MessageUnit 533 { 534 u_int32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* post queue buffer for iop */ 535 u_int32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* done queue buffer for iop */ 536 int32_t postq_index; /* post queue index */ 537 int32_t doneq_index; /* done queue index */ 538 struct HBB_DOORBELL *hbb_doorbell; 539 struct HBB_RWBUFFER *hbb_rwbuffer; 540 bus_size_t drv2iop_doorbell; /* window of "instruction flags" from driver to iop */ 541 bus_size_t drv2iop_doorbell_mask; /* doorbell mask */ 542 bus_size_t iop2drv_doorbell; /* window of "instruction flags" from iop to driver */ 543 bus_size_t iop2drv_doorbell_mask; /* doorbell mask */ 544 }; 545 546 /* 547 ********************************************************************* 548 ** 549 ********************************************************************* 550 */ 551 struct HBC_MessageUnit { 552 u_int32_t message_unit_status; /*0000 0003*/ 553 u_int32_t slave_error_attribute; /*0004 0007*/ 554 u_int32_t slave_error_address; /*0008 000B*/ 555 u_int32_t posted_outbound_doorbell; /*000C 000F*/ 556 u_int32_t master_error_attribute; /*0010 0013*/ 557 u_int32_t master_error_address_low; /*0014 0017*/ 558 u_int32_t master_error_address_high; /*0018 001B*/ 559 u_int32_t hcb_size; /*001C 001F size of the PCIe window used for HCB_Mode accesses*/ 560 u_int32_t inbound_doorbell; /*0020 0023*/ 561 u_int32_t diagnostic_rw_data; /*0024 0027*/ 562 u_int32_t diagnostic_rw_address_low; /*0028 002B*/ 563 u_int32_t diagnostic_rw_address_high; /*002C 002F*/ 564 u_int32_t host_int_status; /*0030 0033 host interrupt status*/ 565 u_int32_t host_int_mask; /*0034 0037 host interrupt mask*/ 566 u_int32_t dcr_data; /*0038 003B*/ 567 u_int32_t dcr_address; /*003C 003F*/ 568 u_int32_t inbound_queueport; /*0040 0043 port32 host inbound queue port*/ 569 u_int32_t outbound_queueport; /*0044 0047 port32 host outbound queue port*/ 570 u_int32_t hcb_pci_address_low; /*0048 004B*/ 571 u_int32_t hcb_pci_address_high; /*004C 004F*/ 572 u_int32_t iop_int_status; /*0050 0053*/ 573 u_int32_t iop_int_mask; /*0054 0057*/ 574 u_int32_t iop_inbound_queue_port; /*0058 005B*/ 575 u_int32_t iop_outbound_queue_port; /*005C 005F*/ 576 u_int32_t inbound_free_list_index; /*0060 0063 inbound free list producer consumer index*/ 577 u_int32_t inbound_post_list_index; /*0064 0067 inbound post list producer consumer index*/ 578 u_int32_t outbound_free_list_index; /*0068 006B outbound free list producer consumer index*/ 579 u_int32_t outbound_post_list_index; /*006C 006F outbound post list producer consumer index*/ 580 u_int32_t inbound_doorbell_clear; /*0070 0073*/ 581 u_int32_t i2o_message_unit_control; /*0074 0077*/ 582 u_int32_t last_used_message_source_address_low; /*0078 007B*/ 583 u_int32_t last_used_message_source_address_high; /*007C 007F*/ 584 u_int32_t pull_mode_data_byte_count[4]; /*0080 008F pull mode data byte count0..count7*/ 585 u_int32_t message_dest_address_index; /*0090 0093*/ 586 u_int32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/ 587 u_int32_t utility_A_int_counter_timer; /*0098 009B*/ 588 u_int32_t outbound_doorbell; /*009C 009F*/ 589 u_int32_t outbound_doorbell_clear; /*00A0 00A3*/ 590 u_int32_t message_source_address_index; /*00A4 00A7 message accelerator source address consumer producer index*/ 591 u_int32_t message_done_queue_index; /*00A8 00AB message accelerator completion queue consumer producer index*/ 592 u_int32_t reserved0; /*00AC 00AF*/ 593 u_int32_t inbound_msgaddr0; /*00B0 00B3 scratchpad0*/ 594 u_int32_t inbound_msgaddr1; /*00B4 00B7 scratchpad1*/ 595 u_int32_t outbound_msgaddr0; /*00B8 00BB scratchpad2*/ 596 u_int32_t outbound_msgaddr1; /*00BC 00BF scratchpad3*/ 597 u_int32_t inbound_queueport_low; /*00C0 00C3 port64 host inbound queue port low*/ 598 u_int32_t inbound_queueport_high; /*00C4 00C7 port64 host inbound queue port high*/ 599 u_int32_t outbound_queueport_low; /*00C8 00CB port64 host outbound queue port low*/ 600 u_int32_t outbound_queueport_high; /*00CC 00CF port64 host outbound queue port high*/ 601 u_int32_t iop_inbound_queue_port_low; /*00D0 00D3*/ 602 u_int32_t iop_inbound_queue_port_high; /*00D4 00D7*/ 603 u_int32_t iop_outbound_queue_port_low; /*00D8 00DB*/ 604 u_int32_t iop_outbound_queue_port_high; /*00DC 00DF*/ 605 u_int32_t message_dest_queue_port_low; /*00E0 00E3 message accelerator destination queue port low*/ 606 u_int32_t message_dest_queue_port_high; /*00E4 00E7 message accelerator destination queue port high*/ 607 u_int32_t last_used_message_dest_address_low; /*00E8 00EB last used message accelerator destination address low*/ 608 u_int32_t last_used_message_dest_address_high; /*00EC 00EF last used message accelerator destination address high*/ 609 u_int32_t message_done_queue_base_address_low; /*00F0 00F3 message accelerator completion queue base address low*/ 610 u_int32_t message_done_queue_base_address_high; /*00F4 00F7 message accelerator completion queue base address high*/ 611 u_int32_t host_diagnostic; /*00F8 00FB*/ 612 u_int32_t write_sequence; /*00FC 00FF*/ 613 u_int32_t reserved1[34]; /*0100 0187*/ 614 u_int32_t reserved2[1950]; /*0188 1FFF*/ 615 u_int32_t message_wbuffer[32]; /*2000 207F*/ 616 u_int32_t reserved3[32]; /*2080 20FF*/ 617 u_int32_t message_rbuffer[32]; /*2100 217F*/ 618 u_int32_t reserved4[32]; /*2180 21FF*/ 619 u_int32_t msgcode_rwbuffer[256]; /*2200 23FF*/ 620 }; 621 /* 622 ********************************************************************* 623 ** 624 ********************************************************************* 625 */ 626 struct InBound_SRB { 627 uint32_t addressLow; //pointer to SRB block 628 uint32_t addressHigh; 629 uint32_t length; // in DWORDs 630 uint32_t reserved0; 631 }; 632 633 struct OutBound_SRB { 634 uint32_t addressLow; //pointer to SRB block 635 uint32_t addressHigh; 636 }; 637 638 struct HBD_MessageUnit { 639 uint32_t reserved0; 640 uint32_t chip_id; //0x0004 641 uint32_t cpu_mem_config; //0x0008 642 uint32_t reserved1[10]; //0x000C 643 uint32_t i2o_host_interrupt_mask; //0x0034 644 uint32_t reserved2[114]; //0x0038 645 uint32_t host_int_status; //0x0200 646 uint32_t host_int_enable; //0x0204 647 uint32_t reserved3[1]; //0x0208 648 uint32_t pcief0_int_enable; //0x020C 649 uint32_t reserved4[124]; //0x0210 650 uint32_t inbound_msgaddr0; //0x0400 651 uint32_t inbound_msgaddr1; //0x0404 652 uint32_t reserved5[6]; //0x0408 653 uint32_t outbound_msgaddr0; //0x0420 654 uint32_t outbound_msgaddr1; //0x0424 655 uint32_t reserved6[14]; //0x0428 656 uint32_t inbound_doorbell; //0x0460 657 uint32_t reserved7[7]; //0x0464 658 uint32_t outbound_doorbell; //0x0480 659 uint32_t outbound_doorbell_enable; //0x0484 660 uint32_t reserved8[734]; //0x0488 661 uint32_t inboundlist_base_low; //0x1000 662 uint32_t inboundlist_base_high; //0x1004 663 uint32_t reserved9[4]; //0x1008 664 uint32_t inboundlist_write_pointer; //0x1018 665 uint32_t inboundlist_read_pointer; //0x101C 666 uint32_t reserved10[16]; //0x1020 667 uint32_t outboundlist_base_low; //0x1060 668 uint32_t outboundlist_base_high; //0x1064 669 uint32_t reserved11; //0x1068 670 uint32_t outboundlist_copy_pointer; //0x106C 671 uint32_t outboundlist_read_pointer; //0x1070 0x1072 672 uint32_t reserved12[5]; //0x1074 673 uint32_t outboundlist_interrupt_cause; //0x1088 674 uint32_t outboundlist_interrupt_enable; //0x108C 675 uint32_t reserved13[988]; //0x1090 676 uint32_t message_wbuffer[32]; //0x2000 677 uint32_t reserved14[32]; //0x2080 678 uint32_t message_rbuffer[32]; //0x2100 679 uint32_t reserved15[32]; //0x2180 680 uint32_t msgcode_rwbuffer[256]; //0x2200 681 }; 682 683 struct HBD_MessageUnit0 { 684 struct InBound_SRB post_qbuffer[ARCMSR_MAX_HBD_POSTQUEUE]; 685 struct OutBound_SRB done_qbuffer[ARCMSR_MAX_HBD_POSTQUEUE+1]; 686 uint16_t postq_index; 687 uint16_t doneq_index; 688 struct HBD_MessageUnit *phbdmu; 689 }; 690 691 /* 692 ********************************************************************* 693 ** 694 ********************************************************************* 695 */ 696 struct MessageUnit_UNION 697 { 698 union { 699 struct HBA_MessageUnit hbamu; 700 struct HBB_MessageUnit hbbmu; 701 struct HBC_MessageUnit hbcmu; 702 struct HBD_MessageUnit0 hbdmu; 703 } muu; 704 }; 705 /* 706 ************************************************************* 707 ** structure for holding DMA address data 708 ************************************************************* 709 */ 710 #define IS_SG64_ADDR 0x01000000 /* bit24 */ 711 /* 712 ************************************************************************************************ 713 ** ARECA FIRMWARE SPEC 714 ************************************************************************************************ 715 ** Usage of IOP331 adapter 716 ** (All In/Out is in IOP331's view) 717 ** 1. Message 0 --> InitThread message and retrun code 718 ** 2. Doorbell is used for RS-232 emulation 719 ** inDoorBell : bit0 -- data in ready (DRIVER DATA WRITE OK) 720 ** bit1 -- data out has been read (DRIVER DATA READ OK) 721 ** outDooeBell: bit0 -- data out ready (IOP331 DATA WRITE OK) 722 ** bit1 -- data in has been read (IOP331 DATA READ OK) 723 ** 3. Index Memory Usage 724 ** offset 0xf00 : for RS232 out (request buffer) 725 ** offset 0xe00 : for RS232 in (scratch buffer) 726 ** offset 0xa00 : for inbound message code msgcode_rwbuffer (driver send to IOP331) 727 ** offset 0xa00 : for outbound message code msgcode_rwbuffer (IOP331 send to driver) 728 ** 4. RS-232 emulation 729 ** Currently 128 byte buffer is used 730 ** 1st u_int32_t : Data length (1--124) 731 ** Byte 4--127 : Max 124 bytes of data 732 ** 5. PostQ 733 ** All SCSI Command must be sent through postQ: 734 ** (inbound queue port) Request frame must be 32 bytes aligned 735 ** # bit27--bit31 => flag for post ccb 736 ** # bit0--bit26 => real address (bit27--bit31) of post arcmsr_cdb 737 ** bit31 : 0 : 256 bytes frame 738 ** 1 : 512 bytes frame 739 ** bit30 : 0 : normal request 740 ** 1 : BIOS request 741 ** bit29 : reserved 742 ** bit28 : reserved 743 ** bit27 : reserved 744 ** ------------------------------------------------------------------------------- 745 ** (outbount queue port) Request reply 746 ** # bit27--bit31 => flag for reply 747 ** # bit0--bit26 => real address (bit27--bit31) of reply arcmsr_cdb 748 ** bit31 : must be 0 (for this type of reply) 749 ** bit30 : reserved for BIOS handshake 750 ** bit29 : reserved 751 ** bit28 : 0 : no error, ignore AdapStatus/DevStatus/SenseData 752 ** 1 : Error, error code in AdapStatus/DevStatus/SenseData 753 ** bit27 : reserved 754 ** 6. BIOS request 755 ** All BIOS request is the same with request from PostQ 756 ** Except : 757 ** Request frame is sent from configuration space 758 ** offset: 0x78 : Request Frame (bit30 == 1) 759 ** offset: 0x18 : writeonly to generate IRQ to IOP331 760 ** Completion of request: 761 ** (bit30 == 0, bit28==err flag) 762 ** 7. Definition of SGL entry (structure) 763 ** 8. Message1 Out - Diag Status Code (????) 764 ** 9. Message0 message code : 765 ** 0x00 : NOP 766 ** 0x01 : Get Config ->offset 0xa00 :for outbound message code msgcode_rwbuffer (IOP331 send to driver) 767 ** Signature 0x87974060(4) 768 ** Request len 0x00000200(4) 769 ** numbers of queue 0x00000100(4) 770 ** SDRAM Size 0x00000100(4)-->256 MB 771 ** IDE Channels 0x00000008(4) 772 ** vendor 40 bytes char 773 ** model 8 bytes char 774 ** FirmVer 16 bytes char 775 ** Device Map 16 bytes char 776 ** 777 ** FirmwareVersion DWORD <== Added for checking of new firmware capability 778 ** 0x02 : Set Config ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver send to IOP331) 779 ** Signature 0x87974063(4) 780 ** UPPER32 of Request Frame (4)-->Driver Only 781 ** 0x03 : Reset (Abort all queued Command) 782 ** 0x04 : Stop Background Activity 783 ** 0x05 : Flush Cache 784 ** 0x06 : Start Background Activity (re-start if background is halted) 785 ** 0x07 : Check If Host Command Pending (Novell May Need This Function) 786 ** 0x08 : Set controller time ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver to IOP331) 787 ** byte 0 : 0xaa <-- signature 788 ** byte 1 : 0x55 <-- signature 789 ** byte 2 : year (04) 790 ** byte 3 : month (1..12) 791 ** byte 4 : date (1..31) 792 ** byte 5 : hour (0..23) 793 ** byte 6 : minute (0..59) 794 ** byte 7 : second (0..59) 795 ** ********************************************************************************* 796 ** Porting Of LSI2108/2116 Based PCIE SAS/6G host raid adapter 797 ** ==> Difference from IOP348 798 ** <1> Message Register 0,1 (the same usage) Init Thread message and retrun code 799 ** Inbound Message 0 (inbound_msgaddr0) : at offset 0xB0 (Scratchpad0) for inbound message code msgcode_rwbuffer (driver send to IOP) 800 ** Inbound Message 1 (inbound_msgaddr1) : at offset 0xB4 (Scratchpad1) Out.... Diag Status Code 801 ** Outbound Message 0 (outbound_msgaddr0): at offset 0xB8 (Scratchpad3) Out.... Diag Status Code 802 ** Outbound Message 1 (outbound_msgaddr1): at offset 0xBC (Scratchpad2) for outbound message code msgcode_rwbuffer (IOP send to driver) 803 ** <A> use doorbell to generate interrupt 804 ** 805 ** inbound doorbell: bit3 -- inbound message 0 ready (driver to iop) 806 ** outbound doorbell: bit3 -- outbound message 0 ready (iop to driver) 807 ** 808 ** a. Message1: Out - Diag Status Code (????) 809 ** 810 ** b. Message0: message code 811 ** 0x00 : NOP 812 ** 0x01 : Get Config ->offset 0xB8 :for outbound message code msgcode_rwbuffer (IOP send to driver) 813 ** Signature 0x87974060(4) 814 ** Request len 0x00000200(4) 815 ** numbers of queue 0x00000100(4) 816 ** SDRAM Size 0x00000100(4)-->256 MB 817 ** IDE Channels 0x00000008(4) 818 ** vendor 40 bytes char 819 ** model 8 bytes char 820 ** FirmVer 16 bytes char 821 ** Device Map 16 bytes char 822 ** cfgVersion ULONG <== Added for checking of new firmware capability 823 ** 0x02 : Set Config ->offset 0xB0 :for inbound message code msgcode_rwbuffer (driver send to IOP) 824 ** Signature 0x87974063(4) 825 ** UPPER32 of Request Frame (4)-->Driver Only 826 ** 0x03 : Reset (Abort all queued Command) 827 ** 0x04 : Stop Background Activity 828 ** 0x05 : Flush Cache 829 ** 0x06 : Start Background Activity (re-start if background is halted) 830 ** 0x07 : Check If Host Command Pending (Novell May Need This Function) 831 ** 0x08 : Set controller time ->offset 0xB0 : for inbound message code msgcode_rwbuffer (driver to IOP) 832 ** byte 0 : 0xaa <-- signature 833 ** byte 1 : 0x55 <-- signature 834 ** byte 2 : year (04) 835 ** byte 3 : month (1..12) 836 ** byte 4 : date (1..31) 837 ** byte 5 : hour (0..23) 838 ** byte 6 : minute (0..59) 839 ** byte 7 : second (0..59) 840 ** 841 ** <2> Doorbell Register is used for RS-232 emulation 842 ** <A> different clear register 843 ** <B> different bit0 definition (bit0 is reserved) 844 ** 845 ** inbound doorbell : at offset 0x20 846 ** inbound doorbell clear : at offset 0x70 847 ** 848 ** inbound doorbell : bit0 -- reserved 849 ** bit1 -- data in ready (DRIVER DATA WRITE OK) 850 ** bit2 -- data out has been read (DRIVER DATA READ OK) 851 ** bit3 -- inbound message 0 ready 852 ** bit4 -- more than 12 request completed in a time 853 ** 854 ** outbound doorbell : at offset 0x9C 855 ** outbound doorbell clear : at offset 0xA0 856 ** 857 ** outbound doorbell : bit0 -- reserved 858 ** bit1 -- data out ready (IOP DATA WRITE OK) 859 ** bit2 -- data in has been read (IOP DATA READ OK) 860 ** bit3 -- outbound message 0 ready 861 ** 862 ** <3> Index Memory Usage (Buffer Area) 863 ** COMPORT_IN at 0x2000: message_wbuffer -- 128 bytes (to be sent to ROC) : for RS232 in (scratch buffer) 864 ** COMPORT_OUT at 0x2100: message_rbuffer -- 128 bytes (to be sent to host): for RS232 out (request buffer) 865 ** BIOS_CFG_AREA at 0x2200: msgcode_rwbuffer -- 1024 bytes for outbound message code msgcode_rwbuffer (IOP send to driver) 866 ** BIOS_CFG_AREA at 0x2200: msgcode_rwbuffer -- 1024 bytes for inbound message code msgcode_rwbuffer (driver send to IOP) 867 ** 868 ** <4> PostQ (Command Post Address) 869 ** All SCSI Command must be sent through postQ: 870 ** inbound queue port32 at offset 0x40 , 0x41, 0x42, 0x43 871 ** inbound queue port64 at offset 0xC0 (lower)/0xC4 (upper) 872 ** outbound queue port32 at offset 0x44 873 ** outbound queue port64 at offset 0xC8 (lower)/0xCC (upper) 874 ** <A> For 32bit queue, access low part is enough to send/receive request 875 ** i.e. write 0x40/0xC0, ROC will get the request with high part == 0, the 876 ** same for outbound queue port 877 ** <B> For 64bit queue, if 64bit instruction is supported, use 64bit instruction 878 ** to post inbound request in a single instruction, and use 64bit instruction 879 ** to retrieve outbound request in a single instruction. 880 ** If in 32bit environment, when sending inbound queue, write high part first 881 ** then write low part. For receiving outbound request, read high part first 882 ** then low part, to check queue empty, ONLY check high part to be 0xFFFFFFFF. 883 ** If high part is 0xFFFFFFFF, DO NOT read low part, this may corrupt the 884 ** consistency of the FIFO. Another way to check empty is to check status flag 885 ** at 0x30 bit3. 886 ** <C> Post Address IS NOT shifted (must be 16 bytes aligned) 887 ** For BIOS, 16bytes aligned is OK 888 ** For Driver, 32bytes alignment is recommended. 889 ** POST Command bit0 to bit3 is defined differently 890 ** ---------------------------- 891 ** bit0:1 for PULL mode (must be 1) 892 ** ---------------------------- 893 ** bit3/2/1: for arcmsr cdb size (arccdbsize) 894 ** 000: <= 0x0080 (128) 895 ** 001: <= 0x0100 (256) 896 ** 010: <= 0x0180 (384) 897 ** 011: <= 0x0200 (512) 898 ** 100: <= 0x0280 (640) 899 ** 101: <= 0x0300 (768) 900 ** 110: <= 0x0300 (reserved) 901 ** 111: <= 0x0300 (reserved) 902 ** ----------------------------- 903 ** if len > 0x300 the len always set as 0x300 904 ** ----------------------------- 905 ** post addr = addr | ((len-1) >> 6) | 1 906 ** ----------------------------- 907 ** page length in command buffer still required, 908 ** 909 ** if page length > 3, 910 ** firmware will assume more request data need to be retrieved 911 ** 912 ** <D> Outbound Posting 913 ** bit0:0 , no error, 1 with error, refer to status buffer 914 ** bit1:0 , reserved (will be 0) 915 ** bit2:0 , reserved (will be 0) 916 ** bit3:0 , reserved (will be 0) 917 ** bit63-4: Completed command address 918 ** 919 ** <E> BIOS support, no special support is required. 920 ** LSI2108 support I/O register 921 ** All driver functionality is supported through I/O address 922 ** 923 ************************************************************************************************ 924 */ 925 /* 926 ********************************** 927 ** 928 ********************************** 929 */ 930 /* size 8 bytes */ 931 /* 32bit Scatter-Gather list */ 932 struct SG32ENTRY { /* length bit 24 == 0 */ 933 u_int32_t length; /* high 8 bit == flag,low 24 bit == length */ 934 u_int32_t address; 935 }; 936 /* size 12 bytes */ 937 /* 64bit Scatter-Gather list */ 938 struct SG64ENTRY { /* length bit 24 == 1 */ 939 u_int32_t length; /* high 8 bit == flag,low 24 bit == length */ 940 u_int32_t address; 941 u_int32_t addresshigh; 942 }; 943 struct SGENTRY_UNION { 944 union { 945 struct SG32ENTRY sg32entry; /* 30h Scatter gather address */ 946 struct SG64ENTRY sg64entry; /* 30h */ 947 }u; 948 }; 949 /* 950 ********************************** 951 ** 952 ********************************** 953 */ 954 struct QBUFFER { 955 u_int32_t data_len; 956 u_int8_t data[124]; 957 }; 958 /* 959 ********************************** 960 */ 961 typedef struct PHYS_ADDR64 { 962 u_int32_t phyadd_low; 963 u_int32_t phyadd_high; 964 }PHYSADDR64; 965 /* 966 ************************************************************************************************ 967 ** FIRMWARE INFO 968 ************************************************************************************************ 969 */ 970 #define ARCMSR_FW_MODEL_OFFSET 15 971 #define ARCMSR_FW_VERS_OFFSET 17 972 #define ARCMSR_FW_DEVMAP_OFFSET 21 973 #define ARCMSR_FW_CFGVER_OFFSET 25 974 975 struct FIRMWARE_INFO { 976 u_int32_t signature; /*0,00-03*/ 977 u_int32_t request_len; /*1,04-07*/ 978 u_int32_t numbers_queue; /*2,08-11*/ 979 u_int32_t sdram_size; /*3,12-15*/ 980 u_int32_t ide_channels; /*4,16-19*/ 981 char vendor[40]; /*5,20-59*/ 982 char model[8]; /*15,60-67*/ 983 char firmware_ver[16]; /*17,68-83*/ 984 char device_map[16]; /*21,84-99*/ 985 u_int32_t cfgVersion; /*25,100-103 Added for checking of new firmware capability*/ 986 char cfgSerial[16]; /*26,104-119*/ 987 u_int32_t cfgPicStatus; /*30,120-123*/ 988 }; 989 /* (A) For cfgVersion in FIRMWARE_INFO 990 ** if low BYTE (byte#0) >= 3 (version 3) 991 ** then byte#1 report the capability of the firmware can xfer in a single request 992 ** 993 ** byte#1 994 ** 0 256K 995 ** 1 512K 996 ** 2 1M 997 ** 3 2M 998 ** 4 4M 999 ** 5 8M 1000 ** 6 16M 1001 ** (B) Byte offset 7 (Reserved1) of CDB is changed to msgPages 1002 ** Driver support new xfer method need to set this field to indicate 1003 ** large CDB block in 0x100 unit (we use 0x100 byte as one page) 1004 ** e.g. If the length of CDB including MSG header and SGL is 0x1508 1005 ** driver need to set the msgPages to 0x16 1006 ** (C) REQ_LEN_512BYTE must be used also to indicate SRB length 1007 ** e.g. CDB len msgPages REQ_LEN_512BYTE flag 1008 ** <= 0x100 1 0 1009 ** <= 0x200 2 1 1010 ** <= 0x300 3 1 1011 ** <= 0x400 4 1 1012 ** . 1013 ** . 1014 */ 1015 1016 /* 1017 ************************************************************************************************ 1018 ** size 0x1F8 (504) 1019 ************************************************************************************************ 1020 */ 1021 struct ARCMSR_CDB { 1022 u_int8_t Bus; /* 00h should be 0 */ 1023 u_int8_t TargetID; /* 01h should be 0--15 */ 1024 u_int8_t LUN; /* 02h should be 0--7 */ 1025 u_int8_t Function; /* 03h should be 1 */ 1026 1027 u_int8_t CdbLength; /* 04h not used now */ 1028 u_int8_t sgcount; /* 05h */ 1029 u_int8_t Flags; /* 06h */ 1030 u_int8_t msgPages; /* 07h */ 1031 1032 u_int32_t Context; /* 08h Address of this request */ 1033 u_int32_t DataLength; /* 0ch not used now */ 1034 1035 u_int8_t Cdb[16]; /* 10h SCSI CDB */ 1036 /* 1037 ******************************************************** 1038 ** Device Status : the same from SCSI bus if error occur 1039 ** SCSI bus status codes. 1040 ******************************************************** 1041 */ 1042 u_int8_t DeviceStatus; /* 20h if error */ 1043 1044 u_int8_t SenseData[15]; /* 21h output */ 1045 1046 union { 1047 struct SG32ENTRY sg32entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h Scatter gather address */ 1048 struct SG64ENTRY sg64entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h */ 1049 } u; 1050 }; 1051 /* CDB flag */ 1052 #define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01 /* bit 0: 0(256) / 1(512) bytes */ 1053 #define ARCMSR_CDB_FLAG_BIOS 0x02 /* bit 1: 0(from driver) / 1(from BIOS) */ 1054 #define ARCMSR_CDB_FLAG_WRITE 0x04 /* bit 2: 0(Data in) / 1(Data out) */ 1055 #define ARCMSR_CDB_FLAG_SIMPLEQ 0x00 /* bit 4/3 ,00 : simple Q,01 : head of Q,10 : ordered Q */ 1056 #define ARCMSR_CDB_FLAG_HEADQ 0x08 1057 #define ARCMSR_CDB_FLAG_ORDEREDQ 0x10 1058 /* scsi status */ 1059 #define SCSISTAT_GOOD 0x00 1060 #define SCSISTAT_CHECK_CONDITION 0x02 1061 #define SCSISTAT_CONDITION_MET 0x04 1062 #define SCSISTAT_BUSY 0x08 1063 #define SCSISTAT_INTERMEDIATE 0x10 1064 #define SCSISTAT_INTERMEDIATE_COND_MET 0x14 1065 #define SCSISTAT_RESERVATION_CONFLICT 0x18 1066 #define SCSISTAT_COMMAND_TERMINATED 0x22 1067 #define SCSISTAT_QUEUE_FULL 0x28 1068 /* DeviceStatus */ 1069 #define ARCMSR_DEV_SELECT_TIMEOUT 0xF0 1070 #define ARCMSR_DEV_ABORTED 0xF1 1071 #define ARCMSR_DEV_INIT_FAIL 0xF2 1072 /* 1073 ********************************************************************* 1074 ** Command Control Block (SrbExtension) 1075 ** SRB must be not cross page boundary,and the order from offset 0 1076 ** structure describing an ATA disk request 1077 ** this SRB length must be 32 bytes boundary 1078 ********************************************************************* 1079 */ 1080 struct CommandControlBlock { 1081 struct ARCMSR_CDB arcmsr_cdb; /* 0 -503 (size of CDB=504): arcmsr messenger scsi command descriptor size 504 bytes */ 1082 u_int32_t cdb_phyaddr_low; /* 504-507 */ 1083 u_int32_t arc_cdb_size; /* 508-511 */ 1084 /* ======================512+32 bytes============================ */ 1085 union ccb *pccb; /* 512-515 516-519 pointer of freebsd scsi command */ 1086 struct AdapterControlBlock *acb; /* 520-523 524-527 */ 1087 bus_dmamap_t dm_segs_dmamap; /* 528-531 532-535 */ 1088 u_int16_t srb_flags; /* 536-537 */ 1089 u_int16_t srb_state; /* 538-539 */ 1090 u_int32_t cdb_phyaddr_high; /* 540-543 */ 1091 struct callout ccb_callout; 1092 /* ========================================================== */ 1093 }; 1094 /* srb_flags */ 1095 #define SRB_FLAG_READ 0x0000 1096 #define SRB_FLAG_WRITE 0x0001 1097 #define SRB_FLAG_ERROR 0x0002 1098 #define SRB_FLAG_FLUSHCACHE 0x0004 1099 #define SRB_FLAG_MASTER_ABORTED 0x0008 1100 #define SRB_FLAG_DMAVALID 0x0010 1101 #define SRB_FLAG_DMACONSISTENT 0x0020 1102 #define SRB_FLAG_DMAWRITE 0x0040 1103 #define SRB_FLAG_PKTBIND 0x0080 1104 #define SRB_FLAG_TIMER_START 0x0080 1105 /* srb_state */ 1106 #define ARCMSR_SRB_DONE 0x0000 1107 #define ARCMSR_SRB_UNBUILD 0x0000 1108 #define ARCMSR_SRB_TIMEOUT 0x1111 1109 #define ARCMSR_SRB_RETRY 0x2222 1110 #define ARCMSR_SRB_START 0x55AA 1111 #define ARCMSR_SRB_PENDING 0xAA55 1112 #define ARCMSR_SRB_RESET 0xA5A5 1113 #define ARCMSR_SRB_ABORTED 0x5A5A 1114 #define ARCMSR_SRB_ILLEGAL 0xFFFF 1115 1116 #define SRB_SIZE ((sizeof(struct CommandControlBlock)+0x1f) & 0xffe0) 1117 #define ARCMSR_SRBS_POOL_SIZE (SRB_SIZE * ARCMSR_MAX_FREESRB_NUM) 1118 1119 /* 1120 ********************************************************************* 1121 ** Adapter Control Block 1122 ********************************************************************* 1123 */ 1124 #define ACB_ADAPTER_TYPE_A 0x00000001 /* hba I IOP */ 1125 #define ACB_ADAPTER_TYPE_B 0x00000002 /* hbb M IOP */ 1126 #define ACB_ADAPTER_TYPE_C 0x00000004 /* hbc L IOP */ 1127 #define ACB_ADAPTER_TYPE_D 0x00000008 /* hbd M IOP */ 1128 1129 struct AdapterControlBlock { 1130 u_int32_t adapter_type; /* adapter A,B..... */ 1131 1132 bus_space_tag_t btag[2]; 1133 bus_space_handle_t bhandle[2]; 1134 bus_dma_tag_t parent_dmat; 1135 bus_dma_tag_t dm_segs_dmat; /* dmat for buffer I/O */ 1136 bus_dma_tag_t srb_dmat; /* dmat for freesrb */ 1137 bus_dmamap_t srb_dmamap; 1138 device_t pci_dev; 1139 #if __FreeBSD_version < 503000 1140 dev_t ioctl_dev; 1141 #else 1142 struct cdev *ioctl_dev; 1143 #endif 1144 int pci_unit; 1145 1146 struct resource *sys_res_arcmsr[2]; 1147 struct resource *irqres; 1148 void *ih; /* interrupt handle */ 1149 1150 /* Hooks into the CAM XPT */ 1151 struct cam_sim *psim; 1152 struct cam_path *ppath; 1153 u_int8_t *uncacheptr; 1154 unsigned long vir2phy_offset; 1155 union { 1156 unsigned long phyaddr; 1157 struct { 1158 u_int32_t phyadd_low; 1159 u_int32_t phyadd_high; 1160 }B; 1161 }srb_phyaddr; 1162 // unsigned long srb_phyaddr; 1163 /* Offset is used in making arc cdb physical to virtual calculations */ 1164 u_int32_t outbound_int_enable; 1165 1166 struct MessageUnit_UNION *pmu; /* message unit ATU inbound base address0 */ 1167 1168 u_int8_t adapter_index; 1169 u_int8_t irq; 1170 u_int16_t acb_flags; 1171 1172 struct CommandControlBlock *psrb_pool[ARCMSR_MAX_FREESRB_NUM]; /* serial srb pointer array */ 1173 struct CommandControlBlock *srbworkingQ[ARCMSR_MAX_FREESRB_NUM]; /* working srb pointer array */ 1174 int32_t workingsrb_doneindex; /* done srb array index */ 1175 int32_t workingsrb_startindex; /* start srb array index */ 1176 int32_t srboutstandingcount; 1177 1178 u_int8_t rqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for read from 80331 */ 1179 u_int32_t rqbuf_firstindex; /* first of read buffer */ 1180 u_int32_t rqbuf_lastindex; /* last of read buffer */ 1181 1182 u_int8_t wqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for write to 80331 */ 1183 u_int32_t wqbuf_firstindex; /* first of write buffer */ 1184 u_int32_t wqbuf_lastindex; /* last of write buffer */ 1185 1186 arcmsr_lock_t isr_lock; 1187 arcmsr_lock_t srb_lock; 1188 arcmsr_lock_t postDone_lock; 1189 arcmsr_lock_t qbuffer_lock; 1190 1191 u_int8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN]; /* id0 ..... id15,lun0...lun7 */ 1192 u_int32_t num_resets; 1193 u_int32_t num_aborts; 1194 u_int32_t firm_request_len; /*1,04-07*/ 1195 u_int32_t firm_numbers_queue; /*2,08-11*/ 1196 u_int32_t firm_sdram_size; /*3,12-15*/ 1197 u_int32_t firm_ide_channels; /*4,16-19*/ 1198 u_int32_t firm_cfg_version; 1199 char firm_model[12]; /*15,60-67*/ 1200 char firm_version[20]; /*17,68-83*/ 1201 char device_map[20]; /*21,84-99 */ 1202 struct callout devmap_callout; 1203 u_int32_t pktRequestCount; 1204 u_int32_t pktReturnCount; 1205 u_int32_t vendor_device_id; 1206 u_int32_t adapter_bus_speed; 1207 u_int32_t maxOutstanding; 1208 u_int16_t sub_device_id; 1209 };/* HW_DEVICE_EXTENSION */ 1210 /* acb_flags */ 1211 #define ACB_F_SCSISTOPADAPTER 0x0001 1212 #define ACB_F_MSG_STOP_BGRB 0x0002 /* stop RAID background rebuild */ 1213 #define ACB_F_MSG_START_BGRB 0x0004 /* stop RAID background rebuild */ 1214 #define ACB_F_IOPDATA_OVERFLOW 0x0008 /* iop ioctl data rqbuffer overflow */ 1215 #define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010 /* ioctl clear wqbuffer */ 1216 #define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020 /* ioctl clear rqbuffer */ 1217 #define ACB_F_MESSAGE_WQBUFFER_READ 0x0040 1218 #define ACB_F_BUS_RESET 0x0080 1219 #define ACB_F_IOP_INITED 0x0100 /* iop init */ 1220 #define ACB_F_MAPFREESRB_FAILD 0x0200 /* arcmsr_map_freesrb faild */ 1221 #define ACB_F_CAM_DEV_QFRZN 0x0400 1222 #define ACB_F_BUS_HANG_ON 0x0800 /* need hardware reset bus */ 1223 #define ACB_F_SRB_FUNCTION_POWER 0x1000 1224 /* devstate */ 1225 #define ARECA_RAID_GONE 0x55 1226 #define ARECA_RAID_GOOD 0xaa 1227 /* adapter_bus_speed */ 1228 #define ACB_BUS_SPEED_3G 0 1229 #define ACB_BUS_SPEED_6G 1 1230 #define ACB_BUS_SPEED_12G 2 1231 /* 1232 ************************************************************* 1233 ************************************************************* 1234 */ 1235 struct SENSE_DATA { 1236 u_int8_t ErrorCode:7; 1237 u_int8_t Valid:1; 1238 u_int8_t SegmentNumber; 1239 u_int8_t SenseKey:4; 1240 u_int8_t Reserved:1; 1241 u_int8_t IncorrectLength:1; 1242 u_int8_t EndOfMedia:1; 1243 u_int8_t FileMark:1; 1244 u_int8_t Information[4]; 1245 u_int8_t AdditionalSenseLength; 1246 u_int8_t CommandSpecificInformation[4]; 1247 u_int8_t AdditionalSenseCode; 1248 u_int8_t AdditionalSenseCodeQualifier; 1249 u_int8_t FieldReplaceableUnitCode; 1250 u_int8_t SenseKeySpecific[3]; 1251 }; 1252 /* 1253 ********************************** 1254 ** Peripheral Device Type definitions 1255 ********************************** 1256 */ 1257 #define SCSI_DASD 0x00 /* Direct-access Device */ 1258 #define SCSI_SEQACESS 0x01 /* Sequential-access device */ 1259 #define SCSI_PRINTER 0x02 /* Printer device */ 1260 #define SCSI_PROCESSOR 0x03 /* Processor device */ 1261 #define SCSI_WRITEONCE 0x04 /* Write-once device */ 1262 #define SCSI_CDROM 0x05 /* CD-ROM device */ 1263 #define SCSI_SCANNER 0x06 /* Scanner device */ 1264 #define SCSI_OPTICAL 0x07 /* Optical memory device */ 1265 #define SCSI_MEDCHGR 0x08 /* Medium changer device */ 1266 #define SCSI_COMM 0x09 /* Communications device */ 1267 #define SCSI_NODEV 0x1F /* Unknown or no device type */ 1268 /* 1269 ************************************************************************************************************ 1270 ** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 1271 ** 80331 PCI-to-PCI Bridge 1272 ** PCI Configuration Space 1273 ** 1274 ** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 1275 ** Programming Interface 1276 ** ======================== 1277 ** Configuration Register Address Space Groupings and Ranges 1278 ** ============================================================= 1279 ** Register Group Configuration Offset 1280 ** ------------------------------------------------------------- 1281 ** Standard PCI Configuration 00-3Fh 1282 ** ------------------------------------------------------------- 1283 ** Device Specific Registers 40-A7h 1284 ** ------------------------------------------------------------- 1285 ** Reserved A8-CBh 1286 ** ------------------------------------------------------------- 1287 ** Enhanced Capability List CC-FFh 1288 ** ========================================================================================================== 1289 ** Standard PCI [Type 1] Configuration Space Address Map 1290 ** ********************************************************************************************************** 1291 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 1292 ** ---------------------------------------------------------------------------------------------------------- 1293 ** | Device ID | Vendor ID | 00h 1294 ** ---------------------------------------------------------------------------------------------------------- 1295 ** | Primary Status | Primary Command | 04h 1296 ** ---------------------------------------------------------------------------------------------------------- 1297 ** | Class Code | RevID | 08h 1298 ** ---------------------------------------------------------------------------------------------------------- 1299 ** | reserved | Header Type | Primary MLT | Primary CLS | 0Ch 1300 ** ---------------------------------------------------------------------------------------------------------- 1301 ** | Reserved | 10h 1302 ** ---------------------------------------------------------------------------------------------------------- 1303 ** | Reserved | 14h 1304 ** ---------------------------------------------------------------------------------------------------------- 1305 ** | Secondary MLT | Subordinate Bus Number | Secondary Bus Number | Primary Bus Number | 18h 1306 ** ---------------------------------------------------------------------------------------------------------- 1307 ** | Secondary Status | I/O Limit | I/O Base | 1Ch 1308 ** ---------------------------------------------------------------------------------------------------------- 1309 ** | Non-prefetchable Memory Limit Address | Non-prefetchable Memory Base Address | 20h 1310 ** ---------------------------------------------------------------------------------------------------------- 1311 ** | Prefetchable Memory Limit Address | Prefetchable Memory Base Address | 24h 1312 ** ---------------------------------------------------------------------------------------------------------- 1313 ** | Prefetchable Memory Base Address Upper 32 Bits | 28h 1314 ** ---------------------------------------------------------------------------------------------------------- 1315 ** | Prefetchable Memory Limit Address Upper 32 Bits | 2Ch 1316 ** ---------------------------------------------------------------------------------------------------------- 1317 ** | I/O Limit Upper 16 Bits | I/O Base Upper 16 | 30h 1318 ** ---------------------------------------------------------------------------------------------------------- 1319 ** | Reserved | Capabilities Pointer | 34h 1320 ** ---------------------------------------------------------------------------------------------------------- 1321 ** | Reserved | 38h 1322 ** ---------------------------------------------------------------------------------------------------------- 1323 ** | Bridge Control | Primary Interrupt Pin | Primary Interrupt Line | 3Ch 1324 **============================================================================================================= 1325 */ 1326 /* 1327 **============================================================================================================= 1328 ** 0x03-0x00 : 1329 ** Bit Default Description 1330 **31:16 0335h Device ID (DID): Indicates the unique device ID that is assigned to bridge by the PCI SIG. 1331 ** ID is unique per product speed as indicated. 1332 **15:00 8086h Vendor ID (VID): 16-bit field which indicates that Intel is the vendor. 1333 **============================================================================================================= 1334 */ 1335 #define ARCMSR_PCI2PCI_VENDORID_REG 0x00 /*word*/ 1336 #define ARCMSR_PCI2PCI_DEVICEID_REG 0x02 /*word*/ 1337 /* 1338 **============================================================================== 1339 ** 0x05-0x04 : command register 1340 ** Bit Default Description 1341 **15:11 00h Reserved 1342 ** 10 0 Interrupt Disable: Disables/Enables the generation of Interrupts on the primary bus. 1343 ** The bridge does not support interrupts. 1344 ** 09 0 FB2B Enable: Enables/Disables the generation of fast back to back 1345 ** transactions on the primary bus. 1346 ** The bridge does not generate fast back to back 1347 ** transactions on the primary bus. 1348 ** 08 0 SERR# Enable (SEE): Enables primary bus SERR# assertions. 1349 ** 0=The bridge does not assert P_SERR#. 1350 ** 1=The bridge may assert P_SERR#, subject to other programmable criteria. 1351 ** 07 0 Wait Cycle Control (WCC): Always returns 0bzero indicating 1352 ** that bridge does not perform address or data stepping, 1353 ** 06 0 Parity Error Response (PER): Controls bridge response to a detected primary bus parity error. 1354 ** 0=When a data parity error is detected bridge does not assert S_PERR#. 1355 ** Also bridge does not assert P_SERR# in response to 1356 ** a detected address or attribute parity error. 1357 ** 1=When a data parity error is detected bridge asserts S_PERR#. 1358 ** The bridge also asserts P_SERR# 1359 ** (when enabled globally via bit(8) of this register) 1360 ** in response to a detected address or attribute parity error. 1361 ** 05 0 VGA Palette Snoop Enable (VGA_PSE): Controls bridge response to VGA-compatible palette write transactions. 1362 ** VGA palette write transactions are I/O transactions 1363 ** whose address bits are: P_AD[9:0] equal to 3C6h, 3C8h or 3C9h 1364 ** P_AD[15:10] are not decoded (i.e. aliases are claimed), 1365 ** or are fully decoding 1366 ** (i.e., must be all 0's depending upon the VGA 1367 ** aliasing bit in the Bridge Control Register, offset 3Eh. 1368 ** P_AD[31:16] equal to 0000h 1369 ** 0=The bridge ignores VGA palette write transactions, 1370 ** unless decoded by the standard I/O address range window. 1371 ** 1=The bridge responds to VGA palette write transactions 1372 ** with medium DEVSEL# timing and forwards them to the secondary bus. 1373 ** 04 0 Memory Write and Invalidate Enable (MWIE): The bridge does not promote MW transactions to MWI transactions. 1374 ** MWI transactions targeting resources on the opposite side of the bridge, 1375 ** however, are forwarded as MWI transactions. 1376 ** 03 0 Special Cycle Enable (SCE): The bridge ignores special cycle transactions. 1377 ** This bit is read only and always returns 0 when read 1378 ** 02 0 Bus Master Enable (BME): Enables bridge to initiate memory and I/O transactions on the primary interface. 1379 ** Initiation of configuration transactions is not affected by the state of this bit. 1380 ** 0=The bridge does not initiate memory or I/O transactions on the primary interface. 1381 ** 1=The bridge is enabled to function as an initiator on the primary interface. 1382 ** 01 0 Memory Space Enable (MSE): Controls target response to memory transactions on the primary interface. 1383 ** 0=The bridge target response to memory transactions on the primary interface is disabled. 1384 ** 1=The bridge target response to memory transactions on the primary interface is enabled. 1385 ** 00 0 I/O Space Enable (IOSE): Controls target response to I/O transactions on the primary interface. 1386 ** 0=The bridge target response to I/O transactions on the primary interface is disabled. 1387 ** 1=The bridge target response to I/O transactions on the primary interface is enabled. 1388 **============================================================================== 1389 */ 1390 #define ARCMSR_PCI2PCI_PRIMARY_COMMAND_REG 0x04 /*word*/ 1391 #define PCI_DISABLE_INTERRUPT 0x0400 1392 /* 1393 **============================================================================== 1394 ** 0x07-0x06 : status register 1395 ** Bit Default Description 1396 ** 15 0 Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address, 1397 ** attribute or data parity error. 1398 ** This bit is set regardless of the state of the PER bit in the command register. 1399 ** 14 0 Signaled System Error: The bridge sets this bit to a 1b whenever it asserts SERR# on the primary bus. 1400 ** 13 0 Received Master Abort: The bridge sets this bit to a 1b when, 1401 ** acting as the initiator on the primary bus, 1402 ** its transaction (with the exception of special cycles) 1403 ** has been terminated with a Master Abort. 1404 ** 12 0 Received Target Abort: The bridge sets this bit to a 1b when, 1405 ** acting as the initiator on the primary bus, 1406 ** its transaction has been terminated with a Target Abort. 1407 ** 11 0 Signaled Target Abort: The bridge sets this bit to a 1b when it, 1408 ** as the target of a transaction, terminates it with a Target Abort. 1409 ** In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code. 1410 ** 10:09 01 DEVSEL# Timing: Indicates slowest response to a non-configuration command on the primary interface. 1411 ** Returns ��01b�� when read, indicating that bridge responds no slower than with medium timing. 1412 ** 08 0 Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true: 1413 ** The bridge is the current master on the primary bus 1414 ** S_PERR# is detected asserted or is asserted by bridge 1415 ** The Parity Error Response bit is set in the Command register 1416 ** 07 1 Fast Back to Back Capable: Returns a 1b when read indicating that bridge 1417 ** is able to respond to fast back to back transactions on its primary interface. 1418 ** 06 0 Reserved 1419 ** 05 1 66 MHz Capable Indication: Returns a 1b when read indicating that bridge primary interface is 66 MHz capable. 1420 ** 1 = 1421 ** 04 1 Capabilities List Enable: Returns 1b when read indicating that bridge supports PCI standard enhanced capabilities. 1422 ** Offset 34h (Capability Pointer register) 1423 ** provides the offset for the first entry 1424 ** in the linked list of enhanced capabilities. 1425 ** 03 0 Interrupt Status: Reflects the state of the interrupt in the device/function. 1426 ** The bridge does not support interrupts. 1427 ** 02:00 000 Reserved 1428 **============================================================================== 1429 */ 1430 #define ARCMSR_PCI2PCI_PRIMARY_STATUS_REG 0x06 /*word: 06,07 */ 1431 #define ARCMSR_ADAP_66MHZ 0x20 1432 /* 1433 **============================================================================== 1434 ** 0x08 : revision ID 1435 ** Bit Default Description 1436 ** 07:00 00000000 Revision ID (RID): '00h' indicating bridge A-0 stepping. 1437 **============================================================================== 1438 */ 1439 #define ARCMSR_PCI2PCI_REVISIONID_REG 0x08 /*byte*/ 1440 /* 1441 **============================================================================== 1442 ** 0x0b-0x09 : 0180_00 (class code 1,native pci mode ) 1443 ** Bit Default Description 1444 ** 23:16 06h Base Class Code (BCC): Indicates that this is a bridge device. 1445 ** 15:08 04h Sub Class Code (SCC): Indicates this is of type PCI-to-PCI bridge. 1446 ** 07:00 00h Programming Interface (PIF): Indicates that this is standard (non-subtractive) PCI-PCI bridge. 1447 **============================================================================== 1448 */ 1449 #define ARCMSR_PCI2PCI_CLASSCODE_REG 0x09 /*3bytes*/ 1450 /* 1451 **============================================================================== 1452 ** 0x0c : cache line size 1453 ** Bit Default Description 1454 ** 07:00 00h Cache Line Size (CLS): Designates the cache line size in 32-bit dword units. 1455 ** The contents of this register are factored into 1456 ** internal policy decisions associated with memory read prefetching, 1457 ** and the promotion of Memory Write transactions to MWI transactions. 1458 ** Valid cache line sizes are 8 and 16 dwords. 1459 ** When the cache line size is set to an invalid value, 1460 ** bridge behaves as though the cache line size was set to 00h. 1461 **============================================================================== 1462 */ 1463 #define ARCMSR_PCI2PCI_PRIMARY_CACHELINESIZE_REG 0x0C /*byte*/ 1464 /* 1465 **============================================================================== 1466 ** 0x0d : latency timer (number of pci clock 00-ff ) 1467 ** Bit Default Description 1468 ** Primary Latency Timer (PTV): 1469 ** 07:00 00h (Conventional PCI) Conventional PCI Mode: Primary bus Master latency timer. Indicates the number of PCI clock cycles, 1470 ** referenced from the assertion of FRAME# to the expiration of the timer, 1471 ** when bridge may continue as master of the current transaction. All bits are writable, 1472 ** resulting in a granularity of 1 PCI clock cycle. 1473 ** When the timer expires (i.e., equals 00h) 1474 ** bridge relinquishes the bus after the first data transfer 1475 ** when its PCI bus grant has been deasserted. 1476 ** or 40h (PCI-X) PCI-X Mode: Primary bus Master latency timer. 1477 ** Indicates the number of PCI clock cycles, 1478 ** referenced from the assertion of FRAME# to the expiration of the timer, 1479 ** when bridge may continue as master of the current transaction. 1480 ** All bits are writable, resulting in a granularity of 1 PCI clock cycle. 1481 ** When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB. 1482 ** (Except in the case where MLT expires within 3 data phases 1483 ** of an ADB.In this case bridge continues on 1484 ** until it reaches the next ADB before relinquishing the bus.) 1485 **============================================================================== 1486 */ 1487 #define ARCMSR_PCI2PCI_PRIMARY_LATENCYTIMER_REG 0x0D /*byte*/ 1488 /* 1489 **============================================================================== 1490 ** 0x0e : (header type,single function ) 1491 ** Bit Default Description 1492 ** 07 0 Multi-function device (MVD): 80331 is a single-function device. 1493 ** 06:00 01h Header Type (HTYPE): Defines the layout of addresses 10h through 3Fh in configuration space. 1494 ** Returns ��01h�� when read indicating 1495 ** that the register layout conforms to the standard PCI-to-PCI bridge layout. 1496 **============================================================================== 1497 */ 1498 #define ARCMSR_PCI2PCI_HEADERTYPE_REG 0x0E /*byte*/ 1499 /* 1500 **============================================================================== 1501 ** 0x0f : 1502 **============================================================================== 1503 */ 1504 /* 1505 **============================================================================== 1506 ** 0x13-0x10 : 1507 ** PCI CFG Base Address #0 (0x10) 1508 **============================================================================== 1509 */ 1510 /* 1511 **============================================================================== 1512 ** 0x17-0x14 : 1513 ** PCI CFG Base Address #1 (0x14) 1514 **============================================================================== 1515 */ 1516 /* 1517 **============================================================================== 1518 ** 0x1b-0x18 : 1519 ** PCI CFG Base Address #2 (0x18) 1520 **-----------------0x1A,0x19,0x18--Bus Number Register - BNR 1521 ** Bit Default Description 1522 ** 23:16 00h Subordinate Bus Number (SBBN): Indicates the highest PCI bus number below this bridge. 1523 ** Any Type 1 configuration cycle 1524 ** on the primary bus whose bus number is greater than the secondary bus number, 1525 ** and less than or equal to the subordinate bus number 1526 ** is forwarded unaltered as a Type 1 configuration cycle on the secondary PCI bus. 1527 ** 15:08 00h Secondary Bus Number (SCBN): Indicates the bus number of PCI to which the secondary interface is connected. 1528 ** Any Type 1 configuration cycle matching this bus number 1529 ** is translated to a Type 0 configuration cycle (or a Special Cycle) 1530 ** before being executed on bridge's secondary PCI bus. 1531 ** 07:00 00h Primary Bus Number (PBN): Indicates bridge primary bus number. 1532 ** Any Type 1 configuration cycle on the primary interface 1533 ** with a bus number that is less than the contents 1534 ** of this register field does not be claimed by bridge. 1535 **-----------------0x1B--Secondary Latency Timer Register - SLTR 1536 ** Bit Default Description 1537 ** Secondary Latency Timer (STV): 1538 ** 07:00 00h (Conventional PCI) Conventional PCI Mode: Secondary bus Master latency timer. 1539 ** Indicates the number of PCI clock cycles, 1540 ** referenced from the assertion of FRAME# to the expiration of the timer, 1541 ** when bridge may continue as master of the current transaction. All bits are writable, 1542 ** resulting in a granularity of 1 PCI clock cycle. 1543 ** When the timer expires (i.e., equals 00h) 1544 ** bridge relinquishes the bus after the first data transfer 1545 ** when its PCI bus grant has been deasserted. 1546 ** or 40h (PCI-X) PCI-X Mode: Secondary bus Master latency timer. 1547 ** Indicates the number of PCI clock cycles,referenced from the assertion of FRAME# 1548 ** to the expiration of the timer, 1549 ** when bridge may continue as master of the current transaction. All bits are writable, 1550 ** resulting in a granularity of 1 PCI clock cycle. 1551 ** When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB. 1552 ** (Except in the case where MLT expires within 3 data phases of an ADB. 1553 ** In this case bridge continues on until it reaches the next ADB 1554 ** before relinquishing the bus) 1555 **============================================================================== 1556 */ 1557 #define ARCMSR_PCI2PCI_PRIMARY_BUSNUMBER_REG 0x18 /*3byte 0x1A,0x19,0x18*/ 1558 #define ARCMSR_PCI2PCI_SECONDARY_BUSNUMBER_REG 0x19 /*byte*/ 1559 #define ARCMSR_PCI2PCI_SUBORDINATE_BUSNUMBER_REG 0x1A /*byte*/ 1560 #define ARCMSR_PCI2PCI_SECONDARY_LATENCYTIMER_REG 0x1B /*byte*/ 1561 /* 1562 **============================================================================== 1563 ** 0x1f-0x1c : 1564 ** PCI CFG Base Address #3 (0x1C) 1565 **-----------------0x1D,0x1C--I/O Base and Limit Register - IOBL 1566 ** Bit Default Description 1567 ** 15:12 0h I/O Limit Address Bits [15:12]: Defines the top address of an address range to 1568 ** determine when to forward I/O transactions from one interface to the other. 1569 ** These bits correspond to address lines 15:12 for 4KB alignment. 1570 ** Bits 11:0 are assumed to be FFFh. 1571 ** 11:08 1h I/O Limit Addressing Capability: This field is hard-wired to 1h, indicating support 32-bit I/O addressing. 1572 ** 07:04 0h I/O Base Address Bits [15:12]: Defines the bottom address of 1573 ** an address range to determine when to forward I/O transactions 1574 ** from one interface to the other. 1575 ** These bits correspond to address lines 15:12 for 4KB alignment. 1576 ** Bits 11:0 are assumed to be 000h. 1577 ** 03:00 1h I/O Base Addressing Capability: This is hard-wired to 1h, indicating support for 32-bit I/O addressing. 1578 **-----------------0x1F,0x1E--Secondary Status Register - SSR 1579 ** Bit Default Description 1580 ** 15 0b Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address, 1581 ** attribute or data parity error on its secondary interface. 1582 ** 14 0b Received System Error: The bridge sets this bit when it samples SERR# asserted on its secondary bus interface. 1583 ** 13 0b Received Master Abort: The bridge sets this bit to a 1b when, 1584 ** acting as the initiator on the secondary bus, 1585 ** it's transaction (with the exception of special cycles) 1586 ** has been terminated with a Master Abort. 1587 ** 12 0b Received Target Abort: The bridge sets this bit to a 1b when, 1588 ** acting as the initiator on the secondary bus, 1589 ** it's transaction has been terminated with a Target Abort. 1590 ** 11 0b Signaled Target Abort: The bridge sets this bit to a 1b when it, 1591 ** as the target of a transaction, terminates it with a Target Abort. 1592 ** In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code. 1593 ** 10:09 01b DEVSEL# Timing: Indicates slowest response to a non-configuration command on the secondary interface. 1594 ** Returns ��01b�� when read, indicating that bridge responds no slower than with medium timing. 1595 ** 08 0b Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true: 1596 ** The bridge is the current master on the secondary bus 1597 ** S_PERR# is detected asserted or is asserted by bridge 1598 ** The Parity Error Response bit is set in the Command register 1599 ** 07 1b Fast Back-to-Back Capable (FBC): Indicates that the secondary interface of bridge can receive fast back-to-back cycles. 1600 ** 06 0b Reserved 1601 ** 05 1b 66 MHz Capable (C66): Indicates the secondary interface of the bridge is 66 MHz capable. 1602 ** 1 = 1603 ** 04:00 00h Reserved 1604 **============================================================================== 1605 */ 1606 #define ARCMSR_PCI2PCI_IO_BASE_REG 0x1C /*byte*/ 1607 #define ARCMSR_PCI2PCI_IO_LIMIT_REG 0x1D /*byte*/ 1608 #define ARCMSR_PCI2PCI_SECONDARY_STATUS_REG 0x1E /*word: 0x1F,0x1E */ 1609 /* 1610 **============================================================================== 1611 ** 0x23-0x20 : 1612 ** PCI CFG Base Address #4 (0x20) 1613 **-----------------0x23,0x22,0x21,0x20--Memory Base and Limit Register - MBL 1614 ** Bit Default Description 1615 ** 31:20 000h Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine 1616 ** the upper 1MB aligned value (exclusive) of the range. 1617 ** The incoming address must be less than or equal to this value. 1618 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0] 1619 ** are assumed to be F FFFFh. 1620 ** 19:16 0h Reserved. 1621 ** 15:04 000h Memory Base: These 12 bits are compared with bits P_AD[31:20] 1622 ** of the incoming address to determine the lower 1MB 1623 ** aligned value (inclusive) of the range. 1624 ** The incoming address must be greater than or equal to this value. 1625 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0]) 1626 ** are assumed to be 0 0000h. 1627 ** 03:00 0h Reserved. 1628 **============================================================================== 1629 */ 1630 #define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_BASE_REG 0x20 /*word: 0x21,0x20 */ 1631 #define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_LIMIT_REG 0x22 /*word: 0x23,0x22 */ 1632 /* 1633 **============================================================================== 1634 ** 0x27-0x24 : 1635 ** PCI CFG Base Address #5 (0x24) 1636 **-----------------0x27,0x26,0x25,0x24--Prefetchable Memory Base and Limit Register - PMBL 1637 ** Bit Default Description 1638 ** 31:20 000h Prefetchable Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine 1639 ** the upper 1MB aligned value (exclusive) of the range. 1640 ** The incoming address must be less than or equal to this value. 1641 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0] 1642 ** are assumed to be F FFFFh. 1643 ** 19:16 1h 64-bit Indicator: Indicates that 64-bit addressing is supported. 1644 ** 15:04 000h Prefetchable Memory Base: These 12 bits are compared with bits P_AD[31:20] 1645 ** of the incoming address to determine the lower 1MB aligned value (inclusive) 1646 ** of the range. 1647 ** The incoming address must be greater than or equal to this value. 1648 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0]) 1649 ** are assumed to be 0 0000h. 1650 ** 03:00 1h 64-bit Indicator: Indicates that 64-bit addressing is supported. 1651 **============================================================================== 1652 */ 1653 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_REG 0x24 /*word: 0x25,0x24 */ 1654 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_REG 0x26 /*word: 0x27,0x26 */ 1655 /* 1656 **============================================================================== 1657 ** 0x2b-0x28 : 1658 ** Bit Default Description 1659 ** 31:00 00000000h Prefetchable Memory Base Upper Portion: All bits are read/writable 1660 ** bridge supports full 64-bit addressing. 1661 **============================================================================== 1662 */ 1663 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_UPPER32_REG 0x28 /*dword: 0x2b,0x2a,0x29,0x28 */ 1664 /* 1665 **============================================================================== 1666 ** 0x2f-0x2c : 1667 ** Bit Default Description 1668 ** 31:00 00000000h Prefetchable Memory Limit Upper Portion: All bits are read/writable 1669 ** bridge supports full 64-bit addressing. 1670 **============================================================================== 1671 */ 1672 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_UPPER32_REG 0x2C /*dword: 0x2f,0x2e,0x2d,0x2c */ 1673 /* 1674 **============================================================================== 1675 ** 0x33-0x30 : 1676 ** Bit Default Description 1677 ** 07:00 DCh Capabilities Pointer: Pointer to the first CAP ID entry in the capabilities list is at DCh in PCI configuration 1678 ** space. (Power Management Capability Registers) 1679 **============================================================================== 1680 */ 1681 #define ARCMSR_PCI2PCI_CAPABILITIES_POINTER_REG 0x34 /*byte*/ 1682 /* 1683 **============================================================================== 1684 ** 0x3b-0x35 : reserved 1685 **============================================================================== 1686 */ 1687 /* 1688 **============================================================================== 1689 ** 0x3d-0x3c : 1690 ** 1691 ** Bit Default Description 1692 ** 15:08 00h Interrupt Pin (PIN): Bridges do not support the generation of interrupts. 1693 ** 07:00 00h Interrupt Line (LINE): The bridge does not generate interrupts, so this is reserved as '00h'. 1694 **============================================================================== 1695 */ 1696 #define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_LINE_REG 0x3C /*byte*/ 1697 #define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_PIN_REG 0x3D /*byte*/ 1698 /* 1699 **============================================================================== 1700 ** 0x3f-0x3e : 1701 ** Bit Default Description 1702 ** 15:12 0h Reserved 1703 ** 11 0b Discard Timer SERR# Enable: Controls the generation of SERR# on the primary interface (P_SERR#) in response 1704 ** to a timer discard on either the primary or secondary interface. 1705 ** 0b=SERR# is not asserted. 1706 ** 1b=SERR# is asserted. 1707 ** 10 0b Discard Timer Status (DTS): This bit is set to a '1b' when either the primary or secondary discard timer expires. 1708 ** The delayed completion is then discarded. 1709 ** 09 0b Secondary Discard Timer (SDT): Sets the maximum number of PCI clock cycles 1710 ** that bridge waits for an initiator on the secondary bus 1711 ** to repeat a delayed transaction request. 1712 ** The counter starts when the delayed transaction completion is ready 1713 ** to be returned to the initiator. 1714 ** When the initiator has not repeated the transaction 1715 ** at least once before the counter expires,bridge 1716 ** discards the delayed transaction from its queues. 1717 ** 0b=The secondary master time-out counter is 2 15 PCI clock cycles. 1718 ** 1b=The secondary master time-out counter is 2 10 PCI clock cycles. 1719 ** 08 0b Primary Discard Timer (PDT): Sets the maximum number of PCI clock cycles 1720 ** that bridge waits for an initiator on the primary bus 1721 ** to repeat a delayed transaction request. 1722 ** The counter starts when the delayed transaction completion 1723 ** is ready to be returned to the initiator. 1724 ** When the initiator has not repeated the transaction 1725 ** at least once before the counter expires, 1726 ** bridge discards the delayed transaction from its queues. 1727 ** 0b=The primary master time-out counter is 2 15 PCI clock cycles. 1728 ** 1b=The primary master time-out counter is 2 10 PCI clock cycles. 1729 ** 07 0b Fast Back-to-Back Enable (FBE): The bridge does not initiate back to back transactions. 1730 ** 06 0b Secondary Bus Reset (SBR): 1731 ** When cleared to 0b: The bridge deasserts S_RST#, 1732 ** when it had been asserted by writing this bit to a 1b. 1733 ** When set to 1b: The bridge asserts S_RST#. 1734 ** 05 0b Master Abort Mode (MAM): Dictates bridge behavior on the initiator bus 1735 ** when a master abort termination occurs in response to 1736 ** a delayed transaction initiated by bridge on the target bus. 1737 ** 0b=The bridge asserts TRDY# in response to a non-locked delayed transaction, 1738 ** and returns FFFF FFFFh when a read. 1739 ** 1b=When the transaction had not yet been completed on the initiator bus 1740 ** (e.g.,delayed reads, or non-posted writes), 1741 ** then bridge returns a Target Abort in response to the original requester 1742 ** when it returns looking for its delayed completion on the initiator bus. 1743 ** When the transaction had completed on the initiator bus (e.g., a PMW), 1744 ** then bridge asserts P_SERR# (when enabled). 1745 ** For PCI-X transactions this bit is an enable for the assertion of P_SERR# due to a master abort 1746 ** while attempting to deliver a posted memory write on the destination bus. 1747 ** 04 0b VGA Alias Filter Enable: This bit dictates bridge behavior in conjunction with the VGA enable bit 1748 ** (also of this register), 1749 ** and the VGA Palette Snoop Enable bit (Command Register). 1750 ** When the VGA enable, or VGA Palette Snoop enable bits are on (i.e., 1b) 1751 ** the VGA Aliasing bit for the corresponding enabled functionality,: 1752 ** 0b=Ignores address bits AD[15:10] when decoding VGA I/O addresses. 1753 ** 1b=Ensures that address bits AD[15:10] equal 000000b when decoding VGA I/O addresses. 1754 ** When all VGA cycle forwarding is disabled, (i.e., VGA Enable bit =0b and VGA Palette Snoop bit =0b), 1755 ** then this bit has no impact on bridge behavior. 1756 ** 03 0b VGA Enable: Setting this bit enables address decoding 1757 ** and transaction forwarding of the following VGA transactions from the primary bus 1758 ** to the secondary bus: 1759 ** frame buffer memory addresses 000A0000h:000BFFFFh, 1760 ** VGA I/O addresses 3B0:3BBh and 3C0h:3DFh, where AD[31:16]=��0000h?** ?and AD[15:10] are either not decoded (i.e., don't cares), 1761 ** or must be ��000000b�� 1762 ** depending upon the state of the VGA Alias Filter Enable bit. (bit(4) of this register) 1763 ** I/O and Memory Enable bits must be set in the Command register 1764 ** to enable forwarding of VGA cycles. 1765 ** 02 0b ISA Enable: Setting this bit enables special handling 1766 ** for the forwarding of ISA I/O transactions that fall within the address range 1767 ** specified by the I/O Base and Limit registers, 1768 ** and are within the lowest 64Kbyte of the I/O address map 1769 ** (i.e., 0000 0000h - 0000 FFFFh). 1770 ** 0b=All I/O transactions that fall within the I/O Base 1771 ** and Limit registers' specified range are forwarded 1772 ** from primary to secondary unfiltered. 1773 ** 1b=Blocks the forwarding from primary to secondary 1774 ** of the top 768 bytes of each 1Kbyte alias. 1775 ** On the secondary the top 768 bytes of each 1K alias 1776 ** are inversely decoded and forwarded 1777 ** from secondary to primary. 1778 ** 01 0b SERR# Forward Enable: 0b=The bridge does not assert P_SERR# as a result of an S_SERR# assertion. 1779 ** 1b=The bridge asserts P_SERR# whenever S_SERR# is detected 1780 ** asserted provided the SERR# Enable bit is set (PCI Command Register bit(8)=1b). 1781 ** 00 0b Parity Error Response: This bit controls bridge response to a parity error 1782 ** that is detected on its secondary interface. 1783 ** 0b=When a data parity error is detected bridge does not assert S_PERR#. 1784 ** Also bridge does not assert P_SERR# in response to a detected address 1785 ** or attribute parity error. 1786 ** 1b=When a data parity error is detected bridge asserts S_PERR#. 1787 ** The bridge also asserts P_SERR# (when enabled globally via bit(8) 1788 ** of the Command register) 1789 ** in response to a detected address or attribute parity error. 1790 **============================================================================== 1791 */ 1792 #define ARCMSR_PCI2PCI_BRIDGE_CONTROL_REG 0x3E /*word*/ 1793 /* 1794 ************************************************************************** 1795 ** Device Specific Registers 40-A7h 1796 ************************************************************************** 1797 ** ---------------------------------------------------------------------------------------------------------- 1798 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 1799 ** ---------------------------------------------------------------------------------------------------------- 1800 ** | Bridge Control 0 | Arbiter Control/Status | Reserved | 40h 1801 ** ---------------------------------------------------------------------------------------------------------- 1802 ** | Bridge Control 2 | Bridge Control 1 | 44h 1803 ** ---------------------------------------------------------------------------------------------------------- 1804 ** | Reserved | Bridge Status | 48h 1805 ** ---------------------------------------------------------------------------------------------------------- 1806 ** | Reserved | 4Ch 1807 ** ---------------------------------------------------------------------------------------------------------- 1808 ** | Prefetch Policy | Multi-Transaction Timer | 50h 1809 ** ---------------------------------------------------------------------------------------------------------- 1810 ** | Reserved | Pre-boot Status | P_SERR# Assertion Control | 54h 1811 ** ---------------------------------------------------------------------------------------------------------- 1812 ** | Reserved | Reserved | Secondary Decode Enable | 58h 1813 ** ---------------------------------------------------------------------------------------------------------- 1814 ** | Reserved | Secondary IDSEL | 5Ch 1815 ** ---------------------------------------------------------------------------------------------------------- 1816 ** | Reserved | 5Ch 1817 ** ---------------------------------------------------------------------------------------------------------- 1818 ** | Reserved | 68h:CBh 1819 ** ---------------------------------------------------------------------------------------------------------- 1820 ************************************************************************** 1821 **============================================================================== 1822 ** 0x42-0x41: Secondary Arbiter Control/Status Register - SACSR 1823 ** Bit Default Description 1824 ** 15:12 1111b Grant Time-out Violator: This field indicates the agent that violated the Grant Time-out rule 1825 ** (PCI=16 clocks,PCI-X=6 clocks). 1826 ** Note that this field is only meaningful when: 1827 ** # Bit[11] of this register is set to 1b, 1828 ** indicating that a Grant Time-out violation had occurred. 1829 ** # bridge internal arbiter is enabled. 1830 ** Bits[15:12] Violating Agent (REQ#/GNT# pair number) 1831 ** 0000b REQ#/GNT#[0] 1832 ** 0001b REQ#/GNT#[1] 1833 ** 0010b REQ#/GNT#[2] 1834 ** 0011b REQ#/GNT#[3] 1835 ** 1111b Default Value (no violation detected) 1836 ** When bit[11] is cleared by software, this field reverts back to its default value. 1837 ** All other values are Reserved 1838 ** 11 0b Grant Time-out Occurred: When set to 1b, 1839 ** this indicates that a Grant Time-out error had occurred involving one of the secondary bus agents. 1840 ** Software clears this bit by writing a 1b to it. 1841 ** 10 0b Bus Parking Control: 0=During bus idle, bridge parks the bus on the last master to use the bus. 1842 ** 1=During bus idle, bridge parks the bus on itself. 1843 ** The bus grant is removed from the last master and internally asserted to bridge. 1844 ** 09:08 00b Reserved 1845 ** 07:00 0000 0000b Secondary Bus Arbiter Priority Configuration: The bridge secondary arbiter provides two rings of arbitration priority. 1846 ** Each bit of this field assigns its corresponding secondary 1847 ** bus master to either the high priority arbiter ring (1b) 1848 ** or to the low priority arbiter ring (0b). 1849 ** Bits [3:0] correspond to request inputs S_REQ#[3:0], respectively. 1850 ** Bit [6] corresponds to the bridge internal secondary bus request 1851 ** while Bit [7] corresponds to the SATU secondary bus request. 1852 ** Bits [5:4] are unused. 1853 ** 0b=Indicates that the master belongs to the low priority group. 1854 ** 1b=Indicates that the master belongs to the high priority group 1855 **================================================================================= 1856 ** 0x43: Bridge Control Register 0 - BCR0 1857 ** Bit Default Description 1858 ** 07 0b Fully Dynamic Queue Mode: 0=The number of Posted write transactions is limited to eight 1859 ** and the Posted Write data is limited to 4KB. 1860 ** 1=Operation in fully dynamic queue mode. The bridge enqueues up to 1861 ** 14 Posted Memory Write transactions and 8KB of posted write data. 1862 ** 06:03 0H Reserved. 1863 ** 02 0b Upstream Prefetch Disable: This bit disables bridge ability 1864 ** to perform upstream prefetch operations for Memory 1865 ** Read requests received on its secondary interface. 1866 ** This bit also controls the bridge's ability to generate advanced read commands 1867 ** when forwarding a Memory Read Block transaction request upstream from a PCI-X bus 1868 ** to a Conventional PCI bus. 1869 ** 0b=bridge treats all upstream Memory Read requests as though they target prefetchable memory. 1870 ** The use of Memory Read Line and Memory Read 1871 ** Multiple is enabled when forwarding a PCI-X Memory Read Block request 1872 ** to an upstream bus operating in Conventional PCI mode. 1873 ** 1b=bridge treats upstream PCI Memory Read requests as though 1874 ** they target non-prefetchable memory and forwards upstream PCI-X Memory 1875 ** Read Block commands as Memory Read 1876 ** when the primary bus is operating 1877 ** in Conventional PCI mode. 1878 ** NOTE: This bit does not affect bridge ability to perform read prefetching 1879 ** when the received command is Memory Read Line or Memory Read Multiple. 1880 **================================================================================= 1881 ** 0x45-0x44: Bridge Control Register 1 - BCR1 (Sheet 2 of 2) 1882 ** Bit Default Description 1883 ** 15:08 0000000b Reserved 1884 ** 07:06 00b Alias Command Mapping: This two bit field determines how bridge handles PCI-X ��Alias�� commands, 1885 ** specifically the Alias to Memory Read Block and Alias to Memory Write Block commands. 1886 ** The three options for handling these alias commands are to either pass it as is, 1887 ** re-map to the actual block memory read/write command encoding, or ignore 1888 ** the transaction forcing a Master Abort to occur on the Origination Bus. 1889 ** Bit (7:6) Handling of command 1890 ** 0 0 Re-map to Memory Read/Write Block before forwarding 1891 ** 0 1 Enqueue and forward the alias command code unaltered 1892 ** 1 0 Ignore the transaction, forcing Master Abort 1893 ** 1 1 Reserved 1894 ** 05 1b Watchdog Timers Disable: Disables or enables all 2 24 Watchdog Timers in both directions. 1895 ** The watchdog timers are used to detect prohibitively long latencies in the system. 1896 ** The watchdog timer expires when any Posted Memory Write (PMW), Delayed Request, 1897 ** or Split Requests (PCI-X mode) is not completed within 2 24 events 1898 ** (��events�� are defined as PCI Clocks when operating in PCI-X mode, 1899 ** and as the number of times being retried when operating in Conventional PCI mode) 1900 ** 0b=All 2 24 watchdog timers are enabled. 1901 ** 1b=All 2 24 watchdog timers are disabled and there is no limits to 1902 ** the number of attempts bridge makes when initiating a PMW, 1903 ** transacting a Delayed Transaction, or how long it waits for 1904 ** a split completion corresponding to one of its requests. 1905 ** 04 0b GRANT# time-out disable: This bit enables/disables the GNT# time-out mechanism. 1906 ** Grant time-out is 16 clocks for conventional PCI, and 6 clocks for PCI-X. 1907 ** 0b=The Secondary bus arbiter times out an agent 1908 ** that does not assert FRAME# within 16/6 clocks of receiving its grant, 1909 ** once the bus has gone idle. 1910 ** The time-out counter begins as soon as the bus goes idle with the new GNT# asserted. 1911 ** An infringing agent does not receive a subsequent GNT# 1912 ** until it de-asserts its REQ# for at least one clock cycle. 1913 ** 1b=GNT# time-out mechanism is disabled. 1914 ** 03 00b Reserved. 1915 ** 02 0b Secondary Discard Timer Disable: This bit enables/disables bridge secondary delayed transaction discard mechanism. 1916 ** The time out mechanism is used to ensure that initiators 1917 ** of delayed transactions return for their delayed completion data/status 1918 ** within a reasonable amount of time after it is available from bridge. 1919 ** 0b=The secondary master time-out counter is enabled 1920 ** and uses the value specified by the Secondary Discard Timer bit 1921 ** (see Bridge Control Register). 1922 ** 1b=The secondary master time-out counter is disabled. 1923 ** The bridge waits indefinitely for a secondary bus master 1924 ** to repeat a delayed transaction. 1925 ** 01 0b Primary Discard Timer Disable: This bit enables/disables bridge primary delayed transaction discard mechanism. 1926 ** The time out mechanism is used to ensure that initiators 1927 ** of delayed transactions return for their delayed completion data/status 1928 ** within a reasonable amount of time after it is available from bridge. 1929 ** 0b=The primary master time-out counter is enabled and uses the value specified 1930 ** by the Primary Discard Timer bit (see Bridge Control Register). 1931 ** 1b=The secondary master time-out counter is disabled. 1932 ** The bridge waits indefinitely for a secondary bus master 1933 ** to repeat a delayed transaction. 1934 ** 00 0b Reserved 1935 **================================================================================= 1936 ** 0x47-0x46: Bridge Control Register 2 - BCR2 1937 ** Bit Default Description 1938 ** 15:07 0000b Reserved. 1939 ** 06 0b Global Clock Out Disable (External Secondary Bus Clock Source Enable): 1940 ** This bit disables all of the secondary PCI clock outputs including 1941 ** the feedback clock S_CLKOUT. 1942 ** This means that the user is required to provide an S_CLKIN input source. 1943 ** 05:04 11 (66 MHz) Preserved. 1944 ** 01 (100 MHz) 1945 ** 00 (133 MHz) 1946 ** 03:00 Fh (100 MHz & 66 MHz) 1947 ** 7h (133 MHz) 1948 ** This 4 bit field provides individual enable/disable mask bits for each of bridge 1949 ** secondary PCI clock outputs. Some, or all secondary clock outputs (S_CLKO[3:0]) 1950 ** default to being enabled following the rising edge of P_RST#, depending on the 1951 ** frequency of the secondary bus clock: 1952 ** �E Designs with 100 MHz (or lower) Secondary PCI clock power up with 1953 ** all four S_CLKOs enabled by default. (SCLKO[3:0])�P 1954 ** �E Designs with 133 MHz Secondary PCI clock power up 1955 ** with the lower order 3 S_CLKOs enabled by default. 1956 ** (S_CLKO[2:0]) Only those SCLKs that power up enabled by can be connected 1957 ** to downstream device clock inputs. 1958 **================================================================================= 1959 ** 0x49-0x48: Bridge Status Register - BSR 1960 ** Bit Default Description 1961 ** 15 0b Upstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR# 1962 ** is conditionally asserted when the secondary discard timer expires. 1963 ** 14 0b Upstream Delayed/Split Read Watchdog Timer Expired: 1964 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# 1965 ** is conditionally asserted when bridge discards an upstream delayed read ** ** transaction request after 2 24 retries following the initial retry. 1966 ** PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 1967 ** when bridge discards an upstream split read request 1968 ** after waiting in excess of 2 24 clocks for the corresponding 1969 ** Split Completion to arrive. 1970 ** 13 0b Upstream Delayed/Split Write Watchdog Timer Expired: 1971 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# 1972 ** is conditionally asserted when bridge discards an upstream delayed write ** ** transaction request after 2 24 retries following the initial retry. 1973 ** PCI-X Mode: This bit is set to a 1b and P_SERR# 1974 ** is conditionally asserted when bridge discards an upstream split write request ** after waiting in excess of 2 24 clocks for the corresponding 1975 ** Split Completion to arrive. 1976 ** 12 0b Master Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR# 1977 ** is conditionally asserted when a Master Abort occurs as a result of an attempt, 1978 ** by bridge, to retire a PMW upstream. 1979 ** 11 0b Target Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR# 1980 ** is conditionally asserted when a Target Abort occurs as a result of an attempt, 1981 ** by bridge, to retire a PMW upstream. 1982 ** 10 0b Upstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR# 1983 ** is conditionally asserted when bridge discards an upstream PMW transaction 1984 ** after receiving 2 24 target retries from the primary bus target 1985 ** 09 0b Upstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR# 1986 ** is conditionally asserted when a data parity error is detected by bridge 1987 ** while attempting to retire a PMW upstream 1988 ** 08 0b Secondary Bus Address Parity Error: This bit is set to a 1b and P_SERR# 1989 ** is conditionally asserted when bridge detects an address parity error on 1990 ** the secondary bus. 1991 ** 07 0b Downstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR# 1992 ** is conditionally asserted when the primary bus discard timer expires. 1993 ** 06 0b Downstream Delayed/Split Read Watchdog Timer Expired: 1994 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# 1995 ** is conditionally asserted when bridge discards a downstream delayed read ** ** transaction request after receiving 2 24 target retries 1996 ** from the secondary bus target. 1997 ** PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 1998 ** when bridge discards a downstream split read request 1999 ** after waiting in excess of 2 24 clocks for the corresponding 2000 ** Split Completion to arrive. 2001 ** 05 0b Downstream Delayed Write/Split Watchdog Timer Expired: 2002 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 2003 ** when bridge discards a downstream delayed write transaction request 2004 ** after receiving 2 24 target retries from the secondary bus target. 2005 ** PCI-X Mode: This bit is set to a 1b and P_SERR# 2006 ** is conditionally asserted when bridge discards a downstream 2007 ** split write request after waiting in excess of 2 24 clocks 2008 ** for the corresponding Split Completion to arrive. 2009 ** 04 0b Master Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR# 2010 ** is conditionally asserted when a Master Abort occurs as a result of an attempt, 2011 ** by bridge, to retire a PMW downstream. 2012 ** 03 0b Target Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR# is conditionally asserted 2013 ** when a Target Abort occurs as a result of an attempt, by bridge, 2014 ** to retire a PMW downstream. 2015 ** 02 0b Downstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR# 2016 ** is conditionally asserted when bridge discards a downstream PMW transaction 2017 ** after receiving 2 24 target retries from the secondary bus target 2018 ** 01 0b Downstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR# 2019 ** is conditionally asserted when a data parity error is detected by bridge 2020 ** while attempting to retire a PMW downstream. 2021 ** 00 0b Primary Bus Address Parity Error: This bit is set to a 1b and P_SERR# is conditionally asserted 2022 ** when bridge detects an address parity error on the primary bus. 2023 **================================================================================== 2024 ** 0x51-0x50: Bridge Multi-Transaction Timer Register - BMTTR 2025 ** Bit Default Description 2026 ** 15:13 000b Reserved 2027 ** 12:10 000b GRANT# Duration: This field specifies the count (PCI clocks) 2028 ** that a secondary bus master has its grant maintained in order to enable 2029 ** multiple transactions to execute within the same arbitration cycle. 2030 ** Bit[02:00] GNT# Extended Duration 2031 ** 000 MTT Disabled (Default=no GNT# extension) 2032 ** 001 16 clocks 2033 ** 010 32 clocks 2034 ** 011 64 clocks 2035 ** 100 128 clocks 2036 ** 101 256 clocks 2037 ** 110 Invalid (treated as 000) 2038 ** 111 Invalid (treated as 000) 2039 ** 09:08 00b Reserved 2040 ** 07:00 FFh MTT Mask: This field enables/disables MTT usage for each REQ#/GNT# 2041 ** pair supported by bridge secondary arbiter. 2042 ** Bit(7) corresponds to SATU internal REQ#/GNT# pair, 2043 ** bit(6) corresponds to bridge internal REQ#/GNT# pair, 2044 ** bit(5) corresponds to REQ#/GNT#(5) pair, etc. 2045 ** When a given bit is set to 1b, its corresponding REQ#/GNT# 2046 ** pair is enabled for MTT functionality as determined by bits(12:10) of this register. 2047 ** When a given bit is cleared to 0b, its corresponding REQ#/GNT# pair is disabled from using the MTT. 2048 **================================================================================== 2049 ** 0x53-0x52: Read Prefetch Policy Register - RPPR 2050 ** Bit Default Description 2051 ** 15:13 000b ReRead_Primary Bus: 3-bit field indicating the multiplication factor 2052 ** to be used in calculating the number of bytes to prefetch from the secondary bus interface on ** subsequent PreFetch operations given that the read demands were not satisfied 2053 ** using the FirstRead parameter. 2054 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs 2055 ** Memory Read Line 1 cache lines Memory Read Multiple 2 cache lines 2056 ** 12:10 000b FirstRead_Primary Bus: 3-bit field indicating the multiplication factor to be used in calculating 2057 ** the number of bytes to prefetch from the secondary bus interface 2058 ** on the initial PreFetch operation. 2059 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs 2060 ** Memory Read Line 1 cache line Memory Read Multiple 2 cache lines 2061 ** 09:07 010b ReRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used 2062 ** in calculating the number of bytes to prefetch from the primary 2063 ** bus interface on subsequent PreFetch operations given 2064 ** that the read demands were not satisfied using 2065 ** the FirstRead parameter. 2066 ** The default value of 010b correlates to: Command Type Hardwired pre-fetch a 2067 ** mount Memory Read 3 cache lines Memory Read Line 3 cache lines 2068 ** Memory Read Multiple 6 cache lines 2069 ** 06:04 000b FirstRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used 2070 ** in calculating the number of bytes to prefetch from 2071 ** the primary bus interface on the initial PreFetch operation. 2072 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount 2073 ** Memory Read 4 DWORDs Memory Read Line 1 cache line Memory Read Multiple 2 cache lines 2074 ** 03:00 1111b Staged Prefetch Enable: This field enables/disables the FirstRead/ReRead pre-fetch 2075 ** algorithm for the secondary and the primary bus interfaces. 2076 ** Bit(3) is a ganged enable bit for REQ#/GNT#[7:3], and bits(2:0) provide individual 2077 ** enable bits for REQ#/GNT#[2:0]. 2078 ** (bit(2) is the enable bit for REQ#/GNT#[2], etc...) 2079 ** 1b: enables the staged pre-fetch feature 2080 ** 0b: disables staged pre-fetch, 2081 ** and hardwires read pre-fetch policy to the following for 2082 ** Memory Read, 2083 ** Memory Read Line, 2084 ** and Memory Read Multiple commands: 2085 ** Command Type Hardwired Pre-Fetch Amount... 2086 ** Memory Read 4 DWORDs 2087 ** Memory Read Line 1 cache line 2088 ** Memory Read Multiple 2 cache lines 2089 ** NOTE: When the starting address is not cache line aligned, bridge pre-fetches Memory Read line commands 2090 ** only to the next higher cache line boundary.For non-cache line aligned Memory Read 2091 ** Multiple commands bridge pre-fetches only to the second cache line boundary encountered. 2092 **================================================================================== 2093 ** 0x55-0x54: P_SERR# Assertion Control - SERR_CTL 2094 ** Bit Default Description 2095 ** 15 0b Upstream Delayed Transaction Discard Timer Expired: Dictates the bridge behavior 2096 ** in response to its discarding of a delayed transaction that was initiated from the primary bus. 2097 ** 0b=bridge asserts P_SERR#. 2098 ** 1b=bridge does not assert P_SERR# 2099 ** 14 0b Upstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 2100 ** 0b=bridge asserts P_SERR#. 2101 ** 1b=bridge does not assert P_SERR# 2102 ** 13 0b Upstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 2103 ** 0b=bridge asserts P_SERR#. 2104 ** 1b=bridge does not assert P_SERR# 2105 ** 12 0b Master Abort during Upstream Posted Write: Dictates bridge behavior following 2106 ** its having detected a Master Abort while attempting to retire one of its PMWs upstream. 2107 ** 0b=bridge asserts P_SERR#. 2108 ** 1b=bridge does not assert P_SERR# 2109 ** 11 0b Target Abort during Upstream Posted Write: Dictates bridge behavior following 2110 ** its having been terminated with Target Abort while attempting to retire one of its PMWs upstream. 2111 ** 0b=bridge asserts P_SERR#. 2112 ** 1b=bridge does not assert P_SERR# 2113 ** 10 0b Upstream Posted Write Data Discarded: Dictates bridge behavior in the event that 2114 ** it discards an upstream posted write transaction. 2115 ** 0b=bridge asserts P_SERR#. 2116 ** 1b=bridge does not assert P_SERR# 2117 ** 09 0b Upstream Posted Write Data Parity Error: Dictates bridge behavior 2118 ** when a data parity error is detected while attempting to retire on of its PMWs upstream. 2119 ** 0b=bridge asserts P_SERR#. 2120 ** 1b=bridge does not assert P_SERR# 2121 ** 08 0b Secondary Bus Address Parity Error: This bit dictates bridge behavior 2122 ** when it detects an address parity error on the secondary bus. 2123 ** 0b=bridge asserts P_SERR#. 2124 ** 1b=bridge does not assert P_SERR# 2125 ** 07 0b Downstream Delayed Transaction Discard Timer Expired: Dictates bridge behavior in response to 2126 ** its discarding of a delayed transaction that was initiated on the secondary bus. 2127 ** 0b=bridge asserts P_SERR#. 2128 ** 1b=bridge does not assert P_SERR# 2129 ** 06 0b Downstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 2130 ** 0b=bridge asserts P_SERR#. 2131 ** 1b=bridge does not assert P_SERR# 2132 ** 05 0b Downstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 2133 ** 0b=bridge asserts P_SERR#. 2134 ** 1b=bridge does not assert P_SERR# 2135 ** 04 0b Master Abort during Downstream Posted Write: Dictates bridge behavior following 2136 ** its having detected a Master Abort while attempting to retire one of its PMWs downstream. 2137 ** 0b=bridge asserts P_SERR#. 2138 ** 1b=bridge does not assert P_SERR# 2139 ** 03 0b Target Abort during Downstream Posted Write: Dictates bridge behavior following 2140 ** its having been terminated with Target Abort while attempting to retire one of its PMWs downstream. 2141 ** 0b=bridge asserts P_SERR#. 2142 ** 1b=bridge does not assert P_SERR# 2143 ** 02 0b Downstream Posted Write Data Discarded: Dictates bridge behavior in the event 2144 ** that it discards a downstream posted write transaction. 2145 ** 0b=bridge asserts P_SERR#. 2146 ** 1b=bridge does not assert P_SERR# 2147 ** 01 0b Downstream Posted Write Data Parity Error: Dictates bridge behavior 2148 ** when a data parity error is detected while attempting to retire on of its PMWs downstream. 2149 ** 0b=bridge asserts P_SERR#. 2150 ** 1b=bridge does not assert P_SERR# 2151 ** 00 0b Primary Bus Address Parity Error: This bit dictates bridge behavior 2152 ** when it detects an address parity error on the primary bus. 2153 ** 0b=bridge asserts P_SERR#. 2154 ** 1b=bridge does not assert P_SERR# 2155 **=============================================================================== 2156 ** 0x56: Pre-Boot Status Register - PBSR 2157 ** Bit Default Description 2158 ** 07 1 Reserved 2159 ** 06 - Reserved - value indeterminate 2160 ** 05:02 0 Reserved 2161 ** 01 Varies with External State of S_133EN at PCI Bus Reset Secondary Bus Max Frequency Setting: 2162 ** This bit reflect captured S_133EN strap, 2163 ** indicating the maximum secondary bus clock frequency when in PCI-X mode. 2164 ** Max Allowable Secondary Bus Frequency 2165 ** ** S_133EN PCI-X Mode 2166 ** ** 0 100 MHz 2167 ** ** 1 133 MH 2168 ** 00 0b Reserved 2169 **=============================================================================== 2170 ** 0x59-0x58: Secondary Decode Enable Register - SDER 2171 ** Bit Default Description 2172 ** 15:03 FFF1h Preserved. 2173 ** 02 Varies with External State of PRIVMEM at PCI Bus Reset Private Memory Space Enable - when set, 2174 ** bridge overrides its secondary inverse decode logic and not 2175 ** forward upstream any secondary bus initiated DAC Memory transactions with AD(63)=1b. 2176 ** This creates a private memory space on the Secondary PCI bus 2177 ** that allows peer-to-peer transactions. 2178 ** 01:00 10 2 Preserved. 2179 **=============================================================================== 2180 ** 0x5D-0x5C: Secondary IDSEL Select Register - SISR 2181 ** Bit Default Description 2182 ** 15:10 000000 2 Reserved. 2183 ** 09 Varies with External State of PRIVDEV at PCI Bus Reset AD25- IDSEL Disable - When this bit is set, 2184 ** AD25 is deasserted for any possible Type 1 to Type 0 conversion. 2185 ** When this bit is clear, 2186 ** AD25 is asserted when Primary addresses AD[15:11]=01001 2 during a Type 1 to Type 0 conversion. 2187 ** 08 Varies with External State of PRIVDEV at PCI Bus Reset AD24- IDSEL Disable - When this bit is set, 2188 ** AD24 is deasserted for any possible Type 1 to Type 0 conversion. 2189 ** When this bit is clear, 2190 ** AD24 is asserted when Primary addresses AD[15:11]=01000 2 during a Type 1 to Type 0 conversion. 2191 ** 07 Varies with External State of PRIVDEV at PCI Bus Reset AD23- IDSEL Disable - When this bit is set, 2192 ** AD23 is deasserted for any possible Type 1 to Type 0 conversion. 2193 ** When this bit is clear, 2194 ** AD23 is asserted when Primary addresses AD[15:11]=00111 2 during a Type 1 to Type 0 conversion. 2195 ** 06 Varies with External State of PRIVDEV at PCI Bus Reset AD22- IDSEL Disable - When this bit is set, 2196 ** AD22 is deasserted for any possible Type 1 to Type 0 conversion. 2197 ** When this bit is clear, 2198 ** AD22 is asserted when Primary addresses AD[15:11]=00110 2 during a Type 1 to Type 0 conversion. 2199 ** 05 Varies with External State of PRIVDEV at PCI Bus Reset AD21- IDSEL Disable - When this bit is set, 2200 ** AD21 is deasserted for any possible Type 1 to Type 0 conversion. 2201 ** When this bit is clear, 2202 ** AD21 is asserted when Primary addresses AD[15:11]=00101 2 during a Type 1 to Type 0 conversion. 2203 ** 04 Varies with External State of PRIVDEV at PCI Bus Reset AD20- IDSEL Disable - When this bit is set, 2204 ** AD20 is deasserted for any possible Type 1 to Type 0 conversion. 2205 ** When this bit is clear, 2206 ** AD20 is asserted when Primary addresses AD[15:11]=00100 2 during a Type 1 to Type 0 conversion. 2207 ** 03 Varies with External State of PRIVDEV at PCI Bus Reset AD19- IDSEL Disable - When this bit is set, 2208 ** AD19 is deasserted for any possible Type 1 to Type 0 conversion. 2209 ** When this bit is clear, 2210 ** AD19 is asserted when Primary addresses AD[15:11]=00011 2 during a Type 1 to Type 0 conversion. 2211 ** 02 Varies with External State of PRIVDEV at PCI Bus Reset AD18- IDSEL Disable - When this bit is set, 2212 ** AD18 is deasserted for any possible Type 1 to Type 0 conversion. 2213 ** When this bit is clear, 2214 ** AD18 is asserted when Primary addresses AD[15:11]=00010 2 during a Type 1 to Type 0 conversion. 2215 ** 01 Varies with External State of PRIVDEV at PCI Bus Reset AD17- IDSEL Disable - When this bit is set, 2216 ** AD17 is deasserted for any possible Type 1 to Type 0 conversion. 2217 ** When this bit is clear, 2218 ** AD17 is asserted when Primary addresses AD[15:11]=00001 2 during a Type 1 to Type 0 conversion. 2219 ** 00 Varies with External State of PRIVDEV at PCI Bus Reset AD16- IDSEL Disable - When this bit is set, 2220 ** AD16 is deasserted for any possible Type 1 to Type 0 conversion. 2221 ** When this bit is clear, 2222 ** AD16 is asserted when Primary addresses AD[15:11]=00000 2 during a Type 1 to Type 0 conversion. 2223 ************************************************************************** 2224 */ 2225 /* 2226 ************************************************************************** 2227 ** Reserved A8-CBh 2228 ************************************************************************** 2229 */ 2230 /* 2231 ************************************************************************** 2232 ** PCI Extended Enhanced Capabilities List CC-FFh 2233 ************************************************************************** 2234 ** ---------------------------------------------------------------------------------------------------------- 2235 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 2236 ** ---------------------------------------------------------------------------------------------------------- 2237 ** | Power Management Capabilities | Next Item Ptr | Capability ID | DCh 2238 ** ---------------------------------------------------------------------------------------------------------- 2239 ** | PM Data | PPB Support | Extensions Power Management CSR | E0h 2240 ** ---------------------------------------------------------------------------------------------------------- 2241 ** | Reserved | Reserved | Reserved | E4h 2242 ** ---------------------------------------------------------------------------------------------------------- 2243 ** | Reserved | E8h 2244 ** ---------------------------------------------------------------------------------------------------------- 2245 ** | Reserved | Reserved | Reserved | Reserved | ECh 2246 ** ---------------------------------------------------------------------------------------------------------- 2247 ** | PCI-X Secondary Status | Next Item Ptr | Capability ID | F0h 2248 ** ---------------------------------------------------------------------------------------------------------- 2249 ** | PCI-X Bridge Status | F4h 2250 ** ---------------------------------------------------------------------------------------------------------- 2251 ** | PCI-X Upstream Split Transaction Control | F8h 2252 ** ---------------------------------------------------------------------------------------------------------- 2253 ** | PCI-X Downstream Split Transaction Control | FCh 2254 ** ---------------------------------------------------------------------------------------------------------- 2255 **=============================================================================== 2256 ** 0xDC: Power Management Capabilities Identifier - PM_CAPID 2257 ** Bit Default Description 2258 ** 07:00 01h Identifier (ID): PCI SIG assigned ID for PCI-PM register block 2259 **=============================================================================== 2260 ** 0xDD: Next Item Pointer - PM_NXTP 2261 ** Bit Default Description 2262 ** 07:00 F0H Next Capabilities Pointer (PTR): The register defaults to F0H pointing to the PCI-X Extended Capability Header. 2263 **=============================================================================== 2264 ** 0xDF-0xDE: Power Management Capabilities Register - PMCR 2265 ** Bit Default Description 2266 ** 15:11 00h PME Supported (PME): PME# cannot be asserted by bridge. 2267 ** 10 0h State D2 Supported (D2): Indicates no support for state D2. No power management action in this state. 2268 ** 09 1h State D1 Supported (D1): Indicates support for state D1. No power management action in this state. 2269 ** 08:06 0h Auxiliary Current (AUXC): This 3 bit field reports the 3.3Vaux auxiliary current requirements for the PCI function. 2270 ** This returns 000b as PME# wake-up for bridge is not implemented. 2271 ** 05 0 Special Initialization Required (SINT): Special initialization is not required for bridge. 2272 ** 04:03 00 Reserved 2273 ** 02:00 010 Version (VS): Indicates that this supports PCI Bus Power Management Interface Specification, Revision 1.1. 2274 **=============================================================================== 2275 ** 0xE1-0xE0: Power Management Control / Status - Register - PMCSR 2276 ** Bit Default Description 2277 ** 15:09 00h Reserved 2278 ** 08 0b PME_Enable: This bit, when set to 1b enables bridge to assert PME#. 2279 ** Note that bridge never has occasion to assert PME# and implements this dummy R/W bit only for the purpose of working around an OS PCI-PM bug. 2280 ** 07:02 00h Reserved 2281 ** 01:00 00 Power State (PSTATE): This 2-bit field is used both to determine the current power state of 2282 ** a function and to set the Function into a new power state. 2283 ** 00 - D0 state 2284 ** 01 - D1 state 2285 ** 10 - D2 state 2286 ** 11 - D3 hot state 2287 **=============================================================================== 2288 ** 0xE2: Power Management Control / Status PCI to PCI Bridge Support - PMCSR_BSE 2289 ** Bit Default Description 2290 ** 07 0 Bus Power/Clock Control Enable (BPCC_En): Indicates that the bus power/clock control policies have been disabled. 2291 ** 06 0 B2/B3 support for D3 Hot (B2_B3#): The state of this bit determines the action that 2292 ** is to occur as a direct result of programming the function to D3 hot. 2293 ** This bit is only meaningful when bit 7 (BPCC_En) is a ��1��. 2294 ** 05:00 00h Reserved 2295 **=============================================================================== 2296 ** 0xE3: Power Management Data Register - PMDR 2297 ** Bit Default Description 2298 ** 07:00 00h Reserved 2299 **=============================================================================== 2300 ** 0xF0: PCI-X Capabilities Identifier - PX_CAPID 2301 ** Bit Default Description 2302 ** 07:00 07h Identifier (ID): Indicates this is a PCI-X capabilities list. 2303 **=============================================================================== 2304 ** 0xF1: Next Item Pointer - PX_NXTP 2305 ** Bit Default Description 2306 ** 07:00 00h Next Item Pointer: Points to the next capability in the linked list The power on default value of this 2307 ** register is 00h indicating that this is the last entry in the linked list of capabilities. 2308 **=============================================================================== 2309 ** 0xF3-0xF2: PCI-X Secondary Status - PX_SSTS 2310 ** Bit Default Description 2311 ** 15:09 00h Reserved 2312 ** 08:06 Xxx Secondary Clock Frequency (SCF): This field is set with the frequency of the secondary bus. 2313 ** The values are: 2314 ** ** BitsMax FrequencyClock Period 2315 ** ** 000PCI ModeN/A 2316 ** ** 00166 15 2317 ** ** 01010010 2318 ** ** 0111337.5 2319 ** ** 1xxreservedreserved 2320 ** ** The default value for this register is the operating frequency of the secondary bus 2321 ** 05 0b Split Request Delayed. (SRD): This bit is supposed to be set by a bridge when it cannot forward a transaction on the 2322 ** secondary bus to the primary bus because there is not enough room within the limit 2323 ** specified in the Split Transaction Commitment Limit field in the Downstream Split 2324 ** Transaction Control register. The bridge does not set this bit. 2325 ** 04 0b Split Completion Overrun (SCO): This bit is supposed to be set when a bridge terminates a Split Completion on the ** ** secondary bus with retry or Disconnect at next ADB because its buffers are full. 2326 ** The bridge does not set this bit. 2327 ** 03 0b Unexpected Split Completion (USC): This bit is set when an unexpected split completion with a requester ID 2328 ** equal to bridge secondary bus number, device number 00h, 2329 ** and function number 0 is received on the secondary interface. 2330 ** This bit is cleared by software writing a '1'. 2331 ** 02 0b Split Completion Discarded (SCD): This bit is set 2332 ** when bridge discards a split completion moving toward the secondary bus 2333 ** because the requester would not accept it. This bit cleared by software writing a '1'. 2334 ** 01 1b 133 MHz Capable: Indicates that bridge is capable of running its secondary bus at 133 MHz 2335 ** 00 1b 64-bit Device (D64): Indicates the width of the secondary bus as 64-bits. 2336 **=============================================================================== 2337 ** 0xF7-0xF6-0xf5-0xF4: PCI-X Bridge Status - PX_BSTS 2338 ** Bit Default Description 2339 ** 31:22 0 Reserved 2340 ** 21 0 Split Request Delayed (SRD): This bit does not be set by bridge. 2341 ** 20 0 Split Completion Overrun (SCO): This bit does not be set by bridge 2342 ** because bridge throttles traffic on the completion side. 2343 ** 19 0 Unexpected Split Completion (USC): The bridge sets this bit to 1b 2344 ** when it encounters a corrupted Split Completion, possibly with an ** ** inconsistent remaining byte count.Software clears 2345 ** this bit by writing a 1b to it. 2346 ** 18 0 Split Completion Discarded (SCD): The bridge sets this bit to 1b 2347 ** when it has discarded a Split Completion.Software clears this bit by ** ** writing a 1b to it. 2348 ** 17 1 133 MHz Capable: This bit indicates that the bridge primary interface is ** capable of 133 MHz operation in PCI-X mode. 2349 ** 0=The maximum operating frequency is 66 MHz. 2350 ** 1=The maximum operating frequency is 133 MHz. 2351 ** 16 Varies with the external state of P_32BITPCI# at PCI Bus Reset 64-bit Device (D64): Indicates bus width of the Primary PCI bus interface. 2352 ** 0=Primary Interface is connected as a 32-bit PCI bus. 2353 ** 1=Primary Interface is connected as a 64-bit PCI bus. 2354 ** 15:08 00h Bus Number (BNUM): This field is simply an alias to the PBN field 2355 ** of the BNUM register at offset 18h. 2356 ** Apparently it was deemed necessary reflect it here for diagnostic purposes. 2357 ** 07:03 1fh Device Number (DNUM): Indicates which IDSEL bridge consumes. 2358 ** May be updated whenever a PCI-X 2359 ** configuration write cycle that targets bridge scores a hit. 2360 ** 02:00 0h Function Number (FNUM): The bridge Function # 2361 **=============================================================================== 2362 ** 0xFB-0xFA-0xF9-0xF8: PCI-X Upstream Split Transaction Control - PX_USTC 2363 ** Bit Default Description 2364 ** 31:16 003Eh Split Transaction Limit (STL): This register indicates the size of the commitment limit in units of ADQs. 2365 ** Software is permitted to program this register to any value greater than or equal to 2366 ** the contents of the Split Transaction Capacity register. A value less than the contents 2367 ** of the Split Transaction Capacity register causes unspecified results. 2368 ** A value of 003Eh or greater enables the bridge to forward all Split Requests of any 2369 ** size regardless of the amount of buffer space available. 2370 ** 15:00 003Eh Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing 2371 ** split completions. This register controls behavior of the bridge buffers for forwarding 2372 ** Split Transactions from a primary bus requester to a secondary bus completer. 2373 ** The default value of 003Eh indicates there is available buffer space for 62 ADQs (7936 bytes). 2374 **=============================================================================== 2375 ** 0xFF-0xFE-0xFD-0xFC: PCI-X Downstream Split Transaction Control - PX_DSTC 2376 ** Bit Default Description 2377 ** 31:16 003Eh Split Transaction Limit (STL): This register indicates the size of the commitment limit in units of ADQs. 2378 ** Software is permitted to program this register to any value greater than or equal to 2379 ** the contents of the Split Transaction Capacity register. A value less than the contents 2380 ** of the Split Transaction Capacity register causes unspecified results. 2381 ** A value of 003Eh or greater enables the bridge to forward all Split Requests of any 2382 ** size regardless of the amount of buffer space available. 2383 ** 15:00 003Eh Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing 2384 ** split completions. This register controls behavior of the bridge buffers for forwarding 2385 ** Split Transactions from a primary bus requester to a secondary bus completer. 2386 ** The default value of 003Eh indicates there is available buffer space for 62 ADQs 2387 ** (7936 bytes). 2388 ************************************************************************** 2389 */ 2390 2391 2392 2393 2394 /* 2395 ************************************************************************************************************************************* 2396 ** 80331 Address Translation Unit Register Definitions 2397 ** ATU Interface Configuration Header Format 2398 ** The ATU is programmed via a [Type 0] configuration command on the PCI interface. 2399 ************************************************************************************************************************************* 2400 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configuration Byte Offset 2401 **=================================================================================================================================== 2402 ** | ATU Device ID | Vendor ID | 00h 2403 ** ---------------------------------------------------------------------------------------------------------- 2404 ** | Status | Command | 04H 2405 ** ---------------------------------------------------------------------------------------------------------- 2406 ** | ATU Class Code | Revision ID | 08H 2407 ** ---------------------------------------------------------------------------------------------------------- 2408 ** | ATUBISTR | Header Type | Latency Timer | Cacheline Size | 0CH 2409 ** ---------------------------------------------------------------------------------------------------------- 2410 ** | Inbound ATU Base Address 0 | 10H 2411 ** ---------------------------------------------------------------------------------------------------------- 2412 ** | Inbound ATU Upper Base Address 0 | 14H 2413 ** ---------------------------------------------------------------------------------------------------------- 2414 ** | Inbound ATU Base Address 1 | 18H 2415 ** ---------------------------------------------------------------------------------------------------------- 2416 ** | Inbound ATU Upper Base Address 1 | 1CH 2417 ** ---------------------------------------------------------------------------------------------------------- 2418 ** | Inbound ATU Base Address 2 | 20H 2419 ** ---------------------------------------------------------------------------------------------------------- 2420 ** | Inbound ATU Upper Base Address 2 | 24H 2421 ** ---------------------------------------------------------------------------------------------------------- 2422 ** | Reserved | 28H 2423 ** ---------------------------------------------------------------------------------------------------------- 2424 ** | ATU Subsystem ID | ATU Subsystem Vendor ID | 2CH 2425 ** ---------------------------------------------------------------------------------------------------------- 2426 ** | Expansion ROM Base Address | 30H 2427 ** ---------------------------------------------------------------------------------------------------------- 2428 ** | Reserved Capabilities Pointer | 34H 2429 ** ---------------------------------------------------------------------------------------------------------- 2430 ** | Reserved | 38H 2431 ** ---------------------------------------------------------------------------------------------------------- 2432 ** | Maximum Latency | Minimum Grant | Interrupt Pin | Interrupt Line | 3CH 2433 ** ---------------------------------------------------------------------------------------------------------- 2434 ********************************************************************************************************************* 2435 */ 2436 /* 2437 *********************************************************************************** 2438 ** ATU Vendor ID Register - ATUVID 2439 ** ----------------------------------------------------------------- 2440 ** Bit Default Description 2441 ** 15:00 8086H (0x17D3) ATU Vendor ID - This is a 16-bit value assigned to Intel. 2442 ** This register, combined with the DID, uniquely identify the PCI device. 2443 ** Access type is Read/Write to allow the 80331 to configure the register as a different vendor ID 2444 ** to simulate the interface of a standard mechanism currently used by existing application software. 2445 *********************************************************************************** 2446 */ 2447 #define ARCMSR_ATU_VENDOR_ID_REG 0x00 /*word*/ 2448 /* 2449 *********************************************************************************** 2450 ** ATU Device ID Register - ATUDID 2451 ** ----------------------------------------------------------------- 2452 ** Bit Default Description 2453 ** 15:00 0336H (0x1110) ATU Device ID - This is a 16-bit value assigned to the ATU. 2454 ** This ID, combined with the VID, uniquely identify any PCI device. 2455 *********************************************************************************** 2456 */ 2457 #define ARCMSR_ATU_DEVICE_ID_REG 0x02 /*word*/ 2458 /* 2459 *********************************************************************************** 2460 ** ATU Command Register - ATUCMD 2461 ** ----------------------------------------------------------------- 2462 ** Bit Default Description 2463 ** 15:11 000000 2 Reserved 2464 ** 10 0 Interrupt Disable - This bit disables 80331 from asserting the ATU interrupt signal. 2465 ** 0=enables the assertion of interrupt signal. 2466 ** 1=disables the assertion of its interrupt signal. 2467 ** 09 0 2 Fast Back to Back Enable - When cleared, 2468 ** the ATU interface is not allowed to generate fast back-to-back cycles on its bus. 2469 ** Ignored when operating in the PCI-X mode. 2470 ** 08 0 2 SERR# Enable - When cleared, the ATU interface is not allowed to assert SERR# on the PCI interface. 2471 ** 07 1 2 Address/Data Stepping Control - Address stepping is implemented for configuration transactions. The 2472 ** ATU inserts 2 clock cycles of address stepping for Conventional Mode and 4 clock cycles 2473 ** of address stepping for PCI-X mode. 2474 ** 06 0 2 Parity Error Response - When set, the ATU takes normal action when a parity error 2475 ** is detected. When cleared, parity checking is disabled. 2476 ** 05 0 2 VGA Palette Snoop Enable - The ATU interface does not support I/O writes and therefore, 2477 ** does not perform VGA palette snooping. 2478 ** 04 0 2 Memory Write and Invalidate Enable - When set, ATU may generate MWI commands. 2479 ** When clear, ATU use Memory Write commands instead of MWI. Ignored when operating in the PCI-X mode. 2480 ** 03 0 2 Special Cycle Enable - The ATU interface does not respond to special cycle commands in any way. 2481 ** Not implemented and a reserved bit field. 2482 ** 02 0 2 Bus Master Enable - The ATU interface can act as a master on the PCI bus. 2483 ** When cleared, disables the device from generating PCI accesses. 2484 ** When set, allows the device to behave as a PCI bus master. 2485 ** When operating in the PCI-X mode, ATU initiates a split completion transaction regardless 2486 ** of the state of this bit. 2487 ** 01 0 2 Memory Enable - Controls the ATU interface��s response to PCI memory addresses. 2488 ** When cleared, the ATU interface does not respond to any memory access on the PCI bus. 2489 ** 00 0 2 I/O Space Enable - Controls the ATU interface response to I/O transactions. 2490 ** Not implemented and a reserved bit field. 2491 *********************************************************************************** 2492 */ 2493 #define ARCMSR_ATU_COMMAND_REG 0x04 /*word*/ 2494 /* 2495 *********************************************************************************** 2496 ** ATU Status Register - ATUSR (Sheet 1 of 2) 2497 ** ----------------------------------------------------------------- 2498 ** Bit Default Description 2499 ** 15 0 2 Detected Parity Error - set when a parity error is detected in data received by the ATU on the PCI bus even 2500 ** when the ATUCMD register��s Parity Error Response bit is cleared. Set under the following conditions: 2501 ** �E Write Data Parity Error when the ATU is a target (inbound write). 2502 ** �E Read Data Parity Error when the ATU is a requester (outbound read). 2503 ** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus ** ** ** (including one generated by the ATU). 2504 ** 14 0 2 SERR# Asserted - set when SERR# is asserted on the PCI bus by the ATU. 2505 ** 13 0 2 Master Abort - set when a transaction initiated by the ATU PCI master interface, ends in a Master-Abort 2506 ** or when the ATU receives a Master Abort Split Completion Error Message in PCI-X mode. 2507 ** 12 0 2 Target Abort (master) - set when a transaction initiated by the ATU PCI master interface, ends in a target 2508 ** abort or when the ATU receives a Target Abort Split Completion Error Message in PCI-X mode. 2509 ** 11 0 2 Target Abort (target) - set when the ATU interface, acting as a target, 2510 ** terminates the transaction on the PCI bus with a target abort. 2511 ** 10:09 01 2 DEVSEL# Timing - These bits are read-only and define the slowest DEVSEL# 2512 ** timing for a target device in Conventional PCI Mode regardless of the operating mode 2513 ** (except configuration accesses). 2514 ** 00 2=Fast 2515 ** 01 2=Medium 2516 ** 10 2=Slow 2517 ** 11 2=Reserved 2518 ** The ATU interface uses Medium timing. 2519 ** 08 0 2 Master Parity Error - The ATU interface sets this bit under the following conditions: 2520 ** �E The ATU asserted PERR# itself or the ATU observed PERR# asserted. 2521 ** �E And the ATU acted as the requester 2522 ** for the operation in which the error occurred. 2523 ** �E And the ATUCMD register��s Parity Error Response bit is set 2524 ** �E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message 2525 ** �E And the ATUCMD register��s Parity Error Response bit is set 2526 ** 07 1 2 (Conventional mode) 2527 ** 0 2 (PCI-X mode) 2528 ** Fast Back-to-Back - The ATU/Messaging Unit interface is capable of accepting fast back-to-back 2529 ** transactions in Conventional PCI mode when the transactions are not to the same target. Since fast 2530 ** back-to-back transactions do not exist in PCI-X mode, this bit is forced to 0 in the PCI-X mode. 2531 ** 06 0 2 UDF Supported - User Definable Features are not supported 2532 ** 05 1 2 66 MHz. Capable - 66 MHz operation is supported. 2533 ** 04 1 2 Capabilities - When set, this function implements extended capabilities. 2534 ** 03 0 Interrupt Status - reflects the state of the ATU interrupt 2535 ** when the Interrupt Disable bit in the command register is a 0. 2536 ** 0=ATU interrupt signal deasserted. 2537 ** 1=ATU interrupt signal asserted. 2538 ** NOTE: Setting the Interrupt Disable bit to a 1 has no effect on the state of this bit. Refer to 2539 ** Section 3.10.23, ��ATU Interrupt Pin Register - ATUIPR�� on page 236 for details on the ATU 2540 ** interrupt signal. 2541 ** 02:00 00000 2 Reserved. 2542 *********************************************************************************** 2543 */ 2544 #define ARCMSR_ATU_STATUS_REG 0x06 /*word*/ 2545 /* 2546 *********************************************************************************** 2547 ** ATU Revision ID Register - ATURID 2548 ** ----------------------------------------------------------------- 2549 ** Bit Default Description 2550 ** 07:00 00H ATU Revision - identifies the 80331 revision number. 2551 *********************************************************************************** 2552 */ 2553 #define ARCMSR_ATU_REVISION_REG 0x08 /*byte*/ 2554 /* 2555 *********************************************************************************** 2556 ** ATU Class Code Register - ATUCCR 2557 ** ----------------------------------------------------------------- 2558 ** Bit Default Description 2559 ** 23:16 05H Base Class - Memory Controller 2560 ** 15:08 80H Sub Class - Other Memory Controller 2561 ** 07:00 00H Programming Interface - None defined 2562 *********************************************************************************** 2563 */ 2564 #define ARCMSR_ATU_CLASS_CODE_REG 0x09 /*3bytes 0x0B,0x0A,0x09*/ 2565 /* 2566 *********************************************************************************** 2567 ** ATU Cacheline Size Register - ATUCLSR 2568 ** ----------------------------------------------------------------- 2569 ** Bit Default Description 2570 ** 07:00 00H ATU Cacheline Size - specifies the system cacheline size in DWORDs. Cacheline size is restricted to either 0, 8 or 16 DWORDs. 2571 *********************************************************************************** 2572 */ 2573 #define ARCMSR_ATU_CACHELINE_SIZE_REG 0x0C /*byte*/ 2574 /* 2575 *********************************************************************************** 2576 ** ATU Latency Timer Register - ATULT 2577 ** ----------------------------------------------------------------- 2578 ** Bit Default Description 2579 ** 07:03 00000 2 (for Conventional mode) 2580 ** 01000 2 (for PCI-X mode) 2581 ** Programmable Latency Timer - This field varies the latency timer for the interface from 0 to 248 clocks. 2582 ** The default value is 0 clocks for Conventional PCI mode, and 64 clocks for PCI-X mode. 2583 ** 02:00 000 2 Latency Timer Granularity - These Bits are read only giving a programmable granularity of 8 clocks for the latency timer. 2584 *********************************************************************************** 2585 */ 2586 #define ARCMSR_ATU_LATENCY_TIMER_REG 0x0D /*byte*/ 2587 /* 2588 *********************************************************************************** 2589 ** ATU Header Type Register - ATUHTR 2590 ** ----------------------------------------------------------------- 2591 ** Bit Default Description 2592 ** 07 0 2 Single Function/Multi-Function Device - Identifies the 80331 as a single-function PCI device. 2593 ** 06:00 000000 2 PCI Header Type - This bit field indicates the type of PCI header implemented. The ATU interface 2594 ** header conforms to PCI Local Bus Specification, Revision 2.3. 2595 *********************************************************************************** 2596 */ 2597 #define ARCMSR_ATU_HEADER_TYPE_REG 0x0E /*byte*/ 2598 /* 2599 *********************************************************************************** 2600 ** ATU BIST Register - ATUBISTR 2601 ** 2602 ** The ATU BIST Register controls the functions the Intel XScale core performs when BIST is 2603 ** initiated. This register is the interface between the host processor requesting BIST functions and 2604 ** the 80331 replying with the results from the software implementation of the BIST functionality. 2605 ** ----------------------------------------------------------------- 2606 ** Bit Default Description 2607 ** 07 0 2 BIST Capable - This bit value is always equal to the ATUCR ATU BIST Interrupt Enable bit. 2608 ** 06 0 2 Start BIST - When the ATUCR BIST Interrupt Enable bit is set: 2609 ** Setting this bit generates an interrupt to the Intel XScale core to perform a software BIST function. 2610 ** The Intel XScale core clears this bit when the BIST software has completed with the BIST results 2611 ** found in ATUBISTR register bits [3:0]. 2612 ** When the ATUCR BIST Interrupt Enable bit is clear: 2613 ** Setting this bit does not generate an interrupt to the Intel XScale core and no BIST functions is performed. 2614 ** The Intel XScale core does not clear this bit. 2615 ** 05:04 00 2 Reserved 2616 ** 03:00 0000 2 BIST Completion Code - when the ATUCR BIST Interrupt Enable bit is set and the ATUBISTR Start BIST bit is set (bit 6): 2617 ** The Intel XScale core places the results of the software BIST in these bits. 2618 ** A nonzero value indicates a device-specific error. 2619 *********************************************************************************** 2620 */ 2621 #define ARCMSR_ATU_BIST_REG 0x0F /*byte*/ 2622 2623 /* 2624 *************************************************************************************** 2625 ** ATU Base Registers and Associated Limit Registers 2626 *************************************************************************************** 2627 ** Base Address Register Limit Register Description 2628 ** Inbound ATU Base Address Register 0 Inbound ATU Limit Register 0 Defines the inbound translation window 0 from the PCI bus. 2629 ** Inbound ATU Upper Base Address Register 0 N/A Together with ATU Base Address Register 0 defines the inbound ** translation window 0 from the PCI bus for DACs. 2630 ** Inbound ATU Base Address Register 1 Inbound ATU Limit Register 1 Defines inbound window 1 from the PCI bus. 2631 ** Inbound ATU Upper Base Address Register 1 N/A Together with ATU Base Address Register 1 defines inbound window ** 1 from the PCI bus for DACs. 2632 ** Inbound ATU Base Address Register 2 Inbound ATU Limit Register 2 Defines the inbound translation window 2 from the PCI bus. 2633 ** Inbound ATU Upper Base Address Register 2 N/A Together with ATU Base Address Register 2 defines the inbound ** ** translation window 2 from the PCI bus for DACs. 2634 ** Inbound ATU Base Address Register 3 Inbound ATU Limit Register 3 Defines the inbound translation window 3 from the PCI bus. 2635 ** Inbound ATU Upper Base Address Register 3 N/A Together with ATU Base Address Register 3 defines the inbound ** ** translation window 3 from the PCI bus for DACs. 2636 ** NOTE: This is a private BAR that resides outside of the standard PCI configuration header space (offsets 00H-3FH). 2637 ** Expansion ROM Base Address Register Expansion ROM Limit Register Defines the window of addresses used by a bus master for reading ** from an Expansion ROM. 2638 **-------------------------------------------------------------------------------------- 2639 ** ATU Inbound Window 1 is not a translate window. 2640 ** The ATU does not claim any PCI accesses that fall within this range. 2641 ** This window is used to allocate host memory for use by Private Devices. 2642 ** When enabled, the ATU interrupts the Intel XScale core when either the IABAR1 register or the IAUBAR1 register is written from the PCI bus. 2643 *********************************************************************************** 2644 */ 2645 2646 /* 2647 *********************************************************************************** 2648 ** Inbound ATU Base Address Register 0 - IABAR0 2649 ** 2650 ** . The Inbound ATU Base Address Register 0 (IABAR0) together with the Inbound ATU Upper Base Address Register 0 (IAUBAR0) 2651 ** defines the block of memory addresses where the inbound translation window 0 begins. 2652 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 2653 ** . The IABAR0 and IAUBAR0 define the base address and describes the required memory block size. 2654 ** . Bits 31 through 12 of the IABAR0 is either read/write bits or read only with a value of 0 2655 ** depending on the value located within the IALR0. 2656 ** This configuration allows the IABAR0 to be programmed per PCI Local Bus Specification. 2657 ** The first 4 Kbytes of memory defined by the IABAR0, IAUBAR0 and the IALR0 is reserved for the Messaging Unit. 2658 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2659 ** Warning: 2660 ** When IALR0 is cleared prior to host configuration: 2661 ** the user should also clear the Prefetchable Indicator and the Type Indicator. 2662 ** Assuming IALR0 is not cleared: 2663 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 2664 ** when the Prefetchable Indicator is cleared prior to host configuration, 2665 ** the user should also set the Type Indicator for 32 bit addressability. 2666 ** b. For compliance to the PCI-X Addendum to the PCI Local Bus Specification, 2667 ** when the Prefetchable Indicator is set prior to host configuration, the user 2668 ** should also set the Type Indicator for 64 bit addressability. 2669 ** This is the default for IABAR0. 2670 ** ----------------------------------------------------------------- 2671 ** Bit Default Description 2672 ** 31:12 00000H Translation Base Address 0 - These bits define the actual location 2673 ** the translation function is to respond to when addressed from the PCI bus. 2674 ** 11:04 00H Reserved. 2675 ** 03 1 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 2676 ** 02:01 10 2 Type Indicator - Defines the width of the addressability for this memory window: 2677 ** 00 - Memory Window is locatable anywhere in 32 bit address space 2678 ** 10 - Memory Window is locatable anywhere in 64 bit address space 2679 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 2680 ** The ATU does not occupy I/O space, 2681 ** thus this bit must be zero. 2682 *********************************************************************************** 2683 */ 2684 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS0_REG 0x10 /*dword 0x13,0x12,0x11,0x10*/ 2685 #define ARCMSR_INBOUND_ATU_MEMORY_PREFETCHABLE 0x08 2686 #define ARCMSR_INBOUND_ATU_MEMORY_WINDOW64 0x04 2687 /* 2688 *********************************************************************************** 2689 ** Inbound ATU Upper Base Address Register 0 - IAUBAR0 2690 ** 2691 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 2692 ** Together with the Translation Base Address this register defines the actual location the translation 2693 ** function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 2694 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2695 ** Note: 2696 ** When the Type indicator of IABAR0 is set to indicate 32 bit addressability, 2697 ** the IAUBAR0 register attributes are read-only. 2698 ** ----------------------------------------------------------------- 2699 ** Bit Default Description 2700 ** 31:0 00000H Translation Upper Base Address 0 - Together with the Translation Base Address 0 these bits define the 2701 ** actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes. 2702 *********************************************************************************** 2703 */ 2704 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS0_REG 0x14 /*dword 0x17,0x16,0x15,0x14*/ 2705 /* 2706 *********************************************************************************** 2707 ** Inbound ATU Base Address Register 1 - IABAR1 2708 ** 2709 ** . The Inbound ATU Base Address Register (IABAR1) together with the Inbound ATU Upper Base Address Register 1 (IAUBAR1) 2710 ** defines the block of memory addresses where the inbound translation window 1 begins. 2711 ** . This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PCI bus transactions to this memory range. 2712 ** . The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2713 ** . When enabled, the ATU interrupts the Intel XScale core when the IABAR1 register is written from the PCI bus. 2714 ** Warning: 2715 ** When a non-zero value is not written to IALR1 prior to host configuration, 2716 ** the user should not set either the Prefetchable Indicator or the Type Indicator for 64 bit addressability. 2717 ** This is the default for IABAR1. 2718 ** Assuming a non-zero value is written to IALR1, 2719 ** the user may set the Prefetchable Indicator 2720 ** or the Type Indicator: 2721 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address 2722 ** boundary, when the Prefetchable Indicator is not set prior to host configuration, 2723 ** the user should also leave the Type Indicator set for 32 bit addressability. 2724 ** This is the default for IABAR1. 2725 ** b. when the Prefetchable Indicator is set prior to host configuration, 2726 ** the user should also set the Type Indicator for 64 bit addressability. 2727 ** ----------------------------------------------------------------- 2728 ** Bit Default Description 2729 ** 31:12 00000H Translation Base Address 1 - These bits define the actual location of window 1 on the PCI bus. 2730 ** 11:04 00H Reserved. 2731 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 2732 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 2733 ** 00 - Memory Window is locatable anywhere in 32 bit address space 2734 ** 10 - Memory Window is locatable anywhere in 64 bit address space 2735 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 2736 ** The ATU does not occupy I/O space, 2737 ** thus this bit must be zero. 2738 *********************************************************************************** 2739 */ 2740 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS1_REG 0x18 /*dword 0x1B,0x1A,0x19,0x18*/ 2741 /* 2742 *********************************************************************************** 2743 ** Inbound ATU Upper Base Address Register 1 - IAUBAR1 2744 ** 2745 ** This register contains the upper base address when locating this window for PCI addresses beyond 4 GBytes. 2746 ** Together with the IABAR1 this register defines the actual location for this memory window for addresses > 4GBytes (for DACs). 2747 ** This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PCI bus transactions to this memory range. 2748 ** The programmed value within the base address register must comply with the PCI programming 2749 ** requirements for address alignment. 2750 ** When enabled, the ATU interrupts the Intel XScale core when the IAUBAR1 register is written 2751 ** from the PCI bus. 2752 ** Note: 2753 ** When the Type indicator of IABAR1 is set to indicate 32 bit addressability, 2754 ** the IAUBAR1 register attributes are read-only. 2755 ** This is the default for IABAR1. 2756 ** ----------------------------------------------------------------- 2757 ** Bit Default Description 2758 ** 31:0 00000H Translation Upper Base Address 1 - Together with the Translation Base Address 1 2759 ** these bits define the actual location for this memory window on the PCI bus for addresses > 4GBytes. 2760 *********************************************************************************** 2761 */ 2762 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS1_REG 0x1C /*dword 0x1F,0x1E,0x1D,0x1C*/ 2763 /* 2764 *********************************************************************************** 2765 ** Inbound ATU Base Address Register 2 - IABAR2 2766 ** 2767 ** . The Inbound ATU Base Address Register 2 (IABAR2) together with the Inbound ATU Upper Base Address Register 2 (IAUBAR2) 2768 ** defines the block of memory addresses where the inbound translation window 2 begins. 2769 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 2770 ** . The IABAR2 and IAUBAR2 define the base address and describes the required memory block size 2771 ** . Bits 31 through 12 of the IABAR2 is either read/write bits or read only with a value of 0 depending on the value located within the IALR2. 2772 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2773 ** Warning: 2774 ** When a non-zero value is not written to IALR2 prior to host configuration, 2775 ** the user should not set either the Prefetchable Indicator 2776 ** or the Type Indicator for 64 bit addressability. 2777 ** This is the default for IABAR2. 2778 ** Assuming a non-zero value is written to IALR2, 2779 ** the user may set the Prefetchable Indicator 2780 ** or the Type Indicator: 2781 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 2782 ** when the Prefetchable Indicator is not set prior to host configuration, 2783 ** the user should also leave the Type Indicator set for 32 bit addressability. 2784 ** This is the default for IABAR2. 2785 ** b. when the Prefetchable Indicator is set prior to host configuration, 2786 ** the user should also set the Type Indicator for 64 bit addressability. 2787 ** ----------------------------------------------------------------- 2788 ** Bit Default Description 2789 ** 31:12 00000H Translation Base Address 2 - These bits define the actual location 2790 ** the translation function is to respond to when addressed from the PCI bus. 2791 ** 11:04 00H Reserved. 2792 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 2793 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 2794 ** 00 - Memory Window is locatable anywhere in 32 bit address space 2795 ** 10 - Memory Window is locatable anywhere in 64 bit address space 2796 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 2797 ** The ATU does not occupy I/O space, 2798 ** thus this bit must be zero. 2799 *********************************************************************************** 2800 */ 2801 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS2_REG 0x20 /*dword 0x23,0x22,0x21,0x20*/ 2802 /* 2803 *********************************************************************************** 2804 ** Inbound ATU Upper Base Address Register 2 - IAUBAR2 2805 ** 2806 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 2807 ** Together with the Translation Base Address this register defines the actual location 2808 ** the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 2809 ** The programmed value within the base address register must comply with the PCI programming 2810 ** requirements for address alignment. 2811 ** Note: 2812 ** When the Type indicator of IABAR2 is set to indicate 32 bit addressability, 2813 ** the IAUBAR2 register attributes are read-only. 2814 ** This is the default for IABAR2. 2815 ** ----------------------------------------------------------------- 2816 ** Bit Default Description 2817 ** 31:0 00000H Translation Upper Base Address 2 - Together with the Translation Base Address 2 2818 ** these bits define the actual location the translation function is to respond to 2819 ** when addressed from the PCI bus for addresses > 4GBytes. 2820 *********************************************************************************** 2821 */ 2822 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS2_REG 0x24 /*dword 0x27,0x26,0x25,0x24*/ 2823 /* 2824 *********************************************************************************** 2825 ** ATU Subsystem Vendor ID Register - ASVIR 2826 ** ----------------------------------------------------------------- 2827 ** Bit Default Description 2828 ** 15:0 0000H Subsystem Vendor ID - This register uniquely identifies the add-in board or subsystem vendor. 2829 *********************************************************************************** 2830 */ 2831 #define ARCMSR_ATU_SUBSYSTEM_VENDOR_ID_REG 0x2C /*word 0x2D,0x2C*/ 2832 /* 2833 *********************************************************************************** 2834 ** ATU Subsystem ID Register - ASIR 2835 ** ----------------------------------------------------------------- 2836 ** Bit Default Description 2837 ** 15:0 0000H Subsystem ID - uniquely identifies the add-in board or subsystem. 2838 *********************************************************************************** 2839 */ 2840 #define ARCMSR_ATU_SUBSYSTEM_ID_REG 0x2E /*word 0x2F,0x2E*/ 2841 /* 2842 *********************************************************************************** 2843 ** Expansion ROM Base Address Register -ERBAR 2844 ** ----------------------------------------------------------------- 2845 ** Bit Default Description 2846 ** 31:12 00000H Expansion ROM Base Address - These bits define the actual location 2847 ** where the Expansion ROM address window resides when addressed from the PCI bus on any 4 Kbyte boundary. 2848 ** 11:01 000H Reserved 2849 ** 00 0 2 Address Decode Enable - This bit field shows the ROM address 2850 ** decoder is enabled or disabled. When cleared, indicates the address decoder is disabled. 2851 *********************************************************************************** 2852 */ 2853 #define ARCMSR_EXPANSION_ROM_BASE_ADDRESS_REG 0x30 /*dword 0x33,0x32,0v31,0x30*/ 2854 #define ARCMSR_EXPANSION_ROM_ADDRESS_DECODE_ENABLE 0x01 2855 /* 2856 *********************************************************************************** 2857 ** ATU Capabilities Pointer Register - ATU_CAP_PTR 2858 ** ----------------------------------------------------------------- 2859 ** Bit Default Description 2860 ** 07:00 C0H Capability List Pointer - This provides an offset in this function��s configuration space 2861 ** that points to the 80331 PCl Bus Power Management extended capability. 2862 *********************************************************************************** 2863 */ 2864 #define ARCMSR_ATU_CAPABILITY_PTR_REG 0x34 /*byte*/ 2865 /* 2866 *********************************************************************************** 2867 ** Determining Block Sizes for Base Address Registers 2868 ** The required address size and type can be determined by writing ones to a base address register and 2869 ** reading from the registers. By scanning the returned value from the least-significant bit of the base 2870 ** address registers upwards, the programmer can determine the required address space size. The 2871 ** binary-weighted value of the first non-zero bit found indicates the required amount of space. 2872 ** Table 105 describes the relationship between the values read back and the byte sizes the base 2873 ** address register requires. 2874 ** As an example, assume that FFFF.FFFFH is written to the ATU Inbound Base Address Register 0 2875 ** (IABAR0) and the value read back is FFF0.0008H. Bit zero is a zero, so the device requires 2876 ** memory address space. Bit three is one, so the memory does supports prefetching. Scanning 2877 ** upwards starting at bit four, bit twenty is the first one bit found. The binary-weighted value of this 2878 ** bit is 1,048,576, indicated that the device requires 1 Mbyte of memory space. 2879 ** The ATU Base Address Registers and the Expansion ROM Base Address Register use their 2880 ** associated limit registers to enable which bits within the base address register are read/write and 2881 ** which bits are read only (0). This allows the programming of these registers in a manner similar to 2882 ** other PCI devices even though the limit is variable. 2883 ** Table 105. Memory Block Size Read Response 2884 ** Response After Writing all 1s 2885 ** to the Base Address Register 2886 ** Size 2887 ** (Bytes) 2888 ** Response After Writing all 1s 2889 ** to the Base Address Register 2890 ** Size 2891 ** (Bytes) 2892 ** FFFFFFF0H 16 FFF00000H 1 M 2893 ** FFFFFFE0H 32 FFE00000H 2 M 2894 ** FFFFFFC0H 64 FFC00000H 4 M 2895 ** FFFFFF80H 128 FF800000H 8 M 2896 ** FFFFFF00H 256 FF000000H 16 M 2897 ** FFFFFE00H 512 FE000000H 32 M 2898 ** FFFFFC00H 1K FC000000H 64 M 2899 ** FFFFF800H 2K F8000000H 128 M 2900 ** FFFFF000H 4K F0000000H 256 M 2901 ** FFFFE000H 8K E0000000H 512 M 2902 ** FFFFC000H 16K C0000000H 1 G 2903 ** FFFF8000H 32K 80000000H 2 G 2904 ** FFFF0000H 64K 2905 ** 00000000H 2906 ** Register not 2907 ** imple-mented, 2908 ** no 2909 ** address 2910 ** space 2911 ** required. 2912 ** FFFE0000H 128K 2913 ** FFFC0000H 256K 2914 ** FFF80000H 512K 2915 ** 2916 *************************************************************************************** 2917 */ 2918 2919 2920 2921 /* 2922 *********************************************************************************** 2923 ** ATU Interrupt Line Register - ATUILR 2924 ** ----------------------------------------------------------------- 2925 ** Bit Default Description 2926 ** 07:00 FFH Interrupt Assigned - system-assigned value identifies which system interrupt controller��s interrupt 2927 ** request line connects to the device's PCI interrupt request lines 2928 ** (as specified in the interrupt pin register). 2929 ** A value of FFH signifies ��no connection�� or ��unknown��. 2930 *********************************************************************************** 2931 */ 2932 #define ARCMSR_ATU_INTERRUPT_LINE_REG 0x3C /*byte*/ 2933 /* 2934 *********************************************************************************** 2935 ** ATU Interrupt Pin Register - ATUIPR 2936 ** ----------------------------------------------------------------- 2937 ** Bit Default Description 2938 ** 07:00 01H Interrupt Used - A value of 01H signifies that the ATU interface unit uses INTA# as the interrupt pin. 2939 *********************************************************************************** 2940 */ 2941 #define ARCMSR_ATU_INTERRUPT_PIN_REG 0x3D /*byte*/ 2942 /* 2943 *********************************************************************************** 2944 ** ATU Minimum Grant Register - ATUMGNT 2945 ** ----------------------------------------------------------------- 2946 ** Bit Default Description 2947 ** 07:00 80H This register specifies how long a burst period the device needs in increments of 8 PCI clocks. 2948 *********************************************************************************** 2949 */ 2950 #define ARCMSR_ATU_MINIMUM_GRANT_REG 0x3E /*byte*/ 2951 /* 2952 *********************************************************************************** 2953 ** ATU Maximum Latency Register - ATUMLAT 2954 ** ----------------------------------------------------------------- 2955 ** Bit Default Description 2956 ** 07:00 00H Specifies frequency (how often) the device needs to access the PCI bus 2957 ** in increments of 8 PCI clocks. A zero value indicates the device has no stringent requirement. 2958 *********************************************************************************** 2959 */ 2960 #define ARCMSR_ATU_MAXIMUM_LATENCY_REG 0x3F /*byte*/ 2961 /* 2962 *********************************************************************************** 2963 ** Inbound Address Translation 2964 ** 2965 ** The ATU allows external PCI bus initiators to directly access the internal bus. 2966 ** These PCI bus initiators can read or write 80331 memory-mapped registers or 80331 local memory space. 2967 ** The process of inbound address translation involves two steps: 2968 ** 1. Address Detection. 2969 ** �E Determine when the 32-bit PCI address (64-bit PCI address during DACs) is 2970 ** within the address windows defined for the inbound ATU. 2971 ** �E Claim the PCI transaction with medium DEVSEL# timing in the conventional PCI 2972 ** mode and with Decode A DEVSEL# timing in the PCI-X mode. 2973 ** 2. Address Translation. 2974 ** �E Translate the 32-bit PCI address (lower 32-bit PCI address during DACs) to a 32-bit 80331 internal bus address. 2975 ** The ATU uses the following registers in inbound address window 0 translation: 2976 ** �E Inbound ATU Base Address Register 0 2977 ** �E Inbound ATU Limit Register 0 2978 ** �E Inbound ATU Translate Value Register 0 2979 ** The ATU uses the following registers in inbound address window 2 translation: 2980 ** �E Inbound ATU Base Address Register 2 2981 ** �E Inbound ATU Limit Register 2 2982 ** �E Inbound ATU Translate Value Register 2 2983 ** The ATU uses the following registers in inbound address window 3 translation: 2984 ** �E Inbound ATU Base Address Register 3 2985 ** �E Inbound ATU Limit Register 3 2986 ** �E Inbound ATU Translate Value Register 3 2987 ** Note: Inbound Address window 1 is not a translate window. 2988 ** Instead, window 1 may be used to allocate host memory for Private Devices. 2989 ** Inbound Address window 3 does not reside in the standard section of the configuration header (offsets 00H - 3CH), 2990 ** thus the host BIOS does not configure window 3. 2991 ** Window 3 is intended to be used as a special window into local memory for private PCI 2992 ** agents controlled by the 80331 in conjunction with the Private Memory Space of the bridge. 2993 ** PCI-to-PCI Bridge in 80331 or 2994 ** Inbound address detection is determined from the 32-bit PCI address, 2995 ** (64-bit PCI address during DACs) the base address register and the limit register. 2996 ** In the case of DACs none of the upper 32-bits of the address is masked during address comparison. 2997 ** 2998 ** The algorithm for detection is: 2999 ** 3000 ** Equation 1. Inbound Address Detection 3001 ** When (PCI_Address [31:0] & Limit_Register[31:0]) == (Base_Register[31:0] & PCI_Address [63:32]) == Base_Register[63:32] (for DACs only) 3002 ** the PCI Address is claimed by the Inbound ATU. 3003 ** 3004 ** The incoming 32-bit PCI address (lower 32-bits of the address in case of DACs) is bitwise ANDed 3005 ** with the associated inbound limit register. 3006 ** When the result matches the base register (and upper base address matches upper PCI address in case of DACs), 3007 ** the inbound PCI address is detected as being within the inbound translation window and is claimed by the ATU. 3008 ** 3009 ** Note: The first 4 Kbytes of the ATU inbound address translation window 0 are reserved for the Messaging Unit. 3010 ** Once the transaction is claimed, the address must be translated from a PCI address to a 32-bit 3011 ** internal bus address. In case of DACs upper 32-bits of the address is simply discarded and only the 3012 ** lower 32-bits are used during address translation. 3013 ** The algorithm is: 3014 ** 3015 ** 3016 ** Equation 2. Inbound Translation 3017 ** Intel I/O processor Internal Bus Address=(PCI_Address[31:0] & ~Limit_Register[31:0]) | ATU_Translate_Value_Register[31:0]. 3018 ** 3019 ** The incoming 32-bit PCI address (lower 32-bits in case of DACs) is first bitwise ANDed with the 3020 ** bitwise inverse of the limit register. This result is bitwise ORed with the ATU Translate Value and 3021 ** the result is the internal bus address. This translation mechanism is used for all inbound memory 3022 ** read and write commands excluding inbound configuration read and writes. 3023 ** In the PCI mode for inbound memory transactions, the only burst order supported is Linear 3024 ** Incrementing. For any other burst order, the ATU signals a Disconnect after the first data phase. 3025 ** The PCI-X supports linear incrementing only, and hence above situation is not encountered in the PCI-X mode. 3026 ** example: 3027 ** Register Values 3028 ** Base_Register=3A00 0000H 3029 ** Limit_Register=FF80 0000H (8 Mbyte limit value) 3030 ** Value_Register=B100 0000H 3031 ** Inbound Translation Window ranges from 3A00 0000H to 3A7F FFFFH (8 Mbytes) 3032 ** 3033 ** Address Detection (32-bit address) 3034 ** 3035 ** PCI_Address & Limit_Register == Base_Register 3036 ** 3A45 012CH & FF80 0000H == 3A00 0000H 3037 ** 3038 ** ANS: PCI_Address is in the Inbound Translation Window 3039 ** Address Translation (to get internal bus address) 3040 ** 3041 ** IB_Address=(PCI_Address & ~Limit_Register) | Value_Reg 3042 ** IB_Address=(3A45 012CH & 007F FFFFH) | B100 0000H 3043 ** 3044 ** ANS:IB_Address=B145 012CH 3045 *********************************************************************************** 3046 */ 3047 3048 3049 3050 /* 3051 *********************************************************************************** 3052 ** Inbound ATU Limit Register 0 - IALR0 3053 ** 3054 ** Inbound address translation for memory window 0 occurs for data transfers occurring from the PCI 3055 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 3056 ** PCI addresses to internal bus addresses. 3057 ** The 80331 translate value register��s programmed value must be naturally aligned with the base 3058 ** address register��s programmed value. The limit register is used as a mask; thus, the lower address 3059 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 3060 ** Specification, Revision 2.3 for additional information on programming base address registers. 3061 ** Bits 31 to 12 within the IALR0 have a direct effect on the IABAR0 register, bits 31 to 12, with a 3062 ** one to one correspondence. A value of 0 in a bit within the IALR0 makes the corresponding bit 3063 ** within the IABAR0 a read only bit which always returns 0. A value of 1 in a bit within the IALR0 3064 ** makes the corresponding bit within the IABAR0 read/write from PCI. Note that a consequence of 3065 ** this programming scheme is that unless a valid value exists within the IALR0, all writes to the 3066 ** IABAR0 has no effect since a value of all zeros within the IALR0 makes the IABAR0 a read only register. 3067 ** ----------------------------------------------------------------- 3068 ** Bit Default Description 3069 ** 31:12 FF000H Inbound Translation Limit 0 - This readback value determines the memory block size required for 3070 ** inbound memory window 0 of the address translation unit. This defaults to an inbound window of 16MB. 3071 ** 11:00 000H Reserved 3072 *********************************************************************************** 3073 */ 3074 #define ARCMSR_INBOUND_ATU_LIMIT0_REG 0x40 /*dword 0x43,0x42,0x41,0x40*/ 3075 /* 3076 *********************************************************************************** 3077 ** Inbound ATU Translate Value Register 0 - IATVR0 3078 ** 3079 ** The Inbound ATU Translate Value Register 0 (IATVR0) contains the internal bus address used to 3080 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 3081 ** inbound ATU address translation. 3082 ** ----------------------------------------------------------------- 3083 ** Bit Default Description 3084 ** 31:12 FF000H Inbound ATU Translation Value 0 - This value is used to convert the PCI address to internal bus addresses. 3085 ** This value must be 64-bit aligned on the internal bus. 3086 ** The default address allows the ATU to access the internal 80331 memory-mapped registers. 3087 ** 11:00 000H Reserved 3088 *********************************************************************************** 3089 */ 3090 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE0_REG 0x44 /*dword 0x47,0x46,0x45,0x44*/ 3091 /* 3092 *********************************************************************************** 3093 ** Expansion ROM Limit Register - ERLR 3094 ** 3095 ** The Expansion ROM Limit Register (ERLR) defines the block size of addresses the ATU defines 3096 ** as Expansion ROM address space. The block size is programmed by writing a value into the ERLR. 3097 ** Bits 31 to 12 within the ERLR have a direct effect on the ERBAR register, bits 31 to 12, with a one 3098 ** to one correspondence. A value of 0 in a bit within the ERLR makes the corresponding bit within 3099 ** the ERBAR a read only bit which always returns 0. A value of 1 in a bit within the ERLR makes 3100 ** the corresponding bit within the ERBAR read/write from PCI. 3101 ** ----------------------------------------------------------------- 3102 ** Bit Default Description 3103 ** 31:12 000000H Expansion ROM Limit - Block size of memory required for the Expansion ROM translation unit. Default 3104 ** value is 0, which indicates no Expansion ROM address space and all bits within the ERBAR are read only with a value of 0. 3105 ** 11:00 000H Reserved. 3106 *********************************************************************************** 3107 */ 3108 #define ARCMSR_EXPANSION_ROM_LIMIT_REG 0x48 /*dword 0x4B,0x4A,0x49,0x48*/ 3109 /* 3110 *********************************************************************************** 3111 ** Expansion ROM Translate Value Register - ERTVR 3112 ** 3113 ** The Expansion ROM Translate Value Register contains the 80331 internal bus address which the 3114 ** ATU converts the PCI bus access. This address is driven on the internal bus as a result of the 3115 ** Expansion ROM address translation. 3116 ** ----------------------------------------------------------------- 3117 ** Bit Default Description 3118 ** 31:12 00000H Expansion ROM Translation Value - Used to convert PCI addresses to 80331 internal bus addresses 3119 ** for Expansion ROM accesses. The Expansion ROM address translation value must be word aligned on the internal bus. 3120 ** 11:00 000H Reserved 3121 *********************************************************************************** 3122 */ 3123 #define ARCMSR_EXPANSION_ROM_TRANSLATE_VALUE_REG 0x4C /*dword 0x4F,0x4E,0x4D,0x4C*/ 3124 /* 3125 *********************************************************************************** 3126 ** Inbound ATU Limit Register 1 - IALR1 3127 ** 3128 ** Bits 31 to 12 within the IALR1 have a direct effect on the IABAR1 register, bits 31 to 12, with a 3129 ** one to one correspondence. A value of 0 in a bit within the IALR1 makes the corresponding bit 3130 ** within the IABAR1 a read only bit which always returns 0. A value of 1 in a bit within the IALR1 3131 ** makes the corresponding bit within the IABAR1 read/write from PCI. Note that a consequence of 3132 ** this programming scheme is that unless a valid value exists within the IALR1, all writes to the 3133 ** IABAR1 has no effect since a value of all zeros within the IALR1 makes the IABAR1 a read only 3134 ** register. 3135 ** The inbound memory window 1 is used merely to allocate memory on the PCI bus. The ATU does 3136 ** not process any PCI bus transactions to this memory range. 3137 ** Warning: The ATU does not claim any PCI accesses that fall within the range defined by IABAR1, 3138 ** IAUBAR1, and IALR1. 3139 ** ----------------------------------------------------------------- 3140 ** Bit Default Description 3141 ** 31:12 00000H Inbound Translation Limit 1 - This readback value determines the memory block size 3142 ** required for the ATUs memory window 1. 3143 ** 11:00 000H Reserved 3144 *********************************************************************************** 3145 */ 3146 #define ARCMSR_INBOUND_ATU_LIMIT1_REG 0x50 /*dword 0x53,0x52,0x51,0x50*/ 3147 /* 3148 *********************************************************************************** 3149 ** Inbound ATU Limit Register 2 - IALR2 3150 ** 3151 ** Inbound address translation for memory window 2 occurs for data transfers occurring from the PCI 3152 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 3153 ** PCI addresses to internal bus addresses. 3154 ** The inbound translation base address for inbound window 2 is specified in Section 3.10.15. When 3155 ** determining block size requirements �X as described in Section 3.10.21 �X the translation limit 3156 ** register provides the block size requirements for the base address register. The remaining registers 3157 ** used for performing address translation are discussed in Section 3.2.1.1. 3158 ** The 80331 translate value register��s programmed value must be naturally aligned with the base 3159 ** address register��s programmed value. The limit register is used as a mask; thus, the lower address 3160 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 3161 ** Specification, Revision 2.3 for additional information on programming base address registers. 3162 ** Bits 31 to 12 within the IALR2 have a direct effect on the IABAR2 register, bits 31 to 12, with a 3163 ** one to one correspondence. A value of 0 in a bit within the IALR2 makes the corresponding bit 3164 ** within the IABAR2 a read only bit which always returns 0. A value of 1 in a bit within the IALR2 3165 ** makes the corresponding bit within the IABAR2 read/write from PCI. Note that a consequence of 3166 ** this programming scheme is that unless a valid value exists within the IALR2, all writes to the 3167 ** IABAR2 has no effect since a value of all zeros within the IALR2 makes the IABAR2 a read only 3168 ** register. 3169 ** ----------------------------------------------------------------- 3170 ** Bit Default Description 3171 ** 31:12 00000H Inbound Translation Limit 2 - This readback value determines the memory block size 3172 ** required for the ATUs memory window 2. 3173 ** 11:00 000H Reserved 3174 *********************************************************************************** 3175 */ 3176 #define ARCMSR_INBOUND_ATU_LIMIT2_REG 0x54 /*dword 0x57,0x56,0x55,0x54*/ 3177 /* 3178 *********************************************************************************** 3179 ** Inbound ATU Translate Value Register 2 - IATVR2 3180 ** 3181 ** The Inbound ATU Translate Value Register 2 (IATVR2) contains the internal bus address used to 3182 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 3183 ** inbound ATU address translation. 3184 ** ----------------------------------------------------------------- 3185 ** Bit Default Description 3186 ** 31:12 00000H Inbound ATU Translation Value 2 - This value is used to convert the PCI address to internal bus addresses. 3187 ** This value must be 64-bit aligned on the internal bus. 3188 ** The default address allows the ATU to access the internal 80331 ** ** memory-mapped registers. 3189 ** 11:00 000H Reserved 3190 *********************************************************************************** 3191 */ 3192 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE2_REG 0x58 /*dword 0x5B,0x5A,0x59,0x58*/ 3193 /* 3194 *********************************************************************************** 3195 ** Outbound I/O Window Translate Value Register - OIOWTVR 3196 ** 3197 ** The Outbound I/O Window Translate Value Register (OIOWTVR) contains the PCI I/O address 3198 ** used to convert the internal bus access to a PCI address. This address is driven on the PCI bus as a 3199 ** result of the outbound ATU address translation. 3200 ** The I/O window is from 80331 internal bus address 9000 000H to 9000 FFFFH with the fixed 3201 ** length of 64 Kbytes. 3202 ** ----------------------------------------------------------------- 3203 ** Bit Default Description 3204 ** 31:16 0000H Outbound I/O Window Translate Value - Used to convert internal bus addresses to PCI addresses. 3205 ** 15:00 0000H Reserved 3206 *********************************************************************************** 3207 */ 3208 #define ARCMSR_OUTBOUND_IO_WINDOW_TRANSLATE_VALUE_REG 0x5C /*dword 0x5F,0x5E,0x5D,0x5C*/ 3209 /* 3210 *********************************************************************************** 3211 ** Outbound Memory Window Translate Value Register 0 -OMWTVR0 3212 ** 3213 ** The Outbound Memory Window Translate Value Register 0 (OMWTVR0) contains the PCI 3214 ** address used to convert 80331 internal bus addresses for outbound transactions. This address is 3215 ** driven on the PCI bus as a result of the outbound ATU address translation. 3216 ** The memory window is from internal bus address 8000 000H to 83FF FFFFH with the fixed length 3217 ** of 64 Mbytes. 3218 ** ----------------------------------------------------------------- 3219 ** Bit Default Description 3220 ** 31:26 00H Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses. 3221 ** 25:02 00 0000H Reserved 3222 ** 01:00 00 2 Burst Order - This bit field shows the address sequence during a memory burst. 3223 ** Only linear incrementing mode is supported. 3224 *********************************************************************************** 3225 */ 3226 #define ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x60 /*dword 0x63,0x62,0x61,0x60*/ 3227 /* 3228 *********************************************************************************** 3229 ** Outbound Upper 32-bit Memory Window Translate Value Register 0 - OUMWTVR0 3230 ** 3231 ** The Outbound Upper 32-bit Memory Window Translate Value Register 0 (OUMWTVR0) defines 3232 ** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to 3233 ** directly address anywhere within the 64-bit host address space. When this register is all-zero, then 3234 ** a SAC is generated on the PCI bus. 3235 ** The memory window is from internal bus address 8000 000H to 83FF FFFFH with the fixed 3236 ** length of 64 Mbytes. 3237 ** ----------------------------------------------------------------- 3238 ** Bit Default Description 3239 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 3240 *********************************************************************************** 3241 */ 3242 #define ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x64 /*dword 0x67,0x66,0x65,0x64*/ 3243 /* 3244 *********************************************************************************** 3245 ** Outbound Memory Window Translate Value Register 1 -OMWTVR1 3246 ** 3247 ** The Outbound Memory Window Translate Value Register 1 (OMWTVR1) contains the PCI 3248 ** address used to convert 80331 internal bus addresses for outbound transactions. This address is 3249 ** driven on the PCI bus as a result of the outbound ATU address translation. 3250 ** The memory window is from internal bus address 8400 000H to 87FF FFFFH with the fixed length 3251 ** of 64 Mbytes. 3252 ** ----------------------------------------------------------------- 3253 ** Bit Default Description 3254 ** 31:26 00H Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses. 3255 ** 25:02 00 0000H Reserved 3256 ** 01:00 00 2 Burst Order - This bit field shows the address sequence during a memory burst. 3257 ** Only linear incrementing mode is supported. 3258 *********************************************************************************** 3259 */ 3260 #define ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x68 /*dword 0x6B,0x6A,0x69,0x68*/ 3261 /* 3262 *********************************************************************************** 3263 ** Outbound Upper 32-bit Memory Window Translate Value Register 1 - OUMWTVR1 3264 ** 3265 ** The Outbound Upper 32-bit Memory Window Translate Value Register 1 (OUMWTVR1) defines 3266 ** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to 3267 ** directly address anywhere within the 64-bit host address space. When this register is all-zero, then 3268 ** a SAC is generated on the PCI bus. 3269 ** The memory window is from internal bus address 8400 000H to 87FF FFFFH with the fixed length 3270 ** of 64 Mbytes. 3271 ** ----------------------------------------------------------------- 3272 ** Bit Default Description 3273 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 3274 *********************************************************************************** 3275 */ 3276 #define ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x6C /*dword 0x6F,0x6E,0x6D,0x6C*/ 3277 /* 3278 *********************************************************************************** 3279 ** Outbound Upper 32-bit Direct Window Translate Value Register - OUDWTVR 3280 ** 3281 ** The Outbound Upper 32-bit Direct Window Translate Value Register (OUDWTVR) defines the 3282 ** upper 32-bits of address used during a dual address cycle for the transactions via Direct Addressing 3283 ** Window. This enables the outbound ATU to directly address anywhere within the 64-bit host 3284 ** address space. When this register is all-zero, then a SAC is generated on the PCI bus. 3285 ** ----------------------------------------------------------------- 3286 ** Bit Default Description 3287 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 3288 *********************************************************************************** 3289 */ 3290 #define ARCMSR_OUTBOUND_UPPER32_DIRECT_WINDOW_TRANSLATE_VALUE_REG 0x78 /*dword 0x7B,0x7A,0x79,0x78*/ 3291 /* 3292 *********************************************************************************** 3293 ** ATU Configuration Register - ATUCR 3294 ** 3295 ** The ATU Configuration Register controls the outbound address translation for address translation 3296 ** unit. It also contains bits for Conventional PCI Delayed Read Command (DRC) aliasing, discard 3297 ** timer status, SERR# manual assertion, SERR# detection interrupt masking, and ATU BIST 3298 ** interrupt enabling. 3299 ** ----------------------------------------------------------------- 3300 ** Bit Default Description 3301 ** 31:20 00H Reserved 3302 ** 19 0 2 ATU DRC Alias - when set, the ATU does not distinguish read commands when attempting to match a 3303 ** current PCI read transaction with read data enqueued within the DRC buffer. When clear, a current read 3304 ** transaction must have the exact same read command as the DRR for the ATU to deliver DRC data. Not 3305 ** applicable in the PCI-X mode. 3306 ** 18 0 2 Direct Addressing Upper 2Gbytes Translation Enable - When set, 3307 ** with Direct Addressing enabled (bit 7 of the ATUCR set), 3308 ** the ATU forwards internal bus cycles with an address between 0000.0040H and 3309 ** 7FFF.FFFFH to the PCI bus with bit 31 of the address set (8000.0000H - FFFF.FFFFH). 3310 ** When clear, no translation occurs. 3311 ** 17 0 2 Reserved 3312 ** 16 0 2 SERR# Manual Assertion - when set, the ATU asserts SERR# for one clock on the PCI interface. Until 3313 ** cleared, SERR# may not be manually asserted again. Once cleared, operation proceeds as specified. 3314 ** 15 0 2 ATU Discard Timer Status - when set, one of the 4 discard timers within the ATU has expired and 3315 ** discarded the delayed completion transaction within the queue. When clear, no timer has expired. 3316 ** 14:10 00000 2 Reserved 3317 ** 09 0 2 SERR# Detected Interrupt Enable - When set, the Intel XScale core is signalled an HPI# interrupt 3318 ** when the ATU detects that SERR# was asserted. When clear, 3319 ** the Intel XScale core is not interrupted when SERR# is detected. 3320 ** 08 0 2 Direct Addressing Enable - Setting this bit enables direct outbound addressing through the ATU. 3321 ** Internal bus cycles with an address between 0000.0040H and 7FFF.FFFFH automatically forwards to 3322 ** the PCI bus with or without translation of address bit 31 based on the setting of bit 18 of 3323 ** the ATUCR. 3324 ** 07:04 0000 2 Reserved 3325 ** 03 0 2 ATU BIST Interrupt Enable - When set, enables an interrupt to the Intel XScale core when the start 3326 ** BIST bit is set in the ATUBISTR register. This bit is also reflected as the BIST Capable bit 7 3327 ** in the ATUBISTR register. 3328 ** 02 0 2 Reserved 3329 ** 01 0 2 Outbound ATU Enable - When set, enables the outbound address translation unit. 3330 ** When cleared, disables the outbound ATU. 3331 ** 00 0 2 Reserved 3332 *********************************************************************************** 3333 */ 3334 #define ARCMSR_ATU_CONFIGURATION_REG 0x80 /*dword 0x83,0x82,0x81,0x80*/ 3335 /* 3336 *********************************************************************************** 3337 ** PCI Configuration and Status Register - PCSR 3338 ** 3339 ** The PCI Configuration and Status Register has additional bits for controlling and monitoring 3340 ** various features of the PCI bus interface. 3341 ** ----------------------------------------------------------------- 3342 ** Bit Default Description 3343 ** 31:19 0000H Reserved 3344 ** 18 0 2 Detected Address or Attribute Parity Error - set when a parity error is detected during either the address 3345 ** or attribute phase of a transaction on the PCI bus even when the ATUCMD register Parity Error 3346 ** Response bit is cleared. Set under the following conditions: 3347 ** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus (including one generated by the ATU). 3348 ** 17:16 Varies with 3349 ** external state 3350 ** of DEVSEL#, 3351 ** STOP#, and 3352 ** TRDY#, 3353 ** during 3354 ** P_RST# 3355 ** PCI-X capability - These two bits define the mode of 3356 ** the PCI bus (conventional or PCI-X) as well as the 3357 ** operating frequency in the case of PCI-X mode. 3358 ** 00 - Conventional PCI mode 3359 ** 01 - PCI-X 66 3360 ** 10 - PCI-X 100 3361 ** 11 - PCI-X 133 3362 ** As defined by the PCI-X Addendum to the PCI Local Bus Specification, 3363 ** Revision 1.0a, the operating 3364 ** mode is determined by an initialization pattern on the PCI bus during 3365 ** P_RST# assertion: 3366 ** DEVSEL# STOP# TRDY# Mode 3367 ** Deasserted Deasserted Deasserted Conventional 3368 ** Deasserted Deasserted Asserted PCI-X 66 3369 ** Deasserted Asserted Deasserted PCI-X 100 3370 ** Deasserted Asserted Asserted PCI-X 133 3371 ** All other patterns are reserved. 3372 ** 15 0 2 3373 ** Outbound Transaction Queue Busy: 3374 ** 0=Outbound Transaction Queue Empty 3375 ** 1=Outbound Transaction Queue Busy 3376 ** 14 0 2 3377 ** Inbound Transaction Queue Busy: 3378 ** 0=Inbound Transaction Queue Empty 3379 ** 1=Inbound Transaction Queue Busy 3380 ** 13 0 2 Reserved. 3381 ** 12 0 2 Discard Timer Value - This bit controls the time-out value 3382 ** for the four discard timers attached to the queues holding read data. 3383 ** A value of 0 indicates the time-out value is 2 15 clocks. 3384 ** A value of 1 indicates the time-out value is 2 10 clocks. 3385 ** 11 0 2 Reserved. 3386 ** 10 Varies with 3387 ** external state 3388 ** of M66EN 3389 ** during 3390 ** P_RST# 3391 ** Bus Operating at 66 MHz - When set, the interface has been initialized to function at 66 MHz in 3392 ** Conventional PCI mode by the assertion of M66EN during bus initialization. 3393 ** When clear, the interface 3394 ** has been initialized as a 33 MHz bus. 3395 ** NOTE: When PCSR bits 17:16 are not equal to zero, then this bit is meaningless since the 80331 is operating in PCI-X mode. 3396 ** 09 0 2 Reserved 3397 ** 08 Varies with 3398 ** external state 3399 ** of REQ64# 3400 ** during 3401 ** P_RST# 3402 ** PCI Bus 64-Bit Capable - When clear, the PCI bus interface has been 3403 ** configured as 64-bit capable by 3404 ** the assertion of REQ64# on the rising edge of P_RST#. When set, 3405 ** the PCI interface is configured as 3406 ** 32-bit only. 3407 ** 07:06 00 2 Reserved. 3408 ** 05 0 2 Reset Internal Bus - This bit controls the reset of the Intel XScale core 3409 ** and all units on the internal 3410 ** bus. In addition to the internal bus initialization, 3411 ** this bit triggers the assertion of the M_RST# pin for 3412 ** initialization of registered DIMMs. When set: 3413 ** When operating in the conventional PCI mode: 3414 ** �E All current PCI transactions being mastered by the ATU completes, 3415 ** and the ATU master interfaces 3416 ** proceeds to an idle state. No additional transactions is mastered by these units 3417 ** until the internal bus reset is complete. 3418 ** �E All current transactions being slaved by the ATU on either the PCI bus 3419 ** or the internal bus 3420 ** completes, and the ATU target interfaces proceeds to an idle state. 3421 ** All future slave transactions master aborts, 3422 ** with the exception of the completion cycle for the transaction that set the Reset 3423 ** Internal Bus bit in the PCSR. 3424 ** �E When the value of the Core Processor Reset bit in the PCSR (upon P_RST# assertion) 3425 ** is set, the Intel XScale core is held in reset when the internal bus reset is complete. 3426 ** �E The ATU ignores configuration cycles, and they appears as master aborts for: 32 3427 ** Internal Bus clocks. 3428 ** �E The 80331 hardware clears this bit after the reset operation completes. 3429 ** When operating in the PCI-X mode: 3430 ** The ATU hardware responds the same as in Conventional PCI-X mode. 3431 ** However, this may create a problem in PCI-X mode for split requests in 3432 ** that there may still be an outstanding split completion that the 3433 ** ATU is either waiting to receive (Outbound Request) or initiate 3434 ** (Inbound Read Request). For a cleaner 3435 ** internal bus reset, host software can take the following steps prior 3436 ** to asserting Reset Internal bus: 3437 ** 1. Clear the Bus Master (bit 2 of the ATUCMD) and the Memory Enable (bit 1 of the ATUCMD) bits in 3438 ** the ATUCMD. This ensures that no new transactions, either outbound or inbound are enqueued. 3439 ** 2. Wait for both the Outbound (bit 15 of the PCSR) and Inbound Read (bit 14 of the PCSR) Transaction 3440 ** queue busy bits to be clear. 3441 ** 3. Set the Reset Internal Bus bit 3442 ** As a result, the ATU hardware resets the internal bus using the same logic as in conventional mode, 3443 ** however the user is now assured that the ATU no longer has any pending inbound or outbound split 3444 ** completion transactions. 3445 ** NOTE: Since the Reset Internal Bus bit is set using an inbound configuration cycle, the user is 3446 ** guaranteed that any prior configuration cycles have properly completed since there is only a one 3447 ** deep transaction queue for configuration transaction requests. The ATU sends the appropriate 3448 ** Split Write Completion Message to the Requester prior to the onset of Internal Bus Reset. 3449 ** 04 0 2 Bus Master Indicator Enable: Provides software control for the 3450 ** Bus Master Indicator signal P_BMI used 3451 ** for external RAIDIOS logic control of private devices. Only valid when operating with the bridge and 3452 ** central resource/arbiter disabled (BRG_EN =low, ARB_EN=low). 3453 ** 03 Varies with external state of PRIVDEV during 3454 ** P_RST# 3455 ** Private Device Enable - This bit indicates the state of the reset strap which enables the private device 3456 ** control mechanism within the PCI-to-PCI Bridge SISR configuration register. 3457 ** 0=Private Device control Disabled - SISR register bits default to zero 3458 ** 1=Private Device control Enabled - SISR register bits default to one 3459 ** 02 Varies with external state of RETRY during P_RST# 3460 ** Configuration Cycle Retry - When this bit is set, the PCI interface of the 80331 responds to all 3461 ** configuration cycles with a Retry condition. When clear, the 80331 responds to the appropriate 3462 ** configuration cycles. 3463 ** The default condition for this bit is based on the external state of the RETRY pin at the rising edge of 3464 ** P_RST#. When the external state of the pin is high, the bit is set. When the external state of the pin is 3465 ** low, the bit is cleared. 3466 ** 01 Varies with external state of CORE_RST# during P_RST# 3467 ** Core Processor Reset - This bit is set to its default value by the hardware when either P_RST# is 3468 ** asserted or the Reset Internal Bus bit in PCSR is set. When this bit is set, the Intel XScale core is 3469 ** being held in reset. Software cannot set this bit. Software is required to clear this bit to deassert Intel 3470 ** XScale core reset. 3471 ** The default condition for this bit is based on the external state of the CORE_RST# pin at the rising edge 3472 ** of P_RST#. When the external state of the pin is low, the bit is set. When the external state of the pin is 3473 ** high, the bit is clear. 3474 ** 00 Varies with external state of PRIVMEM during P_RST# 3475 ** Private Memory Enable - This bit indicates the state of the reset strap which enables the private device 3476 ** control mechanism within the PCI-to-PCI Bridge SDER configuration register. 3477 ** 0=Private Memory control Disabled - SDER register bit 2 default to zero 3478 ** 1=Private Memory control Enabled - SDER register bits 2 default to one 3479 *********************************************************************************** 3480 */ 3481 #define ARCMSR_PCI_CONFIGURATION_STATUS_REG 0x84 /*dword 0x87,0x86,0x85,0x84*/ 3482 /* 3483 *********************************************************************************** 3484 ** ATU Interrupt Status Register - ATUISR 3485 ** 3486 ** The ATU Interrupt Status Register is used to notify the core processor of the source of an ATU 3487 ** interrupt. In addition, this register is written to clear the source of the interrupt to the interrupt unit 3488 ** of the 80331. All bits in this register are Read/Clear. 3489 ** Bits 4:0 are a direct reflection of bits 14:11 and bit 8 (respectively) of the ATU Status Register 3490 ** (these bits are set at the same time by hardware but need to be cleared independently). Bit 7 is set 3491 ** by an error associated with the internal bus of the 80331. Bit 8 is for software BIST. The 3492 ** conditions that result in an ATU interrupt are cleared by writing a 1 to the appropriate bits in this 3493 ** register. 3494 ** Note: Bits 4:0, and bits 15 and 13:7 can result in an interrupt being driven to the Intel XScale core. 3495 ** ----------------------------------------------------------------- 3496 ** Bit Default Description 3497 ** 31:18 0000H Reserved 3498 ** 17 0 2 VPD Address Register Updated - This bit is set when a PCI bus configuration write occurs to the VPDAR 3499 ** register. Configuration register writes to the VPDAR does NOT result in bit 15 also being set. When set, 3500 ** this bit results in the assertion of the ATU Configure Register Write Interrupt. 3501 ** 16 0 2 Reserved 3502 ** 15 0 2 ATU Configuration Write - This bit is set when a PCI bus configuration write occurs to any ATU register. 3503 ** When set, this bit results in the assertion of the ATU Configure Register Write Interrupt. 3504 ** 14 0 2 ATU Inbound Memory Window 1 Base Updated - This bit is set when a PCI bus configuration write 3505 ** occurs to either the IABAR1 register or the IAUBAR1 register. Configuration register writes to these 3506 ** registers deos NOT result in bit 15 also being set. When set, this bit results in the assertion of the ATU 3507 ** Configure Register Write Interrupt. 3508 ** 13 0 2 Initiated Split Completion Error Message - This bit is set when the device initiates a Split Completion 3509 ** Message on the PCI Bus with the Split Completion Error attribute bit set. 3510 ** 12 0 2 Received Split Completion Error Message - This bit is set when the device receives a Split Completion 3511 ** Message from the PCI Bus with the Split Completion Error attribute bit set. 3512 ** 11 0 2 Power State Transition - When the Power State Field of the ATU Power Management Control/Status 3513 ** Register is written to transition the ATU function Power State from D0 to D3, D0 to D1, or D3 to D0 and 3514 ** the ATU Power State Transition Interrupt mask bit is cleared, this bit is set. 3515 ** 10 0 2 P_SERR# Asserted - set when P_SERR# is asserted on the PCI bus by the ATU. 3516 ** 09 0 2 Detected Parity Error - set when a parity error is detected on the PCI bus even when the ATUCMD 3517 ** register��s Parity Error Response bit is cleared. Set under the following conditions: 3518 ** �E Write Data Parity Error when the ATU is a target (inbound write). 3519 ** �E Read Data Parity Error when the ATU is an initiator (outbound read). 3520 ** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus. 3521 ** 08 0 2 ATU BIST Interrupt - When set, generates the ATU BIST Start Interrupt and indicates the host processor 3522 ** has set the Start BIST bit (ATUBISTR register bit 6), when the ATU BIST interrupt is enabled (ATUCR 3523 ** register bit 3). The Intel XScale core can initiate the software BIST and store the result in ATUBISTR 3524 ** register bits 3:0. 3525 ** Configuration register writes to the ATUBISTR does NOT result in bit 15 also being set or the assertion 3526 ** of the ATU Configure Register Write Interrupt. 3527 ** 07 0 2 Internal Bus Master Abort - set when a transaction initiated by the ATU internal bus initiator interface ends in a Master-abort. 3528 ** 06:05 00 2 Reserved. 3529 ** 04 0 2 P_SERR# Detected - set when P_SERR# is detected on the PCI bus by the ATU. 3530 ** 03 0 2 PCI Master Abort - set when a transaction initiated by the ATU PCI initiator interface ends in a Master-abort. 3531 ** 02 0 2 PCI Target Abort (master) - set when a transaction initiated by the ATU PCI master interface ends in a Target-abort. 3532 ** 01 0 2 PCI Target Abort (target) - set when the ATU interface, acting as a target, terminates the transaction on the PCI bus with a target abort. 3533 ** 00 0 2 PCI Master Parity Error - Master Parity Error - The ATU interface sets this bit under the following 3534 ** conditions: 3535 ** �E The ATU asserted PERR# itself or the ATU observed PERR# asserted. 3536 ** �E And the ATU acted as the requester for the operation in which the error occurred. 3537 ** �E And the ATUCMD register��s Parity Error Response bit is set 3538 ** �E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message 3539 ** �E And the ATUCMD register��s Parity Error Response bit is set 3540 *********************************************************************************** 3541 */ 3542 #define ARCMSR_ATU_INTERRUPT_STATUS_REG 0x88 /*dword 0x8B,0x8A,0x89,0x88*/ 3543 /* 3544 *********************************************************************************** 3545 ** ATU Interrupt Mask Register - ATUIMR 3546 ** 3547 ** The ATU Interrupt Mask Register contains the control bit to enable and disable interrupts 3548 ** generated by the ATU. 3549 ** ----------------------------------------------------------------- 3550 ** Bit Default Description 3551 ** 31:15 0 0000H Reserved 3552 ** 14 0 2 VPD Address Register Updated Mask - Controls the setting of bit 17 of the ATUISR and generation of the 3553 ** ATU Configuration Register Write interrupt when a PCI bus write occurs to the VPDAR register. 3554 ** 0=Not Masked 3555 ** 1=Masked 3556 ** 13 0 2 Reserved 3557 ** 12 0 2 Configuration Register Write Mask - Controls the setting of bit 15 of the ATUISR and generation of the 3558 ** ATU Configuration Register Write interrupt when a PCI bus write occurs to any ATU configuration register 3559 ** except those covered by mask bit 11 and bit 14 of this register, and ATU BIST enable bit 3 of the ATUCR. 3560 ** 0=Not Masked 3561 ** 1=Masked 3562 ** 11 1 2 ATU Inbound Memory Window 1 Base Updated Mask - Controls the setting of bit 14 of the ATUISR and 3563 ** generation of the ATU Configuration Register Write interrupt when a PCI bus write occurs to either the 3564 ** IABAR1 register or the IAUBAR1 register. 3565 ** 0=Not Masked 3566 ** 1=Masked 3567 ** 10 0 2 Initiated Split Completion Error Message Interrupt Mask - Controls the setting of bit 13 of the ATUISR and 3568 ** generation of the ATU Error interrupt when the ATU initiates a Split Completion Error Message. 3569 ** 0=Not Masked 3570 ** 1=Masked 3571 ** 09 0 2 Received Split Completion Error Message Interrupt Mask- Controls the setting of bit 12 of the ATUISR 3572 ** and generation of the ATU Error interrupt when a Split Completion Error Message results in bit 29 of the 3573 ** PCIXSR being set. 3574 ** 0=Not Masked 3575 ** 1=Masked 3576 ** 08 1 2 Power State Transition Interrupt Mask - Controls the setting of bit 12 of the ATUISR and generation of the 3577 ** ATU Error interrupt when ATU Power Management Control/Status Register is written to transition the 3578 ** ATU Function Power State from D0 to D3, D0 to D1, D1 to D3 or D3 to D0. 3579 ** 0=Not Masked 3580 ** 1=Masked 3581 ** 07 0 2 ATU Detected Parity Error Interrupt Mask - Controls the setting of bit 9 of the ATUISR and generation of 3582 ** the ATU Error interrupt when a parity error detected on the PCI bus that sets bit 15 of the ATUSR. 3583 ** 0=Not Masked 3584 ** 1=Masked 3585 ** 06 0 2 ATU SERR# Asserted Interrupt Mask - Controls the setting of bit 10 of the ATUISR and generation of the 3586 ** ATU Error interrupt when SERR# is asserted on the PCI interface resulting in bit 14 of the ATUSR being set. 3587 ** 0=Not Masked 3588 ** 1=Masked 3589 ** NOTE: This bit is specific to the ATU asserting SERR# and not detecting SERR# from another master. 3590 ** 05 0 2 ATU PCI Master Abort Interrupt Mask - Controls the setting of bit 3 of the ATUISR and generation of the 3591 ** ATU Error interrupt when a master abort error resulting in bit 13 of the ATUSR being set. 3592 ** 0=Not Masked 3593 ** 1=Masked 3594 ** 04 0 2 ATU PCI Target Abort (Master) Interrupt Mask- Controls the setting of bit 12 of the ATUISR and ATU Error 3595 ** generation of the interrupt when a target abort error resulting in bit 12 of the ATUSR being set 3596 ** 0=Not Masked 3597 ** 1=Masked 3598 ** 03 0 2 ATU PCI Target Abort (Target) Interrupt Mask- Controls the setting of bit 1 of the ATUISR and generation 3599 ** of the ATU Error interrupt when a target abort error resulting in bit 11 of the ATUSR being set. 3600 ** 0=Not Masked 3601 ** 1=Masked 3602 ** 02 0 2 ATU PCI Master Parity Error Interrupt Mask - Controls the setting of bit 0 of the ATUISR and generation 3603 ** of the ATU Error interrupt when a parity error resulting in bit 8 of the ATUSR being set. 3604 ** 0=Not Masked 3605 ** 1=Masked 3606 ** 01 0 2 ATU Inbound Error SERR# Enable - Controls when the ATU asserts (when enabled through the 3607 ** ATUCMD) SERR# on the PCI interface in response to a master abort on the internal bus during an 3608 ** inbound write transaction. 3609 ** 0=SERR# Not Asserted due to error 3610 ** 1=SERR# Asserted due to error 3611 ** 00 0 2 ATU ECC Target Abort Enable - Controls the ATU response on the PCI interface to a target abort (ECC 3612 ** error) from the memory controller on the internal bus. In conventional mode, this action only occurs 3613 ** during an inbound read transaction where the data phase that was target aborted on the internal bus is 3614 ** actually requested from the inbound read queue. 3615 ** 0=Disconnect with data 3616 ** (the data being up to 64 bits of 1��s) 3617 ** 1=Target Abort 3618 ** NOTE: In PCI-X Mode, The ATU initiates a Split Completion Error Message (with message class=2h - 3619 ** completer error and message index=81h - 80331 internal bus target abort) on the PCI bus, 3620 ** independent of the setting of this bit. 3621 *********************************************************************************** 3622 */ 3623 #define ARCMSR_ATU_INTERRUPT_MASK_REG 0x8C /*dword 0x8F,0x8E,0x8D,0x8C*/ 3624 /* 3625 *********************************************************************************** 3626 ** Inbound ATU Base Address Register 3 - IABAR3 3627 ** 3628 ** . The Inbound ATU Base Address Register 3 (IABAR3) together with the Inbound ATU Upper Base Address Register 3 (IAUBAR3) defines the block 3629 ** of memory addresses where the inbound translation window 3 begins. 3630 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 3631 ** . The IABAR3 and IAUBAR3 define the base address and describes the required memory block size. 3632 ** . Bits 31 through 12 of the IABAR3 is either read/write bits or read only with a value of 0 depending on the value located within the IALR3. 3633 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 3634 ** Note: 3635 ** Since IABAR3 does not appear in the standard PCI configuration header space (offsets 00H - 3CH), 3636 ** IABAR3 is not configured by the host during normal system initialization. 3637 ** Warning: 3638 ** When a non-zero value is not written to IALR3, 3639 ** the user should not set either the Prefetchable Indicator 3640 ** or the Type Indicator for 64 bit addressability. 3641 ** This is the default for IABAR3. 3642 ** Assuming a non-zero value is written to IALR3, 3643 ** the user may set the Prefetchable Indicator 3644 ** or the Type Indicator: 3645 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 3646 ** when the Prefetchable Indicator is not set, 3647 ** the user should also leave the Type Indicator set for 32 bit addressability. 3648 ** This is the default for IABAR3. 3649 ** b. when the Prefetchable Indicator is set, 3650 ** the user should also set the Type Indicator for 64 bit addressability. 3651 ** ----------------------------------------------------------------- 3652 ** Bit Default Description 3653 ** 31:12 00000H Translation Base Address 3 - These bits define the actual location 3654 ** the translation function is to respond to when addressed from the PCI bus. 3655 ** 11:04 00H Reserved. 3656 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 3657 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 3658 ** 00 - Memory Window is locatable anywhere in 32 bit address space 3659 ** 10 - Memory Window is locatable anywhere in 64 bit address space 3660 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 3661 ** The ATU does not occupy I/O space, 3662 ** thus this bit must be zero. 3663 *********************************************************************************** 3664 */ 3665 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS3_REG 0x90 /*dword 0x93,0x92,0x91,0x90*/ 3666 /* 3667 *********************************************************************************** 3668 ** Inbound ATU Upper Base Address Register 3 - IAUBAR3 3669 ** 3670 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 3671 ** Together with the Translation Base Address this register defines the actual location 3672 ** the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 3673 ** The programmed value within the base address register must comply with the PCI programming 3674 ** requirements for address alignment. 3675 ** Note: 3676 ** When the Type indicator of IABAR3 is set to indicate 32 bit addressability, 3677 ** the IAUBAR3 register attributes are read-only. 3678 ** This is the default for IABAR3. 3679 ** ----------------------------------------------------------------- 3680 ** Bit Default Description 3681 ** 31:0 00000H Translation Upper Base Address 3 - Together with the Translation Base Address 3 these bits define 3682 ** the actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes. 3683 *********************************************************************************** 3684 */ 3685 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS3_REG 0x94 /*dword 0x97,0x96,0x95,0x94*/ 3686 /* 3687 *********************************************************************************** 3688 ** Inbound ATU Limit Register 3 - IALR3 3689 ** 3690 ** Inbound address translation for memory window 3 occurs for data transfers occurring from the PCI 3691 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 3692 ** PCI addresses to internal bus addresses. 3693 ** The inbound translation base address for inbound window 3 is specified in Section 3.10.15. When 3694 ** determining block size requirements �X as described in Section 3.10.21 �X the translation limit 3695 ** register provides the block size requirements for the base address register. The remaining registers 3696 ** used for performing address translation are discussed in Section 3.2.1.1. 3697 ** The 80331 translate value register��s programmed value must be naturally aligned with the base 3698 ** address register��s programmed value. The limit register is used as a mask; thus, the lower address 3699 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 3700 ** Specification, Revision 2.3 for additional information on programming base address registers. 3701 ** Bits 31 to 12 within the IALR3 have a direct effect on the IABAR3 register, bits 31 to 12, with a 3702 ** one to one correspondence. A value of 0 in a bit within the IALR3 makes the corresponding bit 3703 ** within the IABAR3 a read only bit which always returns 0. A value of 1 in a bit within the IALR3 3704 ** makes the corresponding bit within the IABAR3 read/write from PCI. Note that a consequence of 3705 ** this programming scheme is that unless a valid value exists within the IALR3, all writes to the 3706 ** IABAR3 has no effect since a value of all zeros within the IALR3 makes the IABAR3 a read only 3707 ** register. 3708 ** ----------------------------------------------------------------- 3709 ** Bit Default Description 3710 ** 31:12 00000H Inbound Translation Limit 3 - This readback value determines the memory block size required 3711 ** for the ATUs memory window 3. 3712 ** 11:00 000H Reserved 3713 *********************************************************************************** 3714 */ 3715 #define ARCMSR_INBOUND_ATU_LIMIT3_REG 0x98 /*dword 0x9B,0x9A,0x99,0x98*/ 3716 /* 3717 *********************************************************************************** 3718 ** Inbound ATU Translate Value Register 3 - IATVR3 3719 ** 3720 ** The Inbound ATU Translate Value Register 3 (IATVR3) contains the internal bus address used to 3721 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 3722 ** inbound ATU address translation. 3723 ** ----------------------------------------------------------------- 3724 ** Bit Default Description 3725 ** 31:12 00000H Inbound ATU Translation Value 3 - This value is used to convert the PCI address to internal bus addresses. 3726 ** This value must be 64-bit aligned on the internal bus. The default address allows the ATU to 3727 ** access the internal 80331 memory-mapped registers. 3728 ** 11:00 000H Reserved 3729 *********************************************************************************** 3730 */ 3731 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE3_REG 0x9C /*dword 0x9F,0x9E,0x9D,0x9C*/ 3732 /* 3733 *********************************************************************************** 3734 ** Outbound Configuration Cycle Address Register - OCCAR 3735 ** 3736 ** The Outbound Configuration Cycle Address Register is used to hold the 32-bit PCI configuration 3737 ** cycle address. The Intel XScale core writes the PCI configuration cycles address which then 3738 ** enables the outbound configuration read or write. The Intel XScale core then performs a read or 3739 ** write to the Outbound Configuration Cycle Data Register to initiate the configuration cycle on the 3740 ** PCI bus. 3741 ** Note: Bits 15:11 of the configuration cycle address for Type 0 configuration cycles are defined differently 3742 ** for Conventional versus PCI-X modes. When 80331 software programs the OCCAR to initiate a 3743 ** Type 0 configuration cycle, the OCCAR should always be loaded based on the PCI-X definition for 3744 ** the Type 0 configuration cycle address. When operating in Conventional mode, the 80331 clears 3745 ** bits 15:11 of the OCCAR prior to initiating an outbound Type 0 configuration cycle. See the PCI-X 3746 ** Addendum to the PCI Local Bus Specification, Revision 1.0a for details on the two formats. 3747 ** ----------------------------------------------------------------- 3748 ** Bit Default Description 3749 ** 31:00 0000 0000H Configuration Cycle Address - These bits define the 32-bit PCI address used during an outbound 3750 ** configuration read or write cycle. 3751 *********************************************************************************** 3752 */ 3753 #define ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_ADDRESS_REG 0xA4 /*dword 0xA7,0xA6,0xA5,0xA4*/ 3754 /* 3755 *********************************************************************************** 3756 ** Outbound Configuration Cycle Data Register - OCCDR 3757 ** 3758 ** The Outbound Configuration Cycle Data Register is used to initiate a configuration read or write 3759 ** on the PCI bus. The register is logical rather than physical meaning that it is an address not a 3760 ** register. The Intel XScale core reads or writes the data registers memory-mapped address to 3761 ** initiate the configuration cycle on the PCI bus with the address found in the OCCAR. For a 3762 ** configuration write, the data is latched from the internal bus and forwarded directly to the OWQ. 3763 ** For a read, the data is returned directly from the ORQ to the Intel XScale core and is never 3764 ** actually entered into the data register (which does not physically exist). 3765 ** The OCCDR is only visible from 80331 internal bus address space and appears as a reserved value 3766 ** within the ATU configuration space. 3767 ** ----------------------------------------------------------------- 3768 ** Bit Default Description 3769 ** 31:00 0000 0000H Configuration Cycle Data - These bits define the data used during an outbound configuration read 3770 ** or write cycle. 3771 *********************************************************************************** 3772 */ 3773 #define ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_DATA_REG 0xAC /*dword 0xAF,0xAE,0xAD,0xAC*/ 3774 /* 3775 *********************************************************************************** 3776 ** VPD Capability Identifier Register - VPD_CAPID 3777 ** 3778 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 3779 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 3780 ** Capability contained in that header. In the case of the 80331, this is the VPD extended capability 3781 ** with an ID of 03H as defined by the PCI Local Bus Specification, Revision 2.3. 3782 ** ----------------------------------------------------------------- 3783 ** Bit Default Description 3784 ** 07:00 03H Cap_Id - This field with its�� 03H value identifies this item in the linked list of Extended Capability 3785 ** Headers as being the VPD capability registers. 3786 *********************************************************************************** 3787 */ 3788 #define ARCMSR_VPD_CAPABILITY_IDENTIFIER_REG 0xB8 /*byte*/ 3789 /* 3790 *********************************************************************************** 3791 ** VPD Next Item Pointer Register - VPD_NXTP 3792 ** 3793 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 3794 ** Revision 2.3. This register describes the location of the next item in the function��s capability list. 3795 ** For the 80331, this the final capability list, and hence, this register is set to 00H. 3796 ** ----------------------------------------------------------------- 3797 ** Bit Default Description 3798 ** 07:00 00H Next_ Item_ Pointer - This field provides an offset into the function��s configuration space pointing to the 3799 ** next item in the function��s capability list. Since the VPD capabilities are the last in the linked list of 3800 ** extended capabilities in the 80331, the register is set to 00H. 3801 *********************************************************************************** 3802 */ 3803 #define ARCMSR_VPD_NEXT_ITEM_PTR_REG 0xB9 /*byte*/ 3804 /* 3805 *********************************************************************************** 3806 ** VPD Address Register - VPD_AR 3807 ** 3808 ** The VPD Address register (VPDAR) contains the DWORD-aligned byte address of the VPD to be 3809 ** accessed. The register is read/write and the initial value at power-up is indeterminate. 3810 ** A PCI Configuration Write to the VPDAR interrupts the Intel XScale core. Software can use 3811 ** the Flag setting to determine whether the configuration write was intended to initiate a read or 3812 ** write of the VPD through the VPD Data Register. 3813 ** ----------------------------------------------------------------- 3814 ** Bit Default Description 3815 ** 15 0 2 Flag - A flag is used to indicate when a transfer of data between the VPD Data Register and the storage 3816 ** component has completed. Please see Section 3.9, ��Vital Product Data�� on page 201 for more details on 3817 ** how the 80331 handles the data transfer. 3818 ** 14:0 0000H VPD Address - This register is written to set the DWORD-aligned byte address used to read or write 3819 ** Vital Product Data from the VPD storage component. 3820 *********************************************************************************** 3821 */ 3822 #define ARCMSR_VPD_ADDRESS_REG 0xBA /*word 0xBB,0xBA*/ 3823 /* 3824 *********************************************************************************** 3825 ** VPD Data Register - VPD_DR 3826 ** 3827 ** This register is used to transfer data between the 80331 and the VPD storage component. 3828 ** ----------------------------------------------------------------- 3829 ** Bit Default Description 3830 ** 31:00 0000H VPD Data - Four bytes are always read or written through this register to/from the VPD storage component. 3831 *********************************************************************************** 3832 */ 3833 #define ARCMSR_VPD_DATA_REG 0xBC /*dword 0xBF,0xBE,0xBD,0xBC*/ 3834 /* 3835 *********************************************************************************** 3836 ** Power Management Capability Identifier Register -PM_CAPID 3837 ** 3838 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 3839 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 3840 ** Capability contained in that header. In the case of the 80331, this is the PCI Bus Power 3841 ** Management extended capability with an ID of 01H as defined by the PCI Bus Power Management 3842 ** Interface Specification, Revision 1.1. 3843 ** ----------------------------------------------------------------- 3844 ** Bit Default Description 3845 ** 07:00 01H Cap_Id - This field with its�� 01H value identifies this item in the linked list of Extended Capability 3846 ** Headers as being the PCI Power Management Registers. 3847 *********************************************************************************** 3848 */ 3849 #define ARCMSR_POWER_MANAGEMENT_CAPABILITY_IDENTIFIER_REG 0xC0 /*byte*/ 3850 /* 3851 *********************************************************************************** 3852 ** Power Management Next Item Pointer Register - PM_NXTP 3853 ** 3854 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 3855 ** Revision 2.3. This register describes the location of the next item in the function��s capability list. 3856 ** For the 80331, the next capability (MSI capability list) is located at off-set D0H. 3857 ** ----------------------------------------------------------------- 3858 ** Bit Default Description 3859 ** 07:00 D0H Next_ Item_ Pointer - This field provides an offset into the function��s configuration space pointing to the 3860 ** next item in the function��s capability list which in the 80331 is the MSI extended capabilities header. 3861 *********************************************************************************** 3862 */ 3863 #define ARCMSR_POWER_NEXT_ITEM_PTR_REG 0xC1 /*byte*/ 3864 /* 3865 *********************************************************************************** 3866 ** Power Management Capabilities Register - PM_CAP 3867 ** 3868 ** Power Management Capabilities bits adhere to the definitions in the PCI Bus Power Management 3869 ** Interface Specification, Revision 1.1. This register is a 16-bit read-only register which provides 3870 ** information on the capabilities of the ATU function related to power management. 3871 ** ----------------------------------------------------------------- 3872 ** Bit Default Description 3873 ** 15:11 00000 2 PME_Support - This function is not capable of asserting the PME# signal in any state, since PME# 3874 ** is not supported by the 80331. 3875 ** 10 0 2 D2_Support - This bit is set to 0 2 indicating that the 80331 does not support the D2 Power Management State 3876 ** 9 1 2 D1_Support - This bit is set to 1 2 indicating that the 80331 supports the D1 Power Management State 3877 ** 8:6 000 2 Aux_Current - This field is set to 000 2 indicating that the 80331 has no current requirements for the 3878 ** 3.3Vaux signal as defined in the PCI Bus Power Management Interface Specification, Revision 1.1 3879 ** 5 0 2 DSI - This field is set to 0 2 meaning that this function requires a device specific initialization sequence 3880 ** following the transition to the D0 uninitialized state. 3881 ** 4 0 2 Reserved. 3882 ** 3 0 2 PME Clock - Since the 80331 does not support PME# signal generation this bit is cleared to 0 2 . 3883 ** 2:0 010 2 Version - Setting these bits to 010 2 means that this function complies with PCI Bus Power Management 3884 ** Interface Specification, Revision 1.1 3885 *********************************************************************************** 3886 */ 3887 #define ARCMSR_POWER_MANAGEMENT_CAPABILITY_REG 0xC2 /*word 0xC3,0xC2*/ 3888 /* 3889 *********************************************************************************** 3890 ** Power Management Control/Status Register - PM_CSR 3891 ** 3892 ** Power Management Control/Status bits adhere to the definitions in the PCI Bus Power 3893 ** Management Interface Specification, Revision 1.1. This 16-bit register is the control and status 3894 ** interface for the power management extended capability. 3895 ** ----------------------------------------------------------------- 3896 ** Bit Default Description 3897 ** 15 0 2 PME_Status - This function is not capable of asserting the PME# signal in any state, since PME## is not 3898 ** supported by the 80331. 3899 ** 14:9 00H Reserved 3900 ** 8 0 2 PME_En - This bit is hardwired to read-only 0 2 since this function does not support PME# 3901 ** generation from any power state. 3902 ** 7:2 000000 2 Reserved 3903 ** 1:0 00 2 Power State - This 2-bit field is used both to determine the current power state 3904 ** of a function and to set the function into a new power state. The definition of the values is: 3905 ** 00 2 - D0 3906 ** 01 2 - D1 3907 ** 10 2 - D2 (Unsupported) 3908 ** 11 2 - D3 hot 3909 ** The 80331 supports only the D0 and D3 hot states. 3910 ** 3911 *********************************************************************************** 3912 */ 3913 #define ARCMSR_POWER_MANAGEMENT_CONTROL_STATUS_REG 0xC4 /*word 0xC5,0xC4*/ 3914 /* 3915 *********************************************************************************** 3916 ** PCI-X Capability Identifier Register - PX_CAPID 3917 ** 3918 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 3919 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 3920 ** Capability contained in that header. In the case of the 80331, this is the PCI-X extended capability with 3921 ** an ID of 07H as defined by the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a. 3922 ** ----------------------------------------------------------------- 3923 ** Bit Default Description 3924 ** 07:00 07H Cap_Id - This field with its�� 07H value identifies this item in the linked list of Extended Capability 3925 ** Headers as being the PCI-X capability registers. 3926 *********************************************************************************** 3927 */ 3928 #define ARCMSR_PCIX_CAPABILITY_IDENTIFIER_REG 0xE0 /*byte*/ 3929 /* 3930 *********************************************************************************** 3931 ** PCI-X Next Item Pointer Register - PX_NXTP 3932 ** 3933 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 3934 ** Revision 2.3. This register describes the location of the next item in the function��s capability list. 3935 ** By default, the PCI-X capability is the last capabilities list for the 80331, thus this register defaults 3936 ** to 00H. 3937 ** However, this register may be written to B8H prior to host configuration to include the VPD 3938 ** capability located at off-set B8H. 3939 ** Warning: Writing this register to any value other than 00H (default) or B8H is not supported and may 3940 ** produce unpredictable system behavior. 3941 ** In order to guarantee that this register is written prior to host configuration, the 80331 must be 3942 ** initialized at P_RST# assertion to Retry Type 0 configuration cycles (bit 2 of PCSR). Typically, 3943 ** the Intel XScale core would be enabled to boot immediately following P_RST# assertion in 3944 ** this case (bit 1 of PCSR), as well. Please see Table 125, ��PCI Configuration and Status Register - 3945 ** PCSR�� on page 253 for more details on the 80331 initialization modes. 3946 ** ----------------------------------------------------------------- 3947 ** Bit Default Description 3948 ** 07:00 00H Next_ Item_ Pointer - This field provides an offset into the function��s configuration space pointing to the 3949 ** next item in the function��s capability list. Since the PCI-X capabilities are the last in the linked list of 3950 ** extended capabilities in the 80331, the register is set to 00H. 3951 ** However, this field may be written prior to host configuration with B8H to extend the list to include the 3952 ** VPD extended capabilities header. 3953 *********************************************************************************** 3954 */ 3955 #define ARCMSR_PCIX_NEXT_ITEM_PTR_REG 0xE1 /*byte*/ 3956 /* 3957 *********************************************************************************** 3958 ** PCI-X Command Register - PX_CMD 3959 ** 3960 ** This register controls various modes and features of ATU and Message Unit when operating in the 3961 ** PCI-X mode. 3962 ** ----------------------------------------------------------------- 3963 ** Bit Default Description 3964 ** 15:7 000000000 2 Reserved. 3965 ** 6:4 011 2 Maximum Outstanding Split Transactions - This register sets the maximum number of Split Transactions 3966 ** the device is permitted to have outstanding at one time. 3967 ** Register Maximum Outstanding 3968 ** 0 1 3969 ** 1 2 3970 ** 2 3 3971 ** 3 4 3972 ** 4 8 3973 ** 5 12 3974 ** 6 16 3975 ** 7 32 3976 ** 3:2 00 2 Maximum Memory Read Byte Count - This register sets the maximum byte count the device uses when 3977 ** initiating a Sequence with one of the burst memory read commands. 3978 ** Register Maximum Byte Count 3979 ** 0 512 3980 ** 1 1024 3981 ** 2 2048 3982 ** 3 4096 3983 ** 1 0 2 3984 ** Enable Relaxed Ordering - The 80331 does not set the relaxed ordering bit in the Requester Attributes 3985 ** of Transactions. 3986 ** 0 0 2 Data Parity Error Recovery Enable - The device driver sets this bit to enable the device to attempt to 3987 ** recover from data parity errors. When this bit is 0 and the device is in PCI-X mode, the device asserts 3988 ** SERR# (when enabled) whenever the Master Data Parity Error bit (Status register, bit 8) is set. 3989 *********************************************************************************** 3990 */ 3991 #define ARCMSR_PCIX_COMMAND_REG 0xE2 /*word 0xE3,0xE2*/ 3992 /* 3993 *********************************************************************************** 3994 ** PCI-X Status Register - PX_SR 3995 ** 3996 ** This register identifies the capabilities and current operating mode of ATU, DMAs and Message 3997 ** Unit when operating in the PCI-X mode. 3998 ** ----------------------------------------------------------------- 3999 ** Bit Default Description 4000 ** 31:30 00 2 Reserved 4001 ** 29 0 2 Received Split Completion Error Message - This bit is set when the device receives a Split Completion 4002 ** Message with the Split Completion Error attribute bit set. Once set, this bit remains set until software 4003 ** writes a 1 to this location. 4004 ** 0=no Split Completion error message received. 4005 ** 1=a Split Completion error message has been received. 4006 ** 28:26 001 2 Designed Maximum Cumulative Read Size (DMCRS) - The value of this register depends on the setting 4007 ** of the Maximum Memory Read Byte Count field of the PCIXCMD register: 4008 ** DMCRS Max ADQs Maximum Memory Read Byte Count Register Setting 4009 ** 1 16 512 (Default) 4010 ** 2 32 1024 4011 ** 2 32 2048 4012 ** 2 32 4096 4013 ** 25:23 011 2 Designed Maximum Outstanding Split Transactions - The 80331 can have up to four outstanding split transactions. 4014 ** 22:21 01 2 Designed Maximum Memory Read Byte Count - The 80331 can generate memory reads with byte counts up 4015 ** to 1024 bytes. 4016 ** 20 1 2 80331 is a complex device. 4017 ** 19 0 2 Unexpected Split Completion - This bit is set when an unexpected Split Completion with this device��s 4018 ** Requester ID is received. Once set, this bit remains set until software writes a 1 to this location. 4019 ** 0=no unexpected Split Completion has been received. 4020 ** 1=an unexpected Split Completion has been received. 4021 ** 18 0 2 Split Completion Discarded - This bit is set when the device discards a Split Completion because the 4022 ** requester would not accept it. See Section 5.4.4 of the PCI-X Addendum to the PCI Local Bus 4023 ** Specification, Revision 1.0a for details. Once set, this bit remains set until software writes a 1 to this 4024 ** location. 4025 ** 0=no Split Completion has been discarded. 4026 ** 1=a Split Completion has been discarded. 4027 ** NOTE: The 80331 does not set this bit since there is no Inbound address responding to Inbound Read 4028 ** Requests with Split Responses (Memory or Register) that has ��read side effects.�� 4029 ** 17 1 2 80331 is a 133 MHz capable device. 4030 ** 16 1 2 or P_32BITPCI# 80331 with bridge enabled (BRG_EN=1) implements the ATU with a 64-bit interface on the secondary PCI bus, 4031 ** therefore this bit is always set. 4032 ** 80331 with no bridge and central resource disabled (BRG_EN=0, ARB_EN=0), 4033 ** use this bit to identify the add-in card to the system as 64-bit or 32-bit wide via a user-configurable strap (P_32BITPCI#). 4034 ** This strap, by default, identifies the add in card based on 80331 with bridge disabled 4035 ** as 64-bit unless the user attaches the appropriate pull-down resistor to the strap. 4036 ** 0=The bus is 32 bits wide. 4037 ** 1=The bus is 64 bits wide. 4038 ** 15:8 FFH Bus Number - This register is read for diagnostic purposes only. It indicates the number of the bus 4039 ** segment for the device containing this function. The function uses this number as part of its Requester 4040 ** ID and Completer ID. For all devices other than the source bridge, each time the function is addressed 4041 ** by a Configuration Write transaction, the function must update this register with the contents of AD[7::0] 4042 ** of the attribute phase of the Configuration Write, regardless of which register in the function is 4043 ** addressed by the transaction. The function is addressed by a Configuration Write transaction when all of 4044 ** the following are true: 4045 ** 1. The transaction uses a Configuration Write command. 4046 ** 2. IDSEL is asserted during the address phase. 4047 ** 3. AD[1::0] are 00b (Type 0 configuration transaction). 4048 ** 4. AD[10::08] of the configuration address contain the appropriate function number. 4049 ** 7:3 1FH Device Number - This register is read for diagnostic purposes only. It indicates the number of the device 4050 ** containing this function, i.e., the number in the Device Number field (AD[15::11]) of the address of a 4051 ** Type 0 configuration transaction that is assigned to the device containing this function by the connection 4052 ** of the system hardware. The system must assign a device number other than 00h (00h is reserved for 4053 ** the source bridge). The function uses this number as part of its Requester ID and Completer ID. Each 4054 ** time the function is addressed by a Configuration Write transaction, the device must update this register 4055 ** with the contents of AD[15::11] of the address phase of the Configuration Write, regardless of which 4056 ** register in the function is addressed by the transaction. The function is addressed by a Configuration 4057 ** Write transaction when all of the following are true: 4058 ** 1. The transaction uses a Configuration Write command. 4059 ** 2. IDSEL is asserted during the address phase. 4060 ** 3. AD[1::0] are 00b (Type 0 configuration transaction). 4061 ** 4. AD[10::08] of the configuration address contain the appropriate function number. 4062 ** 2:0 000 2 Function Number - This register is read for diagnostic purposes only. It indicates the number of this 4063 ** function; i.e., the number in the Function Number field (AD[10::08]) of the address of a Type 0 4064 ** configuration transaction to which this function responds. The function uses this number as part of its 4065 ** Requester ID and Completer ID. 4066 ** 4067 ************************************************************************** 4068 */ 4069 #define ARCMSR_PCIX_STATUS_REG 0xE4 /*dword 0xE7,0xE6,0xE5,0xE4*/ 4070 4071 /* 4072 ************************************************************************** 4073 ** Inbound Read Transaction 4074 ** ======================================================================== 4075 ** An inbound read transaction is initiated by a PCI initiator and is targeted at either 80331 local 4076 ** memory or a 80331 memory-mapped register space. The read transaction is propagated through 4077 ** the inbound transaction queue (ITQ) and read data is returned through the inbound read queue 4078 ** (IRQ). 4079 ** When operating in the conventional PCI mode, all inbound read transactions are processed as 4080 ** delayed read transactions. When operating in the PCI-X mode, all inbound read transactions are 4081 ** processed as split transactions. The ATUs PCI interface claims the read transaction and forwards 4082 ** the read request through to the internal bus and returns the read data to the PCI bus. Data flow for 4083 ** an inbound read transaction on the PCI bus is summarized in the following statements: 4084 ** �E The ATU claims the PCI read transaction when the PCI address is within the inbound 4085 ** translation window defined by ATU Inbound Base Address Register (and Inbound Upper Base 4086 ** Address Register during DACs) and Inbound Limit Register. 4087 ** �E When operating in the conventional PCI mode, when the ITQ is currently holding transaction 4088 ** information from a previous delayed read, the current transaction information is compared to 4089 ** the previous transaction information (based on the setting of the DRC Alias bit in 4090 ** Section 3.10.39, ��ATU Configuration Register - ATUCR�� on page 252). When there is a 4091 ** match and the data is in the IRQ, return the data to the master on the PCI bus. When there is a 4092 ** match and the data is not available, a Retry is signaled with no other action taken. When there 4093 ** is not a match and when the ITQ has less than eight entries, capture the transaction 4094 ** information, signal a Retry and initiate a delayed transaction. When there is not a match and 4095 ** when the ITQ is full, then signal a Retry with no other action taken. 4096 ** �X When an address parity error is detected, the address parity response defined in 4097 ** Section 3.7 is used. 4098 ** �E When operating in the conventional PCI mode, once read data is driven onto the PCI bus from 4099 ** the IRQ, it continues until one of the following is true: 4100 ** �X The initiator completes the PCI transaction. When there is data left unread in the IRQ, the 4101 ** data is flushed. 4102 ** �X An internal bus Target Abort was detected. In this case, the QWORD associated with the 4103 ** Target Abort is never entered into the IRQ, and therefore is never returned. 4104 ** �X Target Abort or a Disconnect with Data is returned in response to the Internal Bus Error. 4105 ** �X The IRQ becomes empty. In this case, the PCI interface signals a Disconnect with data to 4106 ** the initiator on the last data word available. 4107 ** �E When operating in the PCI-X mode, when ITQ is not full, the PCI address, attribute and 4108 ** command are latched into the available ITQ and a Split Response Termination is signalled to 4109 ** the initiator. 4110 ** �E When operating in the PCI-X mode, when the transaction does not cross a 1024 byte aligned 4111 ** boundary, then the ATU waits until it receives the full byte count from the internal bus target 4112 ** before returning read data by generating the split completion transaction on the PCI-X bus. 4113 ** When the read requested crosses at least one 1024 byte boundary, then ATU completes the 4114 ** transfer by returning data in 1024 byte aligned chunks. 4115 ** �E When operating in the PCI-X mode, once a split completion transaction has started, it 4116 ** continues until one of the following is true: 4117 ** �X The requester (now the target) generates a Retry Termination, or a Disconnection at Next 4118 ** ADB (when the requester is a bridge) 4119 ** �X The byte count is satisfied. 4120 ** �X An internal bus Target Abort was detected. The ATU generates a Split Completion 4121 ** Message (message class=2h - completer error, and message index=81h - target abort) to 4122 ** inform the requester about the abnormal condition. The ITQ for this transaction is flushed. 4123 ** Refer to Section 3.7.1. 4124 ** �X An internal bus Master Abort was detected. The ATU generates a Split Completion 4125 ** Message (message class=2h - completer error, and message index=80h - Master abort) to 4126 ** inform the requester about the abnormal condition. The ITQ for this transaction is flushed. 4127 ** Refer to Section 3.7.1 4128 ** �E When operating in the conventional PCI mode, when the master inserts wait states on the PCI 4129 ** bus, the ATU PCI slave interface waits with no premature disconnects. 4130 ** �E When a data parity error occurs signified by PERR# asserted from the initiator, no action is 4131 ** taken by the target interface. Refer to Section 3.7.2.5. 4132 ** �E When operating in the conventional PCI mode, when the read on the internal bus is 4133 ** target-aborted, either a target-abort or a disconnect with data is signaled to the initiator. This is 4134 ** based on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). When set, a 4135 ** target abort is used, when clear, a disconnect is used. 4136 ** �E When operating in the PCI-X mode (with the exception of the MU queue ports at offsets 40h 4137 ** and 44h), when the transaction on the internal bus resulted in a target abort, the ATU generates 4138 ** a Split Completion Message (message class=2h - completer error, and message index=81h - 4139 ** internal bus target abort) to inform the requester about the abnormal condition. For the MU 4140 ** queue ports, the ATU returns either a target abort or a single data phase disconnect depending 4141 ** on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). The ITQ for this 4142 ** transaction is flushed. Refer to Section 3.7.1. 4143 ** �E When operating in the conventional PCI mode, when the transaction on the internal bus 4144 ** resulted in a master abort, the ATU returns a target abort to inform the requester about the 4145 ** abnormal condition. The ITQ for this transaction is flushed. Refer to Section 3.7.1 4146 ** �E When operating in the PCI-X mode, when the transaction on the internal bus resulted in a 4147 ** master abort, the ATU generates a Split Completion Message (message class=2h - completer 4148 ** error, and message index=80h - internal bus master abort) to inform the requester about the 4149 ** abnormal condition. The ITQ for this transaction is flushed. Refer to Section 3.7.1. 4150 ** �E When operating in the PCI-X mode, when the Split Completion transaction completes with 4151 ** either Master-Abort or Target-Abort, the requester is indicating a failure condition that 4152 ** prevents it from accepting the completion it requested. In this case, since the Split Request 4153 ** addresses a location that has no read side effects, the completer must discard the Split 4154 ** Completion and take no further action. 4155 ** The data flow for an inbound read transaction on the internal bus is summarized in the following 4156 ** statements: 4157 ** �E The ATU internal bus master interface requests the internal bus when a PCI address appears in 4158 ** an ITQ and transaction ordering has been satisfied. When operating in the PCI-X mode the 4159 ** ATU does not use the information provided by the Relax Ordering Attribute bit. That is, ATU 4160 ** always uses conventional PCI ordering rules. 4161 ** �E Once the internal bus is granted, the internal bus master interface drives the translated address 4162 ** onto the bus and wait for IB_DEVSEL#. When a Retry is signaled, the request is repeated. 4163 ** When a master abort occurs, the transaction is considered complete and a target abort is loaded 4164 ** into the associated IRQ for return to the PCI initiator (transaction is flushed once the PCI 4165 ** master has been delivered the target abort). 4166 ** �E Once the translated address is on the bus and the transaction has been accepted, the internal 4167 ** bus target starts returning data with the assertion of IB_TRDY#. Read data is continuously 4168 ** received by the IRQ until one of the following is true: 4169 ** �X The full byte count requested by the ATU read request is received. The ATU internal bus 4170 ** initiator interface performs a initiator completion in this case. 4171 ** �X When operating in the conventional PCI mode, a Target Abort is received on the internal 4172 ** bus from the internal bus target. In this case, the transaction is aborted and the PCI side is 4173 ** informed. 4174 ** �X When operating in the PCI-X mode, a Target Abort is received on the internal bus from 4175 ** the internal bus target. In this case, the transaction is aborted. The ATU generates a Split 4176 ** Completion Message (message class=2h - completer error, and message index=81h - 4177 ** target abort) on the PCI bus to inform the requester about the abnormal condition. The 4178 ** ITQ for this transaction is flushed. 4179 ** �X When operating in the conventional PCI mode, a single data phase disconnection is 4180 ** received from the internal bus target. When the data has not been received up to the next 4181 ** QWORD boundary, the ATU internal bus master interface attempts to reacquire the bus. 4182 ** When not, the bus returns to idle. 4183 ** �X When operating in the PCI-X mode, a single data phase disconnection is received from 4184 ** the internal bus target. The ATU IB initiator interface attempts to reacquire the bus to 4185 ** obtain remaining data. 4186 ** �X When operating in the conventional PCI mode, a disconnection at Next ADB is received 4187 ** from the internal bus target. The bus returns to idle. 4188 ** �X When operating in the PCI-X mode, a disconnection at Next ADB is received from the 4189 ** internal bus target. The ATU IB initiator interface attempts to reacquire the bus to obtain 4190 ** remaining data. 4191 ** To support PCI Local Bus Specification, Revision 2.0 devices, the ATU can be programmed to 4192 ** ignore the memory read command (Memory Read, Memory Read Line, and Memory Read 4193 ** Multiple) when trying to match the current inbound read transaction with data in a DRC queue 4194 ** which was read previously (DRC on target bus). When the Read Command Alias Bit in the 4195 ** ATUCR register is set, the ATU does not distinguish the read commands on transactions. For 4196 ** example, the ATU enqueues a DRR with a Memory Read Multiple command and performs the read 4197 ** on the internal bus. Some time later, a PCI master attempts a Memory Read with the same address 4198 ** as the previous Memory Read Multiple. When the Read Command Bit is set, the ATU would return 4199 ** the read data from the DRC queue and consider the Delayed Read transaction complete. When the 4200 ** Read Command bit in the ATUCR was clear, the ATU would not return data since the PCI read 4201 ** commands did not match, only the address. 4202 ************************************************************************** 4203 */ 4204 /* 4205 ************************************************************************** 4206 ** Inbound Write Transaction 4207 **======================================================================== 4208 ** An inbound write transaction is initiated by a PCI master and is targeted at either 80331 local 4209 ** memory or a 80331 memory-mapped register. 4210 ** Data flow for an inbound write transaction on the PCI bus is summarized as: 4211 ** �E The ATU claims the PCI write transaction when the PCI address is within the inbound 4212 ** translation window defined by the ATU Inbound Base Address Register (and Inbound Upper 4213 ** Base Address Register during DACs) and Inbound Limit Register. 4214 ** �E When the IWADQ has at least one address entry available and the IWQ has at least one buffer 4215 ** available, the address is captured and the first data phase is accepted. 4216 ** �E The PCI interface continues to accept write data until one of the following is true: 4217 ** �X The initiator performs a disconnect. 4218 ** �X The transaction crosses a buffer boundary. 4219 ** �E When an address parity error is detected during the address phase of the transaction, the 4220 ** address parity error mechanisms are used. Refer to Section 3.7.1 for details of the address 4221 ** parity error response. 4222 ** �E When operating in the PCI-X mode when an attribute parity error is detected, the attribute 4223 ** parity error mechanism described in Section 3.7.1 is used. 4224 ** �E When a data parity error is detected while accepting data, the slave interface sets the 4225 ** appropriate bits based on PCI specifications. No other action is taken. Refer to Section 3.7.2.6 4226 ** for details of the inbound write data parity error response. 4227 ** Once the PCI interface places a PCI address in the IWADQ, when IWQ has received data sufficient 4228 ** to cross a buffer boundary or the master disconnects on the PCI bus, the ATUs internal bus 4229 ** interface becomes aware of the inbound write. When there are additional write transactions ahead 4230 ** in the IWQ/IWADQ, the current transaction remains posted until ordering and priority have been 4231 ** satisfied (Refer to Section 3.5.3) and the transaction is attempted on the internal bus by the ATU 4232 ** internal master interface. The ATU does not insert target wait states nor do data merging on the PCI 4233 ** interface, when operating in the PCI mode. 4234 ** In the PCI-X mode memory writes are always executed as immediate transactions, while 4235 ** configuration write transactions are processed as split transactions. The ATU generates a Split 4236 ** Completion Message, (with Message class=0h - Write Completion Class and Message index = 4237 ** 00h - Write Completion Message) once a configuration write is successfully executed. 4238 ** Also, when operating in the PCI-X mode a write sequence may contain multiple write transactions. 4239 ** The ATU handles such transactions as independent transactions. 4240 ** Data flow for the inbound write transaction on the internal bus is summarized as: 4241 ** �E The ATU internal bus master requests the internal bus when IWADQ has at least one entry 4242 ** with associated data in the IWQ. 4243 ** �E When the internal bus is granted, the internal bus master interface initiates the write 4244 ** transaction by driving the translated address onto the internal bus. For details on inbound 4245 ** address translation. 4246 ** �E When IB_DEVSEL# is not returned, a master abort condition is signaled on the internal bus. 4247 ** The current transaction is flushed from the queue and SERR# may be asserted on the PCI 4248 ** interface. 4249 ** �E The ATU initiator interface asserts IB_REQ64# to attempt a 64-bit transfer. When 4250 ** IB_ACK64# is not returned, a 32-bit transfer is used. Transfers of less than 64-bits use the 4251 ** IB_C/BE[7:0]# to mask the bytes not written in the 64-bit data phase. Write data is transferred 4252 ** from the IWQ to the internal bus when data is available and the internal bus interface retains 4253 ** internal bus ownership. 4254 ** �E The internal bus interface stops transferring data from the current transaction to the internal 4255 ** bus when one of the following conditions becomes true: 4256 ** �X The internal bus initiator interface loses bus ownership. The ATU internal initiator 4257 ** terminates the transfer (initiator disconnection) at the next ADB (for the internal bus ADB 4258 ** is defined as a naturally aligned 128-byte boundary) and attempt to reacquire the bus to 4259 ** complete the delivery of remaining data using the same sequence ID but with the 4260 ** modified starting address and byte count. 4261 ** �X A Disconnect at Next ADB is signaled on the internal bus from the internal target. When 4262 ** the transaction in the IWQ completes at that ADB, the initiator returns to idle. When the 4263 ** transaction in the IWQ is not complete, the initiator attempts to reacquire the bus to 4264 ** complete the delivery of remaining data using the same sequence ID but with the 4265 ** modified starting address and byte count. 4266 ** �X A Single Data Phase Disconnect is signaled on the internal bus from the internal target. 4267 ** When the transaction in the IWQ needs only a single data phase, the master returns to idle. 4268 ** When the transaction in the IWQ is not complete, the initiator attempts to reacquire the 4269 ** bus to complete the delivery of remaining data using the same sequence ID but with the 4270 ** modified starting address and byte count. 4271 ** �X The data from the current transaction has completed (satisfaction of byte count). An 4272 ** initiator termination is performed and the bus returns to idle. 4273 ** �X A Master Abort is signaled on the internal bus. SERR# may be asserted on the PCI bus. 4274 ** Data is flushed from the IWQ. 4275 ***************************************************************** 4276 */ 4277 4278 4279 4280 /* 4281 ************************************************************************** 4282 ** Inbound Read Completions Data Parity Errors 4283 **======================================================================== 4284 ** As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode. 4285 ** When as the completer of a Split Read Request the ATU observes PERR# assertion during the split 4286 ** completion transaction, the ATU attempts to complete the transaction normally and no further 4287 ** action is taken. 4288 ************************************************************************** 4289 */ 4290 4291 /* 4292 ************************************************************************** 4293 ** Inbound Configuration Write Completion Message Data Parity Errors 4294 **======================================================================== 4295 ** As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode. 4296 ** When as the completer of a Configuration (Split) Write Request the ATU observes PERR# 4297 ** assertion during the split completion transaction, the ATU attempts to complete the transaction 4298 ** normally and no further action is taken. 4299 ************************************************************************** 4300 */ 4301 4302 /* 4303 ************************************************************************** 4304 ** Inbound Read Request Data Parity Errors 4305 **===================== Immediate Data Transfer ========================== 4306 ** As a target, the ATU may encounter this error when operating in the Conventional PCI or PCI-X modes. 4307 ** Inbound read data parity errors occur when read data delivered from the IRQ is detected as having 4308 ** bad parity by the initiator of the transaction who is receiving the data. The initiator may optionally 4309 ** report the error to the system by asserting PERR#. As a target device in this scenario, no action is 4310 ** required and no error bits are set. 4311 **=====================Split Response Termination========================= 4312 ** As a target, the ATU may encounter this error when operating in the PCI-X mode. 4313 ** Inbound read data parity errors occur during the Split Response Termination. The initiator may 4314 ** optionally report the error to the system by asserting PERR#. As a target device in this scenario, no 4315 ** action is required and no error bits are set. 4316 ************************************************************************** 4317 */ 4318 4319 /* 4320 ************************************************************************** 4321 ** Inbound Write Request Data Parity Errors 4322 **======================================================================== 4323 ** As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes. 4324 ** Data parity errors occurring during write operations received by the ATU may assert PERR# on 4325 ** the PCI Bus. When an error occurs, the ATU continues accepting data until the initiator of the write 4326 ** transaction completes or a queue fill condition is reached. Specifically, the following actions with 4327 ** the given constraints are taken by the ATU: 4328 ** �E PERR# is asserted two clocks cycles (three clock cycles when operating in the PCI-X mode) 4329 ** following the data phase in which the data parity error is detected on the bus. This is only 4330 ** done when the Parity Error Response bit in the ATUCMD is set. 4331 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4332 ** actions is taken: 4333 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4334 ** Detected Parity Error bit in the ATUISR. When set, no action. 4335 *************************************************************************** 4336 */ 4337 4338 4339 /* 4340 *************************************************************************** 4341 ** Inbound Configuration Write Request 4342 ** ===================================================================== 4343 ** As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes. 4344 ** =============================================== 4345 ** Conventional PCI Mode 4346 ** =============================================== 4347 ** To allow for correct data parity calculations for delayed write transactions, the ATU delays the 4348 ** assertion of STOP# (signalling a Retry) until PAR is driven by the master. A parity error during a 4349 ** delayed write transaction (inbound configuration write cycle) can occur in any of the following 4350 ** parts of the transactions: 4351 ** �E During the initial Delayed Write Request cycle on the PCI bus when the ATU latches the 4352 ** address/command and data for delayed delivery to the internal configuration register. 4353 ** �E During the Delayed Write Completion cycle on the PCI bus when the ATU delivers the status 4354 ** of the operation back to the original master. 4355 ** The 80331 ATU PCI interface has the following responses to a delayed write parity error for 4356 ** inbound transactions during Delayed Write Request cycles with the given constraints: 4357 ** �E When the Parity Error Response bit in the ATUCMD is set, the ATU asserts TRDY# 4358 ** (disconnects with data) and two clock cycles later asserts PERR# notifying the initiator of the 4359 ** parity error. The delayed write cycle is not enqueued and forwarded to the internal bus. 4360 ** When the Parity Error Response bit in the ATUCMD is cleared, the ATU retries the 4361 ** transaction by asserting STOP# and enqueues the Delayed Write Request cycle to be 4362 ** forwarded to the internal bus. PERR# is not asserted. 4363 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4364 ** actions is taken: 4365 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4366 ** Detected Parity Error bit in the ATUISR. When set, no action. 4367 ** For the original write transaction to be completed, the initiator retries the transaction on the PCI 4368 ** bus and the ATU returns the status from the internal bus, completing the transaction. 4369 ** For the Delayed Write Completion transaction on the PCI bus where a data parity error occurs and 4370 ** therefore does not agree with the status being returned from the internal bus (i.e. status being 4371 ** returned is normal completion) the ATU performs the following actions with the given constraints: 4372 ** �E When the Parity Error Response Bit is set in the ATUCMD, the ATU asserts TRDY# 4373 ** (disconnects with data) and two clocks later asserts PERR#. The Delayed Completion cycle in 4374 ** the IDWQ remains since the data of retried command did not match the data within the queue. 4375 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4376 ** actions is taken: 4377 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4378 ** Detected Parity Error bit in the ATUISR. When set, no action. 4379 ** =================================================== 4380 ** PCI-X Mode 4381 ** =================================================== 4382 ** Data parity errors occurring during configuration write operations received by the ATU may cause 4383 ** PERR# assertion and delivery of a Split Completion Error Message on the PCI Bus. When an error 4384 ** occurs, the ATU accepts the write data and complete with a Split Response Termination. 4385 ** Specifically, the following actions with the given constraints are then taken by the ATU: 4386 ** �E When the Parity Error Response bit in the ATUCMD is set, PERR# is asserted three clocks 4387 ** cycles following the Split Response Termination in which the data parity error is detected on 4388 ** the bus. When the ATU asserts PERR#, additional actions is taken: 4389 ** �X A Split Write Data Parity Error message (with message class=2h - completer error and 4390 ** message index=01h - Split Write Data Parity Error) is initiated by the ATU on the PCI bus 4391 ** that addresses the requester of the configuration write. 4392 ** �X When the Initiated Split Completion Error Message Interrupt Mask in the ATUIMR is 4393 ** clear, set the Initiated Split Completion Error Message bit in the ATUISR. When set, no 4394 ** action. 4395 ** �X The Split Write Request is not enqueued and forwarded to the internal bus. 4396 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4397 ** actions is taken: 4398 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4399 ** Detected Parity Error bit in the ATUISR. When set, no action. 4400 ** 4401 *************************************************************************** 4402 */ 4403 4404 /* 4405 *************************************************************************** 4406 ** Split Completion Messages 4407 ** ======================================================================= 4408 ** As a target, the ATU may encounter this error when operating in the PCI-X mode. 4409 ** Data parity errors occurring during Split Completion Messages claimed by the ATU may assert 4410 ** PERR# (when enabled) or SERR# (when enabled) on the PCI Bus. When an error occurs, the 4411 ** ATU accepts the data and complete normally. Specifically, the following actions with the given 4412 ** constraints are taken by the ATU: 4413 ** �E PERR# is asserted three clocks cycles following the data phase in which the data parity error 4414 ** is detected on the bus. This is only done when the Parity Error Response bit in the ATUCMD 4415 ** is set. When the ATU asserts PERR#, additional actions is taken: 4416 ** �X The Master Parity Error bit in the ATUSR is set. 4417 ** �X When the ATU PCI Master Parity Error Interrupt Mask Bit in the ATUIMR is clear, set the 4418 ** PCI Master Parity Error bit in the ATUISR. When set, no action. 4419 ** �X When the SERR# Enable bit in the ATUCMD is set, and the Data Parity Error Recover 4420 ** Enable bit in the PCIXCMD register is clear, assert SERR#; otherwise no action is taken. 4421 ** When the ATU asserts SERR#, additional actions is taken: 4422 ** Set the SERR# Asserted bit in the ATUSR. 4423 ** When the ATU SERR# Asserted Interrupt Mask Bit in the ATUIMR is clear, set the 4424 ** SERR# Asserted bit in the ATUISR. When set, no action. 4425 ** When the ATU SERR# Detected Interrupt Enable Bit in the ATUCR is set, set the 4426 ** SERR# Detected bit in the ATUISR. When clear, no action. 4427 ** �E When the SCE bit (Split Completion Error -- bit 30 of the Completer Attributes) is set during 4428 ** the Attribute phase, the Received Split Completion Error Message bit in the PCIXSR is set. 4429 ** When the ATU sets this bit, additional actions is taken: 4430 ** �X When the ATU Received Split Completion Error Message Interrupt Mask bit in the 4431 ** ATUIMR is clear, set the Received Split Completion Error Message bit in the ATUISR. 4432 ** When set, no action. 4433 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4434 ** actions is taken: 4435 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4436 ** Detected Parity Error bit in the ATUISR. When set, no action. 4437 ** �E The transaction associated with the Split Completion Message is discarded. 4438 ** �E When the discarded transaction was a read, a completion error message (with message 4439 ** class=2h - completer error and message index=82h - PCI bus read parity error) is generated on 4440 ** the internal bus of the 80331. 4441 ***************************************************************************** 4442 */ 4443 4444 4445 /* 4446 ****************************************************************************************************** 4447 ** Messaging Unit (MU) of the Intel R 80331 I/O processor (80331) 4448 ** ================================================================================================== 4449 ** The Messaging Unit (MU) transfers data between the PCI system and the 80331 4450 ** notifies the respective system when new data arrives. 4451 ** The PCI window for messaging transactions is always the first 4 Kbytes of the inbound translation. 4452 ** window defined by: 4453 ** 1.Inbound ATU Base Address Register 0 (IABAR0) 4454 ** 2.Inbound ATU Limit Register 0 (IALR0) 4455 ** All of the Messaging Unit errors are reported in the same manner as ATU errors. 4456 ** Error conditions and status can be found in : 4457 ** 1.ATUSR 4458 ** 2.ATUISR 4459 **==================================================================================================== 4460 ** Mechanism Quantity Assert PCI Interrupt Signals Generate I/O Processor Interrupt 4461 **---------------------------------------------------------------------------------------------------- 4462 ** Message Registers 2 Inbound Optional Optional 4463 ** 2 Outbound 4464 **---------------------------------------------------------------------------------------------------- 4465 ** Doorbell Registers 1 Inbound Optional Optional 4466 ** 1 Outbound 4467 **---------------------------------------------------------------------------------------------------- 4468 ** Circular Queues 4 Circular Queues Under certain conditions Under certain conditions 4469 **---------------------------------------------------------------------------------------------------- 4470 ** Index Registers 1004 32-bit Memory Locations No Optional 4471 **==================================================================================================== 4472 ** PCI Memory Map: First 4 Kbytes of the ATU Inbound PCI Address Space 4473 **==================================================================================================== 4474 ** 0000H Reserved 4475 ** 0004H Reserved 4476 ** 0008H Reserved 4477 ** 000CH Reserved 4478 **------------------------------------------------------------------------ 4479 ** 0010H Inbound Message Register 0 ] 4480 ** 0014H Inbound Message Register 1 ] 4481 ** 0018H Outbound Message Register 0 ] 4482 ** 001CH Outbound Message Register 1 ] 4 Message Registers 4483 **------------------------------------------------------------------------ 4484 ** 0020H Inbound Doorbell Register ] 4485 ** 0024H Inbound Interrupt Status Register ] 4486 ** 0028H Inbound Interrupt Mask Register ] 4487 ** 002CH Outbound Doorbell Register ] 4488 ** 0030H Outbound Interrupt Status Register ] 4489 ** 0034H Outbound Interrupt Mask Register ] 2 Doorbell Registers and 4 Interrupt Registers 4490 **------------------------------------------------------------------------ 4491 ** 0038H Reserved 4492 ** 003CH Reserved 4493 **------------------------------------------------------------------------ 4494 ** 0040H Inbound Queue Port ] 4495 ** 0044H Outbound Queue Port ] 2 Queue Ports 4496 **------------------------------------------------------------------------ 4497 ** 0048H Reserved 4498 ** 004CH Reserved 4499 **------------------------------------------------------------------------ 4500 ** 0050H ] 4501 ** : ] 4502 ** : Intel Xscale Microarchitecture Local Memory ] 4503 ** : ] 4504 ** 0FFCH ] 1004 Index Registers 4505 ******************************************************************************* 4506 */ 4507 /* 4508 ***************************************************************************** 4509 ** Theory of MU Operation 4510 ***************************************************************************** 4511 **-------------------- 4512 ** inbound_msgaddr0: 4513 ** inbound_msgaddr1: 4514 ** outbound_msgaddr0: 4515 ** outbound_msgaddr1: 4516 ** . The MU has four independent messaging mechanisms. 4517 ** There are four Message Registers that are similar to a combination of mailbox and doorbell registers. 4518 ** Each holds a 32-bit value and generates an interrupt when written. 4519 **-------------------- 4520 ** inbound_doorbell: 4521 ** outbound_doorbell: 4522 ** . The two Doorbell Registers support software interrupts. 4523 ** When a bit is set in a Doorbell Register, an interrupt is generated. 4524 **-------------------- 4525 ** inbound_queueport: 4526 ** outbound_queueport: 4527 ** 4528 ** 4529 ** . The Circular Queues support a message passing scheme that uses 4 circular queues. 4530 ** The 4 circular queues are implemented in 80331 local memory. 4531 ** Two queues are used for inbound messages and two are used for outbound messages. 4532 ** Interrupts may be generated when the queue is written. 4533 **-------------------- 4534 ** local_buffer 0x0050 ....0x0FFF 4535 ** . The Index Registers use a portion of the 80331 local memory to implement a large set of message registers. 4536 ** When one of the Index Registers is written, an interrupt is generated and the address of the register written is captured. 4537 ** Interrupt status for all interrupts is recorded in the Inbound Interrupt Status Register and the Outbound Interrupt Status Register. 4538 ** Each interrupt generated by the Messaging Unit can be masked. 4539 **-------------------- 4540 ** . Multi-DWORD PCI burst accesses are not supported by the Messaging Unit, 4541 ** with the exception of Multi-DWORD reads to the index registers. 4542 ** In Conventional mode: the MU terminates Multi-DWORD PCI transactions 4543 ** (other than index register reads) with a disconnect at the next Qword boundary, with the exception of queue ports. 4544 ** In PCI-X mode : the MU terminates a Multi-DWORD PCI read transaction with a Split Response 4545 ** and the data is returned through split completion transaction(s). 4546 ** however, when the burst request crosses into or through the range of offsets 40h to 4Ch 4547 ** (e.g., this includes the queue ports) the transaction is signaled target-abort immediately on the PCI bus. 4548 ** In PCI-X mode, Multi-DWORD PCI writes is signaled a Single-Data-Phase Disconnect 4549 ** which means that no data beyond the first Qword (Dword when the MU does not assert P_ACK64#) is written. 4550 **-------------------- 4551 ** . All registers needed to configure and control the Messaging Unit are memory-mapped registers. 4552 ** The MU uses the first 4 Kbytes of the inbound translation window in the Address Translation Unit (ATU). 4553 ** This PCI address window is used for PCI transactions that access the 80331 local memory. 4554 ** The PCI address of the inbound translation window is contained in the Inbound ATU Base Address Register. 4555 **-------------------- 4556 ** . From the PCI perspective, the Messaging Unit is part of the Address Translation Unit. 4557 ** The Messaging Unit uses the PCI configuration registers of the ATU for control and status information. 4558 ** The Messaging Unit must observe all PCI control bits in the ATU Command Register and ATU Configuration Register. 4559 ** The Messaging Unit reports all PCI errors in the ATU Status Register. 4560 **-------------------- 4561 ** . Parts of the Messaging Unit can be accessed as a 64-bit PCI device. 4562 ** The register interface, message registers, doorbell registers, 4563 ** and index registers returns a P_ACK64# in response to a P_REQ64# on the PCI interface. 4564 ** Up to 1 Qword of data can be read or written per transaction (except Index Register reads). 4565 ** The Inbound and Outbound Queue Ports are always 32-bit addresses and the MU does not assert P_ACK64# to offsets 40H and 44H. 4566 ************************************************************************** 4567 */ 4568 /* 4569 ************************************************************************** 4570 ** Message Registers 4571 ** ============================== 4572 ** . Messages can be sent and received by the 80331 through the use of the Message Registers. 4573 ** . When written, the message registers may cause an interrupt to be generated to either the Intel XScale core or the host processor. 4574 ** . Inbound messages are sent by the host processor and received by the 80331. 4575 ** Outbound messages are sent by the 80331 and received by the host processor. 4576 ** . The interrupt status for outbound messages is recorded in the Outbound Interrupt Status Register. 4577 ** Interrupt status for inbound messages is recorded in the Inbound Interrupt Status Register. 4578 ** 4579 ** Inbound Messages: 4580 ** ----------------- 4581 ** . When an inbound message register is written by an external PCI agent, an interrupt may be generated to the Intel XScale core. 4582 ** . The interrupt may be masked by the mask bits in the Inbound Interrupt Mask Register. 4583 ** . The Intel XScale core interrupt is recorded in the Inbound Interrupt Status Register. 4584 ** The interrupt causes the Inbound Message Interrupt bit to be set in the Inbound Interrupt Status Register. 4585 ** This is a Read/Clear bit that is set by the MU hardware and cleared by software. 4586 ** The interrupt is cleared when the Intel XScale core writes a value of 4587 ** 1 to the Inbound Message Interrupt bit in the Inbound Interrupt Status Register. 4588 ** ------------------------------------------------------------------------ 4589 ** Inbound Message Register - IMRx 4590 ** 4591 ** . There are two Inbound Message Registers: IMR0 and IMR1. 4592 ** . When the IMR register is written, an interrupt to the Intel XScale core may be generated. 4593 ** The interrupt is recorded in the Inbound Interrupt Status Register and may be masked 4594 ** by the Inbound Message Interrupt Mask bit in the Inbound Interrupt Mask Register. 4595 ** ----------------------------------------------------------------- 4596 ** Bit Default Description 4597 ** 31:00 0000 0000H Inbound Message - This is a 32-bit message written by an external PCI agent. 4598 ** When written, an interrupt to the Intel XScale core may be generated. 4599 ************************************************************************** 4600 */ 4601 #define ARCMSR_MU_INBOUND_MESSAGE_REG0 0x10 /*dword 0x13,0x12,0x11,0x10*/ 4602 #define ARCMSR_MU_INBOUND_MESSAGE_REG1 0x14 /*dword 0x17,0x16,0x15,0x14*/ 4603 /* 4604 ************************************************************************** 4605 ** Outbound Message Register - OMRx 4606 ** -------------------------------- 4607 ** There are two Outbound Message Registers: OMR0 and OMR1. When the OMR register is 4608 ** written, a PCI interrupt may be generated. The interrupt is recorded in the Outbound Interrupt 4609 ** Status Register and may be masked by the Outbound Message Interrupt Mask bit in the Outbound 4610 ** Interrupt Mask Register. 4611 ** 4612 ** Bit Default Description 4613 ** 31:00 00000000H Outbound Message - This is 32-bit message written by the Intel XScale core. When written, an 4614 ** interrupt may be generated on the PCI Interrupt pin determined by the ATU Interrupt Pin Register. 4615 ************************************************************************** 4616 */ 4617 #define ARCMSR_MU_OUTBOUND_MESSAGE_REG0 0x18 /*dword 0x1B,0x1A,0x19,0x18*/ 4618 #define ARCMSR_MU_OUTBOUND_MESSAGE_REG1 0x1C /*dword 0x1F,0x1E,0x1D,0x1C*/ 4619 /* 4620 ************************************************************************** 4621 ** Doorbell Registers 4622 ** ============================== 4623 ** There are two Doorbell Registers: 4624 ** Inbound Doorbell Register 4625 ** Outbound Doorbell Register 4626 ** The Inbound Doorbell Register allows external PCI agents to generate interrupts to the Intel R XScale core. 4627 ** The Outbound Doorbell Register allows the Intel R XScale core to generate a PCI interrupt. 4628 ** Both Doorbell Registers may generate interrupts whenever a bit in the register is set. 4629 ** 4630 ** Inbound Doorbells: 4631 ** ------------------ 4632 ** . When the Inbound Doorbell Register is written by an external PCI agent, an interrupt may be generated to the Intel R XScale core. 4633 ** An interrupt is generated when any of the bits in the doorbell register is written to a value of 1. 4634 ** Writing a value of 0 to any bit does not change the value of that bit and does not cause an interrupt to be generated. 4635 ** . Once a bit is set in the Inbound Doorbell Register, it cannot be cleared by any external PCI agent. 4636 ** The interrupt is recorded in the Inbound Interrupt Status Register. 4637 ** . The interrupt may be masked by the Inbound Doorbell Interrupt mask bit in the Inbound Interrupt Mask Register. 4638 ** When the mask bit is set for a particular bit, no interrupt is generated for that bit. 4639 ** The Inbound Interrupt Mask Register affects only the generation of the normal messaging unit interrupt 4640 ** and not the values written to the Inbound Doorbell Register. 4641 ** One bit in the Inbound Doorbell Register is reserved for an Error Doorbell interrupt. 4642 ** . The interrupt is cleared when the Intel R XScale core writes a value of 1 to the bits in the Inbound Doorbell Register that are set. 4643 ** Writing a value of 0 to any bit does not change the value of that bit and does not clear the interrupt. 4644 ** ------------------------------------------------------------------------ 4645 ** Inbound Doorbell Register - IDR 4646 ** 4647 ** . The Inbound Doorbell Register (IDR) is used to generate interrupts to the Intel XScale core. 4648 ** . Bit 31 is reserved for generating an Error Doorbell interrupt. 4649 ** When bit 31 is set, an Error interrupt may be generated to the Intel XScale core. 4650 ** All other bits, when set, cause the Normal Messaging Unit interrupt line of the Intel XScale core to be asserted, 4651 ** when the interrupt is not masked by the Inbound Doorbell Interrupt Mask bit in the Inbound Interrupt Mask Register. 4652 ** The bits in the IDR register can only be set by an external PCI agent and can only be cleared by the Intel XScale core. 4653 ** ------------------------------------------------------------------------ 4654 ** Bit Default Description 4655 ** 31 0 2 Error Interrupt - Generate an Error Interrupt to the Intel XScale core. 4656 ** 30:00 00000000H Normal Interrupt - When any bit is set, generate a Normal interrupt to the Intel XScale core. 4657 ** When all bits are clear, do not generate a Normal Interrupt. 4658 ************************************************************************** 4659 */ 4660 #define ARCMSR_MU_INBOUND_DOORBELL_REG 0x20 /*dword 0x23,0x22,0x21,0x20*/ 4661 /* 4662 ************************************************************************** 4663 ** Inbound Interrupt Status Register - IISR 4664 ** 4665 ** . The Inbound Interrupt Status Register (IISR) contains hardware interrupt status. 4666 ** It records the status of Intel XScale core interrupts generated by the Message Registers, Doorbell Registers, and the Circular Queues. 4667 ** All interrupts are routed to the Normal Messaging Unit interrupt input of the Intel XScale core, 4668 ** except for the Error Doorbell Interrupt and the Outbound Free Queue Full interrupt; 4669 ** these two are routed to the Messaging Unit Error interrupt input. 4670 ** The generation of interrupts recorded in the Inbound Interrupt Status Register 4671 ** may be masked by setting the corresponding bit in the Inbound Interrupt Mask Register. 4672 ** Some of the bits in this register are Read Only. 4673 ** For those bits, the interrupt must be cleared through another register. 4674 ** 4675 ** Bit Default Description 4676 ** 31:07 0000000H 0 2 Reserved 4677 ** 06 0 2 Index Register Interrupt - This bit is set by the MU hardware 4678 ** when an Index Register has been written after a PCI transaction. 4679 ** 05 0 2 Outbound Free Queue Full Interrupt - This bit is set 4680 ** when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full. 4681 ** An Error interrupt is generated for this condition. 4682 ** 04 0 2 Inbound Post Queue Interrupt - This bit is set by the MU hardware when the Inbound Post Queue has been written. 4683 ** Once cleared, an interrupt does NOT be generated 4684 ** when the head and tail pointers remain unequal (i.e. queue status is Not Empty). 4685 ** Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared, 4686 ** software must retain the information that the Inbound Post queue status is not empty. 4687 ** NOTE: This interrupt is provided with dedicated support in the 80331 Interrupt Controller. 4688 ** 03 0 2 Error Doorbell Interrupt - This bit is set when the Error Interrupt of the Inbound Doorbell Register is set. 4689 ** To clear this bit (and the interrupt), the Error Interrupt bit of the Inbound Doorbell Register must be clear. 4690 ** 02 0 2 Inbound Doorbell Interrupt - This bit is set when at least one 4691 ** Normal Interrupt bit in the Inbound Doorbell Register is set. 4692 ** To clear this bit (and the interrupt), the Normal Interrupt bits in the Inbound Doorbell Register must all be clear. 4693 ** 01 0 2 Inbound Message 1 Interrupt - This bit is set by the MU hardware when the Inbound Message 1 Register has been written. 4694 ** 00 0 2 Inbound Message 0 Interrupt - This bit is set by the MU hardware when the Inbound Message 0 Register has been written. 4695 ************************************************************************** 4696 */ 4697 #define ARCMSR_MU_INBOUND_INTERRUPT_STATUS_REG 0x24 /*dword 0x27,0x26,0x25,0x24*/ 4698 #define ARCMSR_MU_INBOUND_INDEX_INT 0x40 4699 #define ARCMSR_MU_INBOUND_QUEUEFULL_INT 0x20 4700 #define ARCMSR_MU_INBOUND_POSTQUEUE_INT 0x10 4701 #define ARCMSR_MU_INBOUND_ERROR_DOORBELL_INT 0x08 4702 #define ARCMSR_MU_INBOUND_DOORBELL_INT 0x04 4703 #define ARCMSR_MU_INBOUND_MESSAGE1_INT 0x02 4704 #define ARCMSR_MU_INBOUND_MESSAGE0_INT 0x01 4705 /* 4706 ************************************************************************** 4707 ** Inbound Interrupt Mask Register - IIMR 4708 ** 4709 ** . The Inbound Interrupt Mask Register (IIMR) provides the ability to mask Intel XScale core interrupts generated by the Messaging Unit. 4710 ** Each bit in the Mask register corresponds to an interrupt bit in the Inbound Interrupt Status Register. 4711 ** Setting or clearing bits in this register does not affect the Inbound Interrupt Status Register. 4712 ** They only affect the generation of the Intel XScale core interrupt. 4713 ** ------------------------------------------------------------------------ 4714 ** Bit Default Description 4715 ** 31:07 000000H 0 2 Reserved 4716 ** 06 0 2 Index Register Interrupt Mask - When set, this bit masks the interrupt generated by the MU hardware 4717 ** when an Index Register has been written after a PCI transaction. 4718 ** 05 0 2 Outbound Free Queue Full Interrupt Mask - When set, this bit masks the Error interrupt generated 4719 ** when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full. 4720 ** 04 0 2 Inbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated 4721 ** by the MU hardware when the Inbound Post Queue has been written. 4722 ** 03 0 2 Error Doorbell Interrupt Mask - When set, this bit masks the Error Interrupt 4723 ** when the Error Interrupt bit of the Inbound Doorbell Register is set. 4724 ** 02 0 2 Inbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated 4725 ** when at least one Normal Interrupt bit in the Inbound Doorbell Register is set. 4726 ** 01 0 2 Inbound Message 1 Interrupt Mask - When set, this bit masks the Inbound Message 1 4727 ** Interrupt generated by a write to the Inbound Message 1 Register. 4728 ** 00 0 2 Inbound Message 0 Interrupt Mask - When set, 4729 ** this bit masks the Inbound Message 0 Interrupt generated by a write to the Inbound Message 0 Register. 4730 ************************************************************************** 4731 */ 4732 #define ARCMSR_MU_INBOUND_INTERRUPT_MASK_REG 0x28 /*dword 0x2B,0x2A,0x29,0x28*/ 4733 #define ARCMSR_MU_INBOUND_INDEX_INTMASKENABLE 0x40 4734 #define ARCMSR_MU_INBOUND_QUEUEFULL_INTMASKENABLE 0x20 4735 #define ARCMSR_MU_INBOUND_POSTQUEUE_INTMASKENABLE 0x10 4736 #define ARCMSR_MU_INBOUND_DOORBELL_ERROR_INTMASKENABLE 0x08 4737 #define ARCMSR_MU_INBOUND_DOORBELL_INTMASKENABLE 0x04 4738 #define ARCMSR_MU_INBOUND_MESSAGE1_INTMASKENABLE 0x02 4739 #define ARCMSR_MU_INBOUND_MESSAGE0_INTMASKENABLE 0x01 4740 /* 4741 ************************************************************************** 4742 ** Outbound Doorbell Register - ODR 4743 ** 4744 ** The Outbound Doorbell Register (ODR) allows software interrupt generation. It allows the Intel 4745 ** XScale core to generate PCI interrupts to the host processor by writing to this register. The 4746 ** generation of PCI interrupts through the Outbound Doorbell Register may be masked by setting the 4747 ** Outbound Doorbell Interrupt Mask bit in the Outbound Interrupt Mask Register. 4748 ** The Software Interrupt bits in this register can only be set by the Intel XScale core and can only 4749 ** be cleared by an external PCI agent. 4750 ** ---------------------------------------------------------------------- 4751 ** Bit Default Description 4752 ** 31 0 2 Reserved 4753 ** 30 0 2 Reserved. 4754 ** 29 0 2 Reserved 4755 ** 28 0000 0000H PCI Interrupt - When set, this bit causes the P_INTC# interrupt output 4756 ** (P_INTA# with BRG_EN and ARB_EN straps low) 4757 ** signal to be asserted or a Message-signaled Interrupt is generated (when enabled). 4758 ** When this bit is cleared, the P_INTC# interrupt output 4759 ** (P_INTA# with BRG_EN and ARB_EN straps low) 4760 ** signal is deasserted. 4761 ** 27:00 000 0000H Software Interrupts - When any bit is set the P_INTC# interrupt output 4762 ** (P_INTA# with BRG_EN and ARB_EN straps low) 4763 ** signal is asserted or a Message-signaled Interrupt is generated (when enabled). 4764 ** When all bits are cleared, the P_INTC# interrupt output (P_INTA# with BRG_EN and ARB_EN straps low) 4765 ** signal is deasserted. 4766 ************************************************************************** 4767 */ 4768 #define ARCMSR_MU_OUTBOUND_DOORBELL_REG 0x2C /*dword 0x2F,0x2E,0x2D,0x2C*/ 4769 /* 4770 ************************************************************************** 4771 ** Outbound Interrupt Status Register - OISR 4772 ** 4773 ** The Outbound Interrupt Status Register (OISR) contains hardware interrupt status. It records the 4774 ** status of PCI interrupts generated by the Message Registers, Doorbell Registers, and the Circular 4775 ** Queues. The generation of PCI interrupts recorded in the Outbound Interrupt Status Register may 4776 ** be masked by setting the corresponding bit in the Outbound Interrupt Mask Register. Some of the 4777 ** bits in this register are Read Only. For those bits, the interrupt must be cleared through another 4778 ** register. 4779 ** ---------------------------------------------------------------------- 4780 ** Bit Default Description 4781 ** 31:05 000000H 000 2 Reserved 4782 ** 04 0 2 PCI Interrupt - This bit is set when the PCI Interrupt bit (bit 28) is set in the Outbound Doorbell Register. 4783 ** To clear this bit (and the interrupt), the PCI Interrupt bit must be cleared. 4784 ** 03 0 2 Outbound Post Queue Interrupt - This bit is set when data in the prefetch buffer is valid. This bit is 4785 ** cleared when any prefetch data has been read from the Outbound Queue Port. 4786 ** 02 0 2 Outbound Doorbell Interrupt - This bit is set when at least one Software Interrupt bit in the Outbound 4787 ** Doorbell Register is set. To clear this bit (and the interrupt), the Software Interrupt bits in the Outbound 4788 ** Doorbell Register must all be clear. 4789 ** 01 0 2 Outbound Message 1 Interrupt - This bit is set by the MU when the Outbound Message 1 Register is 4790 ** written. Clearing this bit clears the interrupt. 4791 ** 00 0 2 Outbound Message 0 Interrupt - This bit is set by the MU when the Outbound Message 0 Register is 4792 ** written. Clearing this bit clears the interrupt. 4793 ************************************************************************** 4794 */ 4795 #define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30 /*dword 0x33,0x32,0x31,0x30*/ 4796 #define ARCMSR_MU_OUTBOUND_PCI_INT 0x10 4797 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08 4798 #define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04 4799 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02 4800 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01 4801 /* 4802 ************************************************************************** 4803 ** Outbound Interrupt Mask Register - OIMR 4804 ** The Outbound Interrupt Mask Register (OIMR) provides the ability to mask outbound PCI 4805 ** interrupts generated by the Messaging Unit. Each bit in the mask register corresponds to a 4806 ** hardware interrupt bit in the Outbound Interrupt Status Register. When the bit is set, the PCI 4807 ** interrupt is not generated. When the bit is clear, the interrupt is allowed to be generated. 4808 ** Setting or clearing bits in this register does not affect the Outbound Interrupt Status Register. They 4809 ** only affect the generation of the PCI interrupt. 4810 ** ---------------------------------------------------------------------- 4811 ** Bit Default Description 4812 ** 31:05 000000H Reserved 4813 ** 04 0 2 PCI Interrupt Mask - When set, this bit masks the interrupt generation when the PCI Interrupt bit (bit 28) 4814 ** in the Outbound Doorbell Register is set. 4815 ** 03 0 2 Outbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated when data in 4816 ** the prefetch buffer is valid. 4817 ** 02 0 2 Outbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated by the Outbound 4818 ** Doorbell Register. 4819 ** 01 0 2 Outbound Message 1 Interrupt Mask - When set, this bit masks the Outbound Message 1 Interrupt 4820 ** generated by a write to the Outbound Message 1 Register. 4821 ** 00 0 2 Outbound Message 0 Interrupt Mask- When set, this bit masks the Outbound Message 0 Interrupt 4822 ** generated by a write to the Outbound Message 0 Register. 4823 ************************************************************************** 4824 */ 4825 #define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34 /*dword 0x37,0x36,0x35,0x34*/ 4826 #define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10 4827 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08 4828 #define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04 4829 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02 4830 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01 4831 #define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F 4832 /* 4833 ************************************************************************** 4834 ** 4835 ************************************************************************** 4836 */ 4837 #define ARCMSR_MU_INBOUND_QUEUE_PORT_REG 0x40 /*dword 0x43,0x42,0x41,0x40*/ 4838 #define ARCMSR_MU_OUTBOUND_QUEUE_PORT_REG 0x44 /*dword 0x47,0x46,0x45,0x44*/ 4839 /* 4840 ************************************************************************** 4841 ** Circular Queues 4842 ** ====================================================================== 4843 ** The MU implements four circular queues. There are 2 inbound queues and 2 outbound queues. In 4844 ** this case, inbound and outbound refer to the direction of the flow of posted messages. 4845 ** Inbound messages are either: 4846 ** �E posted messages by other processors for the Intel XScale core to process or 4847 ** �E free (or empty) messages that can be reused by other processors. 4848 ** Outbound messages are either: 4849 ** �E posted messages by the Intel XScale core for other processors to process or 4850 ** �E free (or empty) messages that can be reused by the Intel XScale core. 4851 ** Therefore, free inbound messages flow away from the 80331 and free outbound messages flow toward the 80331. 4852 ** The four Circular Queues are used to pass messages in the following manner. 4853 ** . The two inbound queues are used to handle inbound messages 4854 ** and the two outbound queues are used to handle outbound messages. 4855 ** . One of the inbound queues is designated the Free queue and it contains inbound free messages. 4856 ** The other inbound queue is designated the Post queue and it contains inbound posted messages. 4857 ** Similarly, one of the outbound queues is designated the Free queue and the other outbound queue is designated the Post queue. 4858 ** 4859 ** ============================================================================================================= 4860 ** Circular Queue Summary 4861 ** _____________________________________________________________________________________________________________ 4862 ** | Queue Name | Purpose | Action on PCI Interface| 4863 ** |______________________|____________________________________________________________|_________________________| 4864 ** |Inbound Post Queue | Queue for inbound messages from other processors | Written | 4865 ** | | waiting to be processed by the 80331 | | 4866 ** |Inbound Free Queue | Queue for empty inbound messages from the 80331 | Read | 4867 ** | | available for use by other processors | | 4868 ** |Outbound Post Queue | Queue for outbound messages from the 80331 | Read | 4869 ** | | that are being posted to the other processors | | 4870 ** |Outbound Free Queue | Queue for empty outbound messages from other processors | Written | 4871 ** | | available for use by the 80331 | | 4872 ** |______________________|____________________________________________________________|_________________________| 4873 ** 4874 ** . The two inbound queues allow the host processor to post inbound messages for the 80331 in one 4875 ** queue and to receive free messages returning from the 80331. 4876 ** The host processor posts inbound messages, 4877 ** the Intel XScale core receives the posted message and when it is finished with the message, 4878 ** places it back on the inbound free queue for reuse by the host processor. 4879 ** 4880 ** The circular queues are accessed by external PCI agents through two port locations in the PCI 4881 ** address space: 4882 ** Inbound Queue Port 4883 ** and Outbound Queue Port. 4884 ** The Inbound Queue Port is used by external PCI agents to read the Inbound Free Queue and write the Inbound Post Queue. 4885 ** The Outbound Queue Port is used by external PCI agents to read the Outbound Post Queue and write the Outbound Free Queue. 4886 ** Note that a PCI transaction to the inbound or outbound queue ports with null byte enables (P_C/BE[3:0]#=1111 2 ) 4887 ** does not cause the MU hardware to increment the queue pointers. 4888 ** This is treated as when the PCI transaction did not occur. 4889 ** The Inbound and Outbound Queue Ports never respond with P_ACK64# on the PCI interface. 4890 ** ====================================================================================== 4891 ** Overview of Circular Queue Operation 4892 ** ====================================================================================== 4893 ** . The data storage for the circular queues must be provided by the 80331 local memory. 4894 ** . The base address of the circular queues is contained in the Queue Base Address Register. 4895 ** Each entry in the queue is a 32-bit data value. 4896 ** . Each read from or write to the queue may access only one queue entry. 4897 ** . Multi-DWORD accesses to the circular queues are not allowed. 4898 ** Sub-DWORD accesses are promoted to DWORD accesses. 4899 ** . Each circular queue has a head pointer and a tail pointer. 4900 ** The pointers are offsets from the Queue Base Address. 4901 ** . Writes to a queue occur at the head of the queue and reads occur from the tail. 4902 ** The head and tail pointers are incremented by either the Intel XScale core or the Messaging Unit hardware. 4903 ** Which unit maintains the pointer is determined by the writer of the queue. 4904 ** More details about the pointers are given in the queue descriptions below. 4905 ** The pointers are incremented after the queue access. 4906 ** Both pointers wrap around to the first address of the circular queue when they reach the circular queue size. 4907 ** 4908 ** Messaging Unit... 4909 ** 4910 ** The Messaging Unit generates an interrupt to the Intel XScale core or generate a PCI interrupt under certain conditions. 4911 ** . In general, when a Post queue is written, an interrupt is generated to notify the receiver that a message was posted. 4912 ** The size of each circular queue can range from 4K entries (16 Kbytes) to 64K entries (256 Kbytes). 4913 ** . All four queues must be the same size and may be contiguous. 4914 ** Therefore, the total amount of local memory needed by the circular queues ranges from 64 Kbytes to 1 Mbytes. 4915 ** The Queue size is determined by the Queue Size field in the MU Configuration Register. 4916 ** . There is one base address for all four queues. 4917 ** It is stored in the Queue Base Address Register (QBAR). 4918 ** The starting addresses of each queue is based on the Queue Base Address and the Queue Size field. 4919 ** here shows an example of how the circular queues should be set up based on the 4920 ** Intelligent I/O (I 2 O) Architecture Specification. 4921 ** Other ordering of the circular queues is possible. 4922 ** 4923 ** Queue Starting Address 4924 ** Inbound Free Queue QBAR 4925 ** Inbound Post Queue QBAR + Queue Size 4926 ** Outbound Post Queue QBAR + 2 * Queue Size 4927 ** Outbound Free Queue QBAR + 3 * Queue Size 4928 ** =================================================================================== 4929 ** Inbound Post Queue 4930 ** ------------------ 4931 ** The Inbound Post Queue holds posted messages placed there by other processors for the Intel XScale core to process. 4932 ** This queue is read from the queue tail by the Intel XScale core. It is written to the queue head by external PCI agents. 4933 ** The tail pointer is maintained by the Intel XScale core. The head pointer is maintained by the MU hardware. 4934 ** For a PCI write transaction that accesses the Inbound Queue Port, 4935 ** the MU writes the data to the local memory location address in the Inbound Post Head Pointer Register. 4936 ** When the data written to the Inbound Queue Port is written to local memory, the MU hardware increments the Inbound Post Head Pointer Register. 4937 ** An Intel XScale core interrupt may be generated when the Inbound Post Queue is written. 4938 ** The Inbound Post Queue Interrupt bit in the Inbound Interrupt Status Register indicates the interrupt status. 4939 ** The interrupt is cleared when the Inbound Post Queue Interrupt bit is cleared. 4940 ** The interrupt can be masked by the Inbound Interrupt Mask Register. 4941 ** Software must be aware of the state of the Inbound Post Queue Interrupt Mask bit to guarantee 4942 ** that the full condition is recognized by the core processor. 4943 ** In addition, to guarantee that the queue does not get overwritten, 4944 ** software must process messages from the tail of the queue before incrementing the tail pointer and clearing this interrupt. 4945 ** Once cleared, an interrupt is NOT generated when the head and tail pointers remain unequal (i.e. queue status is Not Empty). 4946 ** Only a new message posting the in the inbound queue generates a new interrupt. 4947 ** Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared, 4948 ** software must retain the information that the Inbound Post queue status. 4949 ** From the time that the PCI write transaction is received until the data is written 4950 ** in local memory and the Inbound Post Head Pointer Register is incremented, 4951 ** any PCI transaction that attempts to access the Inbound Post Queue Port is signalled a Retry. 4952 ** The Intel XScale core may read messages from the Inbound Post Queue 4953 ** by reading the data from the local memory location pointed to by the Inbound Post Tail Pointer Register. 4954 ** The Intel XScale core must then increment the Inbound Post Tail Pointer Register. 4955 ** When the Inbound Post Queue is full (head and tail pointers are equal and the head pointer was last updated by hardware), 4956 ** the hardware retries any PCI writes until a slot in the queue becomes available. 4957 ** A slot in the post queue becomes available by the Intel XScale core incrementing the tail pointer. 4958 ** =================================================================================== 4959 ** Inbound Free Queue 4960 ** ------------------ 4961 ** The Inbound Free Queue holds free inbound messages placed there by the Intel XScale core for other processors to use. 4962 ** This queue is read from the queue tail by external PCI agents. 4963 ** It is written to the queue head by the Intel XScale core. 4964 ** The tail pointer is maintained by the MU hardware. 4965 ** The head pointer is maintained by the Intel XScale core. 4966 ** For a PCI read transaction that accesses the Inbound Queue Port, 4967 ** the MU attempts to read the data at the local memory address in the Inbound Free Tail Pointer. 4968 ** When the queue is not empty (head and tail pointers are not equal) 4969 ** or full (head and tail pointers are equal but the head pointer was last written by software), the data is returned. 4970 ** When the queue is empty (head and tail pointers are equal and the head pointer was last updated by hardware), 4971 ** the value of -1 (FFFF.FFFFH) is returned. 4972 ** When the queue was not empty and the MU succeeded in returning the data at the tail, 4973 ** the MU hardware must increment the value in the Inbound Free Tail Pointer Register. 4974 ** To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate accesses to the Inbound Free Queue. 4975 ** The MU hardware prefetches the data at the tail of the Inbound Free Queue and load it into an internal prefetch register. 4976 ** When the PCI read access occurs, the data is read directly from the prefetch register. 4977 ** The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register 4978 ** when the head and tail pointers are equal and the queue is empty. 4979 ** In order to update the prefetch register when messages are added to the queue and it becomes non-empty, 4980 ** the prefetch mechanism automatically starts a prefetch when the prefetch register contains FFFF.FFFFH 4981 ** and the Inbound Free Head Pointer Register is written. 4982 ** The Intel XScale core needs to update the Inbound Free Head Pointer Register when it adds messages to the queue. 4983 ** A prefetch must appear atomic from the perspective of the external PCI agent. 4984 ** When a prefetch is started, any PCI transaction that attempts to access the Inbound Free Queue is signalled a Retry until the prefetch is completed. 4985 ** The Intel XScale core may place messages in the Inbound Free Queue by writing the data to the 4986 ** local memory location pointed to by the Inbound Free Head Pointer Register. 4987 ** The processor must then increment the Inbound Free Head Pointer Register. 4988 ** ================================================================================== 4989 ** Outbound Post Queue 4990 ** ------------------- 4991 ** The Outbound Post Queue holds outbound posted messages placed there by the Intel XScale 4992 ** core for other processors to process. This queue is read from the queue tail by external PCI agents. 4993 ** It is written to the queue head by the Intel XScale core. The tail pointer is maintained by the 4994 ** MU hardware. The head pointer is maintained by the Intel XScale core. 4995 ** For a PCI read transaction that accesses the Outbound Queue Port, the MU attempts to read the 4996 ** data at the local memory address in the Outbound Post Tail Pointer Register. When the queue is not 4997 ** empty (head and tail pointers are not equal) or full (head and tail pointers are equal but the head 4998 ** pointer was last written by software), the data is returned. When the queue is empty (head and tail 4999 ** pointers are equal and the head pointer was last updated by hardware), the value of -1 5000 ** (FFFF.FFFFH) is returned. When the queue was not empty and the MU succeeded in returning the 5001 ** data at the tail, the MU hardware must increment the value in the Outbound Post Tail Pointer 5002 ** Register. 5003 ** To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate 5004 ** accesses to the Outbound Post Queue. The MU hardware prefetches the data at the tail of the 5005 ** Outbound Post Queue and load it into an internal prefetch register. When the PCI read access 5006 ** occurs, the data is read directly from the prefetch register. 5007 ** The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register when the head 5008 ** and tail pointers are equal and the queue is empty. In order to update the prefetch register when 5009 ** messages are added to the queue and it becomes non-empty, the prefetch mechanism automatically 5010 ** starts a prefetch when the prefetch register contains FFFF.FFFFH and the Outbound Post Head 5011 ** Pointer Register is written. The Intel XScale core needs to update the Outbound Post Head 5012 ** Pointer Register when it adds messages to the queue. 5013 ** A prefetch must appear atomic from the perspective of the external PCI agent. When a prefetch is 5014 ** started, any PCI transaction that attempts to access the Outbound Post Queue is signalled a Retry 5015 ** until the prefetch is completed. 5016 ** A PCI interrupt may be generated when data in the prefetch buffer is valid. When the prefetch 5017 ** queue is clear, no interrupt is generated. The Outbound Post Queue Interrupt bit in the Outbound 5018 ** Interrupt Status Register shall indicate the status of the prefetch buffer data and therefore the 5019 ** interrupt status. The interrupt is cleared when any prefetched data has been read from the Outbound 5020 ** Queue Port. The interrupt can be masked by the Outbound Interrupt Mask Register. 5021 ** The Intel XScale core may place messages in the Outbound Post Queue by writing the data to 5022 ** the local memory address in the Outbound Post Head Pointer Register. The processor must then 5023 ** increment the Outbound Post Head Pointer Register. 5024 ** ================================================== 5025 ** Outbound Free Queue 5026 ** ----------------------- 5027 ** The Outbound Free Queue holds free messages placed there by other processors for the Intel 5028 ** XScale core to use. This queue is read from the queue tail by the Intel XScale core. It is 5029 ** written to the queue head by external PCI agents. The tail pointer is maintained by the Intel 5030 ** XScale core. The head pointer is maintained by the MU hardware. 5031 ** For a PCI write transaction that accesses the Outbound Queue Port, the MU writes the data to the 5032 ** local memory address in the Outbound Free Head Pointer Register. When the data written to the 5033 ** Outbound Queue Port is written to local memory, the MU hardware increments the Outbound Free 5034 ** Head Pointer Register. 5035 ** When the head pointer and the tail pointer become equal and the queue is full, the MU may signal 5036 ** an interrupt to the Intel XScale core to register the queue full condition. This interrupt is 5037 ** recorded in the Inbound Interrupt Status Register. The interrupt is cleared when the Outbound Free 5038 ** Queue Full Interrupt bit is cleared and not by writing to the head or tail pointers. The interrupt can 5039 ** be masked by the Inbound Interrupt Mask Register. Software must be aware of the state of the 5040 ** Outbound Free Queue Interrupt Mask bit to guarantee that the full condition is recognized by the 5041 ** core processor. 5042 ** From the time that a PCI write transaction is received until the data is written in local memory and 5043 ** the Outbound Free Head Pointer Register is incremented, any PCI transaction that attempts to 5044 ** access the Outbound Free Queue Port is signalled a retry. 5045 ** The Intel XScale core may read messages from the Outbound Free Queue by reading the data 5046 ** from the local memory address in the Outbound Free Tail Pointer Register. The processor must 5047 ** then increment the Outbound Free Tail Pointer Register. When the Outbound Free Queue is full, 5048 ** the hardware must retry any PCI writes until a slot in the queue becomes available. 5049 ** 5050 ** ================================================================================== 5051 ** Circular Queue Summary 5052 ** ---------------------- 5053 ** ________________________________________________________________________________________________________________________________________________ 5054 ** | Queue Name | PCI Port |Generate PCI Interrupt |Generate Intel Xscale Core Interrupt|Head Pointer maintained by|Tail Pointer maintained by| 5055 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 5056 ** |Inbound Post | Inbound Queue | | | | | 5057 ** | Queue | Port | NO | Yes, when queue is written | MU hardware | Intel XScale | 5058 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 5059 ** |Inbound Free | Inbound Queue | | | | | 5060 ** | Queue | Port | NO | NO | Intel XScale | MU hardware | 5061 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 5062 ** ================================================================================== 5063 ** Circular Queue Status Summary 5064 ** ---------------------- 5065 ** ____________________________________________________________________________________________________ 5066 ** | Queue Name | Queue Status | Head & Tail Pointer | Last Pointer Update | 5067 ** |_____________________|________________|_____________________|_______________________________________| 5068 ** | Inbound Post Queue | Empty | Equal | Tail pointer last updated by software | 5069 ** |_____________________|________________|_____________________|_______________________________________| 5070 ** | Inbound Free Queue | Empty | Equal | Head pointer last updated by hardware | 5071 ** |_____________________|________________|_____________________|_______________________________________| 5072 ************************************************************************** 5073 */ 5074 5075 /* 5076 ************************************************************************** 5077 ** Index Registers 5078 ** ======================== 5079 ** . The Index Registers are a set of 1004 registers that when written by an external PCI agent can generate an interrupt to the Intel XScale core. 5080 ** These registers are for inbound messages only. 5081 ** The interrupt is recorded in the Inbound Interrupt Status Register. 5082 ** The storage for the Index Registers is allocated from the 80331 local memory. 5083 ** PCI write accesses to the Index Registers write the data to local memory. 5084 ** PCI read accesses to the Index Registers read the data from local memory. 5085 ** . The local memory used for the Index Registers ranges from Inbound ATU Translate Value Register + 050H 5086 ** to Inbound ATU Translate Value Register + FFFH. 5087 ** . The address of the first write access is stored in the Index Address Register. 5088 ** This register is written during the earliest write access and provides a means to determine which Index Register was written. 5089 ** Once updated by the MU, the Index Address Register is not updated until the Index Register 5090 ** Interrupt bit in the Inbound Interrupt Status Register is cleared. 5091 ** . When the interrupt is cleared, the Index Address Register is re-enabled and stores the address of the next Index Register write access. 5092 ** Writes by the Intel XScale core to the local memory used by the Index Registers 5093 ** does not cause an interrupt and does not update the Index Address Register. 5094 ** . The index registers can be accessed with Multi-DWORD reads and single QWORD aligned writes. 5095 ************************************************************************** 5096 */ 5097 /* 5098 ************************************************************************** 5099 ** Messaging Unit Internal Bus Memory Map 5100 ** ======================================= 5101 ** Internal Bus Address___Register Description (Name)____________________|_PCI Configuration Space Register Number_ 5102 ** FFFF E300H reserved | 5103 ** .. .. | 5104 ** FFFF E30CH reserved | 5105 ** FFFF E310H Inbound Message Register 0 | Available through 5106 ** FFFF E314H Inbound Message Register 1 | ATU Inbound Translation Window 5107 ** FFFF E318H Outbound Message Register 0 | 5108 ** FFFF E31CH Outbound Message Register 1 | or 5109 ** FFFF E320H Inbound Doorbell Register | 5110 ** FFFF E324H Inbound Interrupt Status Register | must translate PCI address to 5111 ** FFFF E328H Inbound Interrupt Mask Register | the Intel Xscale Core 5112 ** FFFF E32CH Outbound Doorbell Register | Memory-Mapped Address 5113 ** FFFF E330H Outbound Interrupt Status Register | 5114 ** FFFF E334H Outbound Interrupt Mask Register | 5115 ** ______________________________________________________________________|________________________________________ 5116 ** FFFF E338H reserved | 5117 ** FFFF E33CH reserved | 5118 ** FFFF E340H reserved | 5119 ** FFFF E344H reserved | 5120 ** FFFF E348H reserved | 5121 ** FFFF E34CH reserved | 5122 ** FFFF E350H MU Configuration Register | 5123 ** FFFF E354H Queue Base Address Register | 5124 ** FFFF E358H reserved | 5125 ** FFFF E35CH reserved | must translate PCI address to 5126 ** FFFF E360H Inbound Free Head Pointer Register | the Intel Xscale Core 5127 ** FFFF E364H Inbound Free Tail Pointer Register | Memory-Mapped Address 5128 ** FFFF E368H Inbound Post Head pointer Register | 5129 ** FFFF E36CH Inbound Post Tail Pointer Register | 5130 ** FFFF E370H Outbound Free Head Pointer Register | 5131 ** FFFF E374H Outbound Free Tail Pointer Register | 5132 ** FFFF E378H Outbound Post Head pointer Register | 5133 ** FFFF E37CH Outbound Post Tail Pointer Register | 5134 ** FFFF E380H Index Address Register | 5135 ** FFFF E384H reserved | 5136 ** .. .. | 5137 ** FFFF E3FCH reserved | 5138 ** ______________________________________________________________________|_______________________________________ 5139 ************************************************************************** 5140 */ 5141 /* 5142 ************************************************************************** 5143 ** MU Configuration Register - MUCR FFFF.E350H 5144 ** 5145 ** . The MU Configuration Register (MUCR) contains the Circular Queue Enable bit and the size of one Circular Queue. 5146 ** . The Circular Queue Enable bit enables or disables the Circular Queues. 5147 ** The Circular Queues are disabled at reset to allow the software to initialize the head 5148 ** and tail pointer registers before any PCI accesses to the Queue Ports. 5149 ** . Each Circular Queue may range from 4 K entries (16 Kbytes) to 64 K entries (256 Kbytes) and there are four Circular Queues. 5150 ** ------------------------------------------------------------------------ 5151 ** Bit Default Description 5152 ** 31:06 000000H 00 2 Reserved 5153 ** 05:01 00001 2 Circular Queue Size - This field determines the size of each Circular Queue. 5154 ** All four queues are the same size. 5155 ** �E 00001 2 - 4K Entries (16 Kbytes) 5156 ** �E 00010 2 - 8K Entries (32 Kbytes) 5157 ** �E 00100 2 - 16K Entries (64 Kbytes) 5158 ** �E 01000 2 - 32K Entries (128 Kbytes) 5159 ** �E 10000 2 - 64K Entries (256 Kbytes) 5160 ** 00 0 2 Circular Queue Enable - This bit enables or disables the Circular Queues. When clear the Circular 5161 ** Queues are disabled, however the MU accepts PCI accesses to the Circular Queue Ports but ignores 5162 ** the data for Writes and return FFFF.FFFFH for Reads. Interrupts are not generated to the core when 5163 ** disabled. When set, the Circular Queues are fully enabled. 5164 ************************************************************************** 5165 */ 5166 #define ARCMSR_MU_CONFIGURATION_REG 0xFFFFE350 5167 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE64K 0x0020 5168 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE32K 0x0010 5169 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE16K 0x0008 5170 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE8K 0x0004 5171 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE4K 0x0002 5172 #define ARCMSR_MU_CIRCULAR_QUEUE_ENABLE 0x0001 /*0:disable 1:enable*/ 5173 /* 5174 ************************************************************************** 5175 ** Queue Base Address Register - QBAR 5176 ** 5177 ** . The Queue Base Address Register (QBAR) contains the local memory address of the Circular Queues. 5178 ** The base address is required to be located on a 1 Mbyte address boundary. 5179 ** . All Circular Queue head and tail pointers are based on the QBAR. 5180 ** When the head and tail pointer registers are read, the Queue Base Address is returned in the upper 12 bits. 5181 ** Writing to the upper 12 bits of the head and tail pointer registers does not affect the Queue Base Address or Queue Base Address Register. 5182 ** Warning: 5183 ** The QBAR must designate a range allocated to the 80331 DDR SDRAM interface 5184 ** ------------------------------------------------------------------------ 5185 ** Bit Default Description 5186 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5187 ** 19:00 00000H Reserved 5188 ************************************************************************** 5189 */ 5190 #define ARCMSR_MU_QUEUE_BASE_ADDRESS_REG 0xFFFFE354 5191 /* 5192 ************************************************************************** 5193 ** Inbound Free Head Pointer Register - IFHPR 5194 ** 5195 ** . The Inbound Free Head Pointer Register (IFHPR) contains the local memory offset from 5196 ** the Queue Base Address of the head pointer for the Inbound Free Queue. 5197 ** The Head Pointer must be aligned on a DWORD address boundary. 5198 ** When read, the Queue Base Address is provided in the upper 12 bits of the register. 5199 ** Writes to the upper 12 bits of the register are ignored. 5200 ** This register is maintained by software. 5201 ** ------------------------------------------------------------------------ 5202 ** Bit Default Description 5203 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5204 ** 19:02 0000H 00 2 Inbound Free Head Pointer - Local memory offset of the head pointer for the Inbound Free Queue. 5205 ** 01:00 00 2 Reserved 5206 ************************************************************************** 5207 */ 5208 #define ARCMSR_MU_INBOUND_FREE_HEAD_PTR_REG 0xFFFFE360 5209 /* 5210 ************************************************************************** 5211 ** Inbound Free Tail Pointer Register - IFTPR 5212 ** 5213 ** . The Inbound Free Tail Pointer Register (IFTPR) contains the local memory offset from the Queue 5214 ** Base Address of the tail pointer for the Inbound Free Queue. The Tail Pointer must be aligned on a 5215 ** DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 5216 ** of the register. Writes to the upper 12 bits of the register are ignored. 5217 ** ------------------------------------------------------------------------ 5218 ** Bit Default Description 5219 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5220 ** 19:02 0000H 00 2 Inbound Free Tail Pointer - Local memory offset of the tail pointer for the Inbound Free Queue. 5221 ** 01:00 00 2 Reserved 5222 ************************************************************************** 5223 */ 5224 #define ARCMSR_MU_INBOUND_FREE_TAIL_PTR_REG 0xFFFFE364 5225 /* 5226 ************************************************************************** 5227 ** Inbound Post Head Pointer Register - IPHPR 5228 ** 5229 ** . The Inbound Post Head Pointer Register (IPHPR) contains the local memory offset from the Queue 5230 ** Base Address of the head pointer for the Inbound Post Queue. The Head Pointer must be aligned on 5231 ** a DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 5232 ** of the register. Writes to the upper 12 bits of the register are ignored. 5233 ** ------------------------------------------------------------------------ 5234 ** Bit Default Description 5235 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5236 ** 19:02 0000H 00 2 Inbound Post Head Pointer - Local memory offset of the head pointer for the Inbound Post Queue. 5237 ** 01:00 00 2 Reserved 5238 ************************************************************************** 5239 */ 5240 #define ARCMSR_MU_INBOUND_POST_HEAD_PTR_REG 0xFFFFE368 5241 /* 5242 ************************************************************************** 5243 ** Inbound Post Tail Pointer Register - IPTPR 5244 ** 5245 ** . The Inbound Post Tail Pointer Register (IPTPR) contains the local memory offset from the Queue 5246 ** Base Address of the tail pointer for the Inbound Post Queue. The Tail Pointer must be aligned on a 5247 ** DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 5248 ** of the register. Writes to the upper 12 bits of the register are ignored. 5249 ** ------------------------------------------------------------------------ 5250 ** Bit Default Description 5251 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5252 ** 19:02 0000H 00 2 Inbound Post Tail Pointer - Local memory offset of the tail pointer for the Inbound Post Queue. 5253 ** 01:00 00 2 Reserved 5254 ************************************************************************** 5255 */ 5256 #define ARCMSR_MU_INBOUND_POST_TAIL_PTR_REG 0xFFFFE36C 5257 /* 5258 ************************************************************************** 5259 ** Index Address Register - IAR 5260 ** 5261 ** . The Index Address Register (IAR) contains the offset of the least recently accessed Index Register. 5262 ** It is written by the MU when the Index Registers are written by a PCI agent. 5263 ** The register is not updated until the Index Interrupt bit in the Inbound Interrupt Status Register is cleared. 5264 ** . The local memory address of the Index Register least recently accessed is computed 5265 ** by adding the Index Address Register to the Inbound ATU Translate Value Register. 5266 ** ------------------------------------------------------------------------ 5267 ** Bit Default Description 5268 ** 31:12 000000H Reserved 5269 ** 11:02 00H 00 2 Index Address - is the local memory offset of the Index Register written (050H to FFCH) 5270 ** 01:00 00 2 Reserved 5271 ************************************************************************** 5272 */ 5273 #define ARCMSR_MU_LOCAL_MEMORY_INDEX_REG 0xFFFFE380 /*1004 dwords 0x0050....0x0FFC, 4016 bytes 0x0050...0x0FFF*/ 5274 /* 5275 ********************************************************************************************************** 5276 ** RS-232 Interface for Areca Raid Controller 5277 ** The low level command interface is exclusive with VT100 terminal 5278 ** -------------------------------------------------------------------- 5279 ** 1. Sequence of command execution 5280 ** -------------------------------------------------------------------- 5281 ** (A) Header : 3 bytes sequence (0x5E, 0x01, 0x61) 5282 ** (B) Command block : variable length of data including length, command code, data and checksum byte 5283 ** (C) Return data : variable length of data 5284 ** -------------------------------------------------------------------- 5285 ** 2. Command block 5286 ** -------------------------------------------------------------------- 5287 ** (A) 1st byte : command block length (low byte) 5288 ** (B) 2nd byte : command block length (high byte) 5289 ** note ..command block length shouldn't > 2040 bytes, length excludes these two bytes 5290 ** (C) 3rd byte : command code 5291 ** (D) 4th and following bytes : variable length data bytes depends on command code 5292 ** (E) last byte : checksum byte (sum of 1st byte until last data byte) 5293 ** -------------------------------------------------------------------- 5294 ** 3. Command code and associated data 5295 ** -------------------------------------------------------------------- 5296 ** The following are command code defined in raid controller Command code 0x10--0x1? are used for system level management, 5297 ** no password checking is needed and should be implemented in separate well controlled utility and not for end user access. 5298 ** Command code 0x20--0x?? always check the password, password must be entered to enable these command. 5299 ** enum 5300 ** { 5301 ** GUI_SET_SERIAL=0x10, 5302 ** GUI_SET_VENDOR, 5303 ** GUI_SET_MODEL, 5304 ** GUI_IDENTIFY, 5305 ** GUI_CHECK_PASSWORD, 5306 ** GUI_LOGOUT, 5307 ** GUI_HTTP, 5308 ** GUI_SET_ETHERNET_ADDR, 5309 ** GUI_SET_LOGO, 5310 ** GUI_POLL_EVENT, 5311 ** GUI_GET_EVENT, 5312 ** GUI_GET_HW_MONITOR, 5313 ** 5314 ** // GUI_QUICK_CREATE=0x20, (function removed) 5315 ** GUI_GET_INFO_R=0x20, 5316 ** GUI_GET_INFO_V, 5317 ** GUI_GET_INFO_P, 5318 ** GUI_GET_INFO_S, 5319 ** GUI_CLEAR_EVENT, 5320 ** 5321 ** GUI_MUTE_BEEPER=0x30, 5322 ** GUI_BEEPER_SETTING, 5323 ** GUI_SET_PASSWORD, 5324 ** GUI_HOST_INTERFACE_MODE, 5325 ** GUI_REBUILD_PRIORITY, 5326 ** GUI_MAX_ATA_MODE, 5327 ** GUI_RESET_CONTROLLER, 5328 ** GUI_COM_PORT_SETTING, 5329 ** GUI_NO_OPERATION, 5330 ** GUI_DHCP_IP, 5331 ** 5332 ** GUI_CREATE_PASS_THROUGH=0x40, 5333 ** GUI_MODIFY_PASS_THROUGH, 5334 ** GUI_DELETE_PASS_THROUGH, 5335 ** GUI_IDENTIFY_DEVICE, 5336 ** 5337 ** GUI_CREATE_RAIDSET=0x50, 5338 ** GUI_DELETE_RAIDSET, 5339 ** GUI_EXPAND_RAIDSET, 5340 ** GUI_ACTIVATE_RAIDSET, 5341 ** GUI_CREATE_HOT_SPARE, 5342 ** GUI_DELETE_HOT_SPARE, 5343 ** 5344 ** GUI_CREATE_VOLUME=0x60, 5345 ** GUI_MODIFY_VOLUME, 5346 ** GUI_DELETE_VOLUME, 5347 ** GUI_START_CHECK_VOLUME, 5348 ** GUI_STOP_CHECK_VOLUME 5349 ** }; 5350 ** 5351 ** Command description : 5352 ** 5353 ** GUI_SET_SERIAL : Set the controller serial# 5354 ** byte 0,1 : length 5355 ** byte 2 : command code 0x10 5356 ** byte 3 : password length (should be 0x0f) 5357 ** byte 4-0x13 : should be "ArEcATecHnoLogY" 5358 ** byte 0x14--0x23 : Serial number string (must be 16 bytes) 5359 ** GUI_SET_VENDOR : Set vendor string for the controller 5360 ** byte 0,1 : length 5361 ** byte 2 : command code 0x11 5362 ** byte 3 : password length (should be 0x08) 5363 ** byte 4-0x13 : should be "ArEcAvAr" 5364 ** byte 0x14--0x3B : vendor string (must be 40 bytes) 5365 ** GUI_SET_MODEL : Set the model name of the controller 5366 ** byte 0,1 : length 5367 ** byte 2 : command code 0x12 5368 ** byte 3 : password length (should be 0x08) 5369 ** byte 4-0x13 : should be "ArEcAvAr" 5370 ** byte 0x14--0x1B : model string (must be 8 bytes) 5371 ** GUI_IDENTIFY : Identify device 5372 ** byte 0,1 : length 5373 ** byte 2 : command code 0x13 5374 ** return "Areca RAID Subsystem " 5375 ** GUI_CHECK_PASSWORD : Verify password 5376 ** byte 0,1 : length 5377 ** byte 2 : command code 0x14 5378 ** byte 3 : password length 5379 ** byte 4-0x?? : user password to be checked 5380 ** GUI_LOGOUT : Logout GUI (force password checking on next command) 5381 ** byte 0,1 : length 5382 ** byte 2 : command code 0x15 5383 ** GUI_HTTP : HTTP interface (reserved for Http proxy service)(0x16) 5384 ** 5385 ** GUI_SET_ETHERNET_ADDR : Set the ethernet MAC address 5386 ** byte 0,1 : length 5387 ** byte 2 : command code 0x17 5388 ** byte 3 : password length (should be 0x08) 5389 ** byte 4-0x13 : should be "ArEcAvAr" 5390 ** byte 0x14--0x19 : Ethernet MAC address (must be 6 bytes) 5391 ** GUI_SET_LOGO : Set logo in HTTP 5392 ** byte 0,1 : length 5393 ** byte 2 : command code 0x18 5394 ** byte 3 : Page# (0/1/2/3) (0xff --> clear OEM logo) 5395 ** byte 4/5/6/7 : 0x55/0xaa/0xa5/0x5a 5396 ** byte 8 : TITLE.JPG data (each page must be 2000 bytes) 5397 ** note .... page0 1st 2 byte must be actual length of the JPG file 5398 ** GUI_POLL_EVENT : Poll If Event Log Changed 5399 ** byte 0,1 : length 5400 ** byte 2 : command code 0x19 5401 ** GUI_GET_EVENT : Read Event 5402 ** byte 0,1 : length 5403 ** byte 2 : command code 0x1a 5404 ** byte 3 : Event Page (0:1st page/1/2/3:last page) 5405 ** GUI_GET_HW_MONITOR : Get HW monitor data 5406 ** byte 0,1 : length 5407 ** byte 2 : command code 0x1b 5408 ** byte 3 : # of FANs(example 2) 5409 ** byte 4 : # of Voltage sensor(example 3) 5410 ** byte 5 : # of temperature sensor(example 2) 5411 ** byte 6 : # of power 5412 ** byte 7/8 : Fan#0 (RPM) 5413 ** byte 9/10 : Fan#1 5414 ** byte 11/12 : Voltage#0 original value in *1000 5415 ** byte 13/14 : Voltage#0 value 5416 ** byte 15/16 : Voltage#1 org 5417 ** byte 17/18 : Voltage#1 5418 ** byte 19/20 : Voltage#2 org 5419 ** byte 21/22 : Voltage#2 5420 ** byte 23 : Temp#0 5421 ** byte 24 : Temp#1 5422 ** byte 25 : Power indicator (bit0 : power#0, bit1 : power#1) 5423 ** byte 26 : UPS indicator 5424 ** GUI_QUICK_CREATE : Quick create raid/volume set 5425 ** byte 0,1 : length 5426 ** byte 2 : command code 0x20 5427 ** byte 3/4/5/6 : raw capacity 5428 ** byte 7 : raid level 5429 ** byte 8 : stripe size 5430 ** byte 9 : spare 5431 ** byte 10/11/12/13: device mask (the devices to create raid/volume) 5432 ** This function is removed, application like to implement quick create function 5433 ** need to use GUI_CREATE_RAIDSET and GUI_CREATE_VOLUMESET function. 5434 ** GUI_GET_INFO_R : Get Raid Set Information 5435 ** byte 0,1 : length 5436 ** byte 2 : command code 0x20 5437 ** byte 3 : raidset# 5438 ** 5439 ** typedef struct sGUI_RAIDSET 5440 ** { 5441 ** BYTE grsRaidSetName[16]; 5442 ** DWORD grsCapacity; 5443 ** DWORD grsCapacityX; 5444 ** DWORD grsFailMask; 5445 ** BYTE grsDevArray[32]; 5446 ** BYTE grsMemberDevices; 5447 ** BYTE grsNewMemberDevices; 5448 ** BYTE grsRaidState; 5449 ** BYTE grsVolumes; 5450 ** BYTE grsVolumeList[16]; 5451 ** BYTE grsRes1; 5452 ** BYTE grsRes2; 5453 ** BYTE grsRes3; 5454 ** BYTE grsFreeSegments; 5455 ** DWORD grsRawStripes[8]; 5456 ** DWORD grsRes4; 5457 ** DWORD grsRes5; // Total to 128 bytes 5458 ** DWORD grsRes6; // Total to 128 bytes 5459 ** } sGUI_RAIDSET, *pGUI_RAIDSET; 5460 ** GUI_GET_INFO_V : Get Volume Set Information 5461 ** byte 0,1 : length 5462 ** byte 2 : command code 0x21 5463 ** byte 3 : volumeset# 5464 ** 5465 ** typedef struct sGUI_VOLUMESET 5466 ** { 5467 ** BYTE gvsVolumeName[16]; // 16 5468 ** DWORD gvsCapacity; 5469 ** DWORD gvsCapacityX; 5470 ** DWORD gvsFailMask; 5471 ** DWORD gvsStripeSize; 5472 ** DWORD gvsNewFailMask; 5473 ** DWORD gvsNewStripeSize; 5474 ** DWORD gvsVolumeStatus; 5475 ** DWORD gvsProgress; // 32 5476 ** sSCSI_ATTR gvsScsi; 5477 ** BYTE gvsMemberDisks; 5478 ** BYTE gvsRaidLevel; // 8 5479 ** 5480 ** BYTE gvsNewMemberDisks; 5481 ** BYTE gvsNewRaidLevel; 5482 ** BYTE gvsRaidSetNumber; 5483 ** BYTE gvsRes0; // 4 5484 ** BYTE gvsRes1[4]; // 64 bytes 5485 ** } sGUI_VOLUMESET, *pGUI_VOLUMESET; 5486 ** 5487 ** GUI_GET_INFO_P : Get Physical Drive Information 5488 ** byte 0,1 : length 5489 ** byte 2 : command code 0x22 5490 ** byte 3 : drive # (from 0 to max-channels - 1) 5491 ** 5492 ** typedef struct sGUI_PHY_DRV 5493 ** { 5494 ** BYTE gpdModelName[40]; 5495 ** BYTE gpdSerialNumber[20]; 5496 ** BYTE gpdFirmRev[8]; 5497 ** DWORD gpdCapacity; 5498 ** DWORD gpdCapacityX; // Reserved for expansion 5499 ** BYTE gpdDeviceState; 5500 ** BYTE gpdPioMode; 5501 ** BYTE gpdCurrentUdmaMode; 5502 ** BYTE gpdUdmaMode; 5503 ** BYTE gpdDriveSelect; 5504 ** BYTE gpdRaidNumber; // 0xff if not belongs to a raid set 5505 ** sSCSI_ATTR gpdScsi; 5506 ** BYTE gpdReserved[40]; // Total to 128 bytes 5507 ** } sGUI_PHY_DRV, *pGUI_PHY_DRV; 5508 ** 5509 ** GUI_GET_INFO_S : Get System Information 5510 ** byte 0,1 : length 5511 ** byte 2 : command code 0x23 5512 ** 5513 ** typedef struct sCOM_ATTR 5514 ** { 5515 ** BYTE comBaudRate; 5516 ** BYTE comDataBits; 5517 ** BYTE comStopBits; 5518 ** BYTE comParity; 5519 ** BYTE comFlowControl; 5520 ** } sCOM_ATTR, *pCOM_ATTR; 5521 ** 5522 ** typedef struct sSYSTEM_INFO 5523 ** { 5524 ** BYTE gsiVendorName[40]; 5525 ** BYTE gsiSerialNumber[16]; 5526 ** BYTE gsiFirmVersion[16]; 5527 ** BYTE gsiBootVersion[16]; 5528 ** BYTE gsiMbVersion[16]; 5529 ** BYTE gsiModelName[8]; 5530 ** BYTE gsiLocalIp[4]; 5531 ** BYTE gsiCurrentIp[4]; 5532 ** DWORD gsiTimeTick; 5533 ** DWORD gsiCpuSpeed; 5534 ** DWORD gsiICache; 5535 ** DWORD gsiDCache; 5536 ** DWORD gsiScache; 5537 ** DWORD gsiMemorySize; 5538 ** DWORD gsiMemorySpeed; 5539 ** DWORD gsiEvents; 5540 ** BYTE gsiMacAddress[6]; 5541 ** BYTE gsiDhcp; 5542 ** BYTE gsiBeeper; 5543 ** BYTE gsiChannelUsage; 5544 ** BYTE gsiMaxAtaMode; 5545 ** BYTE gsiSdramEcc; // 1:if ECC enabled 5546 ** BYTE gsiRebuildPriority; 5547 ** sCOM_ATTR gsiComA; // 5 bytes 5548 ** sCOM_ATTR gsiComB; // 5 bytes 5549 ** BYTE gsiIdeChannels; 5550 ** BYTE gsiScsiHostChannels; 5551 ** BYTE gsiIdeHostChannels; 5552 ** BYTE gsiMaxVolumeSet; 5553 ** BYTE gsiMaxRaidSet; 5554 ** BYTE gsiEtherPort; // 1:if ether net port supported 5555 ** BYTE gsiRaid6Engine; // 1:Raid6 engine supported 5556 ** BYTE gsiRes[75]; 5557 ** } sSYSTEM_INFO, *pSYSTEM_INFO; 5558 ** 5559 ** GUI_CLEAR_EVENT : Clear System Event 5560 ** byte 0,1 : length 5561 ** byte 2 : command code 0x24 5562 ** 5563 ** GUI_MUTE_BEEPER : Mute current beeper 5564 ** byte 0,1 : length 5565 ** byte 2 : command code 0x30 5566 ** 5567 ** GUI_BEEPER_SETTING : Disable beeper 5568 ** byte 0,1 : length 5569 ** byte 2 : command code 0x31 5570 ** byte 3 : 0->disable, 1->enable 5571 ** 5572 ** GUI_SET_PASSWORD : Change password 5573 ** byte 0,1 : length 5574 ** byte 2 : command code 0x32 5575 ** byte 3 : pass word length ( must <= 15 ) 5576 ** byte 4 : password (must be alpha-numerical) 5577 ** 5578 ** GUI_HOST_INTERFACE_MODE : Set host interface mode 5579 ** byte 0,1 : length 5580 ** byte 2 : command code 0x33 5581 ** byte 3 : 0->Independent, 1->cluster 5582 ** 5583 ** GUI_REBUILD_PRIORITY : Set rebuild priority 5584 ** byte 0,1 : length 5585 ** byte 2 : command code 0x34 5586 ** byte 3 : 0/1/2/3 (low->high) 5587 ** 5588 ** GUI_MAX_ATA_MODE : Set maximum ATA mode to be used 5589 ** byte 0,1 : length 5590 ** byte 2 : command code 0x35 5591 ** byte 3 : 0/1/2/3 (133/100/66/33) 5592 ** 5593 ** GUI_RESET_CONTROLLER : Reset Controller 5594 ** byte 0,1 : length 5595 ** byte 2 : command code 0x36 5596 ** *Response with VT100 screen (discard it) 5597 ** 5598 ** GUI_COM_PORT_SETTING : COM port setting 5599 ** byte 0,1 : length 5600 ** byte 2 : command code 0x37 5601 ** byte 3 : 0->COMA (term port), 1->COMB (debug port) 5602 ** byte 4 : 0/1/2/3/4/5/6/7 (1200/2400/4800/9600/19200/38400/57600/115200) 5603 ** byte 5 : data bit (0:7 bit, 1:8 bit : must be 8 bit) 5604 ** byte 6 : stop bit (0:1, 1:2 stop bits) 5605 ** byte 7 : parity (0:none, 1:off, 2:even) 5606 ** byte 8 : flow control (0:none, 1:xon/xoff, 2:hardware => must use none) 5607 ** 5608 ** GUI_NO_OPERATION : No operation 5609 ** byte 0,1 : length 5610 ** byte 2 : command code 0x38 5611 ** 5612 ** GUI_DHCP_IP : Set DHCP option and local IP address 5613 ** byte 0,1 : length 5614 ** byte 2 : command code 0x39 5615 ** byte 3 : 0:dhcp disabled, 1:dhcp enabled 5616 ** byte 4/5/6/7 : IP address 5617 ** 5618 ** GUI_CREATE_PASS_THROUGH : Create pass through disk 5619 ** byte 0,1 : length 5620 ** byte 2 : command code 0x40 5621 ** byte 3 : device # 5622 ** byte 4 : scsi channel (0/1) 5623 ** byte 5 : scsi id (0-->15) 5624 ** byte 6 : scsi lun (0-->7) 5625 ** byte 7 : tagged queue (1 : enabled) 5626 ** byte 8 : cache mode (1 : enabled) 5627 ** byte 9 : max speed (0/1/2/3/4, async/20/40/80/160 for scsi) 5628 ** (0/1/2/3/4, 33/66/100/133/150 for ide ) 5629 ** 5630 ** GUI_MODIFY_PASS_THROUGH : Modify pass through disk 5631 ** byte 0,1 : length 5632 ** byte 2 : command code 0x41 5633 ** byte 3 : device # 5634 ** byte 4 : scsi channel (0/1) 5635 ** byte 5 : scsi id (0-->15) 5636 ** byte 6 : scsi lun (0-->7) 5637 ** byte 7 : tagged queue (1 : enabled) 5638 ** byte 8 : cache mode (1 : enabled) 5639 ** byte 9 : max speed (0/1/2/3/4, async/20/40/80/160 for scsi) 5640 ** (0/1/2/3/4, 33/66/100/133/150 for ide ) 5641 ** 5642 ** GUI_DELETE_PASS_THROUGH : Delete pass through disk 5643 ** byte 0,1 : length 5644 ** byte 2 : command code 0x42 5645 ** byte 3 : device# to be deleted 5646 ** 5647 ** GUI_IDENTIFY_DEVICE : Identify Device 5648 ** byte 0,1 : length 5649 ** byte 2 : command code 0x43 5650 ** byte 3 : Flash Method(0:flash selected, 1:flash not selected) 5651 ** byte 4/5/6/7 : IDE device mask to be flashed 5652 ** note .... no response data available 5653 ** 5654 ** GUI_CREATE_RAIDSET : Create Raid Set 5655 ** byte 0,1 : length 5656 ** byte 2 : command code 0x50 5657 ** byte 3/4/5/6 : device mask 5658 ** byte 7-22 : raidset name (if byte 7 == 0:use default) 5659 ** 5660 ** GUI_DELETE_RAIDSET : Delete Raid Set 5661 ** byte 0,1 : length 5662 ** byte 2 : command code 0x51 5663 ** byte 3 : raidset# 5664 ** 5665 ** GUI_EXPAND_RAIDSET : Expand Raid Set 5666 ** byte 0,1 : length 5667 ** byte 2 : command code 0x52 5668 ** byte 3 : raidset# 5669 ** byte 4/5/6/7 : device mask for expansion 5670 ** byte 8/9/10 : (8:0 no change, 1 change, 0xff:terminate, 9:new raid level,10:new stripe size 0/1/2/3/4/5->4/8/16/32/64/128K ) 5671 ** byte 11/12/13 : repeat for each volume in the raidset .... 5672 ** 5673 ** GUI_ACTIVATE_RAIDSET : Activate incomplete raid set 5674 ** byte 0,1 : length 5675 ** byte 2 : command code 0x53 5676 ** byte 3 : raidset# 5677 ** 5678 ** GUI_CREATE_HOT_SPARE : Create hot spare disk 5679 ** byte 0,1 : length 5680 ** byte 2 : command code 0x54 5681 ** byte 3/4/5/6 : device mask for hot spare creation 5682 ** 5683 ** GUI_DELETE_HOT_SPARE : Delete hot spare disk 5684 ** byte 0,1 : length 5685 ** byte 2 : command code 0x55 5686 ** byte 3/4/5/6 : device mask for hot spare deletion 5687 ** 5688 ** GUI_CREATE_VOLUME : Create volume set 5689 ** byte 0,1 : length 5690 ** byte 2 : command code 0x60 5691 ** byte 3 : raidset# 5692 ** byte 4-19 : volume set name (if byte4 == 0, use default) 5693 ** byte 20-27 : volume capacity (blocks) 5694 ** byte 28 : raid level 5695 ** byte 29 : stripe size (0/1/2/3/4/5->4/8/16/32/64/128K) 5696 ** byte 30 : channel 5697 ** byte 31 : ID 5698 ** byte 32 : LUN 5699 ** byte 33 : 1 enable tag 5700 ** byte 34 : 1 enable cache 5701 ** byte 35 : speed (0/1/2/3/4->async/20/40/80/160 for scsi) 5702 ** (0/1/2/3/4->33/66/100/133/150 for IDE ) 5703 ** byte 36 : 1 to select quick init 5704 ** 5705 ** GUI_MODIFY_VOLUME : Modify volume Set 5706 ** byte 0,1 : length 5707 ** byte 2 : command code 0x61 5708 ** byte 3 : volumeset# 5709 ** byte 4-19 : new volume set name (if byte4 == 0, not change) 5710 ** byte 20-27 : new volume capacity (reserved) 5711 ** byte 28 : new raid level 5712 ** byte 29 : new stripe size (0/1/2/3/4/5->4/8/16/32/64/128K) 5713 ** byte 30 : new channel 5714 ** byte 31 : new ID 5715 ** byte 32 : new LUN 5716 ** byte 33 : 1 enable tag 5717 ** byte 34 : 1 enable cache 5718 ** byte 35 : speed (0/1/2/3/4->async/20/40/80/160 for scsi) 5719 ** (0/1/2/3/4->33/66/100/133/150 for IDE ) 5720 ** 5721 ** GUI_DELETE_VOLUME : Delete volume set 5722 ** byte 0,1 : length 5723 ** byte 2 : command code 0x62 5724 ** byte 3 : volumeset# 5725 ** 5726 ** GUI_START_CHECK_VOLUME : Start volume consistency check 5727 ** byte 0,1 : length 5728 ** byte 2 : command code 0x63 5729 ** byte 3 : volumeset# 5730 ** 5731 ** GUI_STOP_CHECK_VOLUME : Stop volume consistency check 5732 ** byte 0,1 : length 5733 ** byte 2 : command code 0x64 5734 ** --------------------------------------------------------------------- 5735 ** 4. Returned data 5736 ** --------------------------------------------------------------------- 5737 ** (A) Header : 3 bytes sequence (0x5E, 0x01, 0x61) 5738 ** (B) Length : 2 bytes (low byte 1st, excludes length and checksum byte) 5739 ** (C) status or data : 5740 ** <1> If length == 1 ==> 1 byte status code 5741 ** #define GUI_OK 0x41 5742 ** #define GUI_RAIDSET_NOT_NORMAL 0x42 5743 ** #define GUI_VOLUMESET_NOT_NORMAL 0x43 5744 ** #define GUI_NO_RAIDSET 0x44 5745 ** #define GUI_NO_VOLUMESET 0x45 5746 ** #define GUI_NO_PHYSICAL_DRIVE 0x46 5747 ** #define GUI_PARAMETER_ERROR 0x47 5748 ** #define GUI_UNSUPPORTED_COMMAND 0x48 5749 ** #define GUI_DISK_CONFIG_CHANGED 0x49 5750 ** #define GUI_INVALID_PASSWORD 0x4a 5751 ** #define GUI_NO_DISK_SPACE 0x4b 5752 ** #define GUI_CHECKSUM_ERROR 0x4c 5753 ** #define GUI_PASSWORD_REQUIRED 0x4d 5754 ** <2> If length > 1 ==> data block returned from controller and the contents depends on the command code 5755 ** (E) Checksum : checksum of length and status or data byte 5756 ************************************************************************** 5757 */ 5758