1 /* 2 ******************************************************************************** 3 ** OS : FreeBSD 4 ** FILE NAME : arcmsr.h 5 ** BY : Erich Chen, Ching Huang 6 ** Description: SCSI RAID Device Driver for 7 ** ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x) 8 ** SATA/SAS RAID HOST Adapter 9 ******************************************************************************** 10 ******************************************************************************** 11 ** SPDX-License-Identifier: BSD-3-Clause 12 ** 13 ** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved. 14 ** 15 ** Redistribution and use in source and binary forms,with or without 16 ** modification,are permitted provided that the following conditions 17 ** are met: 18 ** 1. Redistributions of source code must retain the above copyright 19 ** notice,this list of conditions and the following disclaimer. 20 ** 2. Redistributions in binary form must reproduce the above copyright 21 ** notice,this list of conditions and the following disclaimer in the 22 ** documentation and/or other materials provided with the distribution. 23 ** 3. The name of the author may not be used to endorse or promote products 24 ** derived from this software without specific prior written permission. 25 ** 26 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 27 ** IMPLIED WARRANTIES,INCLUDING,BUT NOT LIMITED TO,THE IMPLIED WARRANTIES 28 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,INDIRECT, 30 ** INCIDENTAL,SPECIAL,EXEMPLARY,OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT 31 ** NOT LIMITED TO,PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 ** DATA,OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 33 ** THEORY OF LIABILITY,WHETHER IN CONTRACT,STRICT LIABILITY,OR TORT 34 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 35 ** THIS SOFTWARE,EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 ************************************************************************** 37 * $FreeBSD$ 38 */ 39 #define ARCMSR_SCSI_INITIATOR_ID 255 40 #define ARCMSR_DEV_SECTOR_SIZE 512 41 #define ARCMSR_MAX_XFER_SECTORS 4096 42 #define ARCMSR_MAX_TARGETID 17 /*16 max target id + 1*/ 43 #define ARCMSR_MAX_TARGETLUN 8 /*8*/ 44 #define ARCMSR_MAX_CHIPTYPE_NUM 4 45 #define ARCMSR_MAX_OUTSTANDING_CMD 256 46 #define ARCMSR_MAX_START_JOB 256 47 #define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_OUTSTANDING_CMD 48 #define ARCMSR_MAX_FREESRB_NUM 384 49 #define ARCMSR_MAX_QBUFFER 4096 /* ioctl QBUFFER */ 50 #define ARCMSR_MAX_SG_ENTRIES 38 /* max 38*/ 51 #define ARCMSR_MAX_ADAPTER 4 52 #define ARCMSR_RELEASE_SIMQ_LEVEL 230 53 #define ARCMSR_MAX_HBB_POSTQUEUE 264 /* (ARCMSR_MAX_OUTSTANDING_CMD+8) */ 54 #define ARCMSR_MAX_HBD_POSTQUEUE 256 55 #define ARCMSR_TIMEOUT_DELAY 60 /* in sec */ 56 #define ARCMSR_NUM_MSIX_VECTORS 4 57 /* 58 ********************************************************************* 59 */ 60 #ifndef TRUE 61 #define TRUE 1 62 #endif 63 #ifndef FALSE 64 #define FALSE 0 65 #endif 66 #ifndef INTR_ENTROPY 67 # define INTR_ENTROPY 0 68 #endif 69 70 #ifndef offsetof 71 #define offsetof(type, member) ((size_t)(&((type *)0)->member)) 72 #endif 73 74 #define ARCMSR_LOCK_INIT(l, s) mtx_init(l, s, NULL, MTX_DEF) 75 #define ARCMSR_LOCK_DESTROY(l) mtx_destroy(l) 76 #define ARCMSR_LOCK_ACQUIRE(l) mtx_lock(l) 77 #define ARCMSR_LOCK_RELEASE(l) mtx_unlock(l) 78 #define ARCMSR_LOCK_TRY(l) mtx_trylock(l) 79 #define arcmsr_htole32(x) htole32(x) 80 typedef struct mtx arcmsr_lock_t; 81 82 /* 83 ********************************************************************************** 84 ** 85 ********************************************************************************** 86 */ 87 #define PCI_VENDOR_ID_ARECA 0x17D3 /* Vendor ID */ 88 #define PCI_DEVICE_ID_ARECA_1110 0x1110 /* Device ID */ 89 #define PCI_DEVICE_ID_ARECA_1120 0x1120 /* Device ID */ 90 #define PCI_DEVICE_ID_ARECA_1130 0x1130 /* Device ID */ 91 #define PCI_DEVICE_ID_ARECA_1160 0x1160 /* Device ID */ 92 #define PCI_DEVICE_ID_ARECA_1170 0x1170 /* Device ID */ 93 #define PCI_DEVICE_ID_ARECA_1200 0x1200 /* Device ID */ 94 #define PCI_DEVICE_ID_ARECA_1201 0x1201 /* Device ID */ 95 #define PCI_DEVICE_ID_ARECA_1203 0x1203 /* Device ID */ 96 #define PCI_DEVICE_ID_ARECA_1210 0x1210 /* Device ID */ 97 #define PCI_DEVICE_ID_ARECA_1212 0x1212 /* Device ID */ 98 #define PCI_DEVICE_ID_ARECA_1214 0x1214 /* Device ID */ 99 #define PCI_DEVICE_ID_ARECA_1220 0x1220 /* Device ID */ 100 #define PCI_DEVICE_ID_ARECA_1222 0x1222 /* Device ID */ 101 #define PCI_DEVICE_ID_ARECA_1230 0x1230 /* Device ID */ 102 #define PCI_DEVICE_ID_ARECA_1231 0x1231 /* Device ID */ 103 #define PCI_DEVICE_ID_ARECA_1260 0x1260 /* Device ID */ 104 #define PCI_DEVICE_ID_ARECA_1261 0x1261 /* Device ID */ 105 #define PCI_DEVICE_ID_ARECA_1270 0x1270 /* Device ID */ 106 #define PCI_DEVICE_ID_ARECA_1280 0x1280 /* Device ID */ 107 #define PCI_DEVICE_ID_ARECA_1380 0x1380 /* Device ID */ 108 #define PCI_DEVICE_ID_ARECA_1381 0x1381 /* Device ID */ 109 #define PCI_DEVICE_ID_ARECA_1680 0x1680 /* Device ID */ 110 #define PCI_DEVICE_ID_ARECA_1681 0x1681 /* Device ID */ 111 #define PCI_DEVICE_ID_ARECA_1880 0x1880 /* Device ID */ 112 #define PCI_DEVICE_ID_ARECA_1884 0x1884 /* Device ID */ 113 114 #define ARECA_SUB_DEV_ID_1880 0x1880 /* Subsystem Device ID */ 115 #define ARECA_SUB_DEV_ID_1882 0x1882 /* Subsystem Device ID */ 116 #define ARECA_SUB_DEV_ID_1883 0x1883 /* Subsystem Device ID */ 117 #define ARECA_SUB_DEV_ID_1884 0x1884 /* Subsystem Device ID */ 118 #define ARECA_SUB_DEV_ID_1212 0x1212 /* Subsystem Device ID */ 119 #define ARECA_SUB_DEV_ID_1213 0x1213 /* Subsystem Device ID */ 120 #define ARECA_SUB_DEV_ID_1216 0x1216 /* Subsystem Device ID */ 121 #define ARECA_SUB_DEV_ID_1222 0x1222 /* Subsystem Device ID */ 122 #define ARECA_SUB_DEV_ID_1223 0x1223 /* Subsystem Device ID */ 123 #define ARECA_SUB_DEV_ID_1226 0x1226 /* Subsystem Device ID */ 124 125 #define PCIDevVenIDARC1110 0x111017D3 /* Vendor Device ID */ 126 #define PCIDevVenIDARC1120 0x112017D3 /* Vendor Device ID */ 127 #define PCIDevVenIDARC1130 0x113017D3 /* Vendor Device ID */ 128 #define PCIDevVenIDARC1160 0x116017D3 /* Vendor Device ID */ 129 #define PCIDevVenIDARC1170 0x117017D3 /* Vendor Device ID */ 130 #define PCIDevVenIDARC1200 0x120017D3 /* Vendor Device ID */ 131 #define PCIDevVenIDARC1201 0x120117D3 /* Vendor Device ID */ 132 #define PCIDevVenIDARC1203 0x120317D3 /* Vendor Device ID */ 133 #define PCIDevVenIDARC1210 0x121017D3 /* Vendor Device ID */ 134 #define PCIDevVenIDARC1212 0x121217D3 /* Vendor Device ID */ 135 #define PCIDevVenIDARC1213 0x121317D3 /* Vendor Device ID */ 136 #define PCIDevVenIDARC1214 0x121417D3 /* Vendor Device ID */ 137 #define PCIDevVenIDARC1220 0x122017D3 /* Vendor Device ID */ 138 #define PCIDevVenIDARC1222 0x122217D3 /* Vendor Device ID */ 139 #define PCIDevVenIDARC1223 0x122317D3 /* Vendor Device ID */ 140 #define PCIDevVenIDARC1230 0x123017D3 /* Vendor Device ID */ 141 #define PCIDevVenIDARC1231 0x123117D3 /* Vendor Device ID */ 142 #define PCIDevVenIDARC1260 0x126017D3 /* Vendor Device ID */ 143 #define PCIDevVenIDARC1261 0x126117D3 /* Vendor Device ID */ 144 #define PCIDevVenIDARC1270 0x127017D3 /* Vendor Device ID */ 145 #define PCIDevVenIDARC1280 0x128017D3 /* Vendor Device ID */ 146 #define PCIDevVenIDARC1380 0x138017D3 /* Vendor Device ID */ 147 #define PCIDevVenIDARC1381 0x138117D3 /* Vendor Device ID */ 148 #define PCIDevVenIDARC1680 0x168017D3 /* Vendor Device ID */ 149 #define PCIDevVenIDARC1681 0x168117D3 /* Vendor Device ID */ 150 #define PCIDevVenIDARC1880 0x188017D3 /* Vendor Device ID */ 151 #define PCIDevVenIDARC1882 0x188217D3 /* Vendor Device ID */ 152 #define PCIDevVenIDARC1884 0x188417D3 /* Vendor Device ID */ 153 #define PCIDevVenIDARC1886_ 0x188917D3 /* Vendor Device ID */ 154 #define PCIDevVenIDARC1886 0x188A17D3 /* Vendor Device ID */ 155 156 #ifndef PCIR_BARS 157 #define PCIR_BARS 0x10 158 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4) 159 #endif 160 161 #define PCI_BASE_ADDR0 0x10 162 #define PCI_BASE_ADDR1 0x14 163 #define PCI_BASE_ADDR2 0x18 164 #define PCI_BASE_ADDR3 0x1C 165 #define PCI_BASE_ADDR4 0x20 166 #define PCI_BASE_ADDR5 0x24 167 /* 168 ********************************************************************************** 169 ** 170 ********************************************************************************** 171 */ 172 #define ARCMSR_SCSICMD_IOCTL 0x77 173 #define ARCMSR_CDEVSW_IOCTL 0x88 174 #define ARCMSR_MESSAGE_FAIL 0x0001 175 #define ARCMSR_MESSAGE_SUCCESS 0x0000 176 /* 177 ********************************************************************************** 178 ** 179 ********************************************************************************** 180 */ 181 #define arcmsr_ccbsrb_ptr spriv_ptr0 182 #define arcmsr_ccbacb_ptr spriv_ptr1 183 #define dma_addr_hi32(addr) (u_int32_t) ((addr>>16)>>16) 184 #define dma_addr_lo32(addr) (u_int32_t) (addr & 0xffffffff) 185 #define get_min(x,y) ((x) < (y) ? (x) : (y)) 186 #define get_max(x,y) ((x) < (y) ? (y) : (x)) 187 /* 188 ************************************************************************** 189 ************************************************************************** 190 */ 191 #define CHIP_REG_READ32(s, b, r) bus_space_read_4(acb->btag[b], acb->bhandle[b], offsetof(struct s, r)) 192 #define CHIP_REG_WRITE32(s, b, r, d) bus_space_write_4(acb->btag[b], acb->bhandle[b], offsetof(struct s, r), d) 193 #define READ_CHIP_REG32(b, r) bus_space_read_4(acb->btag[b], acb->bhandle[b], r) 194 #define WRITE_CHIP_REG32(b, r, d) bus_space_write_4(acb->btag[b], acb->bhandle[b], r, d) 195 /* 196 ********************************************************************************** 197 ** IOCTL CONTROL Mail Box 198 ********************************************************************************** 199 */ 200 struct CMD_MESSAGE { 201 u_int32_t HeaderLength; 202 u_int8_t Signature[8]; 203 u_int32_t Timeout; 204 u_int32_t ControlCode; 205 u_int32_t ReturnCode; 206 u_int32_t Length; 207 }; 208 209 struct CMD_MESSAGE_FIELD { 210 struct CMD_MESSAGE cmdmessage; /* ioctl header */ 211 u_int8_t messagedatabuffer[1032]; /* areca gui program does not accept more than 1031 byte */ 212 }; 213 214 /************************************************************************/ 215 /************************************************************************/ 216 217 #define ARCMSR_IOP_ERROR_ILLEGALPCI 0x0001 218 #define ARCMSR_IOP_ERROR_VENDORID 0x0002 219 #define ARCMSR_IOP_ERROR_DEVICEID 0x0002 220 #define ARCMSR_IOP_ERROR_ILLEGALCDB 0x0003 221 #define ARCMSR_IOP_ERROR_UNKNOW_CDBERR 0x0004 222 #define ARCMSR_SYS_ERROR_MEMORY_ALLOCATE 0x0005 223 #define ARCMSR_SYS_ERROR_MEMORY_CROSS4G 0x0006 224 #define ARCMSR_SYS_ERROR_MEMORY_LACK 0x0007 225 #define ARCMSR_SYS_ERROR_MEMORY_RANGE 0x0008 226 #define ARCMSR_SYS_ERROR_DEVICE_BASE 0x0009 227 #define ARCMSR_SYS_ERROR_PORT_VALIDATE 0x000A 228 229 /*DeviceType*/ 230 #define ARECA_SATA_RAID 0x90000000 231 232 /*FunctionCode*/ 233 #define FUNCTION_READ_RQBUFFER 0x0801 234 #define FUNCTION_WRITE_WQBUFFER 0x0802 235 #define FUNCTION_CLEAR_RQBUFFER 0x0803 236 #define FUNCTION_CLEAR_WQBUFFER 0x0804 237 #define FUNCTION_CLEAR_ALLQBUFFER 0x0805 238 #define FUNCTION_REQUEST_RETURNCODE_3F 0x0806 239 #define FUNCTION_SAY_HELLO 0x0807 240 #define FUNCTION_SAY_GOODBYE 0x0808 241 #define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809 242 /* 243 ************************************************************************ 244 ** IOCTL CONTROL CODE 245 ************************************************************************ 246 */ 247 /* ARECA IO CONTROL CODE*/ 248 #define ARCMSR_MESSAGE_READ_RQBUFFER _IOWR('F', FUNCTION_READ_RQBUFFER, struct CMD_MESSAGE_FIELD) 249 #define ARCMSR_MESSAGE_WRITE_WQBUFFER _IOWR('F', FUNCTION_WRITE_WQBUFFER, struct CMD_MESSAGE_FIELD) 250 #define ARCMSR_MESSAGE_CLEAR_RQBUFFER _IOWR('F', FUNCTION_CLEAR_RQBUFFER, struct CMD_MESSAGE_FIELD) 251 #define ARCMSR_MESSAGE_CLEAR_WQBUFFER _IOWR('F', FUNCTION_CLEAR_WQBUFFER, struct CMD_MESSAGE_FIELD) 252 #define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER _IOWR('F', FUNCTION_CLEAR_ALLQBUFFER, struct CMD_MESSAGE_FIELD) 253 #define ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F _IOWR('F', FUNCTION_REQUEST_RETURNCODE_3F, struct CMD_MESSAGE_FIELD) 254 #define ARCMSR_MESSAGE_SAY_HELLO _IOWR('F', FUNCTION_SAY_HELLO, struct CMD_MESSAGE_FIELD) 255 #define ARCMSR_MESSAGE_SAY_GOODBYE _IOWR('F', FUNCTION_SAY_GOODBYE, struct CMD_MESSAGE_FIELD) 256 #define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE _IOWR('F', FUNCTION_FLUSH_ADAPTER_CACHE, struct CMD_MESSAGE_FIELD) 257 258 /* ARECA IOCTL ReturnCode */ 259 #define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001 260 #define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006 261 #define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F 262 #define ARCMSR_IOCTL_RETURNCODE_BUS_HANG_ON 0x00000088 263 /* 264 ************************************************************************ 265 ** SPEC. for Areca HBA adapter 266 ************************************************************************ 267 */ 268 /* signature of set and get firmware config */ 269 #define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060 270 #define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063 271 /* message code of inbound message register */ 272 #define ARCMSR_INBOUND_MESG0_NOP 0x00000000 273 #define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001 274 #define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002 275 #define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003 276 #define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004 277 #define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005 278 #define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006 279 #define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007 280 #define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008 281 /* doorbell interrupt generator */ 282 #define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001 283 #define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002 284 #define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001 285 #define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002 286 /* srb areca cdb flag */ 287 #define ARCMSR_SRBPOST_FLAG_SGL_BSIZE 0x80000000 288 #define ARCMSR_SRBPOST_FLAG_IAM_BIOS 0x40000000 289 #define ARCMSR_SRBREPLY_FLAG_IAM_BIOS 0x40000000 290 #define ARCMSR_SRBREPLY_FLAG_ERROR 0x10000000 291 #define ARCMSR_SRBREPLY_FLAG_ERROR_MODE0 0x10000000 292 #define ARCMSR_SRBREPLY_FLAG_ERROR_MODE1 0x00000001 293 /* outbound firmware ok */ 294 #define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000 295 296 #define ARCMSR_ARC1680_BUS_RESET 0x00000003 297 /* 298 ************************************************************************ 299 ** SPEC. for Areca HBB adapter 300 ************************************************************************ 301 */ 302 /* ARECA HBB COMMAND for its FIRMWARE */ 303 #define ARCMSR_DRV2IOP_DOORBELL 0x00020400 /* window of "instruction flags" from driver to iop */ 304 #define ARCMSR_DRV2IOP_DOORBELL_MASK 0x00020404 305 #define ARCMSR_IOP2DRV_DOORBELL 0x00020408 /* window of "instruction flags" from iop to driver */ 306 #define ARCMSR_IOP2DRV_DOORBELL_MASK 0x0002040C 307 308 #define ARCMSR_IOP2DRV_DOORBELL_1203 0x00021870 /* window of "instruction flags" from iop to driver */ 309 #define ARCMSR_IOP2DRV_DOORBELL_MASK_1203 0x00021874 310 #define ARCMSR_DRV2IOP_DOORBELL_1203 0x00021878 /* window of "instruction flags" from driver to iop */ 311 #define ARCMSR_DRV2IOP_DOORBELL_MASK_1203 0x0002187C 312 313 /* ARECA FLAG LANGUAGE */ 314 #define ARCMSR_IOP2DRV_DATA_WRITE_OK 0x00000001 /* ioctl transfer */ 315 #define ARCMSR_IOP2DRV_DATA_READ_OK 0x00000002 /* ioctl transfer */ 316 #define ARCMSR_IOP2DRV_CDB_DONE 0x00000004 317 #define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 318 319 #define ARCMSR_DOORBELL_HANDLE_INT 0x0000000F 320 #define ARCMSR_DOORBELL_INT_CLEAR_PATTERN 0xFF00FFF0 321 #define ARCMSR_MESSAGE_INT_CLEAR_PATTERN 0xFF00FFF7 322 323 #define ARCMSR_MESSAGE_GET_CONFIG 0x00010008 /* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 324 #define ARCMSR_MESSAGE_SET_CONFIG 0x00020008 /* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 325 #define ARCMSR_MESSAGE_ABORT_CMD 0x00030008 /* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 326 #define ARCMSR_MESSAGE_STOP_BGRB 0x00040008 /* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 327 #define ARCMSR_MESSAGE_FLUSH_CACHE 0x00050008 /* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 328 #define ARCMSR_MESSAGE_START_BGRB 0x00060008 /* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 329 #define ARCMSR_MESSAGE_START_DRIVER_MODE 0x000E0008 330 #define ARCMSR_MESSAGE_SET_POST_WINDOW 0x000F0008 331 #define ARCMSR_MESSAGE_ACTIVE_EOI_MODE 0x00100008 332 #define ARCMSR_MESSAGE_FIRMWARE_OK 0x80000000 /* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */ 333 334 #define ARCMSR_DRV2IOP_DATA_WRITE_OK 0x00000001 /* ioctl transfer */ 335 #define ARCMSR_DRV2IOP_DATA_READ_OK 0x00000002 /* ioctl transfer */ 336 #define ARCMSR_DRV2IOP_CDB_POSTED 0x00000004 337 #define ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED 0x00000008 338 #define ARCMSR_DRV2IOP_END_OF_INTERRUPT 0x00000010 /* */ 339 340 /* data tunnel buffer between user space program and its firmware */ 341 #define ARCMSR_MSGCODE_RWBUFFER 0x0000fa00 /* iop msgcode_rwbuffer for message command */ 342 #define ARCMSR_IOCTL_WBUFFER 0x0000fe00 /* user space data to iop 128bytes */ 343 #define ARCMSR_IOCTL_RBUFFER 0x0000ff00 /* iop data to user space 128bytes */ 344 #define ARCMSR_HBB_BASE0_OFFSET 0x00000010 345 #define ARCMSR_HBB_BASE1_OFFSET 0x00000018 346 #define ARCMSR_HBB_BASE0_LEN 0x00021000 347 #define ARCMSR_HBB_BASE1_LEN 0x00010000 348 /* 349 ************************************************************************ 350 ** SPEC. for Areca HBC adapter 351 ************************************************************************ 352 */ 353 #define ARCMSR_HBC_ISR_THROTTLING_LEVEL 12 354 #define ARCMSR_HBC_ISR_MAX_DONE_QUEUE 20 355 /* Host Interrupt Mask */ 356 #define ARCMSR_HBCMU_UTILITY_A_ISR_MASK 0x00000001 /* When clear, the Utility_A interrupt routes to the host.*/ 357 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK 0x00000004 /* When clear, the General Outbound Doorbell interrupt routes to the host.*/ 358 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK 0x00000008 /* When clear, the Outbound Post List FIFO Not Empty interrupt routes to the host.*/ 359 #define ARCMSR_HBCMU_ALL_INTMASKENABLE 0x0000000D /* disable all ISR */ 360 /* Host Interrupt Status */ 361 #define ARCMSR_HBCMU_UTILITY_A_ISR 0x00000001 362 /* 363 ** Set when the Utility_A Interrupt bit is set in the Outbound Doorbell Register. 364 ** It clears by writing a 1 to the Utility_A bit in the Outbound Doorbell Clear Register or through automatic clearing (if enabled). 365 */ 366 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR 0x00000004 367 /* 368 ** Set if Outbound Doorbell register bits 30:1 have a non-zero 369 ** value. This bit clears only when Outbound Doorbell bits 370 ** 30:1 are ALL clear. Only a write to the Outbound Doorbell 371 ** Clear register clears bits in the Outbound Doorbell register. 372 */ 373 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR 0x00000008 374 /* 375 ** Set whenever the Outbound Post List Producer/Consumer 376 ** Register (FIFO) is not empty. It clears when the Outbound 377 ** Post List FIFO is empty. 378 */ 379 #define ARCMSR_HBCMU_SAS_ALL_INT 0x00000010 380 /* 381 ** This bit indicates a SAS interrupt from a source external to 382 ** the PCIe core. This bit is not maskable. 383 */ 384 /* DoorBell*/ 385 #define ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK 0x00000002/**/ 386 #define ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK 0x00000004/**/ 387 #define ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008/*inbound message 0 ready*/ 388 #define ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING 0x00000010/*more than 12 request completed in a time*/ 389 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK 0x00000002/**/ 390 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR 0x00000002/*outbound DATA WRITE isr door bell clear*/ 391 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK 0x00000004/**/ 392 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR 0x00000004/*outbound DATA READ isr door bell clear*/ 393 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008/*outbound message 0 ready*/ 394 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR 0x00000008/*outbound message cmd isr door bell clear*/ 395 #define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK 0x80000000/*ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK*/ 396 #define ARCMSR_HBCMU_RESET_ADAPTER 0x00000024 397 #define ARCMSR_HBCMU_DiagWrite_ENABLE 0x00000080 398 399 /* 400 ************************************************************************ 401 ** SPEC. for Areca HBD adapter 402 ************************************************************************ 403 */ 404 #define ARCMSR_HBDMU_CHIP_ID 0x00004 405 #define ARCMSR_HBDMU_CPU_MEMORY_CONFIGURATION 0x00008 406 #define ARCMSR_HBDMU_I2_HOST_INTERRUPT_MASK 0x00034 407 #define ARCMSR_HBDMU_MAIN_INTERRUPT_STATUS 0x00200 408 #define ARCMSR_HBDMU_PCIE_F0_INTERRUPT_ENABLE 0x0020C 409 #define ARCMSR_HBDMU_INBOUND_MESSAGE0 0x00400 410 #define ARCMSR_HBDMU_INBOUND_MESSAGE1 0x00404 411 #define ARCMSR_HBDMU_OUTBOUND_MESSAGE0 0x00420 412 #define ARCMSR_HBDMU_OUTBOUND_MESSAGE1 0x00424 413 #define ARCMSR_HBDMU_INBOUND_DOORBELL 0x00460 414 #define ARCMSR_HBDMU_OUTBOUND_DOORBELL 0x00480 415 #define ARCMSR_HBDMU_OUTBOUND_DOORBELL_ENABLE 0x00484 416 #define ARCMSR_HBDMU_INBOUND_LIST_BASE_LOW 0x01000 417 #define ARCMSR_HBDMU_INBOUND_LIST_BASE_HIGH 0x01004 418 #define ARCMSR_HBDMU_INBOUND_LIST_WRITE_POINTER 0x01018 419 #define ARCMSR_HBDMU_OUTBOUND_LIST_BASE_LOW 0x01060 420 #define ARCMSR_HBDMU_OUTBOUND_LIST_BASE_HIGH 0x01064 421 #define ARCMSR_HBDMU_OUTBOUND_LIST_COPY_POINTER 0x0106C 422 #define ARCMSR_HBDMU_OUTBOUND_LIST_READ_POINTER 0x01070 423 #define ARCMSR_HBDMU_OUTBOUND_INTERRUPT_CAUSE 0x01088 424 #define ARCMSR_HBDMU_OUTBOUND_INTERRUPT_ENABLE 0x0108C 425 426 #define ARCMSR_HBDMU_MESSAGE_WBUFFER 0x02000 427 #define ARCMSR_HBDMU_MESSAGE_RBUFFER 0x02100 428 #define ARCMSR_HBDMU_MESSAGE_RWBUFFER 0x02200 429 430 #define ARCMSR_HBDMU_ISR_THROTTLING_LEVEL 16 431 #define ARCMSR_HBDMU_ISR_MAX_DONE_QUEUE 20 432 433 /* Host Interrupt Mask */ 434 #define ARCMSR_HBDMU_ALL_INT_ENABLE 0x00001010 /* enable all ISR */ 435 #define ARCMSR_HBDMU_ALL_INT_DISABLE 0x00000000 /* disable all ISR */ 436 437 /* Host Interrupt Status */ 438 #define ARCMSR_HBDMU_OUTBOUND_INT 0x00001010 439 #define ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT 0x00001000 440 #define ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT 0x00000010 441 442 /* DoorBell*/ 443 #define ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY 0x00000001 444 #define ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ 0x00000002 445 446 #define ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK 0x00000001 447 #define ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK 0x00000002 448 449 /*outbound message 0 ready*/ 450 #define ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE 0x02000000 451 452 #define ARCMSR_HBDMU_F0_DOORBELL_CAUSE 0x02000003 453 454 /*outbound message cmd isr door bell clear*/ 455 #define ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR 0x02000000 456 457 /*outbound list */ 458 #define ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT 0x00000001 459 #define ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR 0x00000001 460 461 /*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/ 462 #define ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK 0x80000000 463 /* 464 ******************************************************************************* 465 ** SPEC. for Areca HBE adapter 466 ******************************************************************************* 467 */ 468 #define ARCMSR_SIGNATURE_1884 0x188417D3 469 #define ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR 0x00000001 470 #define ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR 0x00000008 471 #define ARCMSR_HBEMU_ALL_INTMASKENABLE 0x00000009 /* disable all ISR */ 472 473 #define ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK 0x00000002 474 #define ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK 0x00000004 475 #define ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008 /* inbound message 0 ready */ 476 #define ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK 0x00000002 477 #define ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK 0x00000004 478 #define ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 /* outbound message 0 ready */ 479 #define ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK 0x80000000 /* ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK */ 480 /* ARC-1884 doorbell sync */ 481 #define ARCMSR_HBEMU_DOORBELL_SYNC 0x100 482 #define ARCMSR_ARC188X_RESET_ADAPTER 0x00000004 483 /* 484 ******************************************************************************* 485 ** SPEC. for Areca HBF adapter 486 ******************************************************************************* 487 */ 488 #define ARCMSR_SIGNATURE_1886 0x188617D3 489 // Doorbell and interrupt definition are same as Type E adapter 490 /* ARC-1886 doorbell sync */ 491 #define ARCMSR_HBFMU_DOORBELL_SYNC 0x100 492 //set host rw buffer physical address at inbound message 0, 1 (low,high) 493 #define ARCMSR_HBFMU_DOORBELL_SYNC1 0x300 494 #define ARCMSR_HBFMU_MESSAGE_FIRMWARE_OK 0x80000000 495 #define ARCMSR_HBFMU_MESSAGE_NO_VOLUME_CHANGE 0x20000000 496 497 /* 498 ********************************************************************* 499 ** Messaging Unit (MU) of Type A processor 500 ********************************************************************* 501 */ 502 struct HBA_MessageUnit 503 { 504 u_int32_t resrved0[4]; /*0000 000F*/ 505 u_int32_t inbound_msgaddr0; /*0010 0013*/ 506 u_int32_t inbound_msgaddr1; /*0014 0017*/ 507 u_int32_t outbound_msgaddr0; /*0018 001B*/ 508 u_int32_t outbound_msgaddr1; /*001C 001F*/ 509 u_int32_t inbound_doorbell; /*0020 0023*/ 510 u_int32_t inbound_intstatus; /*0024 0027*/ 511 u_int32_t inbound_intmask; /*0028 002B*/ 512 u_int32_t outbound_doorbell; /*002C 002F*/ 513 u_int32_t outbound_intstatus; /*0030 0033*/ 514 u_int32_t outbound_intmask; /*0034 0037*/ 515 u_int32_t reserved1[2]; /*0038 003F*/ 516 u_int32_t inbound_queueport; /*0040 0043*/ 517 u_int32_t outbound_queueport; /*0044 0047*/ 518 u_int32_t reserved2[2]; /*0048 004F*/ 519 u_int32_t reserved3[492]; /*0050 07FF ......local_buffer 492*/ 520 u_int32_t reserved4[128]; /*0800 09FF 128*/ 521 u_int32_t msgcode_rwbuffer[256]; /*0a00 0DFF 256*/ 522 u_int32_t message_wbuffer[32]; /*0E00 0E7F 32*/ 523 u_int32_t reserved5[32]; /*0E80 0EFF 32*/ 524 u_int32_t message_rbuffer[32]; /*0F00 0F7F 32*/ 525 u_int32_t reserved6[32]; /*0F80 0FFF 32*/ 526 }; 527 /* 528 ********************************************************************* 529 ** 530 ********************************************************************* 531 */ 532 struct HBB_DOORBELL_1203 533 { 534 u_int8_t doorbell_reserved[ARCMSR_IOP2DRV_DOORBELL_1203]; /*reserved */ 535 u_int32_t iop2drv_doorbell; /*offset 0x00021870:00,01,02,03: window of "instruction flags" from iop to driver */ 536 u_int32_t iop2drv_doorbell_mask; /* 04,05,06,07: doorbell mask */ 537 u_int32_t drv2iop_doorbell; /* 08,09,10,11: window of "instruction flags" from driver to iop */ 538 u_int32_t drv2iop_doorbell_mask; /* 12,13,14,15: doorbell mask */ 539 }; 540 struct HBB_DOORBELL 541 { 542 u_int8_t doorbell_reserved[ARCMSR_DRV2IOP_DOORBELL]; /*reserved */ 543 u_int32_t drv2iop_doorbell; /*offset 0x00020400:00,01,02,03: window of "instruction flags" from driver to iop */ 544 u_int32_t drv2iop_doorbell_mask; /* 04,05,06,07: doorbell mask */ 545 u_int32_t iop2drv_doorbell; /* 08,09,10,11: window of "instruction flags" from iop to driver */ 546 u_int32_t iop2drv_doorbell_mask; /* 12,13,14,15: doorbell mask */ 547 }; 548 /* 549 ********************************************************************* 550 ** 551 ********************************************************************* 552 */ 553 struct HBB_RWBUFFER 554 { 555 u_int8_t message_reserved0[ARCMSR_MSGCODE_RWBUFFER]; /*reserved */ 556 u_int32_t msgcode_rwbuffer[256]; /*offset 0x0000fa00: 0, 1, 2, 3,...,1023: message code read write 1024bytes */ 557 u_int32_t message_wbuffer[32]; /*offset 0x0000fe00:1024,1025,1026,1027,...,1151: user space data to iop 128bytes */ 558 u_int32_t message_reserved1[32]; /* 1152,1153,1154,1155,...,1279: message reserved*/ 559 u_int32_t message_rbuffer[32]; /*offset 0x0000ff00:1280,1281,1282,1283,...,1407: iop data to user space 128bytes */ 560 }; 561 /* 562 ********************************************************************* 563 ** Messaging Unit (MU) of Type B processor(MARVEL) 564 ********************************************************************* 565 */ 566 struct HBB_MessageUnit 567 { 568 u_int32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* post queue buffer for iop */ 569 u_int32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* done queue buffer for iop */ 570 int32_t postq_index; /* post queue index */ 571 int32_t doneq_index; /* done queue index */ 572 struct HBB_DOORBELL *hbb_doorbell; 573 struct HBB_RWBUFFER *hbb_rwbuffer; 574 bus_size_t drv2iop_doorbell; /* window of "instruction flags" from driver to iop */ 575 bus_size_t drv2iop_doorbell_mask; /* doorbell mask */ 576 bus_size_t iop2drv_doorbell; /* window of "instruction flags" from iop to driver */ 577 bus_size_t iop2drv_doorbell_mask; /* doorbell mask */ 578 }; 579 580 /* 581 ********************************************************************* 582 ** Messaging Unit (MU) of Type C processor(LSI) 583 ********************************************************************* 584 */ 585 struct HBC_MessageUnit { 586 u_int32_t message_unit_status; /*0000 0003*/ 587 u_int32_t slave_error_attribute; /*0004 0007*/ 588 u_int32_t slave_error_address; /*0008 000B*/ 589 u_int32_t posted_outbound_doorbell; /*000C 000F*/ 590 u_int32_t master_error_attribute; /*0010 0013*/ 591 u_int32_t master_error_address_low; /*0014 0017*/ 592 u_int32_t master_error_address_high; /*0018 001B*/ 593 u_int32_t hcb_size; /*001C 001F size of the PCIe window used for HCB_Mode accesses*/ 594 u_int32_t inbound_doorbell; /*0020 0023*/ 595 u_int32_t diagnostic_rw_data; /*0024 0027*/ 596 u_int32_t diagnostic_rw_address_low; /*0028 002B*/ 597 u_int32_t diagnostic_rw_address_high; /*002C 002F*/ 598 u_int32_t host_int_status; /*0030 0033 host interrupt status*/ 599 u_int32_t host_int_mask; /*0034 0037 host interrupt mask*/ 600 u_int32_t dcr_data; /*0038 003B*/ 601 u_int32_t dcr_address; /*003C 003F*/ 602 u_int32_t inbound_queueport; /*0040 0043 port32 host inbound queue port*/ 603 u_int32_t outbound_queueport; /*0044 0047 port32 host outbound queue port*/ 604 u_int32_t hcb_pci_address_low; /*0048 004B*/ 605 u_int32_t hcb_pci_address_high; /*004C 004F*/ 606 u_int32_t iop_int_status; /*0050 0053*/ 607 u_int32_t iop_int_mask; /*0054 0057*/ 608 u_int32_t iop_inbound_queue_port; /*0058 005B*/ 609 u_int32_t iop_outbound_queue_port; /*005C 005F*/ 610 u_int32_t inbound_free_list_index; /*0060 0063 inbound free list producer consumer index*/ 611 u_int32_t inbound_post_list_index; /*0064 0067 inbound post list producer consumer index*/ 612 u_int32_t outbound_free_list_index; /*0068 006B outbound free list producer consumer index*/ 613 u_int32_t outbound_post_list_index; /*006C 006F outbound post list producer consumer index*/ 614 u_int32_t inbound_doorbell_clear; /*0070 0073*/ 615 u_int32_t i2o_message_unit_control; /*0074 0077*/ 616 u_int32_t last_used_message_source_address_low; /*0078 007B*/ 617 u_int32_t last_used_message_source_address_high; /*007C 007F*/ 618 u_int32_t pull_mode_data_byte_count[4]; /*0080 008F pull mode data byte count0..count7*/ 619 u_int32_t message_dest_address_index; /*0090 0093*/ 620 u_int32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/ 621 u_int32_t utility_A_int_counter_timer; /*0098 009B*/ 622 u_int32_t outbound_doorbell; /*009C 009F*/ 623 u_int32_t outbound_doorbell_clear; /*00A0 00A3*/ 624 u_int32_t message_source_address_index; /*00A4 00A7 message accelerator source address consumer producer index*/ 625 u_int32_t message_done_queue_index; /*00A8 00AB message accelerator completion queue consumer producer index*/ 626 u_int32_t reserved0; /*00AC 00AF*/ 627 u_int32_t inbound_msgaddr0; /*00B0 00B3 scratchpad0*/ 628 u_int32_t inbound_msgaddr1; /*00B4 00B7 scratchpad1*/ 629 u_int32_t outbound_msgaddr0; /*00B8 00BB scratchpad2*/ 630 u_int32_t outbound_msgaddr1; /*00BC 00BF scratchpad3*/ 631 u_int32_t inbound_queueport_low; /*00C0 00C3 port64 host inbound queue port low*/ 632 u_int32_t inbound_queueport_high; /*00C4 00C7 port64 host inbound queue port high*/ 633 u_int32_t outbound_queueport_low; /*00C8 00CB port64 host outbound queue port low*/ 634 u_int32_t outbound_queueport_high; /*00CC 00CF port64 host outbound queue port high*/ 635 u_int32_t iop_inbound_queue_port_low; /*00D0 00D3*/ 636 u_int32_t iop_inbound_queue_port_high; /*00D4 00D7*/ 637 u_int32_t iop_outbound_queue_port_low; /*00D8 00DB*/ 638 u_int32_t iop_outbound_queue_port_high; /*00DC 00DF*/ 639 u_int32_t message_dest_queue_port_low; /*00E0 00E3 message accelerator destination queue port low*/ 640 u_int32_t message_dest_queue_port_high; /*00E4 00E7 message accelerator destination queue port high*/ 641 u_int32_t last_used_message_dest_address_low; /*00E8 00EB last used message accelerator destination address low*/ 642 u_int32_t last_used_message_dest_address_high; /*00EC 00EF last used message accelerator destination address high*/ 643 u_int32_t message_done_queue_base_address_low; /*00F0 00F3 message accelerator completion queue base address low*/ 644 u_int32_t message_done_queue_base_address_high; /*00F4 00F7 message accelerator completion queue base address high*/ 645 u_int32_t host_diagnostic; /*00F8 00FB*/ 646 u_int32_t write_sequence; /*00FC 00FF*/ 647 u_int32_t reserved1[34]; /*0100 0187*/ 648 u_int32_t reserved2[1950]; /*0188 1FFF*/ 649 u_int32_t message_wbuffer[32]; /*2000 207F*/ 650 u_int32_t reserved3[32]; /*2080 20FF*/ 651 u_int32_t message_rbuffer[32]; /*2100 217F*/ 652 u_int32_t reserved4[32]; /*2180 21FF*/ 653 u_int32_t msgcode_rwbuffer[256]; /*2200 23FF*/ 654 }; 655 /* 656 ********************************************************************* 657 ** Messaging Unit (MU) of Type D processor 658 ********************************************************************* 659 */ 660 struct InBound_SRB { 661 uint32_t addressLow; //pointer to SRB block 662 uint32_t addressHigh; 663 uint32_t length; // in DWORDs 664 uint32_t reserved0; 665 }; 666 667 struct OutBound_SRB { 668 uint32_t addressLow; //pointer to SRB block 669 uint32_t addressHigh; 670 }; 671 672 struct HBD_MessageUnit { 673 uint32_t reserved0; 674 uint32_t chip_id; //0x0004 675 uint32_t cpu_mem_config; //0x0008 676 uint32_t reserved1[10]; //0x000C 677 uint32_t i2o_host_interrupt_mask; //0x0034 678 uint32_t reserved2[114]; //0x0038 679 uint32_t host_int_status; //0x0200 680 uint32_t host_int_enable; //0x0204 681 uint32_t reserved3[1]; //0x0208 682 uint32_t pcief0_int_enable; //0x020C 683 uint32_t reserved4[124]; //0x0210 684 uint32_t inbound_msgaddr0; //0x0400 685 uint32_t inbound_msgaddr1; //0x0404 686 uint32_t reserved5[6]; //0x0408 687 uint32_t outbound_msgaddr0; //0x0420 688 uint32_t outbound_msgaddr1; //0x0424 689 uint32_t reserved6[14]; //0x0428 690 uint32_t inbound_doorbell; //0x0460 691 uint32_t reserved7[7]; //0x0464 692 uint32_t outbound_doorbell; //0x0480 693 uint32_t outbound_doorbell_enable; //0x0484 694 uint32_t reserved8[734]; //0x0488 695 uint32_t inboundlist_base_low; //0x1000 696 uint32_t inboundlist_base_high; //0x1004 697 uint32_t reserved9[4]; //0x1008 698 uint32_t inboundlist_write_pointer; //0x1018 699 uint32_t inboundlist_read_pointer; //0x101C 700 uint32_t reserved10[16]; //0x1020 701 uint32_t outboundlist_base_low; //0x1060 702 uint32_t outboundlist_base_high; //0x1064 703 uint32_t reserved11; //0x1068 704 uint32_t outboundlist_copy_pointer; //0x106C 705 uint32_t outboundlist_read_pointer; //0x1070 0x1072 706 uint32_t reserved12[5]; //0x1074 707 uint32_t outboundlist_interrupt_cause; //0x1088 708 uint32_t outboundlist_interrupt_enable; //0x108C 709 uint32_t reserved13[988]; //0x1090 710 uint32_t message_wbuffer[32]; //0x2000 711 uint32_t reserved14[32]; //0x2080 712 uint32_t message_rbuffer[32]; //0x2100 713 uint32_t reserved15[32]; //0x2180 714 uint32_t msgcode_rwbuffer[256]; //0x2200 715 }; 716 717 struct HBD_MessageUnit0 { 718 struct InBound_SRB post_qbuffer[ARCMSR_MAX_HBD_POSTQUEUE]; 719 struct OutBound_SRB done_qbuffer[ARCMSR_MAX_HBD_POSTQUEUE+1]; 720 uint16_t postq_index; 721 uint16_t doneq_index; 722 struct HBD_MessageUnit *phbdmu; 723 }; 724 /* 725 ********************************************************************* 726 ** Messaging Unit (MU) of Type E processor(LSI) 727 ********************************************************************* 728 */ 729 struct HBE_MessageUnit { 730 u_int32_t iobound_doorbell; /*0000 0003*/ 731 u_int32_t write_sequence_3xxx; /*0004 0007*/ 732 u_int32_t host_diagnostic_3xxx; /*0008 000B*/ 733 u_int32_t posted_outbound_doorbell; /*000C 000F*/ 734 u_int32_t master_error_attribute; /*0010 0013*/ 735 u_int32_t master_error_address_low; /*0014 0017*/ 736 u_int32_t master_error_address_high; /*0018 001B*/ 737 u_int32_t hcb_size; /*001C 001F*/ 738 u_int32_t inbound_doorbell; /*0020 0023*/ 739 u_int32_t diagnostic_rw_data; /*0024 0027*/ 740 u_int32_t diagnostic_rw_address_low; /*0028 002B*/ 741 u_int32_t diagnostic_rw_address_high; /*002C 002F*/ 742 u_int32_t host_int_status; /*0030 0033 host interrupt status*/ 743 u_int32_t host_int_mask; /*0034 0037 host interrupt mask*/ 744 u_int32_t dcr_data; /*0038 003B*/ 745 u_int32_t dcr_address; /*003C 003F*/ 746 u_int32_t inbound_queueport; /*0040 0043 port32 host inbound queue port*/ 747 u_int32_t outbound_queueport; /*0044 0047 port32 host outbound queue port*/ 748 u_int32_t hcb_pci_address_low; /*0048 004B*/ 749 u_int32_t hcb_pci_address_high; /*004C 004F*/ 750 u_int32_t iop_int_status; /*0050 0053*/ 751 u_int32_t iop_int_mask; /*0054 0057*/ 752 u_int32_t iop_inbound_queue_port; /*0058 005B*/ 753 u_int32_t iop_outbound_queue_port; /*005C 005F*/ 754 u_int32_t inbound_free_list_index; /*0060 0063*/ 755 u_int32_t inbound_post_list_index; /*0064 0067*/ 756 u_int32_t outbound_free_list_index; /*0068 006B*/ 757 u_int32_t outbound_post_list_index; /*006C 006F*/ 758 u_int32_t inbound_doorbell_clear; /*0070 0073*/ 759 u_int32_t i2o_message_unit_control; /*0074 0077*/ 760 u_int32_t last_used_message_source_address_low; /*0078 007B*/ 761 u_int32_t last_used_message_source_address_high; /*007C 007F*/ 762 u_int32_t pull_mode_data_byte_count[4]; /*0080 008F*/ 763 u_int32_t message_dest_address_index; /*0090 0093*/ 764 u_int32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/ 765 u_int32_t utility_A_int_counter_timer; /*0098 009B*/ 766 u_int32_t outbound_doorbell; /*009C 009F*/ 767 u_int32_t outbound_doorbell_clear; /*00A0 00A3*/ 768 u_int32_t message_source_address_index; /*00A4 00A7*/ 769 u_int32_t message_done_queue_index; /*00A8 00AB*/ 770 u_int32_t reserved0; /*00AC 00AF*/ 771 u_int32_t inbound_msgaddr0; /*00B0 00B3 scratchpad0*/ 772 u_int32_t inbound_msgaddr1; /*00B4 00B7 scratchpad1*/ 773 u_int32_t outbound_msgaddr0; /*00B8 00BB scratchpad2*/ 774 u_int32_t outbound_msgaddr1; /*00BC 00BF scratchpad3*/ 775 u_int32_t inbound_queueport_low; /*00C0 00C3 port64 host inbound queue port low*/ 776 u_int32_t inbound_queueport_high; /*00C4 00C7 port64 host inbound queue port high*/ 777 u_int32_t outbound_queueport_low; /*00C8 00CB port64 host outbound queue port low*/ 778 u_int32_t outbound_queueport_high; /*00CC 00CF port64 host outbound queue port high*/ 779 u_int32_t iop_inbound_queue_port_low; /*00D0 00D3*/ 780 u_int32_t iop_inbound_queue_port_high; /*00D4 00D7*/ 781 u_int32_t iop_outbound_queue_port_low; /*00D8 00DB*/ 782 u_int32_t iop_outbound_queue_port_high; /*00DC 00DF*/ 783 u_int32_t message_dest_queue_port_low; /*00E0 00E3*/ 784 u_int32_t message_dest_queue_port_high; /*00E4 00E7*/ 785 u_int32_t last_used_message_dest_address_low; /*00E8 00EB*/ 786 u_int32_t last_used_message_dest_address_high; /*00EC 00EF*/ 787 u_int32_t message_done_queue_base_address_low; /*00F0 00F3*/ 788 u_int32_t message_done_queue_base_address_high; /*00F4 00F7*/ 789 u_int32_t host_diagnostic; /*00F8 00FB*/ 790 u_int32_t write_sequence; /*00FC 00FF*/ 791 u_int32_t reserved1[46]; /*0100 01B7*/ 792 u_int32_t reply_post_producer_index; /*01B8 01BB*/ 793 u_int32_t reply_post_consumer_index; /*01BC 01BF*/ 794 u_int32_t reserved2[1936]; /*01C0 1FFF*/ 795 u_int32_t message_wbuffer[32]; /*2000 207F*/ 796 u_int32_t reserved3[32]; /*2080 20FF*/ 797 u_int32_t message_rbuffer[32]; /*2100 217F*/ 798 u_int32_t reserved4[32]; /*2180 21FF*/ 799 u_int32_t msgcode_rwbuffer[256]; /*2200 23FF*/ 800 }; 801 802 /* 803 ********************************************************************* 804 ** Messaging Unit (MU) of Type F processor(LSI) 805 ********************************************************************* 806 */ 807 struct HBF_MessageUnit { 808 u_int32_t iobound_doorbell; /*0000 0003*/ 809 u_int32_t write_sequence_3xxx; /*0004 0007*/ 810 u_int32_t host_diagnostic_3xxx; /*0008 000B*/ 811 u_int32_t posted_outbound_doorbell; /*000C 000F*/ 812 u_int32_t master_error_attribute; /*0010 0013*/ 813 u_int32_t master_error_address_low; /*0014 0017*/ 814 u_int32_t master_error_address_high; /*0018 001B*/ 815 u_int32_t hcb_size; /*001C 001F*/ 816 u_int32_t inbound_doorbell; /*0020 0023*/ 817 u_int32_t diagnostic_rw_data; /*0024 0027*/ 818 u_int32_t diagnostic_rw_address_low; /*0028 002B*/ 819 u_int32_t diagnostic_rw_address_high; /*002C 002F*/ 820 u_int32_t host_int_status; /*0030 0033 host interrupt status*/ 821 u_int32_t host_int_mask; /*0034 0037 host interrupt mask*/ 822 u_int32_t dcr_data; /*0038 003B*/ 823 u_int32_t dcr_address; /*003C 003F*/ 824 u_int32_t inbound_queueport; /*0040 0043 port32 host inbound queue port*/ 825 u_int32_t outbound_queueport; /*0044 0047 port32 host outbound queue port*/ 826 u_int32_t hcb_pci_address_low; /*0048 004B*/ 827 u_int32_t hcb_pci_address_high; /*004C 004F*/ 828 u_int32_t iop_int_status; /*0050 0053*/ 829 u_int32_t iop_int_mask; /*0054 0057*/ 830 u_int32_t iop_inbound_queue_port; /*0058 005B*/ 831 u_int32_t iop_outbound_queue_port; /*005C 005F*/ 832 u_int32_t inbound_free_list_index; /*0060 0063*/ 833 u_int32_t inbound_post_list_index; /*0064 0067*/ 834 u_int32_t reply_post_producer_index; /*0068 006B*/ 835 u_int32_t reply_post_consumer_index; /*006C 006F*/ 836 u_int32_t inbound_doorbell_clear; /*0070 0073*/ 837 u_int32_t i2o_message_unit_control; /*0074 0077*/ 838 u_int32_t last_used_message_source_address_low; /*0078 007B*/ 839 u_int32_t last_used_message_source_address_high; /*007C 007F*/ 840 u_int32_t pull_mode_data_byte_count[4]; /*0080 008F*/ 841 u_int32_t message_dest_address_index; /*0090 0093*/ 842 u_int32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/ 843 u_int32_t utility_A_int_counter_timer; /*0098 009B*/ 844 u_int32_t outbound_doorbell; /*009C 009F*/ 845 u_int32_t outbound_doorbell_clear; /*00A0 00A3*/ 846 u_int32_t message_source_address_index; /*00A4 00A7*/ 847 u_int32_t message_done_queue_index; /*00A8 00AB*/ 848 u_int32_t reserved0; /*00AC 00AF*/ 849 u_int32_t inbound_msgaddr0; /*00B0 00B3 scratchpad0*/ 850 u_int32_t inbound_msgaddr1; /*00B4 00B7 scratchpad1*/ 851 u_int32_t outbound_msgaddr0; /*00B8 00BB scratchpad2*/ 852 u_int32_t outbound_msgaddr1; /*00BC 00BF scratchpad3*/ 853 u_int32_t inbound_queueport_low; /*00C0 00C3 port64 host inbound queue port low*/ 854 u_int32_t inbound_queueport_high; /*00C4 00C7 port64 host inbound queue port high*/ 855 u_int32_t outbound_queueport_low; /*00C8 00CB port64 host outbound queue port low*/ 856 u_int32_t outbound_queueport_high; /*00CC 00CF port64 host outbound queue port high*/ 857 u_int32_t iop_inbound_queue_port_low; /*00D0 00D3*/ 858 u_int32_t iop_inbound_queue_port_high; /*00D4 00D7*/ 859 u_int32_t iop_outbound_queue_port_low; /*00D8 00DB*/ 860 u_int32_t iop_outbound_queue_port_high; /*00DC 00DF*/ 861 u_int32_t message_dest_queue_port_low; /*00E0 00E3*/ 862 u_int32_t message_dest_queue_port_high; /*00E4 00E7*/ 863 u_int32_t last_used_message_dest_address_low; /*00E8 00EB*/ 864 u_int32_t last_used_message_dest_address_high; /*00EC 00EF*/ 865 u_int32_t message_done_queue_base_address_low; /*00F0 00F3*/ 866 u_int32_t message_done_queue_base_address_high; /*00F4 00F7*/ 867 u_int32_t host_diagnostic; /*00F8 00FB*/ 868 u_int32_t write_sequence; /*00FC 00FF*/ 869 u_int32_t reserved1[46]; /*0100 01B7*/ 870 u_int32_t reply_post_producer_index1; /*01B8 01BB*/ 871 u_int32_t reply_post_consumer_index1; /*01BC 01BF*/ 872 }; 873 874 #define MESG_RW_BUFFER_SIZE (256 * 3) 875 876 typedef struct deliver_completeQ { 877 u_int16_t cmdFlag; 878 u_int16_t cmdSMID; 879 u_int16_t cmdLMID; // reserved (0) 880 u_int16_t cmdFlag2; // reserved (0) 881 } DeliverQ, CompletionQ, *pDeliver_Q, *pCompletion_Q; 882 883 #define COMPLETION_Q_POOL_SIZE (sizeof(struct deliver_completeQ) * 512 + 128) 884 885 /* 886 ********************************************************************* 887 ** 888 ********************************************************************* 889 */ 890 struct MessageUnit_UNION 891 { 892 union { 893 struct HBA_MessageUnit hbamu; 894 struct HBB_MessageUnit hbbmu; 895 struct HBC_MessageUnit hbcmu; 896 struct HBD_MessageUnit0 hbdmu; 897 struct HBE_MessageUnit hbemu; 898 struct HBF_MessageUnit hbfmu; 899 } muu; 900 }; 901 /* 902 ************************************************************* 903 ** structure for holding DMA address data 904 ************************************************************* 905 */ 906 #define IS_SG64_ADDR 0x01000000 /* bit24 */ 907 /* 908 ************************************************************************************************ 909 ** ARECA FIRMWARE SPEC 910 ************************************************************************************************ 911 ** Usage of IOP331 adapter 912 ** (All In/Out is in IOP331's view) 913 ** 1. Message 0 --> InitThread message and retrun code 914 ** 2. Doorbell is used for RS-232 emulation 915 ** inDoorBell : bit0 -- data in ready (DRIVER DATA WRITE OK) 916 ** bit1 -- data out has been read (DRIVER DATA READ OK) 917 ** outDooeBell: bit0 -- data out ready (IOP331 DATA WRITE OK) 918 ** bit1 -- data in has been read (IOP331 DATA READ OK) 919 ** 3. Index Memory Usage 920 ** offset 0xf00 : for RS232 out (request buffer) 921 ** offset 0xe00 : for RS232 in (scratch buffer) 922 ** offset 0xa00 : for inbound message code msgcode_rwbuffer (driver send to IOP331) 923 ** offset 0xa00 : for outbound message code msgcode_rwbuffer (IOP331 send to driver) 924 ** 4. RS-232 emulation 925 ** Currently 128 byte buffer is used 926 ** 1st u_int32_t : Data length (1--124) 927 ** Byte 4--127 : Max 124 bytes of data 928 ** 5. PostQ 929 ** All SCSI Command must be sent through postQ: 930 ** (inbound queue port) Request frame must be 32 bytes aligned 931 ** # bit27--bit31 => flag for post ccb 932 ** # bit0--bit26 => real address (bit27--bit31) of post arcmsr_cdb 933 ** bit31 : 0 : 256 bytes frame 934 ** 1 : 512 bytes frame 935 ** bit30 : 0 : normal request 936 ** 1 : BIOS request 937 ** bit29 : reserved 938 ** bit28 : reserved 939 ** bit27 : reserved 940 ** ------------------------------------------------------------------------------- 941 ** (outbount queue port) Request reply 942 ** # bit27--bit31 => flag for reply 943 ** # bit0--bit26 => real address (bit27--bit31) of reply arcmsr_cdb 944 ** bit31 : must be 0 (for this type of reply) 945 ** bit30 : reserved for BIOS handshake 946 ** bit29 : reserved 947 ** bit28 : 0 : no error, ignore AdapStatus/DevStatus/SenseData 948 ** 1 : Error, error code in AdapStatus/DevStatus/SenseData 949 ** bit27 : reserved 950 ** 6. BIOS request 951 ** All BIOS request is the same with request from PostQ 952 ** Except : 953 ** Request frame is sent from configuration space 954 ** offset: 0x78 : Request Frame (bit30 == 1) 955 ** offset: 0x18 : writeonly to generate IRQ to IOP331 956 ** Completion of request: 957 ** (bit30 == 0, bit28==err flag) 958 ** 7. Definition of SGL entry (structure) 959 ** 8. Message1 Out - Diag Status Code (????) 960 ** 9. Message0 message code : 961 ** 0x00 : NOP 962 ** 0x01 : Get Config ->offset 0xa00 :for outbound message code msgcode_rwbuffer (IOP331 send to driver) 963 ** Signature 0x87974060(4) 964 ** Request len 0x00000200(4) 965 ** numbers of queue 0x00000100(4) 966 ** SDRAM Size 0x00000100(4)-->256 MB 967 ** IDE Channels 0x00000008(4) 968 ** vendor 40 bytes char 969 ** model 8 bytes char 970 ** FirmVer 16 bytes char 971 ** Device Map 16 bytes char 972 ** 973 ** FirmwareVersion DWORD <== Added for checking of new firmware capability 974 ** 0x02 : Set Config ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver send to IOP331) 975 ** Signature 0x87974063(4) 976 ** UPPER32 of Request Frame (4)-->Driver Only 977 ** 0x03 : Reset (Abort all queued Command) 978 ** 0x04 : Stop Background Activity 979 ** 0x05 : Flush Cache 980 ** 0x06 : Start Background Activity (re-start if background is halted) 981 ** 0x07 : Check If Host Command Pending (Novell May Need This Function) 982 ** 0x08 : Set controller time ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver to IOP331) 983 ** byte 0 : 0xaa <-- signature 984 ** byte 1 : 0x55 <-- signature 985 ** byte 2 : year (04) 986 ** byte 3 : month (1..12) 987 ** byte 4 : date (1..31) 988 ** byte 5 : hour (0..23) 989 ** byte 6 : minute (0..59) 990 ** byte 7 : second (0..59) 991 ** ********************************************************************************* 992 ** Porting Of LSI2108/2116 Based PCIE SAS/6G host raid adapter 993 ** ==> Difference from IOP348 994 ** <1> Message Register 0,1 (the same usage) Init Thread message and retrun code 995 ** Inbound Message 0 (inbound_msgaddr0) : at offset 0xB0 (Scratchpad0) for inbound message code msgcode_rwbuffer (driver send to IOP) 996 ** Inbound Message 1 (inbound_msgaddr1) : at offset 0xB4 (Scratchpad1) Out.... Diag Status Code 997 ** Outbound Message 0 (outbound_msgaddr0): at offset 0xB8 (Scratchpad3) Out.... Diag Status Code 998 ** Outbound Message 1 (outbound_msgaddr1): at offset 0xBC (Scratchpad2) for outbound message code msgcode_rwbuffer (IOP send to driver) 999 ** <A> use doorbell to generate interrupt 1000 ** 1001 ** inbound doorbell: bit3 -- inbound message 0 ready (driver to iop) 1002 ** outbound doorbell: bit3 -- outbound message 0 ready (iop to driver) 1003 ** 1004 ** a. Message1: Out - Diag Status Code (????) 1005 ** 1006 ** b. Message0: message code 1007 ** 0x00 : NOP 1008 ** 0x01 : Get Config ->offset 0xB8 :for outbound message code msgcode_rwbuffer (IOP send to driver) 1009 ** Signature 0x87974060(4) 1010 ** Request len 0x00000200(4) 1011 ** numbers of queue 0x00000100(4) 1012 ** SDRAM Size 0x00000100(4)-->256 MB 1013 ** IDE Channels 0x00000008(4) 1014 ** vendor 40 bytes char 1015 ** model 8 bytes char 1016 ** FirmVer 16 bytes char 1017 ** Device Map 16 bytes char 1018 ** cfgVersion ULONG <== Added for checking of new firmware capability 1019 ** 0x02 : Set Config ->offset 0xB0 :for inbound message code msgcode_rwbuffer (driver send to IOP) 1020 ** Signature 0x87974063(4) 1021 ** UPPER32 of Request Frame (4)-->Driver Only 1022 ** 0x03 : Reset (Abort all queued Command) 1023 ** 0x04 : Stop Background Activity 1024 ** 0x05 : Flush Cache 1025 ** 0x06 : Start Background Activity (re-start if background is halted) 1026 ** 0x07 : Check If Host Command Pending (Novell May Need This Function) 1027 ** 0x08 : Set controller time ->offset 0xB0 : for inbound message code msgcode_rwbuffer (driver to IOP) 1028 ** byte 0 : 0xaa <-- signature 1029 ** byte 1 : 0x55 <-- signature 1030 ** byte 2 : year (04) 1031 ** byte 3 : month (1..12) 1032 ** byte 4 : date (1..31) 1033 ** byte 5 : hour (0..23) 1034 ** byte 6 : minute (0..59) 1035 ** byte 7 : second (0..59) 1036 ** 1037 ** <2> Doorbell Register is used for RS-232 emulation 1038 ** <A> different clear register 1039 ** <B> different bit0 definition (bit0 is reserved) 1040 ** 1041 ** inbound doorbell : at offset 0x20 1042 ** inbound doorbell clear : at offset 0x70 1043 ** 1044 ** inbound doorbell : bit0 -- reserved 1045 ** bit1 -- data in ready (DRIVER DATA WRITE OK) 1046 ** bit2 -- data out has been read (DRIVER DATA READ OK) 1047 ** bit3 -- inbound message 0 ready 1048 ** bit4 -- more than 12 request completed in a time 1049 ** 1050 ** outbound doorbell : at offset 0x9C 1051 ** outbound doorbell clear : at offset 0xA0 1052 ** 1053 ** outbound doorbell : bit0 -- reserved 1054 ** bit1 -- data out ready (IOP DATA WRITE OK) 1055 ** bit2 -- data in has been read (IOP DATA READ OK) 1056 ** bit3 -- outbound message 0 ready 1057 ** 1058 ** <3> Index Memory Usage (Buffer Area) 1059 ** COMPORT_IN at 0x2000: message_wbuffer -- 128 bytes (to be sent to ROC) : for RS232 in (scratch buffer) 1060 ** COMPORT_OUT at 0x2100: message_rbuffer -- 128 bytes (to be sent to host): for RS232 out (request buffer) 1061 ** BIOS_CFG_AREA at 0x2200: msgcode_rwbuffer -- 1024 bytes for outbound message code msgcode_rwbuffer (IOP send to driver) 1062 ** BIOS_CFG_AREA at 0x2200: msgcode_rwbuffer -- 1024 bytes for inbound message code msgcode_rwbuffer (driver send to IOP) 1063 ** 1064 ** <4> PostQ (Command Post Address) 1065 ** All SCSI Command must be sent through postQ: 1066 ** inbound queue port32 at offset 0x40 , 0x41, 0x42, 0x43 1067 ** inbound queue port64 at offset 0xC0 (lower)/0xC4 (upper) 1068 ** outbound queue port32 at offset 0x44 1069 ** outbound queue port64 at offset 0xC8 (lower)/0xCC (upper) 1070 ** <A> For 32bit queue, access low part is enough to send/receive request 1071 ** i.e. write 0x40/0xC0, ROC will get the request with high part == 0, the 1072 ** same for outbound queue port 1073 ** <B> For 64bit queue, if 64bit instruction is supported, use 64bit instruction 1074 ** to post inbound request in a single instruction, and use 64bit instruction 1075 ** to retrieve outbound request in a single instruction. 1076 ** If in 32bit environment, when sending inbound queue, write high part first 1077 ** then write low part. For receiving outbound request, read high part first 1078 ** then low part, to check queue empty, ONLY check high part to be 0xFFFFFFFF. 1079 ** If high part is 0xFFFFFFFF, DO NOT read low part, this may corrupt the 1080 ** consistency of the FIFO. Another way to check empty is to check status flag 1081 ** at 0x30 bit3. 1082 ** <C> Post Address IS NOT shifted (must be 16 bytes aligned) 1083 ** For BIOS, 16bytes aligned is OK 1084 ** For Driver, 32bytes alignment is recommended. 1085 ** POST Command bit0 to bit3 is defined differently 1086 ** ---------------------------- 1087 ** bit0:1 for PULL mode (must be 1) 1088 ** ---------------------------- 1089 ** bit3/2/1: for arcmsr cdb size (arccdbsize) 1090 ** 000: <= 0x0080 (128) 1091 ** 001: <= 0x0100 (256) 1092 ** 010: <= 0x0180 (384) 1093 ** 011: <= 0x0200 (512) 1094 ** 100: <= 0x0280 (640) 1095 ** 101: <= 0x0300 (768) 1096 ** 110: <= 0x0300 (reserved) 1097 ** 111: <= 0x0300 (reserved) 1098 ** ----------------------------- 1099 ** if len > 0x300 the len always set as 0x300 1100 ** ----------------------------- 1101 ** post addr = addr | ((len-1) >> 6) | 1 1102 ** ----------------------------- 1103 ** page length in command buffer still required, 1104 ** 1105 ** if page length > 3, 1106 ** firmware will assume more request data need to be retrieved 1107 ** 1108 ** <D> Outbound Posting 1109 ** bit0:0 , no error, 1 with error, refer to status buffer 1110 ** bit1:0 , reserved (will be 0) 1111 ** bit2:0 , reserved (will be 0) 1112 ** bit3:0 , reserved (will be 0) 1113 ** bit63-4: Completed command address 1114 ** 1115 ** <E> BIOS support, no special support is required. 1116 ** LSI2108 support I/O register 1117 ** All driver functionality is supported through I/O address 1118 ** 1119 ************************************************************************************************ 1120 */ 1121 /* 1122 ********************************** 1123 ** 1124 ********************************** 1125 */ 1126 /* size 8 bytes */ 1127 /* 32bit Scatter-Gather list */ 1128 struct SG32ENTRY { /* length bit 24 == 0 */ 1129 u_int32_t length; /* high 8 bit == flag,low 24 bit == length */ 1130 u_int32_t address; 1131 }; 1132 /* size 12 bytes */ 1133 /* 64bit Scatter-Gather list */ 1134 struct SG64ENTRY { /* length bit 24 == 1 */ 1135 u_int32_t length; /* high 8 bit == flag,low 24 bit == length */ 1136 u_int32_t address; 1137 u_int32_t addresshigh; 1138 }; 1139 struct SGENTRY_UNION { 1140 union { 1141 struct SG32ENTRY sg32entry; /* 30h Scatter gather address */ 1142 struct SG64ENTRY sg64entry; /* 30h */ 1143 }u; 1144 }; 1145 /* 1146 ********************************** 1147 ** 1148 ********************************** 1149 */ 1150 struct QBUFFER { 1151 u_int32_t data_len; 1152 u_int8_t data[124]; 1153 }; 1154 /* 1155 ********************************** 1156 */ 1157 typedef struct PHYS_ADDR64 { 1158 u_int32_t phyadd_low; 1159 u_int32_t phyadd_high; 1160 }PHYSADDR64; 1161 /* 1162 ************************************************************************************************ 1163 ** FIRMWARE INFO 1164 ************************************************************************************************ 1165 */ 1166 #define ARCMSR_FW_MODEL_OFFSET 15 1167 #define ARCMSR_FW_VERS_OFFSET 17 1168 #define ARCMSR_FW_DEVMAP_OFFSET 21 1169 #define ARCMSR_FW_CFGVER_OFFSET 25 1170 1171 struct FIRMWARE_INFO { 1172 u_int32_t signature; /*0,00-03*/ 1173 u_int32_t request_len; /*1,04-07*/ 1174 u_int32_t numbers_queue; /*2,08-11*/ 1175 u_int32_t sdram_size; /*3,12-15*/ 1176 u_int32_t ide_channels; /*4,16-19*/ 1177 char vendor[40]; /*5,20-59*/ 1178 char model[8]; /*15,60-67*/ 1179 char firmware_ver[16]; /*17,68-83*/ 1180 char device_map[16]; /*21,84-99*/ 1181 u_int32_t cfgVersion; /*25,100-103 Added for checking of new firmware capability*/ 1182 char cfgSerial[16]; /*26,104-119*/ 1183 u_int32_t cfgPicStatus; /*30,120-123*/ 1184 }; 1185 /* (A) For cfgVersion in FIRMWARE_INFO 1186 ** if low BYTE (byte#0) >= 3 (version 3) 1187 ** then byte#1 report the capability of the firmware can xfer in a single request 1188 ** 1189 ** byte#1 1190 ** 0 256K 1191 ** 1 512K 1192 ** 2 1M 1193 ** 3 2M 1194 ** 4 4M 1195 ** 5 8M 1196 ** 6 16M 1197 ** (B) Byte offset 7 (Reserved1) of CDB is changed to msgPages 1198 ** Driver support new xfer method need to set this field to indicate 1199 ** large CDB block in 0x100 unit (we use 0x100 byte as one page) 1200 ** e.g. If the length of CDB including MSG header and SGL is 0x1508 1201 ** driver need to set the msgPages to 0x16 1202 ** (C) REQ_LEN_512BYTE must be used also to indicate SRB length 1203 ** e.g. CDB len msgPages REQ_LEN_512BYTE flag 1204 ** <= 0x100 1 0 1205 ** <= 0x200 2 1 1206 ** <= 0x300 3 1 1207 ** <= 0x400 4 1 1208 ** . 1209 ** . 1210 */ 1211 1212 /* 1213 ************************************************************************************************ 1214 ** size 0x1F8 (504) 1215 ************************************************************************************************ 1216 */ 1217 struct ARCMSR_CDB { 1218 u_int8_t Bus; /* 00h should be 0 */ 1219 u_int8_t TargetID; /* 01h should be 0--15 */ 1220 u_int8_t LUN; /* 02h should be 0--7 */ 1221 u_int8_t Function; /* 03h should be 1 */ 1222 1223 u_int8_t CdbLength; /* 04h not used now */ 1224 u_int8_t sgcount; /* 05h */ 1225 u_int8_t Flags; /* 06h */ 1226 u_int8_t msgPages; /* 07h */ 1227 1228 u_int32_t Context; /* 08h Address of this request */ 1229 u_int32_t DataLength; /* 0ch not used now */ 1230 1231 u_int8_t Cdb[16]; /* 10h SCSI CDB */ 1232 /* 1233 ******************************************************** 1234 ** Device Status : the same from SCSI bus if error occur 1235 ** SCSI bus status codes. 1236 ******************************************************** 1237 */ 1238 u_int8_t DeviceStatus; /* 20h if error */ 1239 1240 u_int8_t SenseData[15]; /* 21h output */ 1241 1242 union { 1243 struct SG32ENTRY sg32entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h Scatter gather address */ 1244 struct SG64ENTRY sg64entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h */ 1245 } u; 1246 }; 1247 /* CDB flag */ 1248 #define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01 /* bit 0: 0(256) / 1(512) bytes */ 1249 #define ARCMSR_CDB_FLAG_BIOS 0x02 /* bit 1: 0(from driver) / 1(from BIOS) */ 1250 #define ARCMSR_CDB_FLAG_WRITE 0x04 /* bit 2: 0(Data in) / 1(Data out) */ 1251 #define ARCMSR_CDB_FLAG_SIMPLEQ 0x00 /* bit 4/3 ,00 : simple Q,01 : head of Q,10 : ordered Q */ 1252 #define ARCMSR_CDB_FLAG_HEADQ 0x08 1253 #define ARCMSR_CDB_FLAG_ORDEREDQ 0x10 1254 /* scsi status */ 1255 #define SCSISTAT_GOOD 0x00 1256 #define SCSISTAT_CHECK_CONDITION 0x02 1257 #define SCSISTAT_CONDITION_MET 0x04 1258 #define SCSISTAT_BUSY 0x08 1259 #define SCSISTAT_INTERMEDIATE 0x10 1260 #define SCSISTAT_INTERMEDIATE_COND_MET 0x14 1261 #define SCSISTAT_RESERVATION_CONFLICT 0x18 1262 #define SCSISTAT_COMMAND_TERMINATED 0x22 1263 #define SCSISTAT_QUEUE_FULL 0x28 1264 /* DeviceStatus */ 1265 #define ARCMSR_DEV_SELECT_TIMEOUT 0xF0 1266 #define ARCMSR_DEV_ABORTED 0xF1 1267 #define ARCMSR_DEV_INIT_FAIL 0xF2 1268 /* 1269 ********************************************************************* 1270 ** Command Control Block (SrbExtension) 1271 ** SRB must be not cross page boundary,and the order from offset 0 1272 ** structure describing an ATA disk request 1273 ** this SRB length must be 32 bytes boundary 1274 ********************************************************************* 1275 */ 1276 struct CommandControlBlock { 1277 struct ARCMSR_CDB arcmsr_cdb; /* 0 -503 (size of CDB=504): arcmsr messenger scsi command descriptor size 504 bytes */ 1278 u_int32_t cdb_phyaddr_low; /* 504-507 */ 1279 u_int32_t arc_cdb_size; /* 508-511 */ 1280 /* ======================512+32 bytes============================ */ 1281 union ccb *pccb; /* 512-515 516-519 pointer of freebsd scsi command */ 1282 struct AdapterControlBlock *acb; /* 520-523 524-527 */ 1283 bus_dmamap_t dm_segs_dmamap; /* 528-531 532-535 */ 1284 u_int16_t srb_flags; /* 536-537 */ 1285 u_int16_t srb_state; /* 538-539 */ 1286 u_int32_t cdb_phyaddr_high; /* 540-543 */ 1287 struct callout ccb_callout; 1288 u_int32_t smid; 1289 /* ========================================================== */ 1290 }; 1291 /* srb_flags */ 1292 #define SRB_FLAG_READ 0x0000 1293 #define SRB_FLAG_WRITE 0x0001 1294 #define SRB_FLAG_ERROR 0x0002 1295 #define SRB_FLAG_FLUSHCACHE 0x0004 1296 #define SRB_FLAG_MASTER_ABORTED 0x0008 1297 #define SRB_FLAG_DMAVALID 0x0010 1298 #define SRB_FLAG_DMACONSISTENT 0x0020 1299 #define SRB_FLAG_DMAWRITE 0x0040 1300 #define SRB_FLAG_PKTBIND 0x0080 1301 #define SRB_FLAG_TIMER_START 0x0080 1302 /* srb_state */ 1303 #define ARCMSR_SRB_DONE 0x0000 1304 #define ARCMSR_SRB_UNBUILD 0x0000 1305 #define ARCMSR_SRB_TIMEOUT 0x1111 1306 #define ARCMSR_SRB_RETRY 0x2222 1307 #define ARCMSR_SRB_START 0x55AA 1308 #define ARCMSR_SRB_PENDING 0xAA55 1309 #define ARCMSR_SRB_RESET 0xA5A5 1310 #define ARCMSR_SRB_ABORTED 0x5A5A 1311 #define ARCMSR_SRB_ILLEGAL 0xFFFF 1312 1313 #define SRB_SIZE ((sizeof(struct CommandControlBlock)+0x1f) & 0xffe0) 1314 #define ARCMSR_SRBS_POOL_SIZE (SRB_SIZE * ARCMSR_MAX_FREESRB_NUM) 1315 1316 /* 1317 ********************************************************************* 1318 ** Adapter Control Block 1319 ********************************************************************* 1320 */ 1321 #define ACB_ADAPTER_TYPE_A 0x00000000 /* hba I IOP */ 1322 #define ACB_ADAPTER_TYPE_B 0x00000001 /* hbb M IOP */ 1323 #define ACB_ADAPTER_TYPE_C 0x00000002 /* hbc L IOP */ 1324 #define ACB_ADAPTER_TYPE_D 0x00000003 /* hbd M IOP */ 1325 #define ACB_ADAPTER_TYPE_E 0x00000004 /* hbd L IOP */ 1326 #define ACB_ADAPTER_TYPE_F 0x00000005 /* hbd L IOP */ 1327 1328 struct AdapterControlBlock { 1329 u_int32_t adapter_type; /* adapter A,B..... */ 1330 1331 bus_space_tag_t btag[2]; 1332 bus_space_handle_t bhandle[2]; 1333 bus_dma_tag_t parent_dmat; 1334 bus_dma_tag_t dm_segs_dmat; /* dmat for buffer I/O */ 1335 bus_dma_tag_t srb_dmat; /* dmat for freesrb */ 1336 bus_dmamap_t srb_dmamap; 1337 device_t pci_dev; 1338 struct cdev *ioctl_dev; 1339 int pci_unit; 1340 1341 struct resource *sys_res_arcmsr[2]; 1342 struct resource *irqres[ARCMSR_NUM_MSIX_VECTORS]; 1343 void *ih[ARCMSR_NUM_MSIX_VECTORS]; /* interrupt handle */ 1344 int irq_id[ARCMSR_NUM_MSIX_VECTORS]; 1345 1346 /* Hooks into the CAM XPT */ 1347 struct cam_sim *psim; 1348 struct cam_path *ppath; 1349 u_int8_t *uncacheptr; 1350 unsigned long vir2phy_offset; 1351 union { 1352 unsigned long phyaddr; 1353 struct { 1354 u_int32_t phyadd_low; 1355 u_int32_t phyadd_high; 1356 }B; 1357 }srb_phyaddr; 1358 // unsigned long srb_phyaddr; 1359 /* Offset is used in making arc cdb physical to virtual calculations */ 1360 u_int32_t outbound_int_enable; 1361 1362 struct MessageUnit_UNION *pmu; /* message unit ATU inbound base address0 */ 1363 uint32_t *message_wbuffer; //0x000 - COMPORT_IN (to be sent to ROC) 1364 uint32_t *message_rbuffer; //0x100 - COMPORT_OUT (to be sent to Host) 1365 uint32_t *msgcode_rwbuffer; //0x200 - BIOS_AREA 1366 1367 u_int8_t adapter_index; 1368 u_int8_t irq; 1369 u_int16_t acb_flags; 1370 1371 struct CommandControlBlock *psrb_pool[ARCMSR_MAX_FREESRB_NUM]; /* serial srb pointer array */ 1372 struct CommandControlBlock *srbworkingQ[ARCMSR_MAX_FREESRB_NUM]; /* working srb pointer array */ 1373 int32_t workingsrb_doneindex; /* done srb array index */ 1374 int32_t workingsrb_startindex; /* start srb array index */ 1375 int32_t srboutstandingcount; 1376 1377 u_int8_t rqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for read from 80331 */ 1378 u_int32_t rqbuf_firstindex; /* first of read buffer */ 1379 u_int32_t rqbuf_lastindex; /* last of read buffer */ 1380 1381 u_int8_t wqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for write to 80331 */ 1382 u_int32_t wqbuf_firstindex; /* first of write buffer */ 1383 u_int32_t wqbuf_lastindex; /* last of write buffer */ 1384 1385 arcmsr_lock_t isr_lock; 1386 arcmsr_lock_t srb_lock; 1387 arcmsr_lock_t postDone_lock; 1388 arcmsr_lock_t qbuffer_lock; 1389 1390 u_int8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN]; /* id0 ..... id15,lun0...lun7 */ 1391 u_int32_t num_resets; 1392 u_int32_t num_aborts; 1393 u_int32_t firm_request_len; /*1,04-07*/ 1394 u_int32_t firm_numbers_queue; /*2,08-11*/ 1395 u_int32_t firm_sdram_size; /*3,12-15*/ 1396 u_int32_t firm_ide_channels; /*4,16-19*/ 1397 u_int32_t firm_cfg_version; 1398 char firm_model[12]; /*15,60-67*/ 1399 char firm_version[20]; /*17,68-83*/ 1400 char device_map[20]; /*21,84-99 */ 1401 struct callout devmap_callout; 1402 u_int32_t pktRequestCount; 1403 u_int32_t pktReturnCount; 1404 u_int32_t vendor_device_id; 1405 u_int32_t adapter_bus_speed; 1406 u_int32_t maxOutstanding; 1407 u_int16_t sub_device_id; 1408 u_int32_t doneq_index; 1409 u_int32_t in_doorbell; 1410 u_int32_t out_doorbell; 1411 u_int32_t completionQ_entry; 1412 pCompletion_Q pCompletionQ; 1413 int msix_vectors; 1414 int rid[2]; 1415 unsigned long completeQ_phys; 1416 };/* HW_DEVICE_EXTENSION */ 1417 /* acb_flags */ 1418 #define ACB_F_SCSISTOPADAPTER 0x0001 1419 #define ACB_F_MSG_STOP_BGRB 0x0002 /* stop RAID background rebuild */ 1420 #define ACB_F_MSG_START_BGRB 0x0004 /* stop RAID background rebuild */ 1421 #define ACB_F_IOPDATA_OVERFLOW 0x0008 /* iop ioctl data rqbuffer overflow */ 1422 #define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010 /* ioctl clear wqbuffer */ 1423 #define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020 /* ioctl clear rqbuffer */ 1424 #define ACB_F_MESSAGE_WQBUFFER_READ 0x0040 1425 #define ACB_F_BUS_RESET 0x0080 1426 #define ACB_F_IOP_INITED 0x0100 /* iop init */ 1427 #define ACB_F_MAPFREESRB_FAILD 0x0200 /* arcmsr_map_freesrb faild */ 1428 #define ACB_F_CAM_DEV_QFRZN 0x0400 1429 #define ACB_F_BUS_HANG_ON 0x0800 /* need hardware reset bus */ 1430 #define ACB_F_SRB_FUNCTION_POWER 0x1000 1431 #define ACB_F_MSIX_ENABLED 0x2000 1432 /* devstate */ 1433 #define ARECA_RAID_GONE 0x55 1434 #define ARECA_RAID_GOOD 0xaa 1435 /* adapter_bus_speed */ 1436 #define ACB_BUS_SPEED_3G 0 1437 #define ACB_BUS_SPEED_6G 1 1438 #define ACB_BUS_SPEED_12G 2 1439 /* 1440 ************************************************************* 1441 ************************************************************* 1442 */ 1443 struct SENSE_DATA { 1444 u_int8_t ErrorCode:7; 1445 u_int8_t Valid:1; 1446 u_int8_t SegmentNumber; 1447 u_int8_t SenseKey:4; 1448 u_int8_t Reserved:1; 1449 u_int8_t IncorrectLength:1; 1450 u_int8_t EndOfMedia:1; 1451 u_int8_t FileMark:1; 1452 u_int8_t Information[4]; 1453 u_int8_t AdditionalSenseLength; 1454 u_int8_t CommandSpecificInformation[4]; 1455 u_int8_t AdditionalSenseCode; 1456 u_int8_t AdditionalSenseCodeQualifier; 1457 u_int8_t FieldReplaceableUnitCode; 1458 u_int8_t SenseKeySpecific[3]; 1459 }; 1460 /* 1461 ********************************** 1462 ** Peripheral Device Type definitions 1463 ********************************** 1464 */ 1465 #define SCSI_DASD 0x00 /* Direct-access Device */ 1466 #define SCSI_SEQACESS 0x01 /* Sequential-access device */ 1467 #define SCSI_PRINTER 0x02 /* Printer device */ 1468 #define SCSI_PROCESSOR 0x03 /* Processor device */ 1469 #define SCSI_WRITEONCE 0x04 /* Write-once device */ 1470 #define SCSI_CDROM 0x05 /* CD-ROM device */ 1471 #define SCSI_SCANNER 0x06 /* Scanner device */ 1472 #define SCSI_OPTICAL 0x07 /* Optical memory device */ 1473 #define SCSI_MEDCHGR 0x08 /* Medium changer device */ 1474 #define SCSI_COMM 0x09 /* Communications device */ 1475 #define SCSI_NODEV 0x1F /* Unknown or no device type */ 1476 /* 1477 ************************************************************************************************************ 1478 ** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 1479 ** 80331 PCI-to-PCI Bridge 1480 ** PCI Configuration Space 1481 ** 1482 ** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 1483 ** Programming Interface 1484 ** ======================== 1485 ** Configuration Register Address Space Groupings and Ranges 1486 ** ============================================================= 1487 ** Register Group Configuration Offset 1488 ** ------------------------------------------------------------- 1489 ** Standard PCI Configuration 00-3Fh 1490 ** ------------------------------------------------------------- 1491 ** Device Specific Registers 40-A7h 1492 ** ------------------------------------------------------------- 1493 ** Reserved A8-CBh 1494 ** ------------------------------------------------------------- 1495 ** Enhanced Capability List CC-FFh 1496 ** ========================================================================================================== 1497 ** Standard PCI [Type 1] Configuration Space Address Map 1498 ** ********************************************************************************************************** 1499 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 1500 ** ---------------------------------------------------------------------------------------------------------- 1501 ** | Device ID | Vendor ID | 00h 1502 ** ---------------------------------------------------------------------------------------------------------- 1503 ** | Primary Status | Primary Command | 04h 1504 ** ---------------------------------------------------------------------------------------------------------- 1505 ** | Class Code | RevID | 08h 1506 ** ---------------------------------------------------------------------------------------------------------- 1507 ** | reserved | Header Type | Primary MLT | Primary CLS | 0Ch 1508 ** ---------------------------------------------------------------------------------------------------------- 1509 ** | Reserved | 10h 1510 ** ---------------------------------------------------------------------------------------------------------- 1511 ** | Reserved | 14h 1512 ** ---------------------------------------------------------------------------------------------------------- 1513 ** | Secondary MLT | Subordinate Bus Number | Secondary Bus Number | Primary Bus Number | 18h 1514 ** ---------------------------------------------------------------------------------------------------------- 1515 ** | Secondary Status | I/O Limit | I/O Base | 1Ch 1516 ** ---------------------------------------------------------------------------------------------------------- 1517 ** | Non-prefetchable Memory Limit Address | Non-prefetchable Memory Base Address | 20h 1518 ** ---------------------------------------------------------------------------------------------------------- 1519 ** | Prefetchable Memory Limit Address | Prefetchable Memory Base Address | 24h 1520 ** ---------------------------------------------------------------------------------------------------------- 1521 ** | Prefetchable Memory Base Address Upper 32 Bits | 28h 1522 ** ---------------------------------------------------------------------------------------------------------- 1523 ** | Prefetchable Memory Limit Address Upper 32 Bits | 2Ch 1524 ** ---------------------------------------------------------------------------------------------------------- 1525 ** | I/O Limit Upper 16 Bits | I/O Base Upper 16 | 30h 1526 ** ---------------------------------------------------------------------------------------------------------- 1527 ** | Reserved | Capabilities Pointer | 34h 1528 ** ---------------------------------------------------------------------------------------------------------- 1529 ** | Reserved | 38h 1530 ** ---------------------------------------------------------------------------------------------------------- 1531 ** | Bridge Control | Primary Interrupt Pin | Primary Interrupt Line | 3Ch 1532 **============================================================================================================= 1533 */ 1534 /* 1535 **============================================================================================================= 1536 ** 0x03-0x00 : 1537 ** Bit Default Description 1538 **31:16 0335h Device ID (DID): Indicates the unique device ID that is assigned to bridge by the PCI SIG. 1539 ** ID is unique per product speed as indicated. 1540 **15:00 8086h Vendor ID (VID): 16-bit field which indicates that Intel is the vendor. 1541 **============================================================================================================= 1542 */ 1543 #define ARCMSR_PCI2PCI_VENDORID_REG 0x00 /*word*/ 1544 #define ARCMSR_PCI2PCI_DEVICEID_REG 0x02 /*word*/ 1545 /* 1546 **============================================================================== 1547 ** 0x05-0x04 : command register 1548 ** Bit Default Description 1549 **15:11 00h Reserved 1550 ** 10 0 Interrupt Disable: Disables/Enables the generation of Interrupts on the primary bus. 1551 ** The bridge does not support interrupts. 1552 ** 09 0 FB2B Enable: Enables/Disables the generation of fast back to back 1553 ** transactions on the primary bus. 1554 ** The bridge does not generate fast back to back 1555 ** transactions on the primary bus. 1556 ** 08 0 SERR# Enable (SEE): Enables primary bus SERR# assertions. 1557 ** 0=The bridge does not assert P_SERR#. 1558 ** 1=The bridge may assert P_SERR#, subject to other programmable criteria. 1559 ** 07 0 Wait Cycle Control (WCC): Always returns 0bzero indicating 1560 ** that bridge does not perform address or data stepping, 1561 ** 06 0 Parity Error Response (PER): Controls bridge response to a detected primary bus parity error. 1562 ** 0=When a data parity error is detected bridge does not assert S_PERR#. 1563 ** Also bridge does not assert P_SERR# in response to 1564 ** a detected address or attribute parity error. 1565 ** 1=When a data parity error is detected bridge asserts S_PERR#. 1566 ** The bridge also asserts P_SERR# 1567 ** (when enabled globally via bit(8) of this register) 1568 ** in response to a detected address or attribute parity error. 1569 ** 05 0 VGA Palette Snoop Enable (VGA_PSE): Controls bridge response to VGA-compatible palette write transactions. 1570 ** VGA palette write transactions are I/O transactions 1571 ** whose address bits are: P_AD[9:0] equal to 3C6h, 3C8h or 3C9h 1572 ** P_AD[15:10] are not decoded (i.e. aliases are claimed), 1573 ** or are fully decoding 1574 ** (i.e., must be all 0's depending upon the VGA 1575 ** aliasing bit in the Bridge Control Register, offset 3Eh. 1576 ** P_AD[31:16] equal to 0000h 1577 ** 0=The bridge ignores VGA palette write transactions, 1578 ** unless decoded by the standard I/O address range window. 1579 ** 1=The bridge responds to VGA palette write transactions 1580 ** with medium DEVSEL# timing and forwards them to the secondary bus. 1581 ** 04 0 Memory Write and Invalidate Enable (MWIE): The bridge does not promote MW transactions to MWI transactions. 1582 ** MWI transactions targeting resources on the opposite side of the bridge, 1583 ** however, are forwarded as MWI transactions. 1584 ** 03 0 Special Cycle Enable (SCE): The bridge ignores special cycle transactions. 1585 ** This bit is read only and always returns 0 when read 1586 ** 02 0 Bus Master Enable (BME): Enables bridge to initiate memory and I/O transactions on the primary interface. 1587 ** Initiation of configuration transactions is not affected by the state of this bit. 1588 ** 0=The bridge does not initiate memory or I/O transactions on the primary interface. 1589 ** 1=The bridge is enabled to function as an initiator on the primary interface. 1590 ** 01 0 Memory Space Enable (MSE): Controls target response to memory transactions on the primary interface. 1591 ** 0=The bridge target response to memory transactions on the primary interface is disabled. 1592 ** 1=The bridge target response to memory transactions on the primary interface is enabled. 1593 ** 00 0 I/O Space Enable (IOSE): Controls target response to I/O transactions on the primary interface. 1594 ** 0=The bridge target response to I/O transactions on the primary interface is disabled. 1595 ** 1=The bridge target response to I/O transactions on the primary interface is enabled. 1596 **============================================================================== 1597 */ 1598 #define ARCMSR_PCI2PCI_PRIMARY_COMMAND_REG 0x04 /*word*/ 1599 #define PCI_DISABLE_INTERRUPT 0x0400 1600 /* 1601 **============================================================================== 1602 ** 0x07-0x06 : status register 1603 ** Bit Default Description 1604 ** 15 0 Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address, 1605 ** attribute or data parity error. 1606 ** This bit is set regardless of the state of the PER bit in the command register. 1607 ** 14 0 Signaled System Error: The bridge sets this bit to a 1b whenever it asserts SERR# on the primary bus. 1608 ** 13 0 Received Master Abort: The bridge sets this bit to a 1b when, 1609 ** acting as the initiator on the primary bus, 1610 ** its transaction (with the exception of special cycles) 1611 ** has been terminated with a Master Abort. 1612 ** 12 0 Received Target Abort: The bridge sets this bit to a 1b when, 1613 ** acting as the initiator on the primary bus, 1614 ** its transaction has been terminated with a Target Abort. 1615 ** 11 0 Signaled Target Abort: The bridge sets this bit to a 1b when it, 1616 ** as the target of a transaction, terminates it with a Target Abort. 1617 ** In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code. 1618 ** 10:09 01 DEVSEL# Timing: Indicates slowest response to a non-configuration command on the primary interface. 1619 ** Returns ��01b�� when read, indicating that bridge responds no slower than with medium timing. 1620 ** 08 0 Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true: 1621 ** The bridge is the current master on the primary bus 1622 ** S_PERR# is detected asserted or is asserted by bridge 1623 ** The Parity Error Response bit is set in the Command register 1624 ** 07 1 Fast Back to Back Capable: Returns a 1b when read indicating that bridge 1625 ** is able to respond to fast back to back transactions on its primary interface. 1626 ** 06 0 Reserved 1627 ** 05 1 66 MHz Capable Indication: Returns a 1b when read indicating that bridge primary interface is 66 MHz capable. 1628 ** 1 = 1629 ** 04 1 Capabilities List Enable: Returns 1b when read indicating that bridge supports PCI standard enhanced capabilities. 1630 ** Offset 34h (Capability Pointer register) 1631 ** provides the offset for the first entry 1632 ** in the linked list of enhanced capabilities. 1633 ** 03 0 Interrupt Status: Reflects the state of the interrupt in the device/function. 1634 ** The bridge does not support interrupts. 1635 ** 02:00 000 Reserved 1636 **============================================================================== 1637 */ 1638 #define ARCMSR_PCI2PCI_PRIMARY_STATUS_REG 0x06 /*word: 06,07 */ 1639 #define ARCMSR_ADAP_66MHZ 0x20 1640 /* 1641 **============================================================================== 1642 ** 0x08 : revision ID 1643 ** Bit Default Description 1644 ** 07:00 00000000 Revision ID (RID): '00h' indicating bridge A-0 stepping. 1645 **============================================================================== 1646 */ 1647 #define ARCMSR_PCI2PCI_REVISIONID_REG 0x08 /*byte*/ 1648 /* 1649 **============================================================================== 1650 ** 0x0b-0x09 : 0180_00 (class code 1,native pci mode ) 1651 ** Bit Default Description 1652 ** 23:16 06h Base Class Code (BCC): Indicates that this is a bridge device. 1653 ** 15:08 04h Sub Class Code (SCC): Indicates this is of type PCI-to-PCI bridge. 1654 ** 07:00 00h Programming Interface (PIF): Indicates that this is standard (non-subtractive) PCI-PCI bridge. 1655 **============================================================================== 1656 */ 1657 #define ARCMSR_PCI2PCI_CLASSCODE_REG 0x09 /*3bytes*/ 1658 /* 1659 **============================================================================== 1660 ** 0x0c : cache line size 1661 ** Bit Default Description 1662 ** 07:00 00h Cache Line Size (CLS): Designates the cache line size in 32-bit dword units. 1663 ** The contents of this register are factored into 1664 ** internal policy decisions associated with memory read prefetching, 1665 ** and the promotion of Memory Write transactions to MWI transactions. 1666 ** Valid cache line sizes are 8 and 16 dwords. 1667 ** When the cache line size is set to an invalid value, 1668 ** bridge behaves as though the cache line size was set to 00h. 1669 **============================================================================== 1670 */ 1671 #define ARCMSR_PCI2PCI_PRIMARY_CACHELINESIZE_REG 0x0C /*byte*/ 1672 /* 1673 **============================================================================== 1674 ** 0x0d : latency timer (number of pci clock 00-ff ) 1675 ** Bit Default Description 1676 ** Primary Latency Timer (PTV): 1677 ** 07:00 00h (Conventional PCI) Conventional PCI Mode: Primary bus Master latency timer. Indicates the number of PCI clock cycles, 1678 ** referenced from the assertion of FRAME# to the expiration of the timer, 1679 ** when bridge may continue as master of the current transaction. All bits are writable, 1680 ** resulting in a granularity of 1 PCI clock cycle. 1681 ** When the timer expires (i.e., equals 00h) 1682 ** bridge relinquishes the bus after the first data transfer 1683 ** when its PCI bus grant has been deasserted. 1684 ** or 40h (PCI-X) PCI-X Mode: Primary bus Master latency timer. 1685 ** Indicates the number of PCI clock cycles, 1686 ** referenced from the assertion of FRAME# to the expiration of the timer, 1687 ** when bridge may continue as master of the current transaction. 1688 ** All bits are writable, resulting in a granularity of 1 PCI clock cycle. 1689 ** When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB. 1690 ** (Except in the case where MLT expires within 3 data phases 1691 ** of an ADB.In this case bridge continues on 1692 ** until it reaches the next ADB before relinquishing the bus.) 1693 **============================================================================== 1694 */ 1695 #define ARCMSR_PCI2PCI_PRIMARY_LATENCYTIMER_REG 0x0D /*byte*/ 1696 /* 1697 **============================================================================== 1698 ** 0x0e : (header type,single function ) 1699 ** Bit Default Description 1700 ** 07 0 Multi-function device (MVD): 80331 is a single-function device. 1701 ** 06:00 01h Header Type (HTYPE): Defines the layout of addresses 10h through 3Fh in configuration space. 1702 ** Returns ��01h�� when read indicating 1703 ** that the register layout conforms to the standard PCI-to-PCI bridge layout. 1704 **============================================================================== 1705 */ 1706 #define ARCMSR_PCI2PCI_HEADERTYPE_REG 0x0E /*byte*/ 1707 /* 1708 **============================================================================== 1709 ** 0x0f : 1710 **============================================================================== 1711 */ 1712 /* 1713 **============================================================================== 1714 ** 0x13-0x10 : 1715 ** PCI CFG Base Address #0 (0x10) 1716 **============================================================================== 1717 */ 1718 /* 1719 **============================================================================== 1720 ** 0x17-0x14 : 1721 ** PCI CFG Base Address #1 (0x14) 1722 **============================================================================== 1723 */ 1724 /* 1725 **============================================================================== 1726 ** 0x1b-0x18 : 1727 ** PCI CFG Base Address #2 (0x18) 1728 **-----------------0x1A,0x19,0x18--Bus Number Register - BNR 1729 ** Bit Default Description 1730 ** 23:16 00h Subordinate Bus Number (SBBN): Indicates the highest PCI bus number below this bridge. 1731 ** Any Type 1 configuration cycle 1732 ** on the primary bus whose bus number is greater than the secondary bus number, 1733 ** and less than or equal to the subordinate bus number 1734 ** is forwarded unaltered as a Type 1 configuration cycle on the secondary PCI bus. 1735 ** 15:08 00h Secondary Bus Number (SCBN): Indicates the bus number of PCI to which the secondary interface is connected. 1736 ** Any Type 1 configuration cycle matching this bus number 1737 ** is translated to a Type 0 configuration cycle (or a Special Cycle) 1738 ** before being executed on bridge's secondary PCI bus. 1739 ** 07:00 00h Primary Bus Number (PBN): Indicates bridge primary bus number. 1740 ** Any Type 1 configuration cycle on the primary interface 1741 ** with a bus number that is less than the contents 1742 ** of this register field does not be claimed by bridge. 1743 **-----------------0x1B--Secondary Latency Timer Register - SLTR 1744 ** Bit Default Description 1745 ** Secondary Latency Timer (STV): 1746 ** 07:00 00h (Conventional PCI) Conventional PCI Mode: Secondary bus Master latency timer. 1747 ** Indicates the number of PCI clock cycles, 1748 ** referenced from the assertion of FRAME# to the expiration of the timer, 1749 ** when bridge may continue as master of the current transaction. All bits are writable, 1750 ** resulting in a granularity of 1 PCI clock cycle. 1751 ** When the timer expires (i.e., equals 00h) 1752 ** bridge relinquishes the bus after the first data transfer 1753 ** when its PCI bus grant has been deasserted. 1754 ** or 40h (PCI-X) PCI-X Mode: Secondary bus Master latency timer. 1755 ** Indicates the number of PCI clock cycles,referenced from the assertion of FRAME# 1756 ** to the expiration of the timer, 1757 ** when bridge may continue as master of the current transaction. All bits are writable, 1758 ** resulting in a granularity of 1 PCI clock cycle. 1759 ** When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB. 1760 ** (Except in the case where MLT expires within 3 data phases of an ADB. 1761 ** In this case bridge continues on until it reaches the next ADB 1762 ** before relinquishing the bus) 1763 **============================================================================== 1764 */ 1765 #define ARCMSR_PCI2PCI_PRIMARY_BUSNUMBER_REG 0x18 /*3byte 0x1A,0x19,0x18*/ 1766 #define ARCMSR_PCI2PCI_SECONDARY_BUSNUMBER_REG 0x19 /*byte*/ 1767 #define ARCMSR_PCI2PCI_SUBORDINATE_BUSNUMBER_REG 0x1A /*byte*/ 1768 #define ARCMSR_PCI2PCI_SECONDARY_LATENCYTIMER_REG 0x1B /*byte*/ 1769 /* 1770 **============================================================================== 1771 ** 0x1f-0x1c : 1772 ** PCI CFG Base Address #3 (0x1C) 1773 **-----------------0x1D,0x1C--I/O Base and Limit Register - IOBL 1774 ** Bit Default Description 1775 ** 15:12 0h I/O Limit Address Bits [15:12]: Defines the top address of an address range to 1776 ** determine when to forward I/O transactions from one interface to the other. 1777 ** These bits correspond to address lines 15:12 for 4KB alignment. 1778 ** Bits 11:0 are assumed to be FFFh. 1779 ** 11:08 1h I/O Limit Addressing Capability: This field is hard-wired to 1h, indicating support 32-bit I/O addressing. 1780 ** 07:04 0h I/O Base Address Bits [15:12]: Defines the bottom address of 1781 ** an address range to determine when to forward I/O transactions 1782 ** from one interface to the other. 1783 ** These bits correspond to address lines 15:12 for 4KB alignment. 1784 ** Bits 11:0 are assumed to be 000h. 1785 ** 03:00 1h I/O Base Addressing Capability: This is hard-wired to 1h, indicating support for 32-bit I/O addressing. 1786 **-----------------0x1F,0x1E--Secondary Status Register - SSR 1787 ** Bit Default Description 1788 ** 15 0b Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address, 1789 ** attribute or data parity error on its secondary interface. 1790 ** 14 0b Received System Error: The bridge sets this bit when it samples SERR# asserted on its secondary bus interface. 1791 ** 13 0b Received Master Abort: The bridge sets this bit to a 1b when, 1792 ** acting as the initiator on the secondary bus, 1793 ** it's transaction (with the exception of special cycles) 1794 ** has been terminated with a Master Abort. 1795 ** 12 0b Received Target Abort: The bridge sets this bit to a 1b when, 1796 ** acting as the initiator on the secondary bus, 1797 ** it's transaction has been terminated with a Target Abort. 1798 ** 11 0b Signaled Target Abort: The bridge sets this bit to a 1b when it, 1799 ** as the target of a transaction, terminates it with a Target Abort. 1800 ** In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code. 1801 ** 10:09 01b DEVSEL# Timing: Indicates slowest response to a non-configuration command on the secondary interface. 1802 ** Returns ��01b�� when read, indicating that bridge responds no slower than with medium timing. 1803 ** 08 0b Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true: 1804 ** The bridge is the current master on the secondary bus 1805 ** S_PERR# is detected asserted or is asserted by bridge 1806 ** The Parity Error Response bit is set in the Command register 1807 ** 07 1b Fast Back-to-Back Capable (FBC): Indicates that the secondary interface of bridge can receive fast back-to-back cycles. 1808 ** 06 0b Reserved 1809 ** 05 1b 66 MHz Capable (C66): Indicates the secondary interface of the bridge is 66 MHz capable. 1810 ** 1 = 1811 ** 04:00 00h Reserved 1812 **============================================================================== 1813 */ 1814 #define ARCMSR_PCI2PCI_IO_BASE_REG 0x1C /*byte*/ 1815 #define ARCMSR_PCI2PCI_IO_LIMIT_REG 0x1D /*byte*/ 1816 #define ARCMSR_PCI2PCI_SECONDARY_STATUS_REG 0x1E /*word: 0x1F,0x1E */ 1817 /* 1818 **============================================================================== 1819 ** 0x23-0x20 : 1820 ** PCI CFG Base Address #4 (0x20) 1821 **-----------------0x23,0x22,0x21,0x20--Memory Base and Limit Register - MBL 1822 ** Bit Default Description 1823 ** 31:20 000h Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine 1824 ** the upper 1MB aligned value (exclusive) of the range. 1825 ** The incoming address must be less than or equal to this value. 1826 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0] 1827 ** are assumed to be F FFFFh. 1828 ** 19:16 0h Reserved. 1829 ** 15:04 000h Memory Base: These 12 bits are compared with bits P_AD[31:20] 1830 ** of the incoming address to determine the lower 1MB 1831 ** aligned value (inclusive) of the range. 1832 ** The incoming address must be greater than or equal to this value. 1833 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0]) 1834 ** are assumed to be 0 0000h. 1835 ** 03:00 0h Reserved. 1836 **============================================================================== 1837 */ 1838 #define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_BASE_REG 0x20 /*word: 0x21,0x20 */ 1839 #define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_LIMIT_REG 0x22 /*word: 0x23,0x22 */ 1840 /* 1841 **============================================================================== 1842 ** 0x27-0x24 : 1843 ** PCI CFG Base Address #5 (0x24) 1844 **-----------------0x27,0x26,0x25,0x24--Prefetchable Memory Base and Limit Register - PMBL 1845 ** Bit Default Description 1846 ** 31:20 000h Prefetchable Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine 1847 ** the upper 1MB aligned value (exclusive) of the range. 1848 ** The incoming address must be less than or equal to this value. 1849 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0] 1850 ** are assumed to be F FFFFh. 1851 ** 19:16 1h 64-bit Indicator: Indicates that 64-bit addressing is supported. 1852 ** 15:04 000h Prefetchable Memory Base: These 12 bits are compared with bits P_AD[31:20] 1853 ** of the incoming address to determine the lower 1MB aligned value (inclusive) 1854 ** of the range. 1855 ** The incoming address must be greater than or equal to this value. 1856 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0]) 1857 ** are assumed to be 0 0000h. 1858 ** 03:00 1h 64-bit Indicator: Indicates that 64-bit addressing is supported. 1859 **============================================================================== 1860 */ 1861 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_REG 0x24 /*word: 0x25,0x24 */ 1862 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_REG 0x26 /*word: 0x27,0x26 */ 1863 /* 1864 **============================================================================== 1865 ** 0x2b-0x28 : 1866 ** Bit Default Description 1867 ** 31:00 00000000h Prefetchable Memory Base Upper Portion: All bits are read/writable 1868 ** bridge supports full 64-bit addressing. 1869 **============================================================================== 1870 */ 1871 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_UPPER32_REG 0x28 /*dword: 0x2b,0x2a,0x29,0x28 */ 1872 /* 1873 **============================================================================== 1874 ** 0x2f-0x2c : 1875 ** Bit Default Description 1876 ** 31:00 00000000h Prefetchable Memory Limit Upper Portion: All bits are read/writable 1877 ** bridge supports full 64-bit addressing. 1878 **============================================================================== 1879 */ 1880 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_UPPER32_REG 0x2C /*dword: 0x2f,0x2e,0x2d,0x2c */ 1881 /* 1882 **============================================================================== 1883 ** 0x33-0x30 : 1884 ** Bit Default Description 1885 ** 07:00 DCh Capabilities Pointer: Pointer to the first CAP ID entry in the capabilities list is at DCh in PCI configuration 1886 ** space. (Power Management Capability Registers) 1887 **============================================================================== 1888 */ 1889 #define ARCMSR_PCI2PCI_CAPABILITIES_POINTER_REG 0x34 /*byte*/ 1890 /* 1891 **============================================================================== 1892 ** 0x3b-0x35 : reserved 1893 **============================================================================== 1894 */ 1895 /* 1896 **============================================================================== 1897 ** 0x3d-0x3c : 1898 ** 1899 ** Bit Default Description 1900 ** 15:08 00h Interrupt Pin (PIN): Bridges do not support the generation of interrupts. 1901 ** 07:00 00h Interrupt Line (LINE): The bridge does not generate interrupts, so this is reserved as '00h'. 1902 **============================================================================== 1903 */ 1904 #define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_LINE_REG 0x3C /*byte*/ 1905 #define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_PIN_REG 0x3D /*byte*/ 1906 /* 1907 **============================================================================== 1908 ** 0x3f-0x3e : 1909 ** Bit Default Description 1910 ** 15:12 0h Reserved 1911 ** 11 0b Discard Timer SERR# Enable: Controls the generation of SERR# on the primary interface (P_SERR#) in response 1912 ** to a timer discard on either the primary or secondary interface. 1913 ** 0b=SERR# is not asserted. 1914 ** 1b=SERR# is asserted. 1915 ** 10 0b Discard Timer Status (DTS): This bit is set to a '1b' when either the primary or secondary discard timer expires. 1916 ** The delayed completion is then discarded. 1917 ** 09 0b Secondary Discard Timer (SDT): Sets the maximum number of PCI clock cycles 1918 ** that bridge waits for an initiator on the secondary bus 1919 ** to repeat a delayed transaction request. 1920 ** The counter starts when the delayed transaction completion is ready 1921 ** to be returned to the initiator. 1922 ** When the initiator has not repeated the transaction 1923 ** at least once before the counter expires,bridge 1924 ** discards the delayed transaction from its queues. 1925 ** 0b=The secondary master time-out counter is 2 15 PCI clock cycles. 1926 ** 1b=The secondary master time-out counter is 2 10 PCI clock cycles. 1927 ** 08 0b Primary Discard Timer (PDT): Sets the maximum number of PCI clock cycles 1928 ** that bridge waits for an initiator on the primary bus 1929 ** to repeat a delayed transaction request. 1930 ** The counter starts when the delayed transaction completion 1931 ** is ready to be returned to the initiator. 1932 ** When the initiator has not repeated the transaction 1933 ** at least once before the counter expires, 1934 ** bridge discards the delayed transaction from its queues. 1935 ** 0b=The primary master time-out counter is 2 15 PCI clock cycles. 1936 ** 1b=The primary master time-out counter is 2 10 PCI clock cycles. 1937 ** 07 0b Fast Back-to-Back Enable (FBE): The bridge does not initiate back to back transactions. 1938 ** 06 0b Secondary Bus Reset (SBR): 1939 ** When cleared to 0b: The bridge deasserts S_RST#, 1940 ** when it had been asserted by writing this bit to a 1b. 1941 ** When set to 1b: The bridge asserts S_RST#. 1942 ** 05 0b Master Abort Mode (MAM): Dictates bridge behavior on the initiator bus 1943 ** when a master abort termination occurs in response to 1944 ** a delayed transaction initiated by bridge on the target bus. 1945 ** 0b=The bridge asserts TRDY# in response to a non-locked delayed transaction, 1946 ** and returns FFFF FFFFh when a read. 1947 ** 1b=When the transaction had not yet been completed on the initiator bus 1948 ** (e.g.,delayed reads, or non-posted writes), 1949 ** then bridge returns a Target Abort in response to the original requester 1950 ** when it returns looking for its delayed completion on the initiator bus. 1951 ** When the transaction had completed on the initiator bus (e.g., a PMW), 1952 ** then bridge asserts P_SERR# (when enabled). 1953 ** For PCI-X transactions this bit is an enable for the assertion of P_SERR# due to a master abort 1954 ** while attempting to deliver a posted memory write on the destination bus. 1955 ** 04 0b VGA Alias Filter Enable: This bit dictates bridge behavior in conjunction with the VGA enable bit 1956 ** (also of this register), 1957 ** and the VGA Palette Snoop Enable bit (Command Register). 1958 ** When the VGA enable, or VGA Palette Snoop enable bits are on (i.e., 1b) 1959 ** the VGA Aliasing bit for the corresponding enabled functionality,: 1960 ** 0b=Ignores address bits AD[15:10] when decoding VGA I/O addresses. 1961 ** 1b=Ensures that address bits AD[15:10] equal 000000b when decoding VGA I/O addresses. 1962 ** When all VGA cycle forwarding is disabled, (i.e., VGA Enable bit =0b and VGA Palette Snoop bit =0b), 1963 ** then this bit has no impact on bridge behavior. 1964 ** 03 0b VGA Enable: Setting this bit enables address decoding 1965 ** and transaction forwarding of the following VGA transactions from the primary bus 1966 ** to the secondary bus: 1967 ** frame buffer memory addresses 000A0000h:000BFFFFh, 1968 ** VGA I/O addresses 3B0:3BBh and 3C0h:3DFh, where AD[31:16]=��0000h?** ?and AD[15:10] are either not decoded (i.e., don't cares), 1969 ** or must be ��000000b�� 1970 ** depending upon the state of the VGA Alias Filter Enable bit. (bit(4) of this register) 1971 ** I/O and Memory Enable bits must be set in the Command register 1972 ** to enable forwarding of VGA cycles. 1973 ** 02 0b ISA Enable: Setting this bit enables special handling 1974 ** for the forwarding of ISA I/O transactions that fall within the address range 1975 ** specified by the I/O Base and Limit registers, 1976 ** and are within the lowest 64Kbyte of the I/O address map 1977 ** (i.e., 0000 0000h - 0000 FFFFh). 1978 ** 0b=All I/O transactions that fall within the I/O Base 1979 ** and Limit registers' specified range are forwarded 1980 ** from primary to secondary unfiltered. 1981 ** 1b=Blocks the forwarding from primary to secondary 1982 ** of the top 768 bytes of each 1Kbyte alias. 1983 ** On the secondary the top 768 bytes of each 1K alias 1984 ** are inversely decoded and forwarded 1985 ** from secondary to primary. 1986 ** 01 0b SERR# Forward Enable: 0b=The bridge does not assert P_SERR# as a result of an S_SERR# assertion. 1987 ** 1b=The bridge asserts P_SERR# whenever S_SERR# is detected 1988 ** asserted provided the SERR# Enable bit is set (PCI Command Register bit(8)=1b). 1989 ** 00 0b Parity Error Response: This bit controls bridge response to a parity error 1990 ** that is detected on its secondary interface. 1991 ** 0b=When a data parity error is detected bridge does not assert S_PERR#. 1992 ** Also bridge does not assert P_SERR# in response to a detected address 1993 ** or attribute parity error. 1994 ** 1b=When a data parity error is detected bridge asserts S_PERR#. 1995 ** The bridge also asserts P_SERR# (when enabled globally via bit(8) 1996 ** of the Command register) 1997 ** in response to a detected address or attribute parity error. 1998 **============================================================================== 1999 */ 2000 #define ARCMSR_PCI2PCI_BRIDGE_CONTROL_REG 0x3E /*word*/ 2001 /* 2002 ************************************************************************** 2003 ** Device Specific Registers 40-A7h 2004 ************************************************************************** 2005 ** ---------------------------------------------------------------------------------------------------------- 2006 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 2007 ** ---------------------------------------------------------------------------------------------------------- 2008 ** | Bridge Control 0 | Arbiter Control/Status | Reserved | 40h 2009 ** ---------------------------------------------------------------------------------------------------------- 2010 ** | Bridge Control 2 | Bridge Control 1 | 44h 2011 ** ---------------------------------------------------------------------------------------------------------- 2012 ** | Reserved | Bridge Status | 48h 2013 ** ---------------------------------------------------------------------------------------------------------- 2014 ** | Reserved | 4Ch 2015 ** ---------------------------------------------------------------------------------------------------------- 2016 ** | Prefetch Policy | Multi-Transaction Timer | 50h 2017 ** ---------------------------------------------------------------------------------------------------------- 2018 ** | Reserved | Pre-boot Status | P_SERR# Assertion Control | 54h 2019 ** ---------------------------------------------------------------------------------------------------------- 2020 ** | Reserved | Reserved | Secondary Decode Enable | 58h 2021 ** ---------------------------------------------------------------------------------------------------------- 2022 ** | Reserved | Secondary IDSEL | 5Ch 2023 ** ---------------------------------------------------------------------------------------------------------- 2024 ** | Reserved | 5Ch 2025 ** ---------------------------------------------------------------------------------------------------------- 2026 ** | Reserved | 68h:CBh 2027 ** ---------------------------------------------------------------------------------------------------------- 2028 ************************************************************************** 2029 **============================================================================== 2030 ** 0x42-0x41: Secondary Arbiter Control/Status Register - SACSR 2031 ** Bit Default Description 2032 ** 15:12 1111b Grant Time-out Violator: This field indicates the agent that violated the Grant Time-out rule 2033 ** (PCI=16 clocks,PCI-X=6 clocks). 2034 ** Note that this field is only meaningful when: 2035 ** # Bit[11] of this register is set to 1b, 2036 ** indicating that a Grant Time-out violation had occurred. 2037 ** # bridge internal arbiter is enabled. 2038 ** Bits[15:12] Violating Agent (REQ#/GNT# pair number) 2039 ** 0000b REQ#/GNT#[0] 2040 ** 0001b REQ#/GNT#[1] 2041 ** 0010b REQ#/GNT#[2] 2042 ** 0011b REQ#/GNT#[3] 2043 ** 1111b Default Value (no violation detected) 2044 ** When bit[11] is cleared by software, this field reverts back to its default value. 2045 ** All other values are Reserved 2046 ** 11 0b Grant Time-out Occurred: When set to 1b, 2047 ** this indicates that a Grant Time-out error had occurred involving one of the secondary bus agents. 2048 ** Software clears this bit by writing a 1b to it. 2049 ** 10 0b Bus Parking Control: 0=During bus idle, bridge parks the bus on the last master to use the bus. 2050 ** 1=During bus idle, bridge parks the bus on itself. 2051 ** The bus grant is removed from the last master and internally asserted to bridge. 2052 ** 09:08 00b Reserved 2053 ** 07:00 0000 0000b Secondary Bus Arbiter Priority Configuration: The bridge secondary arbiter provides two rings of arbitration priority. 2054 ** Each bit of this field assigns its corresponding secondary 2055 ** bus master to either the high priority arbiter ring (1b) 2056 ** or to the low priority arbiter ring (0b). 2057 ** Bits [3:0] correspond to request inputs S_REQ#[3:0], respectively. 2058 ** Bit [6] corresponds to the bridge internal secondary bus request 2059 ** while Bit [7] corresponds to the SATU secondary bus request. 2060 ** Bits [5:4] are unused. 2061 ** 0b=Indicates that the master belongs to the low priority group. 2062 ** 1b=Indicates that the master belongs to the high priority group 2063 **================================================================================= 2064 ** 0x43: Bridge Control Register 0 - BCR0 2065 ** Bit Default Description 2066 ** 07 0b Fully Dynamic Queue Mode: 0=The number of Posted write transactions is limited to eight 2067 ** and the Posted Write data is limited to 4KB. 2068 ** 1=Operation in fully dynamic queue mode. The bridge enqueues up to 2069 ** 14 Posted Memory Write transactions and 8KB of posted write data. 2070 ** 06:03 0H Reserved. 2071 ** 02 0b Upstream Prefetch Disable: This bit disables bridge ability 2072 ** to perform upstream prefetch operations for Memory 2073 ** Read requests received on its secondary interface. 2074 ** This bit also controls the bridge's ability to generate advanced read commands 2075 ** when forwarding a Memory Read Block transaction request upstream from a PCI-X bus 2076 ** to a Conventional PCI bus. 2077 ** 0b=bridge treats all upstream Memory Read requests as though they target prefetchable memory. 2078 ** The use of Memory Read Line and Memory Read 2079 ** Multiple is enabled when forwarding a PCI-X Memory Read Block request 2080 ** to an upstream bus operating in Conventional PCI mode. 2081 ** 1b=bridge treats upstream PCI Memory Read requests as though 2082 ** they target non-prefetchable memory and forwards upstream PCI-X Memory 2083 ** Read Block commands as Memory Read 2084 ** when the primary bus is operating 2085 ** in Conventional PCI mode. 2086 ** NOTE: This bit does not affect bridge ability to perform read prefetching 2087 ** when the received command is Memory Read Line or Memory Read Multiple. 2088 **================================================================================= 2089 ** 0x45-0x44: Bridge Control Register 1 - BCR1 (Sheet 2 of 2) 2090 ** Bit Default Description 2091 ** 15:08 0000000b Reserved 2092 ** 07:06 00b Alias Command Mapping: This two bit field determines how bridge handles PCI-X ��Alias�� commands, 2093 ** specifically the Alias to Memory Read Block and Alias to Memory Write Block commands. 2094 ** The three options for handling these alias commands are to either pass it as is, 2095 ** re-map to the actual block memory read/write command encoding, or ignore 2096 ** the transaction forcing a Master Abort to occur on the Origination Bus. 2097 ** Bit (7:6) Handling of command 2098 ** 0 0 Re-map to Memory Read/Write Block before forwarding 2099 ** 0 1 Enqueue and forward the alias command code unaltered 2100 ** 1 0 Ignore the transaction, forcing Master Abort 2101 ** 1 1 Reserved 2102 ** 05 1b Watchdog Timers Disable: Disables or enables all 2 24 Watchdog Timers in both directions. 2103 ** The watchdog timers are used to detect prohibitively long latencies in the system. 2104 ** The watchdog timer expires when any Posted Memory Write (PMW), Delayed Request, 2105 ** or Split Requests (PCI-X mode) is not completed within 2 24 events 2106 ** (��events�� are defined as PCI Clocks when operating in PCI-X mode, 2107 ** and as the number of times being retried when operating in Conventional PCI mode) 2108 ** 0b=All 2 24 watchdog timers are enabled. 2109 ** 1b=All 2 24 watchdog timers are disabled and there is no limits to 2110 ** the number of attempts bridge makes when initiating a PMW, 2111 ** transacting a Delayed Transaction, or how long it waits for 2112 ** a split completion corresponding to one of its requests. 2113 ** 04 0b GRANT# time-out disable: This bit enables/disables the GNT# time-out mechanism. 2114 ** Grant time-out is 16 clocks for conventional PCI, and 6 clocks for PCI-X. 2115 ** 0b=The Secondary bus arbiter times out an agent 2116 ** that does not assert FRAME# within 16/6 clocks of receiving its grant, 2117 ** once the bus has gone idle. 2118 ** The time-out counter begins as soon as the bus goes idle with the new GNT# asserted. 2119 ** An infringing agent does not receive a subsequent GNT# 2120 ** until it de-asserts its REQ# for at least one clock cycle. 2121 ** 1b=GNT# time-out mechanism is disabled. 2122 ** 03 00b Reserved. 2123 ** 02 0b Secondary Discard Timer Disable: This bit enables/disables bridge secondary delayed transaction discard mechanism. 2124 ** The time out mechanism is used to ensure that initiators 2125 ** of delayed transactions return for their delayed completion data/status 2126 ** within a reasonable amount of time after it is available from bridge. 2127 ** 0b=The secondary master time-out counter is enabled 2128 ** and uses the value specified by the Secondary Discard Timer bit 2129 ** (see Bridge Control Register). 2130 ** 1b=The secondary master time-out counter is disabled. 2131 ** The bridge waits indefinitely for a secondary bus master 2132 ** to repeat a delayed transaction. 2133 ** 01 0b Primary Discard Timer Disable: This bit enables/disables bridge primary delayed transaction discard mechanism. 2134 ** The time out mechanism is used to ensure that initiators 2135 ** of delayed transactions return for their delayed completion data/status 2136 ** within a reasonable amount of time after it is available from bridge. 2137 ** 0b=The primary master time-out counter is enabled and uses the value specified 2138 ** by the Primary Discard Timer bit (see Bridge Control Register). 2139 ** 1b=The secondary master time-out counter is disabled. 2140 ** The bridge waits indefinitely for a secondary bus master 2141 ** to repeat a delayed transaction. 2142 ** 00 0b Reserved 2143 **================================================================================= 2144 ** 0x47-0x46: Bridge Control Register 2 - BCR2 2145 ** Bit Default Description 2146 ** 15:07 0000b Reserved. 2147 ** 06 0b Global Clock Out Disable (External Secondary Bus Clock Source Enable): 2148 ** This bit disables all of the secondary PCI clock outputs including 2149 ** the feedback clock S_CLKOUT. 2150 ** This means that the user is required to provide an S_CLKIN input source. 2151 ** 05:04 11 (66 MHz) Preserved. 2152 ** 01 (100 MHz) 2153 ** 00 (133 MHz) 2154 ** 03:00 Fh (100 MHz & 66 MHz) 2155 ** 7h (133 MHz) 2156 ** This 4 bit field provides individual enable/disable mask bits for each of bridge 2157 ** secondary PCI clock outputs. Some, or all secondary clock outputs (S_CLKO[3:0]) 2158 ** default to being enabled following the rising edge of P_RST#, depending on the 2159 ** frequency of the secondary bus clock: 2160 ** �E Designs with 100 MHz (or lower) Secondary PCI clock power up with 2161 ** all four S_CLKOs enabled by default. (SCLKO[3:0])�P 2162 ** �E Designs with 133 MHz Secondary PCI clock power up 2163 ** with the lower order 3 S_CLKOs enabled by default. 2164 ** (S_CLKO[2:0]) Only those SCLKs that power up enabled by can be connected 2165 ** to downstream device clock inputs. 2166 **================================================================================= 2167 ** 0x49-0x48: Bridge Status Register - BSR 2168 ** Bit Default Description 2169 ** 15 0b Upstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR# 2170 ** is conditionally asserted when the secondary discard timer expires. 2171 ** 14 0b Upstream Delayed/Split Read Watchdog Timer Expired: 2172 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# 2173 ** is conditionally asserted when bridge discards an upstream delayed read ** ** transaction request after 2 24 retries following the initial retry. 2174 ** PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 2175 ** when bridge discards an upstream split read request 2176 ** after waiting in excess of 2 24 clocks for the corresponding 2177 ** Split Completion to arrive. 2178 ** 13 0b Upstream Delayed/Split Write Watchdog Timer Expired: 2179 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# 2180 ** is conditionally asserted when bridge discards an upstream delayed write ** ** transaction request after 2 24 retries following the initial retry. 2181 ** PCI-X Mode: This bit is set to a 1b and P_SERR# 2182 ** is conditionally asserted when bridge discards an upstream split write request ** after waiting in excess of 2 24 clocks for the corresponding 2183 ** Split Completion to arrive. 2184 ** 12 0b Master Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR# 2185 ** is conditionally asserted when a Master Abort occurs as a result of an attempt, 2186 ** by bridge, to retire a PMW upstream. 2187 ** 11 0b Target Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR# 2188 ** is conditionally asserted when a Target Abort occurs as a result of an attempt, 2189 ** by bridge, to retire a PMW upstream. 2190 ** 10 0b Upstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR# 2191 ** is conditionally asserted when bridge discards an upstream PMW transaction 2192 ** after receiving 2 24 target retries from the primary bus target 2193 ** 09 0b Upstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR# 2194 ** is conditionally asserted when a data parity error is detected by bridge 2195 ** while attempting to retire a PMW upstream 2196 ** 08 0b Secondary Bus Address Parity Error: This bit is set to a 1b and P_SERR# 2197 ** is conditionally asserted when bridge detects an address parity error on 2198 ** the secondary bus. 2199 ** 07 0b Downstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR# 2200 ** is conditionally asserted when the primary bus discard timer expires. 2201 ** 06 0b Downstream Delayed/Split Read Watchdog Timer Expired: 2202 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# 2203 ** is conditionally asserted when bridge discards a downstream delayed read ** ** transaction request after receiving 2 24 target retries 2204 ** from the secondary bus target. 2205 ** PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 2206 ** when bridge discards a downstream split read request 2207 ** after waiting in excess of 2 24 clocks for the corresponding 2208 ** Split Completion to arrive. 2209 ** 05 0b Downstream Delayed Write/Split Watchdog Timer Expired: 2210 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 2211 ** when bridge discards a downstream delayed write transaction request 2212 ** after receiving 2 24 target retries from the secondary bus target. 2213 ** PCI-X Mode: This bit is set to a 1b and P_SERR# 2214 ** is conditionally asserted when bridge discards a downstream 2215 ** split write request after waiting in excess of 2 24 clocks 2216 ** for the corresponding Split Completion to arrive. 2217 ** 04 0b Master Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR# 2218 ** is conditionally asserted when a Master Abort occurs as a result of an attempt, 2219 ** by bridge, to retire a PMW downstream. 2220 ** 03 0b Target Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR# is conditionally asserted 2221 ** when a Target Abort occurs as a result of an attempt, by bridge, 2222 ** to retire a PMW downstream. 2223 ** 02 0b Downstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR# 2224 ** is conditionally asserted when bridge discards a downstream PMW transaction 2225 ** after receiving 2 24 target retries from the secondary bus target 2226 ** 01 0b Downstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR# 2227 ** is conditionally asserted when a data parity error is detected by bridge 2228 ** while attempting to retire a PMW downstream. 2229 ** 00 0b Primary Bus Address Parity Error: This bit is set to a 1b and P_SERR# is conditionally asserted 2230 ** when bridge detects an address parity error on the primary bus. 2231 **================================================================================== 2232 ** 0x51-0x50: Bridge Multi-Transaction Timer Register - BMTTR 2233 ** Bit Default Description 2234 ** 15:13 000b Reserved 2235 ** 12:10 000b GRANT# Duration: This field specifies the count (PCI clocks) 2236 ** that a secondary bus master has its grant maintained in order to enable 2237 ** multiple transactions to execute within the same arbitration cycle. 2238 ** Bit[02:00] GNT# Extended Duration 2239 ** 000 MTT Disabled (Default=no GNT# extension) 2240 ** 001 16 clocks 2241 ** 010 32 clocks 2242 ** 011 64 clocks 2243 ** 100 128 clocks 2244 ** 101 256 clocks 2245 ** 110 Invalid (treated as 000) 2246 ** 111 Invalid (treated as 000) 2247 ** 09:08 00b Reserved 2248 ** 07:00 FFh MTT Mask: This field enables/disables MTT usage for each REQ#/GNT# 2249 ** pair supported by bridge secondary arbiter. 2250 ** Bit(7) corresponds to SATU internal REQ#/GNT# pair, 2251 ** bit(6) corresponds to bridge internal REQ#/GNT# pair, 2252 ** bit(5) corresponds to REQ#/GNT#(5) pair, etc. 2253 ** When a given bit is set to 1b, its corresponding REQ#/GNT# 2254 ** pair is enabled for MTT functionality as determined by bits(12:10) of this register. 2255 ** When a given bit is cleared to 0b, its corresponding REQ#/GNT# pair is disabled from using the MTT. 2256 **================================================================================== 2257 ** 0x53-0x52: Read Prefetch Policy Register - RPPR 2258 ** Bit Default Description 2259 ** 15:13 000b ReRead_Primary Bus: 3-bit field indicating the multiplication factor 2260 ** to be used in calculating the number of bytes to prefetch from the secondary bus interface on ** subsequent PreFetch operations given that the read demands were not satisfied 2261 ** using the FirstRead parameter. 2262 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs 2263 ** Memory Read Line 1 cache lines Memory Read Multiple 2 cache lines 2264 ** 12:10 000b FirstRead_Primary Bus: 3-bit field indicating the multiplication factor to be used in calculating 2265 ** the number of bytes to prefetch from the secondary bus interface 2266 ** on the initial PreFetch operation. 2267 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs 2268 ** Memory Read Line 1 cache line Memory Read Multiple 2 cache lines 2269 ** 09:07 010b ReRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used 2270 ** in calculating the number of bytes to prefetch from the primary 2271 ** bus interface on subsequent PreFetch operations given 2272 ** that the read demands were not satisfied using 2273 ** the FirstRead parameter. 2274 ** The default value of 010b correlates to: Command Type Hardwired pre-fetch a 2275 ** mount Memory Read 3 cache lines Memory Read Line 3 cache lines 2276 ** Memory Read Multiple 6 cache lines 2277 ** 06:04 000b FirstRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used 2278 ** in calculating the number of bytes to prefetch from 2279 ** the primary bus interface on the initial PreFetch operation. 2280 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount 2281 ** Memory Read 4 DWORDs Memory Read Line 1 cache line Memory Read Multiple 2 cache lines 2282 ** 03:00 1111b Staged Prefetch Enable: This field enables/disables the FirstRead/ReRead pre-fetch 2283 ** algorithm for the secondary and the primary bus interfaces. 2284 ** Bit(3) is a ganged enable bit for REQ#/GNT#[7:3], and bits(2:0) provide individual 2285 ** enable bits for REQ#/GNT#[2:0]. 2286 ** (bit(2) is the enable bit for REQ#/GNT#[2], etc...) 2287 ** 1b: enables the staged pre-fetch feature 2288 ** 0b: disables staged pre-fetch, 2289 ** and hardwires read pre-fetch policy to the following for 2290 ** Memory Read, 2291 ** Memory Read Line, 2292 ** and Memory Read Multiple commands: 2293 ** Command Type Hardwired Pre-Fetch Amount... 2294 ** Memory Read 4 DWORDs 2295 ** Memory Read Line 1 cache line 2296 ** Memory Read Multiple 2 cache lines 2297 ** NOTE: When the starting address is not cache line aligned, bridge pre-fetches Memory Read line commands 2298 ** only to the next higher cache line boundary.For non-cache line aligned Memory Read 2299 ** Multiple commands bridge pre-fetches only to the second cache line boundary encountered. 2300 **================================================================================== 2301 ** 0x55-0x54: P_SERR# Assertion Control - SERR_CTL 2302 ** Bit Default Description 2303 ** 15 0b Upstream Delayed Transaction Discard Timer Expired: Dictates the bridge behavior 2304 ** in response to its discarding of a delayed transaction that was initiated from the primary bus. 2305 ** 0b=bridge asserts P_SERR#. 2306 ** 1b=bridge does not assert P_SERR# 2307 ** 14 0b Upstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 2308 ** 0b=bridge asserts P_SERR#. 2309 ** 1b=bridge does not assert P_SERR# 2310 ** 13 0b Upstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 2311 ** 0b=bridge asserts P_SERR#. 2312 ** 1b=bridge does not assert P_SERR# 2313 ** 12 0b Master Abort during Upstream Posted Write: Dictates bridge behavior following 2314 ** its having detected a Master Abort while attempting to retire one of its PMWs upstream. 2315 ** 0b=bridge asserts P_SERR#. 2316 ** 1b=bridge does not assert P_SERR# 2317 ** 11 0b Target Abort during Upstream Posted Write: Dictates bridge behavior following 2318 ** its having been terminated with Target Abort while attempting to retire one of its PMWs upstream. 2319 ** 0b=bridge asserts P_SERR#. 2320 ** 1b=bridge does not assert P_SERR# 2321 ** 10 0b Upstream Posted Write Data Discarded: Dictates bridge behavior in the event that 2322 ** it discards an upstream posted write transaction. 2323 ** 0b=bridge asserts P_SERR#. 2324 ** 1b=bridge does not assert P_SERR# 2325 ** 09 0b Upstream Posted Write Data Parity Error: Dictates bridge behavior 2326 ** when a data parity error is detected while attempting to retire on of its PMWs upstream. 2327 ** 0b=bridge asserts P_SERR#. 2328 ** 1b=bridge does not assert P_SERR# 2329 ** 08 0b Secondary Bus Address Parity Error: This bit dictates bridge behavior 2330 ** when it detects an address parity error on the secondary bus. 2331 ** 0b=bridge asserts P_SERR#. 2332 ** 1b=bridge does not assert P_SERR# 2333 ** 07 0b Downstream Delayed Transaction Discard Timer Expired: Dictates bridge behavior in response to 2334 ** its discarding of a delayed transaction that was initiated on the secondary bus. 2335 ** 0b=bridge asserts P_SERR#. 2336 ** 1b=bridge does not assert P_SERR# 2337 ** 06 0b Downstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 2338 ** 0b=bridge asserts P_SERR#. 2339 ** 1b=bridge does not assert P_SERR# 2340 ** 05 0b Downstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 2341 ** 0b=bridge asserts P_SERR#. 2342 ** 1b=bridge does not assert P_SERR# 2343 ** 04 0b Master Abort during Downstream Posted Write: Dictates bridge behavior following 2344 ** its having detected a Master Abort while attempting to retire one of its PMWs downstream. 2345 ** 0b=bridge asserts P_SERR#. 2346 ** 1b=bridge does not assert P_SERR# 2347 ** 03 0b Target Abort during Downstream Posted Write: Dictates bridge behavior following 2348 ** its having been terminated with Target Abort while attempting to retire one of its PMWs downstream. 2349 ** 0b=bridge asserts P_SERR#. 2350 ** 1b=bridge does not assert P_SERR# 2351 ** 02 0b Downstream Posted Write Data Discarded: Dictates bridge behavior in the event 2352 ** that it discards a downstream posted write transaction. 2353 ** 0b=bridge asserts P_SERR#. 2354 ** 1b=bridge does not assert P_SERR# 2355 ** 01 0b Downstream Posted Write Data Parity Error: Dictates bridge behavior 2356 ** when a data parity error is detected while attempting to retire on of its PMWs downstream. 2357 ** 0b=bridge asserts P_SERR#. 2358 ** 1b=bridge does not assert P_SERR# 2359 ** 00 0b Primary Bus Address Parity Error: This bit dictates bridge behavior 2360 ** when it detects an address parity error on the primary bus. 2361 ** 0b=bridge asserts P_SERR#. 2362 ** 1b=bridge does not assert P_SERR# 2363 **=============================================================================== 2364 ** 0x56: Pre-Boot Status Register - PBSR 2365 ** Bit Default Description 2366 ** 07 1 Reserved 2367 ** 06 - Reserved - value indeterminate 2368 ** 05:02 0 Reserved 2369 ** 01 Varies with External State of S_133EN at PCI Bus Reset Secondary Bus Max Frequency Setting: 2370 ** This bit reflect captured S_133EN strap, 2371 ** indicating the maximum secondary bus clock frequency when in PCI-X mode. 2372 ** Max Allowable Secondary Bus Frequency 2373 ** ** S_133EN PCI-X Mode 2374 ** ** 0 100 MHz 2375 ** ** 1 133 MH 2376 ** 00 0b Reserved 2377 **=============================================================================== 2378 ** 0x59-0x58: Secondary Decode Enable Register - SDER 2379 ** Bit Default Description 2380 ** 15:03 FFF1h Preserved. 2381 ** 02 Varies with External State of PRIVMEM at PCI Bus Reset Private Memory Space Enable - when set, 2382 ** bridge overrides its secondary inverse decode logic and not 2383 ** forward upstream any secondary bus initiated DAC Memory transactions with AD(63)=1b. 2384 ** This creates a private memory space on the Secondary PCI bus 2385 ** that allows peer-to-peer transactions. 2386 ** 01:00 10 2 Preserved. 2387 **=============================================================================== 2388 ** 0x5D-0x5C: Secondary IDSEL Select Register - SISR 2389 ** Bit Default Description 2390 ** 15:10 000000 2 Reserved. 2391 ** 09 Varies with External State of PRIVDEV at PCI Bus Reset AD25- IDSEL Disable - When this bit is set, 2392 ** AD25 is deasserted for any possible Type 1 to Type 0 conversion. 2393 ** When this bit is clear, 2394 ** AD25 is asserted when Primary addresses AD[15:11]=01001 2 during a Type 1 to Type 0 conversion. 2395 ** 08 Varies with External State of PRIVDEV at PCI Bus Reset AD24- IDSEL Disable - When this bit is set, 2396 ** AD24 is deasserted for any possible Type 1 to Type 0 conversion. 2397 ** When this bit is clear, 2398 ** AD24 is asserted when Primary addresses AD[15:11]=01000 2 during a Type 1 to Type 0 conversion. 2399 ** 07 Varies with External State of PRIVDEV at PCI Bus Reset AD23- IDSEL Disable - When this bit is set, 2400 ** AD23 is deasserted for any possible Type 1 to Type 0 conversion. 2401 ** When this bit is clear, 2402 ** AD23 is asserted when Primary addresses AD[15:11]=00111 2 during a Type 1 to Type 0 conversion. 2403 ** 06 Varies with External State of PRIVDEV at PCI Bus Reset AD22- IDSEL Disable - When this bit is set, 2404 ** AD22 is deasserted for any possible Type 1 to Type 0 conversion. 2405 ** When this bit is clear, 2406 ** AD22 is asserted when Primary addresses AD[15:11]=00110 2 during a Type 1 to Type 0 conversion. 2407 ** 05 Varies with External State of PRIVDEV at PCI Bus Reset AD21- IDSEL Disable - When this bit is set, 2408 ** AD21 is deasserted for any possible Type 1 to Type 0 conversion. 2409 ** When this bit is clear, 2410 ** AD21 is asserted when Primary addresses AD[15:11]=00101 2 during a Type 1 to Type 0 conversion. 2411 ** 04 Varies with External State of PRIVDEV at PCI Bus Reset AD20- IDSEL Disable - When this bit is set, 2412 ** AD20 is deasserted for any possible Type 1 to Type 0 conversion. 2413 ** When this bit is clear, 2414 ** AD20 is asserted when Primary addresses AD[15:11]=00100 2 during a Type 1 to Type 0 conversion. 2415 ** 03 Varies with External State of PRIVDEV at PCI Bus Reset AD19- IDSEL Disable - When this bit is set, 2416 ** AD19 is deasserted for any possible Type 1 to Type 0 conversion. 2417 ** When this bit is clear, 2418 ** AD19 is asserted when Primary addresses AD[15:11]=00011 2 during a Type 1 to Type 0 conversion. 2419 ** 02 Varies with External State of PRIVDEV at PCI Bus Reset AD18- IDSEL Disable - When this bit is set, 2420 ** AD18 is deasserted for any possible Type 1 to Type 0 conversion. 2421 ** When this bit is clear, 2422 ** AD18 is asserted when Primary addresses AD[15:11]=00010 2 during a Type 1 to Type 0 conversion. 2423 ** 01 Varies with External State of PRIVDEV at PCI Bus Reset AD17- IDSEL Disable - When this bit is set, 2424 ** AD17 is deasserted for any possible Type 1 to Type 0 conversion. 2425 ** When this bit is clear, 2426 ** AD17 is asserted when Primary addresses AD[15:11]=00001 2 during a Type 1 to Type 0 conversion. 2427 ** 00 Varies with External State of PRIVDEV at PCI Bus Reset AD16- IDSEL Disable - When this bit is set, 2428 ** AD16 is deasserted for any possible Type 1 to Type 0 conversion. 2429 ** When this bit is clear, 2430 ** AD16 is asserted when Primary addresses AD[15:11]=00000 2 during a Type 1 to Type 0 conversion. 2431 ************************************************************************** 2432 */ 2433 /* 2434 ************************************************************************** 2435 ** Reserved A8-CBh 2436 ************************************************************************** 2437 */ 2438 /* 2439 ************************************************************************** 2440 ** PCI Extended Enhanced Capabilities List CC-FFh 2441 ************************************************************************** 2442 ** ---------------------------------------------------------------------------------------------------------- 2443 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 2444 ** ---------------------------------------------------------------------------------------------------------- 2445 ** | Power Management Capabilities | Next Item Ptr | Capability ID | DCh 2446 ** ---------------------------------------------------------------------------------------------------------- 2447 ** | PM Data | PPB Support | Extensions Power Management CSR | E0h 2448 ** ---------------------------------------------------------------------------------------------------------- 2449 ** | Reserved | Reserved | Reserved | E4h 2450 ** ---------------------------------------------------------------------------------------------------------- 2451 ** | Reserved | E8h 2452 ** ---------------------------------------------------------------------------------------------------------- 2453 ** | Reserved | Reserved | Reserved | Reserved | ECh 2454 ** ---------------------------------------------------------------------------------------------------------- 2455 ** | PCI-X Secondary Status | Next Item Ptr | Capability ID | F0h 2456 ** ---------------------------------------------------------------------------------------------------------- 2457 ** | PCI-X Bridge Status | F4h 2458 ** ---------------------------------------------------------------------------------------------------------- 2459 ** | PCI-X Upstream Split Transaction Control | F8h 2460 ** ---------------------------------------------------------------------------------------------------------- 2461 ** | PCI-X Downstream Split Transaction Control | FCh 2462 ** ---------------------------------------------------------------------------------------------------------- 2463 **=============================================================================== 2464 ** 0xDC: Power Management Capabilities Identifier - PM_CAPID 2465 ** Bit Default Description 2466 ** 07:00 01h Identifier (ID): PCI SIG assigned ID for PCI-PM register block 2467 **=============================================================================== 2468 ** 0xDD: Next Item Pointer - PM_NXTP 2469 ** Bit Default Description 2470 ** 07:00 F0H Next Capabilities Pointer (PTR): The register defaults to F0H pointing to the PCI-X Extended Capability Header. 2471 **=============================================================================== 2472 ** 0xDF-0xDE: Power Management Capabilities Register - PMCR 2473 ** Bit Default Description 2474 ** 15:11 00h PME Supported (PME): PME# cannot be asserted by bridge. 2475 ** 10 0h State D2 Supported (D2): Indicates no support for state D2. No power management action in this state. 2476 ** 09 1h State D1 Supported (D1): Indicates support for state D1. No power management action in this state. 2477 ** 08:06 0h Auxiliary Current (AUXC): This 3 bit field reports the 3.3Vaux auxiliary current requirements for the PCI function. 2478 ** This returns 000b as PME# wake-up for bridge is not implemented. 2479 ** 05 0 Special Initialization Required (SINT): Special initialization is not required for bridge. 2480 ** 04:03 00 Reserved 2481 ** 02:00 010 Version (VS): Indicates that this supports PCI Bus Power Management Interface Specification, Revision 1.1. 2482 **=============================================================================== 2483 ** 0xE1-0xE0: Power Management Control / Status - Register - PMCSR 2484 ** Bit Default Description 2485 ** 15:09 00h Reserved 2486 ** 08 0b PME_Enable: This bit, when set to 1b enables bridge to assert PME#. 2487 ** Note that bridge never has occasion to assert PME# and implements this dummy R/W bit only for the purpose of working around an OS PCI-PM bug. 2488 ** 07:02 00h Reserved 2489 ** 01:00 00 Power State (PSTATE): This 2-bit field is used both to determine the current power state of 2490 ** a function and to set the Function into a new power state. 2491 ** 00 - D0 state 2492 ** 01 - D1 state 2493 ** 10 - D2 state 2494 ** 11 - D3 hot state 2495 **=============================================================================== 2496 ** 0xE2: Power Management Control / Status PCI to PCI Bridge Support - PMCSR_BSE 2497 ** Bit Default Description 2498 ** 07 0 Bus Power/Clock Control Enable (BPCC_En): Indicates that the bus power/clock control policies have been disabled. 2499 ** 06 0 B2/B3 support for D3 Hot (B2_B3#): The state of this bit determines the action that 2500 ** is to occur as a direct result of programming the function to D3 hot. 2501 ** This bit is only meaningful when bit 7 (BPCC_En) is a ��1��. 2502 ** 05:00 00h Reserved 2503 **=============================================================================== 2504 ** 0xE3: Power Management Data Register - PMDR 2505 ** Bit Default Description 2506 ** 07:00 00h Reserved 2507 **=============================================================================== 2508 ** 0xF0: PCI-X Capabilities Identifier - PX_CAPID 2509 ** Bit Default Description 2510 ** 07:00 07h Identifier (ID): Indicates this is a PCI-X capabilities list. 2511 **=============================================================================== 2512 ** 0xF1: Next Item Pointer - PX_NXTP 2513 ** Bit Default Description 2514 ** 07:00 00h Next Item Pointer: Points to the next capability in the linked list The power on default value of this 2515 ** register is 00h indicating that this is the last entry in the linked list of capabilities. 2516 **=============================================================================== 2517 ** 0xF3-0xF2: PCI-X Secondary Status - PX_SSTS 2518 ** Bit Default Description 2519 ** 15:09 00h Reserved 2520 ** 08:06 Xxx Secondary Clock Frequency (SCF): This field is set with the frequency of the secondary bus. 2521 ** The values are: 2522 ** ** BitsMax FrequencyClock Period 2523 ** ** 000PCI ModeN/A 2524 ** ** 00166 15 2525 ** ** 01010010 2526 ** ** 0111337.5 2527 ** ** 1xxreservedreserved 2528 ** ** The default value for this register is the operating frequency of the secondary bus 2529 ** 05 0b Split Request Delayed. (SRD): This bit is supposed to be set by a bridge when it cannot forward a transaction on the 2530 ** secondary bus to the primary bus because there is not enough room within the limit 2531 ** specified in the Split Transaction Commitment Limit field in the Downstream Split 2532 ** Transaction Control register. The bridge does not set this bit. 2533 ** 04 0b Split Completion Overrun (SCO): This bit is supposed to be set when a bridge terminates a Split Completion on the ** ** secondary bus with retry or Disconnect at next ADB because its buffers are full. 2534 ** The bridge does not set this bit. 2535 ** 03 0b Unexpected Split Completion (USC): This bit is set when an unexpected split completion with a requester ID 2536 ** equal to bridge secondary bus number, device number 00h, 2537 ** and function number 0 is received on the secondary interface. 2538 ** This bit is cleared by software writing a '1'. 2539 ** 02 0b Split Completion Discarded (SCD): This bit is set 2540 ** when bridge discards a split completion moving toward the secondary bus 2541 ** because the requester would not accept it. This bit cleared by software writing a '1'. 2542 ** 01 1b 133 MHz Capable: Indicates that bridge is capable of running its secondary bus at 133 MHz 2543 ** 00 1b 64-bit Device (D64): Indicates the width of the secondary bus as 64-bits. 2544 **=============================================================================== 2545 ** 0xF7-0xF6-0xf5-0xF4: PCI-X Bridge Status - PX_BSTS 2546 ** Bit Default Description 2547 ** 31:22 0 Reserved 2548 ** 21 0 Split Request Delayed (SRD): This bit does not be set by bridge. 2549 ** 20 0 Split Completion Overrun (SCO): This bit does not be set by bridge 2550 ** because bridge throttles traffic on the completion side. 2551 ** 19 0 Unexpected Split Completion (USC): The bridge sets this bit to 1b 2552 ** when it encounters a corrupted Split Completion, possibly with an ** ** inconsistent remaining byte count.Software clears 2553 ** this bit by writing a 1b to it. 2554 ** 18 0 Split Completion Discarded (SCD): The bridge sets this bit to 1b 2555 ** when it has discarded a Split Completion.Software clears this bit by ** ** writing a 1b to it. 2556 ** 17 1 133 MHz Capable: This bit indicates that the bridge primary interface is ** capable of 133 MHz operation in PCI-X mode. 2557 ** 0=The maximum operating frequency is 66 MHz. 2558 ** 1=The maximum operating frequency is 133 MHz. 2559 ** 16 Varies with the external state of P_32BITPCI# at PCI Bus Reset 64-bit Device (D64): Indicates bus width of the Primary PCI bus interface. 2560 ** 0=Primary Interface is connected as a 32-bit PCI bus. 2561 ** 1=Primary Interface is connected as a 64-bit PCI bus. 2562 ** 15:08 00h Bus Number (BNUM): This field is simply an alias to the PBN field 2563 ** of the BNUM register at offset 18h. 2564 ** Apparently it was deemed necessary reflect it here for diagnostic purposes. 2565 ** 07:03 1fh Device Number (DNUM): Indicates which IDSEL bridge consumes. 2566 ** May be updated whenever a PCI-X 2567 ** configuration write cycle that targets bridge scores a hit. 2568 ** 02:00 0h Function Number (FNUM): The bridge Function # 2569 **=============================================================================== 2570 ** 0xFB-0xFA-0xF9-0xF8: PCI-X Upstream Split Transaction Control - PX_USTC 2571 ** Bit Default Description 2572 ** 31:16 003Eh Split Transaction Limit (STL): This register indicates the size of the commitment limit in units of ADQs. 2573 ** Software is permitted to program this register to any value greater than or equal to 2574 ** the contents of the Split Transaction Capacity register. A value less than the contents 2575 ** of the Split Transaction Capacity register causes unspecified results. 2576 ** A value of 003Eh or greater enables the bridge to forward all Split Requests of any 2577 ** size regardless of the amount of buffer space available. 2578 ** 15:00 003Eh Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing 2579 ** split completions. This register controls behavior of the bridge buffers for forwarding 2580 ** Split Transactions from a primary bus requester to a secondary bus completer. 2581 ** The default value of 003Eh indicates there is available buffer space for 62 ADQs (7936 bytes). 2582 **=============================================================================== 2583 ** 0xFF-0xFE-0xFD-0xFC: PCI-X Downstream Split Transaction Control - PX_DSTC 2584 ** Bit Default Description 2585 ** 31:16 003Eh Split Transaction Limit (STL): This register indicates the size of the commitment limit in units of ADQs. 2586 ** Software is permitted to program this register to any value greater than or equal to 2587 ** the contents of the Split Transaction Capacity register. A value less than the contents 2588 ** of the Split Transaction Capacity register causes unspecified results. 2589 ** A value of 003Eh or greater enables the bridge to forward all Split Requests of any 2590 ** size regardless of the amount of buffer space available. 2591 ** 15:00 003Eh Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing 2592 ** split completions. This register controls behavior of the bridge buffers for forwarding 2593 ** Split Transactions from a primary bus requester to a secondary bus completer. 2594 ** The default value of 003Eh indicates there is available buffer space for 62 ADQs 2595 ** (7936 bytes). 2596 ************************************************************************** 2597 */ 2598 2599 /* 2600 ************************************************************************************************************************************* 2601 ** 80331 Address Translation Unit Register Definitions 2602 ** ATU Interface Configuration Header Format 2603 ** The ATU is programmed via a [Type 0] configuration command on the PCI interface. 2604 ************************************************************************************************************************************* 2605 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configuration Byte Offset 2606 **=================================================================================================================================== 2607 ** | ATU Device ID | Vendor ID | 00h 2608 ** ---------------------------------------------------------------------------------------------------------- 2609 ** | Status | Command | 04H 2610 ** ---------------------------------------------------------------------------------------------------------- 2611 ** | ATU Class Code | Revision ID | 08H 2612 ** ---------------------------------------------------------------------------------------------------------- 2613 ** | ATUBISTR | Header Type | Latency Timer | Cacheline Size | 0CH 2614 ** ---------------------------------------------------------------------------------------------------------- 2615 ** | Inbound ATU Base Address 0 | 10H 2616 ** ---------------------------------------------------------------------------------------------------------- 2617 ** | Inbound ATU Upper Base Address 0 | 14H 2618 ** ---------------------------------------------------------------------------------------------------------- 2619 ** | Inbound ATU Base Address 1 | 18H 2620 ** ---------------------------------------------------------------------------------------------------------- 2621 ** | Inbound ATU Upper Base Address 1 | 1CH 2622 ** ---------------------------------------------------------------------------------------------------------- 2623 ** | Inbound ATU Base Address 2 | 20H 2624 ** ---------------------------------------------------------------------------------------------------------- 2625 ** | Inbound ATU Upper Base Address 2 | 24H 2626 ** ---------------------------------------------------------------------------------------------------------- 2627 ** | Reserved | 28H 2628 ** ---------------------------------------------------------------------------------------------------------- 2629 ** | ATU Subsystem ID | ATU Subsystem Vendor ID | 2CH 2630 ** ---------------------------------------------------------------------------------------------------------- 2631 ** | Expansion ROM Base Address | 30H 2632 ** ---------------------------------------------------------------------------------------------------------- 2633 ** | Reserved Capabilities Pointer | 34H 2634 ** ---------------------------------------------------------------------------------------------------------- 2635 ** | Reserved | 38H 2636 ** ---------------------------------------------------------------------------------------------------------- 2637 ** | Maximum Latency | Minimum Grant | Interrupt Pin | Interrupt Line | 3CH 2638 ** ---------------------------------------------------------------------------------------------------------- 2639 ********************************************************************************************************************* 2640 */ 2641 /* 2642 *********************************************************************************** 2643 ** ATU Vendor ID Register - ATUVID 2644 ** ----------------------------------------------------------------- 2645 ** Bit Default Description 2646 ** 15:00 8086H (0x17D3) ATU Vendor ID - This is a 16-bit value assigned to Intel. 2647 ** This register, combined with the DID, uniquely identify the PCI device. 2648 ** Access type is Read/Write to allow the 80331 to configure the register as a different vendor ID 2649 ** to simulate the interface of a standard mechanism currently used by existing application software. 2650 *********************************************************************************** 2651 */ 2652 #define ARCMSR_ATU_VENDOR_ID_REG 0x00 /*word*/ 2653 /* 2654 *********************************************************************************** 2655 ** ATU Device ID Register - ATUDID 2656 ** ----------------------------------------------------------------- 2657 ** Bit Default Description 2658 ** 15:00 0336H (0x1110) ATU Device ID - This is a 16-bit value assigned to the ATU. 2659 ** This ID, combined with the VID, uniquely identify any PCI device. 2660 *********************************************************************************** 2661 */ 2662 #define ARCMSR_ATU_DEVICE_ID_REG 0x02 /*word*/ 2663 /* 2664 *********************************************************************************** 2665 ** ATU Command Register - ATUCMD 2666 ** ----------------------------------------------------------------- 2667 ** Bit Default Description 2668 ** 15:11 000000 2 Reserved 2669 ** 10 0 Interrupt Disable - This bit disables 80331 from asserting the ATU interrupt signal. 2670 ** 0=enables the assertion of interrupt signal. 2671 ** 1=disables the assertion of its interrupt signal. 2672 ** 09 0 2 Fast Back to Back Enable - When cleared, 2673 ** the ATU interface is not allowed to generate fast back-to-back cycles on its bus. 2674 ** Ignored when operating in the PCI-X mode. 2675 ** 08 0 2 SERR# Enable - When cleared, the ATU interface is not allowed to assert SERR# on the PCI interface. 2676 ** 07 1 2 Address/Data Stepping Control - Address stepping is implemented for configuration transactions. The 2677 ** ATU inserts 2 clock cycles of address stepping for Conventional Mode and 4 clock cycles 2678 ** of address stepping for PCI-X mode. 2679 ** 06 0 2 Parity Error Response - When set, the ATU takes normal action when a parity error 2680 ** is detected. When cleared, parity checking is disabled. 2681 ** 05 0 2 VGA Palette Snoop Enable - The ATU interface does not support I/O writes and therefore, 2682 ** does not perform VGA palette snooping. 2683 ** 04 0 2 Memory Write and Invalidate Enable - When set, ATU may generate MWI commands. 2684 ** When clear, ATU use Memory Write commands instead of MWI. Ignored when operating in the PCI-X mode. 2685 ** 03 0 2 Special Cycle Enable - The ATU interface does not respond to special cycle commands in any way. 2686 ** Not implemented and a reserved bit field. 2687 ** 02 0 2 Bus Master Enable - The ATU interface can act as a master on the PCI bus. 2688 ** When cleared, disables the device from generating PCI accesses. 2689 ** When set, allows the device to behave as a PCI bus master. 2690 ** When operating in the PCI-X mode, ATU initiates a split completion transaction regardless 2691 ** of the state of this bit. 2692 ** 01 0 2 Memory Enable - Controls the ATU interface��s response to PCI memory addresses. 2693 ** When cleared, the ATU interface does not respond to any memory access on the PCI bus. 2694 ** 00 0 2 I/O Space Enable - Controls the ATU interface response to I/O transactions. 2695 ** Not implemented and a reserved bit field. 2696 *********************************************************************************** 2697 */ 2698 #define ARCMSR_ATU_COMMAND_REG 0x04 /*word*/ 2699 /* 2700 *********************************************************************************** 2701 ** ATU Status Register - ATUSR (Sheet 1 of 2) 2702 ** ----------------------------------------------------------------- 2703 ** Bit Default Description 2704 ** 15 0 2 Detected Parity Error - set when a parity error is detected in data received by the ATU on the PCI bus even 2705 ** when the ATUCMD register��s Parity Error Response bit is cleared. Set under the following conditions: 2706 ** �E Write Data Parity Error when the ATU is a target (inbound write). 2707 ** �E Read Data Parity Error when the ATU is a requester (outbound read). 2708 ** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus ** ** ** (including one generated by the ATU). 2709 ** 14 0 2 SERR# Asserted - set when SERR# is asserted on the PCI bus by the ATU. 2710 ** 13 0 2 Master Abort - set when a transaction initiated by the ATU PCI master interface, ends in a Master-Abort 2711 ** or when the ATU receives a Master Abort Split Completion Error Message in PCI-X mode. 2712 ** 12 0 2 Target Abort (master) - set when a transaction initiated by the ATU PCI master interface, ends in a target 2713 ** abort or when the ATU receives a Target Abort Split Completion Error Message in PCI-X mode. 2714 ** 11 0 2 Target Abort (target) - set when the ATU interface, acting as a target, 2715 ** terminates the transaction on the PCI bus with a target abort. 2716 ** 10:09 01 2 DEVSEL# Timing - These bits are read-only and define the slowest DEVSEL# 2717 ** timing for a target device in Conventional PCI Mode regardless of the operating mode 2718 ** (except configuration accesses). 2719 ** 00 2=Fast 2720 ** 01 2=Medium 2721 ** 10 2=Slow 2722 ** 11 2=Reserved 2723 ** The ATU interface uses Medium timing. 2724 ** 08 0 2 Master Parity Error - The ATU interface sets this bit under the following conditions: 2725 ** �E The ATU asserted PERR# itself or the ATU observed PERR# asserted. 2726 ** �E And the ATU acted as the requester 2727 ** for the operation in which the error occurred. 2728 ** �E And the ATUCMD register��s Parity Error Response bit is set 2729 ** �E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message 2730 ** �E And the ATUCMD register��s Parity Error Response bit is set 2731 ** 07 1 2 (Conventional mode) 2732 ** 0 2 (PCI-X mode) 2733 ** Fast Back-to-Back - The ATU/Messaging Unit interface is capable of accepting fast back-to-back 2734 ** transactions in Conventional PCI mode when the transactions are not to the same target. Since fast 2735 ** back-to-back transactions do not exist in PCI-X mode, this bit is forced to 0 in the PCI-X mode. 2736 ** 06 0 2 UDF Supported - User Definable Features are not supported 2737 ** 05 1 2 66 MHz. Capable - 66 MHz operation is supported. 2738 ** 04 1 2 Capabilities - When set, this function implements extended capabilities. 2739 ** 03 0 Interrupt Status - reflects the state of the ATU interrupt 2740 ** when the Interrupt Disable bit in the command register is a 0. 2741 ** 0=ATU interrupt signal deasserted. 2742 ** 1=ATU interrupt signal asserted. 2743 ** NOTE: Setting the Interrupt Disable bit to a 1 has no effect on the state of this bit. Refer to 2744 ** Section 3.10.23, ��ATU Interrupt Pin Register - ATUIPR�� on page 236 for details on the ATU 2745 ** interrupt signal. 2746 ** 02:00 00000 2 Reserved. 2747 *********************************************************************************** 2748 */ 2749 #define ARCMSR_ATU_STATUS_REG 0x06 /*word*/ 2750 /* 2751 *********************************************************************************** 2752 ** ATU Revision ID Register - ATURID 2753 ** ----------------------------------------------------------------- 2754 ** Bit Default Description 2755 ** 07:00 00H ATU Revision - identifies the 80331 revision number. 2756 *********************************************************************************** 2757 */ 2758 #define ARCMSR_ATU_REVISION_REG 0x08 /*byte*/ 2759 /* 2760 *********************************************************************************** 2761 ** ATU Class Code Register - ATUCCR 2762 ** ----------------------------------------------------------------- 2763 ** Bit Default Description 2764 ** 23:16 05H Base Class - Memory Controller 2765 ** 15:08 80H Sub Class - Other Memory Controller 2766 ** 07:00 00H Programming Interface - None defined 2767 *********************************************************************************** 2768 */ 2769 #define ARCMSR_ATU_CLASS_CODE_REG 0x09 /*3bytes 0x0B,0x0A,0x09*/ 2770 /* 2771 *********************************************************************************** 2772 ** ATU Cacheline Size Register - ATUCLSR 2773 ** ----------------------------------------------------------------- 2774 ** Bit Default Description 2775 ** 07:00 00H ATU Cacheline Size - specifies the system cacheline size in DWORDs. Cacheline size is restricted to either 0, 8 or 16 DWORDs. 2776 *********************************************************************************** 2777 */ 2778 #define ARCMSR_ATU_CACHELINE_SIZE_REG 0x0C /*byte*/ 2779 /* 2780 *********************************************************************************** 2781 ** ATU Latency Timer Register - ATULT 2782 ** ----------------------------------------------------------------- 2783 ** Bit Default Description 2784 ** 07:03 00000 2 (for Conventional mode) 2785 ** 01000 2 (for PCI-X mode) 2786 ** Programmable Latency Timer - This field varies the latency timer for the interface from 0 to 248 clocks. 2787 ** The default value is 0 clocks for Conventional PCI mode, and 64 clocks for PCI-X mode. 2788 ** 02:00 000 2 Latency Timer Granularity - These Bits are read only giving a programmable granularity of 8 clocks for the latency timer. 2789 *********************************************************************************** 2790 */ 2791 #define ARCMSR_ATU_LATENCY_TIMER_REG 0x0D /*byte*/ 2792 /* 2793 *********************************************************************************** 2794 ** ATU Header Type Register - ATUHTR 2795 ** ----------------------------------------------------------------- 2796 ** Bit Default Description 2797 ** 07 0 2 Single Function/Multi-Function Device - Identifies the 80331 as a single-function PCI device. 2798 ** 06:00 000000 2 PCI Header Type - This bit field indicates the type of PCI header implemented. The ATU interface 2799 ** header conforms to PCI Local Bus Specification, Revision 2.3. 2800 *********************************************************************************** 2801 */ 2802 #define ARCMSR_ATU_HEADER_TYPE_REG 0x0E /*byte*/ 2803 /* 2804 *********************************************************************************** 2805 ** ATU BIST Register - ATUBISTR 2806 ** 2807 ** The ATU BIST Register controls the functions the Intel XScale core performs when BIST is 2808 ** initiated. This register is the interface between the host processor requesting BIST functions and 2809 ** the 80331 replying with the results from the software implementation of the BIST functionality. 2810 ** ----------------------------------------------------------------- 2811 ** Bit Default Description 2812 ** 07 0 2 BIST Capable - This bit value is always equal to the ATUCR ATU BIST Interrupt Enable bit. 2813 ** 06 0 2 Start BIST - When the ATUCR BIST Interrupt Enable bit is set: 2814 ** Setting this bit generates an interrupt to the Intel XScale core to perform a software BIST function. 2815 ** The Intel XScale core clears this bit when the BIST software has completed with the BIST results 2816 ** found in ATUBISTR register bits [3:0]. 2817 ** When the ATUCR BIST Interrupt Enable bit is clear: 2818 ** Setting this bit does not generate an interrupt to the Intel XScale core and no BIST functions is performed. 2819 ** The Intel XScale core does not clear this bit. 2820 ** 05:04 00 2 Reserved 2821 ** 03:00 0000 2 BIST Completion Code - when the ATUCR BIST Interrupt Enable bit is set and the ATUBISTR Start BIST bit is set (bit 6): 2822 ** The Intel XScale core places the results of the software BIST in these bits. 2823 ** A nonzero value indicates a device-specific error. 2824 *********************************************************************************** 2825 */ 2826 #define ARCMSR_ATU_BIST_REG 0x0F /*byte*/ 2827 2828 /* 2829 *************************************************************************************** 2830 ** ATU Base Registers and Associated Limit Registers 2831 *************************************************************************************** 2832 ** Base Address Register Limit Register Description 2833 ** Inbound ATU Base Address Register 0 Inbound ATU Limit Register 0 Defines the inbound translation window 0 from the PCI bus. 2834 ** Inbound ATU Upper Base Address Register 0 N/A Together with ATU Base Address Register 0 defines the inbound ** translation window 0 from the PCI bus for DACs. 2835 ** Inbound ATU Base Address Register 1 Inbound ATU Limit Register 1 Defines inbound window 1 from the PCI bus. 2836 ** Inbound ATU Upper Base Address Register 1 N/A Together with ATU Base Address Register 1 defines inbound window ** 1 from the PCI bus for DACs. 2837 ** Inbound ATU Base Address Register 2 Inbound ATU Limit Register 2 Defines the inbound translation window 2 from the PCI bus. 2838 ** Inbound ATU Upper Base Address Register 2 N/A Together with ATU Base Address Register 2 defines the inbound ** ** translation window 2 from the PCI bus for DACs. 2839 ** Inbound ATU Base Address Register 3 Inbound ATU Limit Register 3 Defines the inbound translation window 3 from the PCI bus. 2840 ** Inbound ATU Upper Base Address Register 3 N/A Together with ATU Base Address Register 3 defines the inbound ** ** translation window 3 from the PCI bus for DACs. 2841 ** NOTE: This is a private BAR that resides outside of the standard PCI configuration header space (offsets 00H-3FH). 2842 ** Expansion ROM Base Address Register Expansion ROM Limit Register Defines the window of addresses used by a bus master for reading ** from an Expansion ROM. 2843 **-------------------------------------------------------------------------------------- 2844 ** ATU Inbound Window 1 is not a translate window. 2845 ** The ATU does not claim any PCI accesses that fall within this range. 2846 ** This window is used to allocate host memory for use by Private Devices. 2847 ** When enabled, the ATU interrupts the Intel XScale core when either the IABAR1 register or the IAUBAR1 register is written from the PCI bus. 2848 *********************************************************************************** 2849 */ 2850 2851 /* 2852 *********************************************************************************** 2853 ** Inbound ATU Base Address Register 0 - IABAR0 2854 ** 2855 ** . The Inbound ATU Base Address Register 0 (IABAR0) together with the Inbound ATU Upper Base Address Register 0 (IAUBAR0) 2856 ** defines the block of memory addresses where the inbound translation window 0 begins. 2857 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 2858 ** . The IABAR0 and IAUBAR0 define the base address and describes the required memory block size. 2859 ** . Bits 31 through 12 of the IABAR0 is either read/write bits or read only with a value of 0 2860 ** depending on the value located within the IALR0. 2861 ** This configuration allows the IABAR0 to be programmed per PCI Local Bus Specification. 2862 ** The first 4 Kbytes of memory defined by the IABAR0, IAUBAR0 and the IALR0 is reserved for the Messaging Unit. 2863 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2864 ** Warning: 2865 ** When IALR0 is cleared prior to host configuration: 2866 ** the user should also clear the Prefetchable Indicator and the Type Indicator. 2867 ** Assuming IALR0 is not cleared: 2868 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 2869 ** when the Prefetchable Indicator is cleared prior to host configuration, 2870 ** the user should also set the Type Indicator for 32 bit addressability. 2871 ** b. For compliance to the PCI-X Addendum to the PCI Local Bus Specification, 2872 ** when the Prefetchable Indicator is set prior to host configuration, the user 2873 ** should also set the Type Indicator for 64 bit addressability. 2874 ** This is the default for IABAR0. 2875 ** ----------------------------------------------------------------- 2876 ** Bit Default Description 2877 ** 31:12 00000H Translation Base Address 0 - These bits define the actual location 2878 ** the translation function is to respond to when addressed from the PCI bus. 2879 ** 11:04 00H Reserved. 2880 ** 03 1 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 2881 ** 02:01 10 2 Type Indicator - Defines the width of the addressability for this memory window: 2882 ** 00 - Memory Window is locatable anywhere in 32 bit address space 2883 ** 10 - Memory Window is locatable anywhere in 64 bit address space 2884 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 2885 ** The ATU does not occupy I/O space, 2886 ** thus this bit must be zero. 2887 *********************************************************************************** 2888 */ 2889 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS0_REG 0x10 /*dword 0x13,0x12,0x11,0x10*/ 2890 #define ARCMSR_INBOUND_ATU_MEMORY_PREFETCHABLE 0x08 2891 #define ARCMSR_INBOUND_ATU_MEMORY_WINDOW64 0x04 2892 /* 2893 *********************************************************************************** 2894 ** Inbound ATU Upper Base Address Register 0 - IAUBAR0 2895 ** 2896 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 2897 ** Together with the Translation Base Address this register defines the actual location the translation 2898 ** function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 2899 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2900 ** Note: 2901 ** When the Type indicator of IABAR0 is set to indicate 32 bit addressability, 2902 ** the IAUBAR0 register attributes are read-only. 2903 ** ----------------------------------------------------------------- 2904 ** Bit Default Description 2905 ** 31:0 00000H Translation Upper Base Address 0 - Together with the Translation Base Address 0 these bits define the 2906 ** actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes. 2907 *********************************************************************************** 2908 */ 2909 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS0_REG 0x14 /*dword 0x17,0x16,0x15,0x14*/ 2910 /* 2911 *********************************************************************************** 2912 ** Inbound ATU Base Address Register 1 - IABAR1 2913 ** 2914 ** . The Inbound ATU Base Address Register (IABAR1) together with the Inbound ATU Upper Base Address Register 1 (IAUBAR1) 2915 ** defines the block of memory addresses where the inbound translation window 1 begins. 2916 ** . This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PCI bus transactions to this memory range. 2917 ** . The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2918 ** . When enabled, the ATU interrupts the Intel XScale core when the IABAR1 register is written from the PCI bus. 2919 ** Warning: 2920 ** When a non-zero value is not written to IALR1 prior to host configuration, 2921 ** the user should not set either the Prefetchable Indicator or the Type Indicator for 64 bit addressability. 2922 ** This is the default for IABAR1. 2923 ** Assuming a non-zero value is written to IALR1, 2924 ** the user may set the Prefetchable Indicator 2925 ** or the Type Indicator: 2926 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address 2927 ** boundary, when the Prefetchable Indicator is not set prior to host configuration, 2928 ** the user should also leave the Type Indicator set for 32 bit addressability. 2929 ** This is the default for IABAR1. 2930 ** b. when the Prefetchable Indicator is set prior to host configuration, 2931 ** the user should also set the Type Indicator for 64 bit addressability. 2932 ** ----------------------------------------------------------------- 2933 ** Bit Default Description 2934 ** 31:12 00000H Translation Base Address 1 - These bits define the actual location of window 1 on the PCI bus. 2935 ** 11:04 00H Reserved. 2936 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 2937 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 2938 ** 00 - Memory Window is locatable anywhere in 32 bit address space 2939 ** 10 - Memory Window is locatable anywhere in 64 bit address space 2940 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 2941 ** The ATU does not occupy I/O space, 2942 ** thus this bit must be zero. 2943 *********************************************************************************** 2944 */ 2945 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS1_REG 0x18 /*dword 0x1B,0x1A,0x19,0x18*/ 2946 /* 2947 *********************************************************************************** 2948 ** Inbound ATU Upper Base Address Register 1 - IAUBAR1 2949 ** 2950 ** This register contains the upper base address when locating this window for PCI addresses beyond 4 GBytes. 2951 ** Together with the IABAR1 this register defines the actual location for this memory window for addresses > 4GBytes (for DACs). 2952 ** This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PCI bus transactions to this memory range. 2953 ** The programmed value within the base address register must comply with the PCI programming 2954 ** requirements for address alignment. 2955 ** When enabled, the ATU interrupts the Intel XScale core when the IAUBAR1 register is written 2956 ** from the PCI bus. 2957 ** Note: 2958 ** When the Type indicator of IABAR1 is set to indicate 32 bit addressability, 2959 ** the IAUBAR1 register attributes are read-only. 2960 ** This is the default for IABAR1. 2961 ** ----------------------------------------------------------------- 2962 ** Bit Default Description 2963 ** 31:0 00000H Translation Upper Base Address 1 - Together with the Translation Base Address 1 2964 ** these bits define the actual location for this memory window on the PCI bus for addresses > 4GBytes. 2965 *********************************************************************************** 2966 */ 2967 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS1_REG 0x1C /*dword 0x1F,0x1E,0x1D,0x1C*/ 2968 /* 2969 *********************************************************************************** 2970 ** Inbound ATU Base Address Register 2 - IABAR2 2971 ** 2972 ** . The Inbound ATU Base Address Register 2 (IABAR2) together with the Inbound ATU Upper Base Address Register 2 (IAUBAR2) 2973 ** defines the block of memory addresses where the inbound translation window 2 begins. 2974 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 2975 ** . The IABAR2 and IAUBAR2 define the base address and describes the required memory block size 2976 ** . Bits 31 through 12 of the IABAR2 is either read/write bits or read only with a value of 0 depending on the value located within the IALR2. 2977 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2978 ** Warning: 2979 ** When a non-zero value is not written to IALR2 prior to host configuration, 2980 ** the user should not set either the Prefetchable Indicator 2981 ** or the Type Indicator for 64 bit addressability. 2982 ** This is the default for IABAR2. 2983 ** Assuming a non-zero value is written to IALR2, 2984 ** the user may set the Prefetchable Indicator 2985 ** or the Type Indicator: 2986 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 2987 ** when the Prefetchable Indicator is not set prior to host configuration, 2988 ** the user should also leave the Type Indicator set for 32 bit addressability. 2989 ** This is the default for IABAR2. 2990 ** b. when the Prefetchable Indicator is set prior to host configuration, 2991 ** the user should also set the Type Indicator for 64 bit addressability. 2992 ** ----------------------------------------------------------------- 2993 ** Bit Default Description 2994 ** 31:12 00000H Translation Base Address 2 - These bits define the actual location 2995 ** the translation function is to respond to when addressed from the PCI bus. 2996 ** 11:04 00H Reserved. 2997 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 2998 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 2999 ** 00 - Memory Window is locatable anywhere in 32 bit address space 3000 ** 10 - Memory Window is locatable anywhere in 64 bit address space 3001 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 3002 ** The ATU does not occupy I/O space, 3003 ** thus this bit must be zero. 3004 *********************************************************************************** 3005 */ 3006 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS2_REG 0x20 /*dword 0x23,0x22,0x21,0x20*/ 3007 /* 3008 *********************************************************************************** 3009 ** Inbound ATU Upper Base Address Register 2 - IAUBAR2 3010 ** 3011 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 3012 ** Together with the Translation Base Address this register defines the actual location 3013 ** the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 3014 ** The programmed value within the base address register must comply with the PCI programming 3015 ** requirements for address alignment. 3016 ** Note: 3017 ** When the Type indicator of IABAR2 is set to indicate 32 bit addressability, 3018 ** the IAUBAR2 register attributes are read-only. 3019 ** This is the default for IABAR2. 3020 ** ----------------------------------------------------------------- 3021 ** Bit Default Description 3022 ** 31:0 00000H Translation Upper Base Address 2 - Together with the Translation Base Address 2 3023 ** these bits define the actual location the translation function is to respond to 3024 ** when addressed from the PCI bus for addresses > 4GBytes. 3025 *********************************************************************************** 3026 */ 3027 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS2_REG 0x24 /*dword 0x27,0x26,0x25,0x24*/ 3028 /* 3029 *********************************************************************************** 3030 ** ATU Subsystem Vendor ID Register - ASVIR 3031 ** ----------------------------------------------------------------- 3032 ** Bit Default Description 3033 ** 15:0 0000H Subsystem Vendor ID - This register uniquely identifies the add-in board or subsystem vendor. 3034 *********************************************************************************** 3035 */ 3036 #define ARCMSR_ATU_SUBSYSTEM_VENDOR_ID_REG 0x2C /*word 0x2D,0x2C*/ 3037 /* 3038 *********************************************************************************** 3039 ** ATU Subsystem ID Register - ASIR 3040 ** ----------------------------------------------------------------- 3041 ** Bit Default Description 3042 ** 15:0 0000H Subsystem ID - uniquely identifies the add-in board or subsystem. 3043 *********************************************************************************** 3044 */ 3045 #define ARCMSR_ATU_SUBSYSTEM_ID_REG 0x2E /*word 0x2F,0x2E*/ 3046 /* 3047 *********************************************************************************** 3048 ** Expansion ROM Base Address Register -ERBAR 3049 ** ----------------------------------------------------------------- 3050 ** Bit Default Description 3051 ** 31:12 00000H Expansion ROM Base Address - These bits define the actual location 3052 ** where the Expansion ROM address window resides when addressed from the PCI bus on any 4 Kbyte boundary. 3053 ** 11:01 000H Reserved 3054 ** 00 0 2 Address Decode Enable - This bit field shows the ROM address 3055 ** decoder is enabled or disabled. When cleared, indicates the address decoder is disabled. 3056 *********************************************************************************** 3057 */ 3058 #define ARCMSR_EXPANSION_ROM_BASE_ADDRESS_REG 0x30 /*dword 0x33,0x32,0v31,0x30*/ 3059 #define ARCMSR_EXPANSION_ROM_ADDRESS_DECODE_ENABLE 0x01 3060 /* 3061 *********************************************************************************** 3062 ** ATU Capabilities Pointer Register - ATU_CAP_PTR 3063 ** ----------------------------------------------------------------- 3064 ** Bit Default Description 3065 ** 07:00 C0H Capability List Pointer - This provides an offset in this function��s configuration space 3066 ** that points to the 80331 PCl Bus Power Management extended capability. 3067 *********************************************************************************** 3068 */ 3069 #define ARCMSR_ATU_CAPABILITY_PTR_REG 0x34 /*byte*/ 3070 /* 3071 *********************************************************************************** 3072 ** Determining Block Sizes for Base Address Registers 3073 ** The required address size and type can be determined by writing ones to a base address register and 3074 ** reading from the registers. By scanning the returned value from the least-significant bit of the base 3075 ** address registers upwards, the programmer can determine the required address space size. The 3076 ** binary-weighted value of the first non-zero bit found indicates the required amount of space. 3077 ** Table 105 describes the relationship between the values read back and the byte sizes the base 3078 ** address register requires. 3079 ** As an example, assume that FFFF.FFFFH is written to the ATU Inbound Base Address Register 0 3080 ** (IABAR0) and the value read back is FFF0.0008H. Bit zero is a zero, so the device requires 3081 ** memory address space. Bit three is one, so the memory does supports prefetching. Scanning 3082 ** upwards starting at bit four, bit twenty is the first one bit found. The binary-weighted value of this 3083 ** bit is 1,048,576, indicated that the device requires 1 Mbyte of memory space. 3084 ** The ATU Base Address Registers and the Expansion ROM Base Address Register use their 3085 ** associated limit registers to enable which bits within the base address register are read/write and 3086 ** which bits are read only (0). This allows the programming of these registers in a manner similar to 3087 ** other PCI devices even though the limit is variable. 3088 ** Table 105. Memory Block Size Read Response 3089 ** Response After Writing all 1s 3090 ** to the Base Address Register 3091 ** Size 3092 ** (Bytes) 3093 ** Response After Writing all 1s 3094 ** to the Base Address Register 3095 ** Size 3096 ** (Bytes) 3097 ** FFFFFFF0H 16 FFF00000H 1 M 3098 ** FFFFFFE0H 32 FFE00000H 2 M 3099 ** FFFFFFC0H 64 FFC00000H 4 M 3100 ** FFFFFF80H 128 FF800000H 8 M 3101 ** FFFFFF00H 256 FF000000H 16 M 3102 ** FFFFFE00H 512 FE000000H 32 M 3103 ** FFFFFC00H 1K FC000000H 64 M 3104 ** FFFFF800H 2K F8000000H 128 M 3105 ** FFFFF000H 4K F0000000H 256 M 3106 ** FFFFE000H 8K E0000000H 512 M 3107 ** FFFFC000H 16K C0000000H 1 G 3108 ** FFFF8000H 32K 80000000H 2 G 3109 ** FFFF0000H 64K 3110 ** 00000000H 3111 ** Register not 3112 ** imple-mented, 3113 ** no 3114 ** address 3115 ** space 3116 ** required. 3117 ** FFFE0000H 128K 3118 ** FFFC0000H 256K 3119 ** FFF80000H 512K 3120 ** 3121 *************************************************************************************** 3122 */ 3123 3124 /* 3125 *********************************************************************************** 3126 ** ATU Interrupt Line Register - ATUILR 3127 ** ----------------------------------------------------------------- 3128 ** Bit Default Description 3129 ** 07:00 FFH Interrupt Assigned - system-assigned value identifies which system interrupt controller��s interrupt 3130 ** request line connects to the device's PCI interrupt request lines 3131 ** (as specified in the interrupt pin register). 3132 ** A value of FFH signifies ��no connection�� or ��unknown��. 3133 *********************************************************************************** 3134 */ 3135 #define ARCMSR_ATU_INTERRUPT_LINE_REG 0x3C /*byte*/ 3136 /* 3137 *********************************************************************************** 3138 ** ATU Interrupt Pin Register - ATUIPR 3139 ** ----------------------------------------------------------------- 3140 ** Bit Default Description 3141 ** 07:00 01H Interrupt Used - A value of 01H signifies that the ATU interface unit uses INTA# as the interrupt pin. 3142 *********************************************************************************** 3143 */ 3144 #define ARCMSR_ATU_INTERRUPT_PIN_REG 0x3D /*byte*/ 3145 /* 3146 *********************************************************************************** 3147 ** ATU Minimum Grant Register - ATUMGNT 3148 ** ----------------------------------------------------------------- 3149 ** Bit Default Description 3150 ** 07:00 80H This register specifies how long a burst period the device needs in increments of 8 PCI clocks. 3151 *********************************************************************************** 3152 */ 3153 #define ARCMSR_ATU_MINIMUM_GRANT_REG 0x3E /*byte*/ 3154 /* 3155 *********************************************************************************** 3156 ** ATU Maximum Latency Register - ATUMLAT 3157 ** ----------------------------------------------------------------- 3158 ** Bit Default Description 3159 ** 07:00 00H Specifies frequency (how often) the device needs to access the PCI bus 3160 ** in increments of 8 PCI clocks. A zero value indicates the device has no stringent requirement. 3161 *********************************************************************************** 3162 */ 3163 #define ARCMSR_ATU_MAXIMUM_LATENCY_REG 0x3F /*byte*/ 3164 /* 3165 *********************************************************************************** 3166 ** Inbound Address Translation 3167 ** 3168 ** The ATU allows external PCI bus initiators to directly access the internal bus. 3169 ** These PCI bus initiators can read or write 80331 memory-mapped registers or 80331 local memory space. 3170 ** The process of inbound address translation involves two steps: 3171 ** 1. Address Detection. 3172 ** �E Determine when the 32-bit PCI address (64-bit PCI address during DACs) is 3173 ** within the address windows defined for the inbound ATU. 3174 ** �E Claim the PCI transaction with medium DEVSEL# timing in the conventional PCI 3175 ** mode and with Decode A DEVSEL# timing in the PCI-X mode. 3176 ** 2. Address Translation. 3177 ** �E Translate the 32-bit PCI address (lower 32-bit PCI address during DACs) to a 32-bit 80331 internal bus address. 3178 ** The ATU uses the following registers in inbound address window 0 translation: 3179 ** �E Inbound ATU Base Address Register 0 3180 ** �E Inbound ATU Limit Register 0 3181 ** �E Inbound ATU Translate Value Register 0 3182 ** The ATU uses the following registers in inbound address window 2 translation: 3183 ** �E Inbound ATU Base Address Register 2 3184 ** �E Inbound ATU Limit Register 2 3185 ** �E Inbound ATU Translate Value Register 2 3186 ** The ATU uses the following registers in inbound address window 3 translation: 3187 ** �E Inbound ATU Base Address Register 3 3188 ** �E Inbound ATU Limit Register 3 3189 ** �E Inbound ATU Translate Value Register 3 3190 ** Note: Inbound Address window 1 is not a translate window. 3191 ** Instead, window 1 may be used to allocate host memory for Private Devices. 3192 ** Inbound Address window 3 does not reside in the standard section of the configuration header (offsets 00H - 3CH), 3193 ** thus the host BIOS does not configure window 3. 3194 ** Window 3 is intended to be used as a special window into local memory for private PCI 3195 ** agents controlled by the 80331 in conjunction with the Private Memory Space of the bridge. 3196 ** PCI-to-PCI Bridge in 80331 or 3197 ** Inbound address detection is determined from the 32-bit PCI address, 3198 ** (64-bit PCI address during DACs) the base address register and the limit register. 3199 ** In the case of DACs none of the upper 32-bits of the address is masked during address comparison. 3200 ** 3201 ** The algorithm for detection is: 3202 ** 3203 ** Equation 1. Inbound Address Detection 3204 ** When (PCI_Address [31:0] & Limit_Register[31:0]) == (Base_Register[31:0] & PCI_Address [63:32]) == Base_Register[63:32] (for DACs only) 3205 ** the PCI Address is claimed by the Inbound ATU. 3206 ** 3207 ** The incoming 32-bit PCI address (lower 32-bits of the address in case of DACs) is bitwise ANDed 3208 ** with the associated inbound limit register. 3209 ** When the result matches the base register (and upper base address matches upper PCI address in case of DACs), 3210 ** the inbound PCI address is detected as being within the inbound translation window and is claimed by the ATU. 3211 ** 3212 ** Note: The first 4 Kbytes of the ATU inbound address translation window 0 are reserved for the Messaging Unit. 3213 ** Once the transaction is claimed, the address must be translated from a PCI address to a 32-bit 3214 ** internal bus address. In case of DACs upper 32-bits of the address is simply discarded and only the 3215 ** lower 32-bits are used during address translation. 3216 ** The algorithm is: 3217 ** 3218 ** 3219 ** Equation 2. Inbound Translation 3220 ** Intel I/O processor Internal Bus Address=(PCI_Address[31:0] & ~Limit_Register[31:0]) | ATU_Translate_Value_Register[31:0]. 3221 ** 3222 ** The incoming 32-bit PCI address (lower 32-bits in case of DACs) is first bitwise ANDed with the 3223 ** bitwise inverse of the limit register. This result is bitwise ORed with the ATU Translate Value and 3224 ** the result is the internal bus address. This translation mechanism is used for all inbound memory 3225 ** read and write commands excluding inbound configuration read and writes. 3226 ** In the PCI mode for inbound memory transactions, the only burst order supported is Linear 3227 ** Incrementing. For any other burst order, the ATU signals a Disconnect after the first data phase. 3228 ** The PCI-X supports linear incrementing only, and hence above situation is not encountered in the PCI-X mode. 3229 ** example: 3230 ** Register Values 3231 ** Base_Register=3A00 0000H 3232 ** Limit_Register=FF80 0000H (8 Mbyte limit value) 3233 ** Value_Register=B100 0000H 3234 ** Inbound Translation Window ranges from 3A00 0000H to 3A7F FFFFH (8 Mbytes) 3235 ** 3236 ** Address Detection (32-bit address) 3237 ** 3238 ** PCI_Address & Limit_Register == Base_Register 3239 ** 3A45 012CH & FF80 0000H == 3A00 0000H 3240 ** 3241 ** ANS: PCI_Address is in the Inbound Translation Window 3242 ** Address Translation (to get internal bus address) 3243 ** 3244 ** IB_Address=(PCI_Address & ~Limit_Register) | Value_Reg 3245 ** IB_Address=(3A45 012CH & 007F FFFFH) | B100 0000H 3246 ** 3247 ** ANS:IB_Address=B145 012CH 3248 *********************************************************************************** 3249 */ 3250 3251 /* 3252 *********************************************************************************** 3253 ** Inbound ATU Limit Register 0 - IALR0 3254 ** 3255 ** Inbound address translation for memory window 0 occurs for data transfers occurring from the PCI 3256 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 3257 ** PCI addresses to internal bus addresses. 3258 ** The 80331 translate value register��s programmed value must be naturally aligned with the base 3259 ** address register��s programmed value. The limit register is used as a mask; thus, the lower address 3260 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 3261 ** Specification, Revision 2.3 for additional information on programming base address registers. 3262 ** Bits 31 to 12 within the IALR0 have a direct effect on the IABAR0 register, bits 31 to 12, with a 3263 ** one to one correspondence. A value of 0 in a bit within the IALR0 makes the corresponding bit 3264 ** within the IABAR0 a read only bit which always returns 0. A value of 1 in a bit within the IALR0 3265 ** makes the corresponding bit within the IABAR0 read/write from PCI. Note that a consequence of 3266 ** this programming scheme is that unless a valid value exists within the IALR0, all writes to the 3267 ** IABAR0 has no effect since a value of all zeros within the IALR0 makes the IABAR0 a read only register. 3268 ** ----------------------------------------------------------------- 3269 ** Bit Default Description 3270 ** 31:12 FF000H Inbound Translation Limit 0 - This readback value determines the memory block size required for 3271 ** inbound memory window 0 of the address translation unit. This defaults to an inbound window of 16MB. 3272 ** 11:00 000H Reserved 3273 *********************************************************************************** 3274 */ 3275 #define ARCMSR_INBOUND_ATU_LIMIT0_REG 0x40 /*dword 0x43,0x42,0x41,0x40*/ 3276 /* 3277 *********************************************************************************** 3278 ** Inbound ATU Translate Value Register 0 - IATVR0 3279 ** 3280 ** The Inbound ATU Translate Value Register 0 (IATVR0) contains the internal bus address used to 3281 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 3282 ** inbound ATU address translation. 3283 ** ----------------------------------------------------------------- 3284 ** Bit Default Description 3285 ** 31:12 FF000H Inbound ATU Translation Value 0 - This value is used to convert the PCI address to internal bus addresses. 3286 ** This value must be 64-bit aligned on the internal bus. 3287 ** The default address allows the ATU to access the internal 80331 memory-mapped registers. 3288 ** 11:00 000H Reserved 3289 *********************************************************************************** 3290 */ 3291 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE0_REG 0x44 /*dword 0x47,0x46,0x45,0x44*/ 3292 /* 3293 *********************************************************************************** 3294 ** Expansion ROM Limit Register - ERLR 3295 ** 3296 ** The Expansion ROM Limit Register (ERLR) defines the block size of addresses the ATU defines 3297 ** as Expansion ROM address space. The block size is programmed by writing a value into the ERLR. 3298 ** Bits 31 to 12 within the ERLR have a direct effect on the ERBAR register, bits 31 to 12, with a one 3299 ** to one correspondence. A value of 0 in a bit within the ERLR makes the corresponding bit within 3300 ** the ERBAR a read only bit which always returns 0. A value of 1 in a bit within the ERLR makes 3301 ** the corresponding bit within the ERBAR read/write from PCI. 3302 ** ----------------------------------------------------------------- 3303 ** Bit Default Description 3304 ** 31:12 000000H Expansion ROM Limit - Block size of memory required for the Expansion ROM translation unit. Default 3305 ** value is 0, which indicates no Expansion ROM address space and all bits within the ERBAR are read only with a value of 0. 3306 ** 11:00 000H Reserved. 3307 *********************************************************************************** 3308 */ 3309 #define ARCMSR_EXPANSION_ROM_LIMIT_REG 0x48 /*dword 0x4B,0x4A,0x49,0x48*/ 3310 /* 3311 *********************************************************************************** 3312 ** Expansion ROM Translate Value Register - ERTVR 3313 ** 3314 ** The Expansion ROM Translate Value Register contains the 80331 internal bus address which the 3315 ** ATU converts the PCI bus access. This address is driven on the internal bus as a result of the 3316 ** Expansion ROM address translation. 3317 ** ----------------------------------------------------------------- 3318 ** Bit Default Description 3319 ** 31:12 00000H Expansion ROM Translation Value - Used to convert PCI addresses to 80331 internal bus addresses 3320 ** for Expansion ROM accesses. The Expansion ROM address translation value must be word aligned on the internal bus. 3321 ** 11:00 000H Reserved 3322 *********************************************************************************** 3323 */ 3324 #define ARCMSR_EXPANSION_ROM_TRANSLATE_VALUE_REG 0x4C /*dword 0x4F,0x4E,0x4D,0x4C*/ 3325 /* 3326 *********************************************************************************** 3327 ** Inbound ATU Limit Register 1 - IALR1 3328 ** 3329 ** Bits 31 to 12 within the IALR1 have a direct effect on the IABAR1 register, bits 31 to 12, with a 3330 ** one to one correspondence. A value of 0 in a bit within the IALR1 makes the corresponding bit 3331 ** within the IABAR1 a read only bit which always returns 0. A value of 1 in a bit within the IALR1 3332 ** makes the corresponding bit within the IABAR1 read/write from PCI. Note that a consequence of 3333 ** this programming scheme is that unless a valid value exists within the IALR1, all writes to the 3334 ** IABAR1 has no effect since a value of all zeros within the IALR1 makes the IABAR1 a read only 3335 ** register. 3336 ** The inbound memory window 1 is used merely to allocate memory on the PCI bus. The ATU does 3337 ** not process any PCI bus transactions to this memory range. 3338 ** Warning: The ATU does not claim any PCI accesses that fall within the range defined by IABAR1, 3339 ** IAUBAR1, and IALR1. 3340 ** ----------------------------------------------------------------- 3341 ** Bit Default Description 3342 ** 31:12 00000H Inbound Translation Limit 1 - This readback value determines the memory block size 3343 ** required for the ATUs memory window 1. 3344 ** 11:00 000H Reserved 3345 *********************************************************************************** 3346 */ 3347 #define ARCMSR_INBOUND_ATU_LIMIT1_REG 0x50 /*dword 0x53,0x52,0x51,0x50*/ 3348 /* 3349 *********************************************************************************** 3350 ** Inbound ATU Limit Register 2 - IALR2 3351 ** 3352 ** Inbound address translation for memory window 2 occurs for data transfers occurring from the PCI 3353 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 3354 ** PCI addresses to internal bus addresses. 3355 ** The inbound translation base address for inbound window 2 is specified in Section 3.10.15. When 3356 ** determining block size requirements �X as described in Section 3.10.21 �X the translation limit 3357 ** register provides the block size requirements for the base address register. The remaining registers 3358 ** used for performing address translation are discussed in Section 3.2.1.1. 3359 ** The 80331 translate value register��s programmed value must be naturally aligned with the base 3360 ** address register��s programmed value. The limit register is used as a mask; thus, the lower address 3361 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 3362 ** Specification, Revision 2.3 for additional information on programming base address registers. 3363 ** Bits 31 to 12 within the IALR2 have a direct effect on the IABAR2 register, bits 31 to 12, with a 3364 ** one to one correspondence. A value of 0 in a bit within the IALR2 makes the corresponding bit 3365 ** within the IABAR2 a read only bit which always returns 0. A value of 1 in a bit within the IALR2 3366 ** makes the corresponding bit within the IABAR2 read/write from PCI. Note that a consequence of 3367 ** this programming scheme is that unless a valid value exists within the IALR2, all writes to the 3368 ** IABAR2 has no effect since a value of all zeros within the IALR2 makes the IABAR2 a read only 3369 ** register. 3370 ** ----------------------------------------------------------------- 3371 ** Bit Default Description 3372 ** 31:12 00000H Inbound Translation Limit 2 - This readback value determines the memory block size 3373 ** required for the ATUs memory window 2. 3374 ** 11:00 000H Reserved 3375 *********************************************************************************** 3376 */ 3377 #define ARCMSR_INBOUND_ATU_LIMIT2_REG 0x54 /*dword 0x57,0x56,0x55,0x54*/ 3378 /* 3379 *********************************************************************************** 3380 ** Inbound ATU Translate Value Register 2 - IATVR2 3381 ** 3382 ** The Inbound ATU Translate Value Register 2 (IATVR2) contains the internal bus address used to 3383 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 3384 ** inbound ATU address translation. 3385 ** ----------------------------------------------------------------- 3386 ** Bit Default Description 3387 ** 31:12 00000H Inbound ATU Translation Value 2 - This value is used to convert the PCI address to internal bus addresses. 3388 ** This value must be 64-bit aligned on the internal bus. 3389 ** The default address allows the ATU to access the internal 80331 ** ** memory-mapped registers. 3390 ** 11:00 000H Reserved 3391 *********************************************************************************** 3392 */ 3393 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE2_REG 0x58 /*dword 0x5B,0x5A,0x59,0x58*/ 3394 /* 3395 *********************************************************************************** 3396 ** Outbound I/O Window Translate Value Register - OIOWTVR 3397 ** 3398 ** The Outbound I/O Window Translate Value Register (OIOWTVR) contains the PCI I/O address 3399 ** used to convert the internal bus access to a PCI address. This address is driven on the PCI bus as a 3400 ** result of the outbound ATU address translation. 3401 ** The I/O window is from 80331 internal bus address 9000 000H to 9000 FFFFH with the fixed 3402 ** length of 64 Kbytes. 3403 ** ----------------------------------------------------------------- 3404 ** Bit Default Description 3405 ** 31:16 0000H Outbound I/O Window Translate Value - Used to convert internal bus addresses to PCI addresses. 3406 ** 15:00 0000H Reserved 3407 *********************************************************************************** 3408 */ 3409 #define ARCMSR_OUTBOUND_IO_WINDOW_TRANSLATE_VALUE_REG 0x5C /*dword 0x5F,0x5E,0x5D,0x5C*/ 3410 /* 3411 *********************************************************************************** 3412 ** Outbound Memory Window Translate Value Register 0 -OMWTVR0 3413 ** 3414 ** The Outbound Memory Window Translate Value Register 0 (OMWTVR0) contains the PCI 3415 ** address used to convert 80331 internal bus addresses for outbound transactions. This address is 3416 ** driven on the PCI bus as a result of the outbound ATU address translation. 3417 ** The memory window is from internal bus address 8000 000H to 83FF FFFFH with the fixed length 3418 ** of 64 Mbytes. 3419 ** ----------------------------------------------------------------- 3420 ** Bit Default Description 3421 ** 31:26 00H Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses. 3422 ** 25:02 00 0000H Reserved 3423 ** 01:00 00 2 Burst Order - This bit field shows the address sequence during a memory burst. 3424 ** Only linear incrementing mode is supported. 3425 *********************************************************************************** 3426 */ 3427 #define ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x60 /*dword 0x63,0x62,0x61,0x60*/ 3428 /* 3429 *********************************************************************************** 3430 ** Outbound Upper 32-bit Memory Window Translate Value Register 0 - OUMWTVR0 3431 ** 3432 ** The Outbound Upper 32-bit Memory Window Translate Value Register 0 (OUMWTVR0) defines 3433 ** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to 3434 ** directly address anywhere within the 64-bit host address space. When this register is all-zero, then 3435 ** a SAC is generated on the PCI bus. 3436 ** The memory window is from internal bus address 8000 000H to 83FF FFFFH with the fixed 3437 ** length of 64 Mbytes. 3438 ** ----------------------------------------------------------------- 3439 ** Bit Default Description 3440 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 3441 *********************************************************************************** 3442 */ 3443 #define ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x64 /*dword 0x67,0x66,0x65,0x64*/ 3444 /* 3445 *********************************************************************************** 3446 ** Outbound Memory Window Translate Value Register 1 -OMWTVR1 3447 ** 3448 ** The Outbound Memory Window Translate Value Register 1 (OMWTVR1) contains the PCI 3449 ** address used to convert 80331 internal bus addresses for outbound transactions. This address is 3450 ** driven on the PCI bus as a result of the outbound ATU address translation. 3451 ** The memory window is from internal bus address 8400 000H to 87FF FFFFH with the fixed length 3452 ** of 64 Mbytes. 3453 ** ----------------------------------------------------------------- 3454 ** Bit Default Description 3455 ** 31:26 00H Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses. 3456 ** 25:02 00 0000H Reserved 3457 ** 01:00 00 2 Burst Order - This bit field shows the address sequence during a memory burst. 3458 ** Only linear incrementing mode is supported. 3459 *********************************************************************************** 3460 */ 3461 #define ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x68 /*dword 0x6B,0x6A,0x69,0x68*/ 3462 /* 3463 *********************************************************************************** 3464 ** Outbound Upper 32-bit Memory Window Translate Value Register 1 - OUMWTVR1 3465 ** 3466 ** The Outbound Upper 32-bit Memory Window Translate Value Register 1 (OUMWTVR1) defines 3467 ** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to 3468 ** directly address anywhere within the 64-bit host address space. When this register is all-zero, then 3469 ** a SAC is generated on the PCI bus. 3470 ** The memory window is from internal bus address 8400 000H to 87FF FFFFH with the fixed length 3471 ** of 64 Mbytes. 3472 ** ----------------------------------------------------------------- 3473 ** Bit Default Description 3474 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 3475 *********************************************************************************** 3476 */ 3477 #define ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x6C /*dword 0x6F,0x6E,0x6D,0x6C*/ 3478 /* 3479 *********************************************************************************** 3480 ** Outbound Upper 32-bit Direct Window Translate Value Register - OUDWTVR 3481 ** 3482 ** The Outbound Upper 32-bit Direct Window Translate Value Register (OUDWTVR) defines the 3483 ** upper 32-bits of address used during a dual address cycle for the transactions via Direct Addressing 3484 ** Window. This enables the outbound ATU to directly address anywhere within the 64-bit host 3485 ** address space. When this register is all-zero, then a SAC is generated on the PCI bus. 3486 ** ----------------------------------------------------------------- 3487 ** Bit Default Description 3488 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 3489 *********************************************************************************** 3490 */ 3491 #define ARCMSR_OUTBOUND_UPPER32_DIRECT_WINDOW_TRANSLATE_VALUE_REG 0x78 /*dword 0x7B,0x7A,0x79,0x78*/ 3492 /* 3493 *********************************************************************************** 3494 ** ATU Configuration Register - ATUCR 3495 ** 3496 ** The ATU Configuration Register controls the outbound address translation for address translation 3497 ** unit. It also contains bits for Conventional PCI Delayed Read Command (DRC) aliasing, discard 3498 ** timer status, SERR# manual assertion, SERR# detection interrupt masking, and ATU BIST 3499 ** interrupt enabling. 3500 ** ----------------------------------------------------------------- 3501 ** Bit Default Description 3502 ** 31:20 00H Reserved 3503 ** 19 0 2 ATU DRC Alias - when set, the ATU does not distinguish read commands when attempting to match a 3504 ** current PCI read transaction with read data enqueued within the DRC buffer. When clear, a current read 3505 ** transaction must have the exact same read command as the DRR for the ATU to deliver DRC data. Not 3506 ** applicable in the PCI-X mode. 3507 ** 18 0 2 Direct Addressing Upper 2Gbytes Translation Enable - When set, 3508 ** with Direct Addressing enabled (bit 7 of the ATUCR set), 3509 ** the ATU forwards internal bus cycles with an address between 0000.0040H and 3510 ** 7FFF.FFFFH to the PCI bus with bit 31 of the address set (8000.0000H - FFFF.FFFFH). 3511 ** When clear, no translation occurs. 3512 ** 17 0 2 Reserved 3513 ** 16 0 2 SERR# Manual Assertion - when set, the ATU asserts SERR# for one clock on the PCI interface. Until 3514 ** cleared, SERR# may not be manually asserted again. Once cleared, operation proceeds as specified. 3515 ** 15 0 2 ATU Discard Timer Status - when set, one of the 4 discard timers within the ATU has expired and 3516 ** discarded the delayed completion transaction within the queue. When clear, no timer has expired. 3517 ** 14:10 00000 2 Reserved 3518 ** 09 0 2 SERR# Detected Interrupt Enable - When set, the Intel XScale core is signalled an HPI# interrupt 3519 ** when the ATU detects that SERR# was asserted. When clear, 3520 ** the Intel XScale core is not interrupted when SERR# is detected. 3521 ** 08 0 2 Direct Addressing Enable - Setting this bit enables direct outbound addressing through the ATU. 3522 ** Internal bus cycles with an address between 0000.0040H and 7FFF.FFFFH automatically forwards to 3523 ** the PCI bus with or without translation of address bit 31 based on the setting of bit 18 of 3524 ** the ATUCR. 3525 ** 07:04 0000 2 Reserved 3526 ** 03 0 2 ATU BIST Interrupt Enable - When set, enables an interrupt to the Intel XScale core when the start 3527 ** BIST bit is set in the ATUBISTR register. This bit is also reflected as the BIST Capable bit 7 3528 ** in the ATUBISTR register. 3529 ** 02 0 2 Reserved 3530 ** 01 0 2 Outbound ATU Enable - When set, enables the outbound address translation unit. 3531 ** When cleared, disables the outbound ATU. 3532 ** 00 0 2 Reserved 3533 *********************************************************************************** 3534 */ 3535 #define ARCMSR_ATU_CONFIGURATION_REG 0x80 /*dword 0x83,0x82,0x81,0x80*/ 3536 /* 3537 *********************************************************************************** 3538 ** PCI Configuration and Status Register - PCSR 3539 ** 3540 ** The PCI Configuration and Status Register has additional bits for controlling and monitoring 3541 ** various features of the PCI bus interface. 3542 ** ----------------------------------------------------------------- 3543 ** Bit Default Description 3544 ** 31:19 0000H Reserved 3545 ** 18 0 2 Detected Address or Attribute Parity Error - set when a parity error is detected during either the address 3546 ** or attribute phase of a transaction on the PCI bus even when the ATUCMD register Parity Error 3547 ** Response bit is cleared. Set under the following conditions: 3548 ** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus (including one generated by the ATU). 3549 ** 17:16 Varies with 3550 ** external state 3551 ** of DEVSEL#, 3552 ** STOP#, and 3553 ** TRDY#, 3554 ** during 3555 ** P_RST# 3556 ** PCI-X capability - These two bits define the mode of 3557 ** the PCI bus (conventional or PCI-X) as well as the 3558 ** operating frequency in the case of PCI-X mode. 3559 ** 00 - Conventional PCI mode 3560 ** 01 - PCI-X 66 3561 ** 10 - PCI-X 100 3562 ** 11 - PCI-X 133 3563 ** As defined by the PCI-X Addendum to the PCI Local Bus Specification, 3564 ** Revision 1.0a, the operating 3565 ** mode is determined by an initialization pattern on the PCI bus during 3566 ** P_RST# assertion: 3567 ** DEVSEL# STOP# TRDY# Mode 3568 ** Deasserted Deasserted Deasserted Conventional 3569 ** Deasserted Deasserted Asserted PCI-X 66 3570 ** Deasserted Asserted Deasserted PCI-X 100 3571 ** Deasserted Asserted Asserted PCI-X 133 3572 ** All other patterns are reserved. 3573 ** 15 0 2 3574 ** Outbound Transaction Queue Busy: 3575 ** 0=Outbound Transaction Queue Empty 3576 ** 1=Outbound Transaction Queue Busy 3577 ** 14 0 2 3578 ** Inbound Transaction Queue Busy: 3579 ** 0=Inbound Transaction Queue Empty 3580 ** 1=Inbound Transaction Queue Busy 3581 ** 13 0 2 Reserved. 3582 ** 12 0 2 Discard Timer Value - This bit controls the time-out value 3583 ** for the four discard timers attached to the queues holding read data. 3584 ** A value of 0 indicates the time-out value is 2 15 clocks. 3585 ** A value of 1 indicates the time-out value is 2 10 clocks. 3586 ** 11 0 2 Reserved. 3587 ** 10 Varies with 3588 ** external state 3589 ** of M66EN 3590 ** during 3591 ** P_RST# 3592 ** Bus Operating at 66 MHz - When set, the interface has been initialized to function at 66 MHz in 3593 ** Conventional PCI mode by the assertion of M66EN during bus initialization. 3594 ** When clear, the interface 3595 ** has been initialized as a 33 MHz bus. 3596 ** NOTE: When PCSR bits 17:16 are not equal to zero, then this bit is meaningless since the 80331 is operating in PCI-X mode. 3597 ** 09 0 2 Reserved 3598 ** 08 Varies with 3599 ** external state 3600 ** of REQ64# 3601 ** during 3602 ** P_RST# 3603 ** PCI Bus 64-Bit Capable - When clear, the PCI bus interface has been 3604 ** configured as 64-bit capable by 3605 ** the assertion of REQ64# on the rising edge of P_RST#. When set, 3606 ** the PCI interface is configured as 3607 ** 32-bit only. 3608 ** 07:06 00 2 Reserved. 3609 ** 05 0 2 Reset Internal Bus - This bit controls the reset of the Intel XScale core 3610 ** and all units on the internal 3611 ** bus. In addition to the internal bus initialization, 3612 ** this bit triggers the assertion of the M_RST# pin for 3613 ** initialization of registered DIMMs. When set: 3614 ** When operating in the conventional PCI mode: 3615 ** �E All current PCI transactions being mastered by the ATU completes, 3616 ** and the ATU master interfaces 3617 ** proceeds to an idle state. No additional transactions is mastered by these units 3618 ** until the internal bus reset is complete. 3619 ** �E All current transactions being slaved by the ATU on either the PCI bus 3620 ** or the internal bus 3621 ** completes, and the ATU target interfaces proceeds to an idle state. 3622 ** All future slave transactions master aborts, 3623 ** with the exception of the completion cycle for the transaction that set the Reset 3624 ** Internal Bus bit in the PCSR. 3625 ** �E When the value of the Core Processor Reset bit in the PCSR (upon P_RST# assertion) 3626 ** is set, the Intel XScale core is held in reset when the internal bus reset is complete. 3627 ** �E The ATU ignores configuration cycles, and they appears as master aborts for: 32 3628 ** Internal Bus clocks. 3629 ** �E The 80331 hardware clears this bit after the reset operation completes. 3630 ** When operating in the PCI-X mode: 3631 ** The ATU hardware responds the same as in Conventional PCI-X mode. 3632 ** However, this may create a problem in PCI-X mode for split requests in 3633 ** that there may still be an outstanding split completion that the 3634 ** ATU is either waiting to receive (Outbound Request) or initiate 3635 ** (Inbound Read Request). For a cleaner 3636 ** internal bus reset, host software can take the following steps prior 3637 ** to asserting Reset Internal bus: 3638 ** 1. Clear the Bus Master (bit 2 of the ATUCMD) and the Memory Enable (bit 1 of the ATUCMD) bits in 3639 ** the ATUCMD. This ensures that no new transactions, either outbound or inbound are enqueued. 3640 ** 2. Wait for both the Outbound (bit 15 of the PCSR) and Inbound Read (bit 14 of the PCSR) Transaction 3641 ** queue busy bits to be clear. 3642 ** 3. Set the Reset Internal Bus bit 3643 ** As a result, the ATU hardware resets the internal bus using the same logic as in conventional mode, 3644 ** however the user is now assured that the ATU no longer has any pending inbound or outbound split 3645 ** completion transactions. 3646 ** NOTE: Since the Reset Internal Bus bit is set using an inbound configuration cycle, the user is 3647 ** guaranteed that any prior configuration cycles have properly completed since there is only a one 3648 ** deep transaction queue for configuration transaction requests. The ATU sends the appropriate 3649 ** Split Write Completion Message to the Requester prior to the onset of Internal Bus Reset. 3650 ** 04 0 2 Bus Master Indicator Enable: Provides software control for the 3651 ** Bus Master Indicator signal P_BMI used 3652 ** for external RAIDIOS logic control of private devices. Only valid when operating with the bridge and 3653 ** central resource/arbiter disabled (BRG_EN =low, ARB_EN=low). 3654 ** 03 Varies with external state of PRIVDEV during 3655 ** P_RST# 3656 ** Private Device Enable - This bit indicates the state of the reset strap which enables the private device 3657 ** control mechanism within the PCI-to-PCI Bridge SISR configuration register. 3658 ** 0=Private Device control Disabled - SISR register bits default to zero 3659 ** 1=Private Device control Enabled - SISR register bits default to one 3660 ** 02 Varies with external state of RETRY during P_RST# 3661 ** Configuration Cycle Retry - When this bit is set, the PCI interface of the 80331 responds to all 3662 ** configuration cycles with a Retry condition. When clear, the 80331 responds to the appropriate 3663 ** configuration cycles. 3664 ** The default condition for this bit is based on the external state of the RETRY pin at the rising edge of 3665 ** P_RST#. When the external state of the pin is high, the bit is set. When the external state of the pin is 3666 ** low, the bit is cleared. 3667 ** 01 Varies with external state of CORE_RST# during P_RST# 3668 ** Core Processor Reset - This bit is set to its default value by the hardware when either P_RST# is 3669 ** asserted or the Reset Internal Bus bit in PCSR is set. When this bit is set, the Intel XScale core is 3670 ** being held in reset. Software cannot set this bit. Software is required to clear this bit to deassert Intel 3671 ** XScale core reset. 3672 ** The default condition for this bit is based on the external state of the CORE_RST# pin at the rising edge 3673 ** of P_RST#. When the external state of the pin is low, the bit is set. When the external state of the pin is 3674 ** high, the bit is clear. 3675 ** 00 Varies with external state of PRIVMEM during P_RST# 3676 ** Private Memory Enable - This bit indicates the state of the reset strap which enables the private device 3677 ** control mechanism within the PCI-to-PCI Bridge SDER configuration register. 3678 ** 0=Private Memory control Disabled - SDER register bit 2 default to zero 3679 ** 1=Private Memory control Enabled - SDER register bits 2 default to one 3680 *********************************************************************************** 3681 */ 3682 #define ARCMSR_PCI_CONFIGURATION_STATUS_REG 0x84 /*dword 0x87,0x86,0x85,0x84*/ 3683 /* 3684 *********************************************************************************** 3685 ** ATU Interrupt Status Register - ATUISR 3686 ** 3687 ** The ATU Interrupt Status Register is used to notify the core processor of the source of an ATU 3688 ** interrupt. In addition, this register is written to clear the source of the interrupt to the interrupt unit 3689 ** of the 80331. All bits in this register are Read/Clear. 3690 ** Bits 4:0 are a direct reflection of bits 14:11 and bit 8 (respectively) of the ATU Status Register 3691 ** (these bits are set at the same time by hardware but need to be cleared independently). Bit 7 is set 3692 ** by an error associated with the internal bus of the 80331. Bit 8 is for software BIST. The 3693 ** conditions that result in an ATU interrupt are cleared by writing a 1 to the appropriate bits in this 3694 ** register. 3695 ** Note: Bits 4:0, and bits 15 and 13:7 can result in an interrupt being driven to the Intel XScale core. 3696 ** ----------------------------------------------------------------- 3697 ** Bit Default Description 3698 ** 31:18 0000H Reserved 3699 ** 17 0 2 VPD Address Register Updated - This bit is set when a PCI bus configuration write occurs to the VPDAR 3700 ** register. Configuration register writes to the VPDAR does NOT result in bit 15 also being set. When set, 3701 ** this bit results in the assertion of the ATU Configure Register Write Interrupt. 3702 ** 16 0 2 Reserved 3703 ** 15 0 2 ATU Configuration Write - This bit is set when a PCI bus configuration write occurs to any ATU register. 3704 ** When set, this bit results in the assertion of the ATU Configure Register Write Interrupt. 3705 ** 14 0 2 ATU Inbound Memory Window 1 Base Updated - This bit is set when a PCI bus configuration write 3706 ** occurs to either the IABAR1 register or the IAUBAR1 register. Configuration register writes to these 3707 ** registers deos NOT result in bit 15 also being set. When set, this bit results in the assertion of the ATU 3708 ** Configure Register Write Interrupt. 3709 ** 13 0 2 Initiated Split Completion Error Message - This bit is set when the device initiates a Split Completion 3710 ** Message on the PCI Bus with the Split Completion Error attribute bit set. 3711 ** 12 0 2 Received Split Completion Error Message - This bit is set when the device receives a Split Completion 3712 ** Message from the PCI Bus with the Split Completion Error attribute bit set. 3713 ** 11 0 2 Power State Transition - When the Power State Field of the ATU Power Management Control/Status 3714 ** Register is written to transition the ATU function Power State from D0 to D3, D0 to D1, or D3 to D0 and 3715 ** the ATU Power State Transition Interrupt mask bit is cleared, this bit is set. 3716 ** 10 0 2 P_SERR# Asserted - set when P_SERR# is asserted on the PCI bus by the ATU. 3717 ** 09 0 2 Detected Parity Error - set when a parity error is detected on the PCI bus even when the ATUCMD 3718 ** register��s Parity Error Response bit is cleared. Set under the following conditions: 3719 ** �E Write Data Parity Error when the ATU is a target (inbound write). 3720 ** �E Read Data Parity Error when the ATU is an initiator (outbound read). 3721 ** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus. 3722 ** 08 0 2 ATU BIST Interrupt - When set, generates the ATU BIST Start Interrupt and indicates the host processor 3723 ** has set the Start BIST bit (ATUBISTR register bit 6), when the ATU BIST interrupt is enabled (ATUCR 3724 ** register bit 3). The Intel XScale core can initiate the software BIST and store the result in ATUBISTR 3725 ** register bits 3:0. 3726 ** Configuration register writes to the ATUBISTR does NOT result in bit 15 also being set or the assertion 3727 ** of the ATU Configure Register Write Interrupt. 3728 ** 07 0 2 Internal Bus Master Abort - set when a transaction initiated by the ATU internal bus initiator interface ends in a Master-abort. 3729 ** 06:05 00 2 Reserved. 3730 ** 04 0 2 P_SERR# Detected - set when P_SERR# is detected on the PCI bus by the ATU. 3731 ** 03 0 2 PCI Master Abort - set when a transaction initiated by the ATU PCI initiator interface ends in a Master-abort. 3732 ** 02 0 2 PCI Target Abort (master) - set when a transaction initiated by the ATU PCI master interface ends in a Target-abort. 3733 ** 01 0 2 PCI Target Abort (target) - set when the ATU interface, acting as a target, terminates the transaction on the PCI bus with a target abort. 3734 ** 00 0 2 PCI Master Parity Error - Master Parity Error - The ATU interface sets this bit under the following 3735 ** conditions: 3736 ** �E The ATU asserted PERR# itself or the ATU observed PERR# asserted. 3737 ** �E And the ATU acted as the requester for the operation in which the error occurred. 3738 ** �E And the ATUCMD register��s Parity Error Response bit is set 3739 ** �E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message 3740 ** �E And the ATUCMD register��s Parity Error Response bit is set 3741 *********************************************************************************** 3742 */ 3743 #define ARCMSR_ATU_INTERRUPT_STATUS_REG 0x88 /*dword 0x8B,0x8A,0x89,0x88*/ 3744 /* 3745 *********************************************************************************** 3746 ** ATU Interrupt Mask Register - ATUIMR 3747 ** 3748 ** The ATU Interrupt Mask Register contains the control bit to enable and disable interrupts 3749 ** generated by the ATU. 3750 ** ----------------------------------------------------------------- 3751 ** Bit Default Description 3752 ** 31:15 0 0000H Reserved 3753 ** 14 0 2 VPD Address Register Updated Mask - Controls the setting of bit 17 of the ATUISR and generation of the 3754 ** ATU Configuration Register Write interrupt when a PCI bus write occurs to the VPDAR register. 3755 ** 0=Not Masked 3756 ** 1=Masked 3757 ** 13 0 2 Reserved 3758 ** 12 0 2 Configuration Register Write Mask - Controls the setting of bit 15 of the ATUISR and generation of the 3759 ** ATU Configuration Register Write interrupt when a PCI bus write occurs to any ATU configuration register 3760 ** except those covered by mask bit 11 and bit 14 of this register, and ATU BIST enable bit 3 of the ATUCR. 3761 ** 0=Not Masked 3762 ** 1=Masked 3763 ** 11 1 2 ATU Inbound Memory Window 1 Base Updated Mask - Controls the setting of bit 14 of the ATUISR and 3764 ** generation of the ATU Configuration Register Write interrupt when a PCI bus write occurs to either the 3765 ** IABAR1 register or the IAUBAR1 register. 3766 ** 0=Not Masked 3767 ** 1=Masked 3768 ** 10 0 2 Initiated Split Completion Error Message Interrupt Mask - Controls the setting of bit 13 of the ATUISR and 3769 ** generation of the ATU Error interrupt when the ATU initiates a Split Completion Error Message. 3770 ** 0=Not Masked 3771 ** 1=Masked 3772 ** 09 0 2 Received Split Completion Error Message Interrupt Mask- Controls the setting of bit 12 of the ATUISR 3773 ** and generation of the ATU Error interrupt when a Split Completion Error Message results in bit 29 of the 3774 ** PCIXSR being set. 3775 ** 0=Not Masked 3776 ** 1=Masked 3777 ** 08 1 2 Power State Transition Interrupt Mask - Controls the setting of bit 12 of the ATUISR and generation of the 3778 ** ATU Error interrupt when ATU Power Management Control/Status Register is written to transition the 3779 ** ATU Function Power State from D0 to D3, D0 to D1, D1 to D3 or D3 to D0. 3780 ** 0=Not Masked 3781 ** 1=Masked 3782 ** 07 0 2 ATU Detected Parity Error Interrupt Mask - Controls the setting of bit 9 of the ATUISR and generation of 3783 ** the ATU Error interrupt when a parity error detected on the PCI bus that sets bit 15 of the ATUSR. 3784 ** 0=Not Masked 3785 ** 1=Masked 3786 ** 06 0 2 ATU SERR# Asserted Interrupt Mask - Controls the setting of bit 10 of the ATUISR and generation of the 3787 ** ATU Error interrupt when SERR# is asserted on the PCI interface resulting in bit 14 of the ATUSR being set. 3788 ** 0=Not Masked 3789 ** 1=Masked 3790 ** NOTE: This bit is specific to the ATU asserting SERR# and not detecting SERR# from another master. 3791 ** 05 0 2 ATU PCI Master Abort Interrupt Mask - Controls the setting of bit 3 of the ATUISR and generation of the 3792 ** ATU Error interrupt when a master abort error resulting in bit 13 of the ATUSR being set. 3793 ** 0=Not Masked 3794 ** 1=Masked 3795 ** 04 0 2 ATU PCI Target Abort (Master) Interrupt Mask- Controls the setting of bit 12 of the ATUISR and ATU Error 3796 ** generation of the interrupt when a target abort error resulting in bit 12 of the ATUSR being set 3797 ** 0=Not Masked 3798 ** 1=Masked 3799 ** 03 0 2 ATU PCI Target Abort (Target) Interrupt Mask- Controls the setting of bit 1 of the ATUISR and generation 3800 ** of the ATU Error interrupt when a target abort error resulting in bit 11 of the ATUSR being set. 3801 ** 0=Not Masked 3802 ** 1=Masked 3803 ** 02 0 2 ATU PCI Master Parity Error Interrupt Mask - Controls the setting of bit 0 of the ATUISR and generation 3804 ** of the ATU Error interrupt when a parity error resulting in bit 8 of the ATUSR being set. 3805 ** 0=Not Masked 3806 ** 1=Masked 3807 ** 01 0 2 ATU Inbound Error SERR# Enable - Controls when the ATU asserts (when enabled through the 3808 ** ATUCMD) SERR# on the PCI interface in response to a master abort on the internal bus during an 3809 ** inbound write transaction. 3810 ** 0=SERR# Not Asserted due to error 3811 ** 1=SERR# Asserted due to error 3812 ** 00 0 2 ATU ECC Target Abort Enable - Controls the ATU response on the PCI interface to a target abort (ECC 3813 ** error) from the memory controller on the internal bus. In conventional mode, this action only occurs 3814 ** during an inbound read transaction where the data phase that was target aborted on the internal bus is 3815 ** actually requested from the inbound read queue. 3816 ** 0=Disconnect with data 3817 ** (the data being up to 64 bits of 1��s) 3818 ** 1=Target Abort 3819 ** NOTE: In PCI-X Mode, The ATU initiates a Split Completion Error Message (with message class=2h - 3820 ** completer error and message index=81h - 80331 internal bus target abort) on the PCI bus, 3821 ** independent of the setting of this bit. 3822 *********************************************************************************** 3823 */ 3824 #define ARCMSR_ATU_INTERRUPT_MASK_REG 0x8C /*dword 0x8F,0x8E,0x8D,0x8C*/ 3825 /* 3826 *********************************************************************************** 3827 ** Inbound ATU Base Address Register 3 - IABAR3 3828 ** 3829 ** . The Inbound ATU Base Address Register 3 (IABAR3) together with the Inbound ATU Upper Base Address Register 3 (IAUBAR3) defines the block 3830 ** of memory addresses where the inbound translation window 3 begins. 3831 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 3832 ** . The IABAR3 and IAUBAR3 define the base address and describes the required memory block size. 3833 ** . Bits 31 through 12 of the IABAR3 is either read/write bits or read only with a value of 0 depending on the value located within the IALR3. 3834 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 3835 ** Note: 3836 ** Since IABAR3 does not appear in the standard PCI configuration header space (offsets 00H - 3CH), 3837 ** IABAR3 is not configured by the host during normal system initialization. 3838 ** Warning: 3839 ** When a non-zero value is not written to IALR3, 3840 ** the user should not set either the Prefetchable Indicator 3841 ** or the Type Indicator for 64 bit addressability. 3842 ** This is the default for IABAR3. 3843 ** Assuming a non-zero value is written to IALR3, 3844 ** the user may set the Prefetchable Indicator 3845 ** or the Type Indicator: 3846 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 3847 ** when the Prefetchable Indicator is not set, 3848 ** the user should also leave the Type Indicator set for 32 bit addressability. 3849 ** This is the default for IABAR3. 3850 ** b. when the Prefetchable Indicator is set, 3851 ** the user should also set the Type Indicator for 64 bit addressability. 3852 ** ----------------------------------------------------------------- 3853 ** Bit Default Description 3854 ** 31:12 00000H Translation Base Address 3 - These bits define the actual location 3855 ** the translation function is to respond to when addressed from the PCI bus. 3856 ** 11:04 00H Reserved. 3857 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 3858 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 3859 ** 00 - Memory Window is locatable anywhere in 32 bit address space 3860 ** 10 - Memory Window is locatable anywhere in 64 bit address space 3861 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 3862 ** The ATU does not occupy I/O space, 3863 ** thus this bit must be zero. 3864 *********************************************************************************** 3865 */ 3866 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS3_REG 0x90 /*dword 0x93,0x92,0x91,0x90*/ 3867 /* 3868 *********************************************************************************** 3869 ** Inbound ATU Upper Base Address Register 3 - IAUBAR3 3870 ** 3871 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 3872 ** Together with the Translation Base Address this register defines the actual location 3873 ** the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 3874 ** The programmed value within the base address register must comply with the PCI programming 3875 ** requirements for address alignment. 3876 ** Note: 3877 ** When the Type indicator of IABAR3 is set to indicate 32 bit addressability, 3878 ** the IAUBAR3 register attributes are read-only. 3879 ** This is the default for IABAR3. 3880 ** ----------------------------------------------------------------- 3881 ** Bit Default Description 3882 ** 31:0 00000H Translation Upper Base Address 3 - Together with the Translation Base Address 3 these bits define 3883 ** the actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes. 3884 *********************************************************************************** 3885 */ 3886 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS3_REG 0x94 /*dword 0x97,0x96,0x95,0x94*/ 3887 /* 3888 *********************************************************************************** 3889 ** Inbound ATU Limit Register 3 - IALR3 3890 ** 3891 ** Inbound address translation for memory window 3 occurs for data transfers occurring from the PCI 3892 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 3893 ** PCI addresses to internal bus addresses. 3894 ** The inbound translation base address for inbound window 3 is specified in Section 3.10.15. When 3895 ** determining block size requirements �X as described in Section 3.10.21 �X the translation limit 3896 ** register provides the block size requirements for the base address register. The remaining registers 3897 ** used for performing address translation are discussed in Section 3.2.1.1. 3898 ** The 80331 translate value register��s programmed value must be naturally aligned with the base 3899 ** address register��s programmed value. The limit register is used as a mask; thus, the lower address 3900 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 3901 ** Specification, Revision 2.3 for additional information on programming base address registers. 3902 ** Bits 31 to 12 within the IALR3 have a direct effect on the IABAR3 register, bits 31 to 12, with a 3903 ** one to one correspondence. A value of 0 in a bit within the IALR3 makes the corresponding bit 3904 ** within the IABAR3 a read only bit which always returns 0. A value of 1 in a bit within the IALR3 3905 ** makes the corresponding bit within the IABAR3 read/write from PCI. Note that a consequence of 3906 ** this programming scheme is that unless a valid value exists within the IALR3, all writes to the 3907 ** IABAR3 has no effect since a value of all zeros within the IALR3 makes the IABAR3 a read only 3908 ** register. 3909 ** ----------------------------------------------------------------- 3910 ** Bit Default Description 3911 ** 31:12 00000H Inbound Translation Limit 3 - This readback value determines the memory block size required 3912 ** for the ATUs memory window 3. 3913 ** 11:00 000H Reserved 3914 *********************************************************************************** 3915 */ 3916 #define ARCMSR_INBOUND_ATU_LIMIT3_REG 0x98 /*dword 0x9B,0x9A,0x99,0x98*/ 3917 /* 3918 *********************************************************************************** 3919 ** Inbound ATU Translate Value Register 3 - IATVR3 3920 ** 3921 ** The Inbound ATU Translate Value Register 3 (IATVR3) contains the internal bus address used to 3922 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 3923 ** inbound ATU address translation. 3924 ** ----------------------------------------------------------------- 3925 ** Bit Default Description 3926 ** 31:12 00000H Inbound ATU Translation Value 3 - This value is used to convert the PCI address to internal bus addresses. 3927 ** This value must be 64-bit aligned on the internal bus. The default address allows the ATU to 3928 ** access the internal 80331 memory-mapped registers. 3929 ** 11:00 000H Reserved 3930 *********************************************************************************** 3931 */ 3932 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE3_REG 0x9C /*dword 0x9F,0x9E,0x9D,0x9C*/ 3933 /* 3934 *********************************************************************************** 3935 ** Outbound Configuration Cycle Address Register - OCCAR 3936 ** 3937 ** The Outbound Configuration Cycle Address Register is used to hold the 32-bit PCI configuration 3938 ** cycle address. The Intel XScale core writes the PCI configuration cycles address which then 3939 ** enables the outbound configuration read or write. The Intel XScale core then performs a read or 3940 ** write to the Outbound Configuration Cycle Data Register to initiate the configuration cycle on the 3941 ** PCI bus. 3942 ** Note: Bits 15:11 of the configuration cycle address for Type 0 configuration cycles are defined differently 3943 ** for Conventional versus PCI-X modes. When 80331 software programs the OCCAR to initiate a 3944 ** Type 0 configuration cycle, the OCCAR should always be loaded based on the PCI-X definition for 3945 ** the Type 0 configuration cycle address. When operating in Conventional mode, the 80331 clears 3946 ** bits 15:11 of the OCCAR prior to initiating an outbound Type 0 configuration cycle. See the PCI-X 3947 ** Addendum to the PCI Local Bus Specification, Revision 1.0a for details on the two formats. 3948 ** ----------------------------------------------------------------- 3949 ** Bit Default Description 3950 ** 31:00 0000 0000H Configuration Cycle Address - These bits define the 32-bit PCI address used during an outbound 3951 ** configuration read or write cycle. 3952 *********************************************************************************** 3953 */ 3954 #define ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_ADDRESS_REG 0xA4 /*dword 0xA7,0xA6,0xA5,0xA4*/ 3955 /* 3956 *********************************************************************************** 3957 ** Outbound Configuration Cycle Data Register - OCCDR 3958 ** 3959 ** The Outbound Configuration Cycle Data Register is used to initiate a configuration read or write 3960 ** on the PCI bus. The register is logical rather than physical meaning that it is an address not a 3961 ** register. The Intel XScale core reads or writes the data registers memory-mapped address to 3962 ** initiate the configuration cycle on the PCI bus with the address found in the OCCAR. For a 3963 ** configuration write, the data is latched from the internal bus and forwarded directly to the OWQ. 3964 ** For a read, the data is returned directly from the ORQ to the Intel XScale core and is never 3965 ** actually entered into the data register (which does not physically exist). 3966 ** The OCCDR is only visible from 80331 internal bus address space and appears as a reserved value 3967 ** within the ATU configuration space. 3968 ** ----------------------------------------------------------------- 3969 ** Bit Default Description 3970 ** 31:00 0000 0000H Configuration Cycle Data - These bits define the data used during an outbound configuration read 3971 ** or write cycle. 3972 *********************************************************************************** 3973 */ 3974 #define ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_DATA_REG 0xAC /*dword 0xAF,0xAE,0xAD,0xAC*/ 3975 /* 3976 *********************************************************************************** 3977 ** VPD Capability Identifier Register - VPD_CAPID 3978 ** 3979 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 3980 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 3981 ** Capability contained in that header. In the case of the 80331, this is the VPD extended capability 3982 ** with an ID of 03H as defined by the PCI Local Bus Specification, Revision 2.3. 3983 ** ----------------------------------------------------------------- 3984 ** Bit Default Description 3985 ** 07:00 03H Cap_Id - This field with its�� 03H value identifies this item in the linked list of Extended Capability 3986 ** Headers as being the VPD capability registers. 3987 *********************************************************************************** 3988 */ 3989 #define ARCMSR_VPD_CAPABILITY_IDENTIFIER_REG 0xB8 /*byte*/ 3990 /* 3991 *********************************************************************************** 3992 ** VPD Next Item Pointer Register - VPD_NXTP 3993 ** 3994 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 3995 ** Revision 2.3. This register describes the location of the next item in the function��s capability list. 3996 ** For the 80331, this the final capability list, and hence, this register is set to 00H. 3997 ** ----------------------------------------------------------------- 3998 ** Bit Default Description 3999 ** 07:00 00H Next_ Item_ Pointer - This field provides an offset into the function��s configuration space pointing to the 4000 ** next item in the function��s capability list. Since the VPD capabilities are the last in the linked list of 4001 ** extended capabilities in the 80331, the register is set to 00H. 4002 *********************************************************************************** 4003 */ 4004 #define ARCMSR_VPD_NEXT_ITEM_PTR_REG 0xB9 /*byte*/ 4005 /* 4006 *********************************************************************************** 4007 ** VPD Address Register - VPD_AR 4008 ** 4009 ** The VPD Address register (VPDAR) contains the DWORD-aligned byte address of the VPD to be 4010 ** accessed. The register is read/write and the initial value at power-up is indeterminate. 4011 ** A PCI Configuration Write to the VPDAR interrupts the Intel XScale core. Software can use 4012 ** the Flag setting to determine whether the configuration write was intended to initiate a read or 4013 ** write of the VPD through the VPD Data Register. 4014 ** ----------------------------------------------------------------- 4015 ** Bit Default Description 4016 ** 15 0 2 Flag - A flag is used to indicate when a transfer of data between the VPD Data Register and the storage 4017 ** component has completed. Please see Section 3.9, ��Vital Product Data�� on page 201 for more details on 4018 ** how the 80331 handles the data transfer. 4019 ** 14:0 0000H VPD Address - This register is written to set the DWORD-aligned byte address used to read or write 4020 ** Vital Product Data from the VPD storage component. 4021 *********************************************************************************** 4022 */ 4023 #define ARCMSR_VPD_ADDRESS_REG 0xBA /*word 0xBB,0xBA*/ 4024 /* 4025 *********************************************************************************** 4026 ** VPD Data Register - VPD_DR 4027 ** 4028 ** This register is used to transfer data between the 80331 and the VPD storage component. 4029 ** ----------------------------------------------------------------- 4030 ** Bit Default Description 4031 ** 31:00 0000H VPD Data - Four bytes are always read or written through this register to/from the VPD storage component. 4032 *********************************************************************************** 4033 */ 4034 #define ARCMSR_VPD_DATA_REG 0xBC /*dword 0xBF,0xBE,0xBD,0xBC*/ 4035 /* 4036 *********************************************************************************** 4037 ** Power Management Capability Identifier Register -PM_CAPID 4038 ** 4039 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 4040 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 4041 ** Capability contained in that header. In the case of the 80331, this is the PCI Bus Power 4042 ** Management extended capability with an ID of 01H as defined by the PCI Bus Power Management 4043 ** Interface Specification, Revision 1.1. 4044 ** ----------------------------------------------------------------- 4045 ** Bit Default Description 4046 ** 07:00 01H Cap_Id - This field with its�� 01H value identifies this item in the linked list of Extended Capability 4047 ** Headers as being the PCI Power Management Registers. 4048 *********************************************************************************** 4049 */ 4050 #define ARCMSR_POWER_MANAGEMENT_CAPABILITY_IDENTIFIER_REG 0xC0 /*byte*/ 4051 /* 4052 *********************************************************************************** 4053 ** Power Management Next Item Pointer Register - PM_NXTP 4054 ** 4055 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 4056 ** Revision 2.3. This register describes the location of the next item in the function��s capability list. 4057 ** For the 80331, the next capability (MSI capability list) is located at off-set D0H. 4058 ** ----------------------------------------------------------------- 4059 ** Bit Default Description 4060 ** 07:00 D0H Next_ Item_ Pointer - This field provides an offset into the function��s configuration space pointing to the 4061 ** next item in the function��s capability list which in the 80331 is the MSI extended capabilities header. 4062 *********************************************************************************** 4063 */ 4064 #define ARCMSR_POWER_NEXT_ITEM_PTR_REG 0xC1 /*byte*/ 4065 /* 4066 *********************************************************************************** 4067 ** Power Management Capabilities Register - PM_CAP 4068 ** 4069 ** Power Management Capabilities bits adhere to the definitions in the PCI Bus Power Management 4070 ** Interface Specification, Revision 1.1. This register is a 16-bit read-only register which provides 4071 ** information on the capabilities of the ATU function related to power management. 4072 ** ----------------------------------------------------------------- 4073 ** Bit Default Description 4074 ** 15:11 00000 2 PME_Support - This function is not capable of asserting the PME# signal in any state, since PME# 4075 ** is not supported by the 80331. 4076 ** 10 0 2 D2_Support - This bit is set to 0 2 indicating that the 80331 does not support the D2 Power Management State 4077 ** 9 1 2 D1_Support - This bit is set to 1 2 indicating that the 80331 supports the D1 Power Management State 4078 ** 8:6 000 2 Aux_Current - This field is set to 000 2 indicating that the 80331 has no current requirements for the 4079 ** 3.3Vaux signal as defined in the PCI Bus Power Management Interface Specification, Revision 1.1 4080 ** 5 0 2 DSI - This field is set to 0 2 meaning that this function requires a device specific initialization sequence 4081 ** following the transition to the D0 uninitialized state. 4082 ** 4 0 2 Reserved. 4083 ** 3 0 2 PME Clock - Since the 80331 does not support PME# signal generation this bit is cleared to 0 2 . 4084 ** 2:0 010 2 Version - Setting these bits to 010 2 means that this function complies with PCI Bus Power Management 4085 ** Interface Specification, Revision 1.1 4086 *********************************************************************************** 4087 */ 4088 #define ARCMSR_POWER_MANAGEMENT_CAPABILITY_REG 0xC2 /*word 0xC3,0xC2*/ 4089 /* 4090 *********************************************************************************** 4091 ** Power Management Control/Status Register - PM_CSR 4092 ** 4093 ** Power Management Control/Status bits adhere to the definitions in the PCI Bus Power 4094 ** Management Interface Specification, Revision 1.1. This 16-bit register is the control and status 4095 ** interface for the power management extended capability. 4096 ** ----------------------------------------------------------------- 4097 ** Bit Default Description 4098 ** 15 0 2 PME_Status - This function is not capable of asserting the PME# signal in any state, since PME## is not 4099 ** supported by the 80331. 4100 ** 14:9 00H Reserved 4101 ** 8 0 2 PME_En - This bit is hardwired to read-only 0 2 since this function does not support PME# 4102 ** generation from any power state. 4103 ** 7:2 000000 2 Reserved 4104 ** 1:0 00 2 Power State - This 2-bit field is used both to determine the current power state 4105 ** of a function and to set the function into a new power state. The definition of the values is: 4106 ** 00 2 - D0 4107 ** 01 2 - D1 4108 ** 10 2 - D2 (Unsupported) 4109 ** 11 2 - D3 hot 4110 ** The 80331 supports only the D0 and D3 hot states. 4111 ** 4112 *********************************************************************************** 4113 */ 4114 #define ARCMSR_POWER_MANAGEMENT_CONTROL_STATUS_REG 0xC4 /*word 0xC5,0xC4*/ 4115 /* 4116 *********************************************************************************** 4117 ** PCI-X Capability Identifier Register - PX_CAPID 4118 ** 4119 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 4120 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 4121 ** Capability contained in that header. In the case of the 80331, this is the PCI-X extended capability with 4122 ** an ID of 07H as defined by the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a. 4123 ** ----------------------------------------------------------------- 4124 ** Bit Default Description 4125 ** 07:00 07H Cap_Id - This field with its�� 07H value identifies this item in the linked list of Extended Capability 4126 ** Headers as being the PCI-X capability registers. 4127 *********************************************************************************** 4128 */ 4129 #define ARCMSR_PCIX_CAPABILITY_IDENTIFIER_REG 0xE0 /*byte*/ 4130 /* 4131 *********************************************************************************** 4132 ** PCI-X Next Item Pointer Register - PX_NXTP 4133 ** 4134 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 4135 ** Revision 2.3. This register describes the location of the next item in the function��s capability list. 4136 ** By default, the PCI-X capability is the last capabilities list for the 80331, thus this register defaults 4137 ** to 00H. 4138 ** However, this register may be written to B8H prior to host configuration to include the VPD 4139 ** capability located at off-set B8H. 4140 ** Warning: Writing this register to any value other than 00H (default) or B8H is not supported and may 4141 ** produce unpredictable system behavior. 4142 ** In order to guarantee that this register is written prior to host configuration, the 80331 must be 4143 ** initialized at P_RST# assertion to Retry Type 0 configuration cycles (bit 2 of PCSR). Typically, 4144 ** the Intel XScale core would be enabled to boot immediately following P_RST# assertion in 4145 ** this case (bit 1 of PCSR), as well. Please see Table 125, ��PCI Configuration and Status Register - 4146 ** PCSR�� on page 253 for more details on the 80331 initialization modes. 4147 ** ----------------------------------------------------------------- 4148 ** Bit Default Description 4149 ** 07:00 00H Next_ Item_ Pointer - This field provides an offset into the function��s configuration space pointing to the 4150 ** next item in the function��s capability list. Since the PCI-X capabilities are the last in the linked list of 4151 ** extended capabilities in the 80331, the register is set to 00H. 4152 ** However, this field may be written prior to host configuration with B8H to extend the list to include the 4153 ** VPD extended capabilities header. 4154 *********************************************************************************** 4155 */ 4156 #define ARCMSR_PCIX_NEXT_ITEM_PTR_REG 0xE1 /*byte*/ 4157 /* 4158 *********************************************************************************** 4159 ** PCI-X Command Register - PX_CMD 4160 ** 4161 ** This register controls various modes and features of ATU and Message Unit when operating in the 4162 ** PCI-X mode. 4163 ** ----------------------------------------------------------------- 4164 ** Bit Default Description 4165 ** 15:7 000000000 2 Reserved. 4166 ** 6:4 011 2 Maximum Outstanding Split Transactions - This register sets the maximum number of Split Transactions 4167 ** the device is permitted to have outstanding at one time. 4168 ** Register Maximum Outstanding 4169 ** 0 1 4170 ** 1 2 4171 ** 2 3 4172 ** 3 4 4173 ** 4 8 4174 ** 5 12 4175 ** 6 16 4176 ** 7 32 4177 ** 3:2 00 2 Maximum Memory Read Byte Count - This register sets the maximum byte count the device uses when 4178 ** initiating a Sequence with one of the burst memory read commands. 4179 ** Register Maximum Byte Count 4180 ** 0 512 4181 ** 1 1024 4182 ** 2 2048 4183 ** 3 4096 4184 ** 1 0 2 4185 ** Enable Relaxed Ordering - The 80331 does not set the relaxed ordering bit in the Requester Attributes 4186 ** of Transactions. 4187 ** 0 0 2 Data Parity Error Recovery Enable - The device driver sets this bit to enable the device to attempt to 4188 ** recover from data parity errors. When this bit is 0 and the device is in PCI-X mode, the device asserts 4189 ** SERR# (when enabled) whenever the Master Data Parity Error bit (Status register, bit 8) is set. 4190 *********************************************************************************** 4191 */ 4192 #define ARCMSR_PCIX_COMMAND_REG 0xE2 /*word 0xE3,0xE2*/ 4193 /* 4194 *********************************************************************************** 4195 ** PCI-X Status Register - PX_SR 4196 ** 4197 ** This register identifies the capabilities and current operating mode of ATU, DMAs and Message 4198 ** Unit when operating in the PCI-X mode. 4199 ** ----------------------------------------------------------------- 4200 ** Bit Default Description 4201 ** 31:30 00 2 Reserved 4202 ** 29 0 2 Received Split Completion Error Message - This bit is set when the device receives a Split Completion 4203 ** Message with the Split Completion Error attribute bit set. Once set, this bit remains set until software 4204 ** writes a 1 to this location. 4205 ** 0=no Split Completion error message received. 4206 ** 1=a Split Completion error message has been received. 4207 ** 28:26 001 2 Designed Maximum Cumulative Read Size (DMCRS) - The value of this register depends on the setting 4208 ** of the Maximum Memory Read Byte Count field of the PCIXCMD register: 4209 ** DMCRS Max ADQs Maximum Memory Read Byte Count Register Setting 4210 ** 1 16 512 (Default) 4211 ** 2 32 1024 4212 ** 2 32 2048 4213 ** 2 32 4096 4214 ** 25:23 011 2 Designed Maximum Outstanding Split Transactions - The 80331 can have up to four outstanding split transactions. 4215 ** 22:21 01 2 Designed Maximum Memory Read Byte Count - The 80331 can generate memory reads with byte counts up 4216 ** to 1024 bytes. 4217 ** 20 1 2 80331 is a complex device. 4218 ** 19 0 2 Unexpected Split Completion - This bit is set when an unexpected Split Completion with this device��s 4219 ** Requester ID is received. Once set, this bit remains set until software writes a 1 to this location. 4220 ** 0=no unexpected Split Completion has been received. 4221 ** 1=an unexpected Split Completion has been received. 4222 ** 18 0 2 Split Completion Discarded - This bit is set when the device discards a Split Completion because the 4223 ** requester would not accept it. See Section 5.4.4 of the PCI-X Addendum to the PCI Local Bus 4224 ** Specification, Revision 1.0a for details. Once set, this bit remains set until software writes a 1 to this 4225 ** location. 4226 ** 0=no Split Completion has been discarded. 4227 ** 1=a Split Completion has been discarded. 4228 ** NOTE: The 80331 does not set this bit since there is no Inbound address responding to Inbound Read 4229 ** Requests with Split Responses (Memory or Register) that has ��read side effects.�� 4230 ** 17 1 2 80331 is a 133 MHz capable device. 4231 ** 16 1 2 or P_32BITPCI# 80331 with bridge enabled (BRG_EN=1) implements the ATU with a 64-bit interface on the secondary PCI bus, 4232 ** therefore this bit is always set. 4233 ** 80331 with no bridge and central resource disabled (BRG_EN=0, ARB_EN=0), 4234 ** use this bit to identify the add-in card to the system as 64-bit or 32-bit wide via a user-configurable strap (P_32BITPCI#). 4235 ** This strap, by default, identifies the add in card based on 80331 with bridge disabled 4236 ** as 64-bit unless the user attaches the appropriate pull-down resistor to the strap. 4237 ** 0=The bus is 32 bits wide. 4238 ** 1=The bus is 64 bits wide. 4239 ** 15:8 FFH Bus Number - This register is read for diagnostic purposes only. It indicates the number of the bus 4240 ** segment for the device containing this function. The function uses this number as part of its Requester 4241 ** ID and Completer ID. For all devices other than the source bridge, each time the function is addressed 4242 ** by a Configuration Write transaction, the function must update this register with the contents of AD[7::0] 4243 ** of the attribute phase of the Configuration Write, regardless of which register in the function is 4244 ** addressed by the transaction. The function is addressed by a Configuration Write transaction when all of 4245 ** the following are true: 4246 ** 1. The transaction uses a Configuration Write command. 4247 ** 2. IDSEL is asserted during the address phase. 4248 ** 3. AD[1::0] are 00b (Type 0 configuration transaction). 4249 ** 4. AD[10::08] of the configuration address contain the appropriate function number. 4250 ** 7:3 1FH Device Number - This register is read for diagnostic purposes only. It indicates the number of the device 4251 ** containing this function, i.e., the number in the Device Number field (AD[15::11]) of the address of a 4252 ** Type 0 configuration transaction that is assigned to the device containing this function by the connection 4253 ** of the system hardware. The system must assign a device number other than 00h (00h is reserved for 4254 ** the source bridge). The function uses this number as part of its Requester ID and Completer ID. Each 4255 ** time the function is addressed by a Configuration Write transaction, the device must update this register 4256 ** with the contents of AD[15::11] of the address phase of the Configuration Write, regardless of which 4257 ** register in the function is addressed by the transaction. The function is addressed by a Configuration 4258 ** Write transaction when all of the following are true: 4259 ** 1. The transaction uses a Configuration Write command. 4260 ** 2. IDSEL is asserted during the address phase. 4261 ** 3. AD[1::0] are 00b (Type 0 configuration transaction). 4262 ** 4. AD[10::08] of the configuration address contain the appropriate function number. 4263 ** 2:0 000 2 Function Number - This register is read for diagnostic purposes only. It indicates the number of this 4264 ** function; i.e., the number in the Function Number field (AD[10::08]) of the address of a Type 0 4265 ** configuration transaction to which this function responds. The function uses this number as part of its 4266 ** Requester ID and Completer ID. 4267 ** 4268 ************************************************************************** 4269 */ 4270 #define ARCMSR_PCIX_STATUS_REG 0xE4 /*dword 0xE7,0xE6,0xE5,0xE4*/ 4271 4272 /* 4273 ************************************************************************** 4274 ** Inbound Read Transaction 4275 ** ======================================================================== 4276 ** An inbound read transaction is initiated by a PCI initiator and is targeted at either 80331 local 4277 ** memory or a 80331 memory-mapped register space. The read transaction is propagated through 4278 ** the inbound transaction queue (ITQ) and read data is returned through the inbound read queue 4279 ** (IRQ). 4280 ** When operating in the conventional PCI mode, all inbound read transactions are processed as 4281 ** delayed read transactions. When operating in the PCI-X mode, all inbound read transactions are 4282 ** processed as split transactions. The ATUs PCI interface claims the read transaction and forwards 4283 ** the read request through to the internal bus and returns the read data to the PCI bus. Data flow for 4284 ** an inbound read transaction on the PCI bus is summarized in the following statements: 4285 ** �E The ATU claims the PCI read transaction when the PCI address is within the inbound 4286 ** translation window defined by ATU Inbound Base Address Register (and Inbound Upper Base 4287 ** Address Register during DACs) and Inbound Limit Register. 4288 ** �E When operating in the conventional PCI mode, when the ITQ is currently holding transaction 4289 ** information from a previous delayed read, the current transaction information is compared to 4290 ** the previous transaction information (based on the setting of the DRC Alias bit in 4291 ** Section 3.10.39, ��ATU Configuration Register - ATUCR�� on page 252). When there is a 4292 ** match and the data is in the IRQ, return the data to the master on the PCI bus. When there is a 4293 ** match and the data is not available, a Retry is signaled with no other action taken. When there 4294 ** is not a match and when the ITQ has less than eight entries, capture the transaction 4295 ** information, signal a Retry and initiate a delayed transaction. When there is not a match and 4296 ** when the ITQ is full, then signal a Retry with no other action taken. 4297 ** �X When an address parity error is detected, the address parity response defined in 4298 ** Section 3.7 is used. 4299 ** �E When operating in the conventional PCI mode, once read data is driven onto the PCI bus from 4300 ** the IRQ, it continues until one of the following is true: 4301 ** �X The initiator completes the PCI transaction. When there is data left unread in the IRQ, the 4302 ** data is flushed. 4303 ** �X An internal bus Target Abort was detected. In this case, the QWORD associated with the 4304 ** Target Abort is never entered into the IRQ, and therefore is never returned. 4305 ** �X Target Abort or a Disconnect with Data is returned in response to the Internal Bus Error. 4306 ** �X The IRQ becomes empty. In this case, the PCI interface signals a Disconnect with data to 4307 ** the initiator on the last data word available. 4308 ** �E When operating in the PCI-X mode, when ITQ is not full, the PCI address, attribute and 4309 ** command are latched into the available ITQ and a Split Response Termination is signalled to 4310 ** the initiator. 4311 ** �E When operating in the PCI-X mode, when the transaction does not cross a 1024 byte aligned 4312 ** boundary, then the ATU waits until it receives the full byte count from the internal bus target 4313 ** before returning read data by generating the split completion transaction on the PCI-X bus. 4314 ** When the read requested crosses at least one 1024 byte boundary, then ATU completes the 4315 ** transfer by returning data in 1024 byte aligned chunks. 4316 ** �E When operating in the PCI-X mode, once a split completion transaction has started, it 4317 ** continues until one of the following is true: 4318 ** �X The requester (now the target) generates a Retry Termination, or a Disconnection at Next 4319 ** ADB (when the requester is a bridge) 4320 ** �X The byte count is satisfied. 4321 ** �X An internal bus Target Abort was detected. The ATU generates a Split Completion 4322 ** Message (message class=2h - completer error, and message index=81h - target abort) to 4323 ** inform the requester about the abnormal condition. The ITQ for this transaction is flushed. 4324 ** Refer to Section 3.7.1. 4325 ** �X An internal bus Master Abort was detected. The ATU generates a Split Completion 4326 ** Message (message class=2h - completer error, and message index=80h - Master abort) to 4327 ** inform the requester about the abnormal condition. The ITQ for this transaction is flushed. 4328 ** Refer to Section 3.7.1 4329 ** �E When operating in the conventional PCI mode, when the master inserts wait states on the PCI 4330 ** bus, the ATU PCI slave interface waits with no premature disconnects. 4331 ** �E When a data parity error occurs signified by PERR# asserted from the initiator, no action is 4332 ** taken by the target interface. Refer to Section 3.7.2.5. 4333 ** �E When operating in the conventional PCI mode, when the read on the internal bus is 4334 ** target-aborted, either a target-abort or a disconnect with data is signaled to the initiator. This is 4335 ** based on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). When set, a 4336 ** target abort is used, when clear, a disconnect is used. 4337 ** �E When operating in the PCI-X mode (with the exception of the MU queue ports at offsets 40h 4338 ** and 44h), when the transaction on the internal bus resulted in a target abort, the ATU generates 4339 ** a Split Completion Message (message class=2h - completer error, and message index=81h - 4340 ** internal bus target abort) to inform the requester about the abnormal condition. For the MU 4341 ** queue ports, the ATU returns either a target abort or a single data phase disconnect depending 4342 ** on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). The ITQ for this 4343 ** transaction is flushed. Refer to Section 3.7.1. 4344 ** �E When operating in the conventional PCI mode, when the transaction on the internal bus 4345 ** resulted in a master abort, the ATU returns a target abort to inform the requester about the 4346 ** abnormal condition. The ITQ for this transaction is flushed. Refer to Section 3.7.1 4347 ** �E When operating in the PCI-X mode, when the transaction on the internal bus resulted in a 4348 ** master abort, the ATU generates a Split Completion Message (message class=2h - completer 4349 ** error, and message index=80h - internal bus master abort) to inform the requester about the 4350 ** abnormal condition. The ITQ for this transaction is flushed. Refer to Section 3.7.1. 4351 ** �E When operating in the PCI-X mode, when the Split Completion transaction completes with 4352 ** either Master-Abort or Target-Abort, the requester is indicating a failure condition that 4353 ** prevents it from accepting the completion it requested. In this case, since the Split Request 4354 ** addresses a location that has no read side effects, the completer must discard the Split 4355 ** Completion and take no further action. 4356 ** The data flow for an inbound read transaction on the internal bus is summarized in the following 4357 ** statements: 4358 ** �E The ATU internal bus master interface requests the internal bus when a PCI address appears in 4359 ** an ITQ and transaction ordering has been satisfied. When operating in the PCI-X mode the 4360 ** ATU does not use the information provided by the Relax Ordering Attribute bit. That is, ATU 4361 ** always uses conventional PCI ordering rules. 4362 ** �E Once the internal bus is granted, the internal bus master interface drives the translated address 4363 ** onto the bus and wait for IB_DEVSEL#. When a Retry is signaled, the request is repeated. 4364 ** When a master abort occurs, the transaction is considered complete and a target abort is loaded 4365 ** into the associated IRQ for return to the PCI initiator (transaction is flushed once the PCI 4366 ** master has been delivered the target abort). 4367 ** �E Once the translated address is on the bus and the transaction has been accepted, the internal 4368 ** bus target starts returning data with the assertion of IB_TRDY#. Read data is continuously 4369 ** received by the IRQ until one of the following is true: 4370 ** �X The full byte count requested by the ATU read request is received. The ATU internal bus 4371 ** initiator interface performs a initiator completion in this case. 4372 ** �X When operating in the conventional PCI mode, a Target Abort is received on the internal 4373 ** bus from the internal bus target. In this case, the transaction is aborted and the PCI side is 4374 ** informed. 4375 ** �X When operating in the PCI-X mode, a Target Abort is received on the internal bus from 4376 ** the internal bus target. In this case, the transaction is aborted. The ATU generates a Split 4377 ** Completion Message (message class=2h - completer error, and message index=81h - 4378 ** target abort) on the PCI bus to inform the requester about the abnormal condition. The 4379 ** ITQ for this transaction is flushed. 4380 ** �X When operating in the conventional PCI mode, a single data phase disconnection is 4381 ** received from the internal bus target. When the data has not been received up to the next 4382 ** QWORD boundary, the ATU internal bus master interface attempts to reacquire the bus. 4383 ** When not, the bus returns to idle. 4384 ** �X When operating in the PCI-X mode, a single data phase disconnection is received from 4385 ** the internal bus target. The ATU IB initiator interface attempts to reacquire the bus to 4386 ** obtain remaining data. 4387 ** �X When operating in the conventional PCI mode, a disconnection at Next ADB is received 4388 ** from the internal bus target. The bus returns to idle. 4389 ** �X When operating in the PCI-X mode, a disconnection at Next ADB is received from the 4390 ** internal bus target. The ATU IB initiator interface attempts to reacquire the bus to obtain 4391 ** remaining data. 4392 ** To support PCI Local Bus Specification, Revision 2.0 devices, the ATU can be programmed to 4393 ** ignore the memory read command (Memory Read, Memory Read Line, and Memory Read 4394 ** Multiple) when trying to match the current inbound read transaction with data in a DRC queue 4395 ** which was read previously (DRC on target bus). When the Read Command Alias Bit in the 4396 ** ATUCR register is set, the ATU does not distinguish the read commands on transactions. For 4397 ** example, the ATU enqueues a DRR with a Memory Read Multiple command and performs the read 4398 ** on the internal bus. Some time later, a PCI master attempts a Memory Read with the same address 4399 ** as the previous Memory Read Multiple. When the Read Command Bit is set, the ATU would return 4400 ** the read data from the DRC queue and consider the Delayed Read transaction complete. When the 4401 ** Read Command bit in the ATUCR was clear, the ATU would not return data since the PCI read 4402 ** commands did not match, only the address. 4403 ************************************************************************** 4404 */ 4405 /* 4406 ************************************************************************** 4407 ** Inbound Write Transaction 4408 **======================================================================== 4409 ** An inbound write transaction is initiated by a PCI master and is targeted at either 80331 local 4410 ** memory or a 80331 memory-mapped register. 4411 ** Data flow for an inbound write transaction on the PCI bus is summarized as: 4412 ** �E The ATU claims the PCI write transaction when the PCI address is within the inbound 4413 ** translation window defined by the ATU Inbound Base Address Register (and Inbound Upper 4414 ** Base Address Register during DACs) and Inbound Limit Register. 4415 ** �E When the IWADQ has at least one address entry available and the IWQ has at least one buffer 4416 ** available, the address is captured and the first data phase is accepted. 4417 ** �E The PCI interface continues to accept write data until one of the following is true: 4418 ** �X The initiator performs a disconnect. 4419 ** �X The transaction crosses a buffer boundary. 4420 ** �E When an address parity error is detected during the address phase of the transaction, the 4421 ** address parity error mechanisms are used. Refer to Section 3.7.1 for details of the address 4422 ** parity error response. 4423 ** �E When operating in the PCI-X mode when an attribute parity error is detected, the attribute 4424 ** parity error mechanism described in Section 3.7.1 is used. 4425 ** �E When a data parity error is detected while accepting data, the slave interface sets the 4426 ** appropriate bits based on PCI specifications. No other action is taken. Refer to Section 3.7.2.6 4427 ** for details of the inbound write data parity error response. 4428 ** Once the PCI interface places a PCI address in the IWADQ, when IWQ has received data sufficient 4429 ** to cross a buffer boundary or the master disconnects on the PCI bus, the ATUs internal bus 4430 ** interface becomes aware of the inbound write. When there are additional write transactions ahead 4431 ** in the IWQ/IWADQ, the current transaction remains posted until ordering and priority have been 4432 ** satisfied (Refer to Section 3.5.3) and the transaction is attempted on the internal bus by the ATU 4433 ** internal master interface. The ATU does not insert target wait states nor do data merging on the PCI 4434 ** interface, when operating in the PCI mode. 4435 ** In the PCI-X mode memory writes are always executed as immediate transactions, while 4436 ** configuration write transactions are processed as split transactions. The ATU generates a Split 4437 ** Completion Message, (with Message class=0h - Write Completion Class and Message index = 4438 ** 00h - Write Completion Message) once a configuration write is successfully executed. 4439 ** Also, when operating in the PCI-X mode a write sequence may contain multiple write transactions. 4440 ** The ATU handles such transactions as independent transactions. 4441 ** Data flow for the inbound write transaction on the internal bus is summarized as: 4442 ** �E The ATU internal bus master requests the internal bus when IWADQ has at least one entry 4443 ** with associated data in the IWQ. 4444 ** �E When the internal bus is granted, the internal bus master interface initiates the write 4445 ** transaction by driving the translated address onto the internal bus. For details on inbound 4446 ** address translation. 4447 ** �E When IB_DEVSEL# is not returned, a master abort condition is signaled on the internal bus. 4448 ** The current transaction is flushed from the queue and SERR# may be asserted on the PCI 4449 ** interface. 4450 ** �E The ATU initiator interface asserts IB_REQ64# to attempt a 64-bit transfer. When 4451 ** IB_ACK64# is not returned, a 32-bit transfer is used. Transfers of less than 64-bits use the 4452 ** IB_C/BE[7:0]# to mask the bytes not written in the 64-bit data phase. Write data is transferred 4453 ** from the IWQ to the internal bus when data is available and the internal bus interface retains 4454 ** internal bus ownership. 4455 ** �E The internal bus interface stops transferring data from the current transaction to the internal 4456 ** bus when one of the following conditions becomes true: 4457 ** �X The internal bus initiator interface loses bus ownership. The ATU internal initiator 4458 ** terminates the transfer (initiator disconnection) at the next ADB (for the internal bus ADB 4459 ** is defined as a naturally aligned 128-byte boundary) and attempt to reacquire the bus to 4460 ** complete the delivery of remaining data using the same sequence ID but with the 4461 ** modified starting address and byte count. 4462 ** �X A Disconnect at Next ADB is signaled on the internal bus from the internal target. When 4463 ** the transaction in the IWQ completes at that ADB, the initiator returns to idle. When the 4464 ** transaction in the IWQ is not complete, the initiator attempts to reacquire the bus to 4465 ** complete the delivery of remaining data using the same sequence ID but with the 4466 ** modified starting address and byte count. 4467 ** �X A Single Data Phase Disconnect is signaled on the internal bus from the internal target. 4468 ** When the transaction in the IWQ needs only a single data phase, the master returns to idle. 4469 ** When the transaction in the IWQ is not complete, the initiator attempts to reacquire the 4470 ** bus to complete the delivery of remaining data using the same sequence ID but with the 4471 ** modified starting address and byte count. 4472 ** �X The data from the current transaction has completed (satisfaction of byte count). An 4473 ** initiator termination is performed and the bus returns to idle. 4474 ** �X A Master Abort is signaled on the internal bus. SERR# may be asserted on the PCI bus. 4475 ** Data is flushed from the IWQ. 4476 ***************************************************************** 4477 */ 4478 4479 /* 4480 ************************************************************************** 4481 ** Inbound Read Completions Data Parity Errors 4482 **======================================================================== 4483 ** As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode. 4484 ** When as the completer of a Split Read Request the ATU observes PERR# assertion during the split 4485 ** completion transaction, the ATU attempts to complete the transaction normally and no further 4486 ** action is taken. 4487 ************************************************************************** 4488 */ 4489 4490 /* 4491 ************************************************************************** 4492 ** Inbound Configuration Write Completion Message Data Parity Errors 4493 **======================================================================== 4494 ** As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode. 4495 ** When as the completer of a Configuration (Split) Write Request the ATU observes PERR# 4496 ** assertion during the split completion transaction, the ATU attempts to complete the transaction 4497 ** normally and no further action is taken. 4498 ************************************************************************** 4499 */ 4500 4501 /* 4502 ************************************************************************** 4503 ** Inbound Read Request Data Parity Errors 4504 **===================== Immediate Data Transfer ========================== 4505 ** As a target, the ATU may encounter this error when operating in the Conventional PCI or PCI-X modes. 4506 ** Inbound read data parity errors occur when read data delivered from the IRQ is detected as having 4507 ** bad parity by the initiator of the transaction who is receiving the data. The initiator may optionally 4508 ** report the error to the system by asserting PERR#. As a target device in this scenario, no action is 4509 ** required and no error bits are set. 4510 **=====================Split Response Termination========================= 4511 ** As a target, the ATU may encounter this error when operating in the PCI-X mode. 4512 ** Inbound read data parity errors occur during the Split Response Termination. The initiator may 4513 ** optionally report the error to the system by asserting PERR#. As a target device in this scenario, no 4514 ** action is required and no error bits are set. 4515 ************************************************************************** 4516 */ 4517 4518 /* 4519 ************************************************************************** 4520 ** Inbound Write Request Data Parity Errors 4521 **======================================================================== 4522 ** As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes. 4523 ** Data parity errors occurring during write operations received by the ATU may assert PERR# on 4524 ** the PCI Bus. When an error occurs, the ATU continues accepting data until the initiator of the write 4525 ** transaction completes or a queue fill condition is reached. Specifically, the following actions with 4526 ** the given constraints are taken by the ATU: 4527 ** �E PERR# is asserted two clocks cycles (three clock cycles when operating in the PCI-X mode) 4528 ** following the data phase in which the data parity error is detected on the bus. This is only 4529 ** done when the Parity Error Response bit in the ATUCMD is set. 4530 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4531 ** actions is taken: 4532 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4533 ** Detected Parity Error bit in the ATUISR. When set, no action. 4534 *************************************************************************** 4535 */ 4536 4537 /* 4538 *************************************************************************** 4539 ** Inbound Configuration Write Request 4540 ** ===================================================================== 4541 ** As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes. 4542 ** =============================================== 4543 ** Conventional PCI Mode 4544 ** =============================================== 4545 ** To allow for correct data parity calculations for delayed write transactions, the ATU delays the 4546 ** assertion of STOP# (signalling a Retry) until PAR is driven by the master. A parity error during a 4547 ** delayed write transaction (inbound configuration write cycle) can occur in any of the following 4548 ** parts of the transactions: 4549 ** �E During the initial Delayed Write Request cycle on the PCI bus when the ATU latches the 4550 ** address/command and data for delayed delivery to the internal configuration register. 4551 ** �E During the Delayed Write Completion cycle on the PCI bus when the ATU delivers the status 4552 ** of the operation back to the original master. 4553 ** The 80331 ATU PCI interface has the following responses to a delayed write parity error for 4554 ** inbound transactions during Delayed Write Request cycles with the given constraints: 4555 ** �E When the Parity Error Response bit in the ATUCMD is set, the ATU asserts TRDY# 4556 ** (disconnects with data) and two clock cycles later asserts PERR# notifying the initiator of the 4557 ** parity error. The delayed write cycle is not enqueued and forwarded to the internal bus. 4558 ** When the Parity Error Response bit in the ATUCMD is cleared, the ATU retries the 4559 ** transaction by asserting STOP# and enqueues the Delayed Write Request cycle to be 4560 ** forwarded to the internal bus. PERR# is not asserted. 4561 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4562 ** actions is taken: 4563 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4564 ** Detected Parity Error bit in the ATUISR. When set, no action. 4565 ** For the original write transaction to be completed, the initiator retries the transaction on the PCI 4566 ** bus and the ATU returns the status from the internal bus, completing the transaction. 4567 ** For the Delayed Write Completion transaction on the PCI bus where a data parity error occurs and 4568 ** therefore does not agree with the status being returned from the internal bus (i.e. status being 4569 ** returned is normal completion) the ATU performs the following actions with the given constraints: 4570 ** �E When the Parity Error Response Bit is set in the ATUCMD, the ATU asserts TRDY# 4571 ** (disconnects with data) and two clocks later asserts PERR#. The Delayed Completion cycle in 4572 ** the IDWQ remains since the data of retried command did not match the data within the queue. 4573 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4574 ** actions is taken: 4575 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4576 ** Detected Parity Error bit in the ATUISR. When set, no action. 4577 ** =================================================== 4578 ** PCI-X Mode 4579 ** =================================================== 4580 ** Data parity errors occurring during configuration write operations received by the ATU may cause 4581 ** PERR# assertion and delivery of a Split Completion Error Message on the PCI Bus. When an error 4582 ** occurs, the ATU accepts the write data and complete with a Split Response Termination. 4583 ** Specifically, the following actions with the given constraints are then taken by the ATU: 4584 ** �E When the Parity Error Response bit in the ATUCMD is set, PERR# is asserted three clocks 4585 ** cycles following the Split Response Termination in which the data parity error is detected on 4586 ** the bus. When the ATU asserts PERR#, additional actions is taken: 4587 ** �X A Split Write Data Parity Error message (with message class=2h - completer error and 4588 ** message index=01h - Split Write Data Parity Error) is initiated by the ATU on the PCI bus 4589 ** that addresses the requester of the configuration write. 4590 ** �X When the Initiated Split Completion Error Message Interrupt Mask in the ATUIMR is 4591 ** clear, set the Initiated Split Completion Error Message bit in the ATUISR. When set, no 4592 ** action. 4593 ** �X The Split Write Request is not enqueued and forwarded to the internal bus. 4594 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4595 ** actions is taken: 4596 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4597 ** Detected Parity Error bit in the ATUISR. When set, no action. 4598 ** 4599 *************************************************************************** 4600 */ 4601 4602 /* 4603 *************************************************************************** 4604 ** Split Completion Messages 4605 ** ======================================================================= 4606 ** As a target, the ATU may encounter this error when operating in the PCI-X mode. 4607 ** Data parity errors occurring during Split Completion Messages claimed by the ATU may assert 4608 ** PERR# (when enabled) or SERR# (when enabled) on the PCI Bus. When an error occurs, the 4609 ** ATU accepts the data and complete normally. Specifically, the following actions with the given 4610 ** constraints are taken by the ATU: 4611 ** �E PERR# is asserted three clocks cycles following the data phase in which the data parity error 4612 ** is detected on the bus. This is only done when the Parity Error Response bit in the ATUCMD 4613 ** is set. When the ATU asserts PERR#, additional actions is taken: 4614 ** �X The Master Parity Error bit in the ATUSR is set. 4615 ** �X When the ATU PCI Master Parity Error Interrupt Mask Bit in the ATUIMR is clear, set the 4616 ** PCI Master Parity Error bit in the ATUISR. When set, no action. 4617 ** �X When the SERR# Enable bit in the ATUCMD is set, and the Data Parity Error Recover 4618 ** Enable bit in the PCIXCMD register is clear, assert SERR#; otherwise no action is taken. 4619 ** When the ATU asserts SERR#, additional actions is taken: 4620 ** Set the SERR# Asserted bit in the ATUSR. 4621 ** When the ATU SERR# Asserted Interrupt Mask Bit in the ATUIMR is clear, set the 4622 ** SERR# Asserted bit in the ATUISR. When set, no action. 4623 ** When the ATU SERR# Detected Interrupt Enable Bit in the ATUCR is set, set the 4624 ** SERR# Detected bit in the ATUISR. When clear, no action. 4625 ** �E When the SCE bit (Split Completion Error -- bit 30 of the Completer Attributes) is set during 4626 ** the Attribute phase, the Received Split Completion Error Message bit in the PCIXSR is set. 4627 ** When the ATU sets this bit, additional actions is taken: 4628 ** �X When the ATU Received Split Completion Error Message Interrupt Mask bit in the 4629 ** ATUIMR is clear, set the Received Split Completion Error Message bit in the ATUISR. 4630 ** When set, no action. 4631 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4632 ** actions is taken: 4633 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4634 ** Detected Parity Error bit in the ATUISR. When set, no action. 4635 ** �E The transaction associated with the Split Completion Message is discarded. 4636 ** �E When the discarded transaction was a read, a completion error message (with message 4637 ** class=2h - completer error and message index=82h - PCI bus read parity error) is generated on 4638 ** the internal bus of the 80331. 4639 ***************************************************************************** 4640 */ 4641 4642 /* 4643 ****************************************************************************************************** 4644 ** Messaging Unit (MU) of the Intel R 80331 I/O processor (80331) 4645 ** ================================================================================================== 4646 ** The Messaging Unit (MU) transfers data between the PCI system and the 80331 4647 ** notifies the respective system when new data arrives. 4648 ** The PCI window for messaging transactions is always the first 4 Kbytes of the inbound translation. 4649 ** window defined by: 4650 ** 1.Inbound ATU Base Address Register 0 (IABAR0) 4651 ** 2.Inbound ATU Limit Register 0 (IALR0) 4652 ** All of the Messaging Unit errors are reported in the same manner as ATU errors. 4653 ** Error conditions and status can be found in : 4654 ** 1.ATUSR 4655 ** 2.ATUISR 4656 **==================================================================================================== 4657 ** Mechanism Quantity Assert PCI Interrupt Signals Generate I/O Processor Interrupt 4658 **---------------------------------------------------------------------------------------------------- 4659 ** Message Registers 2 Inbound Optional Optional 4660 ** 2 Outbound 4661 **---------------------------------------------------------------------------------------------------- 4662 ** Doorbell Registers 1 Inbound Optional Optional 4663 ** 1 Outbound 4664 **---------------------------------------------------------------------------------------------------- 4665 ** Circular Queues 4 Circular Queues Under certain conditions Under certain conditions 4666 **---------------------------------------------------------------------------------------------------- 4667 ** Index Registers 1004 32-bit Memory Locations No Optional 4668 **==================================================================================================== 4669 ** PCI Memory Map: First 4 Kbytes of the ATU Inbound PCI Address Space 4670 **==================================================================================================== 4671 ** 0000H Reserved 4672 ** 0004H Reserved 4673 ** 0008H Reserved 4674 ** 000CH Reserved 4675 **------------------------------------------------------------------------ 4676 ** 0010H Inbound Message Register 0 ] 4677 ** 0014H Inbound Message Register 1 ] 4678 ** 0018H Outbound Message Register 0 ] 4679 ** 001CH Outbound Message Register 1 ] 4 Message Registers 4680 **------------------------------------------------------------------------ 4681 ** 0020H Inbound Doorbell Register ] 4682 ** 0024H Inbound Interrupt Status Register ] 4683 ** 0028H Inbound Interrupt Mask Register ] 4684 ** 002CH Outbound Doorbell Register ] 4685 ** 0030H Outbound Interrupt Status Register ] 4686 ** 0034H Outbound Interrupt Mask Register ] 2 Doorbell Registers and 4 Interrupt Registers 4687 **------------------------------------------------------------------------ 4688 ** 0038H Reserved 4689 ** 003CH Reserved 4690 **------------------------------------------------------------------------ 4691 ** 0040H Inbound Queue Port ] 4692 ** 0044H Outbound Queue Port ] 2 Queue Ports 4693 **------------------------------------------------------------------------ 4694 ** 0048H Reserved 4695 ** 004CH Reserved 4696 **------------------------------------------------------------------------ 4697 ** 0050H ] 4698 ** : ] 4699 ** : Intel Xscale Microarchitecture Local Memory ] 4700 ** : ] 4701 ** 0FFCH ] 1004 Index Registers 4702 ******************************************************************************* 4703 */ 4704 /* 4705 ***************************************************************************** 4706 ** Theory of MU Operation 4707 ***************************************************************************** 4708 **-------------------- 4709 ** inbound_msgaddr0: 4710 ** inbound_msgaddr1: 4711 ** outbound_msgaddr0: 4712 ** outbound_msgaddr1: 4713 ** . The MU has four independent messaging mechanisms. 4714 ** There are four Message Registers that are similar to a combination of mailbox and doorbell registers. 4715 ** Each holds a 32-bit value and generates an interrupt when written. 4716 **-------------------- 4717 ** inbound_doorbell: 4718 ** outbound_doorbell: 4719 ** . The two Doorbell Registers support software interrupts. 4720 ** When a bit is set in a Doorbell Register, an interrupt is generated. 4721 **-------------------- 4722 ** inbound_queueport: 4723 ** outbound_queueport: 4724 ** 4725 ** 4726 ** . The Circular Queues support a message passing scheme that uses 4 circular queues. 4727 ** The 4 circular queues are implemented in 80331 local memory. 4728 ** Two queues are used for inbound messages and two are used for outbound messages. 4729 ** Interrupts may be generated when the queue is written. 4730 **-------------------- 4731 ** local_buffer 0x0050 ....0x0FFF 4732 ** . The Index Registers use a portion of the 80331 local memory to implement a large set of message registers. 4733 ** When one of the Index Registers is written, an interrupt is generated and the address of the register written is captured. 4734 ** Interrupt status for all interrupts is recorded in the Inbound Interrupt Status Register and the Outbound Interrupt Status Register. 4735 ** Each interrupt generated by the Messaging Unit can be masked. 4736 **-------------------- 4737 ** . Multi-DWORD PCI burst accesses are not supported by the Messaging Unit, 4738 ** with the exception of Multi-DWORD reads to the index registers. 4739 ** In Conventional mode: the MU terminates Multi-DWORD PCI transactions 4740 ** (other than index register reads) with a disconnect at the next Qword boundary, with the exception of queue ports. 4741 ** In PCI-X mode : the MU terminates a Multi-DWORD PCI read transaction with a Split Response 4742 ** and the data is returned through split completion transaction(s). 4743 ** however, when the burst request crosses into or through the range of offsets 40h to 4Ch 4744 ** (e.g., this includes the queue ports) the transaction is signaled target-abort immediately on the PCI bus. 4745 ** In PCI-X mode, Multi-DWORD PCI writes is signaled a Single-Data-Phase Disconnect 4746 ** which means that no data beyond the first Qword (Dword when the MU does not assert P_ACK64#) is written. 4747 **-------------------- 4748 ** . All registers needed to configure and control the Messaging Unit are memory-mapped registers. 4749 ** The MU uses the first 4 Kbytes of the inbound translation window in the Address Translation Unit (ATU). 4750 ** This PCI address window is used for PCI transactions that access the 80331 local memory. 4751 ** The PCI address of the inbound translation window is contained in the Inbound ATU Base Address Register. 4752 **-------------------- 4753 ** . From the PCI perspective, the Messaging Unit is part of the Address Translation Unit. 4754 ** The Messaging Unit uses the PCI configuration registers of the ATU for control and status information. 4755 ** The Messaging Unit must observe all PCI control bits in the ATU Command Register and ATU Configuration Register. 4756 ** The Messaging Unit reports all PCI errors in the ATU Status Register. 4757 **-------------------- 4758 ** . Parts of the Messaging Unit can be accessed as a 64-bit PCI device. 4759 ** The register interface, message registers, doorbell registers, 4760 ** and index registers returns a P_ACK64# in response to a P_REQ64# on the PCI interface. 4761 ** Up to 1 Qword of data can be read or written per transaction (except Index Register reads). 4762 ** The Inbound and Outbound Queue Ports are always 32-bit addresses and the MU does not assert P_ACK64# to offsets 40H and 44H. 4763 ************************************************************************** 4764 */ 4765 /* 4766 ************************************************************************** 4767 ** Message Registers 4768 ** ============================== 4769 ** . Messages can be sent and received by the 80331 through the use of the Message Registers. 4770 ** . When written, the message registers may cause an interrupt to be generated to either the Intel XScale core or the host processor. 4771 ** . Inbound messages are sent by the host processor and received by the 80331. 4772 ** Outbound messages are sent by the 80331 and received by the host processor. 4773 ** . The interrupt status for outbound messages is recorded in the Outbound Interrupt Status Register. 4774 ** Interrupt status for inbound messages is recorded in the Inbound Interrupt Status Register. 4775 ** 4776 ** Inbound Messages: 4777 ** ----------------- 4778 ** . When an inbound message register is written by an external PCI agent, an interrupt may be generated to the Intel XScale core. 4779 ** . The interrupt may be masked by the mask bits in the Inbound Interrupt Mask Register. 4780 ** . The Intel XScale core interrupt is recorded in the Inbound Interrupt Status Register. 4781 ** The interrupt causes the Inbound Message Interrupt bit to be set in the Inbound Interrupt Status Register. 4782 ** This is a Read/Clear bit that is set by the MU hardware and cleared by software. 4783 ** The interrupt is cleared when the Intel XScale core writes a value of 4784 ** 1 to the Inbound Message Interrupt bit in the Inbound Interrupt Status Register. 4785 ** ------------------------------------------------------------------------ 4786 ** Inbound Message Register - IMRx 4787 ** 4788 ** . There are two Inbound Message Registers: IMR0 and IMR1. 4789 ** . When the IMR register is written, an interrupt to the Intel XScale core may be generated. 4790 ** The interrupt is recorded in the Inbound Interrupt Status Register and may be masked 4791 ** by the Inbound Message Interrupt Mask bit in the Inbound Interrupt Mask Register. 4792 ** ----------------------------------------------------------------- 4793 ** Bit Default Description 4794 ** 31:00 0000 0000H Inbound Message - This is a 32-bit message written by an external PCI agent. 4795 ** When written, an interrupt to the Intel XScale core may be generated. 4796 ************************************************************************** 4797 */ 4798 #define ARCMSR_MU_INBOUND_MESSAGE_REG0 0x10 /*dword 0x13,0x12,0x11,0x10*/ 4799 #define ARCMSR_MU_INBOUND_MESSAGE_REG1 0x14 /*dword 0x17,0x16,0x15,0x14*/ 4800 /* 4801 ************************************************************************** 4802 ** Outbound Message Register - OMRx 4803 ** -------------------------------- 4804 ** There are two Outbound Message Registers: OMR0 and OMR1. When the OMR register is 4805 ** written, a PCI interrupt may be generated. The interrupt is recorded in the Outbound Interrupt 4806 ** Status Register and may be masked by the Outbound Message Interrupt Mask bit in the Outbound 4807 ** Interrupt Mask Register. 4808 ** 4809 ** Bit Default Description 4810 ** 31:00 00000000H Outbound Message - This is 32-bit message written by the Intel XScale core. When written, an 4811 ** interrupt may be generated on the PCI Interrupt pin determined by the ATU Interrupt Pin Register. 4812 ************************************************************************** 4813 */ 4814 #define ARCMSR_MU_OUTBOUND_MESSAGE_REG0 0x18 /*dword 0x1B,0x1A,0x19,0x18*/ 4815 #define ARCMSR_MU_OUTBOUND_MESSAGE_REG1 0x1C /*dword 0x1F,0x1E,0x1D,0x1C*/ 4816 /* 4817 ************************************************************************** 4818 ** Doorbell Registers 4819 ** ============================== 4820 ** There are two Doorbell Registers: 4821 ** Inbound Doorbell Register 4822 ** Outbound Doorbell Register 4823 ** The Inbound Doorbell Register allows external PCI agents to generate interrupts to the Intel R XScale core. 4824 ** The Outbound Doorbell Register allows the Intel R XScale core to generate a PCI interrupt. 4825 ** Both Doorbell Registers may generate interrupts whenever a bit in the register is set. 4826 ** 4827 ** Inbound Doorbells: 4828 ** ------------------ 4829 ** . When the Inbound Doorbell Register is written by an external PCI agent, an interrupt may be generated to the Intel R XScale core. 4830 ** An interrupt is generated when any of the bits in the doorbell register is written to a value of 1. 4831 ** Writing a value of 0 to any bit does not change the value of that bit and does not cause an interrupt to be generated. 4832 ** . Once a bit is set in the Inbound Doorbell Register, it cannot be cleared by any external PCI agent. 4833 ** The interrupt is recorded in the Inbound Interrupt Status Register. 4834 ** . The interrupt may be masked by the Inbound Doorbell Interrupt mask bit in the Inbound Interrupt Mask Register. 4835 ** When the mask bit is set for a particular bit, no interrupt is generated for that bit. 4836 ** The Inbound Interrupt Mask Register affects only the generation of the normal messaging unit interrupt 4837 ** and not the values written to the Inbound Doorbell Register. 4838 ** One bit in the Inbound Doorbell Register is reserved for an Error Doorbell interrupt. 4839 ** . The interrupt is cleared when the Intel R XScale core writes a value of 1 to the bits in the Inbound Doorbell Register that are set. 4840 ** Writing a value of 0 to any bit does not change the value of that bit and does not clear the interrupt. 4841 ** ------------------------------------------------------------------------ 4842 ** Inbound Doorbell Register - IDR 4843 ** 4844 ** . The Inbound Doorbell Register (IDR) is used to generate interrupts to the Intel XScale core. 4845 ** . Bit 31 is reserved for generating an Error Doorbell interrupt. 4846 ** When bit 31 is set, an Error interrupt may be generated to the Intel XScale core. 4847 ** All other bits, when set, cause the Normal Messaging Unit interrupt line of the Intel XScale core to be asserted, 4848 ** when the interrupt is not masked by the Inbound Doorbell Interrupt Mask bit in the Inbound Interrupt Mask Register. 4849 ** The bits in the IDR register can only be set by an external PCI agent and can only be cleared by the Intel XScale core. 4850 ** ------------------------------------------------------------------------ 4851 ** Bit Default Description 4852 ** 31 0 2 Error Interrupt - Generate an Error Interrupt to the Intel XScale core. 4853 ** 30:00 00000000H Normal Interrupt - When any bit is set, generate a Normal interrupt to the Intel XScale core. 4854 ** When all bits are clear, do not generate a Normal Interrupt. 4855 ************************************************************************** 4856 */ 4857 #define ARCMSR_MU_INBOUND_DOORBELL_REG 0x20 /*dword 0x23,0x22,0x21,0x20*/ 4858 /* 4859 ************************************************************************** 4860 ** Inbound Interrupt Status Register - IISR 4861 ** 4862 ** . The Inbound Interrupt Status Register (IISR) contains hardware interrupt status. 4863 ** It records the status of Intel XScale core interrupts generated by the Message Registers, Doorbell Registers, and the Circular Queues. 4864 ** All interrupts are routed to the Normal Messaging Unit interrupt input of the Intel XScale core, 4865 ** except for the Error Doorbell Interrupt and the Outbound Free Queue Full interrupt; 4866 ** these two are routed to the Messaging Unit Error interrupt input. 4867 ** The generation of interrupts recorded in the Inbound Interrupt Status Register 4868 ** may be masked by setting the corresponding bit in the Inbound Interrupt Mask Register. 4869 ** Some of the bits in this register are Read Only. 4870 ** For those bits, the interrupt must be cleared through another register. 4871 ** 4872 ** Bit Default Description 4873 ** 31:07 0000000H 0 2 Reserved 4874 ** 06 0 2 Index Register Interrupt - This bit is set by the MU hardware 4875 ** when an Index Register has been written after a PCI transaction. 4876 ** 05 0 2 Outbound Free Queue Full Interrupt - This bit is set 4877 ** when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full. 4878 ** An Error interrupt is generated for this condition. 4879 ** 04 0 2 Inbound Post Queue Interrupt - This bit is set by the MU hardware when the Inbound Post Queue has been written. 4880 ** Once cleared, an interrupt does NOT be generated 4881 ** when the head and tail pointers remain unequal (i.e. queue status is Not Empty). 4882 ** Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared, 4883 ** software must retain the information that the Inbound Post queue status is not empty. 4884 ** NOTE: This interrupt is provided with dedicated support in the 80331 Interrupt Controller. 4885 ** 03 0 2 Error Doorbell Interrupt - This bit is set when the Error Interrupt of the Inbound Doorbell Register is set. 4886 ** To clear this bit (and the interrupt), the Error Interrupt bit of the Inbound Doorbell Register must be clear. 4887 ** 02 0 2 Inbound Doorbell Interrupt - This bit is set when at least one 4888 ** Normal Interrupt bit in the Inbound Doorbell Register is set. 4889 ** To clear this bit (and the interrupt), the Normal Interrupt bits in the Inbound Doorbell Register must all be clear. 4890 ** 01 0 2 Inbound Message 1 Interrupt - This bit is set by the MU hardware when the Inbound Message 1 Register has been written. 4891 ** 00 0 2 Inbound Message 0 Interrupt - This bit is set by the MU hardware when the Inbound Message 0 Register has been written. 4892 ************************************************************************** 4893 */ 4894 #define ARCMSR_MU_INBOUND_INTERRUPT_STATUS_REG 0x24 /*dword 0x27,0x26,0x25,0x24*/ 4895 #define ARCMSR_MU_INBOUND_INDEX_INT 0x40 4896 #define ARCMSR_MU_INBOUND_QUEUEFULL_INT 0x20 4897 #define ARCMSR_MU_INBOUND_POSTQUEUE_INT 0x10 4898 #define ARCMSR_MU_INBOUND_ERROR_DOORBELL_INT 0x08 4899 #define ARCMSR_MU_INBOUND_DOORBELL_INT 0x04 4900 #define ARCMSR_MU_INBOUND_MESSAGE1_INT 0x02 4901 #define ARCMSR_MU_INBOUND_MESSAGE0_INT 0x01 4902 /* 4903 ************************************************************************** 4904 ** Inbound Interrupt Mask Register - IIMR 4905 ** 4906 ** . The Inbound Interrupt Mask Register (IIMR) provides the ability to mask Intel XScale core interrupts generated by the Messaging Unit. 4907 ** Each bit in the Mask register corresponds to an interrupt bit in the Inbound Interrupt Status Register. 4908 ** Setting or clearing bits in this register does not affect the Inbound Interrupt Status Register. 4909 ** They only affect the generation of the Intel XScale core interrupt. 4910 ** ------------------------------------------------------------------------ 4911 ** Bit Default Description 4912 ** 31:07 000000H 0 2 Reserved 4913 ** 06 0 2 Index Register Interrupt Mask - When set, this bit masks the interrupt generated by the MU hardware 4914 ** when an Index Register has been written after a PCI transaction. 4915 ** 05 0 2 Outbound Free Queue Full Interrupt Mask - When set, this bit masks the Error interrupt generated 4916 ** when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full. 4917 ** 04 0 2 Inbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated 4918 ** by the MU hardware when the Inbound Post Queue has been written. 4919 ** 03 0 2 Error Doorbell Interrupt Mask - When set, this bit masks the Error Interrupt 4920 ** when the Error Interrupt bit of the Inbound Doorbell Register is set. 4921 ** 02 0 2 Inbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated 4922 ** when at least one Normal Interrupt bit in the Inbound Doorbell Register is set. 4923 ** 01 0 2 Inbound Message 1 Interrupt Mask - When set, this bit masks the Inbound Message 1 4924 ** Interrupt generated by a write to the Inbound Message 1 Register. 4925 ** 00 0 2 Inbound Message 0 Interrupt Mask - When set, 4926 ** this bit masks the Inbound Message 0 Interrupt generated by a write to the Inbound Message 0 Register. 4927 ************************************************************************** 4928 */ 4929 #define ARCMSR_MU_INBOUND_INTERRUPT_MASK_REG 0x28 /*dword 0x2B,0x2A,0x29,0x28*/ 4930 #define ARCMSR_MU_INBOUND_INDEX_INTMASKENABLE 0x40 4931 #define ARCMSR_MU_INBOUND_QUEUEFULL_INTMASKENABLE 0x20 4932 #define ARCMSR_MU_INBOUND_POSTQUEUE_INTMASKENABLE 0x10 4933 #define ARCMSR_MU_INBOUND_DOORBELL_ERROR_INTMASKENABLE 0x08 4934 #define ARCMSR_MU_INBOUND_DOORBELL_INTMASKENABLE 0x04 4935 #define ARCMSR_MU_INBOUND_MESSAGE1_INTMASKENABLE 0x02 4936 #define ARCMSR_MU_INBOUND_MESSAGE0_INTMASKENABLE 0x01 4937 /* 4938 ************************************************************************** 4939 ** Outbound Doorbell Register - ODR 4940 ** 4941 ** The Outbound Doorbell Register (ODR) allows software interrupt generation. It allows the Intel 4942 ** XScale core to generate PCI interrupts to the host processor by writing to this register. The 4943 ** generation of PCI interrupts through the Outbound Doorbell Register may be masked by setting the 4944 ** Outbound Doorbell Interrupt Mask bit in the Outbound Interrupt Mask Register. 4945 ** The Software Interrupt bits in this register can only be set by the Intel XScale core and can only 4946 ** be cleared by an external PCI agent. 4947 ** ---------------------------------------------------------------------- 4948 ** Bit Default Description 4949 ** 31 0 2 Reserved 4950 ** 30 0 2 Reserved. 4951 ** 29 0 2 Reserved 4952 ** 28 0000 0000H PCI Interrupt - When set, this bit causes the P_INTC# interrupt output 4953 ** (P_INTA# with BRG_EN and ARB_EN straps low) 4954 ** signal to be asserted or a Message-signaled Interrupt is generated (when enabled). 4955 ** When this bit is cleared, the P_INTC# interrupt output 4956 ** (P_INTA# with BRG_EN and ARB_EN straps low) 4957 ** signal is deasserted. 4958 ** 27:00 000 0000H Software Interrupts - When any bit is set the P_INTC# interrupt output 4959 ** (P_INTA# with BRG_EN and ARB_EN straps low) 4960 ** signal is asserted or a Message-signaled Interrupt is generated (when enabled). 4961 ** When all bits are cleared, the P_INTC# interrupt output (P_INTA# with BRG_EN and ARB_EN straps low) 4962 ** signal is deasserted. 4963 ************************************************************************** 4964 */ 4965 #define ARCMSR_MU_OUTBOUND_DOORBELL_REG 0x2C /*dword 0x2F,0x2E,0x2D,0x2C*/ 4966 /* 4967 ************************************************************************** 4968 ** Outbound Interrupt Status Register - OISR 4969 ** 4970 ** The Outbound Interrupt Status Register (OISR) contains hardware interrupt status. It records the 4971 ** status of PCI interrupts generated by the Message Registers, Doorbell Registers, and the Circular 4972 ** Queues. The generation of PCI interrupts recorded in the Outbound Interrupt Status Register may 4973 ** be masked by setting the corresponding bit in the Outbound Interrupt Mask Register. Some of the 4974 ** bits in this register are Read Only. For those bits, the interrupt must be cleared through another 4975 ** register. 4976 ** ---------------------------------------------------------------------- 4977 ** Bit Default Description 4978 ** 31:05 000000H 000 2 Reserved 4979 ** 04 0 2 PCI Interrupt - This bit is set when the PCI Interrupt bit (bit 28) is set in the Outbound Doorbell Register. 4980 ** To clear this bit (and the interrupt), the PCI Interrupt bit must be cleared. 4981 ** 03 0 2 Outbound Post Queue Interrupt - This bit is set when data in the prefetch buffer is valid. This bit is 4982 ** cleared when any prefetch data has been read from the Outbound Queue Port. 4983 ** 02 0 2 Outbound Doorbell Interrupt - This bit is set when at least one Software Interrupt bit in the Outbound 4984 ** Doorbell Register is set. To clear this bit (and the interrupt), the Software Interrupt bits in the Outbound 4985 ** Doorbell Register must all be clear. 4986 ** 01 0 2 Outbound Message 1 Interrupt - This bit is set by the MU when the Outbound Message 1 Register is 4987 ** written. Clearing this bit clears the interrupt. 4988 ** 00 0 2 Outbound Message 0 Interrupt - This bit is set by the MU when the Outbound Message 0 Register is 4989 ** written. Clearing this bit clears the interrupt. 4990 ************************************************************************** 4991 */ 4992 #define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30 /*dword 0x33,0x32,0x31,0x30*/ 4993 #define ARCMSR_MU_OUTBOUND_PCI_INT 0x10 4994 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08 4995 #define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04 4996 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02 4997 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01 4998 /* 4999 ************************************************************************** 5000 ** Outbound Interrupt Mask Register - OIMR 5001 ** The Outbound Interrupt Mask Register (OIMR) provides the ability to mask outbound PCI 5002 ** interrupts generated by the Messaging Unit. Each bit in the mask register corresponds to a 5003 ** hardware interrupt bit in the Outbound Interrupt Status Register. When the bit is set, the PCI 5004 ** interrupt is not generated. When the bit is clear, the interrupt is allowed to be generated. 5005 ** Setting or clearing bits in this register does not affect the Outbound Interrupt Status Register. They 5006 ** only affect the generation of the PCI interrupt. 5007 ** ---------------------------------------------------------------------- 5008 ** Bit Default Description 5009 ** 31:05 000000H Reserved 5010 ** 04 0 2 PCI Interrupt Mask - When set, this bit masks the interrupt generation when the PCI Interrupt bit (bit 28) 5011 ** in the Outbound Doorbell Register is set. 5012 ** 03 0 2 Outbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated when data in 5013 ** the prefetch buffer is valid. 5014 ** 02 0 2 Outbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated by the Outbound 5015 ** Doorbell Register. 5016 ** 01 0 2 Outbound Message 1 Interrupt Mask - When set, this bit masks the Outbound Message 1 Interrupt 5017 ** generated by a write to the Outbound Message 1 Register. 5018 ** 00 0 2 Outbound Message 0 Interrupt Mask- When set, this bit masks the Outbound Message 0 Interrupt 5019 ** generated by a write to the Outbound Message 0 Register. 5020 ************************************************************************** 5021 */ 5022 #define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34 /*dword 0x37,0x36,0x35,0x34*/ 5023 #define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10 5024 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08 5025 #define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04 5026 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02 5027 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01 5028 #define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F 5029 /* 5030 ************************************************************************** 5031 ** 5032 ************************************************************************** 5033 */ 5034 #define ARCMSR_MU_INBOUND_QUEUE_PORT_REG 0x40 /*dword 0x43,0x42,0x41,0x40*/ 5035 #define ARCMSR_MU_OUTBOUND_QUEUE_PORT_REG 0x44 /*dword 0x47,0x46,0x45,0x44*/ 5036 /* 5037 ************************************************************************** 5038 ** Circular Queues 5039 ** ====================================================================== 5040 ** The MU implements four circular queues. There are 2 inbound queues and 2 outbound queues. In 5041 ** this case, inbound and outbound refer to the direction of the flow of posted messages. 5042 ** Inbound messages are either: 5043 ** �E posted messages by other processors for the Intel XScale core to process or 5044 ** �E free (or empty) messages that can be reused by other processors. 5045 ** Outbound messages are either: 5046 ** �E posted messages by the Intel XScale core for other processors to process or 5047 ** �E free (or empty) messages that can be reused by the Intel XScale core. 5048 ** Therefore, free inbound messages flow away from the 80331 and free outbound messages flow toward the 80331. 5049 ** The four Circular Queues are used to pass messages in the following manner. 5050 ** . The two inbound queues are used to handle inbound messages 5051 ** and the two outbound queues are used to handle outbound messages. 5052 ** . One of the inbound queues is designated the Free queue and it contains inbound free messages. 5053 ** The other inbound queue is designated the Post queue and it contains inbound posted messages. 5054 ** Similarly, one of the outbound queues is designated the Free queue and the other outbound queue is designated the Post queue. 5055 ** 5056 ** ============================================================================================================= 5057 ** Circular Queue Summary 5058 ** _____________________________________________________________________________________________________________ 5059 ** | Queue Name | Purpose | Action on PCI Interface| 5060 ** |______________________|____________________________________________________________|_________________________| 5061 ** |Inbound Post Queue | Queue for inbound messages from other processors | Written | 5062 ** | | waiting to be processed by the 80331 | | 5063 ** |Inbound Free Queue | Queue for empty inbound messages from the 80331 | Read | 5064 ** | | available for use by other processors | | 5065 ** |Outbound Post Queue | Queue for outbound messages from the 80331 | Read | 5066 ** | | that are being posted to the other processors | | 5067 ** |Outbound Free Queue | Queue for empty outbound messages from other processors | Written | 5068 ** | | available for use by the 80331 | | 5069 ** |______________________|____________________________________________________________|_________________________| 5070 ** 5071 ** . The two inbound queues allow the host processor to post inbound messages for the 80331 in one 5072 ** queue and to receive free messages returning from the 80331. 5073 ** The host processor posts inbound messages, 5074 ** the Intel XScale core receives the posted message and when it is finished with the message, 5075 ** places it back on the inbound free queue for reuse by the host processor. 5076 ** 5077 ** The circular queues are accessed by external PCI agents through two port locations in the PCI 5078 ** address space: 5079 ** Inbound Queue Port 5080 ** and Outbound Queue Port. 5081 ** The Inbound Queue Port is used by external PCI agents to read the Inbound Free Queue and write the Inbound Post Queue. 5082 ** The Outbound Queue Port is used by external PCI agents to read the Outbound Post Queue and write the Outbound Free Queue. 5083 ** Note that a PCI transaction to the inbound or outbound queue ports with null byte enables (P_C/BE[3:0]#=1111 2 ) 5084 ** does not cause the MU hardware to increment the queue pointers. 5085 ** This is treated as when the PCI transaction did not occur. 5086 ** The Inbound and Outbound Queue Ports never respond with P_ACK64# on the PCI interface. 5087 ** ====================================================================================== 5088 ** Overview of Circular Queue Operation 5089 ** ====================================================================================== 5090 ** . The data storage for the circular queues must be provided by the 80331 local memory. 5091 ** . The base address of the circular queues is contained in the Queue Base Address Register. 5092 ** Each entry in the queue is a 32-bit data value. 5093 ** . Each read from or write to the queue may access only one queue entry. 5094 ** . Multi-DWORD accesses to the circular queues are not allowed. 5095 ** Sub-DWORD accesses are promoted to DWORD accesses. 5096 ** . Each circular queue has a head pointer and a tail pointer. 5097 ** The pointers are offsets from the Queue Base Address. 5098 ** . Writes to a queue occur at the head of the queue and reads occur from the tail. 5099 ** The head and tail pointers are incremented by either the Intel XScale core or the Messaging Unit hardware. 5100 ** Which unit maintains the pointer is determined by the writer of the queue. 5101 ** More details about the pointers are given in the queue descriptions below. 5102 ** The pointers are incremented after the queue access. 5103 ** Both pointers wrap around to the first address of the circular queue when they reach the circular queue size. 5104 ** 5105 ** Messaging Unit... 5106 ** 5107 ** The Messaging Unit generates an interrupt to the Intel XScale core or generate a PCI interrupt under certain conditions. 5108 ** . In general, when a Post queue is written, an interrupt is generated to notify the receiver that a message was posted. 5109 ** The size of each circular queue can range from 4K entries (16 Kbytes) to 64K entries (256 Kbytes). 5110 ** . All four queues must be the same size and may be contiguous. 5111 ** Therefore, the total amount of local memory needed by the circular queues ranges from 64 Kbytes to 1 Mbytes. 5112 ** The Queue size is determined by the Queue Size field in the MU Configuration Register. 5113 ** . There is one base address for all four queues. 5114 ** It is stored in the Queue Base Address Register (QBAR). 5115 ** The starting addresses of each queue is based on the Queue Base Address and the Queue Size field. 5116 ** here shows an example of how the circular queues should be set up based on the 5117 ** Intelligent I/O (I 2 O) Architecture Specification. 5118 ** Other ordering of the circular queues is possible. 5119 ** 5120 ** Queue Starting Address 5121 ** Inbound Free Queue QBAR 5122 ** Inbound Post Queue QBAR + Queue Size 5123 ** Outbound Post Queue QBAR + 2 * Queue Size 5124 ** Outbound Free Queue QBAR + 3 * Queue Size 5125 ** =================================================================================== 5126 ** Inbound Post Queue 5127 ** ------------------ 5128 ** The Inbound Post Queue holds posted messages placed there by other processors for the Intel XScale core to process. 5129 ** This queue is read from the queue tail by the Intel XScale core. It is written to the queue head by external PCI agents. 5130 ** The tail pointer is maintained by the Intel XScale core. The head pointer is maintained by the MU hardware. 5131 ** For a PCI write transaction that accesses the Inbound Queue Port, 5132 ** the MU writes the data to the local memory location address in the Inbound Post Head Pointer Register. 5133 ** When the data written to the Inbound Queue Port is written to local memory, the MU hardware increments the Inbound Post Head Pointer Register. 5134 ** An Intel XScale core interrupt may be generated when the Inbound Post Queue is written. 5135 ** The Inbound Post Queue Interrupt bit in the Inbound Interrupt Status Register indicates the interrupt status. 5136 ** The interrupt is cleared when the Inbound Post Queue Interrupt bit is cleared. 5137 ** The interrupt can be masked by the Inbound Interrupt Mask Register. 5138 ** Software must be aware of the state of the Inbound Post Queue Interrupt Mask bit to guarantee 5139 ** that the full condition is recognized by the core processor. 5140 ** In addition, to guarantee that the queue does not get overwritten, 5141 ** software must process messages from the tail of the queue before incrementing the tail pointer and clearing this interrupt. 5142 ** Once cleared, an interrupt is NOT generated when the head and tail pointers remain unequal (i.e. queue status is Not Empty). 5143 ** Only a new message posting the in the inbound queue generates a new interrupt. 5144 ** Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared, 5145 ** software must retain the information that the Inbound Post queue status. 5146 ** From the time that the PCI write transaction is received until the data is written 5147 ** in local memory and the Inbound Post Head Pointer Register is incremented, 5148 ** any PCI transaction that attempts to access the Inbound Post Queue Port is signalled a Retry. 5149 ** The Intel XScale core may read messages from the Inbound Post Queue 5150 ** by reading the data from the local memory location pointed to by the Inbound Post Tail Pointer Register. 5151 ** The Intel XScale core must then increment the Inbound Post Tail Pointer Register. 5152 ** When the Inbound Post Queue is full (head and tail pointers are equal and the head pointer was last updated by hardware), 5153 ** the hardware retries any PCI writes until a slot in the queue becomes available. 5154 ** A slot in the post queue becomes available by the Intel XScale core incrementing the tail pointer. 5155 ** =================================================================================== 5156 ** Inbound Free Queue 5157 ** ------------------ 5158 ** The Inbound Free Queue holds free inbound messages placed there by the Intel XScale core for other processors to use. 5159 ** This queue is read from the queue tail by external PCI agents. 5160 ** It is written to the queue head by the Intel XScale core. 5161 ** The tail pointer is maintained by the MU hardware. 5162 ** The head pointer is maintained by the Intel XScale core. 5163 ** For a PCI read transaction that accesses the Inbound Queue Port, 5164 ** the MU attempts to read the data at the local memory address in the Inbound Free Tail Pointer. 5165 ** When the queue is not empty (head and tail pointers are not equal) 5166 ** or full (head and tail pointers are equal but the head pointer was last written by software), the data is returned. 5167 ** When the queue is empty (head and tail pointers are equal and the head pointer was last updated by hardware), 5168 ** the value of -1 (FFFF.FFFFH) is returned. 5169 ** When the queue was not empty and the MU succeeded in returning the data at the tail, 5170 ** the MU hardware must increment the value in the Inbound Free Tail Pointer Register. 5171 ** To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate accesses to the Inbound Free Queue. 5172 ** The MU hardware prefetches the data at the tail of the Inbound Free Queue and load it into an internal prefetch register. 5173 ** When the PCI read access occurs, the data is read directly from the prefetch register. 5174 ** The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register 5175 ** when the head and tail pointers are equal and the queue is empty. 5176 ** In order to update the prefetch register when messages are added to the queue and it becomes non-empty, 5177 ** the prefetch mechanism automatically starts a prefetch when the prefetch register contains FFFF.FFFFH 5178 ** and the Inbound Free Head Pointer Register is written. 5179 ** The Intel XScale core needs to update the Inbound Free Head Pointer Register when it adds messages to the queue. 5180 ** A prefetch must appear atomic from the perspective of the external PCI agent. 5181 ** When a prefetch is started, any PCI transaction that attempts to access the Inbound Free Queue is signalled a Retry until the prefetch is completed. 5182 ** The Intel XScale core may place messages in the Inbound Free Queue by writing the data to the 5183 ** local memory location pointed to by the Inbound Free Head Pointer Register. 5184 ** The processor must then increment the Inbound Free Head Pointer Register. 5185 ** ================================================================================== 5186 ** Outbound Post Queue 5187 ** ------------------- 5188 ** The Outbound Post Queue holds outbound posted messages placed there by the Intel XScale 5189 ** core for other processors to process. This queue is read from the queue tail by external PCI agents. 5190 ** It is written to the queue head by the Intel XScale core. The tail pointer is maintained by the 5191 ** MU hardware. The head pointer is maintained by the Intel XScale core. 5192 ** For a PCI read transaction that accesses the Outbound Queue Port, the MU attempts to read the 5193 ** data at the local memory address in the Outbound Post Tail Pointer Register. When the queue is not 5194 ** empty (head and tail pointers are not equal) or full (head and tail pointers are equal but the head 5195 ** pointer was last written by software), the data is returned. When the queue is empty (head and tail 5196 ** pointers are equal and the head pointer was last updated by hardware), the value of -1 5197 ** (FFFF.FFFFH) is returned. When the queue was not empty and the MU succeeded in returning the 5198 ** data at the tail, the MU hardware must increment the value in the Outbound Post Tail Pointer 5199 ** Register. 5200 ** To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate 5201 ** accesses to the Outbound Post Queue. The MU hardware prefetches the data at the tail of the 5202 ** Outbound Post Queue and load it into an internal prefetch register. When the PCI read access 5203 ** occurs, the data is read directly from the prefetch register. 5204 ** The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register when the head 5205 ** and tail pointers are equal and the queue is empty. In order to update the prefetch register when 5206 ** messages are added to the queue and it becomes non-empty, the prefetch mechanism automatically 5207 ** starts a prefetch when the prefetch register contains FFFF.FFFFH and the Outbound Post Head 5208 ** Pointer Register is written. The Intel XScale core needs to update the Outbound Post Head 5209 ** Pointer Register when it adds messages to the queue. 5210 ** A prefetch must appear atomic from the perspective of the external PCI agent. When a prefetch is 5211 ** started, any PCI transaction that attempts to access the Outbound Post Queue is signalled a Retry 5212 ** until the prefetch is completed. 5213 ** A PCI interrupt may be generated when data in the prefetch buffer is valid. When the prefetch 5214 ** queue is clear, no interrupt is generated. The Outbound Post Queue Interrupt bit in the Outbound 5215 ** Interrupt Status Register shall indicate the status of the prefetch buffer data and therefore the 5216 ** interrupt status. The interrupt is cleared when any prefetched data has been read from the Outbound 5217 ** Queue Port. The interrupt can be masked by the Outbound Interrupt Mask Register. 5218 ** The Intel XScale core may place messages in the Outbound Post Queue by writing the data to 5219 ** the local memory address in the Outbound Post Head Pointer Register. The processor must then 5220 ** increment the Outbound Post Head Pointer Register. 5221 ** ================================================== 5222 ** Outbound Free Queue 5223 ** ----------------------- 5224 ** The Outbound Free Queue holds free messages placed there by other processors for the Intel 5225 ** XScale core to use. This queue is read from the queue tail by the Intel XScale core. It is 5226 ** written to the queue head by external PCI agents. The tail pointer is maintained by the Intel 5227 ** XScale core. The head pointer is maintained by the MU hardware. 5228 ** For a PCI write transaction that accesses the Outbound Queue Port, the MU writes the data to the 5229 ** local memory address in the Outbound Free Head Pointer Register. When the data written to the 5230 ** Outbound Queue Port is written to local memory, the MU hardware increments the Outbound Free 5231 ** Head Pointer Register. 5232 ** When the head pointer and the tail pointer become equal and the queue is full, the MU may signal 5233 ** an interrupt to the Intel XScale core to register the queue full condition. This interrupt is 5234 ** recorded in the Inbound Interrupt Status Register. The interrupt is cleared when the Outbound Free 5235 ** Queue Full Interrupt bit is cleared and not by writing to the head or tail pointers. The interrupt can 5236 ** be masked by the Inbound Interrupt Mask Register. Software must be aware of the state of the 5237 ** Outbound Free Queue Interrupt Mask bit to guarantee that the full condition is recognized by the 5238 ** core processor. 5239 ** From the time that a PCI write transaction is received until the data is written in local memory and 5240 ** the Outbound Free Head Pointer Register is incremented, any PCI transaction that attempts to 5241 ** access the Outbound Free Queue Port is signalled a retry. 5242 ** The Intel XScale core may read messages from the Outbound Free Queue by reading the data 5243 ** from the local memory address in the Outbound Free Tail Pointer Register. The processor must 5244 ** then increment the Outbound Free Tail Pointer Register. When the Outbound Free Queue is full, 5245 ** the hardware must retry any PCI writes until a slot in the queue becomes available. 5246 ** 5247 ** ================================================================================== 5248 ** Circular Queue Summary 5249 ** ---------------------- 5250 ** ________________________________________________________________________________________________________________________________________________ 5251 ** | Queue Name | PCI Port |Generate PCI Interrupt |Generate Intel Xscale Core Interrupt|Head Pointer maintained by|Tail Pointer maintained by| 5252 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 5253 ** |Inbound Post | Inbound Queue | | | | | 5254 ** | Queue | Port | NO | Yes, when queue is written | MU hardware | Intel XScale | 5255 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 5256 ** |Inbound Free | Inbound Queue | | | | | 5257 ** | Queue | Port | NO | NO | Intel XScale | MU hardware | 5258 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 5259 ** ================================================================================== 5260 ** Circular Queue Status Summary 5261 ** ---------------------- 5262 ** ____________________________________________________________________________________________________ 5263 ** | Queue Name | Queue Status | Head & Tail Pointer | Last Pointer Update | 5264 ** |_____________________|________________|_____________________|_______________________________________| 5265 ** | Inbound Post Queue | Empty | Equal | Tail pointer last updated by software | 5266 ** |_____________________|________________|_____________________|_______________________________________| 5267 ** | Inbound Free Queue | Empty | Equal | Head pointer last updated by hardware | 5268 ** |_____________________|________________|_____________________|_______________________________________| 5269 ************************************************************************** 5270 */ 5271 5272 /* 5273 ************************************************************************** 5274 ** Index Registers 5275 ** ======================== 5276 ** . The Index Registers are a set of 1004 registers that when written by an external PCI agent can generate an interrupt to the Intel XScale core. 5277 ** These registers are for inbound messages only. 5278 ** The interrupt is recorded in the Inbound Interrupt Status Register. 5279 ** The storage for the Index Registers is allocated from the 80331 local memory. 5280 ** PCI write accesses to the Index Registers write the data to local memory. 5281 ** PCI read accesses to the Index Registers read the data from local memory. 5282 ** . The local memory used for the Index Registers ranges from Inbound ATU Translate Value Register + 050H 5283 ** to Inbound ATU Translate Value Register + FFFH. 5284 ** . The address of the first write access is stored in the Index Address Register. 5285 ** This register is written during the earliest write access and provides a means to determine which Index Register was written. 5286 ** Once updated by the MU, the Index Address Register is not updated until the Index Register 5287 ** Interrupt bit in the Inbound Interrupt Status Register is cleared. 5288 ** . When the interrupt is cleared, the Index Address Register is re-enabled and stores the address of the next Index Register write access. 5289 ** Writes by the Intel XScale core to the local memory used by the Index Registers 5290 ** does not cause an interrupt and does not update the Index Address Register. 5291 ** . The index registers can be accessed with Multi-DWORD reads and single QWORD aligned writes. 5292 ************************************************************************** 5293 */ 5294 /* 5295 ************************************************************************** 5296 ** Messaging Unit Internal Bus Memory Map 5297 ** ======================================= 5298 ** Internal Bus Address___Register Description (Name)____________________|_PCI Configuration Space Register Number_ 5299 ** FFFF E300H reserved | 5300 ** .. .. | 5301 ** FFFF E30CH reserved | 5302 ** FFFF E310H Inbound Message Register 0 | Available through 5303 ** FFFF E314H Inbound Message Register 1 | ATU Inbound Translation Window 5304 ** FFFF E318H Outbound Message Register 0 | 5305 ** FFFF E31CH Outbound Message Register 1 | or 5306 ** FFFF E320H Inbound Doorbell Register | 5307 ** FFFF E324H Inbound Interrupt Status Register | must translate PCI address to 5308 ** FFFF E328H Inbound Interrupt Mask Register | the Intel Xscale Core 5309 ** FFFF E32CH Outbound Doorbell Register | Memory-Mapped Address 5310 ** FFFF E330H Outbound Interrupt Status Register | 5311 ** FFFF E334H Outbound Interrupt Mask Register | 5312 ** ______________________________________________________________________|________________________________________ 5313 ** FFFF E338H reserved | 5314 ** FFFF E33CH reserved | 5315 ** FFFF E340H reserved | 5316 ** FFFF E344H reserved | 5317 ** FFFF E348H reserved | 5318 ** FFFF E34CH reserved | 5319 ** FFFF E350H MU Configuration Register | 5320 ** FFFF E354H Queue Base Address Register | 5321 ** FFFF E358H reserved | 5322 ** FFFF E35CH reserved | must translate PCI address to 5323 ** FFFF E360H Inbound Free Head Pointer Register | the Intel Xscale Core 5324 ** FFFF E364H Inbound Free Tail Pointer Register | Memory-Mapped Address 5325 ** FFFF E368H Inbound Post Head pointer Register | 5326 ** FFFF E36CH Inbound Post Tail Pointer Register | 5327 ** FFFF E370H Outbound Free Head Pointer Register | 5328 ** FFFF E374H Outbound Free Tail Pointer Register | 5329 ** FFFF E378H Outbound Post Head pointer Register | 5330 ** FFFF E37CH Outbound Post Tail Pointer Register | 5331 ** FFFF E380H Index Address Register | 5332 ** FFFF E384H reserved | 5333 ** .. .. | 5334 ** FFFF E3FCH reserved | 5335 ** ______________________________________________________________________|_______________________________________ 5336 ************************************************************************** 5337 */ 5338 /* 5339 ************************************************************************** 5340 ** MU Configuration Register - MUCR FFFF.E350H 5341 ** 5342 ** . The MU Configuration Register (MUCR) contains the Circular Queue Enable bit and the size of one Circular Queue. 5343 ** . The Circular Queue Enable bit enables or disables the Circular Queues. 5344 ** The Circular Queues are disabled at reset to allow the software to initialize the head 5345 ** and tail pointer registers before any PCI accesses to the Queue Ports. 5346 ** . Each Circular Queue may range from 4 K entries (16 Kbytes) to 64 K entries (256 Kbytes) and there are four Circular Queues. 5347 ** ------------------------------------------------------------------------ 5348 ** Bit Default Description 5349 ** 31:06 000000H 00 2 Reserved 5350 ** 05:01 00001 2 Circular Queue Size - This field determines the size of each Circular Queue. 5351 ** All four queues are the same size. 5352 ** �E 00001 2 - 4K Entries (16 Kbytes) 5353 ** �E 00010 2 - 8K Entries (32 Kbytes) 5354 ** �E 00100 2 - 16K Entries (64 Kbytes) 5355 ** �E 01000 2 - 32K Entries (128 Kbytes) 5356 ** �E 10000 2 - 64K Entries (256 Kbytes) 5357 ** 00 0 2 Circular Queue Enable - This bit enables or disables the Circular Queues. When clear the Circular 5358 ** Queues are disabled, however the MU accepts PCI accesses to the Circular Queue Ports but ignores 5359 ** the data for Writes and return FFFF.FFFFH for Reads. Interrupts are not generated to the core when 5360 ** disabled. When set, the Circular Queues are fully enabled. 5361 ************************************************************************** 5362 */ 5363 #define ARCMSR_MU_CONFIGURATION_REG 0xFFFFE350 5364 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE64K 0x0020 5365 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE32K 0x0010 5366 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE16K 0x0008 5367 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE8K 0x0004 5368 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE4K 0x0002 5369 #define ARCMSR_MU_CIRCULAR_QUEUE_ENABLE 0x0001 /*0:disable 1:enable*/ 5370 /* 5371 ************************************************************************** 5372 ** Queue Base Address Register - QBAR 5373 ** 5374 ** . The Queue Base Address Register (QBAR) contains the local memory address of the Circular Queues. 5375 ** The base address is required to be located on a 1 Mbyte address boundary. 5376 ** . All Circular Queue head and tail pointers are based on the QBAR. 5377 ** When the head and tail pointer registers are read, the Queue Base Address is returned in the upper 12 bits. 5378 ** Writing to the upper 12 bits of the head and tail pointer registers does not affect the Queue Base Address or Queue Base Address Register. 5379 ** Warning: 5380 ** The QBAR must designate a range allocated to the 80331 DDR SDRAM interface 5381 ** ------------------------------------------------------------------------ 5382 ** Bit Default Description 5383 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5384 ** 19:00 00000H Reserved 5385 ************************************************************************** 5386 */ 5387 #define ARCMSR_MU_QUEUE_BASE_ADDRESS_REG 0xFFFFE354 5388 /* 5389 ************************************************************************** 5390 ** Inbound Free Head Pointer Register - IFHPR 5391 ** 5392 ** . The Inbound Free Head Pointer Register (IFHPR) contains the local memory offset from 5393 ** the Queue Base Address of the head pointer for the Inbound Free Queue. 5394 ** The Head Pointer must be aligned on a DWORD address boundary. 5395 ** When read, the Queue Base Address is provided in the upper 12 bits of the register. 5396 ** Writes to the upper 12 bits of the register are ignored. 5397 ** This register is maintained by software. 5398 ** ------------------------------------------------------------------------ 5399 ** Bit Default Description 5400 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5401 ** 19:02 0000H 00 2 Inbound Free Head Pointer - Local memory offset of the head pointer for the Inbound Free Queue. 5402 ** 01:00 00 2 Reserved 5403 ************************************************************************** 5404 */ 5405 #define ARCMSR_MU_INBOUND_FREE_HEAD_PTR_REG 0xFFFFE360 5406 /* 5407 ************************************************************************** 5408 ** Inbound Free Tail Pointer Register - IFTPR 5409 ** 5410 ** . The Inbound Free Tail Pointer Register (IFTPR) contains the local memory offset from the Queue 5411 ** Base Address of the tail pointer for the Inbound Free Queue. The Tail Pointer must be aligned on a 5412 ** DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 5413 ** of the register. Writes to the upper 12 bits of the register are ignored. 5414 ** ------------------------------------------------------------------------ 5415 ** Bit Default Description 5416 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5417 ** 19:02 0000H 00 2 Inbound Free Tail Pointer - Local memory offset of the tail pointer for the Inbound Free Queue. 5418 ** 01:00 00 2 Reserved 5419 ************************************************************************** 5420 */ 5421 #define ARCMSR_MU_INBOUND_FREE_TAIL_PTR_REG 0xFFFFE364 5422 /* 5423 ************************************************************************** 5424 ** Inbound Post Head Pointer Register - IPHPR 5425 ** 5426 ** . The Inbound Post Head Pointer Register (IPHPR) contains the local memory offset from the Queue 5427 ** Base Address of the head pointer for the Inbound Post Queue. The Head Pointer must be aligned on 5428 ** a DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 5429 ** of the register. Writes to the upper 12 bits of the register are ignored. 5430 ** ------------------------------------------------------------------------ 5431 ** Bit Default Description 5432 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5433 ** 19:02 0000H 00 2 Inbound Post Head Pointer - Local memory offset of the head pointer for the Inbound Post Queue. 5434 ** 01:00 00 2 Reserved 5435 ************************************************************************** 5436 */ 5437 #define ARCMSR_MU_INBOUND_POST_HEAD_PTR_REG 0xFFFFE368 5438 /* 5439 ************************************************************************** 5440 ** Inbound Post Tail Pointer Register - IPTPR 5441 ** 5442 ** . The Inbound Post Tail Pointer Register (IPTPR) contains the local memory offset from the Queue 5443 ** Base Address of the tail pointer for the Inbound Post Queue. The Tail Pointer must be aligned on a 5444 ** DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 5445 ** of the register. Writes to the upper 12 bits of the register are ignored. 5446 ** ------------------------------------------------------------------------ 5447 ** Bit Default Description 5448 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5449 ** 19:02 0000H 00 2 Inbound Post Tail Pointer - Local memory offset of the tail pointer for the Inbound Post Queue. 5450 ** 01:00 00 2 Reserved 5451 ************************************************************************** 5452 */ 5453 #define ARCMSR_MU_INBOUND_POST_TAIL_PTR_REG 0xFFFFE36C 5454 /* 5455 ************************************************************************** 5456 ** Index Address Register - IAR 5457 ** 5458 ** . The Index Address Register (IAR) contains the offset of the least recently accessed Index Register. 5459 ** It is written by the MU when the Index Registers are written by a PCI agent. 5460 ** The register is not updated until the Index Interrupt bit in the Inbound Interrupt Status Register is cleared. 5461 ** . The local memory address of the Index Register least recently accessed is computed 5462 ** by adding the Index Address Register to the Inbound ATU Translate Value Register. 5463 ** ------------------------------------------------------------------------ 5464 ** Bit Default Description 5465 ** 31:12 000000H Reserved 5466 ** 11:02 00H 00 2 Index Address - is the local memory offset of the Index Register written (050H to FFCH) 5467 ** 01:00 00 2 Reserved 5468 ************************************************************************** 5469 */ 5470 #define ARCMSR_MU_LOCAL_MEMORY_INDEX_REG 0xFFFFE380 /*1004 dwords 0x0050....0x0FFC, 4016 bytes 0x0050...0x0FFF*/ 5471 /* 5472 ********************************************************************************************************** 5473 ** RS-232 Interface for Areca Raid Controller 5474 ** The low level command interface is exclusive with VT100 terminal 5475 ** -------------------------------------------------------------------- 5476 ** 1. Sequence of command execution 5477 ** -------------------------------------------------------------------- 5478 ** (A) Header : 3 bytes sequence (0x5E, 0x01, 0x61) 5479 ** (B) Command block : variable length of data including length, command code, data and checksum byte 5480 ** (C) Return data : variable length of data 5481 ** -------------------------------------------------------------------- 5482 ** 2. Command block 5483 ** -------------------------------------------------------------------- 5484 ** (A) 1st byte : command block length (low byte) 5485 ** (B) 2nd byte : command block length (high byte) 5486 ** note ..command block length shouldn't > 2040 bytes, length excludes these two bytes 5487 ** (C) 3rd byte : command code 5488 ** (D) 4th and following bytes : variable length data bytes depends on command code 5489 ** (E) last byte : checksum byte (sum of 1st byte until last data byte) 5490 ** -------------------------------------------------------------------- 5491 ** 3. Command code and associated data 5492 ** -------------------------------------------------------------------- 5493 ** The following are command code defined in raid controller Command code 0x10--0x1? are used for system level management, 5494 ** no password checking is needed and should be implemented in separate well controlled utility and not for end user access. 5495 ** Command code 0x20--0x?? always check the password, password must be entered to enable these command. 5496 ** enum 5497 ** { 5498 ** GUI_SET_SERIAL=0x10, 5499 ** GUI_SET_VENDOR, 5500 ** GUI_SET_MODEL, 5501 ** GUI_IDENTIFY, 5502 ** GUI_CHECK_PASSWORD, 5503 ** GUI_LOGOUT, 5504 ** GUI_HTTP, 5505 ** GUI_SET_ETHERNET_ADDR, 5506 ** GUI_SET_LOGO, 5507 ** GUI_POLL_EVENT, 5508 ** GUI_GET_EVENT, 5509 ** GUI_GET_HW_MONITOR, 5510 ** 5511 ** // GUI_QUICK_CREATE=0x20, (function removed) 5512 ** GUI_GET_INFO_R=0x20, 5513 ** GUI_GET_INFO_V, 5514 ** GUI_GET_INFO_P, 5515 ** GUI_GET_INFO_S, 5516 ** GUI_CLEAR_EVENT, 5517 ** 5518 ** GUI_MUTE_BEEPER=0x30, 5519 ** GUI_BEEPER_SETTING, 5520 ** GUI_SET_PASSWORD, 5521 ** GUI_HOST_INTERFACE_MODE, 5522 ** GUI_REBUILD_PRIORITY, 5523 ** GUI_MAX_ATA_MODE, 5524 ** GUI_RESET_CONTROLLER, 5525 ** GUI_COM_PORT_SETTING, 5526 ** GUI_NO_OPERATION, 5527 ** GUI_DHCP_IP, 5528 ** 5529 ** GUI_CREATE_PASS_THROUGH=0x40, 5530 ** GUI_MODIFY_PASS_THROUGH, 5531 ** GUI_DELETE_PASS_THROUGH, 5532 ** GUI_IDENTIFY_DEVICE, 5533 ** 5534 ** GUI_CREATE_RAIDSET=0x50, 5535 ** GUI_DELETE_RAIDSET, 5536 ** GUI_EXPAND_RAIDSET, 5537 ** GUI_ACTIVATE_RAIDSET, 5538 ** GUI_CREATE_HOT_SPARE, 5539 ** GUI_DELETE_HOT_SPARE, 5540 ** 5541 ** GUI_CREATE_VOLUME=0x60, 5542 ** GUI_MODIFY_VOLUME, 5543 ** GUI_DELETE_VOLUME, 5544 ** GUI_START_CHECK_VOLUME, 5545 ** GUI_STOP_CHECK_VOLUME 5546 ** }; 5547 ** 5548 ** Command description : 5549 ** 5550 ** GUI_SET_SERIAL : Set the controller serial# 5551 ** byte 0,1 : length 5552 ** byte 2 : command code 0x10 5553 ** byte 3 : password length (should be 0x0f) 5554 ** byte 4-0x13 : should be "ArEcATecHnoLogY" 5555 ** byte 0x14--0x23 : Serial number string (must be 16 bytes) 5556 ** GUI_SET_VENDOR : Set vendor string for the controller 5557 ** byte 0,1 : length 5558 ** byte 2 : command code 0x11 5559 ** byte 3 : password length (should be 0x08) 5560 ** byte 4-0x13 : should be "ArEcAvAr" 5561 ** byte 0x14--0x3B : vendor string (must be 40 bytes) 5562 ** GUI_SET_MODEL : Set the model name of the controller 5563 ** byte 0,1 : length 5564 ** byte 2 : command code 0x12 5565 ** byte 3 : password length (should be 0x08) 5566 ** byte 4-0x13 : should be "ArEcAvAr" 5567 ** byte 0x14--0x1B : model string (must be 8 bytes) 5568 ** GUI_IDENTIFY : Identify device 5569 ** byte 0,1 : length 5570 ** byte 2 : command code 0x13 5571 ** return "Areca RAID Subsystem " 5572 ** GUI_CHECK_PASSWORD : Verify password 5573 ** byte 0,1 : length 5574 ** byte 2 : command code 0x14 5575 ** byte 3 : password length 5576 ** byte 4-0x?? : user password to be checked 5577 ** GUI_LOGOUT : Logout GUI (force password checking on next command) 5578 ** byte 0,1 : length 5579 ** byte 2 : command code 0x15 5580 ** GUI_HTTP : HTTP interface (reserved for Http proxy service)(0x16) 5581 ** 5582 ** GUI_SET_ETHERNET_ADDR : Set the ethernet MAC address 5583 ** byte 0,1 : length 5584 ** byte 2 : command code 0x17 5585 ** byte 3 : password length (should be 0x08) 5586 ** byte 4-0x13 : should be "ArEcAvAr" 5587 ** byte 0x14--0x19 : Ethernet MAC address (must be 6 bytes) 5588 ** GUI_SET_LOGO : Set logo in HTTP 5589 ** byte 0,1 : length 5590 ** byte 2 : command code 0x18 5591 ** byte 3 : Page# (0/1/2/3) (0xff --> clear OEM logo) 5592 ** byte 4/5/6/7 : 0x55/0xaa/0xa5/0x5a 5593 ** byte 8 : TITLE.JPG data (each page must be 2000 bytes) 5594 ** note .... page0 1st 2 byte must be actual length of the JPG file 5595 ** GUI_POLL_EVENT : Poll If Event Log Changed 5596 ** byte 0,1 : length 5597 ** byte 2 : command code 0x19 5598 ** GUI_GET_EVENT : Read Event 5599 ** byte 0,1 : length 5600 ** byte 2 : command code 0x1a 5601 ** byte 3 : Event Page (0:1st page/1/2/3:last page) 5602 ** GUI_GET_HW_MONITOR : Get HW monitor data 5603 ** byte 0,1 : length 5604 ** byte 2 : command code 0x1b 5605 ** byte 3 : # of FANs(example 2) 5606 ** byte 4 : # of Voltage sensor(example 3) 5607 ** byte 5 : # of temperature sensor(example 2) 5608 ** byte 6 : # of power 5609 ** byte 7/8 : Fan#0 (RPM) 5610 ** byte 9/10 : Fan#1 5611 ** byte 11/12 : Voltage#0 original value in *1000 5612 ** byte 13/14 : Voltage#0 value 5613 ** byte 15/16 : Voltage#1 org 5614 ** byte 17/18 : Voltage#1 5615 ** byte 19/20 : Voltage#2 org 5616 ** byte 21/22 : Voltage#2 5617 ** byte 23 : Temp#0 5618 ** byte 24 : Temp#1 5619 ** byte 25 : Power indicator (bit0 : power#0, bit1 : power#1) 5620 ** byte 26 : UPS indicator 5621 ** GUI_QUICK_CREATE : Quick create raid/volume set 5622 ** byte 0,1 : length 5623 ** byte 2 : command code 0x20 5624 ** byte 3/4/5/6 : raw capacity 5625 ** byte 7 : raid level 5626 ** byte 8 : stripe size 5627 ** byte 9 : spare 5628 ** byte 10/11/12/13: device mask (the devices to create raid/volume) 5629 ** This function is removed, application like to implement quick create function 5630 ** need to use GUI_CREATE_RAIDSET and GUI_CREATE_VOLUMESET function. 5631 ** GUI_GET_INFO_R : Get Raid Set Information 5632 ** byte 0,1 : length 5633 ** byte 2 : command code 0x20 5634 ** byte 3 : raidset# 5635 ** 5636 ** typedef struct sGUI_RAIDSET 5637 ** { 5638 ** BYTE grsRaidSetName[16]; 5639 ** DWORD grsCapacity; 5640 ** DWORD grsCapacityX; 5641 ** DWORD grsFailMask; 5642 ** BYTE grsDevArray[32]; 5643 ** BYTE grsMemberDevices; 5644 ** BYTE grsNewMemberDevices; 5645 ** BYTE grsRaidState; 5646 ** BYTE grsVolumes; 5647 ** BYTE grsVolumeList[16]; 5648 ** BYTE grsRes1; 5649 ** BYTE grsRes2; 5650 ** BYTE grsRes3; 5651 ** BYTE grsFreeSegments; 5652 ** DWORD grsRawStripes[8]; 5653 ** DWORD grsRes4; 5654 ** DWORD grsRes5; // Total to 128 bytes 5655 ** DWORD grsRes6; // Total to 128 bytes 5656 ** } sGUI_RAIDSET, *pGUI_RAIDSET; 5657 ** GUI_GET_INFO_V : Get Volume Set Information 5658 ** byte 0,1 : length 5659 ** byte 2 : command code 0x21 5660 ** byte 3 : volumeset# 5661 ** 5662 ** typedef struct sGUI_VOLUMESET 5663 ** { 5664 ** BYTE gvsVolumeName[16]; // 16 5665 ** DWORD gvsCapacity; 5666 ** DWORD gvsCapacityX; 5667 ** DWORD gvsFailMask; 5668 ** DWORD gvsStripeSize; 5669 ** DWORD gvsNewFailMask; 5670 ** DWORD gvsNewStripeSize; 5671 ** DWORD gvsVolumeStatus; 5672 ** DWORD gvsProgress; // 32 5673 ** sSCSI_ATTR gvsScsi; 5674 ** BYTE gvsMemberDisks; 5675 ** BYTE gvsRaidLevel; // 8 5676 ** 5677 ** BYTE gvsNewMemberDisks; 5678 ** BYTE gvsNewRaidLevel; 5679 ** BYTE gvsRaidSetNumber; 5680 ** BYTE gvsRes0; // 4 5681 ** BYTE gvsRes1[4]; // 64 bytes 5682 ** } sGUI_VOLUMESET, *pGUI_VOLUMESET; 5683 ** 5684 ** GUI_GET_INFO_P : Get Physical Drive Information 5685 ** byte 0,1 : length 5686 ** byte 2 : command code 0x22 5687 ** byte 3 : drive # (from 0 to max-channels - 1) 5688 ** 5689 ** typedef struct sGUI_PHY_DRV 5690 ** { 5691 ** BYTE gpdModelName[40]; 5692 ** BYTE gpdSerialNumber[20]; 5693 ** BYTE gpdFirmRev[8]; 5694 ** DWORD gpdCapacity; 5695 ** DWORD gpdCapacityX; // Reserved for expansion 5696 ** BYTE gpdDeviceState; 5697 ** BYTE gpdPioMode; 5698 ** BYTE gpdCurrentUdmaMode; 5699 ** BYTE gpdUdmaMode; 5700 ** BYTE gpdDriveSelect; 5701 ** BYTE gpdRaidNumber; // 0xff if not belongs to a raid set 5702 ** sSCSI_ATTR gpdScsi; 5703 ** BYTE gpdReserved[40]; // Total to 128 bytes 5704 ** } sGUI_PHY_DRV, *pGUI_PHY_DRV; 5705 ** 5706 ** GUI_GET_INFO_S : Get System Information 5707 ** byte 0,1 : length 5708 ** byte 2 : command code 0x23 5709 ** 5710 ** typedef struct sCOM_ATTR 5711 ** { 5712 ** BYTE comBaudRate; 5713 ** BYTE comDataBits; 5714 ** BYTE comStopBits; 5715 ** BYTE comParity; 5716 ** BYTE comFlowControl; 5717 ** } sCOM_ATTR, *pCOM_ATTR; 5718 ** 5719 ** typedef struct sSYSTEM_INFO 5720 ** { 5721 ** BYTE gsiVendorName[40]; 5722 ** BYTE gsiSerialNumber[16]; 5723 ** BYTE gsiFirmVersion[16]; 5724 ** BYTE gsiBootVersion[16]; 5725 ** BYTE gsiMbVersion[16]; 5726 ** BYTE gsiModelName[8]; 5727 ** BYTE gsiLocalIp[4]; 5728 ** BYTE gsiCurrentIp[4]; 5729 ** DWORD gsiTimeTick; 5730 ** DWORD gsiCpuSpeed; 5731 ** DWORD gsiICache; 5732 ** DWORD gsiDCache; 5733 ** DWORD gsiScache; 5734 ** DWORD gsiMemorySize; 5735 ** DWORD gsiMemorySpeed; 5736 ** DWORD gsiEvents; 5737 ** BYTE gsiMacAddress[6]; 5738 ** BYTE gsiDhcp; 5739 ** BYTE gsiBeeper; 5740 ** BYTE gsiChannelUsage; 5741 ** BYTE gsiMaxAtaMode; 5742 ** BYTE gsiSdramEcc; // 1:if ECC enabled 5743 ** BYTE gsiRebuildPriority; 5744 ** sCOM_ATTR gsiComA; // 5 bytes 5745 ** sCOM_ATTR gsiComB; // 5 bytes 5746 ** BYTE gsiIdeChannels; 5747 ** BYTE gsiScsiHostChannels; 5748 ** BYTE gsiIdeHostChannels; 5749 ** BYTE gsiMaxVolumeSet; 5750 ** BYTE gsiMaxRaidSet; 5751 ** BYTE gsiEtherPort; // 1:if ether net port supported 5752 ** BYTE gsiRaid6Engine; // 1:Raid6 engine supported 5753 ** BYTE gsiRes[75]; 5754 ** } sSYSTEM_INFO, *pSYSTEM_INFO; 5755 ** 5756 ** GUI_CLEAR_EVENT : Clear System Event 5757 ** byte 0,1 : length 5758 ** byte 2 : command code 0x24 5759 ** 5760 ** GUI_MUTE_BEEPER : Mute current beeper 5761 ** byte 0,1 : length 5762 ** byte 2 : command code 0x30 5763 ** 5764 ** GUI_BEEPER_SETTING : Disable beeper 5765 ** byte 0,1 : length 5766 ** byte 2 : command code 0x31 5767 ** byte 3 : 0->disable, 1->enable 5768 ** 5769 ** GUI_SET_PASSWORD : Change password 5770 ** byte 0,1 : length 5771 ** byte 2 : command code 0x32 5772 ** byte 3 : pass word length ( must <= 15 ) 5773 ** byte 4 : password (must be alpha-numerical) 5774 ** 5775 ** GUI_HOST_INTERFACE_MODE : Set host interface mode 5776 ** byte 0,1 : length 5777 ** byte 2 : command code 0x33 5778 ** byte 3 : 0->Independent, 1->cluster 5779 ** 5780 ** GUI_REBUILD_PRIORITY : Set rebuild priority 5781 ** byte 0,1 : length 5782 ** byte 2 : command code 0x34 5783 ** byte 3 : 0/1/2/3 (low->high) 5784 ** 5785 ** GUI_MAX_ATA_MODE : Set maximum ATA mode to be used 5786 ** byte 0,1 : length 5787 ** byte 2 : command code 0x35 5788 ** byte 3 : 0/1/2/3 (133/100/66/33) 5789 ** 5790 ** GUI_RESET_CONTROLLER : Reset Controller 5791 ** byte 0,1 : length 5792 ** byte 2 : command code 0x36 5793 ** *Response with VT100 screen (discard it) 5794 ** 5795 ** GUI_COM_PORT_SETTING : COM port setting 5796 ** byte 0,1 : length 5797 ** byte 2 : command code 0x37 5798 ** byte 3 : 0->COMA (term port), 1->COMB (debug port) 5799 ** byte 4 : 0/1/2/3/4/5/6/7 (1200/2400/4800/9600/19200/38400/57600/115200) 5800 ** byte 5 : data bit (0:7 bit, 1:8 bit : must be 8 bit) 5801 ** byte 6 : stop bit (0:1, 1:2 stop bits) 5802 ** byte 7 : parity (0:none, 1:off, 2:even) 5803 ** byte 8 : flow control (0:none, 1:xon/xoff, 2:hardware => must use none) 5804 ** 5805 ** GUI_NO_OPERATION : No operation 5806 ** byte 0,1 : length 5807 ** byte 2 : command code 0x38 5808 ** 5809 ** GUI_DHCP_IP : Set DHCP option and local IP address 5810 ** byte 0,1 : length 5811 ** byte 2 : command code 0x39 5812 ** byte 3 : 0:dhcp disabled, 1:dhcp enabled 5813 ** byte 4/5/6/7 : IP address 5814 ** 5815 ** GUI_CREATE_PASS_THROUGH : Create pass through disk 5816 ** byte 0,1 : length 5817 ** byte 2 : command code 0x40 5818 ** byte 3 : device # 5819 ** byte 4 : scsi channel (0/1) 5820 ** byte 5 : scsi id (0-->15) 5821 ** byte 6 : scsi lun (0-->7) 5822 ** byte 7 : tagged queue (1 : enabled) 5823 ** byte 8 : cache mode (1 : enabled) 5824 ** byte 9 : max speed (0/1/2/3/4, async/20/40/80/160 for scsi) 5825 ** (0/1/2/3/4, 33/66/100/133/150 for ide ) 5826 ** 5827 ** GUI_MODIFY_PASS_THROUGH : Modify pass through disk 5828 ** byte 0,1 : length 5829 ** byte 2 : command code 0x41 5830 ** byte 3 : device # 5831 ** byte 4 : scsi channel (0/1) 5832 ** byte 5 : scsi id (0-->15) 5833 ** byte 6 : scsi lun (0-->7) 5834 ** byte 7 : tagged queue (1 : enabled) 5835 ** byte 8 : cache mode (1 : enabled) 5836 ** byte 9 : max speed (0/1/2/3/4, async/20/40/80/160 for scsi) 5837 ** (0/1/2/3/4, 33/66/100/133/150 for ide ) 5838 ** 5839 ** GUI_DELETE_PASS_THROUGH : Delete pass through disk 5840 ** byte 0,1 : length 5841 ** byte 2 : command code 0x42 5842 ** byte 3 : device# to be deleted 5843 ** 5844 ** GUI_IDENTIFY_DEVICE : Identify Device 5845 ** byte 0,1 : length 5846 ** byte 2 : command code 0x43 5847 ** byte 3 : Flash Method(0:flash selected, 1:flash not selected) 5848 ** byte 4/5/6/7 : IDE device mask to be flashed 5849 ** note .... no response data available 5850 ** 5851 ** GUI_CREATE_RAIDSET : Create Raid Set 5852 ** byte 0,1 : length 5853 ** byte 2 : command code 0x50 5854 ** byte 3/4/5/6 : device mask 5855 ** byte 7-22 : raidset name (if byte 7 == 0:use default) 5856 ** 5857 ** GUI_DELETE_RAIDSET : Delete Raid Set 5858 ** byte 0,1 : length 5859 ** byte 2 : command code 0x51 5860 ** byte 3 : raidset# 5861 ** 5862 ** GUI_EXPAND_RAIDSET : Expand Raid Set 5863 ** byte 0,1 : length 5864 ** byte 2 : command code 0x52 5865 ** byte 3 : raidset# 5866 ** byte 4/5/6/7 : device mask for expansion 5867 ** byte 8/9/10 : (8:0 no change, 1 change, 0xff:terminate, 9:new raid level,10:new stripe size 0/1/2/3/4/5->4/8/16/32/64/128K ) 5868 ** byte 11/12/13 : repeat for each volume in the raidset .... 5869 ** 5870 ** GUI_ACTIVATE_RAIDSET : Activate incomplete raid set 5871 ** byte 0,1 : length 5872 ** byte 2 : command code 0x53 5873 ** byte 3 : raidset# 5874 ** 5875 ** GUI_CREATE_HOT_SPARE : Create hot spare disk 5876 ** byte 0,1 : length 5877 ** byte 2 : command code 0x54 5878 ** byte 3/4/5/6 : device mask for hot spare creation 5879 ** 5880 ** GUI_DELETE_HOT_SPARE : Delete hot spare disk 5881 ** byte 0,1 : length 5882 ** byte 2 : command code 0x55 5883 ** byte 3/4/5/6 : device mask for hot spare deletion 5884 ** 5885 ** GUI_CREATE_VOLUME : Create volume set 5886 ** byte 0,1 : length 5887 ** byte 2 : command code 0x60 5888 ** byte 3 : raidset# 5889 ** byte 4-19 : volume set name (if byte4 == 0, use default) 5890 ** byte 20-27 : volume capacity (blocks) 5891 ** byte 28 : raid level 5892 ** byte 29 : stripe size (0/1/2/3/4/5->4/8/16/32/64/128K) 5893 ** byte 30 : channel 5894 ** byte 31 : ID 5895 ** byte 32 : LUN 5896 ** byte 33 : 1 enable tag 5897 ** byte 34 : 1 enable cache 5898 ** byte 35 : speed (0/1/2/3/4->async/20/40/80/160 for scsi) 5899 ** (0/1/2/3/4->33/66/100/133/150 for IDE ) 5900 ** byte 36 : 1 to select quick init 5901 ** 5902 ** GUI_MODIFY_VOLUME : Modify volume Set 5903 ** byte 0,1 : length 5904 ** byte 2 : command code 0x61 5905 ** byte 3 : volumeset# 5906 ** byte 4-19 : new volume set name (if byte4 == 0, not change) 5907 ** byte 20-27 : new volume capacity (reserved) 5908 ** byte 28 : new raid level 5909 ** byte 29 : new stripe size (0/1/2/3/4/5->4/8/16/32/64/128K) 5910 ** byte 30 : new channel 5911 ** byte 31 : new ID 5912 ** byte 32 : new LUN 5913 ** byte 33 : 1 enable tag 5914 ** byte 34 : 1 enable cache 5915 ** byte 35 : speed (0/1/2/3/4->async/20/40/80/160 for scsi) 5916 ** (0/1/2/3/4->33/66/100/133/150 for IDE ) 5917 ** 5918 ** GUI_DELETE_VOLUME : Delete volume set 5919 ** byte 0,1 : length 5920 ** byte 2 : command code 0x62 5921 ** byte 3 : volumeset# 5922 ** 5923 ** GUI_START_CHECK_VOLUME : Start volume consistency check 5924 ** byte 0,1 : length 5925 ** byte 2 : command code 0x63 5926 ** byte 3 : volumeset# 5927 ** 5928 ** GUI_STOP_CHECK_VOLUME : Stop volume consistency check 5929 ** byte 0,1 : length 5930 ** byte 2 : command code 0x64 5931 ** --------------------------------------------------------------------- 5932 ** 4. Returned data 5933 ** --------------------------------------------------------------------- 5934 ** (A) Header : 3 bytes sequence (0x5E, 0x01, 0x61) 5935 ** (B) Length : 2 bytes (low byte 1st, excludes length and checksum byte) 5936 ** (C) status or data : 5937 ** <1> If length == 1 ==> 1 byte status code 5938 ** #define GUI_OK 0x41 5939 ** #define GUI_RAIDSET_NOT_NORMAL 0x42 5940 ** #define GUI_VOLUMESET_NOT_NORMAL 0x43 5941 ** #define GUI_NO_RAIDSET 0x44 5942 ** #define GUI_NO_VOLUMESET 0x45 5943 ** #define GUI_NO_PHYSICAL_DRIVE 0x46 5944 ** #define GUI_PARAMETER_ERROR 0x47 5945 ** #define GUI_UNSUPPORTED_COMMAND 0x48 5946 ** #define GUI_DISK_CONFIG_CHANGED 0x49 5947 ** #define GUI_INVALID_PASSWORD 0x4a 5948 ** #define GUI_NO_DISK_SPACE 0x4b 5949 ** #define GUI_CHECKSUM_ERROR 0x4c 5950 ** #define GUI_PASSWORD_REQUIRED 0x4d 5951 ** <2> If length > 1 ==> data block returned from controller and the contents depends on the command code 5952 ** (E) Checksum : checksum of length and status or data byte 5953 ************************************************************************** 5954 */ 5955