1 /* 2 *********************************************************************************************** 3 ** O.S : FreeBSD 4 ** FILE NAME : arcmsr.h 5 ** BY : Erich Chen 6 ** Description: SCSI RAID Device Driver for 7 ** ARECA (ARC1110/1120/1210/1220) SATA RAID HOST Adapter 8 ** ARCMSR RAID Host adapter[RAID controller:INTEL 331(PCI-X) 341(PCI-EXPRESS) chip set] 9 *********************************************************************************************** 10 ************************************************************************ 11 ** Redistribution and use in source and binary forms,with or without 12 ** modification,are permitted provided that the following conditions 13 ** are met: 14 ** 1. Redistributions of source code must retain the above copyright 15 ** notice,this list of conditions and the following disclaimer. 16 ** 2. Redistributions in binary form must reproduce the above copyright 17 ** notice,this list of conditions and the following disclaimer in the 18 ** documentation and/or other materials provided with the distribution. 19 ** 3. The name of the author may not be used to endorse or promote products 20 ** derived from this software without specific prior written permission. 21 ** 22 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 ** IMPLIED WARRANTIES,INCLUDING,BUT NOT LIMITED TO,THE IMPLIED WARRANTIES 24 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,INDIRECT, 26 ** INCIDENTAL,SPECIAL,EXEMPLARY,OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT 27 ** NOT LIMITED TO,PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 ** DATA,OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 29 ** THEORY OF LIABILITY,WHETHER IN CONTRACT,STRICT LIABILITY,OR TORT 30 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 31 ** THIS SOFTWARE,EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 ************************************************************************** 33 ** $FreeBSD$ 34 */ 35 #define ARCMSR_DRIVER_VERSION "Driver Version 1.20.00.02" 36 #define ARCMSR_SCSI_INITIATOR_ID 16 37 #define ARCMSR_DEV_SECTOR_SIZE 512 38 #define ARCMSR_MAX_XFER_SECTORS 256 39 #define ARCMSR_MAX_XFER_LEN ARCMSR_MAX_XFER_SECTORS * ARCMSR_DEV_SECTOR_SIZE /*128k*/ 40 #define ARCMSR_MAX_TARGETID 16 /*16 max target id + 1*/ 41 #define ARCMSR_MAX_TARGETLUN 8 /*8*/ 42 #define ARCMSR_MAX_CHIPTYPE_NUM 4 43 #define ARCMSR_MAX_OUTSTANDING_CMD 256 44 #define ARCMSR_MAX_START_JOB 257 45 #define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_OUTSTANDING_CMD 46 #define ARCMSR_MAX_FREESRB_NUM 320 47 #define ARCMSR_MAX_DPC 16 /* defer procedure call */ 48 #define ARCMSR_MAX_QBUFFER 4096 /* ioctl QBUFFER */ 49 #define ARCMSR_MAX_SG_ENTRIES 38 /* max 38*/ 50 #define ARCMSR_MAX_ADAPTER 4 51 /* 52 ********************************************************************* 53 */ 54 typedef int8_t CHAR,*PCHAR; 55 typedef int16_t SHORT,*PSHORT; 56 typedef int32_t LONG,*PLONG; 57 typedef int64_t LONG64,*PLONG64; 58 typedef u_int8_t UCHAR,*PUCHAR; 59 typedef u_int16_t USHORT,*PUSHORT; 60 typedef u_int32_t ULONG,*PULONG; 61 typedef u_int64_t ULONG64,*PULONG64; 62 typedef void VOID,*PVOID; 63 typedef void (*DPCFUN) (void*); 64 typedef struct _MU MU,*PMU; 65 typedef struct _SRB SRB,*PSRB; 66 typedef struct _ACB ACB,*PACB; 67 typedef struct _HCB HCB,*PHCB; 68 typedef struct _DPC DPC,*PDPC; 69 typedef struct _EVENT EVENT,*PEVENT; 70 typedef struct _QBUFFER QBUFFER,*PQBUFFER; 71 typedef struct _SG32ENTRY SG32ENTRY,*PSG32ENTRY; 72 typedef struct _SG64ENTRY SG64ENTRY,*PSG64ENTRY; 73 typedef struct _SGENTRY_UNION SGENTRY_UNION,PSGENTRY_UNION; 74 typedef struct _SYSTEMTIME SYSTEMTIME,*PSYSTEMTIME; 75 typedef struct _TIMERECORD TIMERECORD,*PTIMERECORD; 76 typedef struct _SENSE_DATA SENSE_DATA, *PSENSE_DATA; 77 typedef struct _ARCMSR_PCIINFO ARCMSR_PCIINFO,*PARCMSR_PCIINFO; 78 typedef struct _ARCMSR_CDB ARCMSR_CDB,*PARCMSR_CDB; 79 typedef struct _CMD_IO_CONTROL CMD_IO_CONTROL,*PCMD_IO_CONTROL; 80 typedef struct _CMD_IOCTL_FIELD CMD_IOCTL_FIELD,*PCMD_IOCTL_FIELD; 81 #if defined(__x86_64__) || defined(__amd64__) || defined(__ia64__) 82 typedef uint64_t CPT2INT,*PCPT2INT; 83 typedef uint64_t CINT2P,*PCINT2P; 84 typedef uint64_t VIR2PHY_OFFSET,*PVIR2PHY_OFFSET; 85 #else 86 typedef uint32_t CPT2INT,*PCPT2INT; 87 typedef uint32_t CINT2P,*PCINT2P; 88 typedef uint32_t VIR2PHY_OFFSET,*PVIR2PHY_OFFSET; 89 #endif 90 /* 91 ********************************************************************* 92 */ 93 #ifndef BOOLEAN 94 typedef u_int8_t BOOLEAN; 95 #endif 96 #ifndef TRUE 97 #define TRUE 1 98 #endif 99 #ifndef FALSE 100 #define FALSE 0 101 #endif 102 /* 103 ********************************************************************************** 104 ** 105 ********************************************************************************** 106 */ 107 #define CHIP_REG_READ8(a) (UCHAR)(readb((PUCHAR)(a))) 108 #define CHIP_REG_READ16(a) (USHORT)(readw((PUSHORT)(a))) 109 #define CHIP_REG_READ32(a) (ULONG)(readl((PULONG)(a))) 110 #define CHIP_REG_WRITE8(a,d) writeb((PUCHAR)(a),(UCHAR)(d)) 111 #define CHIP_REG_WRITE16(a,d) writew((PUSHORT)(a),(USHORT)(d)) 112 #define CHIP_REG_WRITE32(a,d) writel((PULONG)(a),(ULONG)(d)) 113 /* 114 ********************************************************************************** 115 ** 116 ********************************************************************************** 117 */ 118 #define PCIVendorIDARECA 0x17D3 /* Vendor ID */ 119 #define PCIDeviceIDARC1110 0x1110 /* Device ID */ 120 #define PCIDeviceIDARC1120 0x1120 /* Device ID */ 121 #define PCIDeviceIDARC1130 0x1130 /* Device ID */ 122 #define PCIDeviceIDARC1160 0x1160 /* Device ID */ 123 #define PCIDeviceIDARC1210 0x1210 /* Device ID */ 124 #define PCIDeviceIDARC1220 0x1220 /* Device ID */ 125 #define PCIDeviceIDARC1230 0x1230 /* Device ID */ 126 #define PCIDeviceIDARC1260 0x1260 /* Device ID */ 127 128 #define PCIDevVenIDARC1110 0x111017D3 /* Vendor Device ID */ 129 #define PCIDevVenIDARC1120 0x112017D3 /* Vendor Device ID */ 130 #define PCIDevVenIDARC1130 0x113017D3 /* Vendor Device ID */ 131 #define PCIDevVenIDARC1160 0x116017D3 /* Vendor Device ID */ 132 #define PCIDevVenIDARC1210 0x121017D3 /* Vendor Device ID */ 133 #define PCIDevVenIDARC1220 0x122017D3 /* Vendor Device ID */ 134 #define PCIDevVenIDARC1230 0x123017D3 /* Vendor Device ID */ 135 #define PCIDevVenIDARC1260 0x126017D3 /* Vendor Device ID */ 136 137 #define PCI_BASE_ADDR0 0x10 138 #define PCI_BASE_ADDR1 0x14 139 #define PCI_BASE_ADDR2 0x18 140 #define PCI_BASE_ADDR3 0x1C 141 #define PCI_BASE_ADDR4 0x20 142 #define PCI_BASE_ADDR5 0x24 143 /* 144 ********************************************************************************** 145 ** 146 ********************************************************************************** 147 */ 148 #define ARCMSR_SCSICMD_IOCTL 0x77 149 #define ARCMSR_CDEVSW_IOCTL 0x88 150 #define ARC_IOCTL_SUCCESS 0x00 151 /* 152 ********************************************************************************** 153 ** 154 ********************************************************************************** 155 */ 156 #define get_min(x,y) ((x) < (y) ? (x) : (y)) 157 #define get_max(x,y) ((x) < (y) ? (y) : (x)) 158 /* CAM SIM entry points */ 159 #define arcmsr_ccbsrb_ptr spriv_ptr0 160 #define arcmsr_ccbacb_ptr spriv_ptr1 161 #define dma_addr_hi32(a) ((ULONG) (0xffffffff & (((ULONG64)(a))>>32))) 162 #define dma_addr_lo32(a) ((ULONG) (0xffffffff & (((ULONG64)(a))))) 163 /* 164 ************************************************************************ 165 ** IOCTL CONTROL CODE 166 ** =================== 167 ** IOCtl definitions 168 ** =================== 169 ** Define the various device type values. Note that values used by Microsoft 170 ** Corporation are in the range 0x0000 - 0x7FFF, and 0x8000 - 0xFFFF are 171 ** reserved for use by customers. 172 ** 173 ** #define IOCTL_SCSI_MINIPORT_IO_CONTROL 0x8001 174 ** 175 ** Macro definition for defining IOCTL and FSCTL function control codes. 176 ** Note that function codes 0x000 - 0x7FF are reserved for Microsoft 177 ** Corporation, and 0x800 - 0xFFF are reserved for customers. 178 ** 179 ** #define RETURNCODE0x0000003F 0x850 180 ** #define SMP_RETURN_3F CTL_CODE(IOCTL_SCSI_MINIPORT_IO_CONTROL, RETURNCODE0x0000003F, METHOD_BUFFERED, FILE_ANY_ACCESS) 181 ** #define SMP_PRINT_STRING 0x80000001 182 **--------------- 183 ** #define IOCTL_Device_Function CTL_CODE(DeviceType, Function, Method, Access) 184 **--------------- 185 ** _31_ _30..16_ ___15_14___ _13_ _12...2_ _1_0_ 186 ** Common DeviceType Required Access Custom FunctionCode TransferType 187 ** 188 **--------------- 189 **DeviceType 190 ** Identifies the device type. 191 ** This value must match the value that is set in the DeviceType member of the driver's DEVICE_OBJECT structure. 192 ** (See Specifying Device Types). 193 ** Values of less than 0x8000 are reserved for Microsoft. 194 ** Values of 0x8000 and higher can be used by vendors. 195 ** Note that the vendor-assigned values set the Common bit. 196 **--------------- 197 **FunctionCode 198 ** Identifies the function to be performed by the driver. 199 ** Values of less than 0x800 are reserved for Microsoft. 200 ** Values of 0x800 and higher can be used by vendors. 201 ** Note that the vendor-assigned values set the Custom bit. 202 **--------------- 203 **TransferType 204 ** Indicates how the system will pass data between the caller of DeviceIoControl 205 ** (or IoBuildDeviceIoControlRequest) and the driver that handles the IRP. 206 ** Use one of the following system-defined constants: 207 ** METHOD_BUFFERED 208 ** Specifies the buffered I/O method, which is typically used for transferring small amounts of data per request. 209 ** Most I/O control codes for device and intermediate drivers use this TransferType value. 210 ** For information about how the system specifies data buffers for METHOD_BUFFERED I/O control codes, 211 ** see Buffer Descriptions for I/O Control Codes. 212 ** For more information about buffered I/O, see Using Buffered I/O. 213 ** METHOD_IN_DIRECT or METHOD_OUT_DIRECT 214 ** Specifies the direct I/O method, which is typically used for reading or writing large amounts of data, 215 ** using DMA or PIO, that must be transferred quickly. 216 ** Specify METHOD_IN_DIRECT if the caller of DeviceIoControl or IoBuildDeviceIoControlRequest will pass data to the driver. 217 ** Specify METHOD_OUT_DIRECT if the caller of DeviceIoControl or IoBuildDeviceIoControlRequest will receive data from the driver. 218 ** For information about how the system specifies data buffers for METHOD_IN_DIRECT and METHOD_OUT_DIRECT I/O control codes, 219 ** see Buffer Descriptions for I/O Control Codes. 220 ** For more information about direct I/O, see Using Direct I/O. 221 ** METHOD_NEITHER 222 ** Specifies neither buffered nor direct I/O. 223 ** The I/O manager does not provide any system buffers or MDLs. 224 ** The IRP supplies the user-mode virtual addresses of the input and output buffers 225 ** that were specified to DeviceIoControl or IoBuildDeviceIoControlRequest,without validating or mapping them. 226 ** For information about how the system specifies data buffers for METHOD_NEITHER I/O control codes, 227 ** see Buffer Descriptions for I/O Control Codes. 228 ** This method can be used only if the driver can be guaranteed to be running in the context 229 ** of the thread that originated the I/O control request. 230 ** Only a highest-level kernel-mode driver is guaranteed to meet this condition, 231 ** so METHOD_NEITHER is seldom used for the I/O control codes that are passed to low-level device drivers. 232 ** With this method, the highest-level driver must determine whether to set up buffered 233 ** or direct access to user data on receipt of the request, 234 ** possibly must lock down the user buffer, 235 ** and must wrap its access to the user buffer in a structured exception handler (see Handling Exceptions). 236 ** Otherwise, the originating user-mode caller might change the buffered data before the driver can use it, 237 ** or the caller could be swapped out just as the driver is accessing the user buffer. 238 ** For more information, see Using Neither Buffered Nor Direct I/O. 239 **------------------- 240 **RequiredAccess 241 ** Indicates the type of access that a caller must request 242 ** when opening the file object that represents the device (see IRP_MJ_CREATE). 243 ** The I/O Manager will create IRPs and call the driver with a particular I/O control code 244 ** only if the caller has requested the specified access rights. 245 ** RequiredAccess is specified by using the following system-defined constants: 246 ** FILE_ANY_ACCESS 247 ** The I/O Manager sends the IRP for any caller that has a handle to the file object 248 ** that represents the target device object. 249 ** FILE_READ_DATA 250 ** The I/O Manager sends the IRP only for a caller with read access rights, 251 ** allowing the underlying device driver to transfer data from the device to system memory. 252 ** FILE_WRITE_DATA 253 ** The I/O Manager sends the IRP only for a caller with write access rights, 254 ** allowing the underlying device driver to transfer data from system memory to its device. 255 ** FILE_READ_DATA and FILE_WRITE_DATA can be OR'ed together 256 ** if the caller must have both read and write access rights. 257 ** Some system-defined I/O control codes have a RequiredAccess value of FILE_ANY_ACCESS. 258 ** This is especially true for I/O control codes that are sent to drivers of exclusive devices, 259 ** and for those that specify buffered I/O. 260 ************************************************************************ 261 */ 262 struct _CMD_IO_CONTROL 263 { 264 ULONG HeaderLength; 265 UCHAR Signature[8]; 266 ULONG Timeout; 267 ULONG ControlCode; 268 ULONG ReturnCode; 269 ULONG Length; 270 }; 271 /* 272 ************************************************************************************************************ 273 ** 274 ************************************************************************************************************ 275 */ 276 struct _CMD_IOCTL_FIELD 277 { 278 CMD_IO_CONTROL cmdioctl; /*ioctl header*/ 279 UCHAR ioctldatabuffer[1032];/*areca gui program does not accept more than 1031 byte*/ 280 }; 281 /*error code for StorPortLogError,ScsiPortLogError*/ 282 #define ARCMSR_IOP_ERROR_ILLEGALPCI 0x0001 283 #define ARCMSR_IOP_ERROR_VENDORID 0x0002 284 #define ARCMSR_IOP_ERROR_DEVICEID 0x0002 285 #define ARCMSR_IOP_ERROR_ILLEGALCDB 0x0003 286 #define ARCMSR_IOP_ERROR_UNKNOW_CDBERR 0x0004 287 #define ARCMSR_SYS_ERROR_MEMORY_ALLOCATE 0x0005 288 #define ARCMSR_SYS_ERROR_MEMORY_CROSS4G 0x0006 289 #define ARCMSR_SYS_ERROR_MEMORY_LACK 0x0007 290 #define ARCMSR_SYS_ERROR_MEMORY_RANGE 0x0008 291 #define ARCMSR_SYS_ERROR_DEVICE_BASE 0x0009 292 #define ARCMSR_SYS_ERROR_PORT_VALIDATE 0x000A 293 /*DeviceType*/ 294 #define ARECA_SATA_RAID 0x90000000 295 /*FunctionCode*/ 296 #define FUNCTION_READ_RQBUFFER 0x0801 297 #define FUNCTION_WRITE_WQBUFFER 0x0802 298 #define FUNCTION_CLEAR_RQBUFFER 0x0803 299 #define FUNCTION_CLEAR_WQBUFFER 0x0804 300 #define FUNCTION_CLEAR_ALLQBUFFER 0x0805 301 #define FUNCTION_RETURN_CODE_3F 0x0806 302 #define FUNCTION_SAY_HELLO 0x0807 303 /* ARECA IO CONTROL CODE*/ 304 #define ARCMSR_IOCTL_READ_RQBUFFER _IOWR('F', FUNCTION_READ_RQBUFFER, CMD_IOCTL_FIELD) 305 #define ARCMSR_IOCTL_WRITE_WQBUFFER _IOWR('F', FUNCTION_WRITE_WQBUFFER, CMD_IOCTL_FIELD) 306 #define ARCMSR_IOCTL_CLEAR_RQBUFFER _IOWR('F', FUNCTION_CLEAR_RQBUFFER, CMD_IOCTL_FIELD) 307 #define ARCMSR_IOCTL_CLEAR_WQBUFFER _IOWR('F', FUNCTION_CLEAR_WQBUFFER, CMD_IOCTL_FIELD) 308 #define ARCMSR_IOCTL_CLEAR_ALLQBUFFER _IOWR('F', FUNCTION_CLEAR_ALLQBUFFER, CMD_IOCTL_FIELD) 309 #define ARCMSR_IOCTL_RETURN_CODE_3F _IOWR('F', FUNCTION_RETURN_CODE_3F, CMD_IOCTL_FIELD) 310 #define ARCMSR_IOCTL_SAY_HELLO _IOWR('F', FUNCTION_SAY_HELLO, CMD_IOCTL_FIELD) 311 /* ARECA IOCTL ReturnCode */ 312 #define ARCMSR_IOCTL_RETURNCODE_OK 0x01 313 #define ARCMSR_IOCTL_RETURNCODE_ERROR 0x06 314 #define ARCMSR_IOCTL_RETURNCODE_3F 0x3F 315 /* 316 ************************************************************* 317 ** busmaster DMA related defines end 318 ************************************************************* 319 */ 320 #define get_min(x,y) ((x) < (y) ? (x) : (y)) 321 #define get_max(x,y) ((x) < (y) ? (y) : (x)) 322 /* 323 ************************************************************* 324 ** structure for holding DMA address data 325 ************************************************************* 326 */ 327 #define IS_SG64_ADDR 0x01000000 /* bit24 */ 328 struct _SG32ENTRY /* size 8 bytes */ 329 { /* length bit 24 == 0 */ 330 ULONG length; /* high 8 bit == flag,low 24 bit == length */ 331 ULONG address; 332 }; 333 struct _SG64ENTRY /* size 12 bytes */ 334 { /* length bit 24 == 1 */ 335 ULONG length; /* high 8 bit == flag,low 24 bit == length */ 336 ULONG address; 337 ULONG addresshigh; 338 }; 339 struct _SGENTRY_UNION 340 { 341 union 342 { 343 SG32ENTRY sg32entry; /* 30h Scatter gather address */ 344 SG64ENTRY sg64entry; /* 30h */ 345 }u; 346 }; 347 /* 348 **struct scatterlist 349 **{ 350 ** char * address; // Location data is to be transferred to 351 ** char * alt_address; // Location of actual if address is a dma indirect buffer. NULL otherwise 352 ** unsigned int length; 353 **}; 354 */ 355 /* 356 ************************************************************* 357 ** 358 ************************************************************* 359 */ 360 struct _ARCMSR_PCIINFO 361 { 362 USHORT vendor_id; 363 USHORT device_id; 364 USHORT irq; 365 USHORT reserved; 366 }; 367 /* 368 ************************************************************* 369 ** DPC 370 ** defer procedure call 371 ************************************************************* 372 */ 373 struct _DPC 374 { 375 VOID (*dpcfun) (VOID *); 376 VOID *arg; 377 }; 378 /* 379 ************************************************************* 380 ** time represented in ULONG format 381 ************************************************************* 382 */ 383 struct _TIMERECORD 384 { 385 ULONG seconds:6; /* bit 05,04,03,02,01,00: 0 - 59 */ 386 ULONG minutes:6; /* bit 11,10,09,08,07,06: 0 - 59 */ 387 ULONG month:4; /* bit 15,14,13,12: 1 - 12 */ 388 ULONG hours:6; /* bit 21,20,19,18,17,16: 0 - 59 */ 389 ULONG day:5; /* bit 26,25,24,23,22: 1 - 31 */ 390 ULONG year:5; /* bit 31,30,29,28,27: 0=2000,31=2031 */ 391 }; 392 /* 393 ********************************** 394 ** Inquiry Data format 395 ** typedef struct _INQUIRYDATA 396 ** { 397 ** UCHAR DeviceType : 5; 398 ** UCHAR DeviceTypeQualifier : 3; 399 ** UCHAR DeviceTypeModifier : 7; 400 ** UCHAR RemovableMedia : 1; 401 ** UCHAR Versions; 402 ** UCHAR ResponseDataFormat : 4; 403 ** UCHAR HiSupport : 1; 404 ** UCHAR NormACA : 1; 405 ** UCHAR ReservedBit : 1; 406 ** UCHAR AERC : 1; 407 ** UCHAR AdditionalLength; 408 ** UCHAR Reserved[2]; 409 ** UCHAR SoftReset : 1; 410 ** UCHAR CommandQueue : 1; 411 ** UCHAR Reserved2 : 1; 412 ** UCHAR LinkedCommands : 1; 413 ** UCHAR Synchronous : 1; 414 ** UCHAR Wide16Bit : 1; 415 ** UCHAR Wide32Bit : 1; 416 ** UCHAR RelativeAddressing : 1; 417 ** UCHAR VendorId[8]; 418 ** UCHAR ProductId[16]; 419 ** UCHAR ProductRevisionLevel[4]; 420 ** UCHAR VendorSpecific[20]; 421 ** UCHAR Reserved3[40]; 422 ** } INQUIRYDATA, *PINQUIRYDATA; 423 ********************************** 424 */ 425 struct _QBUFFER 426 { 427 ULONG data_len; 428 UCHAR data[124]; 429 }; 430 /* 431 ************************************************************************************************ 432 ** ARECA FIRMWARE SPEC 433 ************************************************************************************************ 434 ** Usage of IOP331 adapter 435 ** (All In/Out is in IOP331's view) 436 ** 1. Message 0 --> InitThread message and retrun code 437 ** 2. Doorbell is used for RS-232 emulation 438 ** inDoorBell : bit0 -- data in ready (DRIVER DATA WRITE OK) 439 ** bit1 -- data out has been read (DRIVER DATA READ OK) 440 ** outDooeBell: bit0 -- data out ready (IOP331 DATA WRITE OK) 441 ** bit1 -- data in has been read (IOP331 DATA READ OK) 442 ** 3. Index Memory Usage 443 ** offset 0xf00 : for RS232 out (request buffer) 444 ** offset 0xe00 : for RS232 in (scratch buffer) 445 ** offset 0xa00 : for inbound message code message_wbuffer (driver to IOP331) 446 ** offset 0x800 : for outbound message code message_rbuffer (IOP331 to driver) 447 ** 4. RS-232 emulation 448 ** Currently 128 byte buffer is used 449 ** 1st ULONG : Data length (1--124) 450 ** Byte 4--127 : Max 124 bytes of data 451 ** 5. PostQ 452 ** All SCSI Command must be sent through postQ: 453 ** (inbound queue port) Request frame must be 32 bytes aligned 454 ** # bit27--bit31 => flag for post srb 455 ** # bit0--bit26 => real address (bit27--bit31) of post arcmsr_cdb 456 ** bit31 : 0 : 256 bytes frame 457 ** 1 : 512 bytes frame 458 ** bit30 : 0 : normal request 459 ** 1 : BIOS request 460 ** bit29 : reserved 461 ** bit28 : reserved 462 ** bit27 : reserved 463 ** ------------------------------------------------------------------------------- 464 ** (outbount queue port) Request reply 465 ** # bit27--bit31 => flag for reply 466 ** # bit0--bit26 => real address (bit27--bit31) of reply arcmsr_cdb 467 ** bit31 : must be 0 (for this type of reply) 468 ** bit30 : reserved for BIOS handshake 469 ** bit29 : reserved 470 ** bit28 : 0 : no error, ignore AdapStatus/DevStatus/SenseData 471 ** 1 : Error, error code in AdapStatus/DevStatus/SenseData 472 ** bit27 : reserved 473 ** 6. BIOS request 474 ** All BIOS request is the same with request from PostQ 475 ** Except : 476 ** Request frame is sent from configuration space 477 ** offset: 0x78 : Request Frame (bit30 == 1) 478 ** offset: 0x18 : writeonly to generate IRQ to IOP331 479 ** Completion of request: 480 ** (bit30 == 0, bit28==err flag) 481 ** 7. Definition of SGL entry (structure) 482 ** 8. Message1 Out - Diag Status Code (????) 483 ** 9. Message0 message code : 484 ** 0x00 : NOP 485 ** 0x01 : Get Config ->offset 0xa00 :for outbound message code message_rbuffer (IOP331 to driver) 486 ** Signature 0x87974060(4) 487 ** Request len 0x00000200(4) 488 ** # of queue 0x00000100(4) 489 ** SDRAM Size 0x00000100(4)-->256 MB 490 ** IDE Channels 0x00000008(4) 491 ** vendor 40 bytes char 492 ** model 8 bytes char 493 ** FirmVer 16 bytes char 494 ** Device Map 16 Bytes 495 ** FirmwareVersion DWORD <== Added for checking of new firmware capability 496 ** 0x02 : Set Config ->offset 0xa00 : for inbound message code message_wbuffer (driver to IOP331) 497 ** Signature 0x87974063(4) 498 ** UPPER32 of Request Frame (4)-->Driver Only 499 ** 0x03 : Reset (Abort all queued Command) 500 ** 0x04 : Stop Background Activity 501 ** 0x05 : Flush Cache 502 ** 0x06 : Start Background Activity (re-start if background is halted) 503 ** 0x07 : Check If Host Command Pending (Novell May Need This Function) 504 ** 0x08 : Set controller time ->offset 0xa00 : for inbound message code message_wbuffer (driver to IOP331) 505 ** byte 0 : 0xaa <-- signature 506 ** byte 1 : 0x55 <-- signature 507 ** byte 2 : year (04) 508 ** byte 3 : month (1..12) 509 ** byte 4 : date (1..31) 510 ** byte 5 : hour (0..23) 511 ** byte 6 : minute (0..59) 512 ** byte 7 : second (0..59) 513 ************************************************************************************************ 514 */ 515 /* message code of inbound message register */ 516 #define ARCMSR_INBOUND_MESG0_NOP 0x00000000 517 #define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001 518 #define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002 519 #define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003 520 #define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004 521 #define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005 522 #define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006 523 #define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007 524 #define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008 525 /* doorbell interrupt generator */ 526 #define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001 527 #define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002 528 #define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001 529 #define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002 530 /* srb areca cdb flag */ 531 #define ARCMSR_SRBPOST_FLAG_SGL_BSIZE 0x80000000 532 #define ARCMSR_SRBPOST_FLAG_IAM_BIOS 0x40000000 533 #define ARCMSR_SRBREPLY_FLAG_IAM_BIOS 0x40000000 534 #define ARCMSR_SRBREPLY_FLAG_ERROR 0x10000000 535 /* outbound firmware ok */ 536 #define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000 537 /* 538 ************************************************************************************************ 539 ** size 0x1F8 (504) 540 ************************************************************************************************ 541 */ 542 struct _ARCMSR_CDB 543 { 544 UCHAR Bus; /* 00h should be 0 */ 545 UCHAR TargetID; /* 01h should be 0--15 */ 546 UCHAR LUN; /* 02h should be 0--7 */ 547 UCHAR Function; /* 03h should be 1 */ 548 549 UCHAR CdbLength; /* 04h not used now */ 550 UCHAR sgcount; /* 05h */ 551 UCHAR Flags; /* 06h */ 552 #define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01 /* bit 0: 0(256) / 1(512) bytes */ 553 #define ARCMSR_CDB_FLAG_BIOS 0x02 /* bit 1: 0(from driver) / 1(from BIOS) */ 554 #define ARCMSR_CDB_FLAG_WRITE 0x04 /* bit 2: 0(Data in) / 1(Data out) */ 555 #define ARCMSR_CDB_FLAG_SIMPLEQ 0x00 /* bit 4/3 ,00 : simple Q,01 : head of Q,10 : ordered Q */ 556 #define ARCMSR_CDB_FLAG_HEADQ 0x08 557 #define ARCMSR_CDB_FLAG_ORDEREDQ 0x10 558 UCHAR Reserved1; /* 07h */ 559 560 ULONG Context; /* 08h Address of this request */ 561 ULONG DataLength; /* 0ch not used now */ 562 563 UCHAR Cdb[16]; /* 10h SCSI CDB */ 564 /* 565 ******************************************************** 566 **Device Status : the same from SCSI bus if error occur 567 ** SCSI bus status codes. 568 ******************************************************** 569 */ 570 UCHAR DeviceStatus; /* 20h if error */ 571 #define SCSISTAT_GOOD 0x00 572 #define SCSISTAT_CHECK_CONDITION 0x02 573 #define SCSISTAT_CONDITION_MET 0x04 574 #define SCSISTAT_BUSY 0x08 575 #define SCSISTAT_INTERMEDIATE 0x10 576 #define SCSISTAT_INTERMEDIATE_COND_MET 0x14 577 #define SCSISTAT_RESERVATION_CONFLICT 0x18 578 #define SCSISTAT_COMMAND_TERMINATED 0x22 579 #define SCSISTAT_QUEUE_FULL 0x28 580 #define ARCMSR_DEV_SELECT_TIMEOUT 0xF0 581 #define ARCMSR_DEV_ABORTED 0xF1 582 #define ARCMSR_DEV_INIT_FAIL 0xF2 583 584 UCHAR SenseData[15]; /* 21h output */ 585 586 union 587 { 588 SG32ENTRY sg32entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h Scatter gather address */ 589 SG64ENTRY sg64entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h */ 590 } u; 591 }; 592 /* 593 ********************************************************************* 594 ** Command Control Block (SrbExtension) 595 ** SRB must be not cross page boundary,and the order from offset 0 596 ** structure describing an ATA disk request 597 ** this SRB length must be 32 bytes boundary 598 ********************************************************************* 599 */ 600 struct _SRB 601 { 602 ARCMSR_CDB arcmsr_cdb; /* 0-503 (size of CDB=504): arcmsr messenger scsi command descriptor size 504 bytes */ 603 ULONG cdb_shifted_phyaddr; /* 504-507 */ 604 ULONG reserved1; /* 508-511*/ 605 /* ======================512+32 bytes======================== */ 606 #if defined(__x86_64__) || defined(__amd64__) || defined(__ia64__) 607 union ccb *pccb; /* 512-515 516-519 pointer of freebsd scsi command */ 608 PACB pACB; /* 520-523 524-527 */ 609 bus_dmamap_t dmamap; /* 528-531 532-535 */ 610 USHORT srb_flags; /* 536-537 */ 611 #define SRB_FLAG_READ 0x0000 612 #define SRB_FLAG_WRITE 0x0001 613 #define SRB_FLAG_ERROR 0x0002 614 #define SRB_FLAG_FLUSHCACHE 0x0004 615 #define SRB_FLAG_MASTER_ABORTED 0x0008 616 USHORT startdone; /* 538-539 */ 617 #define ARCMSR_SRB_DONE 0x0000 618 #define ARCMSR_SRB_START 0x55AA 619 #define ARCMSR_SRB_ABORTED 0xAA55 620 #define ARCMSR_SRB_ILLEGAL 0xFFFF 621 ULONG reserved2; /* 540-543 */ 622 #else 623 union ccb *pccb; /* 512-515 pointer of freebsd scsi command */ 624 PACB pACB; /* 516-519 */ 625 bus_dmamap_t dmamap; /* 520-523 */ 626 USHORT srb_flags; /* 524-525 */ 627 #define SRB_FLAG_READ 0x0000 628 #define SRB_FLAG_WRITE 0x0001 629 #define SRB_FLAG_ERROR 0x0002 630 #define SRB_FLAG_FLUSHCACHE 0x0004 631 #define SRB_FLAG_MASTER_ABORTED 0x0008 632 USHORT startdone; /* 526-527 */ 633 #define ARCMSR_SRB_DONE 0x0000 634 #define ARCMSR_SRB_START 0x55AA 635 #define ARCMSR_SRB_ABORTED 0xAA55 636 #define ARCMSR_SRB_ILLEGAL 0xFFFF 637 ULONG reserved2[4]; /* 528-531 532-535 536-539 540-543 */ 638 #endif 639 /* ========================================================== */ 640 }; 641 /* 642 ********************************************************************* 643 ** Adapter Control Block 644 ** 645 ********************************************************************* 646 */ 647 struct _ACB 648 { 649 bus_space_tag_t btag; 650 bus_space_handle_t bhandle; 651 bus_dma_tag_t parent_dmat; 652 bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */ 653 bus_dma_tag_t srb_dmat; /* dmat for freesrb */ 654 bus_dmamap_t srb_dmamap; 655 device_t pci_dev; 656 #if __FreeBSD_version < 503000 657 dev_t ioctl_dev; 658 #else 659 struct cdev *ioctl_dev; 660 #endif 661 int pci_unit; 662 663 struct resource *sys_res_arcmsr; 664 struct resource *irqres; 665 void *ih; /*interrupt handle*/ 666 667 /* Hooks into the CAM XPT */ 668 struct cam_sim *psim; 669 struct cam_path *ppath; 670 PCHAR uncacheptr; 671 VIR2PHY_OFFSET vir2phy_offset; /* Offset is used in making arc cdb physical to virtual calculations */ 672 ULONG outbound_int_enable; 673 674 PMU pmu; /* message unit ATU inbound base address0 */ 675 676 USHORT reserved; 677 USHORT acb_flags; /* */ 678 #define ACB_F_SCSISTOPADAPTER 0x0001 679 #define ACB_F_MSG_STOP_BGRB 0x0002 /* stop RAID background rebuild */ 680 #define ACB_F_MSG_START_BGRB 0x0004 /* stop RAID background rebuild */ 681 #define ACB_F_IOPDATA_OVERFLOW 0x0008 /* iop ioctl data rqbuffer overflow */ 682 #define ACB_F_IOCTL_WQBUFFER_CLEARED 0x0010 /* ioctl clear wqbuffer */ 683 #define ACB_F_IOCTL_RQBUFFER_CLEARED 0x0020 /* ioctl clear rqbuffer */ 684 #define ACB_F_IOCTL_OPEN 0x0040 685 #define ACB_F_IOP_INITED 0x0080 /* iop init */ 686 #define ACB_F_STOP_THREAD 0x0100 /* kernel thread flag */ 687 #define ACB_F_MAPFREESRB_FAILD 0x0200 /* arcmsr_map_freesrb faild */ 688 689 PSRB pfreesrb; 690 691 PSRB psrbwait2go[ARCMSR_MAX_OUTSTANDING_CMD]; 692 LONG srbwait2gocount; 693 LONG srboutstandingcount; 694 695 PSRB psrbringQ[ARCMSR_MAX_FREESRB_NUM]; /* srb pointer array */ 696 LONG srb_doneindex; /* done srb array index */ 697 LONG srb_startindex; /* start srb array index */ 698 699 UCHAR rqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for read from 80331 */ 700 LONG rqbuf_firstindex; /* first of read buffer */ 701 LONG rqbuf_lastindex; /* last of read buffer */ 702 703 UCHAR wqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for write to 80331 */ 704 LONG wqbuf_firstindex; /* first of write buffer */ 705 LONG wqbuf_lastindex; /* last of write buffer */ 706 707 arcmsr_lock_t arcmsr_kthread_lock; 708 struct proc *kthread_proc; 709 710 DPC dpcQ[ARCMSR_MAX_DPC]; /* normal dpc routines work on kernel thread */ 711 712 LONG dpcQ_head; /*array index number*/ 713 LONG dpcQ_tail; /*array index number*/ 714 };/* HW_DEVICE_EXTENSION */ 715 /* 716 ************************************************************* 717 ************************************************************* 718 */ 719 struct _SENSE_DATA 720 { 721 UCHAR ErrorCode:7; 722 UCHAR Valid:1; 723 UCHAR SegmentNumber; 724 UCHAR SenseKey:4; 725 UCHAR Reserved:1; 726 UCHAR IncorrectLength:1; 727 UCHAR EndOfMedia:1; 728 UCHAR FileMark:1; 729 UCHAR Information[4]; 730 UCHAR AdditionalSenseLength; 731 UCHAR CommandSpecificInformation[4]; 732 UCHAR AdditionalSenseCode; 733 UCHAR AdditionalSenseCodeQualifier; 734 UCHAR FieldReplaceableUnitCode; 735 UCHAR SenseKeySpecific[3]; 736 }; 737 /* 738 ********************************** 739 ** Peripheral Device Type definitions 740 ********************************** 741 */ 742 #define SCSI_DASD 0x00 /* Direct-access Device */ 743 #define SCSI_SEQACESS 0x01 /* Sequential-access device */ 744 #define SCSI_PRINTER 0x02 /* Printer device */ 745 #define SCSI_PROCESSOR 0x03 /* Processor device */ 746 #define SCSI_WRITEONCE 0x04 /* Write-once device */ 747 #define SCSI_CDROM 0x05 /* CD-ROM device */ 748 #define SCSI_SCANNER 0x06 /* Scanner device */ 749 #define SCSI_OPTICAL 0x07 /* Optical memory device */ 750 #define SCSI_MEDCHGR 0x08 /* Medium changer device */ 751 #define SCSI_COMM 0x09 /* Communications device */ 752 #define SCSI_NODEV 0x1F /* Unknown or no device type*/ 753 /* 754 ************************************************************************************************************ 755 ** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 756 ** 80331 PCI-to-PCI Bridge 757 ** PCI Configuration Space 758 ** 759 ** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 760 ** Programming Interface 761 ** ======================== 762 ** Configuration Register Address Space Groupings and Ranges 763 ** ============================================================= 764 ** Register Group Configuration Offset 765 ** ------------------------------------------------------------- 766 ** Standard PCI Configuration 00-3Fh 767 ** ------------------------------------------------------------- 768 ** Device Specific Registers 40-A7h 769 ** ------------------------------------------------------------- 770 ** Reserved A8-CBh 771 ** ------------------------------------------------------------- 772 ** Enhanced Capability List CC-FFh 773 ** ========================================================================================================== 774 ** Standard PCI [Type 1] Configuration Space Address Map 775 ** ********************************************************************************************************** 776 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 777 ** ---------------------------------------------------------------------------------------------------------- 778 ** | Device ID | Vendor ID | 00h 779 ** ---------------------------------------------------------------------------------------------------------- 780 ** | Primary Status | Primary Command | 04h 781 ** ---------------------------------------------------------------------------------------------------------- 782 ** | Class Code | RevID | 08h 783 ** ---------------------------------------------------------------------------------------------------------- 784 ** | reserved | Header Type | Primary MLT | Primary CLS | 0Ch 785 ** ---------------------------------------------------------------------------------------------------------- 786 ** | Reserved | 10h 787 ** ---------------------------------------------------------------------------------------------------------- 788 ** | Reserved | 14h 789 ** ---------------------------------------------------------------------------------------------------------- 790 ** | Secondary MLT | Subordinate Bus Number | Secondary Bus Number | Primary Bus Number | 18h 791 ** ---------------------------------------------------------------------------------------------------------- 792 ** | Secondary Status | I/O Limit | I/O Base | 1Ch 793 ** ---------------------------------------------------------------------------------------------------------- 794 ** | Non-prefetchable Memory Limit Address | Non-prefetchable Memory Base Address | 20h 795 ** ---------------------------------------------------------------------------------------------------------- 796 ** | Prefetchable Memory Limit Address | Prefetchable Memory Base Address | 24h 797 ** ---------------------------------------------------------------------------------------------------------- 798 ** | Prefetchable Memory Base Address Upper 32 Bits | 28h 799 ** ---------------------------------------------------------------------------------------------------------- 800 ** | Prefetchable Memory Limit Address Upper 32 Bits | 2Ch 801 ** ---------------------------------------------------------------------------------------------------------- 802 ** | I/O Limit Upper 16 Bits | I/O Base Upper 16 | 30h 803 ** ---------------------------------------------------------------------------------------------------------- 804 ** | Reserved | Capabilities Pointer | 34h 805 ** ---------------------------------------------------------------------------------------------------------- 806 ** | Reserved | 38h 807 ** ---------------------------------------------------------------------------------------------------------- 808 ** | Bridge Control | Primary Interrupt Pin | Primary Interrupt Line | 3Ch 809 **============================================================================================================= 810 */ 811 /* 812 **============================================================================================================= 813 ** 0x03-0x00 : 814 ** Bit Default Description 815 **31:16 0335h Device ID (DID): Indicates the unique device ID that is assigned to bridge by the PCI SIG. 816 ** ID is unique per product speed as indicated. 817 **15:00 8086h Vendor ID (VID): 16-bit field which indicates that Intel is the vendor. 818 **============================================================================================================= 819 */ 820 #define ARCMSR_PCI2PCI_VENDORID_REG 0x00 /*word*/ 821 #define ARCMSR_PCI2PCI_DEVICEID_REG 0x02 /*word*/ 822 /* 823 **============================================================================== 824 ** 0x05-0x04 : command register 825 ** Bit Default Description 826 **15:11 00h Reserved 827 ** 10 0 Interrupt Disable: Disables/Enables the generation of Interrupts on the primary bus. 828 ** The bridge does not support interrupts. 829 ** 09 0 FB2B Enable: Enables/Disables the generation of fast back to back transactions on the primary bus. 830 ** The bridge does not generate fast back to back transactions on the primary bus. 831 ** 08 0 SERR# Enable (SEE): Enables primary bus SERR# assertions. 832 ** 0=The bridge does not assert P_SERR#. 833 ** 1=The bridge may assert P_SERR#, subject to other programmable criteria. 834 ** 07 0 Wait Cycle Control (WCC): Always returns 0bzero indicating that bridge does not perform address or data stepping, 835 ** 06 0 Parity Error Response (PER): Controls bridge response to a detected primary bus parity error. 836 ** 0=When a data parity error is detected bridge does not assert S_PERR#. 837 ** Also bridge does not assert P_SERR# in response to a detected address or attribute parity error. 838 ** 1=When a data parity error is detected bridge asserts S_PERR#. 839 ** The bridge also asserts P_SERR# (when enabled globally via bit(8) of this register) in response to a detected address or attribute parity error. 840 ** 05 0 VGA Palette Snoop Enable (VGA_PSE): Controls bridge response to VGA-compatible palette write transactions. 841 ** VGA palette write transactions are I/O transactions whose address bits are: P_AD[9:0] equal to 3C6h, 3C8h or 3C9h 842 ** P_AD[15:10] are not decoded (i.e. aliases are claimed), or are fully decoding (i.e., must be all 0's depending upon the VGA aliasing bit in the Bridge Control Register, offset 3Eh. 843 ** P_AD[31:16] equal to 0000h 844 ** 0=The bridge ignores VGA palette write transactions, unless decoded by the standard I/O address range window. 845 ** 1=The bridge responds to VGA palette write transactions with medium DEVSEL# timing and forwards them to the secondary bus. 846 ** 04 0 Memory Write and Invalidate Enable (MWIE): The bridge does not promote MW transactions to MWI transactions. 847 ** MWI transactions targeting resources on the opposite side of the bridge, however, are forwarded as MWI transactions. 848 ** 03 0 Special Cycle Enable (SCE): The bridge ignores special cycle transactions. 849 ** This bit is read only and always returns 0 when read 850 ** 02 0 Bus Master Enable (BME): Enables bridge to initiate memory and I/O transactions on the primary interface. 851 ** Initiation of configuration transactions is not affected by the state of this bit. 852 ** 0=The bridge does not initiate memory or I/O transactions on the primary interface. 853 ** 1=The bridge is enabled to function as an initiator on the primary interface. 854 ** 01 0 Memory Space Enable (MSE): Controls target response to memory transactions on the primary interface. 855 ** 0=The bridge target response to memory transactions on the primary interface is disabled. 856 ** 1=The bridge target response to memory transactions on the primary interface is enabled. 857 ** 00 0 I/O Space Enable (IOSE): Controls target response to I/O transactions on the primary interface. 858 ** 0=The bridge target response to I/O transactions on the primary interface is disabled. 859 ** 1=The bridge target response to I/O transactions on the primary interface is enabled. 860 **============================================================================== 861 */ 862 #define ARCMSR_PCI2PCI_PRIMARY_COMMAND_REG 0x04 /*word*/ 863 #define PCI_DISABLE_INTERRUPT 0x0400 864 /* 865 **============================================================================== 866 ** 0x07-0x06 : status register 867 ** Bit Default Description 868 ** 15 0 Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address, attribute or data parity error. 869 ** This bit is set regardless of the state of the PER bit in the command register. 870 ** 14 0 Signaled System Error: The bridge sets this bit to a 1b whenever it asserts SERR# on the primary bus. 871 ** 13 0 Received Master Abort: The bridge sets this bit to a 1b when, acting as the initiator on the primary bus, its transaction (with the exception of special cycles) has been terminated with a Master Abort. 872 ** 12 0 Received Target Abort: The bridge sets this bit to a 1b when, acting as the initiator on the primary bus, its transaction has been terminated with a Target Abort. 873 ** 11 0 Signaled Target Abort: The bridge sets this bit to a 1b when it, as the target of a transaction, terminates it with a Target Abort. 874 ** In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code. 875 ** 10:09 01 DEVSEL# Timing: Indicates slowest response to a non-configuration command on the primary interface. 876 ** Returns ��01b�� when read, indicating that bridge responds no slower than with medium timing. 877 ** 08 0 Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true: The bridge is the current master on the primary bus 878 ** S_PERR# is detected asserted or is asserted by bridge 879 ** The Parity Error Response bit is set in the Command register 880 ** 07 1 Fast Back to Back Capable: Returns a 1b when read indicating that bridge is able to respond to fast back to back transactions on its primary interface. 881 ** 06 0 Reserved 882 ** 05 1 66 MHz Capable Indication: Returns a 1b when read indicating that bridge primary interface is 66 MHz capable. 883 ** 1 = 884 ** 04 1 Capabilities List Enable: Returns 1b when read indicating that bridge supports PCI standard enhanced capabilities. 885 ** Offset 34h (Capability Pointer register) provides the offset for the first entry in the linked list of enhanced capabilities. 886 ** 03 0 Interrupt Status: Reflects the state of the interrupt in the device/function. 887 ** The bridge does not support interrupts. 888 ** 02:00 000 Reserved 889 **============================================================================== 890 */ 891 #define ARCMSR_PCI2PCI_PRIMARY_STATUS_REG 0x06 /*word: 06,07 */ 892 #define ARCMSR_ADAP_66MHZ 0x20 893 /* 894 **============================================================================== 895 ** 0x08 : revision ID 896 ** Bit Default Description 897 ** 07:00 00000000 Revision ID (RID): '00h' indicating bridge A-0 stepping. 898 **============================================================================== 899 */ 900 #define ARCMSR_PCI2PCI_REVISIONID_REG 0x08 /*byte*/ 901 /* 902 **============================================================================== 903 ** 0x0b-0x09 : 0180_00 (class code 1,native pci mode ) 904 ** Bit Default Description 905 ** 23:16 06h Base Class Code (BCC): Indicates that this is a bridge device. 906 ** 15:08 04h Sub Class Code (SCC): Indicates this is of type PCI-to-PCI bridge. 907 ** 07:00 00h Programming Interface (PIF): Indicates that this is standard (non-subtractive) PCI-PCI bridge. 908 **============================================================================== 909 */ 910 #define ARCMSR_PCI2PCI_CLASSCODE_REG 0x09 /*3bytes*/ 911 /* 912 **============================================================================== 913 ** 0x0c : cache line size 914 ** Bit Default Description 915 ** 07:00 00h Cache Line Size (CLS): Designates the cache line size in 32-bit dword units. 916 ** The contents of this register are factored into internal policy decisions associated with memory read prefetching, and the promotion of Memory Write transactions to MWI transactions. 917 ** Valid cache line sizes are 8 and 16 dwords. 918 ** When the cache line size is set to an invalid value, bridge behaves as though the cache line size was set to 00h. 919 **============================================================================== 920 */ 921 #define ARCMSR_PCI2PCI_PRIMARY_CACHELINESIZE_REG 0x0C /*byte*/ 922 /* 923 **============================================================================== 924 ** 0x0d : latency timer (number of pci clock 00-ff ) 925 ** Bit Default Description 926 ** Primary Latency Timer (PTV): 927 ** 07:00 00h (Conventional PCI) Conventional PCI Mode: Primary bus Master latency timer. Indicates the number of PCI clock cycles, 928 ** referenced from the assertion of FRAME# to the expiration of the timer, 929 ** when bridge may continue as master of the current transaction. All bits are writable, 930 ** resulting in a granularity of 1 PCI clock cycle. 931 ** When the timer expires (i.e., equals 00h) bridge relinquishes the bus after the first data transfer when its PCI bus grant has been deasserted. 932 ** or 40h (PCI-X) PCI-X Mode: Primary bus Master latency timer. 933 ** Indicates the number of PCI clock cycles, 934 ** referenced from the assertion of FRAME# to the expiration of the timer, 935 ** when bridge may continue as master of the current transaction. 936 ** All bits are writable, resulting in a granularity of 1 PCI clock cycle. 937 ** When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB. 938 ** (Except in the case where MLT expires within 3 data phases of an ADB.In this case bridge continues on until it reaches the next ADB before relinquishing the bus.) 939 **============================================================================== 940 */ 941 #define ARCMSR_PCI2PCI_PRIMARY_LATENCYTIMER_REG 0x0D /*byte*/ 942 /* 943 **============================================================================== 944 ** 0x0e : (header type,single function ) 945 ** Bit Default Description 946 ** 07 0 Multi-function device (MVD): 80331 is a single-function device. 947 ** 06:00 01h Header Type (HTYPE): Defines the layout of addresses 10h through 3Fh in configuration space. 948 ** Returns ��01h�� when read indicating that the register layout conforms to the standard PCI-to-PCI bridge layout. 949 **============================================================================== 950 */ 951 #define ARCMSR_PCI2PCI_HEADERTYPE_REG 0x0E /*byte*/ 952 /* 953 **============================================================================== 954 ** 0x0f : 955 **============================================================================== 956 */ 957 /* 958 **============================================================================== 959 ** 0x13-0x10 : 960 ** PCI CFG Base Address #0 (0x10) 961 **============================================================================== 962 */ 963 /* 964 **============================================================================== 965 ** 0x17-0x14 : 966 ** PCI CFG Base Address #1 (0x14) 967 **============================================================================== 968 */ 969 /* 970 **============================================================================== 971 ** 0x1b-0x18 : 972 ** PCI CFG Base Address #2 (0x18) 973 **-----------------0x1A,0x19,0x18--Bus Number Register - BNR 974 ** Bit Default Description 975 ** 23:16 00h Subordinate Bus Number (SBBN): Indicates the highest PCI bus number below this bridge. 976 ** Any Type 1 configuration cycle on the primary bus whose bus number is greater than the secondary bus number, 977 ** and less than or equal to the subordinate bus number is forwarded unaltered as a Type 1 configuration cycle on the secondary PCI bus. 978 ** 15:08 00h Secondary Bus Number (SCBN): Indicates the bus number of PCI to which the secondary interface is connected. 979 ** Any Type 1 configuration cycle matching this bus number is translated to a Type 0 configuration cycle (or a Special Cycle) before being executed on bridge's secondary PCI bus. 980 ** 07:00 00h Primary Bus Number (PBN): Indicates bridge primary bus number. 981 ** Any Type 1 configuration cycle on the primary interface with a bus number that is less than the contents of this register field does not be claimed by bridge. 982 **-----------------0x1B--Secondary Latency Timer Register - SLTR 983 ** Bit Default Description 984 ** Secondary Latency Timer (STV): 985 ** 07:00 00h (Conventional PCI) Conventional PCI Mode: Secondary bus Master latency timer. 986 ** Indicates the number of PCI clock cycles,referenced from the assertion of FRAME# to the expiration of the timer, 987 ** when bridge may continue as master of the current transaction. All bits are writable, 988 ** resulting in a granularity of 1 PCI clock cycle. 989 ** When the timer expires (i.e., equals 00h) bridge relinquishes the bus after the first data transfer when its PCI bus grant has been deasserted. 990 ** or 40h (PCI-X) PCI-X Mode: Secondary bus Master latency timer. 991 ** Indicates the number of PCI clock cycles,referenced from the assertion of FRAME# to the expiration of the timer, 992 ** when bridge may continue as master of the current transaction. All bits are writable, 993 ** resulting in a granularity of 1 PCI clock cycle. 994 ** When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB. 995 ** (Except in the case where MLT expires within 3 data phases of an ADB. In this case bridge continues on until it reaches the next ADB before relinquishing the bus) 996 **============================================================================== 997 */ 998 #define ARCMSR_PCI2PCI_PRIMARY_BUSNUMBER_REG 0x18 /*3byte 0x1A,0x19,0x18*/ 999 #define ARCMSR_PCI2PCI_SECONDARY_BUSNUMBER_REG 0x19 /*byte*/ 1000 #define ARCMSR_PCI2PCI_SUBORDINATE_BUSNUMBER_REG 0x1A /*byte*/ 1001 #define ARCMSR_PCI2PCI_SECONDARY_LATENCYTIMER_REG 0x1B /*byte*/ 1002 /* 1003 **============================================================================== 1004 ** 0x1f-0x1c : 1005 ** PCI CFG Base Address #3 (0x1C) 1006 **-----------------0x1D,0x1C--I/O Base and Limit Register - IOBL 1007 ** Bit Default Description 1008 ** 15:12 0h I/O Limit Address Bits [15:12]: Defines the top address of an address range to determine when to forward I/O transactions from one interface to the other. 1009 ** These bits correspond to address lines 15:12 for 4KB alignment. 1010 ** Bits 11:0 are assumed to be FFFh. 1011 ** 11:08 1h I/O Limit Addressing Capability: This field is hard-wired to 1h, indicating support 32-bit I/O addressing. 1012 ** 07:04 0h I/O Base Address Bits [15:12]: Defines the bottom address of an address range to determine when to forward I/O transactions from one interface to the other. 1013 ** These bits correspond to address lines 15:12 for 4KB alignment. Bits 11:0 are assumed to be 000h. 1014 ** 03:00 1h I/O Base Addressing Capability: This is hard-wired to 1h, indicating support for 32-bit I/O addressing. 1015 **-----------------0x1F,0x1E--Secondary Status Register - SSR 1016 ** Bit Default Description 1017 ** 15 0b Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address, attribute or data parity error on its secondary interface. 1018 ** 14 0b Received System Error: The bridge sets this bit when it samples SERR# asserted on its secondary bus interface. 1019 ** 13 0b Received Master Abort: The bridge sets this bit to a 1b when, acting as the initiator on the secondary bus, it's transaction (with the exception of special cycles) has been terminated with a Master Abort. 1020 ** 12 0b Received Target Abort: The bridge sets this bit to a 1b when, acting as the initiator on the secondary bus, it's transaction has been terminated with a Target Abort. 1021 ** 11 0b Signaled Target Abort: The bridge sets this bit to a 1b when it, as the target of a transaction, terminates it with a Target Abort. 1022 ** In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code. 1023 ** 10:09 01b DEVSEL# Timing: Indicates slowest response to a non-configuration command on the secondary interface. 1024 ** Returns ��01b�� when read, indicating that bridge responds no slower than with medium timing. 1025 ** 08 0b Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true: 1026 ** The bridge is the current master on the secondary bus 1027 ** S_PERR# is detected asserted or is asserted by bridge 1028 ** The Parity Error Response bit is set in the Command register 1029 ** 07 1b Fast Back-to-Back Capable (FBC): Indicates that the secondary interface of bridge can receive fast back-to-back cycles. 1030 ** 06 0b Reserved 1031 ** 05 1b 66 MHz Capable (C66): Indicates the secondary interface of the bridge is 66 MHz capable. 1032 ** 1 = 1033 ** 04:00 00h Reserved 1034 **============================================================================== 1035 */ 1036 #define ARCMSR_PCI2PCI_IO_BASE_REG 0x1C /*byte*/ 1037 #define ARCMSR_PCI2PCI_IO_LIMIT_REG 0x1D /*byte*/ 1038 #define ARCMSR_PCI2PCI_SECONDARY_STATUS_REG 0x1E /*word: 0x1F,0x1E */ 1039 /* 1040 **============================================================================== 1041 ** 0x23-0x20 : 1042 ** PCI CFG Base Address #4 (0x20) 1043 **-----------------0x23,0x22,0x21,0x20--Memory Base and Limit Register - MBL 1044 ** Bit Default Description 1045 ** 31:20 000h Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine 1046 ** the upper 1MB aligned value (exclusive) of the range. 1047 ** The incoming address must be less than or equal to this value. 1048 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0] are assumed to be F FFFFh. 1049 ** 19:16 0h Reserved. 1050 ** 15:04 000h Memory Base: These 12 bits are compared with bits P_AD[31:20] of the incoming address to determine the lower 1MB aligned value (inclusive) of the range. 1051 ** The incoming address must be greater than or equal to this value. 1052 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0]) are assumed to be 0 0000h. 1053 ** 03:00 0h Reserved. 1054 **============================================================================== 1055 */ 1056 #define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_BASE_REG 0x20 /*word: 0x21,0x20 */ 1057 #define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_LIMIT_REG 0x22 /*word: 0x23,0x22 */ 1058 /* 1059 **============================================================================== 1060 ** 0x27-0x24 : 1061 ** PCI CFG Base Address #5 (0x24) 1062 **-----------------0x27,0x26,0x25,0x24--Prefetchable Memory Base and Limit Register - PMBL 1063 ** Bit Default Description 1064 ** 31:20 000h Prefetchable Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine 1065 ** the upper 1MB aligned value (exclusive) of the range. 1066 ** The incoming address must be less than or equal to this value. 1067 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0] are assumed to be F FFFFh. 1068 ** 19:16 1h 64-bit Indicator: Indicates that 64-bit addressing is supported. 1069 ** 15:04 000h Prefetchable Memory Base: These 12 bits are compared with bits P_AD[31:20] of the incoming address to determine the lower 1MB aligned value (inclusive) of the range. 1070 ** The incoming address must be greater than or equal to this value. 1071 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0]) are assumed to be 0 0000h. 1072 ** 03:00 1h 64-bit Indicator: Indicates that 64-bit addressing is supported. 1073 **============================================================================== 1074 */ 1075 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_REG 0x24 /*word: 0x25,0x24 */ 1076 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_REG 0x26 /*word: 0x27,0x26 */ 1077 /* 1078 **============================================================================== 1079 ** 0x2b-0x28 : 1080 ** Bit Default Description 1081 ** 31:00 00000000h Prefetchable Memory Base Upper Portion: All bits are read/writable 1082 ** bridge supports full 64-bit addressing. 1083 **============================================================================== 1084 */ 1085 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_UPPER32_REG 0x28 /*dword: 0x2b,0x2a,0x29,0x28 */ 1086 /* 1087 **============================================================================== 1088 ** 0x2f-0x2c : 1089 ** Bit Default Description 1090 ** 31:00 00000000h Prefetchable Memory Limit Upper Portion: All bits are read/writable 1091 ** bridge supports full 64-bit addressing. 1092 **============================================================================== 1093 */ 1094 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_UPPER32_REG 0x2C /*dword: 0x2f,0x2e,0x2d,0x2c */ 1095 /* 1096 **============================================================================== 1097 ** 0x33-0x30 : 1098 ** Bit Default Description 1099 ** 07:00 DCh Capabilities Pointer: Pointer to the first CAP ID entry in the capabilities list is at DCh in PCI configuration 1100 ** space. (Power Management Capability Registers) 1101 **============================================================================== 1102 */ 1103 #define ARCMSR_PCI2PCI_CAPABILITIES_POINTER_REG 0x34 /*byte*/ 1104 /* 1105 **============================================================================== 1106 ** 0x3b-0x35 : reserved 1107 **============================================================================== 1108 */ 1109 /* 1110 **============================================================================== 1111 ** 0x3d-0x3c : 1112 ** 1113 ** Bit Default Description 1114 ** 15:08 00h Interrupt Pin (PIN): Bridges do not support the generation of interrupts. 1115 ** 07:00 00h Interrupt Line (LINE): The bridge does not generate interrupts, so this is reserved as '00h'. 1116 **============================================================================== 1117 */ 1118 #define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_LINE_REG 0x3C /*byte*/ 1119 #define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_PIN_REG 0x3D /*byte*/ 1120 /* 1121 **============================================================================== 1122 ** 0x3f-0x3e : 1123 ** Bit Default Description 1124 ** 15:12 0h Reserved 1125 ** 11 0b Discard Timer SERR# Enable: Controls the generation of SERR# on the primary interface (P_SERR#) in response 1126 ** to a timer discard on either the primary or secondary interface. 1127 ** 0b=SERR# is not asserted. 1128 ** 1b=SERR# is asserted. 1129 ** 10 0b Discard Timer Status (DTS): This bit is set to a '1b' when either the primary or secondary discard timer expires. 1130 ** The delayed completion is then discarded. 1131 ** 09 0b Secondary Discard Timer (SDT): Sets the maximum number of PCI clock cycles that bridge waits for an initiator on the secondary bus to repeat a delayed transaction request. 1132 ** The counter starts when the delayed transaction completion is ready to be returned to the initiator. 1133 ** When the initiator has not repeated the transaction at least once before the counter expires,bridge discards the delayed transaction from its queues. 1134 ** 0b=The secondary master time-out counter is 2 15 PCI clock cycles. 1135 ** 1b=The secondary master time-out counter is 2 10 PCI clock cycles. 1136 ** 08 0b Primary Discard Timer (PDT): Sets the maximum number of PCI clock cycles that bridge waits for an initiator on the primary bus to repeat a delayed transaction request. 1137 ** The counter starts when the delayed transaction completion is ready to be returned to the initiator. 1138 ** When the initiator has not repeated the transaction at least once before the counter expires, bridge discards the delayed transaction from its queues. 1139 ** 0b=The primary master time-out counter is 2 15 PCI clock cycles. 1140 ** 1b=The primary master time-out counter is 2 10 PCI clock cycles. 1141 ** 07 0b Fast Back-to-Back Enable (FBE): The bridge does not initiate back to back transactions. 1142 ** 06 0b Secondary Bus Reset (SBR): 1143 ** When cleared to 0b: The bridge deasserts S_RST#, when it had been asserted by writing this bit to a 1b. 1144 ** When set to 1b: The bridge asserts S_RST#. 1145 ** 05 0b Master Abort Mode (MAM): Dictates bridge behavior on the initiator bus when a master abort termination occurs in response to a delayed transaction initiated by bridge on the target bus. 1146 ** 0b=The bridge asserts TRDY# in response to a non-locked delayed transaction,and returns FFFF FFFFh when a read. 1147 ** 1b=When the transaction had not yet been completed on the initiator bus (e.g.,delayed reads, or non-posted writes), 1148 ** then bridge returns a Target Abort in response to the original requester 1149 ** when it returns looking for its delayed completion on the initiator bus. 1150 ** When the transaction had completed on the initiator bus (e.g., a PMW), then bridge asserts P_SERR# (when enabled). 1151 ** For PCI-X transactions this bit is an enable for the assertion of P_SERR# due to a master abort while attempting to deliver a posted memory write on the destination bus. 1152 ** 04 0b VGA Alias Filter Enable: This bit dictates bridge behavior in conjunction with the VGA enable bit (also of this register), 1153 ** and the VGA Palette Snoop Enable bit (Command Register). 1154 ** When the VGA enable, or VGA Palette Snoop enable bits are on (i.e., 1b) the VGA Aliasing bit for the corresponding enabled functionality,: 1155 ** 0b=Ignores address bits AD[15:10] when decoding VGA I/O addresses. 1156 ** 1b=Ensures that address bits AD[15:10] equal 000000b when decoding VGA I/O addresses. 1157 ** When all VGA cycle forwarding is disabled, (i.e., VGA Enable bit =0b and VGA Palette Snoop bit =0b), then this bit has no impact on bridge behavior. 1158 ** 03 0b VGA Enable: Setting this bit enables address decoding and transaction forwarding of the following VGA transactions from the primary bus to the secondary bus: 1159 ** frame buffer memory addresses 000A0000h:000BFFFFh, VGA I/O addresses 3B0:3BBh and 3C0h:3DFh, where AD[31:16]=��0000h�� and AD[15:10] are either not decoded (i.e., don't cares), or must be ��000000b�� 1160 ** depending upon the state of the VGA Alias Filter Enable bit. (bit(4) of this register) 1161 ** I/O and Memory Enable bits must be set in the Command register to enable forwarding of VGA cycles. 1162 ** 02 0b ISA Enable: Setting this bit enables special handling for the forwarding of ISA I/O transactions that fall within the address range specified by the I/O Base and Limit registers, and are within the lowest 64Kbyte of the I/O address map (i.e., 0000 0000h - 0000 FFFFh). 1163 ** 0b=All I/O transactions that fall within the I/O Base and Limit registers' specified range are forwarded from primary to secondary unfiltered. 1164 ** 1b=Blocks the forwarding from primary to secondary of the top 768 bytes of each 1Kbyte alias. On the secondary the top 768 bytes of each 1K alias are inversely decoded and forwarded from secondary to primary. 1165 ** 01 0b SERR# Forward Enable: 0b=The bridge does not assert P_SERR# as a result of an S_SERR# assertion. 1166 ** 1b=The bridge asserts P_SERR# whenever S_SERR# is detected asserted provided the SERR# Enable bit is set (PCI Command Register bit(8)=1b). 1167 ** 00 0b Parity Error Response: This bit controls bridge response to a parity error that is detected on its secondary interface. 1168 ** 0b=When a data parity error is detected bridge does not assert S_PERR#. 1169 ** Also bridge does not assert P_SERR# in response to a detected address or attribute parity error. 1170 ** 1b=When a data parity error is detected bridge asserts S_PERR#. The bridge also asserts P_SERR# (when enabled globally via bit(8) of the Command register) 1171 ** in response to a detected address or attribute parity error. 1172 **============================================================================== 1173 */ 1174 #define ARCMSR_PCI2PCI_BRIDGE_CONTROL_REG 0x3E /*word*/ 1175 /* 1176 ************************************************************************** 1177 ** Device Specific Registers 40-A7h 1178 ************************************************************************** 1179 ** ---------------------------------------------------------------------------------------------------------- 1180 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 1181 ** ---------------------------------------------------------------------------------------------------------- 1182 ** | Bridge Control 0 | Arbiter Control/Status | Reserved | 40h 1183 ** ---------------------------------------------------------------------------------------------------------- 1184 ** | Bridge Control 2 | Bridge Control 1 | 44h 1185 ** ---------------------------------------------------------------------------------------------------------- 1186 ** | Reserved | Bridge Status | 48h 1187 ** ---------------------------------------------------------------------------------------------------------- 1188 ** | Reserved | 4Ch 1189 ** ---------------------------------------------------------------------------------------------------------- 1190 ** | Prefetch Policy | Multi-Transaction Timer | 50h 1191 ** ---------------------------------------------------------------------------------------------------------- 1192 ** | Reserved | Pre-boot Status | P_SERR# Assertion Control | 54h 1193 ** ---------------------------------------------------------------------------------------------------------- 1194 ** | Reserved | Reserved | Secondary Decode Enable | 58h 1195 ** ---------------------------------------------------------------------------------------------------------- 1196 ** | Reserved | Secondary IDSEL | 5Ch 1197 ** ---------------------------------------------------------------------------------------------------------- 1198 ** | Reserved | 5Ch 1199 ** ---------------------------------------------------------------------------------------------------------- 1200 ** | Reserved | 68h:CBh 1201 ** ---------------------------------------------------------------------------------------------------------- 1202 ************************************************************************** 1203 **============================================================================== 1204 ** 0x42-0x41: Secondary Arbiter Control/Status Register - SACSR 1205 ** Bit Default Description 1206 ** 15:12 1111b Grant Time-out Violator: This field indicates the agent that violated the Grant Time-out rule (PCI=16 clocks,PCI-X=6 clocks). 1207 ** Note that this field is only meaningful when: 1208 ** # Bit[11] of this register is set to 1b, indicating that a Grant Time-out violation had occurred. 1209 ** # bridge internal arbiter is enabled. 1210 ** Bits[15:12] Violating Agent (REQ#/GNT# pair number) 1211 ** 0000b REQ#/GNT#[0] 1212 ** 0001b REQ#/GNT#[1] 1213 ** 0010b REQ#/GNT#[2] 1214 ** 0011b REQ#/GNT#[3] 1215 ** 1111b Default Value (no violation detected) 1216 ** When bit[11] is cleared by software, this field reverts back to its default value. 1217 ** All other values are Reserved 1218 ** 11 0b Grant Time-out Occurred: When set to 1b, 1219 ** this indicates that a Grant Time-out error had occurred involving one of the secondary bus agents. 1220 ** Software clears this bit by writing a 1b to it. 1221 ** 10 0b Bus Parking Control: 0=During bus idle, bridge parks the bus on the last master to use the bus. 1222 ** 1=During bus idle, bridge parks the bus on itself. The bus grant is removed from the last master and internally asserted to bridge. 1223 ** 09:08 00b Reserved 1224 ** 07:00 0000 0000b Secondary Bus Arbiter Priority Configuration: The bridge secondary arbiter provides two rings of arbitration priority. 1225 ** Each bit of this field assigns its corresponding secondary bus master to either the high priority arbiter ring (1b) or to the low priority arbiter ring (0b). 1226 ** Bits [3:0] correspond to request inputs S_REQ#[3:0], respectively. 1227 ** Bit [6] corresponds to the bridge internal secondary bus request while Bit [7] corresponds to the SATU secondary bus request. 1228 ** Bits [5:4] are unused. 1229 ** 0b=Indicates that the master belongs to the low priority group. 1230 ** 1b=Indicates that the master belongs to the high priority group 1231 **================================================================================= 1232 ** 0x43: Bridge Control Register 0 - BCR0 1233 ** Bit Default Description 1234 ** 07 0b Fully Dynamic Queue Mode: 0=The number of Posted write transactions is limited to eight and the Posted Write data is limited to 4KB. 1235 ** 1=Operation in fully dynamic queue mode. The bridge enqueues up to 14 Posted Memory Write transactions and 8KB of posted write data. 1236 ** 06:03 0H Reserved. 1237 ** 02 0b Upstream Prefetch Disable: This bit disables bridge ability to perform upstream prefetch operations for Memory Read requests received on its secondary interface. 1238 ** This bit also controls the bridge's ability to generate advanced read commands when forwarding a Memory Read Block transaction request upstream from a PCI-X bus to a Conventional PCI bus. 1239 ** 0b=bridge treats all upstream Memory Read requests as though they target prefetchable memory. The use of Memory Read Line and Memory Read 1240 ** Multiple is enabled when forwarding a PCI-X Memory Read Block request to an upstream bus operating in Conventional PCI mode. 1241 ** 1b=bridge treats upstream PCI Memory Read requests as though they target non-prefetchable memory and forwards upstream PCI-X Memory Read Block commands as Memory Read when the primary bus is operating in Conventional PCI mode. 1242 ** NOTE: This bit does not affect bridge ability to perform read prefetching when the received command is Memory Read Line or Memory Read Multiple. 1243 **================================================================================= 1244 ** 0x45-0x44: Bridge Control Register 1 - BCR1 (Sheet 2 of 2) 1245 ** Bit Default Description 1246 ** 15:08 0000000b Reserved 1247 ** 07:06 00b Alias Command Mapping: This two bit field determines how bridge handles PCI-X ��Alias�� commands, specifically the Alias to Memory Read Block and Alias to Memory Write Block commands. 1248 ** The three options for handling these alias commands are to either pass it as is, re-map to the actual block memory read/write command encoding, or ignore 1249 ** the transaction forcing a Master Abort to occur on the Origination Bus. 1250 ** Bit (7:6) Handling of command 1251 ** 0 0 Re-map to Memory Read/Write Block before forwarding 1252 ** 0 1 Enqueue and forward the alias command code unaltered 1253 ** 1 0 Ignore the transaction, forcing Master Abort 1254 ** 1 1 Reserved 1255 ** 05 1b Watchdog Timers Disable: Disables or enables all 2 24 Watchdog Timers in both directions. 1256 ** The watchdog timers are used to detect prohibitively long latencies in the system. 1257 ** The watchdog timer expires when any Posted Memory Write (PMW), Delayed Request, 1258 ** or Split Requests (PCI-X mode) is not completed within 2 24 events 1259 ** (��events�� are defined as PCI Clocks when operating in PCI-X mode, and as the number of times being retried when operating in Conventional PCI mode) 1260 ** 0b=All 2 24 watchdog timers are enabled. 1261 ** 1b=All 2 24 watchdog timers are disabled and there is no limits to the number of attempts bridge makes when initiating a PMW, 1262 ** transacting a Delayed Transaction, or how long it waits for a split completion corresponding to one of its requests. 1263 ** 04 0b GRANT# time-out disable: This bit enables/disables the GNT# time-out mechanism. 1264 ** Grant time-out is 16 clocks for conventional PCI, and 6 clocks for PCI-X. 1265 ** 0b=The Secondary bus arbiter times out an agent that does not assert FRAME# within 16/6 clocks of receiving its grant, once the bus has gone idle. 1266 ** The time-out counter begins as soon as the bus goes idle with the new GNT# asserted. 1267 ** An infringing agent does not receive a subsequent GNT# until it de-asserts its REQ# for at least one clock cycle. 1268 ** 1b=GNT# time-out mechanism is disabled. 1269 ** 03 00b Reserved. 1270 ** 02 0b Secondary Discard Timer Disable: This bit enables/disables bridge secondary delayed transaction discard mechanism. 1271 ** The time out mechanism is used to ensure that initiators of delayed transactions return for their delayed completion data/status within a reasonable amount of time after it is available from bridge. 1272 ** 0b=The secondary master time-out counter is enabled and uses the value specified by the Secondary Discard Timer bit (see Bridge Control Register). 1273 ** 1b=The secondary master time-out counter is disabled. The bridge waits indefinitely for a secondary bus master to repeat a delayed transaction. 1274 ** 01 0b Primary Discard Timer Disable: This bit enables/disables bridge primary delayed transaction discard mechanism. The time out mechanism is used to ensure that initiators of delayed transactions return for their delayed completion data/status within a reasonable amount of time after it is available from bridge. 1275 ** 0b=The primary master time-out counter is enabled and uses the value specified by the Primary Discard Timer bit (see Bridge Control Register). 1276 ** 1b=The secondary master time-out counter is disabled. The bridge waits indefinitely for a secondary bus master to repeat a delayed transaction. 1277 ** 00 0b Reserved 1278 **================================================================================= 1279 ** 0x47-0x46: Bridge Control Register 2 - BCR2 1280 ** Bit Default Description 1281 ** 15:07 0000b Reserved. 1282 ** 06 0b Global Clock Out Disable (External Secondary Bus Clock Source Enable): This bit disables all of the secondary PCI clock outputs including the feedback clock S_CLKOUT. 1283 ** This means that the user is required to provide an S_CLKIN input source. 1284 ** 05:04 11 (66 MHz) Preserved. 1285 ** 01 (100 MHz) 1286 ** 00 (133 MHz) 1287 ** 03:00 Fh (100 MHz & 66 MHz) 1288 ** 7h (133 MHz) 1289 ** This 4 bit field provides individual enable/disable mask bits for each of bridge 1290 ** secondary PCI clock outputs. Some, or all secondary clock outputs (S_CLKO[3:0]) 1291 ** default to being enabled following the rising edge of P_RST#, depending on the 1292 ** frequency of the secondary bus clock: 1293 ** �E Designs with 100 MHz (or lower) Secondary PCI clock power up with all four S_CLKOs enabled by default. (SCLKO[3:0])�P 1294 ** �E Designs with 133 MHz Secondary PCI clock power up with the lower order 3 S_CLKOs enabled by default. (S_CLKO[2:0]) Only those SCLKs that power up enabled by can be connected to downstream device clock inputs. 1295 **================================================================================= 1296 ** 0x49-0x48: Bridge Status Register - BSR 1297 ** Bit Default Description 1298 ** 15 0b Upstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR# is conditionally asserted when the secondary discard timer expires. 1299 ** 14 0b Upstream Delayed/Split Read Watchdog Timer Expired: 1300 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# is conditionally asserted when bridge discards an upstream delayed read transaction request after 2 24 retries following the initial retry. 1301 ** PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted when bridge discards an upstream split read request after waiting in excess of 2 24 clocks for the corresponding Split Completion to arrive. 1302 ** 13 0b Upstream Delayed/Split Write Watchdog Timer Expired: 1303 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# is conditionally asserted when bridge discards an upstream delayed write transaction request after 2 24 retries following the initial retry. 1304 ** PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted when bridge discards an upstream split write request after waiting in excess of 2 24 clocks for the corresponding Split Completion to arrive. 1305 ** 12 0b Master Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR# is conditionally asserted when a Master Abort occurs as a result of an attempt, by bridge, to retire a PMW upstream. 1306 ** 11 0b Target Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR# is conditionally asserted when a Target Abort occurs as a result of an attempt, by bridge, to retire a PMW upstream. 1307 ** 10 0b Upstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR# is conditionally asserted when bridge discards an upstream PMW transaction after receiving 2 24 target retries from the primary bus target 1308 ** 09 0b Upstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR# is conditionally asserted when a data parity error is detected by bridge while attempting to retire a PMW upstream 1309 ** 08 0b Secondary Bus Address Parity Error: This bit is set to a 1b and P_SERR# is conditionally asserted when bridge detects an address parity error on the secondary bus. 1310 ** 07 0b Downstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR# is conditionally asserted when the primary bus discard timer expires. 1311 ** 06 0b Downstream Delayed/Split Read Watchdog Timer Expired: 1312 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# is conditionally asserted when bridge discards a downstream delayed read transaction request after receiving 2 24 target retries from the secondary bus target. 1313 ** PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted when bridge discards a downstream split read request after waiting in excess of 2 24 clocks for the corresponding Split Completion to arrive. 1314 ** 05 0b Downstream Delayed Write/Split Watchdog Timer Expired: 1315 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# is conditionally asserted when bridge discards a downstream delayed write transaction request after receiving 2 24 target retries from the secondary bus target. 1316 ** PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted when bridge discards a downstream split write request after waiting in excess of 2 24 clocks for the corresponding Split Completion to arrive. 1317 ** 04 0b Master Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR# is conditionally asserted when a Master Abort occurs as a result of an attempt, by bridge, to retire a PMW downstream. 1318 ** 03 0b Target Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR# is conditionally asserted when a Target Abort occurs as a result of an attempt, by bridge, to retire a PMW downstream. 1319 ** 02 0b Downstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR# is conditionally asserted when bridge discards a downstream PMW transaction after receiving 2 24 target retries from the secondary bus target 1320 ** 01 0b Downstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR# is conditionally asserted when a data parity error is detected by bridge while attempting to retire a PMW downstream. 1321 ** 00 0b Primary Bus Address Parity Error: This bit is set to a 1b and P_SERR# is conditionally asserted when bridge detects an address parity error on the primary bus. 1322 **================================================================================== 1323 ** 0x51-0x50: Bridge Multi-Transaction Timer Register - BMTTR 1324 ** Bit Default Description 1325 ** 15:13 000b Reserved 1326 ** 12:10 000b GRANT# Duration: This field specifies the count (PCI clocks) that a secondary bus master has its grant maintained in order to enable multiple transactions to execute within the same arbitration cycle. 1327 ** Bit[02:00] GNT# Extended Duration 1328 ** 000 MTT Disabled (Default=no GNT# extension) 1329 ** 001 16 clocks 1330 ** 010 32 clocks 1331 ** 011 64 clocks 1332 ** 100 128 clocks 1333 ** 101 256 clocks 1334 ** 110 Invalid (treated as 000) 1335 ** 111 Invalid (treated as 000) 1336 ** 09:08 00b Reserved 1337 ** 07:00 FFh MTT Mask: This field enables/disables MTT usage for each REQ#/GNT# pair supported by bridge secondary arbiter. 1338 ** Bit(7) corresponds to SATU internal REQ#/GNT# pair, 1339 ** bit(6) corresponds to bridge internal REQ#/GNT# pair, 1340 ** bit(5) corresponds to REQ#/GNT#(5) pair, etc. 1341 ** When a given bit is set to 1b, its corresponding REQ#/GNT# pair is enabled for MTT functionality as determined by bits(12:10) of this register. 1342 ** When a given bit is cleared to 0b, its corresponding REQ#/GNT# pair is disabled from using the MTT. 1343 **================================================================================== 1344 ** 0x53-0x52: Read Prefetch Policy Register - RPPR 1345 ** Bit Default Description 1346 ** 15:13 000b ReRead_Primary Bus: 3-bit field indicating the multiplication factor to be used in calculating the number of bytes to prefetch from the secondary bus interface on subsequent PreFetch operations given that the read demands were not satisfied using the FirstRead parameter. 1347 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs Memory Read Line 1 cache lines Memory Read Multiple 2 cache lines 1348 ** 12:10 000b FirstRead_Primary Bus: 3-bit field indicating the multiplication factor to be used in calculating the number of bytes to prefetch from the secondary bus interface on the initial PreFetch operation. 1349 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs Memory Read Line 1 cache line Memory Read Multiple 2 cache lines 1350 ** 09:07 010b ReRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used in calculating the number of bytes to prefetch from the primary bus interface on subsequent PreFetch operations given that the read demands were not satisfied using the FirstRead parameter. 1351 ** The default value of 010b correlates to: Command Type Hardwired pre-fetch amount Memory Read 3 cache lines Memory Read Line 3 cache lines Memory Read Multiple 6 cache lines 1352 ** 06:04 000b FirstRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used in calculating the number of bytes to prefetch from the primary bus interface on the initial PreFetch operation. 1353 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs Memory Read Line 1 cache line Memory Read Multiple 2 cache lines 1354 ** 03:00 1111b Staged Prefetch Enable: This field enables/disables the FirstRead/ReRead pre-fetch algorithm for the secondary and the primary bus interfaces. 1355 ** Bit(3) is a ganged enable bit for REQ#/GNT#[7:3], and bits(2:0) provide individual 1356 ** enable bits for REQ#/GNT#[2:0]. (bit(2) is the enable bit for REQ#/GNT#[2], etc...) 1357 ** 1b: enables the staged pre-fetch feature 1358 ** 0b: disables staged pre-fetch, 1359 ** and hardwires read pre-fetch policy to the following for 1360 ** Memory Read, 1361 ** Memory Read Line, 1362 ** and Memory Read Multiple commands: 1363 ** Command Type Hardwired Pre-Fetch Amount... 1364 ** Memory Read 4 DWORDs 1365 ** Memory Read Line 1 cache line 1366 ** Memory Read Multiple 2 cache lines 1367 ** NOTE: When the starting address is not cache line aligned, bridge pre-fetches Memory Read line commands only to the next higher cache line boundary.For non-cache line aligned Memory Read Multiple commands bridge pre-fetches only to the second cache line boundary encountered. 1368 **================================================================================== 1369 ** 0x55-0x54: P_SERR# Assertion Control - SERR_CTL 1370 ** Bit Default Description 1371 ** 15 0b Upstream Delayed Transaction Discard Timer Expired: Dictates the bridge behavior in response to its discarding of a delayed transaction that was initiated from the primary bus. 1372 ** 0b=bridge asserts P_SERR#. 1373 ** 1b=bridge does not assert P_SERR# 1374 ** 14 0b Upstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 1375 ** 0b=bridge asserts P_SERR#. 1376 ** 1b=bridge does not assert P_SERR# 1377 ** 13 0b Upstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 1378 ** 0b=bridge asserts P_SERR#. 1379 ** 1b=bridge does not assert P_SERR# 1380 ** 12 0b Master Abort during Upstream Posted Write: Dictates bridge behavior following its having detected a Master Abort while attempting to retire one of its PMWs upstream. 1381 ** 0b=bridge asserts P_SERR#. 1382 ** 1b=bridge does not assert P_SERR# 1383 ** 11 0b Target Abort during Upstream Posted Write: Dictates bridge behavior following its having been terminated with Target Abort while attempting to retire one of its PMWs upstream. 1384 ** 0b=bridge asserts P_SERR#. 1385 ** 1b=bridge does not assert P_SERR# 1386 ** 10 0b Upstream Posted Write Data Discarded: Dictates bridge behavior in the event that it discards an upstream posted write transaction. 1387 ** 0b=bridge asserts P_SERR#. 1388 ** 1b=bridge does not assert P_SERR# 1389 ** 09 0b Upstream Posted Write Data Parity Error: Dictates bridge behavior when a data parity error is detected while attempting to retire on of its PMWs upstream. 1390 ** 0b=bridge asserts P_SERR#. 1391 ** 1b=bridge does not assert P_SERR# 1392 ** 08 0b Secondary Bus Address Parity Error: This bit dictates bridge behavior when it detects an address parity error on the secondary bus. 1393 ** 0b=bridge asserts P_SERR#. 1394 ** 1b=bridge does not assert P_SERR# 1395 ** 07 0b Downstream Delayed Transaction Discard Timer Expired: Dictates bridge behavior in response to its discarding of a delayed transaction that was initiated on the secondary bus. 1396 ** 0b=bridge asserts P_SERR#. 1397 ** 1b=bridge does not assert P_SERR# 1398 ** 06 0b Downstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 1399 ** 0b=bridge asserts P_SERR#. 1400 ** 1b=bridge does not assert P_SERR# 1401 ** 05 0b Downstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 1402 ** 0b=bridge asserts P_SERR#. 1403 ** 1b=bridge does not assert P_SERR# 1404 ** 04 0b Master Abort during Downstream Posted Write: Dictates bridge behavior following its having detected a Master Abort while attempting to retire one of its PMWs downstream. 1405 ** 0b=bridge asserts P_SERR#. 1406 ** 1b=bridge does not assert P_SERR# 1407 ** 03 0b Target Abort during Downstream Posted Write: Dictates bridge behavior following its having been terminated with Target Abort while attempting to retire one of its PMWs downstream. 1408 ** 0b=bridge asserts P_SERR#. 1409 ** 1b=bridge does not assert P_SERR# 1410 ** 02 0b Downstream Posted Write Data Discarded: Dictates bridge behavior in the event that it discards a downstream posted write transaction. 1411 ** 0b=bridge asserts P_SERR#. 1412 ** 1b=bridge does not assert P_SERR# 1413 ** 01 0b Downstream Posted Write Data Parity Error: Dictates bridge behavior when a data parity error is detected while attempting to retire on of its PMWs downstream. 1414 ** 0b=bridge asserts P_SERR#. 1415 ** 1b=bridge does not assert P_SERR# 1416 ** 00 0b Primary Bus Address Parity Error: This bit dictates bridge behavior when it detects an address parity error on the primary bus. 1417 ** 0b=bridge asserts P_SERR#. 1418 ** 1b=bridge does not assert P_SERR# 1419 **=============================================================================== 1420 ** 0x56: Pre-Boot Status Register - PBSR 1421 ** Bit Default Description 1422 ** 07 1 Reserved 1423 ** 06 - Reserved - value indeterminate 1424 ** 05:02 0 Reserved 1425 ** 01 Varies with External State of S_133EN at PCI Bus Reset Secondary Bus Max Frequency Setting: This bit reflect captured S_133EN strap, indicating the maximum secondary bus clock frequency when in PCI-X mode. 1426 ** Max Allowable Secondary Bus Frequency 1427 ** S_133EN PCI-X Mode 1428 ** 0 100 MHz 1429 ** 1 133 MH 1430 ** 00 0b Reserved 1431 **=============================================================================== 1432 ** 0x59-0x58: Secondary Decode Enable Register - SDER 1433 ** Bit Default Description 1434 ** 15:03 FFF1h Preserved. 1435 ** 02 Varies with External State of PRIVMEM at PCI Bus Reset Private Memory Space Enable - when set, bridge overrides its secondary inverse decode logic and not 1436 ** forward upstream any secondary bus initiated DAC Memory transactions with AD(63)=1b. 1437 ** This creates a private memory space on the Secondary PCI bus that allows peer-to-peer transactions. 1438 ** 01:00 10 2 Preserved. 1439 **=============================================================================== 1440 ** 0x5D-0x5C: Secondary IDSEL Select Register - SISR 1441 ** Bit Default Description 1442 ** 15:10 000000 2 Reserved. 1443 ** 09 Varies with External State of PRIVDEV at PCI Bus Reset AD25- IDSEL Disable - When this bit is set, AD25 is deasserted for any possible Type 1 to Type 0 conversion. 1444 ** When this bit is clear, AD25 is asserted when Primary addresses AD[15:11]=01001 2 during a Type 1 to Type 0 conversion. 1445 ** 08 Varies with External State of PRIVDEV at PCI Bus Reset AD24- IDSEL Disable - When this bit is set, AD24 is deasserted for any possible Type 1 to Type 0 conversion. 1446 ** When this bit is clear, AD24 is asserted when Primary addresses AD[15:11]=01000 2 during a Type 1 to Type 0 conversion. 1447 ** 07 Varies with External State of PRIVDEV at PCI Bus Reset AD23- IDSEL Disable - When this bit is set, AD23 is deasserted for any possible Type 1 to Type 0 conversion. 1448 ** When this bit is clear, AD23 is asserted when Primary addresses AD[15:11]=00111 2 during a Type 1 to Type 0 conversion. 1449 ** 06 Varies with External State of PRIVDEV at PCI Bus Reset AD22- IDSEL Disable - When this bit is set, AD22 is deasserted for any possible Type 1 to Type 0 conversion. 1450 ** When this bit is clear, AD22 is asserted when Primary addresses AD[15:11]=00110 2 during a Type 1 to Type 0 conversion. 1451 ** 05 Varies with External State of PRIVDEV at PCI Bus Reset AD21- IDSEL Disable - When this bit is set, AD21 is deasserted for any possible Type 1 to Type 0 conversion. 1452 ** When this bit is clear, AD21 is asserted when Primary addresses AD[15:11]=00101 2 during a Type 1 to Type 0 conversion. 1453 ** 04 Varies with External State of PRIVDEV at PCI Bus Reset AD20- IDSEL Disable - When this bit is set, AD20 is deasserted for any possible Type 1 to Type 0 conversion. 1454 ** When this bit is clear, AD20 is asserted when Primary addresses AD[15:11]=00100 2 during a Type 1 to Type 0 conversion. 1455 ** 03 Varies with External State of PRIVDEV at PCI Bus Reset AD19- IDSEL Disable - When this bit is set, AD19 is deasserted for any possible Type 1 to Type 0 conversion. 1456 ** When this bit is clear, AD19 is asserted when Primary addresses AD[15:11]=00011 2 during a Type 1 to Type 0 conversion. 1457 ** 02 Varies with External State of PRIVDEV at PCI Bus Reset AD18- IDSEL Disable - When this bit is set, AD18 is deasserted for any possible Type 1 to Type 0 conversion. 1458 ** When this bit is clear, AD18 is asserted when Primary addresses AD[15:11]=00010 2 during a Type 1 to Type 0 conversion. 1459 ** 01 Varies with External State of PRIVDEV at PCI Bus Reset AD17- IDSEL Disable - When this bit is set, AD17 is deasserted for any possible Type 1 to Type 0 conversion. 1460 ** When this bit is clear, AD17 is asserted when Primary addresses AD[15:11]=00001 2 during a Type 1 to Type 0 conversion. 1461 ** 00 Varies with External State of PRIVDEV at PCI Bus Reset AD16- IDSEL Disable - When this bit is set, AD16 is deasserted for any possible Type 1 to Type 0 conversion. 1462 ** When this bit is clear, AD16 is asserted when Primary addresses AD[15:11]=00000 2 during a Type 1 to Type 0 conversion. 1463 ************************************************************************** 1464 */ 1465 /* 1466 ************************************************************************** 1467 ** Reserved A8-CBh 1468 ************************************************************************** 1469 */ 1470 /* 1471 ************************************************************************** 1472 ** PCI Extended Enhanced Capabilities List CC-FFh 1473 ************************************************************************** 1474 ** ---------------------------------------------------------------------------------------------------------- 1475 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 1476 ** ---------------------------------------------------------------------------------------------------------- 1477 ** | Power Management Capabilities | Next Item Ptr | Capability ID | DCh 1478 ** ---------------------------------------------------------------------------------------------------------- 1479 ** | PM Data | PPB Support | Extensions Power Management CSR | E0h 1480 ** ---------------------------------------------------------------------------------------------------------- 1481 ** | Reserved | Reserved | Reserved | E4h 1482 ** ---------------------------------------------------------------------------------------------------------- 1483 ** | Reserved | E8h 1484 ** ---------------------------------------------------------------------------------------------------------- 1485 ** | Reserved | Reserved | Reserved | Reserved | ECh 1486 ** ---------------------------------------------------------------------------------------------------------- 1487 ** | PCI-X Secondary Status | Next Item Ptr | Capability ID | F0h 1488 ** ---------------------------------------------------------------------------------------------------------- 1489 ** | PCI-X Bridge Status | F4h 1490 ** ---------------------------------------------------------------------------------------------------------- 1491 ** | PCI-X Upstream Split Transaction Control | F8h 1492 ** ---------------------------------------------------------------------------------------------------------- 1493 ** | PCI-X Downstream Split Transaction Control | FCh 1494 ** ---------------------------------------------------------------------------------------------------------- 1495 **=============================================================================== 1496 ** 0xDC: Power Management Capabilities Identifier - PM_CAPID 1497 ** Bit Default Description 1498 ** 07:00 01h Identifier (ID): PCI SIG assigned ID for PCI-PM register block 1499 **=============================================================================== 1500 ** 0xDD: Next Item Pointer - PM_NXTP 1501 ** Bit Default Description 1502 ** 07:00 F0H Next Capabilities Pointer (PTR): The register defaults to F0H pointing to the PCI-X Extended Capability Header. 1503 **=============================================================================== 1504 ** 0xDF-0xDE: Power Management Capabilities Register - PMCR 1505 ** Bit Default Description 1506 ** 15:11 00h PME Supported (PME): PME# cannot be asserted by bridge. 1507 ** 10 0h State D2 Supported (D2): Indicates no support for state D2. No power management action in this state. 1508 ** 09 1h State D1 Supported (D1): Indicates support for state D1. No power management action in this state. 1509 ** 08:06 0h Auxiliary Current (AUXC): This 3 bit field reports the 3.3Vaux auxiliary current requirements for the PCI function. 1510 ** This returns 000b as PME# wake-up for bridge is not implemented. 1511 ** 05 0 Special Initialization Required (SINT): Special initialization is not required for bridge. 1512 ** 04:03 00 Reserved 1513 ** 02:00 010 Version (VS): Indicates that this supports PCI Bus Power Management Interface Specification, Revision 1.1. 1514 **=============================================================================== 1515 ** 0xE1-0xE0: Power Management Control / Status - Register - PMCSR 1516 ** Bit Default Description 1517 ** 15:09 00h Reserved 1518 ** 08 0b PME_Enable: This bit, when set to 1b enables bridge to assert PME#. Note that bridge never has occasion to assert PME# and implements this dummy R/W bit only for the purpose of working around an OS PCI-PM bug. 1519 ** 07:02 00h Reserved 1520 ** 01:00 00 Power State (PSTATE): This 2-bit field is used both to determine the current power state of a function and to set the Function into a new power state. 1521 ** 00 - D0 state 1522 ** 01 - D1 state 1523 ** 10 - D2 state 1524 ** 11 - D3 hot state 1525 **=============================================================================== 1526 ** 0xE2: Power Management Control / Status PCI to PCI Bridge Support - PMCSR_BSE 1527 ** Bit Default Description 1528 ** 07 0 Bus Power/Clock Control Enable (BPCC_En): Indicates that the bus power/clock control policies have been disabled. 1529 ** 06 0 B2/B3 support for D3 Hot (B2_B3#): The state of this bit determines the action that is to occur as a direct result of programming the function to D3 hot. 1530 ** This bit is only meaningful when bit 7 (BPCC_En) is a ��1��. 1531 ** 05:00 00h Reserved 1532 **=============================================================================== 1533 ** 0xE3: Power Management Data Register - PMDR 1534 ** Bit Default Description 1535 ** 07:00 00h Reserved 1536 **=============================================================================== 1537 ** 0xF0: PCI-X Capabilities Identifier - PX_CAPID 1538 ** Bit Default Description 1539 ** 07:00 07h Identifier (ID): Indicates this is a PCI-X capabilities list. 1540 **=============================================================================== 1541 ** 0xF1: Next Item Pointer - PX_NXTP 1542 ** Bit Default Description 1543 ** 07:00 00h Next Item Pointer: Points to the next capability in the linked list The power on default value of this 1544 ** register is 00h indicating that this is the last entry in the linked list of capabilities. 1545 **=============================================================================== 1546 ** 0xF3-0xF2: PCI-X Secondary Status - PX_SSTS 1547 ** Bit Default Description 1548 ** 15:09 00h Reserved 1549 ** 08:06 Xxx Secondary Clock Frequency (SCF): This field is set with the frequency of the secondary bus. 1550 ** The values are: 1551 ** BitsMax FrequencyClock Period 1552 ** 000PCI ModeN/A 1553 ** 00166 15 1554 ** 01010010 1555 ** 0111337.5 1556 ** 1xxreservedreserved 1557 ** The default value for this register is the operating frequency of the secondary bus 1558 ** 05 0b Split Request Delayed. (SRD): This bit is supposed to be set by a bridge when it cannot forward a transaction on the 1559 ** secondary bus to the primary bus because there is not enough room within the limit 1560 ** specified in the Split Transaction Commitment Limit field in the Downstream Split 1561 ** Transaction Control register. The bridge does not set this bit. 1562 ** 04 0b Split Completion Overrun (SCO): This bit is supposed to be set when a bridge terminates a Split Completion on the secondary bus with retry or Disconnect at next ADB because its buffers are full. The bridge does not set this bit. 1563 ** 03 0b Unexpected Split Completion (USC): This bit is set when an unexpected split completion with a requester ID equal to bridge secondary bus number, device number 00h, and function number 0 is received on the secondary interface. This bit is cleared by software writing a '1'. 1564 ** 02 0b Split Completion Discarded (SCD): This bit is set when bridge discards a split completion moving toward the secondary bus because the requester would not accept it. This bit cleared by software writing a '1'. 1565 ** 01 1b 133 MHz Capable: Indicates that bridge is capable of running its secondary bus at 133 MHz 1566 ** 00 1b 64-bit Device (D64): Indicates the width of the secondary bus as 64-bits. 1567 **=============================================================================== 1568 ** 0xF7-0xF6-0xf5-0xF4: PCI-X Bridge Status - PX_BSTS 1569 ** Bit Default Description 1570 ** 31:22 0 Reserved 1571 ** 21 0 Split Request Delayed (SRD): This bit does not be set by bridge. 1572 ** 20 0 Split Completion Overrun (SCO): This bit does not be set by bridge because bridge throttles traffic on the completion side. 1573 ** 19 0 Unexpected Split Completion (USC): The bridge sets this bit to 1b when it encounters a corrupted Split Completion, possibly with an inconsistent remaining byte count.Software clears this bit by writing a 1b to it. 1574 ** 18 0 Split Completion Discarded (SCD): The bridge sets this bit to 1b when it has discarded a Split Completion.Software clears this bit by writing a 1b to it. 1575 ** 17 1 133 MHz Capable: This bit indicates that the bridge primary interface is capable of 133 MHz operation in PCI-X mode. 1576 ** 0=The maximum operating frequency is 66 MHz. 1577 ** 1=The maximum operating frequency is 133 MHz. 1578 ** 16 Varies with the external state of P_32BITPCI# at PCI Bus Reset 64-bit Device (D64): Indicates bus width of the Primary PCI bus interface. 1579 ** 0=Primary Interface is connected as a 32-bit PCI bus. 1580 ** 1=Primary Interface is connected as a 64-bit PCI bus. 1581 ** 15:08 00h Bus Number (BNUM): This field is simply an alias to the PBN field of the BNUM register at offset 18h. 1582 ** Apparently it was deemed necessary reflect it here for diagnostic purposes. 1583 ** 07:03 1fh Device Number (DNUM): Indicates which IDSEL bridge consumes. May be updated whenever a PCI-X 1584 ** configuration write cycle that targets bridge scores a hit. 1585 ** 02:00 0h Function Number (FNUM): The bridge Function # 1586 **=============================================================================== 1587 ** 0xFB-0xFA-0xF9-0xF8: PCI-X Upstream Split Transaction Control - PX_USTC 1588 ** Bit Default Description 1589 ** 31:16 003Eh Split Transaction Limit (STL): This register indicates the size of the commitment limit in units of ADQs. 1590 ** Software is permitted to program this register to any value greater than or equal to 1591 ** the contents of the Split Transaction Capacity register. A value less than the contents 1592 ** of the Split Transaction Capacity register causes unspecified results. 1593 ** A value of 003Eh or greater enables the bridge to forward all Split Requests of any 1594 ** size regardless of the amount of buffer space available. 1595 ** 15:00 003Eh Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing 1596 ** split completions. This register controls behavior of the bridge buffers for forwarding 1597 ** Split Transactions from a primary bus requester to a secondary bus completer. 1598 ** The default value of 003Eh indicates there is available buffer space for 62 ADQs (7936 bytes). 1599 **=============================================================================== 1600 ** 0xFF-0xFE-0xFD-0xFC: PCI-X Downstream Split Transaction Control - PX_DSTC 1601 ** Bit Default Description 1602 ** 31:16 003Eh Split Transaction Limit (STL): This register indicates the size of the commitment limit in units of ADQs. 1603 ** Software is permitted to program this register to any value greater than or equal to 1604 ** the contents of the Split Transaction Capacity register. A value less than the contents 1605 ** of the Split Transaction Capacity register causes unspecified results. 1606 ** A value of 003Eh or greater enables the bridge to forward all Split Requests of any 1607 ** size regardless of the amount of buffer space available. 1608 ** 15:00 003Eh Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing 1609 ** split completions. This register controls behavior of the bridge buffers for forwarding 1610 ** Split Transactions from a primary bus requester to a secondary bus completer. 1611 ** The default value of 003Eh indicates there is available buffer space for 62 ADQs (7936 bytes). 1612 ************************************************************************** 1613 */ 1614 1615 1616 1617 1618 /* 1619 ************************************************************************************************************************************* 1620 ** 80331 Address Translation Unit Register Definitions 1621 ** ATU Interface Configuration Header Format 1622 ** The ATU is programmed via a [Type 0] configuration command on the PCI interface. 1623 ************************************************************************************************************************************* 1624 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configuration Byte Offset 1625 **=================================================================================================================================== 1626 ** | ATU Device ID | Vendor ID | 00h 1627 ** ---------------------------------------------------------------------------------------------------------- 1628 ** | Status | Command | 04H 1629 ** ---------------------------------------------------------------------------------------------------------- 1630 ** | ATU Class Code | Revision ID | 08H 1631 ** ---------------------------------------------------------------------------------------------------------- 1632 ** | ATUBISTR | Header Type | Latency Timer | Cacheline Size | 0CH 1633 ** ---------------------------------------------------------------------------------------------------------- 1634 ** | Inbound ATU Base Address 0 | 10H 1635 ** ---------------------------------------------------------------------------------------------------------- 1636 ** | Inbound ATU Upper Base Address 0 | 14H 1637 ** ---------------------------------------------------------------------------------------------------------- 1638 ** | Inbound ATU Base Address 1 | 18H 1639 ** ---------------------------------------------------------------------------------------------------------- 1640 ** | Inbound ATU Upper Base Address 1 | 1CH 1641 ** ---------------------------------------------------------------------------------------------------------- 1642 ** | Inbound ATU Base Address 2 | 20H 1643 ** ---------------------------------------------------------------------------------------------------------- 1644 ** | Inbound ATU Upper Base Address 2 | 24H 1645 ** ---------------------------------------------------------------------------------------------------------- 1646 ** | Reserved | 28H 1647 ** ---------------------------------------------------------------------------------------------------------- 1648 ** | ATU Subsystem ID | ATU Subsystem Vendor ID | 2CH 1649 ** ---------------------------------------------------------------------------------------------------------- 1650 ** | Expansion ROM Base Address | 30H 1651 ** ---------------------------------------------------------------------------------------------------------- 1652 ** | Reserved Capabilities Pointer | 34H 1653 ** ---------------------------------------------------------------------------------------------------------- 1654 ** | Reserved | 38H 1655 ** ---------------------------------------------------------------------------------------------------------- 1656 ** | Maximum Latency | Minimum Grant | Interrupt Pin | Interrupt Line | 3CH 1657 ** ---------------------------------------------------------------------------------------------------------- 1658 ********************************************************************************************************************* 1659 */ 1660 /* 1661 *********************************************************************************** 1662 ** ATU Vendor ID Register - ATUVID 1663 ** ----------------------------------------------------------------- 1664 ** Bit Default Description 1665 ** 15:00 8086H (0x17D3) ATU Vendor ID - This is a 16-bit value assigned to Intel. This register, combined with the DID, uniquely identify the PCI device. 1666 ** Access type is Read/Write to allow the 80331 to configure the register as a different vendor ID to simulate the interface of a standard mechanism currently used by existing application software. 1667 *********************************************************************************** 1668 */ 1669 #define ARCMSR_ATU_VENDOR_ID_REG 0x00 /*word*/ 1670 /* 1671 *********************************************************************************** 1672 ** ATU Device ID Register - ATUDID 1673 ** ----------------------------------------------------------------- 1674 ** Bit Default Description 1675 ** 15:00 0336H (0x1110) ATU Device ID - This is a 16-bit value assigned to the ATU. This ID, combined with the VID, uniquely identify any PCI device. 1676 *********************************************************************************** 1677 */ 1678 #define ARCMSR_ATU_DEVICE_ID_REG 0x02 /*word*/ 1679 /* 1680 *********************************************************************************** 1681 ** ATU Command Register - ATUCMD 1682 ** ----------------------------------------------------------------- 1683 ** Bit Default Description 1684 ** 15:11 000000 2 Reserved 1685 ** 10 0 Interrupt Disable - This bit disables 80331 from asserting the ATU interrupt signal. 1686 ** 0=enables the assertion of interrupt signal. 1687 ** 1=disables the assertion of its interrupt signal. 1688 ** 09 0 2 Fast Back to Back Enable - When cleared, the ATU interface is not allowed to generate fast back-to-back cycles on its bus. Ignored when operating in the PCI-X mode. 1689 ** 08 0 2 SERR# Enable - When cleared, the ATU interface is not allowed to assert SERR# on the PCI interface. 1690 ** 07 1 2 Address/Data Stepping Control - Address stepping is implemented for configuration transactions. The 1691 ** ATU inserts 2 clock cycles of address stepping for Conventional Mode and 4 clock cycles of address stepping for PCI-X mode. 1692 ** 06 0 2 Parity Error Response - When set, the ATU takes normal action when a parity error is detected. When cleared, parity checking is disabled. 1693 ** 05 0 2 VGA Palette Snoop Enable - The ATU interface does not support I/O writes and therefore, does not perform VGA palette snooping. 1694 ** 04 0 2 Memory Write and Invalidate Enable - When set, ATU may generate MWI commands. When clear, ATU use Memory Write commands instead of MWI. Ignored when operating in the PCI-X mode. 1695 ** 03 0 2 Special Cycle Enable - The ATU interface does not respond to special cycle commands in any way. Not implemented and a reserved bit field. 1696 ** 02 0 2 Bus Master Enable - The ATU interface can act as a master on the PCI bus. When cleared, disables the device from generating PCI accesses. When set, allows the device to behave as a PCI bus master. 1697 ** When operating in the PCI-X mode, ATU initiates a split completion transaction regardless of the state of this bit. 1698 ** 01 0 2 Memory Enable - Controls the ATU interface��s response to PCI memory addresses. When cleared, the ATU interface does not respond to any memory access on the PCI bus. 1699 ** 00 0 2 I/O Space Enable - Controls the ATU interface response to I/O transactions. Not implemented and a reserved bit field. 1700 *********************************************************************************** 1701 */ 1702 #define ARCMSR_ATU_COMMAND_REG 0x04 /*word*/ 1703 /* 1704 *********************************************************************************** 1705 ** ATU Status Register - ATUSR (Sheet 1 of 2) 1706 ** ----------------------------------------------------------------- 1707 ** Bit Default Description 1708 ** 15 0 2 Detected Parity Error - set when a parity error is detected in data received by the ATU on the PCI bus even 1709 ** when the ATUCMD register��s Parity Error Response bit is cleared. Set under the following conditions: 1710 ** �E Write Data Parity Error when the ATU is a target (inbound write). 1711 ** �E Read Data Parity Error when the ATU is a requester (outbound read). 1712 ** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus (including one generated by the ATU). 1713 ** 14 0 2 SERR# Asserted - set when SERR# is asserted on the PCI bus by the ATU. 1714 ** 13 0 2 Master Abort - set when a transaction initiated by the ATU PCI master interface, ends in a Master-Abort 1715 ** or when the ATU receives a Master Abort Split Completion Error Message in PCI-X mode. 1716 ** 12 0 2 Target Abort (master) - set when a transaction initiated by the ATU PCI master interface, ends in a target 1717 ** abort or when the ATU receives a Target Abort Split Completion Error Message in PCI-X mode. 1718 ** 11 0 2 Target Abort (target) - set when the ATU interface, acting as a target, terminates the transaction on the PCI bus with a target abort. 1719 ** 10:09 01 2 DEVSEL# Timing - These bits are read-only and define the slowest DEVSEL# timing for a target device in Conventional PCI Mode regardless of the operating mode (except configuration accesses). 1720 ** 00 2=Fast 1721 ** 01 2=Medium 1722 ** 10 2=Slow 1723 ** 11 2=Reserved 1724 ** The ATU interface uses Medium timing. 1725 ** 08 0 2 Master Parity Error - The ATU interface sets this bit under the following conditions: 1726 ** �E The ATU asserted PERR# itself or the ATU observed PERR# asserted. 1727 ** �E And the ATU acted as the requester for the operation in which the error occurred. 1728 ** �E And the ATUCMD register��s Parity Error Response bit is set 1729 ** �E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message 1730 ** �E And the ATUCMD register��s Parity Error Response bit is set 1731 ** 07 1 2 (Conventional mode) 1732 ** 0 2 (PCI-X mode) 1733 ** Fast Back-to-Back - The ATU/Messaging Unit interface is capable of accepting fast back-to-back 1734 ** transactions in Conventional PCI mode when the transactions are not to the same target. Since fast 1735 ** back-to-back transactions do not exist in PCI-X mode, this bit is forced to 0 in the PCI-X mode. 1736 ** 06 0 2 UDF Supported - User Definable Features are not supported 1737 ** 05 1 2 66 MHz. Capable - 66 MHz operation is supported. 1738 ** 04 1 2 Capabilities - When set, this function implements extended capabilities. 1739 ** 03 0 Interrupt Status - reflects the state of the ATU interrupt when the Interrupt Disable bit in the command register is a 0. 1740 ** 0=ATU interrupt signal deasserted. 1741 ** 1=ATU interrupt signal asserted. 1742 ** NOTE: Setting the Interrupt Disable bit to a 1 has no effect on the state of this bit. Refer to 1743 ** Section 3.10.23, ��ATU Interrupt Pin Register - ATUIPR�� on page 236 for details on the ATU 1744 ** interrupt signal. 1745 ** 02:00 00000 2 Reserved. 1746 *********************************************************************************** 1747 */ 1748 #define ARCMSR_ATU_STATUS_REG 0x06 /*word*/ 1749 /* 1750 *********************************************************************************** 1751 ** ATU Revision ID Register - ATURID 1752 ** ----------------------------------------------------------------- 1753 ** Bit Default Description 1754 ** 07:00 00H ATU Revision - identifies the 80331 revision number. 1755 *********************************************************************************** 1756 */ 1757 #define ARCMSR_ATU_REVISION_REG 0x08 /*byte*/ 1758 /* 1759 *********************************************************************************** 1760 ** ATU Class Code Register - ATUCCR 1761 ** ----------------------------------------------------------------- 1762 ** Bit Default Description 1763 ** 23:16 05H Base Class - Memory Controller 1764 ** 15:08 80H Sub Class - Other Memory Controller 1765 ** 07:00 00H Programming Interface - None defined 1766 *********************************************************************************** 1767 */ 1768 #define ARCMSR_ATU_CLASS_CODE_REG 0x09 /*3bytes 0x0B,0x0A,0x09*/ 1769 /* 1770 *********************************************************************************** 1771 ** ATU Cacheline Size Register - ATUCLSR 1772 ** ----------------------------------------------------------------- 1773 ** Bit Default Description 1774 ** 07:00 00H ATU Cacheline Size - specifies the system cacheline size in DWORDs. Cacheline size is restricted to either 0, 8 or 16 DWORDs. 1775 *********************************************************************************** 1776 */ 1777 #define ARCMSR_ATU_CACHELINE_SIZE_REG 0x0C /*byte*/ 1778 /* 1779 *********************************************************************************** 1780 ** ATU Latency Timer Register - ATULT 1781 ** ----------------------------------------------------------------- 1782 ** Bit Default Description 1783 ** 07:03 00000 2 (for Conventional mode) 1784 ** 01000 2 (for PCI-X mode) 1785 ** Programmable Latency Timer - This field varies the latency timer for the interface from 0 to 248 clocks. 1786 ** The default value is 0 clocks for Conventional PCI mode, and 64 clocks for PCI-X mode. 1787 ** 02:00 000 2 Latency Timer Granularity - These Bits are read only giving a programmable granularity of 8 clocks for the latency timer. 1788 *********************************************************************************** 1789 */ 1790 #define ARCMSR_ATU_LATENCY_TIMER_REG 0x0D /*byte*/ 1791 /* 1792 *********************************************************************************** 1793 ** ATU Header Type Register - ATUHTR 1794 ** ----------------------------------------------------------------- 1795 ** Bit Default Description 1796 ** 07 0 2 Single Function/Multi-Function Device - Identifies the 80331 as a single-function PCI device. 1797 ** 06:00 000000 2 PCI Header Type - This bit field indicates the type of PCI header implemented. The ATU interface 1798 ** header conforms to PCI Local Bus Specification, Revision 2.3. 1799 *********************************************************************************** 1800 */ 1801 #define ARCMSR_ATU_HEADER_TYPE_REG 0x0E /*byte*/ 1802 /* 1803 *********************************************************************************** 1804 ** ATU BIST Register - ATUBISTR 1805 ** 1806 ** The ATU BIST Register controls the functions the Intel XScale core performs when BIST is 1807 ** initiated. This register is the interface between the host processor requesting BIST functions and 1808 ** the 80331 replying with the results from the software implementation of the BIST functionality. 1809 ** ----------------------------------------------------------------- 1810 ** Bit Default Description 1811 ** 07 0 2 BIST Capable - This bit value is always equal to the ATUCR ATU BIST Interrupt Enable bit. 1812 ** 06 0 2 Start BIST - When the ATUCR BIST Interrupt Enable bit is set: 1813 ** Setting this bit generates an interrupt to the Intel XScale core to perform a software BIST function. 1814 ** The Intel XScale core clears this bit when the BIST software has completed with the BIST results 1815 ** found in ATUBISTR register bits [3:0]. 1816 ** When the ATUCR BIST Interrupt Enable bit is clear: 1817 ** Setting this bit does not generate an interrupt to the Intel XScale core and no BIST functions is performed. 1818 ** The Intel XScale core does not clear this bit. 1819 ** 05:04 00 2 Reserved 1820 ** 03:00 0000 2 BIST Completion Code - when the ATUCR BIST Interrupt Enable bit is set and the ATUBISTR Start BIST bit is set (bit 6): 1821 ** The Intel XScale core places the results of the software BIST in these bits. A nonzero value indicates a device-specific error. 1822 *********************************************************************************** 1823 */ 1824 #define ARCMSR_ATU_BIST_REG 0x0F /*byte*/ 1825 1826 /* 1827 *************************************************************************************** 1828 ** ATU Base Registers and Associated Limit Registers 1829 *************************************************************************************** 1830 ** Base Address Register Limit Register Description 1831 ** Inbound ATU Base Address Register 0 Inbound ATU Limit Register 0 Defines the inbound translation window 0 from the PCI bus. 1832 ** Inbound ATU Upper Base Address Register 0 N/A Together with ATU Base Address Register 0 defines the inbound translation window 0 from the PCI bus for DACs. 1833 ** Inbound ATU Base Address Register 1 Inbound ATU Limit Register 1 Defines inbound window 1 from the PCI bus. 1834 ** Inbound ATU Upper Base Address Register 1 N/A Together with ATU Base Address Register 1 defines inbound window 1 from the PCI bus for DACs. 1835 ** Inbound ATU Base Address Register 2 Inbound ATU Limit Register 2 Defines the inbound translation window 2 from the PCI bus. 1836 ** Inbound ATU Upper Base Address Register 2 N/A Together with ATU Base Address Register 2 defines the inbound translation window 2 from the PCI bus for DACs. 1837 ** Inbound ATU Base Address Register 3 Inbound ATU Limit Register 3 Defines the inbound translation window 3 from the PCI bus. 1838 ** Inbound ATU Upper Base Address Register 3 N/A Together with ATU Base Address Register 3 defines the inbound translation window 3 from the PCI bus for DACs. 1839 ** NOTE: This is a private BAR that resides outside of the standard PCI configuration header space (offsets 00H-3FH). 1840 ** Expansion ROM Base Address Register Expansion ROM Limit Register Defines the window of addresses used by a bus master for reading from an Expansion ROM. 1841 **-------------------------------------------------------------------------------------- 1842 ** ATU Inbound Window 1 is not a translate window. 1843 ** The ATU does not claim any PCI accesses that fall within this range. 1844 ** This window is used to allocate host memory for use by Private Devices. 1845 ** When enabled, the ATU interrupts the Intel XScale core when either the IABAR1 register or the IAUBAR1 register is written from the PCI bus. 1846 *********************************************************************************** 1847 */ 1848 1849 /* 1850 *********************************************************************************** 1851 ** Inbound ATU Base Address Register 0 - IABAR0 1852 ** 1853 ** . The Inbound ATU Base Address Register 0 (IABAR0) together with the Inbound ATU Upper Base Address Register 0 (IAUBAR0) defines the block of memory addresses where the inbound translation window 0 begins. 1854 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 1855 ** . The IABAR0 and IAUBAR0 define the base address and describes the required memory block size. 1856 ** . Bits 31 through 12 of the IABAR0 is either read/write bits or read only with a value of 0 1857 ** depending on the value located within the IALR0. 1858 ** This configuration allows the IABAR0 to be programmed per PCI Local Bus Specification. 1859 ** The first 4 Kbytes of memory defined by the IABAR0, IAUBAR0 and the IALR0 is reserved for the Messaging Unit. 1860 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 1861 ** Warning: 1862 ** When IALR0 is cleared prior to host configuration: 1863 ** the user should also clear the Prefetchable Indicator and the Type Indicator. 1864 ** Assuming IALR0 is not cleared: 1865 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 1866 ** when the Prefetchable Indicator is cleared prior to host configuration, 1867 ** the user should also set the Type Indicator for 32 bit addressability. 1868 ** b. For compliance to the PCI-X Addendum to the PCI Local Bus Specification, 1869 ** when the Prefetchable Indicator is set prior to host configuration, the user 1870 ** should also set the Type Indicator for 64 bit addressability. 1871 ** This is the default for IABAR0. 1872 ** ----------------------------------------------------------------- 1873 ** Bit Default Description 1874 ** 31:12 00000H Translation Base Address 0 - These bits define the actual location the translation function is to respond to when addressed from the PCI bus. 1875 ** 11:04 00H Reserved. 1876 ** 03 1 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 1877 ** 02:01 10 2 Type Indicator - Defines the width of the addressability for this memory window: 1878 ** 00 - Memory Window is locatable anywhere in 32 bit address space 1879 ** 10 - Memory Window is locatable anywhere in 64 bit address space 1880 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 1881 ** The ATU does not occupy I/O space, 1882 ** thus this bit must be zero. 1883 *********************************************************************************** 1884 */ 1885 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS0_REG 0x10 /*dword 0x13,0x12,0x11,0x10*/ 1886 #define ARCMSR_INBOUND_ATU_MEMORY_PREFETCHABLE 0x08 1887 #define ARCMSR_INBOUND_ATU_MEMORY_WINDOW64 0x04 1888 /* 1889 *********************************************************************************** 1890 ** Inbound ATU Upper Base Address Register 0 - IAUBAR0 1891 ** 1892 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 1893 ** Together with the Translation Base Address this register defines the actual location the translation 1894 ** function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 1895 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 1896 ** Note: 1897 ** When the Type indicator of IABAR0 is set to indicate 32 bit addressability, 1898 ** the IAUBAR0 register attributes are read-only. 1899 ** ----------------------------------------------------------------- 1900 ** Bit Default Description 1901 ** 31:0 00000H Translation Upper Base Address 0 - Together with the Translation Base Address 0 these bits define the 1902 ** actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes. 1903 *********************************************************************************** 1904 */ 1905 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS0_REG 0x14 /*dword 0x17,0x16,0x15,0x14*/ 1906 /* 1907 *********************************************************************************** 1908 ** Inbound ATU Base Address Register 1 - IABAR1 1909 ** 1910 ** . The Inbound ATU Base Address Register (IABAR1) together with the Inbound ATU Upper Base Address Register 1 (IAUBAR1) defines the block of memory addresses where the inbound translation window 1 begins. 1911 ** . This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PCI bus transactions to this memory range. 1912 ** . The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 1913 ** . When enabled, the ATU interrupts the Intel XScale core when the IABAR1 register is written from the PCI bus. 1914 ** Warning: 1915 ** When a non-zero value is not written to IALR1 prior to host configuration, 1916 ** the user should not set either the Prefetchable Indicator or the Type Indicator for 64 bit addressability. 1917 ** This is the default for IABAR1. 1918 ** Assuming a non-zero value is written to IALR1, 1919 ** the user may set the Prefetchable Indicator 1920 ** or the Type Indicator: 1921 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address 1922 ** boundary, when the Prefetchable Indicator is not set prior to host configuration, 1923 ** the user should also leave the Type Indicator set for 32 bit addressability. 1924 ** This is the default for IABAR1. 1925 ** b. when the Prefetchable Indicator is set prior to host configuration, 1926 ** the user should also set the Type Indicator for 64 bit addressability. 1927 ** ----------------------------------------------------------------- 1928 ** Bit Default Description 1929 ** 31:12 00000H Translation Base Address 1 - These bits define the actual location of window 1 on the PCI bus. 1930 ** 11:04 00H Reserved. 1931 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 1932 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 1933 ** 00 - Memory Window is locatable anywhere in 32 bit address space 1934 ** 10 - Memory Window is locatable anywhere in 64 bit address space 1935 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 1936 ** The ATU does not occupy I/O space, 1937 ** thus this bit must be zero. 1938 *********************************************************************************** 1939 */ 1940 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS1_REG 0x18 /*dword 0x1B,0x1A,0x19,0x18*/ 1941 /* 1942 *********************************************************************************** 1943 ** Inbound ATU Upper Base Address Register 1 - IAUBAR1 1944 ** 1945 ** This register contains the upper base address when locating this window for PCI addresses beyond 4 GBytes. 1946 ** Together with the IABAR1 this register defines the actual location for this memory window for addresses > 4GBytes (for DACs). 1947 ** This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PCI bus transactions to this memory range. 1948 ** The programmed value within the base address register must comply with the PCI programming 1949 ** requirements for address alignment. 1950 ** When enabled, the ATU interrupts the Intel XScale core when the IAUBAR1 register is written 1951 ** from the PCI bus. 1952 ** Note: 1953 ** When the Type indicator of IABAR1 is set to indicate 32 bit addressability, 1954 ** the IAUBAR1 register attributes are read-only. 1955 ** This is the default for IABAR1. 1956 ** ----------------------------------------------------------------- 1957 ** Bit Default Description 1958 ** 31:0 00000H Translation Upper Base Address 1 - Together with the Translation Base Address 1 these bits define the actual location for this memory window on the PCI bus for addresses > 4GBytes. 1959 *********************************************************************************** 1960 */ 1961 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS1_REG 0x1C /*dword 0x1F,0x1E,0x1D,0x1C*/ 1962 /* 1963 *********************************************************************************** 1964 ** Inbound ATU Base Address Register 2 - IABAR2 1965 ** 1966 ** . The Inbound ATU Base Address Register 2 (IABAR2) together with the Inbound ATU Upper Base Address Register 2 (IAUBAR2) defines the block of memory addresses where the inbound translation window 2 begins. 1967 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 1968 ** . The IABAR2 and IAUBAR2 define the base address and describes the required memory block size 1969 ** . Bits 31 through 12 of the IABAR2 is either read/write bits or read only with a value of 0 depending on the value located within the IALR2. 1970 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 1971 ** Warning: 1972 ** When a non-zero value is not written to IALR2 prior to host configuration, 1973 ** the user should not set either the Prefetchable Indicator 1974 ** or the Type Indicator for 64 bit addressability. 1975 ** This is the default for IABAR2. 1976 ** Assuming a non-zero value is written to IALR2, 1977 ** the user may set the Prefetchable Indicator 1978 ** or the Type Indicator: 1979 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 1980 ** when the Prefetchable Indicator is not set prior to host configuration, 1981 ** the user should also leave the Type Indicator set for 32 bit addressability. 1982 ** This is the default for IABAR2. 1983 ** b. when the Prefetchable Indicator is set prior to host configuration, 1984 ** the user should also set the Type Indicator for 64 bit addressability. 1985 ** ----------------------------------------------------------------- 1986 ** Bit Default Description 1987 ** 31:12 00000H Translation Base Address 2 - These bits define the actual location the translation function is to respond to when addressed from the PCI bus. 1988 ** 11:04 00H Reserved. 1989 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 1990 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 1991 ** 00 - Memory Window is locatable anywhere in 32 bit address space 1992 ** 10 - Memory Window is locatable anywhere in 64 bit address space 1993 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 1994 ** The ATU does not occupy I/O space, 1995 ** thus this bit must be zero. 1996 *********************************************************************************** 1997 */ 1998 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS2_REG 0x20 /*dword 0x23,0x22,0x21,0x20*/ 1999 /* 2000 *********************************************************************************** 2001 ** Inbound ATU Upper Base Address Register 2 - IAUBAR2 2002 ** 2003 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 2004 ** Together with the Translation Base Address this register defines the actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 2005 ** The programmed value within the base address register must comply with the PCI programming 2006 ** requirements for address alignment. 2007 ** Note: 2008 ** When the Type indicator of IABAR2 is set to indicate 32 bit addressability, 2009 ** the IAUBAR2 register attributes are read-only. 2010 ** This is the default for IABAR2. 2011 ** ----------------------------------------------------------------- 2012 ** Bit Default Description 2013 ** 31:0 00000H Translation Upper Base Address 2 - Together with the Translation Base Address 2 these bits define the actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes. 2014 *********************************************************************************** 2015 */ 2016 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS2_REG 0x24 /*dword 0x27,0x26,0x25,0x24*/ 2017 /* 2018 *********************************************************************************** 2019 ** ATU Subsystem Vendor ID Register - ASVIR 2020 ** ----------------------------------------------------------------- 2021 ** Bit Default Description 2022 ** 15:0 0000H Subsystem Vendor ID - This register uniquely identifies the add-in board or subsystem vendor. 2023 *********************************************************************************** 2024 */ 2025 #define ARCMSR_ATU_SUBSYSTEM_VENDOR_ID_REG 0x2C /*word 0x2D,0x2C*/ 2026 /* 2027 *********************************************************************************** 2028 ** ATU Subsystem ID Register - ASIR 2029 ** ----------------------------------------------------------------- 2030 ** Bit Default Description 2031 ** 15:0 0000H Subsystem ID - uniquely identifies the add-in board or subsystem. 2032 *********************************************************************************** 2033 */ 2034 #define ARCMSR_ATU_SUBSYSTEM_ID_REG 0x2E /*word 0x2F,0x2E*/ 2035 /* 2036 *********************************************************************************** 2037 ** Expansion ROM Base Address Register -ERBAR 2038 ** ----------------------------------------------------------------- 2039 ** Bit Default Description 2040 ** 31:12 00000H Expansion ROM Base Address - These bits define the actual location where the Expansion ROM address window resides when addressed from the PCI bus on any 4 Kbyte boundary. 2041 ** 11:01 000H Reserved 2042 ** 00 0 2 Address Decode Enable - This bit field shows the ROM address decoder is enabled or disabled. When cleared, indicates the address decoder is disabled. 2043 *********************************************************************************** 2044 */ 2045 #define ARCMSR_EXPANSION_ROM_BASE_ADDRESS_REG 0x30 /*dword 0x33,0x32,0v31,0x30*/ 2046 #define ARCMSR_EXPANSION_ROM_ADDRESS_DECODE_ENABLE 0x01 2047 /* 2048 *********************************************************************************** 2049 ** ATU Capabilities Pointer Register - ATU_CAP_PTR 2050 ** ----------------------------------------------------------------- 2051 ** Bit Default Description 2052 ** 07:00 C0H Capability List Pointer - This provides an offset in this function��s configuration space that points to the 80331 PCl Bus Power Management extended capability. 2053 *********************************************************************************** 2054 */ 2055 #define ARCMSR_ATU_CAPABILITY_PTR_REG 0x34 /*byte*/ 2056 /* 2057 *********************************************************************************** 2058 ** Determining Block Sizes for Base Address Registers 2059 ** The required address size and type can be determined by writing ones to a base address register and 2060 ** reading from the registers. By scanning the returned value from the least-significant bit of the base 2061 ** address registers upwards, the programmer can determine the required address space size. The 2062 ** binary-weighted value of the first non-zero bit found indicates the required amount of space. 2063 ** Table 105 describes the relationship between the values read back and the byte sizes the base 2064 ** address register requires. 2065 ** As an example, assume that FFFF.FFFFH is written to the ATU Inbound Base Address Register 0 2066 ** (IABAR0) and the value read back is FFF0.0008H. Bit zero is a zero, so the device requires 2067 ** memory address space. Bit three is one, so the memory does supports prefetching. Scanning 2068 ** upwards starting at bit four, bit twenty is the first one bit found. The binary-weighted value of this 2069 ** bit is 1,048,576, indicated that the device requires 1 Mbyte of memory space. 2070 ** The ATU Base Address Registers and the Expansion ROM Base Address Register use their 2071 ** associated limit registers to enable which bits within the base address register are read/write and 2072 ** which bits are read only (0). This allows the programming of these registers in a manner similar to 2073 ** other PCI devices even though the limit is variable. 2074 ** Table 105. Memory Block Size Read Response 2075 ** Response After Writing all 1s 2076 ** to the Base Address Register 2077 ** Size 2078 ** (Bytes) 2079 ** Response After Writing all 1s 2080 ** to the Base Address Register 2081 ** Size 2082 ** (Bytes) 2083 ** FFFFFFF0H 16 FFF00000H 1 M 2084 ** FFFFFFE0H 32 FFE00000H 2 M 2085 ** FFFFFFC0H 64 FFC00000H 4 M 2086 ** FFFFFF80H 128 FF800000H 8 M 2087 ** FFFFFF00H 256 FF000000H 16 M 2088 ** FFFFFE00H 512 FE000000H 32 M 2089 ** FFFFFC00H 1K FC000000H 64 M 2090 ** FFFFF800H 2K F8000000H 128 M 2091 ** FFFFF000H 4K F0000000H 256 M 2092 ** FFFFE000H 8K E0000000H 512 M 2093 ** FFFFC000H 16K C0000000H 1 G 2094 ** FFFF8000H 32K 80000000H 2 G 2095 ** FFFF0000H 64K 2096 ** 00000000H 2097 ** Register not 2098 ** imple-mented, 2099 ** no 2100 ** address 2101 ** space 2102 ** required. 2103 ** FFFE0000H 128K 2104 ** FFFC0000H 256K 2105 ** FFF80000H 512K 2106 ** 2107 *************************************************************************************** 2108 */ 2109 2110 2111 2112 /* 2113 *********************************************************************************** 2114 ** ATU Interrupt Line Register - ATUILR 2115 ** ----------------------------------------------------------------- 2116 ** Bit Default Description 2117 ** 07:00 FFH Interrupt Assigned - system-assigned value identifies which system interrupt controller��s interrupt 2118 ** request line connects to the device's PCI interrupt request lines (as specified in the interrupt pin register). 2119 ** A value of FFH signifies ��no connection�� or ��unknown��. 2120 *********************************************************************************** 2121 */ 2122 #define ARCMSR_ATU_INTERRUPT_LINE_REG 0x3C /*byte*/ 2123 /* 2124 *********************************************************************************** 2125 ** ATU Interrupt Pin Register - ATUIPR 2126 ** ----------------------------------------------------------------- 2127 ** Bit Default Description 2128 ** 07:00 01H Interrupt Used - A value of 01H signifies that the ATU interface unit uses INTA# as the interrupt pin. 2129 *********************************************************************************** 2130 */ 2131 #define ARCMSR_ATU_INTERRUPT_PIN_REG 0x3D /*byte*/ 2132 /* 2133 *********************************************************************************** 2134 ** ATU Minimum Grant Register - ATUMGNT 2135 ** ----------------------------------------------------------------- 2136 ** Bit Default Description 2137 ** 07:00 80H This register specifies how long a burst period the device needs in increments of 8 PCI clocks. 2138 *********************************************************************************** 2139 */ 2140 #define ARCMSR_ATU_MINIMUM_GRANT_REG 0x3E /*byte*/ 2141 /* 2142 *********************************************************************************** 2143 ** ATU Maximum Latency Register - ATUMLAT 2144 ** ----------------------------------------------------------------- 2145 ** Bit Default Description 2146 ** 07:00 00H Specifies frequency (how often) the device needs to access the PCI bus in increments of 8 PCI clocks. A zero value indicates the device has no stringent requirement. 2147 *********************************************************************************** 2148 */ 2149 #define ARCMSR_ATU_MAXIMUM_LATENCY_REG 0x3F /*byte*/ 2150 /* 2151 *********************************************************************************** 2152 ** Inbound Address Translation 2153 ** 2154 ** The ATU allows external PCI bus initiators to directly access the internal bus. 2155 ** These PCI bus initiators can read or write 80331 memory-mapped registers or 80331 local memory space. 2156 ** The process of inbound address translation involves two steps: 2157 ** 1. Address Detection. 2158 ** �E Determine when the 32-bit PCI address (64-bit PCI address during DACs) is 2159 ** within the address windows defined for the inbound ATU. 2160 ** �E Claim the PCI transaction with medium DEVSEL# timing in the conventional PCI 2161 ** mode and with Decode A DEVSEL# timing in the PCI-X mode. 2162 ** 2. Address Translation. 2163 ** �E Translate the 32-bit PCI address (lower 32-bit PCI address during DACs) to a 32-bit 80331 internal bus address. 2164 ** The ATU uses the following registers in inbound address window 0 translation: 2165 ** �E Inbound ATU Base Address Register 0 2166 ** �E Inbound ATU Limit Register 0 2167 ** �E Inbound ATU Translate Value Register 0 2168 ** The ATU uses the following registers in inbound address window 2 translation: 2169 ** �E Inbound ATU Base Address Register 2 2170 ** �E Inbound ATU Limit Register 2 2171 ** �E Inbound ATU Translate Value Register 2 2172 ** The ATU uses the following registers in inbound address window 3 translation: 2173 ** �E Inbound ATU Base Address Register 3 2174 ** �E Inbound ATU Limit Register 3 2175 ** �E Inbound ATU Translate Value Register 3 2176 ** Note: Inbound Address window 1 is not a translate window. 2177 ** Instead, window 1 may be used to allocate host memory for Private Devices. 2178 ** Inbound Address window 3 does not reside in the standard section of the configuration header (offsets 00H - 3CH), 2179 ** thus the host BIOS does not configure window 3. 2180 ** Window 3 is intended to be used as a special window into local memory for private PCI 2181 ** agents controlled by the 80331 in conjunction with the Private Memory Space of the bridge. 2182 ** PCI-to-PCI Bridge in 80331 or 2183 ** Inbound address detection is determined from the 32-bit PCI address, 2184 ** (64-bit PCI address during DACs) the base address register and the limit register. 2185 ** In the case of DACs none of the upper 32-bits of the address is masked during address comparison. 2186 ** 2187 ** The algorithm for detection is: 2188 ** 2189 ** Equation 1. Inbound Address Detection 2190 ** When (PCI_Address [31:0] & Limit_Register[31:0]) == (Base_Register[31:0] & PCI_Address [63:32]) == Base_Register[63:32] (for DACs only) 2191 ** the PCI Address is claimed by the Inbound ATU. 2192 ** 2193 ** The incoming 32-bit PCI address (lower 32-bits of the address in case of DACs) is bitwise ANDed 2194 ** with the associated inbound limit register. 2195 ** When the result matches the base register (and upper base address matches upper PCI address in case of DACs), 2196 ** the inbound PCI address is detected as being within the inbound translation window and is claimed by the ATU. 2197 ** 2198 ** Note: The first 4 Kbytes of the ATU inbound address translation window 0 are reserved for the Messaging Unit. 2199 ** Once the transaction is claimed, the address must be translated from a PCI address to a 32-bit 2200 ** internal bus address. In case of DACs upper 32-bits of the address is simply discarded and only the 2201 ** lower 32-bits are used during address translation. 2202 ** The algorithm is: 2203 ** 2204 ** 2205 ** Equation 2. Inbound Translation 2206 ** Intel I/O processor Internal Bus Address=(PCI_Address[31:0] & ~Limit_Register[31:0]) | ATU_Translate_Value_Register[31:0]. 2207 ** 2208 ** The incoming 32-bit PCI address (lower 32-bits in case of DACs) is first bitwise ANDed with the 2209 ** bitwise inverse of the limit register. This result is bitwise ORed with the ATU Translate Value and 2210 ** the result is the internal bus address. This translation mechanism is used for all inbound memory 2211 ** read and write commands excluding inbound configuration read and writes. 2212 ** In the PCI mode for inbound memory transactions, the only burst order supported is Linear 2213 ** Incrementing. For any other burst order, the ATU signals a Disconnect after the first data phase. 2214 ** The PCI-X supports linear incrementing only, and hence above situation is not encountered in the PCI-X mode. 2215 ** example: 2216 ** Register Values 2217 ** Base_Register=3A00 0000H 2218 ** Limit_Register=FF80 0000H (8 Mbyte limit value) 2219 ** Value_Register=B100 0000H 2220 ** Inbound Translation Window ranges from 3A00 0000H to 3A7F FFFFH (8 Mbytes) 2221 ** 2222 ** Address Detection (32-bit address) 2223 ** 2224 ** PCI_Address & Limit_Register == Base_Register 2225 ** 3A45 012CH & FF80 0000H == 3A00 0000H 2226 ** 2227 ** ANS: PCI_Address is in the Inbound Translation Window 2228 ** Address Translation (to get internal bus address) 2229 ** 2230 ** IB_Address=(PCI_Address & ~Limit_Register) | Value_Reg 2231 ** IB_Address=(3A45 012CH & 007F FFFFH) | B100 0000H 2232 ** 2233 ** ANS:IB_Address=B145 012CH 2234 *********************************************************************************** 2235 */ 2236 2237 2238 2239 /* 2240 *********************************************************************************** 2241 ** Inbound ATU Limit Register 0 - IALR0 2242 ** 2243 ** Inbound address translation for memory window 0 occurs for data transfers occurring from the PCI 2244 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 2245 ** PCI addresses to internal bus addresses. 2246 ** The 80331 translate value register��s programmed value must be naturally aligned with the base 2247 ** address register��s programmed value. The limit register is used as a mask; thus, the lower address 2248 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 2249 ** Specification, Revision 2.3 for additional information on programming base address registers. 2250 ** Bits 31 to 12 within the IALR0 have a direct effect on the IABAR0 register, bits 31 to 12, with a 2251 ** one to one correspondence. A value of 0 in a bit within the IALR0 makes the corresponding bit 2252 ** within the IABAR0 a read only bit which always returns 0. A value of 1 in a bit within the IALR0 2253 ** makes the corresponding bit within the IABAR0 read/write from PCI. Note that a consequence of 2254 ** this programming scheme is that unless a valid value exists within the IALR0, all writes to the 2255 ** IABAR0 has no effect since a value of all zeros within the IALR0 makes the IABAR0 a read only register. 2256 ** ----------------------------------------------------------------- 2257 ** Bit Default Description 2258 ** 31:12 FF000H Inbound Translation Limit 0 - This readback value determines the memory block size required for 2259 ** inbound memory window 0 of the address translation unit. This defaults to an inbound window of 16MB. 2260 ** 11:00 000H Reserved 2261 *********************************************************************************** 2262 */ 2263 #define ARCMSR_INBOUND_ATU_LIMIT0_REG 0x40 /*dword 0x43,0x42,0x41,0x40*/ 2264 /* 2265 *********************************************************************************** 2266 ** Inbound ATU Translate Value Register 0 - IATVR0 2267 ** 2268 ** The Inbound ATU Translate Value Register 0 (IATVR0) contains the internal bus address used to 2269 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 2270 ** inbound ATU address translation. 2271 ** ----------------------------------------------------------------- 2272 ** Bit Default Description 2273 ** 31:12 FF000H Inbound ATU Translation Value 0 - This value is used to convert the PCI address to internal bus addresses. 2274 ** This value must be 64-bit aligned on the internal bus. The default address allows the ATU to access the internal 80331 memory-mapped registers. 2275 ** 11:00 000H Reserved 2276 *********************************************************************************** 2277 */ 2278 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE0_REG 0x44 /*dword 0x47,0x46,0x45,0x44*/ 2279 /* 2280 *********************************************************************************** 2281 ** Expansion ROM Limit Register - ERLR 2282 ** 2283 ** The Expansion ROM Limit Register (ERLR) defines the block size of addresses the ATU defines 2284 ** as Expansion ROM address space. The block size is programmed by writing a value into the ERLR. 2285 ** Bits 31 to 12 within the ERLR have a direct effect on the ERBAR register, bits 31 to 12, with a one 2286 ** to one correspondence. A value of 0 in a bit within the ERLR makes the corresponding bit within 2287 ** the ERBAR a read only bit which always returns 0. A value of 1 in a bit within the ERLR makes 2288 ** the corresponding bit within the ERBAR read/write from PCI. 2289 ** ----------------------------------------------------------------- 2290 ** Bit Default Description 2291 ** 31:12 000000H Expansion ROM Limit - Block size of memory required for the Expansion ROM translation unit. Default 2292 ** value is 0, which indicates no Expansion ROM address space and all bits within the ERBAR are read only with a value of 0. 2293 ** 11:00 000H Reserved. 2294 *********************************************************************************** 2295 */ 2296 #define ARCMSR_EXPANSION_ROM_LIMIT_REG 0x48 /*dword 0x4B,0x4A,0x49,0x48*/ 2297 /* 2298 *********************************************************************************** 2299 ** Expansion ROM Translate Value Register - ERTVR 2300 ** 2301 ** The Expansion ROM Translate Value Register contains the 80331 internal bus address which the 2302 ** ATU converts the PCI bus access. This address is driven on the internal bus as a result of the 2303 ** Expansion ROM address translation. 2304 ** ----------------------------------------------------------------- 2305 ** Bit Default Description 2306 ** 31:12 00000H Expansion ROM Translation Value - Used to convert PCI addresses to 80331 internal bus addresses 2307 ** for Expansion ROM accesses. The Expansion ROM address translation value must be word aligned on the internal bus. 2308 ** 11:00 000H Reserved 2309 *********************************************************************************** 2310 */ 2311 #define ARCMSR_EXPANSION_ROM_TRANSLATE_VALUE_REG 0x4C /*dword 0x4F,0x4E,0x4D,0x4C*/ 2312 /* 2313 *********************************************************************************** 2314 ** Inbound ATU Limit Register 1 - IALR1 2315 ** 2316 ** Bits 31 to 12 within the IALR1 have a direct effect on the IABAR1 register, bits 31 to 12, with a 2317 ** one to one correspondence. A value of 0 in a bit within the IALR1 makes the corresponding bit 2318 ** within the IABAR1 a read only bit which always returns 0. A value of 1 in a bit within the IALR1 2319 ** makes the corresponding bit within the IABAR1 read/write from PCI. Note that a consequence of 2320 ** this programming scheme is that unless a valid value exists within the IALR1, all writes to the 2321 ** IABAR1 has no effect since a value of all zeros within the IALR1 makes the IABAR1 a read only 2322 ** register. 2323 ** The inbound memory window 1 is used merely to allocate memory on the PCI bus. The ATU does 2324 ** not process any PCI bus transactions to this memory range. 2325 ** Warning: The ATU does not claim any PCI accesses that fall within the range defined by IABAR1, 2326 ** IAUBAR1, and IALR1. 2327 ** ----------------------------------------------------------------- 2328 ** Bit Default Description 2329 ** 31:12 00000H Inbound Translation Limit 1 - This readback value determines the memory block size required for the ATUs memory window 1. 2330 ** 11:00 000H Reserved 2331 *********************************************************************************** 2332 */ 2333 #define ARCMSR_INBOUND_ATU_LIMIT1_REG 0x50 /*dword 0x53,0x52,0x51,0x50*/ 2334 /* 2335 *********************************************************************************** 2336 ** Inbound ATU Limit Register 2 - IALR2 2337 ** 2338 ** Inbound address translation for memory window 2 occurs for data transfers occurring from the PCI 2339 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 2340 ** PCI addresses to internal bus addresses. 2341 ** The inbound translation base address for inbound window 2 is specified in Section 3.10.15. When 2342 ** determining block size requirements �X as described in Section 3.10.21 �X the translation limit 2343 ** register provides the block size requirements for the base address register. The remaining registers 2344 ** used for performing address translation are discussed in Section 3.2.1.1. 2345 ** The 80331 translate value register��s programmed value must be naturally aligned with the base 2346 ** address register��s programmed value. The limit register is used as a mask; thus, the lower address 2347 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 2348 ** Specification, Revision 2.3 for additional information on programming base address registers. 2349 ** Bits 31 to 12 within the IALR2 have a direct effect on the IABAR2 register, bits 31 to 12, with a 2350 ** one to one correspondence. A value of 0 in a bit within the IALR2 makes the corresponding bit 2351 ** within the IABAR2 a read only bit which always returns 0. A value of 1 in a bit within the IALR2 2352 ** makes the corresponding bit within the IABAR2 read/write from PCI. Note that a consequence of 2353 ** this programming scheme is that unless a valid value exists within the IALR2, all writes to the 2354 ** IABAR2 has no effect since a value of all zeros within the IALR2 makes the IABAR2 a read only 2355 ** register. 2356 ** ----------------------------------------------------------------- 2357 ** Bit Default Description 2358 ** 31:12 00000H Inbound Translation Limit 2 - This readback value determines the memory block size required for the ATUs memory window 2. 2359 ** 11:00 000H Reserved 2360 *********************************************************************************** 2361 */ 2362 #define ARCMSR_INBOUND_ATU_LIMIT2_REG 0x54 /*dword 0x57,0x56,0x55,0x54*/ 2363 /* 2364 *********************************************************************************** 2365 ** Inbound ATU Translate Value Register 2 - IATVR2 2366 ** 2367 ** The Inbound ATU Translate Value Register 2 (IATVR2) contains the internal bus address used to 2368 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 2369 ** inbound ATU address translation. 2370 ** ----------------------------------------------------------------- 2371 ** Bit Default Description 2372 ** 31:12 00000H Inbound ATU Translation Value 2 - This value is used to convert the PCI address to internal bus addresses. 2373 ** This value must be 64-bit aligned on the internal bus. The default address allows the ATU to access the internal 80331 memory-mapped registers. 2374 ** 11:00 000H Reserved 2375 *********************************************************************************** 2376 */ 2377 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE2_REG 0x58 /*dword 0x5B,0x5A,0x59,0x58*/ 2378 /* 2379 *********************************************************************************** 2380 ** Outbound I/O Window Translate Value Register - OIOWTVR 2381 ** 2382 ** The Outbound I/O Window Translate Value Register (OIOWTVR) contains the PCI I/O address 2383 ** used to convert the internal bus access to a PCI address. This address is driven on the PCI bus as a 2384 ** result of the outbound ATU address translation. 2385 ** The I/O window is from 80331 internal bus address 9000 000H to 9000 FFFFH with the fixed 2386 ** length of 64 Kbytes. 2387 ** ----------------------------------------------------------------- 2388 ** Bit Default Description 2389 ** 31:16 0000H Outbound I/O Window Translate Value - Used to convert internal bus addresses to PCI addresses. 2390 ** 15:00 0000H Reserved 2391 *********************************************************************************** 2392 */ 2393 #define ARCMSR_OUTBOUND_IO_WINDOW_TRANSLATE_VALUE_REG 0x5C /*dword 0x5F,0x5E,0x5D,0x5C*/ 2394 /* 2395 *********************************************************************************** 2396 ** Outbound Memory Window Translate Value Register 0 -OMWTVR0 2397 ** 2398 ** The Outbound Memory Window Translate Value Register 0 (OMWTVR0) contains the PCI 2399 ** address used to convert 80331 internal bus addresses for outbound transactions. This address is 2400 ** driven on the PCI bus as a result of the outbound ATU address translation. 2401 ** The memory window is from internal bus address 8000 000H to 83FF FFFFH with the fixed length 2402 ** of 64 Mbytes. 2403 ** ----------------------------------------------------------------- 2404 ** Bit Default Description 2405 ** 31:26 00H Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses. 2406 ** 25:02 00 0000H Reserved 2407 ** 01:00 00 2 Burst Order - This bit field shows the address sequence during a memory burst. Only linear incrementing mode is supported. 2408 *********************************************************************************** 2409 */ 2410 #define ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x60 /*dword 0x63,0x62,0x61,0x60*/ 2411 /* 2412 *********************************************************************************** 2413 ** Outbound Upper 32-bit Memory Window Translate Value Register 0 - OUMWTVR0 2414 ** 2415 ** The Outbound Upper 32-bit Memory Window Translate Value Register 0 (OUMWTVR0) defines 2416 ** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to 2417 ** directly address anywhere within the 64-bit host address space. When this register is all-zero, then 2418 ** a SAC is generated on the PCI bus. 2419 ** The memory window is from internal bus address 8000 000H to 83FF FFFFH with the fixed 2420 ** length of 64 Mbytes. 2421 ** ----------------------------------------------------------------- 2422 ** Bit Default Description 2423 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 2424 *********************************************************************************** 2425 */ 2426 #define ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x64 /*dword 0x67,0x66,0x65,0x64*/ 2427 /* 2428 *********************************************************************************** 2429 ** Outbound Memory Window Translate Value Register 1 -OMWTVR1 2430 ** 2431 ** The Outbound Memory Window Translate Value Register 1 (OMWTVR1) contains the PCI 2432 ** address used to convert 80331 internal bus addresses for outbound transactions. This address is 2433 ** driven on the PCI bus as a result of the outbound ATU address translation. 2434 ** The memory window is from internal bus address 8400 000H to 87FF FFFFH with the fixed length 2435 ** of 64 Mbytes. 2436 ** ----------------------------------------------------------------- 2437 ** Bit Default Description 2438 ** 31:26 00H Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses. 2439 ** 25:02 00 0000H Reserved 2440 ** 01:00 00 2 Burst Order - This bit field shows the address sequence during a memory burst. Only linear incrementing mode is supported. 2441 *********************************************************************************** 2442 */ 2443 #define ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x68 /*dword 0x6B,0x6A,0x69,0x68*/ 2444 /* 2445 *********************************************************************************** 2446 ** Outbound Upper 32-bit Memory Window Translate Value Register 1 - OUMWTVR1 2447 ** 2448 ** The Outbound Upper 32-bit Memory Window Translate Value Register 1 (OUMWTVR1) defines 2449 ** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to 2450 ** directly address anywhere within the 64-bit host address space. When this register is all-zero, then 2451 ** a SAC is generated on the PCI bus. 2452 ** The memory window is from internal bus address 8400 000H to 87FF FFFFH with the fixed length 2453 ** of 64 Mbytes. 2454 ** ----------------------------------------------------------------- 2455 ** Bit Default Description 2456 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 2457 *********************************************************************************** 2458 */ 2459 #define ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x6C /*dword 0x6F,0x6E,0x6D,0x6C*/ 2460 /* 2461 *********************************************************************************** 2462 ** Outbound Upper 32-bit Direct Window Translate Value Register - OUDWTVR 2463 ** 2464 ** The Outbound Upper 32-bit Direct Window Translate Value Register (OUDWTVR) defines the 2465 ** upper 32-bits of address used during a dual address cycle for the transactions via Direct Addressing 2466 ** Window. This enables the outbound ATU to directly address anywhere within the 64-bit host 2467 ** address space. When this register is all-zero, then a SAC is generated on the PCI bus. 2468 ** ----------------------------------------------------------------- 2469 ** Bit Default Description 2470 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 2471 *********************************************************************************** 2472 */ 2473 #define ARCMSR_OUTBOUND_UPPER32_DIRECT_WINDOW_TRANSLATE_VALUE_REG 0x78 /*dword 0x7B,0x7A,0x79,0x78*/ 2474 /* 2475 *********************************************************************************** 2476 ** ATU Configuration Register - ATUCR 2477 ** 2478 ** The ATU Configuration Register controls the outbound address translation for address translation 2479 ** unit. It also contains bits for Conventional PCI Delayed Read Command (DRC) aliasing, discard 2480 ** timer status, SERR# manual assertion, SERR# detection interrupt masking, and ATU BIST 2481 ** interrupt enabling. 2482 ** ----------------------------------------------------------------- 2483 ** Bit Default Description 2484 ** 31:20 00H Reserved 2485 ** 19 0 2 ATU DRC Alias - when set, the ATU does not distinguish read commands when attempting to match a 2486 ** current PCI read transaction with read data enqueued within the DRC buffer. When clear, a current read 2487 ** transaction must have the exact same read command as the DRR for the ATU to deliver DRC data. Not 2488 ** applicable in the PCI-X mode. 2489 ** 18 0 2 Direct Addressing Upper 2Gbytes Translation Enable - When set, with Direct Addressing enabled (bit 7 of the ATUCR set), the ATU forwards internal bus cycles with an address between 0000.0040H and 2490 ** 7FFF.FFFFH to the PCI bus with bit 31 of the address set (8000.0000H - FFFF.FFFFH). When clear, no translation occurs. 2491 ** 17 0 2 Reserved 2492 ** 16 0 2 SERR# Manual Assertion - when set, the ATU asserts SERR# for one clock on the PCI interface. Until 2493 ** cleared, SERR# may not be manually asserted again. Once cleared, operation proceeds as specified. 2494 ** 15 0 2 ATU Discard Timer Status - when set, one of the 4 discard timers within the ATU has expired and 2495 ** discarded the delayed completion transaction within the queue. When clear, no timer has expired. 2496 ** 14:10 00000 2 Reserved 2497 ** 09 0 2 SERR# Detected Interrupt Enable - When set, the Intel XScale core is signalled an HPI# interrupt 2498 ** when the ATU detects that SERR# was asserted. When clear, the Intel XScale core is not interrupted when SERR# is detected. 2499 ** 08 0 2 Direct Addressing Enable - Setting this bit enables direct outbound addressing through the ATU. 2500 ** Internal bus cycles with an address between 0000.0040H and 7FFF.FFFFH automatically forwards to 2501 ** the PCI bus with or without translation of address bit 31 based on the setting of bit 18 of the ATUCR. 2502 ** 07:04 0000 2 Reserved 2503 ** 03 0 2 ATU BIST Interrupt Enable - When set, enables an interrupt to the Intel XScale core when the start 2504 ** BIST bit is set in the ATUBISTR register. This bit is also reflected as the BIST Capable bit 7 in the ATUBISTR register. 2505 ** 02 0 2 Reserved 2506 ** 01 0 2 Outbound ATU Enable - When set, enables the outbound address translation unit. When cleared, disables the outbound ATU. 2507 ** 00 0 2 Reserved 2508 *********************************************************************************** 2509 */ 2510 #define ARCMSR_ATU_CONFIGURATION_REG 0x80 /*dword 0x83,0x82,0x81,0x80*/ 2511 /* 2512 *********************************************************************************** 2513 ** PCI Configuration and Status Register - PCSR 2514 ** 2515 ** The PCI Configuration and Status Register has additional bits for controlling and monitoring 2516 ** various features of the PCI bus interface. 2517 ** ----------------------------------------------------------------- 2518 ** Bit Default Description 2519 ** 31:19 0000H Reserved 2520 ** 18 0 2 Detected Address or Attribute Parity Error - set when a parity error is detected during either the address 2521 ** or attribute phase of a transaction on the PCI bus even when the ATUCMD register Parity Error 2522 ** Response bit is cleared. Set under the following conditions: 2523 ** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus (including one generated by the ATU). 2524 ** 17:16 Varies with 2525 ** external state 2526 ** of DEVSEL#, 2527 ** STOP#, and 2528 ** TRDY#, 2529 ** during 2530 ** P_RST# 2531 ** PCI-X capability - These two bits define the mode of the PCI bus (conventional or PCI-X) as well as the 2532 ** operating frequency in the case of PCI-X mode. 2533 ** 00 - Conventional PCI mode 2534 ** 01 - PCI-X 66 2535 ** 10 - PCI-X 100 2536 ** 11 - PCI-X 133 2537 ** As defined by the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a, the operating 2538 ** mode is determined by an initialization pattern on the PCI bus during P_RST# assertion: 2539 ** DEVSEL# STOP# TRDY# Mode 2540 ** Deasserted Deasserted Deasserted Conventional 2541 ** Deasserted Deasserted Asserted PCI-X 66 2542 ** Deasserted Asserted Deasserted PCI-X 100 2543 ** Deasserted Asserted Asserted PCI-X 133 2544 ** All other patterns are reserved. 2545 ** 15 0 2 2546 ** Outbound Transaction Queue Busy: 2547 ** 0=Outbound Transaction Queue Empty 2548 ** 1=Outbound Transaction Queue Busy 2549 ** 14 0 2 2550 ** Inbound Transaction Queue Busy: 2551 ** 0=Inbound Transaction Queue Empty 2552 ** 1=Inbound Transaction Queue Busy 2553 ** 13 0 2 Reserved. 2554 ** 12 0 2 2555 ** Discard Timer Value - This bit controls the time-out value for the four discard timers attached to the queues holding read data. 2556 ** A value of 0 indicates the time-out value is 2 15 clocks. 2557 ** A value of 1 indicates the time-out value is 2 10 clocks. 2558 ** 11 0 2 Reserved. 2559 ** 10 Varies with 2560 ** external state 2561 ** of M66EN 2562 ** during 2563 ** P_RST# 2564 ** Bus Operating at 66 MHz - When set, the interface has been initialized to function at 66 MHz in 2565 ** Conventional PCI mode by the assertion of M66EN during bus initialization. When clear, the interface 2566 ** has been initialized as a 33 MHz bus. 2567 ** NOTE: When PCSR bits 17:16 are not equal to zero, then this bit is meaningless since the 80331 is 2568 ** operating in PCI-X mode. 2569 ** 09 0 2 Reserved 2570 ** 08 Varies with 2571 ** external state 2572 ** of REQ64# 2573 ** during 2574 ** P_RST# 2575 ** PCI Bus 64-Bit Capable - When clear, the PCI bus interface has been configured as 64-bit capable by 2576 ** the assertion of REQ64# on the rising edge of P_RST#. When set, the PCI interface is configured as 2577 ** 32-bit only. 2578 ** 07:06 00 2 Reserved. 2579 ** 05 0 2 Reset Internal Bus - This bit controls the reset of the Intel XScale core and all units on the internal 2580 ** bus. In addition to the internal bus initialization, this bit triggers the assertion of the M_RST# pin for 2581 ** initialization of registered DIMMs. When set: 2582 ** When operating in the conventional PCI mode: 2583 ** �E All current PCI transactions being mastered by the ATU completes, and the ATU master interfaces 2584 ** proceeds to an idle state. No additional transactions is mastered by these units until the internal bus 2585 ** reset is complete. 2586 ** �E All current transactions being slaved by the ATU on either the PCI bus or the internal bus 2587 ** completes, and the ATU target interfaces proceeds to an idle state. All future slave transactions 2588 ** master aborts, with the exception of the completion cycle for the transaction that set the Reset 2589 ** Internal Bus bit in the PCSR. 2590 ** �E When the value of the Core Processor Reset bit in the PCSR (upon P_RST# assertion) is set, the 2591 ** Intel XScale core is held in reset when the internal bus reset is complete. 2592 ** �E The ATU ignores configuration cycles, and they appears as master aborts for: 32 Internal Bus clocks. 2593 ** �E The 80331 hardware clears this bit after the reset operation completes. 2594 ** When operating in the PCI-X mode: 2595 ** The ATU hardware responds the same as in Conventional PCI-X mode. However, this may create a 2596 ** problem in PCI-X mode for split requests in that there may still be an outstanding split completion that the 2597 ** ATU is either waiting to receive (Outbound Request) or initiate (Inbound Read Request). For a cleaner 2598 ** internal bus reset, host software can take the following steps prior to asserting Reset Internal bus: 2599 ** 1. Clear the Bus Master (bit 2 of the ATUCMD) and the Memory Enable (bit 1 of the ATUCMD) bits in 2600 ** the ATUCMD. This ensures that no new transactions, either outbound or inbound are enqueued. 2601 ** 2. Wait for both the Outbound (bit 15 of the PCSR) and Inbound Read (bit 14 of the PCSR) Transaction 2602 ** queue busy bits to be clear. 2603 ** 3. Set the Reset Internal Bus bit 2604 ** As a result, the ATU hardware resets the internal bus using the same logic as in conventional mode, 2605 ** however the user is now assured that the ATU no longer has any pending inbound or outbound split 2606 ** completion transactions. 2607 ** NOTE: Since the Reset Internal Bus bit is set using an inbound configuration cycle, the user is 2608 ** guaranteed that any prior configuration cycles have properly completed since there is only a one 2609 ** deep transaction queue for configuration transaction requests. The ATU sends the appropriate 2610 ** Split Write Completion Message to the Requester prior to the onset of Internal Bus Reset. 2611 ** 04 0 2 Bus Master Indicator Enable: Provides software control for the Bus Master Indicator signal P_BMI used 2612 ** for external RAIDIOS logic control of private devices. Only valid when operating with the bridge and 2613 ** central resource/arbiter disabled (BRG_EN =low, ARB_EN=low). 2614 ** 03 Varies with 2615 ** external state 2616 ** of PRIVDEV 2617 ** during 2618 ** P_RST# 2619 ** Private Device Enable - This bit indicates the state of the reset strap which enables the private device 2620 ** control mechanism within the PCI-to-PCI Bridge SISR configuration register. 2621 ** 0=Private Device control Disabled - SISR register bits default to zero 2622 ** 1=Private Device control Enabled - SISR register bits default to one 2623 ** 02 Varies with 2624 ** external state 2625 ** of RETRY 2626 ** during 2627 ** P_RST# 2628 ** Configuration Cycle Retry - When this bit is set, the PCI interface of the 80331 responds to all 2629 ** configuration cycles with a Retry condition. When clear, the 80331 responds to the appropriate 2630 ** configuration cycles. 2631 ** The default condition for this bit is based on the external state of the RETRY pin at the rising edge of 2632 ** P_RST#. When the external state of the pin is high, the bit is set. When the external state of the pin is 2633 ** low, the bit is cleared. 2634 ** 01 Varies with 2635 ** external state 2636 ** of 2637 ** CORE_RST# 2638 ** during 2639 ** P_RST# 2640 ** Core Processor Reset - This bit is set to its default value by the hardware when either P_RST# is 2641 ** asserted or the Reset Internal Bus bit in PCSR is set. When this bit is set, the Intel XScale core is 2642 ** being held in reset. Software cannot set this bit. Software is required to clear this bit to deassert Intel 2643 ** XScale core reset. 2644 ** The default condition for this bit is based on the external state of the CORE_RST# pin at the rising edge 2645 ** of P_RST#. When the external state of the pin is low, the bit is set. When the external state of the pin is 2646 ** high, the bit is clear. 2647 ** 00 Varies with 2648 ** external state 2649 ** of PRIVMEM 2650 ** during 2651 ** P_RST# 2652 ** Private Memory Enable - This bit indicates the state of the reset strap which enables the private device 2653 ** control mechanism within the PCI-to-PCI Bridge SDER configuration register. 2654 ** 0=Private Memory control Disabled - SDER register bit 2 default to zero 2655 ** 1=Private Memory control Enabled - SDER register bits 2 default to one 2656 *********************************************************************************** 2657 */ 2658 #define ARCMSR_PCI_CONFIGURATION_STATUS_REG 0x84 /*dword 0x87,0x86,0x85,0x84*/ 2659 /* 2660 *********************************************************************************** 2661 ** ATU Interrupt Status Register - ATUISR 2662 ** 2663 ** The ATU Interrupt Status Register is used to notify the core processor of the source of an ATU 2664 ** interrupt. In addition, this register is written to clear the source of the interrupt to the interrupt unit 2665 ** of the 80331. All bits in this register are Read/Clear. 2666 ** Bits 4:0 are a direct reflection of bits 14:11 and bit 8 (respectively) of the ATU Status Register 2667 ** (these bits are set at the same time by hardware but need to be cleared independently). Bit 7 is set 2668 ** by an error associated with the internal bus of the 80331. Bit 8 is for software BIST. The 2669 ** conditions that result in an ATU interrupt are cleared by writing a 1 to the appropriate bits in this 2670 ** register. 2671 ** Note: Bits 4:0, and bits 15 and 13:7 can result in an interrupt being driven to the Intel XScale core. 2672 ** ----------------------------------------------------------------- 2673 ** Bit Default Description 2674 ** 31:18 0000H Reserved 2675 ** 17 0 2 VPD Address Register Updated - This bit is set when a PCI bus configuration write occurs to the VPDAR 2676 ** register. Configuration register writes to the VPDAR does NOT result in bit 15 also being set. When set, 2677 ** this bit results in the assertion of the ATU Configure Register Write Interrupt. 2678 ** 16 0 2 Reserved 2679 ** 15 0 2 ATU Configuration Write - This bit is set when a PCI bus configuration write occurs to any ATU register. 2680 ** When set, this bit results in the assertion of the ATU Configure Register Write Interrupt. 2681 ** 14 0 2 ATU Inbound Memory Window 1 Base Updated - This bit is set when a PCI bus configuration write 2682 ** occurs to either the IABAR1 register or the IAUBAR1 register. Configuration register writes to these 2683 ** registers deos NOT result in bit 15 also being set. When set, this bit results in the assertion of the ATU 2684 ** Configure Register Write Interrupt. 2685 ** 13 0 2 Initiated Split Completion Error Message - This bit is set when the device initiates a Split Completion 2686 ** Message on the PCI Bus with the Split Completion Error attribute bit set. 2687 ** 12 0 2 Received Split Completion Error Message - This bit is set when the device receives a Split Completion 2688 ** Message from the PCI Bus with the Split Completion Error attribute bit set. 2689 ** 11 0 2 Power State Transition - When the Power State Field of the ATU Power Management Control/Status 2690 ** Register is written to transition the ATU function Power State from D0 to D3, D0 to D1, or D3 to D0 and 2691 ** the ATU Power State Transition Interrupt mask bit is cleared, this bit is set. 2692 ** 10 0 2 P_SERR# Asserted - set when P_SERR# is asserted on the PCI bus by the ATU. 2693 ** 09 0 2 Detected Parity Error - set when a parity error is detected on the PCI bus even when the ATUCMD 2694 ** register��s Parity Error Response bit is cleared. Set under the following conditions: 2695 ** �E Write Data Parity Error when the ATU is a target (inbound write). 2696 ** �E Read Data Parity Error when the ATU is an initiator (outbound read). 2697 ** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus. 2698 ** 08 0 2 ATU BIST Interrupt - When set, generates the ATU BIST Start Interrupt and indicates the host processor 2699 ** has set the Start BIST bit (ATUBISTR register bit 6), when the ATU BIST interrupt is enabled (ATUCR 2700 ** register bit 3). The Intel XScale core can initiate the software BIST and store the result in ATUBISTR 2701 ** register bits 3:0. 2702 ** Configuration register writes to the ATUBISTR does NOT result in bit 15 also being set or the assertion 2703 ** of the ATU Configure Register Write Interrupt. 2704 ** 07 0 2 Internal Bus Master Abort - set when a transaction initiated by the ATU internal bus initiator interface ends in a Master-abort. 2705 ** 06:05 00 2 Reserved. 2706 ** 04 0 2 P_SERR# Detected - set when P_SERR# is detected on the PCI bus by the ATU. 2707 ** 03 0 2 PCI Master Abort - set when a transaction initiated by the ATU PCI initiator interface ends in a Master-abort. 2708 ** 02 0 2 PCI Target Abort (master) - set when a transaction initiated by the ATU PCI master interface ends in a Target-abort. 2709 ** 01 0 2 PCI Target Abort (target) - set when the ATU interface, acting as a target, terminates the transaction on the PCI bus with a target abort. 2710 ** 00 0 2 PCI Master Parity Error - Master Parity Error - The ATU interface sets this bit under the following 2711 ** conditions: 2712 ** �E The ATU asserted PERR# itself or the ATU observed PERR# asserted. 2713 ** �E And the ATU acted as the requester for the operation in which the error occurred. 2714 ** �E And the ATUCMD register��s Parity Error Response bit is set 2715 ** �E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message 2716 ** �E And the ATUCMD register��s Parity Error Response bit is set 2717 *********************************************************************************** 2718 */ 2719 #define ARCMSR_ATU_INTERRUPT_STATUS_REG 0x88 /*dword 0x8B,0x8A,0x89,0x88*/ 2720 /* 2721 *********************************************************************************** 2722 ** ATU Interrupt Mask Register - ATUIMR 2723 ** 2724 ** The ATU Interrupt Mask Register contains the control bit to enable and disable interrupts 2725 ** generated by the ATU. 2726 ** ----------------------------------------------------------------- 2727 ** Bit Default Description 2728 ** 31:15 0 0000H Reserved 2729 ** 14 0 2 VPD Address Register Updated Mask - Controls the setting of bit 17 of the ATUISR and generation of the 2730 ** ATU Configuration Register Write interrupt when a PCI bus write occurs to the VPDAR register. 2731 ** 0=Not Masked 2732 ** 1=Masked 2733 ** 13 0 2 Reserved 2734 ** 12 0 2 Configuration Register Write Mask - Controls the setting of bit 15 of the ATUISR and generation of the 2735 ** ATU Configuration Register Write interrupt when a PCI bus write occurs to any ATU configuration register 2736 ** except those covered by mask bit 11 and bit 14 of this register, and ATU BIST enable bit 3 of the ATUCR. 2737 ** 0=Not Masked 2738 ** 1=Masked 2739 ** 11 1 2 ATU Inbound Memory Window 1 Base Updated Mask - Controls the setting of bit 14 of the ATUISR and 2740 ** generation of the ATU Configuration Register Write interrupt when a PCI bus write occurs to either the 2741 ** IABAR1 register or the IAUBAR1 register. 2742 ** 0=Not Masked 2743 ** 1=Masked 2744 ** 10 0 2 Initiated Split Completion Error Message Interrupt Mask - Controls the setting of bit 13 of the ATUISR and 2745 ** generation of the ATU Error interrupt when the ATU initiates a Split Completion Error Message. 2746 ** 0=Not Masked 2747 ** 1=Masked 2748 ** 09 0 2 Received Split Completion Error Message Interrupt Mask- Controls the setting of bit 12 of the ATUISR 2749 ** and generation of the ATU Error interrupt when a Split Completion Error Message results in bit 29 of the 2750 ** PCIXSR being set. 2751 ** 0=Not Masked 2752 ** 1=Masked 2753 ** 08 1 2 Power State Transition Interrupt Mask - Controls the setting of bit 12 of the ATUISR and generation of the 2754 ** ATU Error interrupt when ATU Power Management Control/Status Register is written to transition the 2755 ** ATU Function Power State from D0 to D3, D0 to D1, D1 to D3 or D3 to D0. 2756 ** 0=Not Masked 2757 ** 1=Masked 2758 ** 07 0 2 ATU Detected Parity Error Interrupt Mask - Controls the setting of bit 9 of the ATUISR and generation of 2759 ** the ATU Error interrupt when a parity error detected on the PCI bus that sets bit 15 of the ATUSR. 2760 ** 0=Not Masked 2761 ** 1=Masked 2762 ** 06 0 2 ATU SERR# Asserted Interrupt Mask - Controls the setting of bit 10 of the ATUISR and generation of the 2763 ** ATU Error interrupt when SERR# is asserted on the PCI interface resulting in bit 14 of the ATUSR being set. 2764 ** 0=Not Masked 2765 ** 1=Masked 2766 ** NOTE: This bit is specific to the ATU asserting SERR# and not detecting SERR# from another master. 2767 ** 05 0 2 ATU PCI Master Abort Interrupt Mask - Controls the setting of bit 3 of the ATUISR and generation of the 2768 ** ATU Error interrupt when a master abort error resulting in bit 13 of the ATUSR being set. 2769 ** 0=Not Masked 2770 ** 1=Masked 2771 ** 04 0 2 ATU PCI Target Abort (Master) Interrupt Mask- Controls the setting of bit 12 of the ATUISR and ATU Error 2772 ** generation of the interrupt when a target abort error resulting in bit 12 of the ATUSR being set 2773 ** 0=Not Masked 2774 ** 1=Masked 2775 ** 03 0 2 ATU PCI Target Abort (Target) Interrupt Mask- Controls the setting of bit 1 of the ATUISR and generation 2776 ** of the ATU Error interrupt when a target abort error resulting in bit 11 of the ATUSR being set. 2777 ** 0=Not Masked 2778 ** 1=Masked 2779 ** 02 0 2 ATU PCI Master Parity Error Interrupt Mask - Controls the setting of bit 0 of the ATUISR and generation 2780 ** of the ATU Error interrupt when a parity error resulting in bit 8 of the ATUSR being set. 2781 ** 0=Not Masked 2782 ** 1=Masked 2783 ** 01 0 2 ATU Inbound Error SERR# Enable - Controls when the ATU asserts (when enabled through the 2784 ** ATUCMD) SERR# on the PCI interface in response to a master abort on the internal bus during an 2785 ** inbound write transaction. 2786 ** 0=SERR# Not Asserted due to error 2787 ** 1=SERR# Asserted due to error 2788 ** 00 0 2 ATU ECC Target Abort Enable - Controls the ATU response on the PCI interface to a target abort (ECC 2789 ** error) from the memory controller on the internal bus. In conventional mode, this action only occurs 2790 ** during an inbound read transaction where the data phase that was target aborted on the internal bus is 2791 ** actually requested from the inbound read queue. 2792 ** 0=Disconnect with data (the data being up to 64 bits of 1��s) 2793 ** 1=Target Abort 2794 ** NOTE: In PCI-X Mode, The ATU initiates a Split Completion Error Message (with message class=2h - 2795 ** completer error and message index=81h - 80331 internal bus target abort) on the PCI bus, 2796 ** independent of the setting of this bit. 2797 *********************************************************************************** 2798 */ 2799 #define ARCMSR_ATU_INTERRUPT_MASK_REG 0x8C /*dword 0x8F,0x8E,0x8D,0x8C*/ 2800 /* 2801 *********************************************************************************** 2802 ** Inbound ATU Base Address Register 3 - IABAR3 2803 ** 2804 ** . The Inbound ATU Base Address Register 3 (IABAR3) together with the Inbound ATU Upper Base Address Register 3 (IAUBAR3) defines the block of memory addresses where the inbound translation window 3 begins. 2805 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 2806 ** . The IABAR3 and IAUBAR3 define the base address and describes the required memory block size. 2807 ** . Bits 31 through 12 of the IABAR3 is either read/write bits or read only with a value of 0 depending on the value located within the IALR3. 2808 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2809 ** Note: 2810 ** Since IABAR3 does not appear in the standard PCI configuration header space (offsets 00H - 3CH), 2811 ** IABAR3 is not configured by the host during normal system initialization. 2812 ** Warning: 2813 ** When a non-zero value is not written to IALR3, 2814 ** the user should not set either the Prefetchable Indicator 2815 ** or the Type Indicator for 64 bit addressability. 2816 ** This is the default for IABAR3. 2817 ** Assuming a non-zero value is written to IALR3, 2818 ** the user may set the Prefetchable Indicator 2819 ** or the Type Indicator: 2820 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 2821 ** when the Prefetchable Indicator is not set, 2822 ** the user should also leave the Type Indicator set for 32 bit addressability. 2823 ** This is the default for IABAR3. 2824 ** b. when the Prefetchable Indicator is set, 2825 ** the user should also set the Type Indicator for 64 bit addressability. 2826 ** ----------------------------------------------------------------- 2827 ** Bit Default Description 2828 ** 31:12 00000H Translation Base Address 3 - These bits define the actual location the translation function is to respond to when addressed from the PCI bus. 2829 ** 11:04 00H Reserved. 2830 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 2831 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 2832 ** 00 - Memory Window is locatable anywhere in 32 bit address space 2833 ** 10 - Memory Window is locatable anywhere in 64 bit address space 2834 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 2835 ** The ATU does not occupy I/O space, 2836 ** thus this bit must be zero. 2837 *********************************************************************************** 2838 */ 2839 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS3_REG 0x90 /*dword 0x93,0x92,0x91,0x90*/ 2840 /* 2841 *********************************************************************************** 2842 ** Inbound ATU Upper Base Address Register 3 - IAUBAR3 2843 ** 2844 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 2845 ** Together with the Translation Base Address this register defines the actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 2846 ** The programmed value within the base address register must comply with the PCI programming 2847 ** requirements for address alignment. 2848 ** Note: 2849 ** When the Type indicator of IABAR3 is set to indicate 32 bit addressability, 2850 ** the IAUBAR3 register attributes are read-only. 2851 ** This is the default for IABAR3. 2852 ** ----------------------------------------------------------------- 2853 ** Bit Default Description 2854 ** 31:0 00000H Translation Upper Base Address 3 - Together with the Translation Base Address 3 these bits define the actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes. 2855 *********************************************************************************** 2856 */ 2857 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS3_REG 0x94 /*dword 0x97,0x96,0x95,0x94*/ 2858 /* 2859 *********************************************************************************** 2860 ** Inbound ATU Limit Register 3 - IALR3 2861 ** 2862 ** Inbound address translation for memory window 3 occurs for data transfers occurring from the PCI 2863 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 2864 ** PCI addresses to internal bus addresses. 2865 ** The inbound translation base address for inbound window 3 is specified in Section 3.10.15. When 2866 ** determining block size requirements �X as described in Section 3.10.21 �X the translation limit 2867 ** register provides the block size requirements for the base address register. The remaining registers 2868 ** used for performing address translation are discussed in Section 3.2.1.1. 2869 ** The 80331 translate value register��s programmed value must be naturally aligned with the base 2870 ** address register��s programmed value. The limit register is used as a mask; thus, the lower address 2871 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 2872 ** Specification, Revision 2.3 for additional information on programming base address registers. 2873 ** Bits 31 to 12 within the IALR3 have a direct effect on the IABAR3 register, bits 31 to 12, with a 2874 ** one to one correspondence. A value of 0 in a bit within the IALR3 makes the corresponding bit 2875 ** within the IABAR3 a read only bit which always returns 0. A value of 1 in a bit within the IALR3 2876 ** makes the corresponding bit within the IABAR3 read/write from PCI. Note that a consequence of 2877 ** this programming scheme is that unless a valid value exists within the IALR3, all writes to the 2878 ** IABAR3 has no effect since a value of all zeros within the IALR3 makes the IABAR3 a read only 2879 ** register. 2880 ** ----------------------------------------------------------------- 2881 ** Bit Default Description 2882 ** 31:12 00000H Inbound Translation Limit 3 - This readback value determines the memory block size required for the ATUs memory window 3. 2883 ** 11:00 000H Reserved 2884 *********************************************************************************** 2885 */ 2886 #define ARCMSR_INBOUND_ATU_LIMIT3_REG 0x98 /*dword 0x9B,0x9A,0x99,0x98*/ 2887 /* 2888 *********************************************************************************** 2889 ** Inbound ATU Translate Value Register 3 - IATVR3 2890 ** 2891 ** The Inbound ATU Translate Value Register 3 (IATVR3) contains the internal bus address used to 2892 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 2893 ** inbound ATU address translation. 2894 ** ----------------------------------------------------------------- 2895 ** Bit Default Description 2896 ** 31:12 00000H Inbound ATU Translation Value 3 - This value is used to convert the PCI address to internal bus addresses. 2897 ** This value must be 64-bit aligned on the internal bus. The default address allows the ATU to 2898 ** access the internal 80331 memory-mapped registers. 2899 ** 11:00 000H Reserved 2900 *********************************************************************************** 2901 */ 2902 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE3_REG 0x9C /*dword 0x9F,0x9E,0x9D,0x9C*/ 2903 /* 2904 *********************************************************************************** 2905 ** Outbound Configuration Cycle Address Register - OCCAR 2906 ** 2907 ** The Outbound Configuration Cycle Address Register is used to hold the 32-bit PCI configuration 2908 ** cycle address. The Intel XScale core writes the PCI configuration cycles address which then 2909 ** enables the outbound configuration read or write. The Intel XScale core then performs a read or 2910 ** write to the Outbound Configuration Cycle Data Register to initiate the configuration cycle on the 2911 ** PCI bus. 2912 ** Note: Bits 15:11 of the configuration cycle address for Type 0 configuration cycles are defined differently 2913 ** for Conventional versus PCI-X modes. When 80331 software programs the OCCAR to initiate a 2914 ** Type 0 configuration cycle, the OCCAR should always be loaded based on the PCI-X definition for 2915 ** the Type 0 configuration cycle address. When operating in Conventional mode, the 80331 clears 2916 ** bits 15:11 of the OCCAR prior to initiating an outbound Type 0 configuration cycle. See the PCI-X 2917 ** Addendum to the PCI Local Bus Specification, Revision 1.0a for details on the two formats. 2918 ** ----------------------------------------------------------------- 2919 ** Bit Default Description 2920 ** 31:00 0000 0000H Configuration Cycle Address - These bits define the 32-bit PCI address used during an outbound configuration read or write cycle. 2921 *********************************************************************************** 2922 */ 2923 #define ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_ADDRESS_REG 0xA4 /*dword 0xA7,0xA6,0xA5,0xA4*/ 2924 /* 2925 *********************************************************************************** 2926 ** Outbound Configuration Cycle Data Register - OCCDR 2927 ** 2928 ** The Outbound Configuration Cycle Data Register is used to initiate a configuration read or write 2929 ** on the PCI bus. The register is logical rather than physical meaning that it is an address not a 2930 ** register. The Intel XScale core reads or writes the data registers memory-mapped address to 2931 ** initiate the configuration cycle on the PCI bus with the address found in the OCCAR. For a 2932 ** configuration write, the data is latched from the internal bus and forwarded directly to the OWQ. 2933 ** For a read, the data is returned directly from the ORQ to the Intel XScale core and is never 2934 ** actually entered into the data register (which does not physically exist). 2935 ** The OCCDR is only visible from 80331 internal bus address space and appears as a reserved value 2936 ** within the ATU configuration space. 2937 ** ----------------------------------------------------------------- 2938 ** Bit Default Description 2939 ** 31:00 0000 0000H Configuration Cycle Data - These bits define the data used during an outbound configuration read or write cycle. 2940 *********************************************************************************** 2941 */ 2942 #define ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_DATA_REG 0xAC /*dword 0xAF,0xAE,0xAD,0xAC*/ 2943 /* 2944 *********************************************************************************** 2945 ** VPD Capability Identifier Register - VPD_CAPID 2946 ** 2947 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 2948 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 2949 ** Capability contained in that header. In the case of the 80331, this is the VPD extended capability 2950 ** with an ID of 03H as defined by the PCI Local Bus Specification, Revision 2.3. 2951 ** ----------------------------------------------------------------- 2952 ** Bit Default Description 2953 ** 07:00 03H Cap_Id - This field with its�� 03H value identifies this item in the linked list of Extended Capability Headers as being the VPD capability registers. 2954 *********************************************************************************** 2955 */ 2956 #define ARCMSR_VPD_CAPABILITY_IDENTIFIER_REG 0xB8 /*byte*/ 2957 /* 2958 *********************************************************************************** 2959 ** VPD Next Item Pointer Register - VPD_NXTP 2960 ** 2961 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 2962 ** Revision 2.3. This register describes the location of the next item in the function��s capability list. 2963 ** For the 80331, this the final capability list, and hence, this register is set to 00H. 2964 ** ----------------------------------------------------------------- 2965 ** Bit Default Description 2966 ** 07:00 00H Next_ Item_ Pointer - This field provides an offset into the function��s configuration space pointing to the 2967 ** next item in the function��s capability list. Since the VPD capabilities are the last in the linked list of 2968 ** extended capabilities in the 80331, the register is set to 00H. 2969 *********************************************************************************** 2970 */ 2971 #define ARCMSR_VPD_NEXT_ITEM_PTR_REG 0xB9 /*byte*/ 2972 /* 2973 *********************************************************************************** 2974 ** VPD Address Register - VPD_AR 2975 ** 2976 ** The VPD Address register (VPDAR) contains the DWORD-aligned byte address of the VPD to be 2977 ** accessed. The register is read/write and the initial value at power-up is indeterminate. 2978 ** A PCI Configuration Write to the VPDAR interrupts the Intel XScale core. Software can use 2979 ** the Flag setting to determine whether the configuration write was intended to initiate a read or 2980 ** write of the VPD through the VPD Data Register. 2981 ** ----------------------------------------------------------------- 2982 ** Bit Default Description 2983 ** 15 0 2 Flag - A flag is used to indicate when a transfer of data between the VPD Data Register and the storage 2984 ** component has completed. Please see Section 3.9, ��Vital Product Data�� on page 201 for more details on 2985 ** how the 80331 handles the data transfer. 2986 ** 14:0 0000H VPD Address - This register is written to set the DWORD-aligned byte address used to read or write 2987 ** Vital Product Data from the VPD storage component. 2988 *********************************************************************************** 2989 */ 2990 #define ARCMSR_VPD_ADDRESS_REG 0xBA /*word 0xBB,0xBA*/ 2991 /* 2992 *********************************************************************************** 2993 ** VPD Data Register - VPD_DR 2994 ** 2995 ** This register is used to transfer data between the 80331 and the VPD storage component. 2996 ** ----------------------------------------------------------------- 2997 ** Bit Default Description 2998 ** 31:00 0000H VPD Data - Four bytes are always read or written through this register to/from the VPD storage component. 2999 *********************************************************************************** 3000 */ 3001 #define ARCMSR_VPD_DATA_REG 0xBC /*dword 0xBF,0xBE,0xBD,0xBC*/ 3002 /* 3003 *********************************************************************************** 3004 ** Power Management Capability Identifier Register -PM_CAPID 3005 ** 3006 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 3007 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 3008 ** Capability contained in that header. In the case of the 80331, this is the PCI Bus Power 3009 ** Management extended capability with an ID of 01H as defined by the PCI Bus Power Management 3010 ** Interface Specification, Revision 1.1. 3011 ** ----------------------------------------------------------------- 3012 ** Bit Default Description 3013 ** 07:00 01H Cap_Id - This field with its�� 01H value identifies this item in the linked list of Extended Capability Headers as being the PCI Power Management Registers. 3014 *********************************************************************************** 3015 */ 3016 #define ARCMSR_POWER_MANAGEMENT_CAPABILITY_IDENTIFIER_REG 0xC0 /*byte*/ 3017 /* 3018 *********************************************************************************** 3019 ** Power Management Next Item Pointer Register - PM_NXTP 3020 ** 3021 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 3022 ** Revision 2.3. This register describes the location of the next item in the function��s capability list. 3023 ** For the 80331, the next capability (MSI capability list) is located at off-set D0H. 3024 ** ----------------------------------------------------------------- 3025 ** Bit Default Description 3026 ** 07:00 D0H Next_ Item_ Pointer - This field provides an offset into the function��s configuration space pointing to the 3027 ** next item in the function��s capability list which in the 80331 is the MSI extended capabilities header. 3028 *********************************************************************************** 3029 */ 3030 #define ARCMSR_POWER_NEXT_ITEM_PTR_REG 0xC1 /*byte*/ 3031 /* 3032 *********************************************************************************** 3033 ** Power Management Capabilities Register - PM_CAP 3034 ** 3035 ** Power Management Capabilities bits adhere to the definitions in the PCI Bus Power Management 3036 ** Interface Specification, Revision 1.1. This register is a 16-bit read-only register which provides 3037 ** information on the capabilities of the ATU function related to power management. 3038 ** ----------------------------------------------------------------- 3039 ** Bit Default Description 3040 ** 15:11 00000 2 PME_Support - This function is not capable of asserting the PME# signal in any state, since PME# is not supported by the 80331. 3041 ** 10 0 2 D2_Support - This bit is set to 0 2 indicating that the 80331 does not support the D2 Power Management State 3042 ** 9 1 2 D1_Support - This bit is set to 1 2 indicating that the 80331 supports the D1 Power Management State 3043 ** 8:6 000 2 Aux_Current - This field is set to 000 2 indicating that the 80331 has no current requirements for the 3044 ** 3.3Vaux signal as defined in the PCI Bus Power Management Interface Specification, Revision 1.1 3045 ** 5 0 2 DSI - This field is set to 0 2 meaning that this function requires a device specific initialization sequence 3046 ** following the transition to the D0 uninitialized state. 3047 ** 4 0 2 Reserved. 3048 ** 3 0 2 PME Clock - Since the 80331 does not support PME# signal generation this bit is cleared to 0 2 . 3049 ** 2:0 010 2 Version - Setting these bits to 010 2 means that this function complies with PCI Bus Power Management Interface Specification, Revision 1.1 3050 *********************************************************************************** 3051 */ 3052 #define ARCMSR_POWER_MANAGEMENT_CAPABILITY_REG 0xC2 /*word 0xC3,0xC2*/ 3053 /* 3054 *********************************************************************************** 3055 ** Power Management Control/Status Register - PM_CSR 3056 ** 3057 ** Power Management Control/Status bits adhere to the definitions in the PCI Bus Power 3058 ** Management Interface Specification, Revision 1.1. This 16-bit register is the control and status 3059 ** interface for the power management extended capability. 3060 ** ----------------------------------------------------------------- 3061 ** Bit Default Description 3062 ** 15 0 2 PME_Status - This function is not capable of asserting the PME# signal in any state, since PME## is not supported by the 80331. 3063 ** 14:9 00H Reserved 3064 ** 8 0 2 PME_En - This bit is hardwired to read-only 0 2 since this function does not support PME# generation from any power state. 3065 ** 7:2 000000 2 Reserved 3066 ** 1:0 00 2 Power State - This 2-bit field is used both to determine the current power state of a function and to set the function into a new power state. The definition of the values is: 3067 ** 00 2 - D0 3068 ** 01 2 - D1 3069 ** 10 2 - D2 (Unsupported) 3070 ** 11 2 - D3 hot 3071 ** The 80331 supports only the D0 and D3 hot states. 3072 ** 3073 *********************************************************************************** 3074 */ 3075 #define ARCMSR_POWER_MANAGEMENT_CONTROL_STATUS_REG 0xC4 /*word 0xC5,0xC4*/ 3076 /* 3077 *********************************************************************************** 3078 ** PCI-X Capability Identifier Register - PX_CAPID 3079 ** 3080 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 3081 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 3082 ** Capability contained in that header. In the case of the 80331, this is the PCI-X extended capability with 3083 ** an ID of 07H as defined by the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a. 3084 ** ----------------------------------------------------------------- 3085 ** Bit Default Description 3086 ** 07:00 07H Cap_Id - This field with its�� 07H value identifies this item in the linked list of Extended Capability Headers as being the PCI-X capability registers. 3087 *********************************************************************************** 3088 */ 3089 #define ARCMSR_PCIX_CAPABILITY_IDENTIFIER_REG 0xE0 /*byte*/ 3090 /* 3091 *********************************************************************************** 3092 ** PCI-X Next Item Pointer Register - PX_NXTP 3093 ** 3094 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 3095 ** Revision 2.3. This register describes the location of the next item in the function��s capability list. 3096 ** By default, the PCI-X capability is the last capabilities list for the 80331, thus this register defaults 3097 ** to 00H. 3098 ** However, this register may be written to B8H prior to host configuration to include the VPD 3099 ** capability located at off-set B8H. 3100 ** Warning: Writing this register to any value other than 00H (default) or B8H is not supported and may 3101 ** produce unpredictable system behavior. 3102 ** In order to guarantee that this register is written prior to host configuration, the 80331 must be 3103 ** initialized at P_RST# assertion to Retry Type 0 configuration cycles (bit 2 of PCSR). Typically, 3104 ** the Intel XScale core would be enabled to boot immediately following P_RST# assertion in 3105 ** this case (bit 1 of PCSR), as well. Please see Table 125, ��PCI Configuration and Status Register - 3106 ** PCSR�� on page 253 for more details on the 80331 initialization modes. 3107 ** ----------------------------------------------------------------- 3108 ** Bit Default Description 3109 ** 07:00 00H Next_ Item_ Pointer - This field provides an offset into the function��s configuration space pointing to the 3110 ** next item in the function��s capability list. Since the PCI-X capabilities are the last in the linked list of 3111 ** extended capabilities in the 80331, the register is set to 00H. 3112 ** However, this field may be written prior to host configuration with B8H to extend the list to include the 3113 ** VPD extended capabilities header. 3114 *********************************************************************************** 3115 */ 3116 #define ARCMSR_PCIX_NEXT_ITEM_PTR_REG 0xE1 /*byte*/ 3117 /* 3118 *********************************************************************************** 3119 ** PCI-X Command Register - PX_CMD 3120 ** 3121 ** This register controls various modes and features of ATU and Message Unit when operating in the 3122 ** PCI-X mode. 3123 ** ----------------------------------------------------------------- 3124 ** Bit Default Description 3125 ** 15:7 000000000 2 Reserved. 3126 ** 6:4 011 2 Maximum Outstanding Split Transactions - This register sets the maximum number of Split Transactions 3127 ** the device is permitted to have outstanding at one time. 3128 ** Register Maximum Outstanding 3129 ** 0 1 3130 ** 1 2 3131 ** 2 3 3132 ** 3 4 3133 ** 4 8 3134 ** 5 12 3135 ** 6 16 3136 ** 7 32 3137 ** 3:2 00 2 Maximum Memory Read Byte Count - This register sets the maximum byte count the device uses when 3138 ** initiating a Sequence with one of the burst memory read commands. 3139 ** Register Maximum Byte Count 3140 ** 0 512 3141 ** 1 1024 3142 ** 2 2048 3143 ** 3 4096 3144 ** 1 0 2 3145 ** Enable Relaxed Ordering - The 80331 does not set the relaxed ordering bit in the Requester Attributes 3146 ** of Transactions. 3147 ** 0 0 2 Data Parity Error Recovery Enable - The device driver sets this bit to enable the device to attempt to 3148 ** recover from data parity errors. When this bit is 0 and the device is in PCI-X mode, the device asserts 3149 ** SERR# (when enabled) whenever the Master Data Parity Error bit (Status register, bit 8) is set. 3150 *********************************************************************************** 3151 */ 3152 #define ARCMSR_PCIX_COMMAND_REG 0xE2 /*word 0xE3,0xE2*/ 3153 /* 3154 *********************************************************************************** 3155 ** PCI-X Status Register - PX_SR 3156 ** 3157 ** This register identifies the capabilities and current operating mode of ATU, DMAs and Message 3158 ** Unit when operating in the PCI-X mode. 3159 ** ----------------------------------------------------------------- 3160 ** Bit Default Description 3161 ** 31:30 00 2 Reserved 3162 ** 29 0 2 Received Split Completion Error Message - This bit is set when the device receives a Split Completion 3163 ** Message with the Split Completion Error attribute bit set. Once set, this bit remains set until software 3164 ** writes a 1 to this location. 3165 ** 0=no Split Completion error message received. 3166 ** 1=a Split Completion error message has been received. 3167 ** 28:26 001 2 Designed Maximum Cumulative Read Size (DMCRS) - The value of this register depends on the setting 3168 ** of the Maximum Memory Read Byte Count field of the PCIXCMD register: 3169 ** DMCRS Max ADQs Maximum Memory Read Byte Count Register Setting 3170 ** 1 16 512 (Default) 3171 ** 2 32 1024 3172 ** 2 32 2048 3173 ** 2 32 4096 3174 ** 25:23 011 2 Designed Maximum Outstanding Split Transactions - The 80331 can have up to four outstanding split transactions. 3175 ** 22:21 01 2 Designed Maximum Memory Read Byte Count - The 80331 can generate memory reads with byte counts up to 1024 bytes. 3176 ** 20 1 2 80331 is a complex device. 3177 ** 19 0 2 Unexpected Split Completion - This bit is set when an unexpected Split Completion with this device��s 3178 ** Requester ID is received. Once set, this bit remains set until software writes a 1 to this location. 3179 ** 0=no unexpected Split Completion has been received. 3180 ** 1=an unexpected Split Completion has been received. 3181 ** 18 0 2 Split Completion Discarded - This bit is set when the device discards a Split Completion because the 3182 ** requester would not accept it. See Section 5.4.4 of the PCI-X Addendum to the PCI Local Bus 3183 ** Specification, Revision 1.0a for details. Once set, this bit remains set until software writes a 1 to this 3184 ** location. 3185 ** 0=no Split Completion has been discarded. 3186 ** 1=a Split Completion has been discarded. 3187 ** NOTE: The 80331 does not set this bit since there is no Inbound address responding to Inbound Read 3188 ** Requests with Split Responses (Memory or Register) that has ��read side effects.�� 3189 ** 17 1 2 80331 is a 133 MHz capable device. 3190 ** 16 1 2 or P_32BITPCI# 80331 with bridge enabled (BRG_EN=1) implements the ATU with a 64-bit interface on the secondary PCI bus, therefore this bit is always set. 3191 ** 80331 with no bridge and central resource disabled (BRG_EN=0, ARB_EN=0), use this bit to identify the add-in card to the system as 64-bit or 32-bit wide via a user-configurable strap (P_32BITPCI#). 3192 ** This strap, by default, identifies the add in card based on 80331 with bridge disabled as 64-bit unless the user attaches the appropriate pull-down resistor to the strap. 3193 ** 0=The bus is 32 bits wide. 3194 ** 1=The bus is 64 bits wide. 3195 ** 15:8 FFH Bus Number - This register is read for diagnostic purposes only. It indicates the number of the bus 3196 ** segment for the device containing this function. The function uses this number as part of its Requester 3197 ** ID and Completer ID. For all devices other than the source bridge, each time the function is addressed 3198 ** by a Configuration Write transaction, the function must update this register with the contents of AD[7::0] 3199 ** of the attribute phase of the Configuration Write, regardless of which register in the function is 3200 ** addressed by the transaction. The function is addressed by a Configuration Write transaction when all of 3201 ** the following are true: 3202 ** 1. The transaction uses a Configuration Write command. 3203 ** 2. IDSEL is asserted during the address phase. 3204 ** 3. AD[1::0] are 00b (Type 0 configuration transaction). 3205 ** 4. AD[10::08] of the configuration address contain the appropriate function number. 3206 ** 7:3 1FH Device Number - This register is read for diagnostic purposes only. It indicates the number of the device 3207 ** containing this function, i.e., the number in the Device Number field (AD[15::11]) of the address of a 3208 ** Type 0 configuration transaction that is assigned to the device containing this function by the connection 3209 ** of the system hardware. The system must assign a device number other than 00h (00h is reserved for 3210 ** the source bridge). The function uses this number as part of its Requester ID and Completer ID. Each 3211 ** time the function is addressed by a Configuration Write transaction, the device must update this register 3212 ** with the contents of AD[15::11] of the address phase of the Configuration Write, regardless of which 3213 ** register in the function is addressed by the transaction. The function is addressed by a Configuration 3214 ** Write transaction when all of the following are true: 3215 ** 1. The transaction uses a Configuration Write command. 3216 ** 2. IDSEL is asserted during the address phase. 3217 ** 3. AD[1::0] are 00b (Type 0 configuration transaction). 3218 ** 4. AD[10::08] of the configuration address contain the appropriate function number. 3219 ** 2:0 000 2 Function Number - This register is read for diagnostic purposes only. It indicates the number of this 3220 ** function; i.e., the number in the Function Number field (AD[10::08]) of the address of a Type 0 3221 ** configuration transaction to which this function responds. The function uses this number as part of its 3222 ** Requester ID and Completer ID. 3223 ** 3224 ************************************************************************** 3225 */ 3226 #define ARCMSR_PCIX_STATUS_REG 0xE4 /*dword 0xE7,0xE6,0xE5,0xE4*/ 3227 3228 /* 3229 ************************************************************************** 3230 ** Inbound Read Transaction 3231 ** ======================================================================== 3232 ** An inbound read transaction is initiated by a PCI initiator and is targeted at either 80331 local 3233 ** memory or a 80331 memory-mapped register space. The read transaction is propagated through 3234 ** the inbound transaction queue (ITQ) and read data is returned through the inbound read queue 3235 ** (IRQ). 3236 ** When operating in the conventional PCI mode, all inbound read transactions are processed as 3237 ** delayed read transactions. When operating in the PCI-X mode, all inbound read transactions are 3238 ** processed as split transactions. The ATUs PCI interface claims the read transaction and forwards 3239 ** the read request through to the internal bus and returns the read data to the PCI bus. Data flow for 3240 ** an inbound read transaction on the PCI bus is summarized in the following statements: 3241 ** �E The ATU claims the PCI read transaction when the PCI address is within the inbound 3242 ** translation window defined by ATU Inbound Base Address Register (and Inbound Upper Base 3243 ** Address Register during DACs) and Inbound Limit Register. 3244 ** �E When operating in the conventional PCI mode, when the ITQ is currently holding transaction 3245 ** information from a previous delayed read, the current transaction information is compared to 3246 ** the previous transaction information (based on the setting of the DRC Alias bit in 3247 ** Section 3.10.39, ��ATU Configuration Register - ATUCR�� on page 252). When there is a 3248 ** match and the data is in the IRQ, return the data to the master on the PCI bus. When there is a 3249 ** match and the data is not available, a Retry is signaled with no other action taken. When there 3250 ** is not a match and when the ITQ has less than eight entries, capture the transaction 3251 ** information, signal a Retry and initiate a delayed transaction. When there is not a match and 3252 ** when the ITQ is full, then signal a Retry with no other action taken. 3253 ** �X When an address parity error is detected, the address parity response defined in 3254 ** Section 3.7 is used. 3255 ** �E When operating in the conventional PCI mode, once read data is driven onto the PCI bus from 3256 ** the IRQ, it continues until one of the following is true: 3257 ** �X The initiator completes the PCI transaction. When there is data left unread in the IRQ, the 3258 ** data is flushed. 3259 ** �X An internal bus Target Abort was detected. In this case, the QWORD associated with the 3260 ** Target Abort is never entered into the IRQ, and therefore is never returned. 3261 ** �X Target Abort or a Disconnect with Data is returned in response to the Internal Bus Error. 3262 ** �X The IRQ becomes empty. In this case, the PCI interface signals a Disconnect with data to 3263 ** the initiator on the last data word available. 3264 ** �E When operating in the PCI-X mode, when ITQ is not full, the PCI address, attribute and 3265 ** command are latched into the available ITQ and a Split Response Termination is signalled to 3266 ** the initiator. 3267 ** �E When operating in the PCI-X mode, when the transaction does not cross a 1024 byte aligned 3268 ** boundary, then the ATU waits until it receives the full byte count from the internal bus target 3269 ** before returning read data by generating the split completion transaction on the PCI-X bus. 3270 ** When the read requested crosses at least one 1024 byte boundary, then ATU completes the 3271 ** transfer by returning data in 1024 byte aligned chunks. 3272 ** �E When operating in the PCI-X mode, once a split completion transaction has started, it 3273 ** continues until one of the following is true: 3274 ** �X The requester (now the target) generates a Retry Termination, or a Disconnection at Next 3275 ** ADB (when the requester is a bridge) 3276 ** �X The byte count is satisfied. 3277 ** �X An internal bus Target Abort was detected. The ATU generates a Split Completion 3278 ** Message (message class=2h - completer error, and message index=81h - target abort) to 3279 ** inform the requester about the abnormal condition. The ITQ for this transaction is flushed. 3280 ** Refer to Section 3.7.1. 3281 ** �X An internal bus Master Abort was detected. The ATU generates a Split Completion 3282 ** Message (message class=2h - completer error, and message index=80h - Master abort) to 3283 ** inform the requester about the abnormal condition. The ITQ for this transaction is flushed. 3284 ** Refer to Section 3.7.1 3285 ** �E When operating in the conventional PCI mode, when the master inserts wait states on the PCI 3286 ** bus, the ATU PCI slave interface waits with no premature disconnects. 3287 ** �E When a data parity error occurs signified by PERR# asserted from the initiator, no action is 3288 ** taken by the target interface. Refer to Section 3.7.2.5. 3289 ** �E When operating in the conventional PCI mode, when the read on the internal bus is 3290 ** target-aborted, either a target-abort or a disconnect with data is signaled to the initiator. This is 3291 ** based on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). When set, a 3292 ** target abort is used, when clear, a disconnect is used. 3293 ** �E When operating in the PCI-X mode (with the exception of the MU queue ports at offsets 40h 3294 ** and 44h), when the transaction on the internal bus resulted in a target abort, the ATU generates 3295 ** a Split Completion Message (message class=2h - completer error, and message index=81h - 3296 ** internal bus target abort) to inform the requester about the abnormal condition. For the MU 3297 ** queue ports, the ATU returns either a target abort or a single data phase disconnect depending 3298 ** on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). The ITQ for this 3299 ** transaction is flushed. Refer to Section 3.7.1. 3300 ** �E When operating in the conventional PCI mode, when the transaction on the internal bus 3301 ** resulted in a master abort, the ATU returns a target abort to inform the requester about the 3302 ** abnormal condition. The ITQ for this transaction is flushed. Refer to Section 3.7.1 3303 ** �E When operating in the PCI-X mode, when the transaction on the internal bus resulted in a 3304 ** master abort, the ATU generates a Split Completion Message (message class=2h - completer 3305 ** error, and message index=80h - internal bus master abort) to inform the requester about the 3306 ** abnormal condition. The ITQ for this transaction is flushed. Refer to Section 3.7.1. 3307 ** �E When operating in the PCI-X mode, when the Split Completion transaction completes with 3308 ** either Master-Abort or Target-Abort, the requester is indicating a failure condition that 3309 ** prevents it from accepting the completion it requested. In this case, since the Split Request 3310 ** addresses a location that has no read side effects, the completer must discard the Split 3311 ** Completion and take no further action. 3312 ** The data flow for an inbound read transaction on the internal bus is summarized in the following 3313 ** statements: 3314 ** �E The ATU internal bus master interface requests the internal bus when a PCI address appears in 3315 ** an ITQ and transaction ordering has been satisfied. When operating in the PCI-X mode the 3316 ** ATU does not use the information provided by the Relax Ordering Attribute bit. That is, ATU 3317 ** always uses conventional PCI ordering rules. 3318 ** �E Once the internal bus is granted, the internal bus master interface drives the translated address 3319 ** onto the bus and wait for IB_DEVSEL#. When a Retry is signaled, the request is repeated. 3320 ** When a master abort occurs, the transaction is considered complete and a target abort is loaded 3321 ** into the associated IRQ for return to the PCI initiator (transaction is flushed once the PCI 3322 ** master has been delivered the target abort). 3323 ** �E Once the translated address is on the bus and the transaction has been accepted, the internal 3324 ** bus target starts returning data with the assertion of IB_TRDY#. Read data is continuously 3325 ** received by the IRQ until one of the following is true: 3326 ** �X The full byte count requested by the ATU read request is received. The ATU internal bus 3327 ** initiator interface performs a initiator completion in this case. 3328 ** �X When operating in the conventional PCI mode, a Target Abort is received on the internal 3329 ** bus from the internal bus target. In this case, the transaction is aborted and the PCI side is 3330 ** informed. 3331 ** �X When operating in the PCI-X mode, a Target Abort is received on the internal bus from 3332 ** the internal bus target. In this case, the transaction is aborted. The ATU generates a Split 3333 ** Completion Message (message class=2h - completer error, and message index=81h - 3334 ** target abort) on the PCI bus to inform the requester about the abnormal condition. The 3335 ** ITQ for this transaction is flushed. 3336 ** �X When operating in the conventional PCI mode, a single data phase disconnection is 3337 ** received from the internal bus target. When the data has not been received up to the next 3338 ** QWORD boundary, the ATU internal bus master interface attempts to reacquire the bus. 3339 ** When not, the bus returns to idle. 3340 ** �X When operating in the PCI-X mode, a single data phase disconnection is received from 3341 ** the internal bus target. The ATU IB initiator interface attempts to reacquire the bus to 3342 ** obtain remaining data. 3343 ** �X When operating in the conventional PCI mode, a disconnection at Next ADB is received 3344 ** from the internal bus target. The bus returns to idle. 3345 ** �X When operating in the PCI-X mode, a disconnection at Next ADB is received from the 3346 ** internal bus target. The ATU IB initiator interface attempts to reacquire the bus to obtain 3347 ** remaining data. 3348 ** To support PCI Local Bus Specification, Revision 2.0 devices, the ATU can be programmed to 3349 ** ignore the memory read command (Memory Read, Memory Read Line, and Memory Read 3350 ** Multiple) when trying to match the current inbound read transaction with data in a DRC queue 3351 ** which was read previously (DRC on target bus). When the Read Command Alias Bit in the 3352 ** ATUCR register is set, the ATU does not distinguish the read commands on transactions. For 3353 ** example, the ATU enqueues a DRR with a Memory Read Multiple command and performs the read 3354 ** on the internal bus. Some time later, a PCI master attempts a Memory Read with the same address 3355 ** as the previous Memory Read Multiple. When the Read Command Bit is set, the ATU would return 3356 ** the read data from the DRC queue and consider the Delayed Read transaction complete. When the 3357 ** Read Command bit in the ATUCR was clear, the ATU would not return data since the PCI read 3358 ** commands did not match, only the address. 3359 ************************************************************************** 3360 */ 3361 /* 3362 ************************************************************************** 3363 ** Inbound Write Transaction 3364 **======================================================================== 3365 ** An inbound write transaction is initiated by a PCI master and is targeted at either 80331 local 3366 ** memory or a 80331 memory-mapped register. 3367 ** Data flow for an inbound write transaction on the PCI bus is summarized as: 3368 ** �E The ATU claims the PCI write transaction when the PCI address is within the inbound 3369 ** translation window defined by the ATU Inbound Base Address Register (and Inbound Upper 3370 ** Base Address Register during DACs) and Inbound Limit Register. 3371 ** �E When the IWADQ has at least one address entry available and the IWQ has at least one buffer 3372 ** available, the address is captured and the first data phase is accepted. 3373 ** �E The PCI interface continues to accept write data until one of the following is true: 3374 ** �X The initiator performs a disconnect. 3375 ** �X The transaction crosses a buffer boundary. 3376 ** �E When an address parity error is detected during the address phase of the transaction, the 3377 ** address parity error mechanisms are used. Refer to Section 3.7.1 for details of the address 3378 ** parity error response. 3379 ** �E When operating in the PCI-X mode when an attribute parity error is detected, the attribute 3380 ** parity error mechanism described in Section 3.7.1 is used. 3381 ** �E When a data parity error is detected while accepting data, the slave interface sets the 3382 ** appropriate bits based on PCI specifications. No other action is taken. Refer to Section 3.7.2.6 3383 ** for details of the inbound write data parity error response. 3384 ** Once the PCI interface places a PCI address in the IWADQ, when IWQ has received data sufficient 3385 ** to cross a buffer boundary or the master disconnects on the PCI bus, the ATUs internal bus 3386 ** interface becomes aware of the inbound write. When there are additional write transactions ahead 3387 ** in the IWQ/IWADQ, the current transaction remains posted until ordering and priority have been 3388 ** satisfied (Refer to Section 3.5.3) and the transaction is attempted on the internal bus by the ATU 3389 ** internal master interface. The ATU does not insert target wait states nor do data merging on the PCI 3390 ** interface, when operating in the PCI mode. 3391 ** In the PCI-X mode memory writes are always executed as immediate transactions, while 3392 ** configuration write transactions are processed as split transactions. The ATU generates a Split 3393 ** Completion Message, (with Message class=0h - Write Completion Class and Message index = 3394 ** 00h - Write Completion Message) once a configuration write is successfully executed. 3395 ** Also, when operating in the PCI-X mode a write sequence may contain multiple write transactions. 3396 ** The ATU handles such transactions as independent transactions. 3397 ** Data flow for the inbound write transaction on the internal bus is summarized as: 3398 ** �E The ATU internal bus master requests the internal bus when IWADQ has at least one entry 3399 ** with associated data in the IWQ. 3400 ** �E When the internal bus is granted, the internal bus master interface initiates the write 3401 ** transaction by driving the translated address onto the internal bus. For details on inbound 3402 ** address translation. 3403 ** �E When IB_DEVSEL# is not returned, a master abort condition is signaled on the internal bus. 3404 ** The current transaction is flushed from the queue and SERR# may be asserted on the PCI 3405 ** interface. 3406 ** �E The ATU initiator interface asserts IB_REQ64# to attempt a 64-bit transfer. When 3407 ** IB_ACK64# is not returned, a 32-bit transfer is used. Transfers of less than 64-bits use the 3408 ** IB_C/BE[7:0]# to mask the bytes not written in the 64-bit data phase. Write data is transferred 3409 ** from the IWQ to the internal bus when data is available and the internal bus interface retains 3410 ** internal bus ownership. 3411 ** �E The internal bus interface stops transferring data from the current transaction to the internal 3412 ** bus when one of the following conditions becomes true: 3413 ** �X The internal bus initiator interface loses bus ownership. The ATU internal initiator 3414 ** terminates the transfer (initiator disconnection) at the next ADB (for the internal bus ADB 3415 ** is defined as a naturally aligned 128-byte boundary) and attempt to reacquire the bus to 3416 ** complete the delivery of remaining data using the same sequence ID but with the 3417 ** modified starting address and byte count. 3418 ** �X A Disconnect at Next ADB is signaled on the internal bus from the internal target. When 3419 ** the transaction in the IWQ completes at that ADB, the initiator returns to idle. When the 3420 ** transaction in the IWQ is not complete, the initiator attempts to reacquire the bus to 3421 ** complete the delivery of remaining data using the same sequence ID but with the 3422 ** modified starting address and byte count. 3423 ** �X A Single Data Phase Disconnect is signaled on the internal bus from the internal target. 3424 ** When the transaction in the IWQ needs only a single data phase, the master returns to idle. 3425 ** When the transaction in the IWQ is not complete, the initiator attempts to reacquire the 3426 ** bus to complete the delivery of remaining data using the same sequence ID but with the 3427 ** modified starting address and byte count. 3428 ** �X The data from the current transaction has completed (satisfaction of byte count). An 3429 ** initiator termination is performed and the bus returns to idle. 3430 ** �X A Master Abort is signaled on the internal bus. SERR# may be asserted on the PCI bus. 3431 ** Data is flushed from the IWQ. 3432 ***************************************************************** 3433 */ 3434 3435 3436 3437 /* 3438 ************************************************************************** 3439 ** Inbound Read Completions Data Parity Errors 3440 **======================================================================== 3441 ** As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode. 3442 ** When as the completer of a Split Read Request the ATU observes PERR# assertion during the split 3443 ** completion transaction, the ATU attempts to complete the transaction normally and no further 3444 ** action is taken. 3445 ************************************************************************** 3446 */ 3447 3448 /* 3449 ************************************************************************** 3450 ** Inbound Configuration Write Completion Message Data Parity Errors 3451 **======================================================================== 3452 ** As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode. 3453 ** When as the completer of a Configuration (Split) Write Request the ATU observes PERR# 3454 ** assertion during the split completion transaction, the ATU attempts to complete the transaction 3455 ** normally and no further action is taken. 3456 ************************************************************************** 3457 */ 3458 3459 /* 3460 ************************************************************************** 3461 ** Inbound Read Request Data Parity Errors 3462 **===================== Immediate Data Transfer ========================== 3463 ** As a target, the ATU may encounter this error when operating in the Conventional PCI or PCI-X modes. 3464 ** Inbound read data parity errors occur when read data delivered from the IRQ is detected as having 3465 ** bad parity by the initiator of the transaction who is receiving the data. The initiator may optionally 3466 ** report the error to the system by asserting PERR#. As a target device in this scenario, no action is 3467 ** required and no error bits are set. 3468 **=====================Split Response Termination========================= 3469 ** As a target, the ATU may encounter this error when operating in the PCI-X mode. 3470 ** Inbound read data parity errors occur during the Split Response Termination. The initiator may 3471 ** optionally report the error to the system by asserting PERR#. As a target device in this scenario, no 3472 ** action is required and no error bits are set. 3473 ************************************************************************** 3474 */ 3475 3476 /* 3477 ************************************************************************** 3478 ** Inbound Write Request Data Parity Errors 3479 **======================================================================== 3480 ** As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes. 3481 ** Data parity errors occurring during write operations received by the ATU may assert PERR# on 3482 ** the PCI Bus. When an error occurs, the ATU continues accepting data until the initiator of the write 3483 ** transaction completes or a queue fill condition is reached. Specifically, the following actions with 3484 ** the given constraints are taken by the ATU: 3485 ** �E PERR# is asserted two clocks cycles (three clock cycles when operating in the PCI-X mode) 3486 ** following the data phase in which the data parity error is detected on the bus. This is only 3487 ** done when the Parity Error Response bit in the ATUCMD is set. 3488 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 3489 ** actions is taken: 3490 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 3491 ** Detected Parity Error bit in the ATUISR. When set, no action. 3492 *************************************************************************** 3493 */ 3494 3495 3496 /* 3497 *************************************************************************** 3498 ** Inbound Configuration Write Request 3499 ** ===================================================================== 3500 ** As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes. 3501 ** =============================================== 3502 ** Conventional PCI Mode 3503 ** =============================================== 3504 ** To allow for correct data parity calculations for delayed write transactions, the ATU delays the 3505 ** assertion of STOP# (signalling a Retry) until PAR is driven by the master. A parity error during a 3506 ** delayed write transaction (inbound configuration write cycle) can occur in any of the following 3507 ** parts of the transactions: 3508 ** �E During the initial Delayed Write Request cycle on the PCI bus when the ATU latches the 3509 ** address/command and data for delayed delivery to the internal configuration register. 3510 ** �E During the Delayed Write Completion cycle on the PCI bus when the ATU delivers the status 3511 ** of the operation back to the original master. 3512 ** The 80331 ATU PCI interface has the following responses to a delayed write parity error for 3513 ** inbound transactions during Delayed Write Request cycles with the given constraints: 3514 ** �E When the Parity Error Response bit in the ATUCMD is set, the ATU asserts TRDY# 3515 ** (disconnects with data) and two clock cycles later asserts PERR# notifying the initiator of the 3516 ** parity error. The delayed write cycle is not enqueued and forwarded to the internal bus. 3517 ** When the Parity Error Response bit in the ATUCMD is cleared, the ATU retries the 3518 ** transaction by asserting STOP# and enqueues the Delayed Write Request cycle to be 3519 ** forwarded to the internal bus. PERR# is not asserted. 3520 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 3521 ** actions is taken: 3522 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 3523 ** Detected Parity Error bit in the ATUISR. When set, no action. 3524 ** For the original write transaction to be completed, the initiator retries the transaction on the PCI 3525 ** bus and the ATU returns the status from the internal bus, completing the transaction. 3526 ** For the Delayed Write Completion transaction on the PCI bus where a data parity error occurs and 3527 ** therefore does not agree with the status being returned from the internal bus (i.e. status being 3528 ** returned is normal completion) the ATU performs the following actions with the given constraints: 3529 ** �E When the Parity Error Response Bit is set in the ATUCMD, the ATU asserts TRDY# 3530 ** (disconnects with data) and two clocks later asserts PERR#. The Delayed Completion cycle in 3531 ** the IDWQ remains since the data of retried command did not match the data within the queue. 3532 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 3533 ** actions is taken: 3534 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 3535 ** Detected Parity Error bit in the ATUISR. When set, no action. 3536 ** =================================================== 3537 ** PCI-X Mode 3538 ** =================================================== 3539 ** Data parity errors occurring during configuration write operations received by the ATU may cause 3540 ** PERR# assertion and delivery of a Split Completion Error Message on the PCI Bus. When an error 3541 ** occurs, the ATU accepts the write data and complete with a Split Response Termination. 3542 ** Specifically, the following actions with the given constraints are then taken by the ATU: 3543 ** �E When the Parity Error Response bit in the ATUCMD is set, PERR# is asserted three clocks 3544 ** cycles following the Split Response Termination in which the data parity error is detected on 3545 ** the bus. When the ATU asserts PERR#, additional actions is taken: 3546 ** �X A Split Write Data Parity Error message (with message class=2h - completer error and 3547 ** message index=01h - Split Write Data Parity Error) is initiated by the ATU on the PCI bus 3548 ** that addresses the requester of the configuration write. 3549 ** �X When the Initiated Split Completion Error Message Interrupt Mask in the ATUIMR is 3550 ** clear, set the Initiated Split Completion Error Message bit in the ATUISR. When set, no 3551 ** action. 3552 ** �X The Split Write Request is not enqueued and forwarded to the internal bus. 3553 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 3554 ** actions is taken: 3555 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 3556 ** Detected Parity Error bit in the ATUISR. When set, no action. 3557 ** 3558 *************************************************************************** 3559 */ 3560 3561 /* 3562 *************************************************************************** 3563 ** Split Completion Messages 3564 ** ======================================================================= 3565 ** As a target, the ATU may encounter this error when operating in the PCI-X mode. 3566 ** Data parity errors occurring during Split Completion Messages claimed by the ATU may assert 3567 ** PERR# (when enabled) or SERR# (when enabled) on the PCI Bus. When an error occurs, the 3568 ** ATU accepts the data and complete normally. Specifically, the following actions with the given 3569 ** constraints are taken by the ATU: 3570 ** �E PERR# is asserted three clocks cycles following the data phase in which the data parity error 3571 ** is detected on the bus. This is only done when the Parity Error Response bit in the ATUCMD 3572 ** is set. When the ATU asserts PERR#, additional actions is taken: 3573 ** �X The Master Parity Error bit in the ATUSR is set. 3574 ** �X When the ATU PCI Master Parity Error Interrupt Mask Bit in the ATUIMR is clear, set the 3575 ** PCI Master Parity Error bit in the ATUISR. When set, no action. 3576 ** �X When the SERR# Enable bit in the ATUCMD is set, and the Data Parity Error Recover 3577 ** Enable bit in the PCIXCMD register is clear, assert SERR#; otherwise no action is taken. 3578 ** When the ATU asserts SERR#, additional actions is taken: 3579 ** Set the SERR# Asserted bit in the ATUSR. 3580 ** When the ATU SERR# Asserted Interrupt Mask Bit in the ATUIMR is clear, set the 3581 ** SERR# Asserted bit in the ATUISR. When set, no action. 3582 ** When the ATU SERR# Detected Interrupt Enable Bit in the ATUCR is set, set the 3583 ** SERR# Detected bit in the ATUISR. When clear, no action. 3584 ** �E When the SCE bit (Split Completion Error -- bit 30 of the Completer Attributes) is set during 3585 ** the Attribute phase, the Received Split Completion Error Message bit in the PCIXSR is set. 3586 ** When the ATU sets this bit, additional actions is taken: 3587 ** �X When the ATU Received Split Completion Error Message Interrupt Mask bit in the 3588 ** ATUIMR is clear, set the Received Split Completion Error Message bit in the ATUISR. 3589 ** When set, no action. 3590 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 3591 ** actions is taken: 3592 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 3593 ** Detected Parity Error bit in the ATUISR. When set, no action. 3594 ** �E The transaction associated with the Split Completion Message is discarded. 3595 ** �E When the discarded transaction was a read, a completion error message (with message 3596 ** class=2h - completer error and message index=82h - PCI bus read parity error) is generated on 3597 ** the internal bus of the 80331. 3598 ***************************************************************************** 3599 */ 3600 3601 3602 /* 3603 ****************************************************************************************************** 3604 ** Messaging Unit (MU) of the Intel R 80331 I/O processor (80331) 3605 ** ================================================================================================== 3606 ** The Messaging Unit (MU) transfers data between the PCI system and the 80331 3607 ** notifies the respective system when new data arrives. 3608 ** The PCI window for messaging transactions is always the first 4 Kbytes of the inbound translation. 3609 ** window defined by: 3610 ** 1.Inbound ATU Base Address Register 0 (IABAR0) 3611 ** 2.Inbound ATU Limit Register 0 (IALR0) 3612 ** All of the Messaging Unit errors are reported in the same manner as ATU errors. 3613 ** Error conditions and status can be found in : 3614 ** 1.ATUSR 3615 ** 2.ATUISR 3616 **==================================================================================================== 3617 ** Mechanism Quantity Assert PCI Interrupt Signals Generate I/O Processor Interrupt 3618 **---------------------------------------------------------------------------------------------------- 3619 ** Message Registers 2 Inbound Optional Optional 3620 ** 2 Outbound 3621 **---------------------------------------------------------------------------------------------------- 3622 ** Doorbell Registers 1 Inbound Optional Optional 3623 ** 1 Outbound 3624 **---------------------------------------------------------------------------------------------------- 3625 ** Circular Queues 4 Circular Queues Under certain conditions Under certain conditions 3626 **---------------------------------------------------------------------------------------------------- 3627 ** Index Registers 1004 32-bit Memory Locations No Optional 3628 **==================================================================================================== 3629 ** PCI Memory Map: First 4 Kbytes of the ATU Inbound PCI Address Space 3630 **==================================================================================================== 3631 ** 0000H Reserved 3632 ** 0004H Reserved 3633 ** 0008H Reserved 3634 ** 000CH Reserved 3635 **------------------------------------------------------------------------ 3636 ** 0010H Inbound Message Register 0 ] 3637 ** 0014H Inbound Message Register 1 ] 3638 ** 0018H Outbound Message Register 0 ] 3639 ** 001CH Outbound Message Register 1 ] 4 Message Registers 3640 **------------------------------------------------------------------------ 3641 ** 0020H Inbound Doorbell Register ] 3642 ** 0024H Inbound Interrupt Status Register ] 3643 ** 0028H Inbound Interrupt Mask Register ] 3644 ** 002CH Outbound Doorbell Register ] 3645 ** 0030H Outbound Interrupt Status Register ] 3646 ** 0034H Outbound Interrupt Mask Register ] 2 Doorbell Registers and 4 Interrupt Registers 3647 **------------------------------------------------------------------------ 3648 ** 0038H Reserved 3649 ** 003CH Reserved 3650 **------------------------------------------------------------------------ 3651 ** 0040H Inbound Queue Port ] 3652 ** 0044H Outbound Queue Port ] 2 Queue Ports 3653 **------------------------------------------------------------------------ 3654 ** 0048H Reserved 3655 ** 004CH Reserved 3656 **------------------------------------------------------------------------ 3657 ** 0050H ] 3658 ** : ] 3659 ** : Intel Xscale Microarchitecture Local Memory ] 3660 ** : ] 3661 ** 0FFCH ] 1004 Index Registers 3662 ******************************************************************************* 3663 */ 3664 struct _MU 3665 { 3666 ULONG resrved0[4]; /*0000 000F*/ 3667 ULONG inbound_msgaddr0; /*0010 0013*/ 3668 ULONG inbound_msgaddr1; /*0014 0017*/ 3669 ULONG outbound_msgaddr0; /*0018 001B*/ 3670 ULONG outbound_msgaddr1; /*001C 001F*/ 3671 ULONG inbound_doorbell; /*0020 0023*/ 3672 ULONG inbound_intstatus; /*0024 0027*/ 3673 ULONG inbound_intmask; /*0028 002B*/ 3674 ULONG outbound_doorbell; /*002C 002F*/ 3675 ULONG outbound_intstatus; /*0030 0033*/ 3676 ULONG outbound_intmask; /*0034 0037*/ 3677 ULONG reserved1[2]; /*0038 003F*/ 3678 ULONG inbound_queueport; /*0040 0043*/ 3679 ULONG outbound_queueport; /*0044 0047*/ 3680 ULONG reserved2[2]; /*0048 004F*/ 3681 ULONG reserved3[492]; /*0050 07FF ......local_buffer 492*/ 3682 ULONG message_rbuffer[128]; /*0800 09FF 128*/ 3683 ULONG message_wbuffer[256]; /*0a00 0DFF 256*/ 3684 ULONG ioctl_wbuffer[32]; /*0E00 0E7F 32*/ 3685 ULONG reserved4[32]; /*0E80 0EFF 32*/ 3686 ULONG ioctl_rbuffer[32]; /*0F00 0F7F 32*/ 3687 ULONG reserved5[32]; /*0F80 0FFF 32*/ 3688 }; 3689 /* 3690 ***************************************************************************** 3691 ** Theory of MU Operation 3692 ***************************************************************************** 3693 **-------------------- 3694 ** inbound_msgaddr0: 3695 ** inbound_msgaddr1: 3696 ** outbound_msgaddr0: 3697 ** outbound_msgaddr1: 3698 ** . The MU has four independent messaging mechanisms. 3699 ** There are four Message Registers that are similar to a combination of mailbox and doorbell registers. 3700 ** Each holds a 32-bit value and generates an interrupt when written. 3701 **-------------------- 3702 ** inbound_doorbell: 3703 ** outbound_doorbell: 3704 ** . The two Doorbell Registers support software interrupts. 3705 ** When a bit is set in a Doorbell Register, an interrupt is generated. 3706 **-------------------- 3707 ** inbound_queueport: 3708 ** outbound_queueport: 3709 ** 3710 ** 3711 ** . The Circular Queues support a message passing scheme that uses 4 circular queues. 3712 ** The 4 circular queues are implemented in 80331 local memory. 3713 ** Two queues are used for inbound messages and two are used for outbound messages. 3714 ** Interrupts may be generated when the queue is written. 3715 **-------------------- 3716 ** local_buffer 0x0050 ....0x0FFF 3717 ** . The Index Registers use a portion of the 80331 local memory to implement a large set of message registers. 3718 ** When one of the Index Registers is written, an interrupt is generated and the address of the register written is captured. 3719 ** Interrupt status for all interrupts is recorded in the Inbound Interrupt Status Register and the Outbound Interrupt Status Register. 3720 ** Each interrupt generated by the Messaging Unit can be masked. 3721 **-------------------- 3722 ** . Multi-DWORD PCI burst accesses are not supported by the Messaging Unit, 3723 ** with the exception of Multi-DWORD reads to the index registers. 3724 ** In Conventional mode: the MU terminates Multi-DWORD PCI transactions (other than index register reads) with a disconnect at the next Qword boundary, with the exception of queue ports. 3725 ** In PCI-X mode : the MU terminates a Multi-DWORD PCI read transaction with a Split Response and the data is returned through split completion transaction(s). 3726 ** however, when the burst request crosses into or through the range of offsets 40h to 4Ch (e.g., this includes the queue ports) the transaction is signaled target-abort immediately on the PCI bus. 3727 ** In PCI-X mode, Multi-DWORD PCI writes is signaled a Single-Data-Phase Disconnect which means that no data beyond the first Qword (Dword when the MU does not assert P_ACK64#) is written. 3728 **-------------------- 3729 ** . All registers needed to configure and control the Messaging Unit are memory-mapped registers. 3730 ** The MU uses the first 4 Kbytes of the inbound translation window in the Address Translation Unit (ATU). 3731 ** This PCI address window is used for PCI transactions that access the 80331 local memory. 3732 ** The PCI address of the inbound translation window is contained in the Inbound ATU Base Address Register. 3733 **-------------------- 3734 ** . From the PCI perspective, the Messaging Unit is part of the Address Translation Unit. 3735 ** The Messaging Unit uses the PCI configuration registers of the ATU for control and status information. 3736 ** The Messaging Unit must observe all PCI control bits in the ATU Command Register and ATU Configuration Register. 3737 ** The Messaging Unit reports all PCI errors in the ATU Status Register. 3738 **-------------------- 3739 ** . Parts of the Messaging Unit can be accessed as a 64-bit PCI device. 3740 ** The register interface, message registers, doorbell registers, and index registers returns a P_ACK64# in response to a P_REQ64# on the PCI interface. 3741 ** Up to 1 Qword of data can be read or written per transaction (except Index Register reads). 3742 ** The Inbound and Outbound Queue Ports are always 32-bit addresses and the MU does not assert P_ACK64# to offsets 40H and 44H. 3743 ************************************************************************** 3744 */ 3745 /* 3746 ************************************************************************** 3747 ** Message Registers 3748 ** ============================== 3749 ** . Messages can be sent and received by the 80331 through the use of the Message Registers. 3750 ** . When written, the message registers may cause an interrupt to be generated to either the Intel XScale core or the host processor. 3751 ** . Inbound messages are sent by the host processor and received by the 80331. 3752 ** Outbound messages are sent by the 80331 and received by the host processor. 3753 ** . The interrupt status for outbound messages is recorded in the Outbound Interrupt Status Register. 3754 ** Interrupt status for inbound messages is recorded in the Inbound Interrupt Status Register. 3755 ** 3756 ** Inbound Messages: 3757 ** ----------------- 3758 ** . When an inbound message register is written by an external PCI agent, an interrupt may be generated to the Intel XScale core. 3759 ** . The interrupt may be masked by the mask bits in the Inbound Interrupt Mask Register. 3760 ** . The Intel XScale core interrupt is recorded in the Inbound Interrupt Status Register. 3761 ** The interrupt causes the Inbound Message Interrupt bit to be set in the Inbound Interrupt Status Register. 3762 ** This is a Read/Clear bit that is set by the MU hardware and cleared by software. 3763 ** The interrupt is cleared when the Intel XScale core writes a value of 1 to the Inbound Message Interrupt bit in the Inbound Interrupt Status Register. 3764 ** ------------------------------------------------------------------------ 3765 ** Inbound Message Register - IMRx 3766 ** 3767 ** . There are two Inbound Message Registers: IMR0 and IMR1. 3768 ** . When the IMR register is written, an interrupt to the Intel XScale core may be generated. 3769 ** The interrupt is recorded in the Inbound Interrupt Status Register and may be masked by the Inbound Message Interrupt Mask bit in the Inbound Interrupt Mask Register. 3770 ** ----------------------------------------------------------------- 3771 ** Bit Default Description 3772 ** 31:00 0000 0000H Inbound Message - This is a 32-bit message written by an external PCI agent. 3773 ** When written, an interrupt to the Intel XScale core may be generated. 3774 ************************************************************************** 3775 */ 3776 #define ARCMSR_MU_INBOUND_MESSAGE_REG0 0x10 /*dword 0x13,0x12,0x11,0x10*/ 3777 #define ARCMSR_MU_INBOUND_MESSAGE_REG1 0x14 /*dword 0x17,0x16,0x15,0x14*/ 3778 /* 3779 ************************************************************************** 3780 ** Outbound Message Register - OMRx 3781 ** -------------------------------- 3782 ** There are two Outbound Message Registers: OMR0 and OMR1. When the OMR register is 3783 ** written, a PCI interrupt may be generated. The interrupt is recorded in the Outbound Interrupt 3784 ** Status Register and may be masked by the Outbound Message Interrupt Mask bit in the Outbound 3785 ** Interrupt Mask Register. 3786 ** 3787 ** Bit Default Description 3788 ** 31:00 00000000H Outbound Message - This is 32-bit message written by the Intel XScale core. When written, an 3789 ** interrupt may be generated on the PCI Interrupt pin determined by the ATU Interrupt Pin Register. 3790 ************************************************************************** 3791 */ 3792 #define ARCMSR_MU_OUTBOUND_MESSAGE_REG0 0x18 /*dword 0x1B,0x1A,0x19,0x18*/ 3793 #define ARCMSR_MU_OUTBOUND_MESSAGE_REG1 0x1C /*dword 0x1F,0x1E,0x1D,0x1C*/ 3794 /* 3795 ************************************************************************** 3796 ** Doorbell Registers 3797 ** ============================== 3798 ** There are two Doorbell Registers: 3799 ** Inbound Doorbell Register 3800 ** Outbound Doorbell Register 3801 ** The Inbound Doorbell Register allows external PCI agents to generate interrupts to the Intel R XScale core. 3802 ** The Outbound Doorbell Register allows the Intel R XScale core to generate a PCI interrupt. 3803 ** Both Doorbell Registers may generate interrupts whenever a bit in the register is set. 3804 ** 3805 ** Inbound Doorbells: 3806 ** ------------------ 3807 ** . When the Inbound Doorbell Register is written by an external PCI agent, an interrupt may be generated to the Intel R XScale core. 3808 ** An interrupt is generated when any of the bits in the doorbell register is written to a value of 1. 3809 ** Writing a value of 0 to any bit does not change the value of that bit and does not cause an interrupt to be generated. 3810 ** . Once a bit is set in the Inbound Doorbell Register, it cannot be cleared by any external PCI agent. 3811 ** The interrupt is recorded in the Inbound Interrupt Status Register. 3812 ** . The interrupt may be masked by the Inbound Doorbell Interrupt mask bit in the Inbound Interrupt Mask Register. 3813 ** When the mask bit is set for a particular bit, no interrupt is generated for that bit. 3814 ** The Inbound Interrupt Mask Register affects only the generation of the normal messaging unit interrupt and not the values written to the Inbound Doorbell Register. 3815 ** One bit in the Inbound Doorbell Register is reserved for an Error Doorbell interrupt. 3816 ** . The interrupt is cleared when the Intel R XScale core writes a value of 1 to the bits in the Inbound Doorbell Register that are set. 3817 ** Writing a value of 0 to any bit does not change the value of that bit and does not clear the interrupt. 3818 ** ------------------------------------------------------------------------ 3819 ** Inbound Doorbell Register - IDR 3820 ** 3821 ** . The Inbound Doorbell Register (IDR) is used to generate interrupts to the Intel XScale core. 3822 ** . Bit 31 is reserved for generating an Error Doorbell interrupt. 3823 ** When bit 31 is set, an Error interrupt may be generated to the Intel XScale core. 3824 ** All other bits, when set, cause the Normal Messaging Unit interrupt line of the Intel XScale core to be asserted, 3825 ** when the interrupt is not masked by the Inbound Doorbell Interrupt Mask bit in the Inbound Interrupt Mask Register. 3826 ** The bits in the IDR register can only be set by an external PCI agent and can only be cleared by the Intel XScale core. 3827 ** ------------------------------------------------------------------------ 3828 ** Bit Default Description 3829 ** 31 0 2 Error Interrupt - Generate an Error Interrupt to the Intel XScale core. 3830 ** 30:00 00000000H Normal Interrupt - When any bit is set, generate a Normal interrupt to the Intel XScale core. 3831 ** When all bits are clear, do not generate a Normal Interrupt. 3832 ************************************************************************** 3833 */ 3834 #define ARCMSR_MU_INBOUND_DOORBELL_REG 0x20 /*dword 0x23,0x22,0x21,0x20*/ 3835 /* 3836 ************************************************************************** 3837 ** Inbound Interrupt Status Register - IISR 3838 ** 3839 ** . The Inbound Interrupt Status Register (IISR) contains hardware interrupt status. 3840 ** It records the status of Intel XScale core interrupts generated by the Message Registers, Doorbell Registers, and the Circular Queues. 3841 ** All interrupts are routed to the Normal Messaging Unit interrupt input of the Intel XScale core, 3842 ** except for the Error Doorbell Interrupt and the Outbound Free Queue Full interrupt; 3843 ** these two are routed to the Messaging Unit Error interrupt input. 3844 ** The generation of interrupts recorded in the Inbound Interrupt Status Register may be masked by setting the corresponding bit in the Inbound Interrupt Mask Register. 3845 ** Some of the bits in this register are Read Only. 3846 ** For those bits, the interrupt must be cleared through another register. 3847 ** 3848 ** Bit Default Description 3849 ** 31:07 0000000H 0 2 Reserved 3850 ** 06 0 2 Index Register Interrupt - This bit is set by the MU hardware when an Index Register has been written after a PCI transaction. 3851 ** 05 0 2 Outbound Free Queue Full Interrupt - This bit is set when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full. 3852 ** An Error interrupt is generated for this condition. 3853 ** 04 0 2 Inbound Post Queue Interrupt - This bit is set by the MU hardware when the Inbound Post Queue has been written. 3854 ** Once cleared, an interrupt does NOT be generated when the head and tail pointers remain unequal (i.e. queue status is Not Empty). 3855 ** Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared, 3856 ** software must retain the information that the Inbound Post queue status is not empty. 3857 ** NOTE: 3858 ** This interrupt is provided with dedicated support in the 80331 Interrupt Controller. 3859 ** 03 0 2 Error Doorbell Interrupt - This bit is set when the Error Interrupt of the Inbound Doorbell Register is set. 3860 ** To clear this bit (and the interrupt), the Error Interrupt bit of the Inbound Doorbell Register must be clear. 3861 ** 02 0 2 Inbound Doorbell Interrupt - This bit is set when at least one Normal Interrupt bit in the Inbound Doorbell Register is set. 3862 ** To clear this bit (and the interrupt), the Normal Interrupt bits in the Inbound Doorbell Register must all be clear. 3863 ** 01 0 2 Inbound Message 1 Interrupt - This bit is set by the MU hardware when the Inbound Message 1 Register has been written. 3864 ** 00 0 2 Inbound Message 0 Interrupt - This bit is set by the MU hardware when the Inbound Message 0 Register has been written. 3865 ************************************************************************** 3866 */ 3867 #define ARCMSR_MU_INBOUND_INTERRUPT_STATUS_REG 0x24 /*dword 0x27,0x26,0x25,0x24*/ 3868 #define ARCMSR_MU_INBOUND_INDEX_INT 0x40 3869 #define ARCMSR_MU_INBOUND_QUEUEFULL_INT 0x20 3870 #define ARCMSR_MU_INBOUND_POSTQUEUE_INT 0x10 3871 #define ARCMSR_MU_INBOUND_ERROR_DOORBELL_INT 0x08 3872 #define ARCMSR_MU_INBOUND_DOORBELL_INT 0x04 3873 #define ARCMSR_MU_INBOUND_MESSAGE1_INT 0x02 3874 #define ARCMSR_MU_INBOUND_MESSAGE0_INT 0x01 3875 /* 3876 ************************************************************************** 3877 ** Inbound Interrupt Mask Register - IIMR 3878 ** 3879 ** . The Inbound Interrupt Mask Register (IIMR) provides the ability to mask Intel XScale core interrupts generated by the Messaging Unit. 3880 ** Each bit in the Mask register corresponds to an interrupt bit in the Inbound Interrupt Status Register. 3881 ** Setting or clearing bits in this register does not affect the Inbound Interrupt Status Register. 3882 ** They only affect the generation of the Intel XScale core interrupt. 3883 ** ------------------------------------------------------------------------ 3884 ** Bit Default Description 3885 ** 31:07 000000H 0 2 Reserved 3886 ** 06 0 2 Index Register Interrupt Mask - When set, this bit masks the interrupt generated by the MU hardware when an Index Register has been written after a PCI transaction. 3887 ** 05 0 2 Outbound Free Queue Full Interrupt Mask - When set, this bit masks the Error interrupt generated when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full. 3888 ** 04 0 2 Inbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated by the MU hardware when the Inbound Post Queue has been written. 3889 ** 03 0 2 Error Doorbell Interrupt Mask - When set, this bit masks the Error Interrupt when the Error Interrupt bit of the Inbound Doorbell Register is set. 3890 ** 02 0 2 Inbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated when at least one Normal Interrupt bit in the Inbound Doorbell Register is set. 3891 ** 01 0 2 Inbound Message 1 Interrupt Mask - When set, this bit masks the Inbound Message 1 Interrupt generated by a write to the Inbound Message 1 Register. 3892 ** 00 0 2 Inbound Message 0 Interrupt Mask - When set, this bit masks the Inbound Message 0 Interrupt generated by a write to the Inbound Message 0 Register. 3893 ************************************************************************** 3894 */ 3895 #define ARCMSR_MU_INBOUND_INTERRUPT_MASK_REG 0x28 /*dword 0x2B,0x2A,0x29,0x28*/ 3896 #define ARCMSR_MU_INBOUND_INDEX_INTMASKENABLE 0x40 3897 #define ARCMSR_MU_INBOUND_QUEUEFULL_INTMASKENABLE 0x20 3898 #define ARCMSR_MU_INBOUND_POSTQUEUE_INTMASKENABLE 0x10 3899 #define ARCMSR_MU_INBOUND_DOORBELL_ERROR_INTMASKENABLE 0x08 3900 #define ARCMSR_MU_INBOUND_DOORBELL_INTMASKENABLE 0x04 3901 #define ARCMSR_MU_INBOUND_MESSAGE1_INTMASKENABLE 0x02 3902 #define ARCMSR_MU_INBOUND_MESSAGE0_INTMASKENABLE 0x01 3903 /* 3904 ************************************************************************** 3905 ** Outbound Doorbell Register - ODR 3906 ** 3907 ** The Outbound Doorbell Register (ODR) allows software interrupt generation. It allows the Intel 3908 ** XScale core to generate PCI interrupts to the host processor by writing to this register. The 3909 ** generation of PCI interrupts through the Outbound Doorbell Register may be masked by setting the 3910 ** Outbound Doorbell Interrupt Mask bit in the Outbound Interrupt Mask Register. 3911 ** The Software Interrupt bits in this register can only be set by the Intel XScale core and can only 3912 ** be cleared by an external PCI agent. 3913 ** ---------------------------------------------------------------------- 3914 ** Bit Default Description 3915 ** 31 0 2 Reserved 3916 ** 30 0 2 Reserved. 3917 ** 29 0 2 Reserved 3918 ** 28 0000 0000H PCI Interrupt - When set, this bit causes the P_INTC# interrupt output (P_INTA# with BRG_EN and ARB_EN straps low) 3919 ** signal to be asserted or a Message-signaled Interrupt is generated (when enabled). 3920 ** When this bit is cleared, the P_INTC# interrupt output (P_INTA# with BRG_EN and ARB_EN straps low) 3921 ** signal is deasserted. 3922 ** 27:00 000 0000H Software Interrupts - When any bit is set the P_INTC# interrupt output (P_INTA# with BRG_EN and ARB_EN straps low) 3923 ** signal is asserted or a Message-signaled Interrupt is generated (when enabled). 3924 ** When all bits are cleared, the P_INTC# interrupt output (P_INTA# with BRG_EN and ARB_EN straps low) 3925 ** signal is deasserted. 3926 ************************************************************************** 3927 */ 3928 #define ARCMSR_MU_OUTBOUND_DOORBELL_REG 0x2C /*dword 0x2F,0x2E,0x2D,0x2C*/ 3929 /* 3930 ************************************************************************** 3931 ** Outbound Interrupt Status Register - OISR 3932 ** 3933 ** The Outbound Interrupt Status Register (OISR) contains hardware interrupt status. It records the 3934 ** status of PCI interrupts generated by the Message Registers, Doorbell Registers, and the Circular 3935 ** Queues. The generation of PCI interrupts recorded in the Outbound Interrupt Status Register may 3936 ** be masked by setting the corresponding bit in the Outbound Interrupt Mask Register. Some of the 3937 ** bits in this register are Read Only. For those bits, the interrupt must be cleared through another 3938 ** register. 3939 ** ---------------------------------------------------------------------- 3940 ** Bit Default Description 3941 ** 31:05 000000H 000 2 Reserved 3942 ** 04 0 2 PCI Interrupt - This bit is set when the PCI Interrupt bit (bit 28) is set in the Outbound Doorbell Register. 3943 ** To clear this bit (and the interrupt), the PCI Interrupt bit must be cleared. 3944 ** 03 0 2 Outbound Post Queue Interrupt - This bit is set when data in the prefetch buffer is valid. This bit is 3945 ** cleared when any prefetch data has been read from the Outbound Queue Port. 3946 ** 02 0 2 Outbound Doorbell Interrupt - This bit is set when at least one Software Interrupt bit in the Outbound 3947 ** Doorbell Register is set. To clear this bit (and the interrupt), the Software Interrupt bits in the Outbound 3948 ** Doorbell Register must all be clear. 3949 ** 01 0 2 Outbound Message 1 Interrupt - This bit is set by the MU when the Outbound Message 1 Register is 3950 ** written. Clearing this bit clears the interrupt. 3951 ** 00 0 2 Outbound Message 0 Interrupt - This bit is set by the MU when the Outbound Message 0 Register is 3952 ** written. Clearing this bit clears the interrupt. 3953 ************************************************************************** 3954 */ 3955 #define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30 /*dword 0x33,0x32,0x31,0x30*/ 3956 #define ARCMSR_MU_OUTBOUND_PCI_INT 0x10 3957 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08 3958 #define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04 3959 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02 3960 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01 3961 /* 3962 ************************************************************************** 3963 ** Outbound Interrupt Mask Register - OIMR 3964 ** The Outbound Interrupt Mask Register (OIMR) provides the ability to mask outbound PCI 3965 ** interrupts generated by the Messaging Unit. Each bit in the mask register corresponds to a 3966 ** hardware interrupt bit in the Outbound Interrupt Status Register. When the bit is set, the PCI 3967 ** interrupt is not generated. When the bit is clear, the interrupt is allowed to be generated. 3968 ** Setting or clearing bits in this register does not affect the Outbound Interrupt Status Register. They 3969 ** only affect the generation of the PCI interrupt. 3970 ** ---------------------------------------------------------------------- 3971 ** Bit Default Description 3972 ** 31:05 000000H Reserved 3973 ** 04 0 2 PCI Interrupt Mask - When set, this bit masks the interrupt generation when the PCI Interrupt bit (bit 28) 3974 ** in the Outbound Doorbell Register is set. 3975 ** 03 0 2 Outbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated when data in 3976 ** the prefetch buffer is valid. 3977 ** 02 0 2 Outbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated by the Outbound 3978 ** Doorbell Register. 3979 ** 01 0 2 Outbound Message 1 Interrupt Mask - When set, this bit masks the Outbound Message 1 Interrupt 3980 ** generated by a write to the Outbound Message 1 Register. 3981 ** 00 0 2 Outbound Message 0 Interrupt Mask- When set, this bit masks the Outbound Message 0 Interrupt 3982 ** generated by a write to the Outbound Message 0 Register. 3983 ************************************************************************** 3984 */ 3985 #define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34 /*dword 0x37,0x36,0x35,0x34*/ 3986 #define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10 3987 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08 3988 #define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04 3989 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02 3990 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01 3991 #define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F 3992 /* 3993 ************************************************************************** 3994 ** 3995 ************************************************************************** 3996 */ 3997 #define ARCMSR_MU_INBOUND_QUEUE_PORT_REG 0x40 /*dword 0x43,0x42,0x41,0x40*/ 3998 #define ARCMSR_MU_OUTBOUND_QUEUE_PORT_REG 0x44 /*dword 0x47,0x46,0x45,0x44*/ 3999 /* 4000 ************************************************************************** 4001 ** Circular Queues 4002 ** ====================================================================== 4003 ** The MU implements four circular queues. There are 2 inbound queues and 2 outbound queues. In 4004 ** this case, inbound and outbound refer to the direction of the flow of posted messages. 4005 ** Inbound messages are either: 4006 ** �E posted messages by other processors for the Intel XScale core to process or 4007 ** �E free (or empty) messages that can be reused by other processors. 4008 ** Outbound messages are either: 4009 ** �E posted messages by the Intel XScale core for other processors to process or 4010 ** �E free (or empty) messages that can be reused by the Intel XScale core. 4011 ** Therefore, free inbound messages flow away from the 80331 and free outbound messages flow toward the 80331. 4012 ** The four Circular Queues are used to pass messages in the following manner. 4013 ** . The two inbound queues are used to handle inbound messages 4014 ** and the two outbound queues are used to handle outbound messages. 4015 ** . One of the inbound queues is designated the Free queue and it contains inbound free messages. 4016 ** The other inbound queue is designated the Post queue and it contains inbound posted messages. 4017 ** Similarly, one of the outbound queues is designated the Free queue and the other outbound queue is designated the Post queue. 4018 ** 4019 ** ============================================================================================================= 4020 ** Circular Queue Summary 4021 ** _____________________________________________________________________________________________________________ 4022 ** | Queue Name | Purpose | Action on PCI Interface| 4023 ** |______________________|____________________________________________________________|_________________________| 4024 ** |Inbound Post Queue | Queue for inbound messages from other processors | Written | 4025 ** | | waiting to be processed by the 80331 | | 4026 ** |Inbound Free Queue | Queue for empty inbound messages from the 80331 | Read | 4027 ** | | available for use by other processors | | 4028 ** |Outbound Post Queue | Queue for outbound messages from the 80331 | Read | 4029 ** | | that are being posted to the other processors | | 4030 ** |Outbound Free Queue | Queue for empty outbound messages from other processors | Written | 4031 ** | | available for use by the 80331 | | 4032 ** |______________________|____________________________________________________________|_________________________| 4033 ** 4034 ** . The two inbound queues allow the host processor to post inbound messages for the 80331 in one 4035 ** queue and to receive free messages returning from the 80331. 4036 ** The host processor posts inbound messages, 4037 ** the Intel XScale core receives the posted message and when it is finished with the message, 4038 ** places it back on the inbound free queue for reuse by the host processor. 4039 ** 4040 ** The circular queues are accessed by external PCI agents through two port locations in the PCI 4041 ** address space: 4042 ** Inbound Queue Port 4043 ** and Outbound Queue Port. 4044 ** The Inbound Queue Port is used by external PCI agents to read the Inbound Free Queue and write the Inbound Post Queue. 4045 ** The Outbound Queue Port is used by external PCI agents to read the Outbound Post Queue and write the Outbound Free Queue. 4046 ** Note that a PCI transaction to the inbound or outbound queue ports with null byte enables (P_C/BE[3:0]#=1111 2 ) 4047 ** does not cause the MU hardware to increment the queue pointers. 4048 ** This is treated as when the PCI transaction did not occur. 4049 ** The Inbound and Outbound Queue Ports never respond with P_ACK64# on the PCI interface. 4050 ** ====================================================================================== 4051 ** Overview of Circular Queue Operation 4052 ** ====================================================================================== 4053 ** . The data storage for the circular queues must be provided by the 80331 local memory. 4054 ** . The base address of the circular queues is contained in the Queue Base Address Register. 4055 ** Each entry in the queue is a 32-bit data value. 4056 ** . Each read from or write to the queue may access only one queue entry. 4057 ** . Multi-DWORD accesses to the circular queues are not allowed. 4058 ** Sub-DWORD accesses are promoted to DWORD accesses. 4059 ** . Each circular queue has a head pointer and a tail pointer. 4060 ** The pointers are offsets from the Queue Base Address. 4061 ** . Writes to a queue occur at the head of the queue and reads occur from the tail. 4062 ** The head and tail pointers are incremented by either the Intel XScale core or the Messaging Unit hardware. 4063 ** Which unit maintains the pointer is determined by the writer of the queue. 4064 ** More details about the pointers are given in the queue descriptions below. 4065 ** The pointers are incremented after the queue access. 4066 ** Both pointers wrap around to the first address of the circular queue when they reach the circular queue size. 4067 ** 4068 ** Messaging Unit... 4069 ** 4070 ** The Messaging Unit generates an interrupt to the Intel XScale core or generate a PCI interrupt under certain conditions. 4071 ** . In general, when a Post queue is written, an interrupt is generated to notify the receiver that a message was posted. 4072 ** The size of each circular queue can range from 4K entries (16 Kbytes) to 64K entries (256 Kbytes). 4073 ** . All four queues must be the same size and may be contiguous. 4074 ** Therefore, the total amount of local memory needed by the circular queues ranges from 64 Kbytes to 1 Mbytes. 4075 ** The Queue size is determined by the Queue Size field in the MU Configuration Register. 4076 ** . There is one base address for all four queues. 4077 ** It is stored in the Queue Base Address Register (QBAR). 4078 ** The starting addresses of each queue is based on the Queue Base Address and the Queue Size field. 4079 ** here shows an example of how the circular queues should be set up based on the 4080 ** Intelligent I/O (I 2 O) Architecture Specification. 4081 ** Other ordering of the circular queues is possible. 4082 ** 4083 ** Queue Starting Address 4084 ** Inbound Free Queue QBAR 4085 ** Inbound Post Queue QBAR + Queue Size 4086 ** Outbound Post Queue QBAR + 2 * Queue Size 4087 ** Outbound Free Queue QBAR + 3 * Queue Size 4088 ** =================================================================================== 4089 ** Inbound Post Queue 4090 ** ------------------ 4091 ** The Inbound Post Queue holds posted messages placed there by other processors for the Intel XScale core to process. 4092 ** This queue is read from the queue tail by the Intel XScale core. It is written to the queue head by external PCI agents. 4093 ** The tail pointer is maintained by the Intel XScale core. The head pointer is maintained by the MU hardware. 4094 ** For a PCI write transaction that accesses the Inbound Queue Port, the MU writes the data to the local memory location address in the Inbound Post Head Pointer Register. 4095 ** When the data written to the Inbound Queue Port is written to local memory, the MU hardware increments the Inbound Post Head Pointer Register. 4096 ** An Intel XScale core interrupt may be generated when the Inbound Post Queue is written. 4097 ** The Inbound Post Queue Interrupt bit in the Inbound Interrupt Status Register indicates the interrupt status. 4098 ** The interrupt is cleared when the Inbound Post Queue Interrupt bit is cleared. 4099 ** The interrupt can be masked by the Inbound Interrupt Mask Register. 4100 ** Software must be aware of the state of the Inbound Post Queue Interrupt Mask bit to guarantee that the full condition is recognized by the core processor. 4101 ** In addition, to guarantee that the queue does not get overwritten, software must process messages from the tail of the queue before incrementing the tail pointer and clearing this interrupt. 4102 ** Once cleared, an interrupt is NOT generated when the head and tail pointers remain unequal (i.e. queue status is Not Empty). 4103 ** Only a new message posting the in the inbound queue generates a new interrupt. 4104 ** Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared, software must retain the information that the Inbound Post queue status. 4105 ** From the time that the PCI write transaction is received until the data is written in local memory and the Inbound Post Head Pointer Register is incremented, any PCI transaction that attempts to access the Inbound Post Queue Port is signalled a Retry. 4106 ** The Intel XScale core may read messages from the Inbound Post Queue by reading the data from the local memory location pointed to by the Inbound Post Tail Pointer Register. 4107 ** The Intel XScale core must then increment the Inbound Post Tail Pointer Register. 4108 ** When the Inbound Post Queue is full (head and tail pointers are equal and the head pointer was last updated by hardware), the hardware retries any PCI writes until a slot in the queue becomes available. 4109 ** A slot in the post queue becomes available by the Intel XScale core incrementing the tail pointer. 4110 ** =================================================================================== 4111 ** Inbound Free Queue 4112 ** ------------------ 4113 ** The Inbound Free Queue holds free inbound messages placed there by the Intel XScale core for other processors to use. 4114 ** This queue is read from the queue tail by external PCI agents. 4115 ** It is written to the queue head by the Intel XScale core. 4116 ** The tail pointer is maintained by the MU hardware. 4117 ** The head pointer is maintained by the Intel XScale core. 4118 ** For a PCI read transaction that accesses the Inbound Queue Port, 4119 ** the MU attempts to read the data at the local memory address in the Inbound Free Tail Pointer. 4120 ** When the queue is not empty (head and tail pointers are not equal) or full (head and tail pointers are equal but the head pointer was last written by software), the data is returned. 4121 ** When the queue is empty (head and tail pointers are equal and the head pointer was last updated by hardware), the value of -1 (FFFF.FFFFH) is returned. 4122 ** When the queue was not empty and the MU succeeded in returning the data at the tail, 4123 ** the MU hardware must increment the value in the Inbound Free Tail Pointer Register. 4124 ** To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate accesses to the Inbound Free Queue. 4125 ** The MU hardware prefetches the data at the tail of the Inbound Free Queue and load it into an internal prefetch register. 4126 ** When the PCI read access occurs, the data is read directly from the prefetch register. 4127 ** The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register 4128 ** when the head and tail pointers are equal and the queue is empty. 4129 ** In order to update the prefetch register when messages are added to the queue and it becomes non-empty, 4130 ** the prefetch mechanism automatically starts a prefetch when the prefetch register contains FFFF.FFFFH and the Inbound Free Head Pointer Register is written. 4131 ** The Intel XScale core needs to update the Inbound Free Head Pointer Register when it adds messages to the queue. 4132 ** A prefetch must appear atomic from the perspective of the external PCI agent. 4133 ** When a prefetch is started, any PCI transaction that attempts to access the Inbound Free Queue is signalled a Retry until the prefetch is completed. 4134 ** The Intel XScale core may place messages in the Inbound Free Queue by writing the data to the 4135 ** local memory location pointed to by the Inbound Free Head Pointer Register. 4136 ** The processor must then increment the Inbound Free Head Pointer Register. 4137 ** ================================================================================== 4138 ** Outbound Post Queue 4139 ** ------------------- 4140 ** The Outbound Post Queue holds outbound posted messages placed there by the Intel XScale 4141 ** core for other processors to process. This queue is read from the queue tail by external PCI agents. 4142 ** It is written to the queue head by the Intel XScale core. The tail pointer is maintained by the 4143 ** MU hardware. The head pointer is maintained by the Intel XScale core. 4144 ** For a PCI read transaction that accesses the Outbound Queue Port, the MU attempts to read the 4145 ** data at the local memory address in the Outbound Post Tail Pointer Register. When the queue is not 4146 ** empty (head and tail pointers are not equal) or full (head and tail pointers are equal but the head 4147 ** pointer was last written by software), the data is returned. When the queue is empty (head and tail 4148 ** pointers are equal and the head pointer was last updated by hardware), the value of -1 4149 ** (FFFF.FFFFH) is returned. When the queue was not empty and the MU succeeded in returning the 4150 ** data at the tail, the MU hardware must increment the value in the Outbound Post Tail Pointer 4151 ** Register. 4152 ** To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate 4153 ** accesses to the Outbound Post Queue. The MU hardware prefetches the data at the tail of the 4154 ** Outbound Post Queue and load it into an internal prefetch register. When the PCI read access 4155 ** occurs, the data is read directly from the prefetch register. 4156 ** The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register when the head 4157 ** and tail pointers are equal and the queue is empty. In order to update the prefetch register when 4158 ** messages are added to the queue and it becomes non-empty, the prefetch mechanism automatically 4159 ** starts a prefetch when the prefetch register contains FFFF.FFFFH and the Outbound Post Head 4160 ** Pointer Register is written. The Intel XScale core needs to update the Outbound Post Head 4161 ** Pointer Register when it adds messages to the queue. 4162 ** A prefetch must appear atomic from the perspective of the external PCI agent. When a prefetch is 4163 ** started, any PCI transaction that attempts to access the Outbound Post Queue is signalled a Retry 4164 ** until the prefetch is completed. 4165 ** A PCI interrupt may be generated when data in the prefetch buffer is valid. When the prefetch 4166 ** queue is clear, no interrupt is generated. The Outbound Post Queue Interrupt bit in the Outbound 4167 ** Interrupt Status Register shall indicate the status of the prefetch buffer data and therefore the 4168 ** interrupt status. The interrupt is cleared when any prefetched data has been read from the Outbound 4169 ** Queue Port. The interrupt can be masked by the Outbound Interrupt Mask Register. 4170 ** The Intel XScale core may place messages in the Outbound Post Queue by writing the data to 4171 ** the local memory address in the Outbound Post Head Pointer Register. The processor must then 4172 ** increment the Outbound Post Head Pointer Register. 4173 ** ================================================== 4174 ** Outbound Free Queue 4175 ** ----------------------- 4176 ** The Outbound Free Queue holds free messages placed there by other processors for the Intel 4177 ** XScale core to use. This queue is read from the queue tail by the Intel XScale core. It is 4178 ** written to the queue head by external PCI agents. The tail pointer is maintained by the Intel 4179 ** XScale core. The head pointer is maintained by the MU hardware. 4180 ** For a PCI write transaction that accesses the Outbound Queue Port, the MU writes the data to the 4181 ** local memory address in the Outbound Free Head Pointer Register. When the data written to the 4182 ** Outbound Queue Port is written to local memory, the MU hardware increments the Outbound Free 4183 ** Head Pointer Register. 4184 ** When the head pointer and the tail pointer become equal and the queue is full, the MU may signal 4185 ** an interrupt to the Intel XScale core to register the queue full condition. This interrupt is 4186 ** recorded in the Inbound Interrupt Status Register. The interrupt is cleared when the Outbound Free 4187 ** Queue Full Interrupt bit is cleared and not by writing to the head or tail pointers. The interrupt can 4188 ** be masked by the Inbound Interrupt Mask Register. Software must be aware of the state of the 4189 ** Outbound Free Queue Interrupt Mask bit to guarantee that the full condition is recognized by the 4190 ** core processor. 4191 ** From the time that a PCI write transaction is received until the data is written in local memory and 4192 ** the Outbound Free Head Pointer Register is incremented, any PCI transaction that attempts to 4193 ** access the Outbound Free Queue Port is signalled a retry. 4194 ** The Intel XScale core may read messages from the Outbound Free Queue by reading the data 4195 ** from the local memory address in the Outbound Free Tail Pointer Register. The processor must 4196 ** then increment the Outbound Free Tail Pointer Register. When the Outbound Free Queue is full, 4197 ** the hardware must retry any PCI writes until a slot in the queue becomes available. 4198 ** 4199 ** ================================================================================== 4200 ** Circular Queue Summary 4201 ** ---------------------- 4202 ** ________________________________________________________________________________________________________________________________________________ 4203 ** | Queue Name | PCI Port |Generate PCI Interrupt |Generate Intel Xscale Core Interrupt|Head Pointer maintained by|Tail Pointer maintained by| 4204 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 4205 ** |Inbound Post | Inbound Queue | | | | | 4206 ** | Queue | Port | NO | Yes, when queue is written | MU hardware | Intel XScale | 4207 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 4208 ** |Inbound Free | Inbound Queue | | | | | 4209 ** | Queue | Port | NO | NO | Intel XScale | MU hardware | 4210 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 4211 ** ================================================================================== 4212 ** Circular Queue Status Summary 4213 ** ---------------------- 4214 ** ____________________________________________________________________________________________________ 4215 ** | Queue Name | Queue Status | Head & Tail Pointer | Last Pointer Update | 4216 ** |_____________________|________________|_____________________|_______________________________________| 4217 ** | Inbound Post Queue | Empty | Equal | Tail pointer last updated by software | 4218 ** |_____________________|________________|_____________________|_______________________________________| 4219 ** | Inbound Free Queue | Empty | Equal | Head pointer last updated by hardware | 4220 ** |_____________________|________________|_____________________|_______________________________________| 4221 ************************************************************************** 4222 */ 4223 4224 /* 4225 ************************************************************************** 4226 ** Index Registers 4227 ** ======================== 4228 ** . The Index Registers are a set of 1004 registers that when written by an external PCI agent can generate an interrupt to the Intel XScale core. 4229 ** These registers are for inbound messages only. 4230 ** The interrupt is recorded in the Inbound Interrupt Status Register. 4231 ** The storage for the Index Registers is allocated from the 80331 local memory. 4232 ** PCI write accesses to the Index Registers write the data to local memory. 4233 ** PCI read accesses to the Index Registers read the data from local memory. 4234 ** . The local memory used for the Index Registers ranges from Inbound ATU Translate Value Register + 050H 4235 ** to Inbound ATU Translate Value Register + FFFH. 4236 ** . The address of the first write access is stored in the Index Address Register. 4237 ** This register is written during the earliest write access and provides a means to determine which Index Register was written. 4238 ** Once updated by the MU, the Index Address Register is not updated until the Index Register Interrupt bit in the Inbound Interrupt Status Register is cleared. 4239 ** . When the interrupt is cleared, the Index Address Register is re-enabled and stores the address of the next Index Register write access. 4240 ** Writes by the Intel XScale core to the local memory used by the Index Registers does not cause an interrupt and does not update the Index Address Register. 4241 ** . The index registers can be accessed with Multi-DWORD reads and single QWORD aligned writes. 4242 ************************************************************************** 4243 */ 4244 /* 4245 ************************************************************************** 4246 ** Messaging Unit Internal Bus Memory Map 4247 ** ======================================= 4248 ** Internal Bus Address___Register Description (Name)____________________|_PCI Configuration Space Register Number_ 4249 ** FFFF E300H reserved | 4250 ** .. .. | 4251 ** FFFF E30CH reserved | 4252 ** FFFF E310H Inbound Message Register 0 | Available through 4253 ** FFFF E314H Inbound Message Register 1 | ATU Inbound Translation Window 4254 ** FFFF E318H Outbound Message Register 0 | 4255 ** FFFF E31CH Outbound Message Register 1 | or 4256 ** FFFF E320H Inbound Doorbell Register | 4257 ** FFFF E324H Inbound Interrupt Status Register | must translate PCI address to 4258 ** FFFF E328H Inbound Interrupt Mask Register | the Intel Xscale Core 4259 ** FFFF E32CH Outbound Doorbell Register | Memory-Mapped Address 4260 ** FFFF E330H Outbound Interrupt Status Register | 4261 ** FFFF E334H Outbound Interrupt Mask Register | 4262 ** ______________________________________________________________________|________________________________________ 4263 ** FFFF E338H reserved | 4264 ** FFFF E33CH reserved | 4265 ** FFFF E340H reserved | 4266 ** FFFF E344H reserved | 4267 ** FFFF E348H reserved | 4268 ** FFFF E34CH reserved | 4269 ** FFFF E350H MU Configuration Register | 4270 ** FFFF E354H Queue Base Address Register | 4271 ** FFFF E358H reserved | 4272 ** FFFF E35CH reserved | must translate PCI address to 4273 ** FFFF E360H Inbound Free Head Pointer Register | the Intel Xscale Core 4274 ** FFFF E364H Inbound Free Tail Pointer Register | Memory-Mapped Address 4275 ** FFFF E368H Inbound Post Head pointer Register | 4276 ** FFFF E36CH Inbound Post Tail Pointer Register | 4277 ** FFFF E370H Outbound Free Head Pointer Register | 4278 ** FFFF E374H Outbound Free Tail Pointer Register | 4279 ** FFFF E378H Outbound Post Head pointer Register | 4280 ** FFFF E37CH Outbound Post Tail Pointer Register | 4281 ** FFFF E380H Index Address Register | 4282 ** FFFF E384H reserved | 4283 ** .. .. | 4284 ** FFFF E3FCH reserved | 4285 ** ______________________________________________________________________|_______________________________________ 4286 ************************************************************************** 4287 */ 4288 /* 4289 ************************************************************************** 4290 ** MU Configuration Register - MUCR FFFF.E350H 4291 ** 4292 ** . The MU Configuration Register (MUCR) contains the Circular Queue Enable bit and the size of one Circular Queue. 4293 ** . The Circular Queue Enable bit enables or disables the Circular Queues. 4294 ** The Circular Queues are disabled at reset to allow the software to initialize the head and tail pointer registers before any PCI accesses to the Queue Ports. 4295 ** . Each Circular Queue may range from 4 K entries (16 Kbytes) to 64 K entries (256 Kbytes) and there are four Circular Queues. 4296 ** ------------------------------------------------------------------------ 4297 ** Bit Default Description 4298 ** 31:06 000000H 00 2 Reserved 4299 ** 05:01 00001 2 Circular Queue Size - This field determines the size of each Circular Queue. 4300 ** All four queues are the same size. 4301 ** �E 00001 2 - 4K Entries (16 Kbytes) 4302 ** �E 00010 2 - 8K Entries (32 Kbytes) 4303 ** �E 00100 2 - 16K Entries (64 Kbytes) 4304 ** �E 01000 2 - 32K Entries (128 Kbytes) 4305 ** �E 10000 2 - 64K Entries (256 Kbytes) 4306 ** 00 0 2 Circular Queue Enable - This bit enables or disables the Circular Queues. When clear the Circular 4307 ** Queues are disabled, however the MU accepts PCI accesses to the Circular Queue Ports but ignores 4308 ** the data for Writes and return FFFF.FFFFH for Reads. Interrupts are not generated to the core when 4309 ** disabled. When set, the Circular Queues are fully enabled. 4310 ************************************************************************** 4311 */ 4312 #define ARCMSR_MU_CONFIGURATION_REG 0xFFFFE350 4313 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE64K 0x0020 4314 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE32K 0x0010 4315 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE16K 0x0008 4316 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE8K 0x0004 4317 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE4K 0x0002 4318 #define ARCMSR_MU_CIRCULAR_QUEUE_ENABLE 0x0001 /*0:disable 1:enable*/ 4319 /* 4320 ************************************************************************** 4321 ** Queue Base Address Register - QBAR 4322 ** 4323 ** . The Queue Base Address Register (QBAR) contains the local memory address of the Circular Queues. 4324 ** The base address is required to be located on a 1 Mbyte address boundary. 4325 ** . All Circular Queue head and tail pointers are based on the QBAR. 4326 ** When the head and tail pointer registers are read, the Queue Base Address is returned in the upper 12 bits. 4327 ** Writing to the upper 12 bits of the head and tail pointer registers does not affect the Queue Base Address or Queue Base Address Register. 4328 ** Warning: 4329 ** The QBAR must designate a range allocated to the 80331 DDR SDRAM interface 4330 ** ------------------------------------------------------------------------ 4331 ** Bit Default Description 4332 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 4333 ** 19:00 00000H Reserved 4334 ************************************************************************** 4335 */ 4336 #define ARCMSR_MU_QUEUE_BASE_ADDRESS_REG 0xFFFFE354 4337 /* 4338 ************************************************************************** 4339 ** Inbound Free Head Pointer Register - IFHPR 4340 ** 4341 ** . The Inbound Free Head Pointer Register (IFHPR) contains the local memory offset from the Queue Base Address of the head pointer for the Inbound Free Queue. 4342 ** The Head Pointer must be aligned on a DWORD address boundary. 4343 ** When read, the Queue Base Address is provided in the upper 12 bits of the register. 4344 ** Writes to the upper 12 bits of the register are ignored. 4345 ** This register is maintained by software. 4346 ** ------------------------------------------------------------------------ 4347 ** Bit Default Description 4348 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 4349 ** 19:02 0000H 00 2 Inbound Free Head Pointer - Local memory offset of the head pointer for the Inbound Free Queue. 4350 ** 01:00 00 2 Reserved 4351 ************************************************************************** 4352 */ 4353 #define ARCMSR_MU_INBOUND_FREE_HEAD_PTR_REG 0xFFFFE360 4354 /* 4355 ************************************************************************** 4356 ** Inbound Free Tail Pointer Register - IFTPR 4357 ** 4358 ** . The Inbound Free Tail Pointer Register (IFTPR) contains the local memory offset from the Queue 4359 ** Base Address of the tail pointer for the Inbound Free Queue. The Tail Pointer must be aligned on a 4360 ** DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 4361 ** of the register. Writes to the upper 12 bits of the register are ignored. 4362 ** ------------------------------------------------------------------------ 4363 ** Bit Default Description 4364 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 4365 ** 19:02 0000H 00 2 Inbound Free Tail Pointer - Local memory offset of the tail pointer for the Inbound Free Queue. 4366 ** 01:00 00 2 Reserved 4367 ************************************************************************** 4368 */ 4369 #define ARCMSR_MU_INBOUND_FREE_TAIL_PTR_REG 0xFFFFE364 4370 /* 4371 ************************************************************************** 4372 ** Inbound Post Head Pointer Register - IPHPR 4373 ** 4374 ** . The Inbound Post Head Pointer Register (IPHPR) contains the local memory offset from the Queue 4375 ** Base Address of the head pointer for the Inbound Post Queue. The Head Pointer must be aligned on 4376 ** a DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 4377 ** of the register. Writes to the upper 12 bits of the register are ignored. 4378 ** ------------------------------------------------------------------------ 4379 ** Bit Default Description 4380 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 4381 ** 19:02 0000H 00 2 Inbound Post Head Pointer - Local memory offset of the head pointer for the Inbound Post Queue. 4382 ** 01:00 00 2 Reserved 4383 ************************************************************************** 4384 */ 4385 #define ARCMSR_MU_INBOUND_POST_HEAD_PTR_REG 0xFFFFE368 4386 /* 4387 ************************************************************************** 4388 ** Inbound Post Tail Pointer Register - IPTPR 4389 ** 4390 ** . The Inbound Post Tail Pointer Register (IPTPR) contains the local memory offset from the Queue 4391 ** Base Address of the tail pointer for the Inbound Post Queue. The Tail Pointer must be aligned on a 4392 ** DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 4393 ** of the register. Writes to the upper 12 bits of the register are ignored. 4394 ** ------------------------------------------------------------------------ 4395 ** Bit Default Description 4396 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 4397 ** 19:02 0000H 00 2 Inbound Post Tail Pointer - Local memory offset of the tail pointer for the Inbound Post Queue. 4398 ** 01:00 00 2 Reserved 4399 ************************************************************************** 4400 */ 4401 #define ARCMSR_MU_INBOUND_POST_TAIL_PTR_REG 0xFFFFE36C 4402 /* 4403 ************************************************************************** 4404 ** Index Address Register - IAR 4405 ** 4406 ** . The Index Address Register (IAR) contains the offset of the least recently accessed Index Register. 4407 ** It is written by the MU when the Index Registers are written by a PCI agent. 4408 ** The register is not updated until the Index Interrupt bit in the Inbound Interrupt Status Register is cleared. 4409 ** . The local memory address of the Index Register least recently accessed is computed by adding the Index Address Register to the Inbound ATU Translate Value Register. 4410 ** ------------------------------------------------------------------------ 4411 ** Bit Default Description 4412 ** 31:12 000000H Reserved 4413 ** 11:02 00H 00 2 Index Address - is the local memory offset of the Index Register written (050H to FFCH) 4414 ** 01:00 00 2 Reserved 4415 ************************************************************************** 4416 */ 4417 #define ARCMSR_MU_LOCAL_MEMORY_INDEX_REG 0xFFFFE380 /*1004 dwords 0x0050....0x0FFC, 4016 bytes 0x0050...0x0FFF*/ 4418 /* 4419 ********************************************************************************************************** 4420 ** RS-232 Interface for Areca Raid Controller 4421 ** The low level command interface is exclusive with VT100 terminal 4422 ** -------------------------------------------------------------------- 4423 ** 1. Sequence of command execution 4424 ** -------------------------------------------------------------------- 4425 ** (A) Header : 3 bytes sequence (0x5E, 0x01, 0x61) 4426 ** (B) Command block : variable length of data including length, command code, data and checksum byte 4427 ** (C) Return data : variable length of data 4428 ** -------------------------------------------------------------------- 4429 ** 2. Command block 4430 ** -------------------------------------------------------------------- 4431 ** (A) 1st byte : command block length (low byte) 4432 ** (B) 2nd byte : command block length (high byte) 4433 ** note ..command block length shouldn't > 2040 bytes, length excludes these two bytes 4434 ** (C) 3rd byte : command code 4435 ** (D) 4th and following bytes : variable length data bytes depends on command code 4436 ** (E) last byte : checksum byte (sum of 1st byte until last data byte) 4437 ** -------------------------------------------------------------------- 4438 ** 3. Command code and associated data 4439 ** -------------------------------------------------------------------- 4440 ** The following are command code defined in raid controller Command code 0x10--0x1? are used for system level management, no password checking is needed and should be implemented in separate well controlled utility and not for end user access. 4441 ** Command code 0x20--0x?? always check the password, password must be entered to enable these command. 4442 ** enum 4443 ** { 4444 ** GUI_SET_SERIAL=0x10, 4445 ** GUI_SET_VENDOR, 4446 ** GUI_SET_MODEL, 4447 ** GUI_IDENTIFY, 4448 ** GUI_CHECK_PASSWORD, 4449 ** GUI_LOGOUT, 4450 ** GUI_HTTP, 4451 ** GUI_SET_ETHERNET_ADDR, 4452 ** GUI_SET_LOGO, 4453 ** GUI_POLL_EVENT, 4454 ** GUI_GET_EVENT, 4455 ** GUI_GET_HW_MONITOR, 4456 ** 4457 ** // GUI_QUICK_CREATE=0x20, (function removed) 4458 ** GUI_GET_INFO_R=0x20, 4459 ** GUI_GET_INFO_V, 4460 ** GUI_GET_INFO_P, 4461 ** GUI_GET_INFO_S, 4462 ** GUI_CLEAR_EVENT, 4463 ** 4464 ** GUI_MUTE_BEEPER=0x30, 4465 ** GUI_BEEPER_SETTING, 4466 ** GUI_SET_PASSWORD, 4467 ** GUI_HOST_INTERFACE_MODE, 4468 ** GUI_REBUILD_PRIORITY, 4469 ** GUI_MAX_ATA_MODE, 4470 ** GUI_RESET_CONTROLLER, 4471 ** GUI_COM_PORT_SETTING, 4472 ** GUI_NO_OPERATION, 4473 ** GUI_DHCP_IP, 4474 ** 4475 ** GUI_CREATE_PASS_THROUGH=0x40, 4476 ** GUI_MODIFY_PASS_THROUGH, 4477 ** GUI_DELETE_PASS_THROUGH, 4478 ** GUI_IDENTIFY_DEVICE, 4479 ** 4480 ** GUI_CREATE_RAIDSET=0x50, 4481 ** GUI_DELETE_RAIDSET, 4482 ** GUI_EXPAND_RAIDSET, 4483 ** GUI_ACTIVATE_RAIDSET, 4484 ** GUI_CREATE_HOT_SPARE, 4485 ** GUI_DELETE_HOT_SPARE, 4486 ** 4487 ** GUI_CREATE_VOLUME=0x60, 4488 ** GUI_MODIFY_VOLUME, 4489 ** GUI_DELETE_VOLUME, 4490 ** GUI_START_CHECK_VOLUME, 4491 ** GUI_STOP_CHECK_VOLUME 4492 ** }; 4493 ** 4494 ** Command description : 4495 ** 4496 ** GUI_SET_SERIAL : Set the controller serial# 4497 ** byte 0,1 : length 4498 ** byte 2 : command code 0x10 4499 ** byte 3 : password length (should be 0x0f) 4500 ** byte 4-0x13 : should be "ArEcATecHnoLogY" 4501 ** byte 0x14--0x23 : Serial number string (must be 16 bytes) 4502 ** GUI_SET_VENDOR : Set vendor string for the controller 4503 ** byte 0,1 : length 4504 ** byte 2 : command code 0x11 4505 ** byte 3 : password length (should be 0x08) 4506 ** byte 4-0x13 : should be "ArEcAvAr" 4507 ** byte 0x14--0x3B : vendor string (must be 40 bytes) 4508 ** GUI_SET_MODEL : Set the model name of the controller 4509 ** byte 0,1 : length 4510 ** byte 2 : command code 0x12 4511 ** byte 3 : password length (should be 0x08) 4512 ** byte 4-0x13 : should be "ArEcAvAr" 4513 ** byte 0x14--0x1B : model string (must be 8 bytes) 4514 ** GUI_IDENTIFY : Identify device 4515 ** byte 0,1 : length 4516 ** byte 2 : command code 0x13 4517 ** return "Areca RAID Subsystem " 4518 ** GUI_CHECK_PASSWORD : Verify password 4519 ** byte 0,1 : length 4520 ** byte 2 : command code 0x14 4521 ** byte 3 : password length 4522 ** byte 4-0x?? : user password to be checked 4523 ** GUI_LOGOUT : Logout GUI (force password checking on next command) 4524 ** byte 0,1 : length 4525 ** byte 2 : command code 0x15 4526 ** GUI_HTTP : HTTP interface (reserved for Http proxy service)(0x16) 4527 ** 4528 ** GUI_SET_ETHERNET_ADDR : Set the ethernet MAC address 4529 ** byte 0,1 : length 4530 ** byte 2 : command code 0x17 4531 ** byte 3 : password length (should be 0x08) 4532 ** byte 4-0x13 : should be "ArEcAvAr" 4533 ** byte 0x14--0x19 : Ethernet MAC address (must be 6 bytes) 4534 ** GUI_SET_LOGO : Set logo in HTTP 4535 ** byte 0,1 : length 4536 ** byte 2 : command code 0x18 4537 ** byte 3 : Page# (0/1/2/3) (0xff --> clear OEM logo) 4538 ** byte 4/5/6/7 : 0x55/0xaa/0xa5/0x5a 4539 ** byte 8 : TITLE.JPG data (each page must be 2000 bytes) 4540 ** note .... page0 1st 2 byte must be actual length of the JPG file 4541 ** GUI_POLL_EVENT : Poll If Event Log Changed 4542 ** byte 0,1 : length 4543 ** byte 2 : command code 0x19 4544 ** GUI_GET_EVENT : Read Event 4545 ** byte 0,1 : length 4546 ** byte 2 : command code 0x1a 4547 ** byte 3 : Event Page (0:1st page/1/2/3:last page) 4548 ** GUI_GET_HW_MONITOR : Get HW monitor data 4549 ** byte 0,1 : length 4550 ** byte 2 : command code 0x1b 4551 ** byte 3 : # of FANs(example 2) 4552 ** byte 4 : # of Voltage sensor(example 3) 4553 ** byte 5 : # of temperature sensor(example 2) 4554 ** byte 6 : # of power 4555 ** byte 7/8 : Fan#0 (RPM) 4556 ** byte 9/10 : Fan#1 4557 ** byte 11/12 : Voltage#0 original value in *1000 4558 ** byte 13/14 : Voltage#0 value 4559 ** byte 15/16 : Voltage#1 org 4560 ** byte 17/18 : Voltage#1 4561 ** byte 19/20 : Voltage#2 org 4562 ** byte 21/22 : Voltage#2 4563 ** byte 23 : Temp#0 4564 ** byte 24 : Temp#1 4565 ** byte 25 : Power indicator (bit0 : power#0, bit1 : power#1) 4566 ** byte 26 : UPS indicator 4567 ** GUI_QUICK_CREATE : Quick create raid/volume set 4568 ** byte 0,1 : length 4569 ** byte 2 : command code 0x20 4570 ** byte 3/4/5/6 : raw capacity 4571 ** byte 7 : raid level 4572 ** byte 8 : stripe size 4573 ** byte 9 : spare 4574 ** byte 10/11/12/13: device mask (the devices to create raid/volume) 4575 ** This function is removed, application like to implement quick create function 4576 ** need to use GUI_CREATE_RAIDSET and GUI_CREATE_VOLUMESET function. 4577 ** GUI_GET_INFO_R : Get Raid Set Information 4578 ** byte 0,1 : length 4579 ** byte 2 : command code 0x20 4580 ** byte 3 : raidset# 4581 ** 4582 ** typedef struct sGUI_RAIDSET 4583 ** { 4584 ** BYTE grsRaidSetName[16]; 4585 ** DWORD grsCapacity; 4586 ** DWORD grsCapacityX; 4587 ** DWORD grsFailMask; 4588 ** BYTE grsDevArray[32]; 4589 ** BYTE grsMemberDevices; 4590 ** BYTE grsNewMemberDevices; 4591 ** BYTE grsRaidState; 4592 ** BYTE grsVolumes; 4593 ** BYTE grsVolumeList[16]; 4594 ** BYTE grsRes1; 4595 ** BYTE grsRes2; 4596 ** BYTE grsRes3; 4597 ** BYTE grsFreeSegments; 4598 ** DWORD grsRawStripes[8]; 4599 ** DWORD grsRes4; 4600 ** DWORD grsRes5; // Total to 128 bytes 4601 ** DWORD grsRes6; // Total to 128 bytes 4602 ** } sGUI_RAIDSET, *pGUI_RAIDSET; 4603 ** GUI_GET_INFO_V : Get Volume Set Information 4604 ** byte 0,1 : length 4605 ** byte 2 : command code 0x21 4606 ** byte 3 : volumeset# 4607 ** 4608 ** typedef struct sGUI_VOLUMESET 4609 ** { 4610 ** BYTE gvsVolumeName[16]; // 16 4611 ** DWORD gvsCapacity; 4612 ** DWORD gvsCapacityX; 4613 ** DWORD gvsFailMask; 4614 ** DWORD gvsStripeSize; 4615 ** DWORD gvsNewFailMask; 4616 ** DWORD gvsNewStripeSize; 4617 ** DWORD gvsVolumeStatus; 4618 ** DWORD gvsProgress; // 32 4619 ** sSCSI_ATTR gvsScsi; 4620 ** BYTE gvsMemberDisks; 4621 ** BYTE gvsRaidLevel; // 8 4622 ** 4623 ** BYTE gvsNewMemberDisks; 4624 ** BYTE gvsNewRaidLevel; 4625 ** BYTE gvsRaidSetNumber; 4626 ** BYTE gvsRes0; // 4 4627 ** BYTE gvsRes1[4]; // 64 bytes 4628 ** } sGUI_VOLUMESET, *pGUI_VOLUMESET; 4629 ** 4630 ** GUI_GET_INFO_P : Get Physical Drive Information 4631 ** byte 0,1 : length 4632 ** byte 2 : command code 0x22 4633 ** byte 3 : drive # (from 0 to max-channels - 1) 4634 ** 4635 ** typedef struct sGUI_PHY_DRV 4636 ** { 4637 ** BYTE gpdModelName[40]; 4638 ** BYTE gpdSerialNumber[20]; 4639 ** BYTE gpdFirmRev[8]; 4640 ** DWORD gpdCapacity; 4641 ** DWORD gpdCapacityX; // Reserved for expansion 4642 ** BYTE gpdDeviceState; 4643 ** BYTE gpdPioMode; 4644 ** BYTE gpdCurrentUdmaMode; 4645 ** BYTE gpdUdmaMode; 4646 ** BYTE gpdDriveSelect; 4647 ** BYTE gpdRaidNumber; // 0xff if not belongs to a raid set 4648 ** sSCSI_ATTR gpdScsi; 4649 ** BYTE gpdReserved[40]; // Total to 128 bytes 4650 ** } sGUI_PHY_DRV, *pGUI_PHY_DRV; 4651 ** 4652 ** GUI_GET_INFO_S : Get System Information 4653 ** byte 0,1 : length 4654 ** byte 2 : command code 0x23 4655 ** 4656 ** typedef struct sCOM_ATTR 4657 ** { 4658 ** BYTE comBaudRate; 4659 ** BYTE comDataBits; 4660 ** BYTE comStopBits; 4661 ** BYTE comParity; 4662 ** BYTE comFlowControl; 4663 ** } sCOM_ATTR, *pCOM_ATTR; 4664 ** 4665 ** typedef struct sSYSTEM_INFO 4666 ** { 4667 ** BYTE gsiVendorName[40]; 4668 ** BYTE gsiSerialNumber[16]; 4669 ** BYTE gsiFirmVersion[16]; 4670 ** BYTE gsiBootVersion[16]; 4671 ** BYTE gsiMbVersion[16]; 4672 ** BYTE gsiModelName[8]; 4673 ** BYTE gsiLocalIp[4]; 4674 ** BYTE gsiCurrentIp[4]; 4675 ** DWORD gsiTimeTick; 4676 ** DWORD gsiCpuSpeed; 4677 ** DWORD gsiICache; 4678 ** DWORD gsiDCache; 4679 ** DWORD gsiScache; 4680 ** DWORD gsiMemorySize; 4681 ** DWORD gsiMemorySpeed; 4682 ** DWORD gsiEvents; 4683 ** BYTE gsiMacAddress[6]; 4684 ** BYTE gsiDhcp; 4685 ** BYTE gsiBeeper; 4686 ** BYTE gsiChannelUsage; 4687 ** BYTE gsiMaxAtaMode; 4688 ** BYTE gsiSdramEcc; // 1:if ECC enabled 4689 ** BYTE gsiRebuildPriority; 4690 ** sCOM_ATTR gsiComA; // 5 bytes 4691 ** sCOM_ATTR gsiComB; // 5 bytes 4692 ** BYTE gsiIdeChannels; 4693 ** BYTE gsiScsiHostChannels; 4694 ** BYTE gsiIdeHostChannels; 4695 ** BYTE gsiMaxVolumeSet; 4696 ** BYTE gsiMaxRaidSet; 4697 ** BYTE gsiEtherPort; // 1:if ether net port supported 4698 ** BYTE gsiRaid6Engine; // 1:Raid6 engine supported 4699 ** BYTE gsiRes[75]; 4700 ** } sSYSTEM_INFO, *pSYSTEM_INFO; 4701 ** 4702 ** GUI_CLEAR_EVENT : Clear System Event 4703 ** byte 0,1 : length 4704 ** byte 2 : command code 0x24 4705 ** 4706 ** GUI_MUTE_BEEPER : Mute current beeper 4707 ** byte 0,1 : length 4708 ** byte 2 : command code 0x30 4709 ** 4710 ** GUI_BEEPER_SETTING : Disable beeper 4711 ** byte 0,1 : length 4712 ** byte 2 : command code 0x31 4713 ** byte 3 : 0->disable, 1->enable 4714 ** 4715 ** GUI_SET_PASSWORD : Change password 4716 ** byte 0,1 : length 4717 ** byte 2 : command code 0x32 4718 ** byte 3 : pass word length ( must <= 15 ) 4719 ** byte 4 : password (must be alpha-numerical) 4720 ** 4721 ** GUI_HOST_INTERFACE_MODE : Set host interface mode 4722 ** byte 0,1 : length 4723 ** byte 2 : command code 0x33 4724 ** byte 3 : 0->Independent, 1->cluster 4725 ** 4726 ** GUI_REBUILD_PRIORITY : Set rebuild priority 4727 ** byte 0,1 : length 4728 ** byte 2 : command code 0x34 4729 ** byte 3 : 0/1/2/3 (low->high) 4730 ** 4731 ** GUI_MAX_ATA_MODE : Set maximum ATA mode to be used 4732 ** byte 0,1 : length 4733 ** byte 2 : command code 0x35 4734 ** byte 3 : 0/1/2/3 (133/100/66/33) 4735 ** 4736 ** GUI_RESET_CONTROLLER : Reset Controller 4737 ** byte 0,1 : length 4738 ** byte 2 : command code 0x36 4739 ** *Response with VT100 screen (discard it) 4740 ** 4741 ** GUI_COM_PORT_SETTING : COM port setting 4742 ** byte 0,1 : length 4743 ** byte 2 : command code 0x37 4744 ** byte 3 : 0->COMA (term port), 1->COMB (debug port) 4745 ** byte 4 : 0/1/2/3/4/5/6/7 (1200/2400/4800/9600/19200/38400/57600/115200) 4746 ** byte 5 : data bit (0:7 bit, 1:8 bit : must be 8 bit) 4747 ** byte 6 : stop bit (0:1, 1:2 stop bits) 4748 ** byte 7 : parity (0:none, 1:off, 2:even) 4749 ** byte 8 : flow control (0:none, 1:xon/xoff, 2:hardware => must use none) 4750 ** 4751 ** GUI_NO_OPERATION : No operation 4752 ** byte 0,1 : length 4753 ** byte 2 : command code 0x38 4754 ** 4755 ** GUI_DHCP_IP : Set DHCP option and local IP address 4756 ** byte 0,1 : length 4757 ** byte 2 : command code 0x39 4758 ** byte 3 : 0:dhcp disabled, 1:dhcp enabled 4759 ** byte 4/5/6/7 : IP address 4760 ** 4761 ** GUI_CREATE_PASS_THROUGH : Create pass through disk 4762 ** byte 0,1 : length 4763 ** byte 2 : command code 0x40 4764 ** byte 3 : device # 4765 ** byte 4 : scsi channel (0/1) 4766 ** byte 5 : scsi id (0-->15) 4767 ** byte 6 : scsi lun (0-->7) 4768 ** byte 7 : tagged queue (1 : enabled) 4769 ** byte 8 : cache mode (1 : enabled) 4770 ** byte 9 : max speed (0/1/2/3/4, async/20/40/80/160 for scsi) 4771 ** (0/1/2/3/4, 33/66/100/133/150 for ide ) 4772 ** 4773 ** GUI_MODIFY_PASS_THROUGH : Modify pass through disk 4774 ** byte 0,1 : length 4775 ** byte 2 : command code 0x41 4776 ** byte 3 : device # 4777 ** byte 4 : scsi channel (0/1) 4778 ** byte 5 : scsi id (0-->15) 4779 ** byte 6 : scsi lun (0-->7) 4780 ** byte 7 : tagged queue (1 : enabled) 4781 ** byte 8 : cache mode (1 : enabled) 4782 ** byte 9 : max speed (0/1/2/3/4, async/20/40/80/160 for scsi) 4783 ** (0/1/2/3/4, 33/66/100/133/150 for ide ) 4784 ** 4785 ** GUI_DELETE_PASS_THROUGH : Delete pass through disk 4786 ** byte 0,1 : length 4787 ** byte 2 : command code 0x42 4788 ** byte 3 : device# to be deleted 4789 ** 4790 ** GUI_IDENTIFY_DEVICE : Identify Device 4791 ** byte 0,1 : length 4792 ** byte 2 : command code 0x43 4793 ** byte 3 : Flash Method(0:flash selected, 1:flash not selected) 4794 ** byte 4/5/6/7 : IDE device mask to be flashed 4795 ** note .... no response data available 4796 ** 4797 ** GUI_CREATE_RAIDSET : Create Raid Set 4798 ** byte 0,1 : length 4799 ** byte 2 : command code 0x50 4800 ** byte 3/4/5/6 : device mask 4801 ** byte 7-22 : raidset name (if byte 7 == 0:use default) 4802 ** 4803 ** GUI_DELETE_RAIDSET : Delete Raid Set 4804 ** byte 0,1 : length 4805 ** byte 2 : command code 0x51 4806 ** byte 3 : raidset# 4807 ** 4808 ** GUI_EXPAND_RAIDSET : Expand Raid Set 4809 ** byte 0,1 : length 4810 ** byte 2 : command code 0x52 4811 ** byte 3 : raidset# 4812 ** byte 4/5/6/7 : device mask for expansion 4813 ** byte 8/9/10 : (8:0 no change, 1 change, 0xff:terminate, 9:new raid level,10:new stripe size 0/1/2/3/4/5->4/8/16/32/64/128K ) 4814 ** byte 11/12/13 : repeat for each volume in the raidset .... 4815 ** 4816 ** GUI_ACTIVATE_RAIDSET : Activate incomplete raid set 4817 ** byte 0,1 : length 4818 ** byte 2 : command code 0x53 4819 ** byte 3 : raidset# 4820 ** 4821 ** GUI_CREATE_HOT_SPARE : Create hot spare disk 4822 ** byte 0,1 : length 4823 ** byte 2 : command code 0x54 4824 ** byte 3/4/5/6 : device mask for hot spare creation 4825 ** 4826 ** GUI_DELETE_HOT_SPARE : Delete hot spare disk 4827 ** byte 0,1 : length 4828 ** byte 2 : command code 0x55 4829 ** byte 3/4/5/6 : device mask for hot spare deletion 4830 ** 4831 ** GUI_CREATE_VOLUME : Create volume set 4832 ** byte 0,1 : length 4833 ** byte 2 : command code 0x60 4834 ** byte 3 : raidset# 4835 ** byte 4-19 : volume set name (if byte4 == 0, use default) 4836 ** byte 20-27 : volume capacity (blocks) 4837 ** byte 28 : raid level 4838 ** byte 29 : stripe size (0/1/2/3/4/5->4/8/16/32/64/128K) 4839 ** byte 30 : channel 4840 ** byte 31 : ID 4841 ** byte 32 : LUN 4842 ** byte 33 : 1 enable tag 4843 ** byte 34 : 1 enable cache 4844 ** byte 35 : speed (0/1/2/3/4->async/20/40/80/160 for scsi) 4845 ** (0/1/2/3/4->33/66/100/133/150 for IDE ) 4846 ** byte 36 : 1 to select quick init 4847 ** 4848 ** GUI_MODIFY_VOLUME : Modify volume Set 4849 ** byte 0,1 : length 4850 ** byte 2 : command code 0x61 4851 ** byte 3 : volumeset# 4852 ** byte 4-19 : new volume set name (if byte4 == 0, not change) 4853 ** byte 20-27 : new volume capacity (reserved) 4854 ** byte 28 : new raid level 4855 ** byte 29 : new stripe size (0/1/2/3/4/5->4/8/16/32/64/128K) 4856 ** byte 30 : new channel 4857 ** byte 31 : new ID 4858 ** byte 32 : new LUN 4859 ** byte 33 : 1 enable tag 4860 ** byte 34 : 1 enable cache 4861 ** byte 35 : speed (0/1/2/3/4->async/20/40/80/160 for scsi) 4862 ** (0/1/2/3/4->33/66/100/133/150 for IDE ) 4863 ** 4864 ** GUI_DELETE_VOLUME : Delete volume set 4865 ** byte 0,1 : length 4866 ** byte 2 : command code 0x62 4867 ** byte 3 : volumeset# 4868 ** 4869 ** GUI_START_CHECK_VOLUME : Start volume consistency check 4870 ** byte 0,1 : length 4871 ** byte 2 : command code 0x63 4872 ** byte 3 : volumeset# 4873 ** 4874 ** GUI_STOP_CHECK_VOLUME : Stop volume consistency check 4875 ** byte 0,1 : length 4876 ** byte 2 : command code 0x64 4877 ** --------------------------------------------------------------------- 4878 ** 4. Returned data 4879 ** --------------------------------------------------------------------- 4880 ** (A) Header : 3 bytes sequence (0x5E, 0x01, 0x61) 4881 ** (B) Length : 2 bytes (low byte 1st, excludes length and checksum byte) 4882 ** (C) status or data : 4883 ** <1> If length == 1 ==> 1 byte status code 4884 ** #define GUI_OK 0x41 4885 ** #define GUI_RAIDSET_NOT_NORMAL 0x42 4886 ** #define GUI_VOLUMESET_NOT_NORMAL 0x43 4887 ** #define GUI_NO_RAIDSET 0x44 4888 ** #define GUI_NO_VOLUMESET 0x45 4889 ** #define GUI_NO_PHYSICAL_DRIVE 0x46 4890 ** #define GUI_PARAMETER_ERROR 0x47 4891 ** #define GUI_UNSUPPORTED_COMMAND 0x48 4892 ** #define GUI_DISK_CONFIG_CHANGED 0x49 4893 ** #define GUI_INVALID_PASSWORD 0x4a 4894 ** #define GUI_NO_DISK_SPACE 0x4b 4895 ** #define GUI_CHECKSUM_ERROR 0x4c 4896 ** #define GUI_PASSWORD_REQUIRED 0x4d 4897 ** <2> If length > 1 ==> data block returned from controller and the contents depends on the command code 4898 ** (E) Checksum : checksum of length and status or data byte 4899 ************************************************************************** 4900 */ 4901