1 /* 2 ******************************************************************************** 3 ** OS : FreeBSD 4 ** FILE NAME : arcmsr.h 5 ** BY : Erich Chen, Ching Huang 6 ** Description: SCSI RAID Device Driver for 7 ** ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x) 8 ** SATA/SAS RAID HOST Adapter 9 ******************************************************************************** 10 ******************************************************************************** 11 ** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved. 12 ** 13 ** Redistribution and use in source and binary forms,with or without 14 ** modification,are permitted provided that the following conditions 15 ** are met: 16 ** 1. Redistributions of source code must retain the above copyright 17 ** notice,this list of conditions and the following disclaimer. 18 ** 2. Redistributions in binary form must reproduce the above copyright 19 ** notice,this list of conditions and the following disclaimer in the 20 ** documentation and/or other materials provided with the distribution. 21 ** 3. The name of the author may not be used to endorse or promote products 22 ** derived from this software without specific prior written permission. 23 ** 24 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 25 ** IMPLIED WARRANTIES,INCLUDING,BUT NOT LIMITED TO,THE IMPLIED WARRANTIES 26 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 27 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,INDIRECT, 28 ** INCIDENTAL,SPECIAL,EXEMPLARY,OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT 29 ** NOT LIMITED TO,PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 30 ** DATA,OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 31 ** THEORY OF LIABILITY,WHETHER IN CONTRACT,STRICT LIABILITY,OR TORT 32 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 33 ** THIS SOFTWARE,EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 ************************************************************************** 35 * $FreeBSD$ 36 */ 37 #define ARCMSR_SCSI_INITIATOR_ID 255 38 #define ARCMSR_DEV_SECTOR_SIZE 512 39 #define ARCMSR_MAX_XFER_SECTORS 4096 40 #define ARCMSR_MAX_TARGETID 17 /*16 max target id + 1*/ 41 #define ARCMSR_MAX_TARGETLUN 8 /*8*/ 42 #define ARCMSR_MAX_CHIPTYPE_NUM 4 43 #define ARCMSR_MAX_OUTSTANDING_CMD 256 44 #define ARCMSR_MAX_START_JOB 256 45 #define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_OUTSTANDING_CMD 46 #define ARCMSR_MAX_FREESRB_NUM 384 47 #define ARCMSR_MAX_QBUFFER 4096 /* ioctl QBUFFER */ 48 #define ARCMSR_MAX_SG_ENTRIES 38 /* max 38*/ 49 #define ARCMSR_MAX_ADAPTER 4 50 #define ARCMSR_RELEASE_SIMQ_LEVEL 230 51 #define ARCMSR_MAX_HBB_POSTQUEUE 264 /* (ARCMSR_MAX_OUTSTANDING_CMD+8) */ 52 #define ARCMSR_MAX_HBD_POSTQUEUE 256 53 #define ARCMSR_TIMEOUT_DELAY 60 /* in sec */ 54 /* 55 ********************************************************************* 56 */ 57 #ifndef TRUE 58 #define TRUE 1 59 #endif 60 #ifndef FALSE 61 #define FALSE 0 62 #endif 63 #ifndef INTR_ENTROPY 64 # define INTR_ENTROPY 0 65 #endif 66 67 #ifndef offsetof 68 #define offsetof(type, member) ((size_t)(&((type *)0)->member)) 69 #endif 70 71 #if __FreeBSD_version >= 500005 72 #define ARCMSR_LOCK_INIT(l, s) mtx_init(l, s, NULL, MTX_DEF) 73 #define ARCMSR_LOCK_DESTROY(l) mtx_destroy(l) 74 #define ARCMSR_LOCK_ACQUIRE(l) mtx_lock(l) 75 #define ARCMSR_LOCK_RELEASE(l) mtx_unlock(l) 76 #define ARCMSR_LOCK_TRY(l) mtx_trylock(l) 77 #define arcmsr_htole32(x) htole32(x) 78 typedef struct mtx arcmsr_lock_t; 79 #else 80 #define ARCMSR_LOCK_INIT(l, s) simple_lock_init(l) 81 #define ARCMSR_LOCK_DESTROY(l) 82 #define ARCMSR_LOCK_ACQUIRE(l) simple_lock(l) 83 #define ARCMSR_LOCK_RELEASE(l) simple_unlock(l) 84 #define ARCMSR_LOCK_TRY(l) simple_lock_try(l) 85 #define arcmsr_htole32(x) (x) 86 typedef struct simplelock arcmsr_lock_t; 87 #endif 88 89 /* 90 ********************************************************************************** 91 ** 92 ********************************************************************************** 93 */ 94 #define PCI_VENDOR_ID_ARECA 0x17D3 /* Vendor ID */ 95 #define PCI_DEVICE_ID_ARECA_1110 0x1110 /* Device ID */ 96 #define PCI_DEVICE_ID_ARECA_1120 0x1120 /* Device ID */ 97 #define PCI_DEVICE_ID_ARECA_1130 0x1130 /* Device ID */ 98 #define PCI_DEVICE_ID_ARECA_1160 0x1160 /* Device ID */ 99 #define PCI_DEVICE_ID_ARECA_1170 0x1170 /* Device ID */ 100 #define PCI_DEVICE_ID_ARECA_1200 0x1200 /* Device ID */ 101 #define PCI_DEVICE_ID_ARECA_1201 0x1201 /* Device ID */ 102 #define PCI_DEVICE_ID_ARECA_1210 0x1210 /* Device ID */ 103 #define PCI_DEVICE_ID_ARECA_1212 0x1212 /* Device ID */ 104 #define PCI_DEVICE_ID_ARECA_1214 0x1214 /* Device ID */ 105 #define PCI_DEVICE_ID_ARECA_1220 0x1220 /* Device ID */ 106 #define PCI_DEVICE_ID_ARECA_1222 0x1222 /* Device ID */ 107 #define PCI_DEVICE_ID_ARECA_1230 0x1230 /* Device ID */ 108 #define PCI_DEVICE_ID_ARECA_1231 0x1231 /* Device ID */ 109 #define PCI_DEVICE_ID_ARECA_1260 0x1260 /* Device ID */ 110 #define PCI_DEVICE_ID_ARECA_1261 0x1261 /* Device ID */ 111 #define PCI_DEVICE_ID_ARECA_1270 0x1270 /* Device ID */ 112 #define PCI_DEVICE_ID_ARECA_1280 0x1280 /* Device ID */ 113 #define PCI_DEVICE_ID_ARECA_1380 0x1380 /* Device ID */ 114 #define PCI_DEVICE_ID_ARECA_1381 0x1381 /* Device ID */ 115 #define PCI_DEVICE_ID_ARECA_1680 0x1680 /* Device ID */ 116 #define PCI_DEVICE_ID_ARECA_1681 0x1681 /* Device ID */ 117 #define PCI_DEVICE_ID_ARECA_1880 0x1880 /* Device ID */ 118 119 #define ARECA_SUB_DEV_ID_1880 0x1880 /* Subsystem Device ID */ 120 #define ARECA_SUB_DEV_ID_1882 0x1882 /* Subsystem Device ID */ 121 #define ARECA_SUB_DEV_ID_1212 0x1212 /* Subsystem Device ID */ 122 #define ARECA_SUB_DEV_ID_1213 0x1213 /* Subsystem Device ID */ 123 #define ARECA_SUB_DEV_ID_1222 0x1222 /* Subsystem Device ID */ 124 #define ARECA_SUB_DEV_ID_1223 0x1223 /* Subsystem Device ID */ 125 126 #define PCIDevVenIDARC1110 0x111017D3 /* Vendor Device ID */ 127 #define PCIDevVenIDARC1120 0x112017D3 /* Vendor Device ID */ 128 #define PCIDevVenIDARC1130 0x113017D3 /* Vendor Device ID */ 129 #define PCIDevVenIDARC1160 0x116017D3 /* Vendor Device ID */ 130 #define PCIDevVenIDARC1170 0x117017D3 /* Vendor Device ID */ 131 #define PCIDevVenIDARC1200 0x120017D3 /* Vendor Device ID */ 132 #define PCIDevVenIDARC1201 0x120117D3 /* Vendor Device ID */ 133 #define PCIDevVenIDARC1210 0x121017D3 /* Vendor Device ID */ 134 #define PCIDevVenIDARC1212 0x121217D3 /* Vendor Device ID */ 135 #define PCIDevVenIDARC1213 0x121317D3 /* Vendor Device ID */ 136 #define PCIDevVenIDARC1214 0x121417D3 /* Vendor Device ID */ 137 #define PCIDevVenIDARC1220 0x122017D3 /* Vendor Device ID */ 138 #define PCIDevVenIDARC1222 0x122217D3 /* Vendor Device ID */ 139 #define PCIDevVenIDARC1223 0x122317D3 /* Vendor Device ID */ 140 #define PCIDevVenIDARC1230 0x123017D3 /* Vendor Device ID */ 141 #define PCIDevVenIDARC1231 0x123117D3 /* Vendor Device ID */ 142 #define PCIDevVenIDARC1260 0x126017D3 /* Vendor Device ID */ 143 #define PCIDevVenIDARC1261 0x126117D3 /* Vendor Device ID */ 144 #define PCIDevVenIDARC1270 0x127017D3 /* Vendor Device ID */ 145 #define PCIDevVenIDARC1280 0x128017D3 /* Vendor Device ID */ 146 #define PCIDevVenIDARC1380 0x138017D3 /* Vendor Device ID */ 147 #define PCIDevVenIDARC1381 0x138117D3 /* Vendor Device ID */ 148 #define PCIDevVenIDARC1680 0x168017D3 /* Vendor Device ID */ 149 #define PCIDevVenIDARC1681 0x168117D3 /* Vendor Device ID */ 150 #define PCIDevVenIDARC1880 0x188017D3 /* Vendor Device ID */ 151 #define PCIDevVenIDARC1882 0x188217D3 /* Vendor Device ID */ 152 153 #ifndef PCIR_BARS 154 #define PCIR_BARS 0x10 155 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4) 156 #endif 157 158 #define PCI_BASE_ADDR0 0x10 159 #define PCI_BASE_ADDR1 0x14 160 #define PCI_BASE_ADDR2 0x18 161 #define PCI_BASE_ADDR3 0x1C 162 #define PCI_BASE_ADDR4 0x20 163 #define PCI_BASE_ADDR5 0x24 164 /* 165 ********************************************************************************** 166 ** 167 ********************************************************************************** 168 */ 169 #define ARCMSR_SCSICMD_IOCTL 0x77 170 #define ARCMSR_CDEVSW_IOCTL 0x88 171 #define ARCMSR_MESSAGE_FAIL 0x0001 172 #define ARCMSR_MESSAGE_SUCCESS 0x0000 173 /* 174 ********************************************************************************** 175 ** 176 ********************************************************************************** 177 */ 178 #define arcmsr_ccbsrb_ptr spriv_ptr0 179 #define arcmsr_ccbacb_ptr spriv_ptr1 180 #define dma_addr_hi32(addr) (u_int32_t) ((addr>>16)>>16) 181 #define dma_addr_lo32(addr) (u_int32_t) (addr & 0xffffffff) 182 #define get_min(x,y) ((x) < (y) ? (x) : (y)) 183 #define get_max(x,y) ((x) < (y) ? (y) : (x)) 184 /* 185 ************************************************************************** 186 ************************************************************************** 187 */ 188 #define CHIP_REG_READ32(s, b, r) bus_space_read_4(acb->btag[b], acb->bhandle[b], offsetof(struct s, r)) 189 #define CHIP_REG_WRITE32(s, b, r, d) bus_space_write_4(acb->btag[b], acb->bhandle[b], offsetof(struct s, r), d) 190 /* 191 ********************************************************************************** 192 ** IOCTL CONTROL Mail Box 193 ********************************************************************************** 194 */ 195 struct CMD_MESSAGE { 196 u_int32_t HeaderLength; 197 u_int8_t Signature[8]; 198 u_int32_t Timeout; 199 u_int32_t ControlCode; 200 u_int32_t ReturnCode; 201 u_int32_t Length; 202 }; 203 204 struct CMD_MESSAGE_FIELD { 205 struct CMD_MESSAGE cmdmessage; /* ioctl header */ 206 u_int8_t messagedatabuffer[1032]; /* areca gui program does not accept more than 1031 byte */ 207 }; 208 209 /************************************************************************/ 210 /************************************************************************/ 211 212 #define ARCMSR_IOP_ERROR_ILLEGALPCI 0x0001 213 #define ARCMSR_IOP_ERROR_VENDORID 0x0002 214 #define ARCMSR_IOP_ERROR_DEVICEID 0x0002 215 #define ARCMSR_IOP_ERROR_ILLEGALCDB 0x0003 216 #define ARCMSR_IOP_ERROR_UNKNOW_CDBERR 0x0004 217 #define ARCMSR_SYS_ERROR_MEMORY_ALLOCATE 0x0005 218 #define ARCMSR_SYS_ERROR_MEMORY_CROSS4G 0x0006 219 #define ARCMSR_SYS_ERROR_MEMORY_LACK 0x0007 220 #define ARCMSR_SYS_ERROR_MEMORY_RANGE 0x0008 221 #define ARCMSR_SYS_ERROR_DEVICE_BASE 0x0009 222 #define ARCMSR_SYS_ERROR_PORT_VALIDATE 0x000A 223 224 /*DeviceType*/ 225 #define ARECA_SATA_RAID 0x90000000 226 227 /*FunctionCode*/ 228 #define FUNCTION_READ_RQBUFFER 0x0801 229 #define FUNCTION_WRITE_WQBUFFER 0x0802 230 #define FUNCTION_CLEAR_RQBUFFER 0x0803 231 #define FUNCTION_CLEAR_WQBUFFER 0x0804 232 #define FUNCTION_CLEAR_ALLQBUFFER 0x0805 233 #define FUNCTION_REQUEST_RETURNCODE_3F 0x0806 234 #define FUNCTION_SAY_HELLO 0x0807 235 #define FUNCTION_SAY_GOODBYE 0x0808 236 #define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809 237 /* 238 ************************************************************************ 239 ** IOCTL CONTROL CODE 240 ************************************************************************ 241 */ 242 /* ARECA IO CONTROL CODE*/ 243 #define ARCMSR_MESSAGE_READ_RQBUFFER _IOWR('F', FUNCTION_READ_RQBUFFER, struct CMD_MESSAGE_FIELD) 244 #define ARCMSR_MESSAGE_WRITE_WQBUFFER _IOWR('F', FUNCTION_WRITE_WQBUFFER, struct CMD_MESSAGE_FIELD) 245 #define ARCMSR_MESSAGE_CLEAR_RQBUFFER _IOWR('F', FUNCTION_CLEAR_RQBUFFER, struct CMD_MESSAGE_FIELD) 246 #define ARCMSR_MESSAGE_CLEAR_WQBUFFER _IOWR('F', FUNCTION_CLEAR_WQBUFFER, struct CMD_MESSAGE_FIELD) 247 #define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER _IOWR('F', FUNCTION_CLEAR_ALLQBUFFER, struct CMD_MESSAGE_FIELD) 248 #define ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F _IOWR('F', FUNCTION_REQUEST_RETURNCODE_3F, struct CMD_MESSAGE_FIELD) 249 #define ARCMSR_MESSAGE_SAY_HELLO _IOWR('F', FUNCTION_SAY_HELLO, struct CMD_MESSAGE_FIELD) 250 #define ARCMSR_MESSAGE_SAY_GOODBYE _IOWR('F', FUNCTION_SAY_GOODBYE, struct CMD_MESSAGE_FIELD) 251 #define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE _IOWR('F', FUNCTION_FLUSH_ADAPTER_CACHE, struct CMD_MESSAGE_FIELD) 252 253 /* ARECA IOCTL ReturnCode */ 254 #define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001 255 #define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006 256 #define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F 257 #define ARCMSR_IOCTL_RETURNCODE_BUS_HANG_ON 0x00000088 258 /* 259 ************************************************************************ 260 ** SPEC. for Areca HBA adapter 261 ************************************************************************ 262 */ 263 /* signature of set and get firmware config */ 264 #define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060 265 #define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063 266 /* message code of inbound message register */ 267 #define ARCMSR_INBOUND_MESG0_NOP 0x00000000 268 #define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001 269 #define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002 270 #define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003 271 #define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004 272 #define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005 273 #define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006 274 #define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007 275 #define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008 276 /* doorbell interrupt generator */ 277 #define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001 278 #define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002 279 #define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001 280 #define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002 281 /* srb areca cdb flag */ 282 #define ARCMSR_SRBPOST_FLAG_SGL_BSIZE 0x80000000 283 #define ARCMSR_SRBPOST_FLAG_IAM_BIOS 0x40000000 284 #define ARCMSR_SRBREPLY_FLAG_IAM_BIOS 0x40000000 285 #define ARCMSR_SRBREPLY_FLAG_ERROR 0x10000000 286 #define ARCMSR_SRBREPLY_FLAG_ERROR_MODE0 0x10000000 287 #define ARCMSR_SRBREPLY_FLAG_ERROR_MODE1 0x00000001 288 /* outbound firmware ok */ 289 #define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000 290 291 #define ARCMSR_ARC1680_BUS_RESET 0x00000003 292 /* 293 ************************************************************************ 294 ** SPEC. for Areca HBB adapter 295 ************************************************************************ 296 */ 297 /* ARECA HBB COMMAND for its FIRMWARE */ 298 #define ARCMSR_DRV2IOP_DOORBELL 0x00020400 /* window of "instruction flags" from driver to iop */ 299 #define ARCMSR_DRV2IOP_DOORBELL_MASK 0x00020404 300 #define ARCMSR_IOP2DRV_DOORBELL 0x00020408 /* window of "instruction flags" from iop to driver */ 301 #define ARCMSR_IOP2DRV_DOORBELL_MASK 0x0002040C 302 303 /* ARECA FLAG LANGUAGE */ 304 #define ARCMSR_IOP2DRV_DATA_WRITE_OK 0x00000001 /* ioctl transfer */ 305 #define ARCMSR_IOP2DRV_DATA_READ_OK 0x00000002 /* ioctl transfer */ 306 #define ARCMSR_IOP2DRV_CDB_DONE 0x00000004 307 #define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 308 309 #define ARCMSR_DOORBELL_HANDLE_INT 0x0000000F 310 #define ARCMSR_DOORBELL_INT_CLEAR_PATTERN 0xFF00FFF0 311 #define ARCMSR_MESSAGE_INT_CLEAR_PATTERN 0xFF00FFF7 312 313 #define ARCMSR_MESSAGE_GET_CONFIG 0x00010008 /* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 314 #define ARCMSR_MESSAGE_SET_CONFIG 0x00020008 /* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 315 #define ARCMSR_MESSAGE_ABORT_CMD 0x00030008 /* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 316 #define ARCMSR_MESSAGE_STOP_BGRB 0x00040008 /* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 317 #define ARCMSR_MESSAGE_FLUSH_CACHE 0x00050008 /* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 318 #define ARCMSR_MESSAGE_START_BGRB 0x00060008 /* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 319 #define ARCMSR_MESSAGE_START_DRIVER_MODE 0x000E0008 320 #define ARCMSR_MESSAGE_SET_POST_WINDOW 0x000F0008 321 #define ARCMSR_MESSAGE_ACTIVE_EOI_MODE 0x00100008 322 #define ARCMSR_MESSAGE_FIRMWARE_OK 0x80000000 /* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */ 323 324 #define ARCMSR_DRV2IOP_DATA_WRITE_OK 0x00000001 /* ioctl transfer */ 325 #define ARCMSR_DRV2IOP_DATA_READ_OK 0x00000002 /* ioctl transfer */ 326 #define ARCMSR_DRV2IOP_CDB_POSTED 0x00000004 327 #define ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED 0x00000008 328 #define ARCMSR_DRV2IOP_END_OF_INTERRUPT 0x00000010 /* */ 329 330 /* data tunnel buffer between user space program and its firmware */ 331 #define ARCMSR_MSGCODE_RWBUFFER 0x0000fa00 /* iop msgcode_rwbuffer for message command */ 332 #define ARCMSR_IOCTL_WBUFFER 0x0000fe00 /* user space data to iop 128bytes */ 333 #define ARCMSR_IOCTL_RBUFFER 0x0000ff00 /* iop data to user space 128bytes */ 334 #define ARCMSR_HBB_BASE0_OFFSET 0x00000010 335 #define ARCMSR_HBB_BASE1_OFFSET 0x00000018 336 #define ARCMSR_HBB_BASE0_LEN 0x00021000 337 #define ARCMSR_HBB_BASE1_LEN 0x00010000 338 /* 339 ************************************************************************ 340 ** SPEC. for Areca HBC adapter 341 ************************************************************************ 342 */ 343 #define ARCMSR_HBC_ISR_THROTTLING_LEVEL 12 344 #define ARCMSR_HBC_ISR_MAX_DONE_QUEUE 20 345 /* Host Interrupt Mask */ 346 #define ARCMSR_HBCMU_UTILITY_A_ISR_MASK 0x00000001 /* When clear, the Utility_A interrupt routes to the host.*/ 347 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK 0x00000004 /* When clear, the General Outbound Doorbell interrupt routes to the host.*/ 348 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK 0x00000008 /* When clear, the Outbound Post List FIFO Not Empty interrupt routes to the host.*/ 349 #define ARCMSR_HBCMU_ALL_INTMASKENABLE 0x0000000D /* disable all ISR */ 350 /* Host Interrupt Status */ 351 #define ARCMSR_HBCMU_UTILITY_A_ISR 0x00000001 352 /* 353 ** Set when the Utility_A Interrupt bit is set in the Outbound Doorbell Register. 354 ** It clears by writing a 1 to the Utility_A bit in the Outbound Doorbell Clear Register or through automatic clearing (if enabled). 355 */ 356 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR 0x00000004 357 /* 358 ** Set if Outbound Doorbell register bits 30:1 have a non-zero 359 ** value. This bit clears only when Outbound Doorbell bits 360 ** 30:1 are ALL clear. Only a write to the Outbound Doorbell 361 ** Clear register clears bits in the Outbound Doorbell register. 362 */ 363 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR 0x00000008 364 /* 365 ** Set whenever the Outbound Post List Producer/Consumer 366 ** Register (FIFO) is not empty. It clears when the Outbound 367 ** Post List FIFO is empty. 368 */ 369 #define ARCMSR_HBCMU_SAS_ALL_INT 0x00000010 370 /* 371 ** This bit indicates a SAS interrupt from a source external to 372 ** the PCIe core. This bit is not maskable. 373 */ 374 /* DoorBell*/ 375 #define ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK 0x00000002/**/ 376 #define ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK 0x00000004/**/ 377 #define ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008/*inbound message 0 ready*/ 378 #define ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING 0x00000010/*more than 12 request completed in a time*/ 379 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK 0x00000002/**/ 380 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR 0x00000002/*outbound DATA WRITE isr door bell clear*/ 381 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK 0x00000004/**/ 382 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR 0x00000004/*outbound DATA READ isr door bell clear*/ 383 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008/*outbound message 0 ready*/ 384 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR 0x00000008/*outbound message cmd isr door bell clear*/ 385 #define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK 0x80000000/*ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK*/ 386 #define ARCMSR_HBCMU_RESET_ADAPTER 0x00000024 387 #define ARCMSR_HBCMU_DiagWrite_ENABLE 0x00000080 388 389 /* 390 ************************************************************************ 391 ** SPEC. for Areca HBD adapter 392 ************************************************************************ 393 */ 394 #define ARCMSR_HBDMU_CHIP_ID 0x00004 395 #define ARCMSR_HBDMU_CPU_MEMORY_CONFIGURATION 0x00008 396 #define ARCMSR_HBDMU_I2_HOST_INTERRUPT_MASK 0x00034 397 #define ARCMSR_HBDMU_MAIN_INTERRUPT_STATUS 0x00200 398 #define ARCMSR_HBDMU_PCIE_F0_INTERRUPT_ENABLE 0x0020C 399 #define ARCMSR_HBDMU_INBOUND_MESSAGE0 0x00400 400 #define ARCMSR_HBDMU_INBOUND_MESSAGE1 0x00404 401 #define ARCMSR_HBDMU_OUTBOUND_MESSAGE0 0x00420 402 #define ARCMSR_HBDMU_OUTBOUND_MESSAGE1 0x00424 403 #define ARCMSR_HBDMU_INBOUND_DOORBELL 0x00460 404 #define ARCMSR_HBDMU_OUTBOUND_DOORBELL 0x00480 405 #define ARCMSR_HBDMU_OUTBOUND_DOORBELL_ENABLE 0x00484 406 #define ARCMSR_HBDMU_INBOUND_LIST_BASE_LOW 0x01000 407 #define ARCMSR_HBDMU_INBOUND_LIST_BASE_HIGH 0x01004 408 #define ARCMSR_HBDMU_INBOUND_LIST_WRITE_POINTER 0x01018 409 #define ARCMSR_HBDMU_OUTBOUND_LIST_BASE_LOW 0x01060 410 #define ARCMSR_HBDMU_OUTBOUND_LIST_BASE_HIGH 0x01064 411 #define ARCMSR_HBDMU_OUTBOUND_LIST_COPY_POINTER 0x0106C 412 #define ARCMSR_HBDMU_OUTBOUND_LIST_READ_POINTER 0x01070 413 #define ARCMSR_HBDMU_OUTBOUND_INTERRUPT_CAUSE 0x01088 414 #define ARCMSR_HBDMU_OUTBOUND_INTERRUPT_ENABLE 0x0108C 415 416 #define ARCMSR_HBDMU_MESSAGE_WBUFFER 0x02000 417 #define ARCMSR_HBDMU_MESSAGE_RBUFFER 0x02100 418 #define ARCMSR_HBDMU_MESSAGE_RWBUFFER 0x02200 419 420 #define ARCMSR_HBDMU_ISR_THROTTLING_LEVEL 16 421 #define ARCMSR_HBDMU_ISR_MAX_DONE_QUEUE 20 422 423 /* Host Interrupt Mask */ 424 #define ARCMSR_HBDMU_ALL_INT_ENABLE 0x00001010 /* enable all ISR */ 425 #define ARCMSR_HBDMU_ALL_INT_DISABLE 0x00000000 /* disable all ISR */ 426 427 /* Host Interrupt Status */ 428 #define ARCMSR_HBDMU_OUTBOUND_INT 0x00001010 429 #define ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT 0x00001000 430 #define ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT 0x00000010 431 432 /* DoorBell*/ 433 #define ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY 0x00000001 434 #define ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ 0x00000002 435 436 #define ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK 0x00000001 437 #define ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK 0x00000002 438 439 /*outbound message 0 ready*/ 440 #define ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE 0x02000000 441 442 #define ARCMSR_HBDMU_F0_DOORBELL_CAUSE 0x02000003 443 444 /*outbound message cmd isr door bell clear*/ 445 #define ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR 0x02000000 446 447 /*outbound list */ 448 #define ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT 0x00000001 449 #define ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR 0x00000001 450 451 /*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/ 452 #define ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK 0x80000000 453 /* 454 ********************************************************************* 455 ** Message Unit structure 456 ********************************************************************* 457 */ 458 struct HBA_MessageUnit 459 { 460 u_int32_t resrved0[4]; /*0000 000F*/ 461 u_int32_t inbound_msgaddr0; /*0010 0013*/ 462 u_int32_t inbound_msgaddr1; /*0014 0017*/ 463 u_int32_t outbound_msgaddr0; /*0018 001B*/ 464 u_int32_t outbound_msgaddr1; /*001C 001F*/ 465 u_int32_t inbound_doorbell; /*0020 0023*/ 466 u_int32_t inbound_intstatus; /*0024 0027*/ 467 u_int32_t inbound_intmask; /*0028 002B*/ 468 u_int32_t outbound_doorbell; /*002C 002F*/ 469 u_int32_t outbound_intstatus; /*0030 0033*/ 470 u_int32_t outbound_intmask; /*0034 0037*/ 471 u_int32_t reserved1[2]; /*0038 003F*/ 472 u_int32_t inbound_queueport; /*0040 0043*/ 473 u_int32_t outbound_queueport; /*0044 0047*/ 474 u_int32_t reserved2[2]; /*0048 004F*/ 475 u_int32_t reserved3[492]; /*0050 07FF ......local_buffer 492*/ 476 u_int32_t reserved4[128]; /*0800 09FF 128*/ 477 u_int32_t msgcode_rwbuffer[256]; /*0a00 0DFF 256*/ 478 u_int32_t message_wbuffer[32]; /*0E00 0E7F 32*/ 479 u_int32_t reserved5[32]; /*0E80 0EFF 32*/ 480 u_int32_t message_rbuffer[32]; /*0F00 0F7F 32*/ 481 u_int32_t reserved6[32]; /*0F80 0FFF 32*/ 482 }; 483 /* 484 ********************************************************************* 485 ** 486 ********************************************************************* 487 */ 488 struct HBB_DOORBELL 489 { 490 u_int8_t doorbell_reserved[ARCMSR_DRV2IOP_DOORBELL]; /*reserved */ 491 u_int32_t drv2iop_doorbell; /*offset 0x00020400:00,01,02,03: window of "instruction flags" from driver to iop */ 492 u_int32_t drv2iop_doorbell_mask; /* 04,05,06,07: doorbell mask */ 493 u_int32_t iop2drv_doorbell; /* 08,09,10,11: window of "instruction flags" from iop to driver */ 494 u_int32_t iop2drv_doorbell_mask; /* 12,13,14,15: doorbell mask */ 495 }; 496 /* 497 ********************************************************************* 498 ** 499 ********************************************************************* 500 */ 501 struct HBB_RWBUFFER 502 { 503 u_int8_t message_reserved0[ARCMSR_MSGCODE_RWBUFFER]; /*reserved */ 504 u_int32_t msgcode_rwbuffer[256]; /*offset 0x0000fa00: 0, 1, 2, 3,...,1023: message code read write 1024bytes */ 505 u_int32_t message_wbuffer[32]; /*offset 0x0000fe00:1024,1025,1026,1027,...,1151: user space data to iop 128bytes */ 506 u_int32_t message_reserved1[32]; /* 1152,1153,1154,1155,...,1279: message reserved*/ 507 u_int32_t message_rbuffer[32]; /*offset 0x0000ff00:1280,1281,1282,1283,...,1407: iop data to user space 128bytes */ 508 }; 509 /* 510 ********************************************************************* 511 ** 512 ********************************************************************* 513 */ 514 struct HBB_MessageUnit 515 { 516 u_int32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* post queue buffer for iop */ 517 u_int32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* done queue buffer for iop */ 518 int32_t postq_index; /* post queue index */ 519 int32_t doneq_index; /* done queue index */ 520 struct HBB_DOORBELL *hbb_doorbell; 521 struct HBB_RWBUFFER *hbb_rwbuffer; 522 }; 523 524 /* 525 ********************************************************************* 526 ** 527 ********************************************************************* 528 */ 529 struct HBC_MessageUnit { 530 u_int32_t message_unit_status; /*0000 0003*/ 531 u_int32_t slave_error_attribute; /*0004 0007*/ 532 u_int32_t slave_error_address; /*0008 000B*/ 533 u_int32_t posted_outbound_doorbell; /*000C 000F*/ 534 u_int32_t master_error_attribute; /*0010 0013*/ 535 u_int32_t master_error_address_low; /*0014 0017*/ 536 u_int32_t master_error_address_high; /*0018 001B*/ 537 u_int32_t hcb_size; /*001C 001F size of the PCIe window used for HCB_Mode accesses*/ 538 u_int32_t inbound_doorbell; /*0020 0023*/ 539 u_int32_t diagnostic_rw_data; /*0024 0027*/ 540 u_int32_t diagnostic_rw_address_low; /*0028 002B*/ 541 u_int32_t diagnostic_rw_address_high; /*002C 002F*/ 542 u_int32_t host_int_status; /*0030 0033 host interrupt status*/ 543 u_int32_t host_int_mask; /*0034 0037 host interrupt mask*/ 544 u_int32_t dcr_data; /*0038 003B*/ 545 u_int32_t dcr_address; /*003C 003F*/ 546 u_int32_t inbound_queueport; /*0040 0043 port32 host inbound queue port*/ 547 u_int32_t outbound_queueport; /*0044 0047 port32 host outbound queue port*/ 548 u_int32_t hcb_pci_address_low; /*0048 004B*/ 549 u_int32_t hcb_pci_address_high; /*004C 004F*/ 550 u_int32_t iop_int_status; /*0050 0053*/ 551 u_int32_t iop_int_mask; /*0054 0057*/ 552 u_int32_t iop_inbound_queue_port; /*0058 005B*/ 553 u_int32_t iop_outbound_queue_port; /*005C 005F*/ 554 u_int32_t inbound_free_list_index; /*0060 0063 inbound free list producer consumer index*/ 555 u_int32_t inbound_post_list_index; /*0064 0067 inbound post list producer consumer index*/ 556 u_int32_t outbound_free_list_index; /*0068 006B outbound free list producer consumer index*/ 557 u_int32_t outbound_post_list_index; /*006C 006F outbound post list producer consumer index*/ 558 u_int32_t inbound_doorbell_clear; /*0070 0073*/ 559 u_int32_t i2o_message_unit_control; /*0074 0077*/ 560 u_int32_t last_used_message_source_address_low; /*0078 007B*/ 561 u_int32_t last_used_message_source_address_high; /*007C 007F*/ 562 u_int32_t pull_mode_data_byte_count[4]; /*0080 008F pull mode data byte count0..count7*/ 563 u_int32_t message_dest_address_index; /*0090 0093*/ 564 u_int32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/ 565 u_int32_t utility_A_int_counter_timer; /*0098 009B*/ 566 u_int32_t outbound_doorbell; /*009C 009F*/ 567 u_int32_t outbound_doorbell_clear; /*00A0 00A3*/ 568 u_int32_t message_source_address_index; /*00A4 00A7 message accelerator source address consumer producer index*/ 569 u_int32_t message_done_queue_index; /*00A8 00AB message accelerator completion queue consumer producer index*/ 570 u_int32_t reserved0; /*00AC 00AF*/ 571 u_int32_t inbound_msgaddr0; /*00B0 00B3 scratchpad0*/ 572 u_int32_t inbound_msgaddr1; /*00B4 00B7 scratchpad1*/ 573 u_int32_t outbound_msgaddr0; /*00B8 00BB scratchpad2*/ 574 u_int32_t outbound_msgaddr1; /*00BC 00BF scratchpad3*/ 575 u_int32_t inbound_queueport_low; /*00C0 00C3 port64 host inbound queue port low*/ 576 u_int32_t inbound_queueport_high; /*00C4 00C7 port64 host inbound queue port high*/ 577 u_int32_t outbound_queueport_low; /*00C8 00CB port64 host outbound queue port low*/ 578 u_int32_t outbound_queueport_high; /*00CC 00CF port64 host outbound queue port high*/ 579 u_int32_t iop_inbound_queue_port_low; /*00D0 00D3*/ 580 u_int32_t iop_inbound_queue_port_high; /*00D4 00D7*/ 581 u_int32_t iop_outbound_queue_port_low; /*00D8 00DB*/ 582 u_int32_t iop_outbound_queue_port_high; /*00DC 00DF*/ 583 u_int32_t message_dest_queue_port_low; /*00E0 00E3 message accelerator destination queue port low*/ 584 u_int32_t message_dest_queue_port_high; /*00E4 00E7 message accelerator destination queue port high*/ 585 u_int32_t last_used_message_dest_address_low; /*00E8 00EB last used message accelerator destination address low*/ 586 u_int32_t last_used_message_dest_address_high; /*00EC 00EF last used message accelerator destination address high*/ 587 u_int32_t message_done_queue_base_address_low; /*00F0 00F3 message accelerator completion queue base address low*/ 588 u_int32_t message_done_queue_base_address_high; /*00F4 00F7 message accelerator completion queue base address high*/ 589 u_int32_t host_diagnostic; /*00F8 00FB*/ 590 u_int32_t write_sequence; /*00FC 00FF*/ 591 u_int32_t reserved1[34]; /*0100 0187*/ 592 u_int32_t reserved2[1950]; /*0188 1FFF*/ 593 u_int32_t message_wbuffer[32]; /*2000 207F*/ 594 u_int32_t reserved3[32]; /*2080 20FF*/ 595 u_int32_t message_rbuffer[32]; /*2100 217F*/ 596 u_int32_t reserved4[32]; /*2180 21FF*/ 597 u_int32_t msgcode_rwbuffer[256]; /*2200 23FF*/ 598 }; 599 /* 600 ********************************************************************* 601 ** 602 ********************************************************************* 603 */ 604 struct InBound_SRB { 605 uint32_t addressLow; //pointer to SRB block 606 uint32_t addressHigh; 607 uint32_t length; // in DWORDs 608 uint32_t reserved0; 609 }; 610 611 struct OutBound_SRB { 612 uint32_t addressLow; //pointer to SRB block 613 uint32_t addressHigh; 614 }; 615 616 struct HBD_MessageUnit { 617 uint32_t reserved0; 618 uint32_t chip_id; //0x0004 619 uint32_t cpu_mem_config; //0x0008 620 uint32_t reserved1[10]; //0x000C 621 uint32_t i2o_host_interrupt_mask; //0x0034 622 uint32_t reserved2[114]; //0x0038 623 uint32_t host_int_status; //0x0200 624 uint32_t host_int_enable; //0x0204 625 uint32_t reserved3[1]; //0x0208 626 uint32_t pcief0_int_enable; //0x020C 627 uint32_t reserved4[124]; //0x0210 628 uint32_t inbound_msgaddr0; //0x0400 629 uint32_t inbound_msgaddr1; //0x0404 630 uint32_t reserved5[6]; //0x0408 631 uint32_t outbound_msgaddr0; //0x0420 632 uint32_t outbound_msgaddr1; //0x0424 633 uint32_t reserved6[14]; //0x0428 634 uint32_t inbound_doorbell; //0x0460 635 uint32_t reserved7[7]; //0x0464 636 uint32_t outbound_doorbell; //0x0480 637 uint32_t outbound_doorbell_enable; //0x0484 638 uint32_t reserved8[734]; //0x0488 639 uint32_t inboundlist_base_low; //0x1000 640 uint32_t inboundlist_base_high; //0x1004 641 uint32_t reserved9[4]; //0x1008 642 uint32_t inboundlist_write_pointer; //0x1018 643 uint32_t inboundlist_read_pointer; //0x101C 644 uint32_t reserved10[16]; //0x1020 645 uint32_t outboundlist_base_low; //0x1060 646 uint32_t outboundlist_base_high; //0x1064 647 uint32_t reserved11; //0x1068 648 uint32_t outboundlist_copy_pointer; //0x106C 649 uint32_t outboundlist_read_pointer; //0x1070 0x1072 650 uint32_t reserved12[5]; //0x1074 651 uint32_t outboundlist_interrupt_cause; //0x1088 652 uint32_t outboundlist_interrupt_enable; //0x108C 653 uint32_t reserved13[988]; //0x1090 654 uint32_t message_wbuffer[32]; //0x2000 655 uint32_t reserved14[32]; //0x2080 656 uint32_t message_rbuffer[32]; //0x2100 657 uint32_t reserved15[32]; //0x2180 658 uint32_t msgcode_rwbuffer[256]; //0x2200 659 }; 660 661 struct HBD_MessageUnit0 { 662 struct InBound_SRB post_qbuffer[ARCMSR_MAX_HBD_POSTQUEUE]; 663 struct OutBound_SRB done_qbuffer[ARCMSR_MAX_HBD_POSTQUEUE+1]; 664 uint16_t postq_index; 665 uint16_t doneq_index; 666 struct HBD_MessageUnit *phbdmu; 667 }; 668 669 /* 670 ********************************************************************* 671 ** 672 ********************************************************************* 673 */ 674 struct MessageUnit_UNION 675 { 676 union { 677 struct HBA_MessageUnit hbamu; 678 struct HBB_MessageUnit hbbmu; 679 struct HBC_MessageUnit hbcmu; 680 struct HBD_MessageUnit0 hbdmu; 681 } muu; 682 }; 683 /* 684 ************************************************************* 685 ** structure for holding DMA address data 686 ************************************************************* 687 */ 688 #define IS_SG64_ADDR 0x01000000 /* bit24 */ 689 /* 690 ************************************************************************************************ 691 ** ARECA FIRMWARE SPEC 692 ************************************************************************************************ 693 ** Usage of IOP331 adapter 694 ** (All In/Out is in IOP331's view) 695 ** 1. Message 0 --> InitThread message and retrun code 696 ** 2. Doorbell is used for RS-232 emulation 697 ** inDoorBell : bit0 -- data in ready (DRIVER DATA WRITE OK) 698 ** bit1 -- data out has been read (DRIVER DATA READ OK) 699 ** outDooeBell: bit0 -- data out ready (IOP331 DATA WRITE OK) 700 ** bit1 -- data in has been read (IOP331 DATA READ OK) 701 ** 3. Index Memory Usage 702 ** offset 0xf00 : for RS232 out (request buffer) 703 ** offset 0xe00 : for RS232 in (scratch buffer) 704 ** offset 0xa00 : for inbound message code msgcode_rwbuffer (driver send to IOP331) 705 ** offset 0xa00 : for outbound message code msgcode_rwbuffer (IOP331 send to driver) 706 ** 4. RS-232 emulation 707 ** Currently 128 byte buffer is used 708 ** 1st u_int32_t : Data length (1--124) 709 ** Byte 4--127 : Max 124 bytes of data 710 ** 5. PostQ 711 ** All SCSI Command must be sent through postQ: 712 ** (inbound queue port) Request frame must be 32 bytes aligned 713 ** # bit27--bit31 => flag for post ccb 714 ** # bit0--bit26 => real address (bit27--bit31) of post arcmsr_cdb 715 ** bit31 : 0 : 256 bytes frame 716 ** 1 : 512 bytes frame 717 ** bit30 : 0 : normal request 718 ** 1 : BIOS request 719 ** bit29 : reserved 720 ** bit28 : reserved 721 ** bit27 : reserved 722 ** ------------------------------------------------------------------------------- 723 ** (outbount queue port) Request reply 724 ** # bit27--bit31 => flag for reply 725 ** # bit0--bit26 => real address (bit27--bit31) of reply arcmsr_cdb 726 ** bit31 : must be 0 (for this type of reply) 727 ** bit30 : reserved for BIOS handshake 728 ** bit29 : reserved 729 ** bit28 : 0 : no error, ignore AdapStatus/DevStatus/SenseData 730 ** 1 : Error, error code in AdapStatus/DevStatus/SenseData 731 ** bit27 : reserved 732 ** 6. BIOS request 733 ** All BIOS request is the same with request from PostQ 734 ** Except : 735 ** Request frame is sent from configuration space 736 ** offset: 0x78 : Request Frame (bit30 == 1) 737 ** offset: 0x18 : writeonly to generate IRQ to IOP331 738 ** Completion of request: 739 ** (bit30 == 0, bit28==err flag) 740 ** 7. Definition of SGL entry (structure) 741 ** 8. Message1 Out - Diag Status Code (????) 742 ** 9. Message0 message code : 743 ** 0x00 : NOP 744 ** 0x01 : Get Config ->offset 0xa00 :for outbound message code msgcode_rwbuffer (IOP331 send to driver) 745 ** Signature 0x87974060(4) 746 ** Request len 0x00000200(4) 747 ** numbers of queue 0x00000100(4) 748 ** SDRAM Size 0x00000100(4)-->256 MB 749 ** IDE Channels 0x00000008(4) 750 ** vendor 40 bytes char 751 ** model 8 bytes char 752 ** FirmVer 16 bytes char 753 ** Device Map 16 bytes char 754 ** 755 ** FirmwareVersion DWORD <== Added for checking of new firmware capability 756 ** 0x02 : Set Config ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver send to IOP331) 757 ** Signature 0x87974063(4) 758 ** UPPER32 of Request Frame (4)-->Driver Only 759 ** 0x03 : Reset (Abort all queued Command) 760 ** 0x04 : Stop Background Activity 761 ** 0x05 : Flush Cache 762 ** 0x06 : Start Background Activity (re-start if background is halted) 763 ** 0x07 : Check If Host Command Pending (Novell May Need This Function) 764 ** 0x08 : Set controller time ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver to IOP331) 765 ** byte 0 : 0xaa <-- signature 766 ** byte 1 : 0x55 <-- signature 767 ** byte 2 : year (04) 768 ** byte 3 : month (1..12) 769 ** byte 4 : date (1..31) 770 ** byte 5 : hour (0..23) 771 ** byte 6 : minute (0..59) 772 ** byte 7 : second (0..59) 773 ** ********************************************************************************* 774 ** Porting Of LSI2108/2116 Based PCIE SAS/6G host raid adapter 775 ** ==> Difference from IOP348 776 ** <1> Message Register 0,1 (the same usage) Init Thread message and retrun code 777 ** Inbound Message 0 (inbound_msgaddr0) : at offset 0xB0 (Scratchpad0) for inbound message code msgcode_rwbuffer (driver send to IOP) 778 ** Inbound Message 1 (inbound_msgaddr1) : at offset 0xB4 (Scratchpad1) Out.... Diag Status Code 779 ** Outbound Message 0 (outbound_msgaddr0): at offset 0xB8 (Scratchpad3) Out.... Diag Status Code 780 ** Outbound Message 1 (outbound_msgaddr1): at offset 0xBC (Scratchpad2) for outbound message code msgcode_rwbuffer (IOP send to driver) 781 ** <A> use doorbell to generate interrupt 782 ** 783 ** inbound doorbell: bit3 -- inbound message 0 ready (driver to iop) 784 ** outbound doorbell: bit3 -- outbound message 0 ready (iop to driver) 785 ** 786 ** a. Message1: Out - Diag Status Code (????) 787 ** 788 ** b. Message0: message code 789 ** 0x00 : NOP 790 ** 0x01 : Get Config ->offset 0xB8 :for outbound message code msgcode_rwbuffer (IOP send to driver) 791 ** Signature 0x87974060(4) 792 ** Request len 0x00000200(4) 793 ** numbers of queue 0x00000100(4) 794 ** SDRAM Size 0x00000100(4)-->256 MB 795 ** IDE Channels 0x00000008(4) 796 ** vendor 40 bytes char 797 ** model 8 bytes char 798 ** FirmVer 16 bytes char 799 ** Device Map 16 bytes char 800 ** cfgVersion ULONG <== Added for checking of new firmware capability 801 ** 0x02 : Set Config ->offset 0xB0 :for inbound message code msgcode_rwbuffer (driver send to IOP) 802 ** Signature 0x87974063(4) 803 ** UPPER32 of Request Frame (4)-->Driver Only 804 ** 0x03 : Reset (Abort all queued Command) 805 ** 0x04 : Stop Background Activity 806 ** 0x05 : Flush Cache 807 ** 0x06 : Start Background Activity (re-start if background is halted) 808 ** 0x07 : Check If Host Command Pending (Novell May Need This Function) 809 ** 0x08 : Set controller time ->offset 0xB0 : for inbound message code msgcode_rwbuffer (driver to IOP) 810 ** byte 0 : 0xaa <-- signature 811 ** byte 1 : 0x55 <-- signature 812 ** byte 2 : year (04) 813 ** byte 3 : month (1..12) 814 ** byte 4 : date (1..31) 815 ** byte 5 : hour (0..23) 816 ** byte 6 : minute (0..59) 817 ** byte 7 : second (0..59) 818 ** 819 ** <2> Doorbell Register is used for RS-232 emulation 820 ** <A> different clear register 821 ** <B> different bit0 definition (bit0 is reserved) 822 ** 823 ** inbound doorbell : at offset 0x20 824 ** inbound doorbell clear : at offset 0x70 825 ** 826 ** inbound doorbell : bit0 -- reserved 827 ** bit1 -- data in ready (DRIVER DATA WRITE OK) 828 ** bit2 -- data out has been read (DRIVER DATA READ OK) 829 ** bit3 -- inbound message 0 ready 830 ** bit4 -- more than 12 request completed in a time 831 ** 832 ** outbound doorbell : at offset 0x9C 833 ** outbound doorbell clear : at offset 0xA0 834 ** 835 ** outbound doorbell : bit0 -- reserved 836 ** bit1 -- data out ready (IOP DATA WRITE OK) 837 ** bit2 -- data in has been read (IOP DATA READ OK) 838 ** bit3 -- outbound message 0 ready 839 ** 840 ** <3> Index Memory Usage (Buffer Area) 841 ** COMPORT_IN at 0x2000: message_wbuffer -- 128 bytes (to be sent to ROC) : for RS232 in (scratch buffer) 842 ** COMPORT_OUT at 0x2100: message_rbuffer -- 128 bytes (to be sent to host): for RS232 out (request buffer) 843 ** BIOS_CFG_AREA at 0x2200: msgcode_rwbuffer -- 1024 bytes for outbound message code msgcode_rwbuffer (IOP send to driver) 844 ** BIOS_CFG_AREA at 0x2200: msgcode_rwbuffer -- 1024 bytes for inbound message code msgcode_rwbuffer (driver send to IOP) 845 ** 846 ** <4> PostQ (Command Post Address) 847 ** All SCSI Command must be sent through postQ: 848 ** inbound queue port32 at offset 0x40 , 0x41, 0x42, 0x43 849 ** inbound queue port64 at offset 0xC0 (lower)/0xC4 (upper) 850 ** outbound queue port32 at offset 0x44 851 ** outbound queue port64 at offset 0xC8 (lower)/0xCC (upper) 852 ** <A> For 32bit queue, access low part is enough to send/receive request 853 ** i.e. write 0x40/0xC0, ROC will get the request with high part == 0, the 854 ** same for outbound queue port 855 ** <B> For 64bit queue, if 64bit instruction is supported, use 64bit instruction 856 ** to post inbound request in a single instruction, and use 64bit instruction 857 ** to retrieve outbound request in a single instruction. 858 ** If in 32bit environment, when sending inbound queue, write high part first 859 ** then write low part. For receiving outbound request, read high part first 860 ** then low part, to check queue empty, ONLY check high part to be 0xFFFFFFFF. 861 ** If high part is 0xFFFFFFFF, DO NOT read low part, this may corrupt the 862 ** consistency of the FIFO. Another way to check empty is to check status flag 863 ** at 0x30 bit3. 864 ** <C> Post Address IS NOT shifted (must be 16 bytes aligned) 865 ** For BIOS, 16bytes aligned is OK 866 ** For Driver, 32bytes alignment is recommended. 867 ** POST Command bit0 to bit3 is defined differently 868 ** ---------------------------- 869 ** bit0:1 for PULL mode (must be 1) 870 ** ---------------------------- 871 ** bit3/2/1: for arcmsr cdb size (arccdbsize) 872 ** 000: <= 0x0080 (128) 873 ** 001: <= 0x0100 (256) 874 ** 010: <= 0x0180 (384) 875 ** 011: <= 0x0200 (512) 876 ** 100: <= 0x0280 (640) 877 ** 101: <= 0x0300 (768) 878 ** 110: <= 0x0300 (reserved) 879 ** 111: <= 0x0300 (reserved) 880 ** ----------------------------- 881 ** if len > 0x300 the len always set as 0x300 882 ** ----------------------------- 883 ** post addr = addr | ((len-1) >> 6) | 1 884 ** ----------------------------- 885 ** page length in command buffer still required, 886 ** 887 ** if page length > 3, 888 ** firmware will assume more request data need to be retrieved 889 ** 890 ** <D> Outbound Posting 891 ** bit0:0 , no error, 1 with error, refer to status buffer 892 ** bit1:0 , reserved (will be 0) 893 ** bit2:0 , reserved (will be 0) 894 ** bit3:0 , reserved (will be 0) 895 ** bit63-4: Completed command address 896 ** 897 ** <E> BIOS support, no special support is required. 898 ** LSI2108 support I/O register 899 ** All driver functionality is supported through I/O address 900 ** 901 ************************************************************************************************ 902 */ 903 /* 904 ********************************** 905 ** 906 ********************************** 907 */ 908 /* size 8 bytes */ 909 /* 32bit Scatter-Gather list */ 910 struct SG32ENTRY { /* length bit 24 == 0 */ 911 u_int32_t length; /* high 8 bit == flag,low 24 bit == length */ 912 u_int32_t address; 913 }; 914 /* size 12 bytes */ 915 /* 64bit Scatter-Gather list */ 916 struct SG64ENTRY { /* length bit 24 == 1 */ 917 u_int32_t length; /* high 8 bit == flag,low 24 bit == length */ 918 u_int32_t address; 919 u_int32_t addresshigh; 920 }; 921 struct SGENTRY_UNION { 922 union { 923 struct SG32ENTRY sg32entry; /* 30h Scatter gather address */ 924 struct SG64ENTRY sg64entry; /* 30h */ 925 }u; 926 }; 927 /* 928 ********************************** 929 ** 930 ********************************** 931 */ 932 struct QBUFFER { 933 u_int32_t data_len; 934 u_int8_t data[124]; 935 }; 936 /* 937 ********************************** 938 */ 939 typedef struct PHYS_ADDR64 { 940 u_int32_t phyadd_low; 941 u_int32_t phyadd_high; 942 }PHYSADDR64; 943 /* 944 ************************************************************************************************ 945 ** FIRMWARE INFO 946 ************************************************************************************************ 947 */ 948 #define ARCMSR_FW_MODEL_OFFSET 15 949 #define ARCMSR_FW_VERS_OFFSET 17 950 #define ARCMSR_FW_DEVMAP_OFFSET 21 951 #define ARCMSR_FW_CFGVER_OFFSET 25 952 953 struct FIRMWARE_INFO { 954 u_int32_t signature; /*0,00-03*/ 955 u_int32_t request_len; /*1,04-07*/ 956 u_int32_t numbers_queue; /*2,08-11*/ 957 u_int32_t sdram_size; /*3,12-15*/ 958 u_int32_t ide_channels; /*4,16-19*/ 959 char vendor[40]; /*5,20-59*/ 960 char model[8]; /*15,60-67*/ 961 char firmware_ver[16]; /*17,68-83*/ 962 char device_map[16]; /*21,84-99*/ 963 u_int32_t cfgVersion; /*25,100-103 Added for checking of new firmware capability*/ 964 char cfgSerial[16]; /*26,104-119*/ 965 u_int32_t cfgPicStatus; /*30,120-123*/ 966 }; 967 /* (A) For cfgVersion in FIRMWARE_INFO 968 ** if low BYTE (byte#0) >= 3 (version 3) 969 ** then byte#1 report the capability of the firmware can xfer in a single request 970 ** 971 ** byte#1 972 ** 0 256K 973 ** 1 512K 974 ** 2 1M 975 ** 3 2M 976 ** 4 4M 977 ** 5 8M 978 ** 6 16M 979 ** (B) Byte offset 7 (Reserved1) of CDB is changed to msgPages 980 ** Driver support new xfer method need to set this field to indicate 981 ** large CDB block in 0x100 unit (we use 0x100 byte as one page) 982 ** e.g. If the length of CDB including MSG header and SGL is 0x1508 983 ** driver need to set the msgPages to 0x16 984 ** (C) REQ_LEN_512BYTE must be used also to indicate SRB length 985 ** e.g. CDB len msgPages REQ_LEN_512BYTE flag 986 ** <= 0x100 1 0 987 ** <= 0x200 2 1 988 ** <= 0x300 3 1 989 ** <= 0x400 4 1 990 ** . 991 ** . 992 */ 993 994 /* 995 ************************************************************************************************ 996 ** size 0x1F8 (504) 997 ************************************************************************************************ 998 */ 999 struct ARCMSR_CDB { 1000 u_int8_t Bus; /* 00h should be 0 */ 1001 u_int8_t TargetID; /* 01h should be 0--15 */ 1002 u_int8_t LUN; /* 02h should be 0--7 */ 1003 u_int8_t Function; /* 03h should be 1 */ 1004 1005 u_int8_t CdbLength; /* 04h not used now */ 1006 u_int8_t sgcount; /* 05h */ 1007 u_int8_t Flags; /* 06h */ 1008 u_int8_t msgPages; /* 07h */ 1009 1010 u_int32_t Context; /* 08h Address of this request */ 1011 u_int32_t DataLength; /* 0ch not used now */ 1012 1013 u_int8_t Cdb[16]; /* 10h SCSI CDB */ 1014 /* 1015 ******************************************************** 1016 ** Device Status : the same from SCSI bus if error occur 1017 ** SCSI bus status codes. 1018 ******************************************************** 1019 */ 1020 u_int8_t DeviceStatus; /* 20h if error */ 1021 1022 u_int8_t SenseData[15]; /* 21h output */ 1023 1024 union { 1025 struct SG32ENTRY sg32entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h Scatter gather address */ 1026 struct SG64ENTRY sg64entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h */ 1027 } u; 1028 }; 1029 /* CDB flag */ 1030 #define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01 /* bit 0: 0(256) / 1(512) bytes */ 1031 #define ARCMSR_CDB_FLAG_BIOS 0x02 /* bit 1: 0(from driver) / 1(from BIOS) */ 1032 #define ARCMSR_CDB_FLAG_WRITE 0x04 /* bit 2: 0(Data in) / 1(Data out) */ 1033 #define ARCMSR_CDB_FLAG_SIMPLEQ 0x00 /* bit 4/3 ,00 : simple Q,01 : head of Q,10 : ordered Q */ 1034 #define ARCMSR_CDB_FLAG_HEADQ 0x08 1035 #define ARCMSR_CDB_FLAG_ORDEREDQ 0x10 1036 /* scsi status */ 1037 #define SCSISTAT_GOOD 0x00 1038 #define SCSISTAT_CHECK_CONDITION 0x02 1039 #define SCSISTAT_CONDITION_MET 0x04 1040 #define SCSISTAT_BUSY 0x08 1041 #define SCSISTAT_INTERMEDIATE 0x10 1042 #define SCSISTAT_INTERMEDIATE_COND_MET 0x14 1043 #define SCSISTAT_RESERVATION_CONFLICT 0x18 1044 #define SCSISTAT_COMMAND_TERMINATED 0x22 1045 #define SCSISTAT_QUEUE_FULL 0x28 1046 /* DeviceStatus */ 1047 #define ARCMSR_DEV_SELECT_TIMEOUT 0xF0 1048 #define ARCMSR_DEV_ABORTED 0xF1 1049 #define ARCMSR_DEV_INIT_FAIL 0xF2 1050 /* 1051 ********************************************************************* 1052 ** Command Control Block (SrbExtension) 1053 ** SRB must be not cross page boundary,and the order from offset 0 1054 ** structure describing an ATA disk request 1055 ** this SRB length must be 32 bytes boundary 1056 ********************************************************************* 1057 */ 1058 struct CommandControlBlock { 1059 struct ARCMSR_CDB arcmsr_cdb; /* 0 -503 (size of CDB=504): arcmsr messenger scsi command descriptor size 504 bytes */ 1060 u_int32_t cdb_phyaddr_low; /* 504-507 */ 1061 u_int32_t arc_cdb_size; /* 508-511 */ 1062 /* ======================512+32 bytes============================ */ 1063 union ccb *pccb; /* 512-515 516-519 pointer of freebsd scsi command */ 1064 struct AdapterControlBlock *acb; /* 520-523 524-527 */ 1065 bus_dmamap_t dm_segs_dmamap; /* 528-531 532-535 */ 1066 u_int16_t srb_flags; /* 536-537 */ 1067 u_int16_t srb_state; /* 538-539 */ 1068 u_int32_t cdb_phyaddr_high; /* 540-543 */ 1069 struct callout ccb_callout; 1070 /* ========================================================== */ 1071 }; 1072 /* srb_flags */ 1073 #define SRB_FLAG_READ 0x0000 1074 #define SRB_FLAG_WRITE 0x0001 1075 #define SRB_FLAG_ERROR 0x0002 1076 #define SRB_FLAG_FLUSHCACHE 0x0004 1077 #define SRB_FLAG_MASTER_ABORTED 0x0008 1078 #define SRB_FLAG_DMAVALID 0x0010 1079 #define SRB_FLAG_DMACONSISTENT 0x0020 1080 #define SRB_FLAG_DMAWRITE 0x0040 1081 #define SRB_FLAG_PKTBIND 0x0080 1082 #define SRB_FLAG_TIMER_START 0x0080 1083 /* srb_state */ 1084 #define ARCMSR_SRB_DONE 0x0000 1085 #define ARCMSR_SRB_UNBUILD 0x0000 1086 #define ARCMSR_SRB_TIMEOUT 0x1111 1087 #define ARCMSR_SRB_RETRY 0x2222 1088 #define ARCMSR_SRB_START 0x55AA 1089 #define ARCMSR_SRB_PENDING 0xAA55 1090 #define ARCMSR_SRB_RESET 0xA5A5 1091 #define ARCMSR_SRB_ABORTED 0x5A5A 1092 #define ARCMSR_SRB_ILLEGAL 0xFFFF 1093 1094 #define SRB_SIZE ((sizeof(struct CommandControlBlock)+0x1f) & 0xffe0) 1095 #define ARCMSR_SRBS_POOL_SIZE (SRB_SIZE * ARCMSR_MAX_FREESRB_NUM) 1096 1097 /* 1098 ********************************************************************* 1099 ** Adapter Control Block 1100 ********************************************************************* 1101 */ 1102 #define ACB_ADAPTER_TYPE_A 0x00000001 /* hba I IOP */ 1103 #define ACB_ADAPTER_TYPE_B 0x00000002 /* hbb M IOP */ 1104 #define ACB_ADAPTER_TYPE_C 0x00000004 /* hbc L IOP */ 1105 #define ACB_ADAPTER_TYPE_D 0x00000008 /* hbd M IOP */ 1106 1107 struct AdapterControlBlock { 1108 u_int32_t adapter_type; /* adapter A,B..... */ 1109 1110 bus_space_tag_t btag[2]; 1111 bus_space_handle_t bhandle[2]; 1112 bus_dma_tag_t parent_dmat; 1113 bus_dma_tag_t dm_segs_dmat; /* dmat for buffer I/O */ 1114 bus_dma_tag_t srb_dmat; /* dmat for freesrb */ 1115 bus_dmamap_t srb_dmamap; 1116 device_t pci_dev; 1117 #if __FreeBSD_version < 503000 1118 dev_t ioctl_dev; 1119 #else 1120 struct cdev *ioctl_dev; 1121 #endif 1122 int pci_unit; 1123 1124 struct resource *sys_res_arcmsr[2]; 1125 struct resource *irqres; 1126 void *ih; /* interrupt handle */ 1127 1128 /* Hooks into the CAM XPT */ 1129 struct cam_sim *psim; 1130 struct cam_path *ppath; 1131 u_int8_t *uncacheptr; 1132 unsigned long vir2phy_offset; 1133 union { 1134 unsigned long phyaddr; 1135 struct { 1136 u_int32_t phyadd_low; 1137 u_int32_t phyadd_high; 1138 }B; 1139 } srb_phyaddr; 1140 // unsigned long srb_phyaddr; 1141 /* Offset is used in making arc cdb physical to virtual calculations */ 1142 u_int32_t outbound_int_enable; 1143 1144 struct MessageUnit_UNION *pmu; /* message unit ATU inbound base address0 */ 1145 1146 u_int8_t adapter_index; /* */ 1147 u_int8_t irq; 1148 u_int16_t acb_flags; /* */ 1149 1150 struct CommandControlBlock *psrb_pool[ARCMSR_MAX_FREESRB_NUM]; /* serial srb pointer array */ 1151 struct CommandControlBlock *srbworkingQ[ARCMSR_MAX_FREESRB_NUM]; /* working srb pointer array */ 1152 int32_t workingsrb_doneindex; /* done srb array index */ 1153 int32_t workingsrb_startindex; /* start srb array index */ 1154 int32_t srboutstandingcount; 1155 1156 u_int8_t rqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for read from 80331 */ 1157 u_int32_t rqbuf_firstindex; /* first of read buffer */ 1158 u_int32_t rqbuf_lastindex; /* last of read buffer */ 1159 1160 u_int8_t wqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for write to 80331 */ 1161 u_int32_t wqbuf_firstindex; /* first of write buffer */ 1162 u_int32_t wqbuf_lastindex; /* last of write buffer */ 1163 1164 arcmsr_lock_t isr_lock; 1165 arcmsr_lock_t srb_lock; 1166 arcmsr_lock_t postDone_lock; 1167 arcmsr_lock_t qbuffer_lock; 1168 1169 u_int8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN]; /* id0 ..... id15,lun0...lun7 */ 1170 u_int32_t num_resets; 1171 u_int32_t num_aborts; 1172 u_int32_t firm_request_len; /*1,04-07*/ 1173 u_int32_t firm_numbers_queue; /*2,08-11*/ 1174 u_int32_t firm_sdram_size; /*3,12-15*/ 1175 u_int32_t firm_ide_channels; /*4,16-19*/ 1176 u_int32_t firm_cfg_version; 1177 char firm_model[12]; /*15,60-67*/ 1178 char firm_version[20]; /*17,68-83*/ 1179 char device_map[20]; /*21,84-99 */ 1180 struct callout devmap_callout; 1181 u_int32_t pktRequestCount; 1182 u_int32_t pktReturnCount; 1183 u_int32_t vendor_device_id; 1184 u_int32_t adapter_bus_speed; 1185 };/* HW_DEVICE_EXTENSION */ 1186 /* acb_flags */ 1187 #define ACB_F_SCSISTOPADAPTER 0x0001 1188 #define ACB_F_MSG_STOP_BGRB 0x0002 /* stop RAID background rebuild */ 1189 #define ACB_F_MSG_START_BGRB 0x0004 /* stop RAID background rebuild */ 1190 #define ACB_F_IOPDATA_OVERFLOW 0x0008 /* iop ioctl data rqbuffer overflow */ 1191 #define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010 /* ioctl clear wqbuffer */ 1192 #define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020 /* ioctl clear rqbuffer */ 1193 #define ACB_F_MESSAGE_WQBUFFER_READ 0x0040 1194 #define ACB_F_BUS_RESET 0x0080 1195 #define ACB_F_IOP_INITED 0x0100 /* iop init */ 1196 #define ACB_F_MAPFREESRB_FAILD 0x0200 /* arcmsr_map_freesrb faild */ 1197 #define ACB_F_CAM_DEV_QFRZN 0x0400 1198 #define ACB_F_BUS_HANG_ON 0x0800 /* need hardware reset bus */ 1199 #define ACB_F_SRB_FUNCTION_POWER 0x1000 1200 /* devstate */ 1201 #define ARECA_RAID_GONE 0x55 1202 #define ARECA_RAID_GOOD 0xaa 1203 /* adapter_bus_speed */ 1204 #define ACB_BUS_SPEED_3G 0 1205 #define ACB_BUS_SPEED_6G 1 1206 #define ACB_BUS_SPEED_12G 2 1207 /* 1208 ************************************************************* 1209 ************************************************************* 1210 */ 1211 struct SENSE_DATA { 1212 u_int8_t ErrorCode:7; 1213 u_int8_t Valid:1; 1214 u_int8_t SegmentNumber; 1215 u_int8_t SenseKey:4; 1216 u_int8_t Reserved:1; 1217 u_int8_t IncorrectLength:1; 1218 u_int8_t EndOfMedia:1; 1219 u_int8_t FileMark:1; 1220 u_int8_t Information[4]; 1221 u_int8_t AdditionalSenseLength; 1222 u_int8_t CommandSpecificInformation[4]; 1223 u_int8_t AdditionalSenseCode; 1224 u_int8_t AdditionalSenseCodeQualifier; 1225 u_int8_t FieldReplaceableUnitCode; 1226 u_int8_t SenseKeySpecific[3]; 1227 }; 1228 /* 1229 ********************************** 1230 ** Peripheral Device Type definitions 1231 ********************************** 1232 */ 1233 #define SCSI_DASD 0x00 /* Direct-access Device */ 1234 #define SCSI_SEQACESS 0x01 /* Sequential-access device */ 1235 #define SCSI_PRINTER 0x02 /* Printer device */ 1236 #define SCSI_PROCESSOR 0x03 /* Processor device */ 1237 #define SCSI_WRITEONCE 0x04 /* Write-once device */ 1238 #define SCSI_CDROM 0x05 /* CD-ROM device */ 1239 #define SCSI_SCANNER 0x06 /* Scanner device */ 1240 #define SCSI_OPTICAL 0x07 /* Optical memory device */ 1241 #define SCSI_MEDCHGR 0x08 /* Medium changer device */ 1242 #define SCSI_COMM 0x09 /* Communications device */ 1243 #define SCSI_NODEV 0x1F /* Unknown or no device type */ 1244 /* 1245 ************************************************************************************************************ 1246 ** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 1247 ** 80331 PCI-to-PCI Bridge 1248 ** PCI Configuration Space 1249 ** 1250 ** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 1251 ** Programming Interface 1252 ** ======================== 1253 ** Configuration Register Address Space Groupings and Ranges 1254 ** ============================================================= 1255 ** Register Group Configuration Offset 1256 ** ------------------------------------------------------------- 1257 ** Standard PCI Configuration 00-3Fh 1258 ** ------------------------------------------------------------- 1259 ** Device Specific Registers 40-A7h 1260 ** ------------------------------------------------------------- 1261 ** Reserved A8-CBh 1262 ** ------------------------------------------------------------- 1263 ** Enhanced Capability List CC-FFh 1264 ** ========================================================================================================== 1265 ** Standard PCI [Type 1] Configuration Space Address Map 1266 ** ********************************************************************************************************** 1267 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 1268 ** ---------------------------------------------------------------------------------------------------------- 1269 ** | Device ID | Vendor ID | 00h 1270 ** ---------------------------------------------------------------------------------------------------------- 1271 ** | Primary Status | Primary Command | 04h 1272 ** ---------------------------------------------------------------------------------------------------------- 1273 ** | Class Code | RevID | 08h 1274 ** ---------------------------------------------------------------------------------------------------------- 1275 ** | reserved | Header Type | Primary MLT | Primary CLS | 0Ch 1276 ** ---------------------------------------------------------------------------------------------------------- 1277 ** | Reserved | 10h 1278 ** ---------------------------------------------------------------------------------------------------------- 1279 ** | Reserved | 14h 1280 ** ---------------------------------------------------------------------------------------------------------- 1281 ** | Secondary MLT | Subordinate Bus Number | Secondary Bus Number | Primary Bus Number | 18h 1282 ** ---------------------------------------------------------------------------------------------------------- 1283 ** | Secondary Status | I/O Limit | I/O Base | 1Ch 1284 ** ---------------------------------------------------------------------------------------------------------- 1285 ** | Non-prefetchable Memory Limit Address | Non-prefetchable Memory Base Address | 20h 1286 ** ---------------------------------------------------------------------------------------------------------- 1287 ** | Prefetchable Memory Limit Address | Prefetchable Memory Base Address | 24h 1288 ** ---------------------------------------------------------------------------------------------------------- 1289 ** | Prefetchable Memory Base Address Upper 32 Bits | 28h 1290 ** ---------------------------------------------------------------------------------------------------------- 1291 ** | Prefetchable Memory Limit Address Upper 32 Bits | 2Ch 1292 ** ---------------------------------------------------------------------------------------------------------- 1293 ** | I/O Limit Upper 16 Bits | I/O Base Upper 16 | 30h 1294 ** ---------------------------------------------------------------------------------------------------------- 1295 ** | Reserved | Capabilities Pointer | 34h 1296 ** ---------------------------------------------------------------------------------------------------------- 1297 ** | Reserved | 38h 1298 ** ---------------------------------------------------------------------------------------------------------- 1299 ** | Bridge Control | Primary Interrupt Pin | Primary Interrupt Line | 3Ch 1300 **============================================================================================================= 1301 */ 1302 /* 1303 **============================================================================================================= 1304 ** 0x03-0x00 : 1305 ** Bit Default Description 1306 **31:16 0335h Device ID (DID): Indicates the unique device ID that is assigned to bridge by the PCI SIG. 1307 ** ID is unique per product speed as indicated. 1308 **15:00 8086h Vendor ID (VID): 16-bit field which indicates that Intel is the vendor. 1309 **============================================================================================================= 1310 */ 1311 #define ARCMSR_PCI2PCI_VENDORID_REG 0x00 /*word*/ 1312 #define ARCMSR_PCI2PCI_DEVICEID_REG 0x02 /*word*/ 1313 /* 1314 **============================================================================== 1315 ** 0x05-0x04 : command register 1316 ** Bit Default Description 1317 **15:11 00h Reserved 1318 ** 10 0 Interrupt Disable: Disables/Enables the generation of Interrupts on the primary bus. 1319 ** The bridge does not support interrupts. 1320 ** 09 0 FB2B Enable: Enables/Disables the generation of fast back to back 1321 ** transactions on the primary bus. 1322 ** The bridge does not generate fast back to back 1323 ** transactions on the primary bus. 1324 ** 08 0 SERR# Enable (SEE): Enables primary bus SERR# assertions. 1325 ** 0=The bridge does not assert P_SERR#. 1326 ** 1=The bridge may assert P_SERR#, subject to other programmable criteria. 1327 ** 07 0 Wait Cycle Control (WCC): Always returns 0bzero indicating 1328 ** that bridge does not perform address or data stepping, 1329 ** 06 0 Parity Error Response (PER): Controls bridge response to a detected primary bus parity error. 1330 ** 0=When a data parity error is detected bridge does not assert S_PERR#. 1331 ** Also bridge does not assert P_SERR# in response to 1332 ** a detected address or attribute parity error. 1333 ** 1=When a data parity error is detected bridge asserts S_PERR#. 1334 ** The bridge also asserts P_SERR# 1335 ** (when enabled globally via bit(8) of this register) 1336 ** in response to a detected address or attribute parity error. 1337 ** 05 0 VGA Palette Snoop Enable (VGA_PSE): Controls bridge response to VGA-compatible palette write transactions. 1338 ** VGA palette write transactions are I/O transactions 1339 ** whose address bits are: P_AD[9:0] equal to 3C6h, 3C8h or 3C9h 1340 ** P_AD[15:10] are not decoded (i.e. aliases are claimed), 1341 ** or are fully decoding 1342 ** (i.e., must be all 0's depending upon the VGA 1343 ** aliasing bit in the Bridge Control Register, offset 3Eh. 1344 ** P_AD[31:16] equal to 0000h 1345 ** 0=The bridge ignores VGA palette write transactions, 1346 ** unless decoded by the standard I/O address range window. 1347 ** 1=The bridge responds to VGA palette write transactions 1348 ** with medium DEVSEL# timing and forwards them to the secondary bus. 1349 ** 04 0 Memory Write and Invalidate Enable (MWIE): The bridge does not promote MW transactions to MWI transactions. 1350 ** MWI transactions targeting resources on the opposite side of the bridge, 1351 ** however, are forwarded as MWI transactions. 1352 ** 03 0 Special Cycle Enable (SCE): The bridge ignores special cycle transactions. 1353 ** This bit is read only and always returns 0 when read 1354 ** 02 0 Bus Master Enable (BME): Enables bridge to initiate memory and I/O transactions on the primary interface. 1355 ** Initiation of configuration transactions is not affected by the state of this bit. 1356 ** 0=The bridge does not initiate memory or I/O transactions on the primary interface. 1357 ** 1=The bridge is enabled to function as an initiator on the primary interface. 1358 ** 01 0 Memory Space Enable (MSE): Controls target response to memory transactions on the primary interface. 1359 ** 0=The bridge target response to memory transactions on the primary interface is disabled. 1360 ** 1=The bridge target response to memory transactions on the primary interface is enabled. 1361 ** 00 0 I/O Space Enable (IOSE): Controls target response to I/O transactions on the primary interface. 1362 ** 0=The bridge target response to I/O transactions on the primary interface is disabled. 1363 ** 1=The bridge target response to I/O transactions on the primary interface is enabled. 1364 **============================================================================== 1365 */ 1366 #define ARCMSR_PCI2PCI_PRIMARY_COMMAND_REG 0x04 /*word*/ 1367 #define PCI_DISABLE_INTERRUPT 0x0400 1368 /* 1369 **============================================================================== 1370 ** 0x07-0x06 : status register 1371 ** Bit Default Description 1372 ** 15 0 Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address, 1373 ** attribute or data parity error. 1374 ** This bit is set regardless of the state of the PER bit in the command register. 1375 ** 14 0 Signaled System Error: The bridge sets this bit to a 1b whenever it asserts SERR# on the primary bus. 1376 ** 13 0 Received Master Abort: The bridge sets this bit to a 1b when, 1377 ** acting as the initiator on the primary bus, 1378 ** its transaction (with the exception of special cycles) 1379 ** has been terminated with a Master Abort. 1380 ** 12 0 Received Target Abort: The bridge sets this bit to a 1b when, 1381 ** acting as the initiator on the primary bus, 1382 ** its transaction has been terminated with a Target Abort. 1383 ** 11 0 Signaled Target Abort: The bridge sets this bit to a 1b when it, 1384 ** as the target of a transaction, terminates it with a Target Abort. 1385 ** In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code. 1386 ** 10:09 01 DEVSEL# Timing: Indicates slowest response to a non-configuration command on the primary interface. 1387 ** Returns ��01b�� when read, indicating that bridge responds no slower than with medium timing. 1388 ** 08 0 Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true: 1389 ** The bridge is the current master on the primary bus 1390 ** S_PERR# is detected asserted or is asserted by bridge 1391 ** The Parity Error Response bit is set in the Command register 1392 ** 07 1 Fast Back to Back Capable: Returns a 1b when read indicating that bridge 1393 ** is able to respond to fast back to back transactions on its primary interface. 1394 ** 06 0 Reserved 1395 ** 05 1 66 MHz Capable Indication: Returns a 1b when read indicating that bridge primary interface is 66 MHz capable. 1396 ** 1 = 1397 ** 04 1 Capabilities List Enable: Returns 1b when read indicating that bridge supports PCI standard enhanced capabilities. 1398 ** Offset 34h (Capability Pointer register) 1399 ** provides the offset for the first entry 1400 ** in the linked list of enhanced capabilities. 1401 ** 03 0 Interrupt Status: Reflects the state of the interrupt in the device/function. 1402 ** The bridge does not support interrupts. 1403 ** 02:00 000 Reserved 1404 **============================================================================== 1405 */ 1406 #define ARCMSR_PCI2PCI_PRIMARY_STATUS_REG 0x06 /*word: 06,07 */ 1407 #define ARCMSR_ADAP_66MHZ 0x20 1408 /* 1409 **============================================================================== 1410 ** 0x08 : revision ID 1411 ** Bit Default Description 1412 ** 07:00 00000000 Revision ID (RID): '00h' indicating bridge A-0 stepping. 1413 **============================================================================== 1414 */ 1415 #define ARCMSR_PCI2PCI_REVISIONID_REG 0x08 /*byte*/ 1416 /* 1417 **============================================================================== 1418 ** 0x0b-0x09 : 0180_00 (class code 1,native pci mode ) 1419 ** Bit Default Description 1420 ** 23:16 06h Base Class Code (BCC): Indicates that this is a bridge device. 1421 ** 15:08 04h Sub Class Code (SCC): Indicates this is of type PCI-to-PCI bridge. 1422 ** 07:00 00h Programming Interface (PIF): Indicates that this is standard (non-subtractive) PCI-PCI bridge. 1423 **============================================================================== 1424 */ 1425 #define ARCMSR_PCI2PCI_CLASSCODE_REG 0x09 /*3bytes*/ 1426 /* 1427 **============================================================================== 1428 ** 0x0c : cache line size 1429 ** Bit Default Description 1430 ** 07:00 00h Cache Line Size (CLS): Designates the cache line size in 32-bit dword units. 1431 ** The contents of this register are factored into 1432 ** internal policy decisions associated with memory read prefetching, 1433 ** and the promotion of Memory Write transactions to MWI transactions. 1434 ** Valid cache line sizes are 8 and 16 dwords. 1435 ** When the cache line size is set to an invalid value, 1436 ** bridge behaves as though the cache line size was set to 00h. 1437 **============================================================================== 1438 */ 1439 #define ARCMSR_PCI2PCI_PRIMARY_CACHELINESIZE_REG 0x0C /*byte*/ 1440 /* 1441 **============================================================================== 1442 ** 0x0d : latency timer (number of pci clock 00-ff ) 1443 ** Bit Default Description 1444 ** Primary Latency Timer (PTV): 1445 ** 07:00 00h (Conventional PCI) Conventional PCI Mode: Primary bus Master latency timer. Indicates the number of PCI clock cycles, 1446 ** referenced from the assertion of FRAME# to the expiration of the timer, 1447 ** when bridge may continue as master of the current transaction. All bits are writable, 1448 ** resulting in a granularity of 1 PCI clock cycle. 1449 ** When the timer expires (i.e., equals 00h) 1450 ** bridge relinquishes the bus after the first data transfer 1451 ** when its PCI bus grant has been deasserted. 1452 ** or 40h (PCI-X) PCI-X Mode: Primary bus Master latency timer. 1453 ** Indicates the number of PCI clock cycles, 1454 ** referenced from the assertion of FRAME# to the expiration of the timer, 1455 ** when bridge may continue as master of the current transaction. 1456 ** All bits are writable, resulting in a granularity of 1 PCI clock cycle. 1457 ** When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB. 1458 ** (Except in the case where MLT expires within 3 data phases 1459 ** of an ADB.In this case bridge continues on 1460 ** until it reaches the next ADB before relinquishing the bus.) 1461 **============================================================================== 1462 */ 1463 #define ARCMSR_PCI2PCI_PRIMARY_LATENCYTIMER_REG 0x0D /*byte*/ 1464 /* 1465 **============================================================================== 1466 ** 0x0e : (header type,single function ) 1467 ** Bit Default Description 1468 ** 07 0 Multi-function device (MVD): 80331 is a single-function device. 1469 ** 06:00 01h Header Type (HTYPE): Defines the layout of addresses 10h through 3Fh in configuration space. 1470 ** Returns ��01h�� when read indicating 1471 ** that the register layout conforms to the standard PCI-to-PCI bridge layout. 1472 **============================================================================== 1473 */ 1474 #define ARCMSR_PCI2PCI_HEADERTYPE_REG 0x0E /*byte*/ 1475 /* 1476 **============================================================================== 1477 ** 0x0f : 1478 **============================================================================== 1479 */ 1480 /* 1481 **============================================================================== 1482 ** 0x13-0x10 : 1483 ** PCI CFG Base Address #0 (0x10) 1484 **============================================================================== 1485 */ 1486 /* 1487 **============================================================================== 1488 ** 0x17-0x14 : 1489 ** PCI CFG Base Address #1 (0x14) 1490 **============================================================================== 1491 */ 1492 /* 1493 **============================================================================== 1494 ** 0x1b-0x18 : 1495 ** PCI CFG Base Address #2 (0x18) 1496 **-----------------0x1A,0x19,0x18--Bus Number Register - BNR 1497 ** Bit Default Description 1498 ** 23:16 00h Subordinate Bus Number (SBBN): Indicates the highest PCI bus number below this bridge. 1499 ** Any Type 1 configuration cycle 1500 ** on the primary bus whose bus number is greater than the secondary bus number, 1501 ** and less than or equal to the subordinate bus number 1502 ** is forwarded unaltered as a Type 1 configuration cycle on the secondary PCI bus. 1503 ** 15:08 00h Secondary Bus Number (SCBN): Indicates the bus number of PCI to which the secondary interface is connected. 1504 ** Any Type 1 configuration cycle matching this bus number 1505 ** is translated to a Type 0 configuration cycle (or a Special Cycle) 1506 ** before being executed on bridge's secondary PCI bus. 1507 ** 07:00 00h Primary Bus Number (PBN): Indicates bridge primary bus number. 1508 ** Any Type 1 configuration cycle on the primary interface 1509 ** with a bus number that is less than the contents 1510 ** of this register field does not be claimed by bridge. 1511 **-----------------0x1B--Secondary Latency Timer Register - SLTR 1512 ** Bit Default Description 1513 ** Secondary Latency Timer (STV): 1514 ** 07:00 00h (Conventional PCI) Conventional PCI Mode: Secondary bus Master latency timer. 1515 ** Indicates the number of PCI clock cycles, 1516 ** referenced from the assertion of FRAME# to the expiration of the timer, 1517 ** when bridge may continue as master of the current transaction. All bits are writable, 1518 ** resulting in a granularity of 1 PCI clock cycle. 1519 ** When the timer expires (i.e., equals 00h) 1520 ** bridge relinquishes the bus after the first data transfer 1521 ** when its PCI bus grant has been deasserted. 1522 ** or 40h (PCI-X) PCI-X Mode: Secondary bus Master latency timer. 1523 ** Indicates the number of PCI clock cycles,referenced from the assertion of FRAME# 1524 ** to the expiration of the timer, 1525 ** when bridge may continue as master of the current transaction. All bits are writable, 1526 ** resulting in a granularity of 1 PCI clock cycle. 1527 ** When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB. 1528 ** (Except in the case where MLT expires within 3 data phases of an ADB. 1529 ** In this case bridge continues on until it reaches the next ADB 1530 ** before relinquishing the bus) 1531 **============================================================================== 1532 */ 1533 #define ARCMSR_PCI2PCI_PRIMARY_BUSNUMBER_REG 0x18 /*3byte 0x1A,0x19,0x18*/ 1534 #define ARCMSR_PCI2PCI_SECONDARY_BUSNUMBER_REG 0x19 /*byte*/ 1535 #define ARCMSR_PCI2PCI_SUBORDINATE_BUSNUMBER_REG 0x1A /*byte*/ 1536 #define ARCMSR_PCI2PCI_SECONDARY_LATENCYTIMER_REG 0x1B /*byte*/ 1537 /* 1538 **============================================================================== 1539 ** 0x1f-0x1c : 1540 ** PCI CFG Base Address #3 (0x1C) 1541 **-----------------0x1D,0x1C--I/O Base and Limit Register - IOBL 1542 ** Bit Default Description 1543 ** 15:12 0h I/O Limit Address Bits [15:12]: Defines the top address of an address range to 1544 ** determine when to forward I/O transactions from one interface to the other. 1545 ** These bits correspond to address lines 15:12 for 4KB alignment. 1546 ** Bits 11:0 are assumed to be FFFh. 1547 ** 11:08 1h I/O Limit Addressing Capability: This field is hard-wired to 1h, indicating support 32-bit I/O addressing. 1548 ** 07:04 0h I/O Base Address Bits [15:12]: Defines the bottom address of 1549 ** an address range to determine when to forward I/O transactions 1550 ** from one interface to the other. 1551 ** These bits correspond to address lines 15:12 for 4KB alignment. 1552 ** Bits 11:0 are assumed to be 000h. 1553 ** 03:00 1h I/O Base Addressing Capability: This is hard-wired to 1h, indicating support for 32-bit I/O addressing. 1554 **-----------------0x1F,0x1E--Secondary Status Register - SSR 1555 ** Bit Default Description 1556 ** 15 0b Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address, 1557 ** attribute or data parity error on its secondary interface. 1558 ** 14 0b Received System Error: The bridge sets this bit when it samples SERR# asserted on its secondary bus interface. 1559 ** 13 0b Received Master Abort: The bridge sets this bit to a 1b when, 1560 ** acting as the initiator on the secondary bus, 1561 ** it's transaction (with the exception of special cycles) 1562 ** has been terminated with a Master Abort. 1563 ** 12 0b Received Target Abort: The bridge sets this bit to a 1b when, 1564 ** acting as the initiator on the secondary bus, 1565 ** it's transaction has been terminated with a Target Abort. 1566 ** 11 0b Signaled Target Abort: The bridge sets this bit to a 1b when it, 1567 ** as the target of a transaction, terminates it with a Target Abort. 1568 ** In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code. 1569 ** 10:09 01b DEVSEL# Timing: Indicates slowest response to a non-configuration command on the secondary interface. 1570 ** Returns ��01b�� when read, indicating that bridge responds no slower than with medium timing. 1571 ** 08 0b Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true: 1572 ** The bridge is the current master on the secondary bus 1573 ** S_PERR# is detected asserted or is asserted by bridge 1574 ** The Parity Error Response bit is set in the Command register 1575 ** 07 1b Fast Back-to-Back Capable (FBC): Indicates that the secondary interface of bridge can receive fast back-to-back cycles. 1576 ** 06 0b Reserved 1577 ** 05 1b 66 MHz Capable (C66): Indicates the secondary interface of the bridge is 66 MHz capable. 1578 ** 1 = 1579 ** 04:00 00h Reserved 1580 **============================================================================== 1581 */ 1582 #define ARCMSR_PCI2PCI_IO_BASE_REG 0x1C /*byte*/ 1583 #define ARCMSR_PCI2PCI_IO_LIMIT_REG 0x1D /*byte*/ 1584 #define ARCMSR_PCI2PCI_SECONDARY_STATUS_REG 0x1E /*word: 0x1F,0x1E */ 1585 /* 1586 **============================================================================== 1587 ** 0x23-0x20 : 1588 ** PCI CFG Base Address #4 (0x20) 1589 **-----------------0x23,0x22,0x21,0x20--Memory Base and Limit Register - MBL 1590 ** Bit Default Description 1591 ** 31:20 000h Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine 1592 ** the upper 1MB aligned value (exclusive) of the range. 1593 ** The incoming address must be less than or equal to this value. 1594 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0] 1595 ** are assumed to be F FFFFh. 1596 ** 19:16 0h Reserved. 1597 ** 15:04 000h Memory Base: These 12 bits are compared with bits P_AD[31:20] 1598 ** of the incoming address to determine the lower 1MB 1599 ** aligned value (inclusive) of the range. 1600 ** The incoming address must be greater than or equal to this value. 1601 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0]) 1602 ** are assumed to be 0 0000h. 1603 ** 03:00 0h Reserved. 1604 **============================================================================== 1605 */ 1606 #define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_BASE_REG 0x20 /*word: 0x21,0x20 */ 1607 #define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_LIMIT_REG 0x22 /*word: 0x23,0x22 */ 1608 /* 1609 **============================================================================== 1610 ** 0x27-0x24 : 1611 ** PCI CFG Base Address #5 (0x24) 1612 **-----------------0x27,0x26,0x25,0x24--Prefetchable Memory Base and Limit Register - PMBL 1613 ** Bit Default Description 1614 ** 31:20 000h Prefetchable Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine 1615 ** the upper 1MB aligned value (exclusive) of the range. 1616 ** The incoming address must be less than or equal to this value. 1617 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0] 1618 ** are assumed to be F FFFFh. 1619 ** 19:16 1h 64-bit Indicator: Indicates that 64-bit addressing is supported. 1620 ** 15:04 000h Prefetchable Memory Base: These 12 bits are compared with bits P_AD[31:20] 1621 ** of the incoming address to determine the lower 1MB aligned value (inclusive) 1622 ** of the range. 1623 ** The incoming address must be greater than or equal to this value. 1624 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0]) 1625 ** are assumed to be 0 0000h. 1626 ** 03:00 1h 64-bit Indicator: Indicates that 64-bit addressing is supported. 1627 **============================================================================== 1628 */ 1629 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_REG 0x24 /*word: 0x25,0x24 */ 1630 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_REG 0x26 /*word: 0x27,0x26 */ 1631 /* 1632 **============================================================================== 1633 ** 0x2b-0x28 : 1634 ** Bit Default Description 1635 ** 31:00 00000000h Prefetchable Memory Base Upper Portion: All bits are read/writable 1636 ** bridge supports full 64-bit addressing. 1637 **============================================================================== 1638 */ 1639 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_UPPER32_REG 0x28 /*dword: 0x2b,0x2a,0x29,0x28 */ 1640 /* 1641 **============================================================================== 1642 ** 0x2f-0x2c : 1643 ** Bit Default Description 1644 ** 31:00 00000000h Prefetchable Memory Limit Upper Portion: All bits are read/writable 1645 ** bridge supports full 64-bit addressing. 1646 **============================================================================== 1647 */ 1648 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_UPPER32_REG 0x2C /*dword: 0x2f,0x2e,0x2d,0x2c */ 1649 /* 1650 **============================================================================== 1651 ** 0x33-0x30 : 1652 ** Bit Default Description 1653 ** 07:00 DCh Capabilities Pointer: Pointer to the first CAP ID entry in the capabilities list is at DCh in PCI configuration 1654 ** space. (Power Management Capability Registers) 1655 **============================================================================== 1656 */ 1657 #define ARCMSR_PCI2PCI_CAPABILITIES_POINTER_REG 0x34 /*byte*/ 1658 /* 1659 **============================================================================== 1660 ** 0x3b-0x35 : reserved 1661 **============================================================================== 1662 */ 1663 /* 1664 **============================================================================== 1665 ** 0x3d-0x3c : 1666 ** 1667 ** Bit Default Description 1668 ** 15:08 00h Interrupt Pin (PIN): Bridges do not support the generation of interrupts. 1669 ** 07:00 00h Interrupt Line (LINE): The bridge does not generate interrupts, so this is reserved as '00h'. 1670 **============================================================================== 1671 */ 1672 #define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_LINE_REG 0x3C /*byte*/ 1673 #define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_PIN_REG 0x3D /*byte*/ 1674 /* 1675 **============================================================================== 1676 ** 0x3f-0x3e : 1677 ** Bit Default Description 1678 ** 15:12 0h Reserved 1679 ** 11 0b Discard Timer SERR# Enable: Controls the generation of SERR# on the primary interface (P_SERR#) in response 1680 ** to a timer discard on either the primary or secondary interface. 1681 ** 0b=SERR# is not asserted. 1682 ** 1b=SERR# is asserted. 1683 ** 10 0b Discard Timer Status (DTS): This bit is set to a '1b' when either the primary or secondary discard timer expires. 1684 ** The delayed completion is then discarded. 1685 ** 09 0b Secondary Discard Timer (SDT): Sets the maximum number of PCI clock cycles 1686 ** that bridge waits for an initiator on the secondary bus 1687 ** to repeat a delayed transaction request. 1688 ** The counter starts when the delayed transaction completion is ready 1689 ** to be returned to the initiator. 1690 ** When the initiator has not repeated the transaction 1691 ** at least once before the counter expires,bridge 1692 ** discards the delayed transaction from its queues. 1693 ** 0b=The secondary master time-out counter is 2 15 PCI clock cycles. 1694 ** 1b=The secondary master time-out counter is 2 10 PCI clock cycles. 1695 ** 08 0b Primary Discard Timer (PDT): Sets the maximum number of PCI clock cycles 1696 ** that bridge waits for an initiator on the primary bus 1697 ** to repeat a delayed transaction request. 1698 ** The counter starts when the delayed transaction completion 1699 ** is ready to be returned to the initiator. 1700 ** When the initiator has not repeated the transaction 1701 ** at least once before the counter expires, 1702 ** bridge discards the delayed transaction from its queues. 1703 ** 0b=The primary master time-out counter is 2 15 PCI clock cycles. 1704 ** 1b=The primary master time-out counter is 2 10 PCI clock cycles. 1705 ** 07 0b Fast Back-to-Back Enable (FBE): The bridge does not initiate back to back transactions. 1706 ** 06 0b Secondary Bus Reset (SBR): 1707 ** When cleared to 0b: The bridge deasserts S_RST#, 1708 ** when it had been asserted by writing this bit to a 1b. 1709 ** When set to 1b: The bridge asserts S_RST#. 1710 ** 05 0b Master Abort Mode (MAM): Dictates bridge behavior on the initiator bus 1711 ** when a master abort termination occurs in response to 1712 ** a delayed transaction initiated by bridge on the target bus. 1713 ** 0b=The bridge asserts TRDY# in response to a non-locked delayed transaction, 1714 ** and returns FFFF FFFFh when a read. 1715 ** 1b=When the transaction had not yet been completed on the initiator bus 1716 ** (e.g.,delayed reads, or non-posted writes), 1717 ** then bridge returns a Target Abort in response to the original requester 1718 ** when it returns looking for its delayed completion on the initiator bus. 1719 ** When the transaction had completed on the initiator bus (e.g., a PMW), 1720 ** then bridge asserts P_SERR# (when enabled). 1721 ** For PCI-X transactions this bit is an enable for the assertion of P_SERR# due to a master abort 1722 ** while attempting to deliver a posted memory write on the destination bus. 1723 ** 04 0b VGA Alias Filter Enable: This bit dictates bridge behavior in conjunction with the VGA enable bit 1724 ** (also of this register), 1725 ** and the VGA Palette Snoop Enable bit (Command Register). 1726 ** When the VGA enable, or VGA Palette Snoop enable bits are on (i.e., 1b) 1727 ** the VGA Aliasing bit for the corresponding enabled functionality,: 1728 ** 0b=Ignores address bits AD[15:10] when decoding VGA I/O addresses. 1729 ** 1b=Ensures that address bits AD[15:10] equal 000000b when decoding VGA I/O addresses. 1730 ** When all VGA cycle forwarding is disabled, (i.e., VGA Enable bit =0b and VGA Palette Snoop bit =0b), 1731 ** then this bit has no impact on bridge behavior. 1732 ** 03 0b VGA Enable: Setting this bit enables address decoding 1733 ** and transaction forwarding of the following VGA transactions from the primary bus 1734 ** to the secondary bus: 1735 ** frame buffer memory addresses 000A0000h:000BFFFFh, 1736 ** VGA I/O addresses 3B0:3BBh and 3C0h:3DFh, where AD[31:16]=��0000h?** ?and AD[15:10] are either not decoded (i.e., don't cares), 1737 ** or must be ��000000b�� 1738 ** depending upon the state of the VGA Alias Filter Enable bit. (bit(4) of this register) 1739 ** I/O and Memory Enable bits must be set in the Command register 1740 ** to enable forwarding of VGA cycles. 1741 ** 02 0b ISA Enable: Setting this bit enables special handling 1742 ** for the forwarding of ISA I/O transactions that fall within the address range 1743 ** specified by the I/O Base and Limit registers, 1744 ** and are within the lowest 64Kbyte of the I/O address map 1745 ** (i.e., 0000 0000h - 0000 FFFFh). 1746 ** 0b=All I/O transactions that fall within the I/O Base 1747 ** and Limit registers' specified range are forwarded 1748 ** from primary to secondary unfiltered. 1749 ** 1b=Blocks the forwarding from primary to secondary 1750 ** of the top 768 bytes of each 1Kbyte alias. 1751 ** On the secondary the top 768 bytes of each 1K alias 1752 ** are inversely decoded and forwarded 1753 ** from secondary to primary. 1754 ** 01 0b SERR# Forward Enable: 0b=The bridge does not assert P_SERR# as a result of an S_SERR# assertion. 1755 ** 1b=The bridge asserts P_SERR# whenever S_SERR# is detected 1756 ** asserted provided the SERR# Enable bit is set (PCI Command Register bit(8)=1b). 1757 ** 00 0b Parity Error Response: This bit controls bridge response to a parity error 1758 ** that is detected on its secondary interface. 1759 ** 0b=When a data parity error is detected bridge does not assert S_PERR#. 1760 ** Also bridge does not assert P_SERR# in response to a detected address 1761 ** or attribute parity error. 1762 ** 1b=When a data parity error is detected bridge asserts S_PERR#. 1763 ** The bridge also asserts P_SERR# (when enabled globally via bit(8) 1764 ** of the Command register) 1765 ** in response to a detected address or attribute parity error. 1766 **============================================================================== 1767 */ 1768 #define ARCMSR_PCI2PCI_BRIDGE_CONTROL_REG 0x3E /*word*/ 1769 /* 1770 ************************************************************************** 1771 ** Device Specific Registers 40-A7h 1772 ************************************************************************** 1773 ** ---------------------------------------------------------------------------------------------------------- 1774 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 1775 ** ---------------------------------------------------------------------------------------------------------- 1776 ** | Bridge Control 0 | Arbiter Control/Status | Reserved | 40h 1777 ** ---------------------------------------------------------------------------------------------------------- 1778 ** | Bridge Control 2 | Bridge Control 1 | 44h 1779 ** ---------------------------------------------------------------------------------------------------------- 1780 ** | Reserved | Bridge Status | 48h 1781 ** ---------------------------------------------------------------------------------------------------------- 1782 ** | Reserved | 4Ch 1783 ** ---------------------------------------------------------------------------------------------------------- 1784 ** | Prefetch Policy | Multi-Transaction Timer | 50h 1785 ** ---------------------------------------------------------------------------------------------------------- 1786 ** | Reserved | Pre-boot Status | P_SERR# Assertion Control | 54h 1787 ** ---------------------------------------------------------------------------------------------------------- 1788 ** | Reserved | Reserved | Secondary Decode Enable | 58h 1789 ** ---------------------------------------------------------------------------------------------------------- 1790 ** | Reserved | Secondary IDSEL | 5Ch 1791 ** ---------------------------------------------------------------------------------------------------------- 1792 ** | Reserved | 5Ch 1793 ** ---------------------------------------------------------------------------------------------------------- 1794 ** | Reserved | 68h:CBh 1795 ** ---------------------------------------------------------------------------------------------------------- 1796 ************************************************************************** 1797 **============================================================================== 1798 ** 0x42-0x41: Secondary Arbiter Control/Status Register - SACSR 1799 ** Bit Default Description 1800 ** 15:12 1111b Grant Time-out Violator: This field indicates the agent that violated the Grant Time-out rule 1801 ** (PCI=16 clocks,PCI-X=6 clocks). 1802 ** Note that this field is only meaningful when: 1803 ** # Bit[11] of this register is set to 1b, 1804 ** indicating that a Grant Time-out violation had occurred. 1805 ** # bridge internal arbiter is enabled. 1806 ** Bits[15:12] Violating Agent (REQ#/GNT# pair number) 1807 ** 0000b REQ#/GNT#[0] 1808 ** 0001b REQ#/GNT#[1] 1809 ** 0010b REQ#/GNT#[2] 1810 ** 0011b REQ#/GNT#[3] 1811 ** 1111b Default Value (no violation detected) 1812 ** When bit[11] is cleared by software, this field reverts back to its default value. 1813 ** All other values are Reserved 1814 ** 11 0b Grant Time-out Occurred: When set to 1b, 1815 ** this indicates that a Grant Time-out error had occurred involving one of the secondary bus agents. 1816 ** Software clears this bit by writing a 1b to it. 1817 ** 10 0b Bus Parking Control: 0=During bus idle, bridge parks the bus on the last master to use the bus. 1818 ** 1=During bus idle, bridge parks the bus on itself. 1819 ** The bus grant is removed from the last master and internally asserted to bridge. 1820 ** 09:08 00b Reserved 1821 ** 07:00 0000 0000b Secondary Bus Arbiter Priority Configuration: The bridge secondary arbiter provides two rings of arbitration priority. 1822 ** Each bit of this field assigns its corresponding secondary 1823 ** bus master to either the high priority arbiter ring (1b) 1824 ** or to the low priority arbiter ring (0b). 1825 ** Bits [3:0] correspond to request inputs S_REQ#[3:0], respectively. 1826 ** Bit [6] corresponds to the bridge internal secondary bus request 1827 ** while Bit [7] corresponds to the SATU secondary bus request. 1828 ** Bits [5:4] are unused. 1829 ** 0b=Indicates that the master belongs to the low priority group. 1830 ** 1b=Indicates that the master belongs to the high priority group 1831 **================================================================================= 1832 ** 0x43: Bridge Control Register 0 - BCR0 1833 ** Bit Default Description 1834 ** 07 0b Fully Dynamic Queue Mode: 0=The number of Posted write transactions is limited to eight 1835 ** and the Posted Write data is limited to 4KB. 1836 ** 1=Operation in fully dynamic queue mode. The bridge enqueues up to 1837 ** 14 Posted Memory Write transactions and 8KB of posted write data. 1838 ** 06:03 0H Reserved. 1839 ** 02 0b Upstream Prefetch Disable: This bit disables bridge ability 1840 ** to perform upstream prefetch operations for Memory 1841 ** Read requests received on its secondary interface. 1842 ** This bit also controls the bridge's ability to generate advanced read commands 1843 ** when forwarding a Memory Read Block transaction request upstream from a PCI-X bus 1844 ** to a Conventional PCI bus. 1845 ** 0b=bridge treats all upstream Memory Read requests as though they target prefetchable memory. 1846 ** The use of Memory Read Line and Memory Read 1847 ** Multiple is enabled when forwarding a PCI-X Memory Read Block request 1848 ** to an upstream bus operating in Conventional PCI mode. 1849 ** 1b=bridge treats upstream PCI Memory Read requests as though 1850 ** they target non-prefetchable memory and forwards upstream PCI-X Memory 1851 ** Read Block commands as Memory Read 1852 ** when the primary bus is operating 1853 ** in Conventional PCI mode. 1854 ** NOTE: This bit does not affect bridge ability to perform read prefetching 1855 ** when the received command is Memory Read Line or Memory Read Multiple. 1856 **================================================================================= 1857 ** 0x45-0x44: Bridge Control Register 1 - BCR1 (Sheet 2 of 2) 1858 ** Bit Default Description 1859 ** 15:08 0000000b Reserved 1860 ** 07:06 00b Alias Command Mapping: This two bit field determines how bridge handles PCI-X ��Alias�� commands, 1861 ** specifically the Alias to Memory Read Block and Alias to Memory Write Block commands. 1862 ** The three options for handling these alias commands are to either pass it as is, 1863 ** re-map to the actual block memory read/write command encoding, or ignore 1864 ** the transaction forcing a Master Abort to occur on the Origination Bus. 1865 ** Bit (7:6) Handling of command 1866 ** 0 0 Re-map to Memory Read/Write Block before forwarding 1867 ** 0 1 Enqueue and forward the alias command code unaltered 1868 ** 1 0 Ignore the transaction, forcing Master Abort 1869 ** 1 1 Reserved 1870 ** 05 1b Watchdog Timers Disable: Disables or enables all 2 24 Watchdog Timers in both directions. 1871 ** The watchdog timers are used to detect prohibitively long latencies in the system. 1872 ** The watchdog timer expires when any Posted Memory Write (PMW), Delayed Request, 1873 ** or Split Requests (PCI-X mode) is not completed within 2 24 events 1874 ** (��events�� are defined as PCI Clocks when operating in PCI-X mode, 1875 ** and as the number of times being retried when operating in Conventional PCI mode) 1876 ** 0b=All 2 24 watchdog timers are enabled. 1877 ** 1b=All 2 24 watchdog timers are disabled and there is no limits to 1878 ** the number of attempts bridge makes when initiating a PMW, 1879 ** transacting a Delayed Transaction, or how long it waits for 1880 ** a split completion corresponding to one of its requests. 1881 ** 04 0b GRANT# time-out disable: This bit enables/disables the GNT# time-out mechanism. 1882 ** Grant time-out is 16 clocks for conventional PCI, and 6 clocks for PCI-X. 1883 ** 0b=The Secondary bus arbiter times out an agent 1884 ** that does not assert FRAME# within 16/6 clocks of receiving its grant, 1885 ** once the bus has gone idle. 1886 ** The time-out counter begins as soon as the bus goes idle with the new GNT# asserted. 1887 ** An infringing agent does not receive a subsequent GNT# 1888 ** until it de-asserts its REQ# for at least one clock cycle. 1889 ** 1b=GNT# time-out mechanism is disabled. 1890 ** 03 00b Reserved. 1891 ** 02 0b Secondary Discard Timer Disable: This bit enables/disables bridge secondary delayed transaction discard mechanism. 1892 ** The time out mechanism is used to ensure that initiators 1893 ** of delayed transactions return for their delayed completion data/status 1894 ** within a reasonable amount of time after it is available from bridge. 1895 ** 0b=The secondary master time-out counter is enabled 1896 ** and uses the value specified by the Secondary Discard Timer bit 1897 ** (see Bridge Control Register). 1898 ** 1b=The secondary master time-out counter is disabled. 1899 ** The bridge waits indefinitely for a secondary bus master 1900 ** to repeat a delayed transaction. 1901 ** 01 0b Primary Discard Timer Disable: This bit enables/disables bridge primary delayed transaction discard mechanism. 1902 ** The time out mechanism is used to ensure that initiators 1903 ** of delayed transactions return for their delayed completion data/status 1904 ** within a reasonable amount of time after it is available from bridge. 1905 ** 0b=The primary master time-out counter is enabled and uses the value specified 1906 ** by the Primary Discard Timer bit (see Bridge Control Register). 1907 ** 1b=The secondary master time-out counter is disabled. 1908 ** The bridge waits indefinitely for a secondary bus master 1909 ** to repeat a delayed transaction. 1910 ** 00 0b Reserved 1911 **================================================================================= 1912 ** 0x47-0x46: Bridge Control Register 2 - BCR2 1913 ** Bit Default Description 1914 ** 15:07 0000b Reserved. 1915 ** 06 0b Global Clock Out Disable (External Secondary Bus Clock Source Enable): 1916 ** This bit disables all of the secondary PCI clock outputs including 1917 ** the feedback clock S_CLKOUT. 1918 ** This means that the user is required to provide an S_CLKIN input source. 1919 ** 05:04 11 (66 MHz) Preserved. 1920 ** 01 (100 MHz) 1921 ** 00 (133 MHz) 1922 ** 03:00 Fh (100 MHz & 66 MHz) 1923 ** 7h (133 MHz) 1924 ** This 4 bit field provides individual enable/disable mask bits for each of bridge 1925 ** secondary PCI clock outputs. Some, or all secondary clock outputs (S_CLKO[3:0]) 1926 ** default to being enabled following the rising edge of P_RST#, depending on the 1927 ** frequency of the secondary bus clock: 1928 ** �E Designs with 100 MHz (or lower) Secondary PCI clock power up with 1929 ** all four S_CLKOs enabled by default. (SCLKO[3:0])�P 1930 ** �E Designs with 133 MHz Secondary PCI clock power up 1931 ** with the lower order 3 S_CLKOs enabled by default. 1932 ** (S_CLKO[2:0]) Only those SCLKs that power up enabled by can be connected 1933 ** to downstream device clock inputs. 1934 **================================================================================= 1935 ** 0x49-0x48: Bridge Status Register - BSR 1936 ** Bit Default Description 1937 ** 15 0b Upstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR# 1938 ** is conditionally asserted when the secondary discard timer expires. 1939 ** 14 0b Upstream Delayed/Split Read Watchdog Timer Expired: 1940 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# 1941 ** is conditionally asserted when bridge discards an upstream delayed read ** ** transaction request after 2 24 retries following the initial retry. 1942 ** PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 1943 ** when bridge discards an upstream split read request 1944 ** after waiting in excess of 2 24 clocks for the corresponding 1945 ** Split Completion to arrive. 1946 ** 13 0b Upstream Delayed/Split Write Watchdog Timer Expired: 1947 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# 1948 ** is conditionally asserted when bridge discards an upstream delayed write ** ** transaction request after 2 24 retries following the initial retry. 1949 ** PCI-X Mode: This bit is set to a 1b and P_SERR# 1950 ** is conditionally asserted when bridge discards an upstream split write request ** after waiting in excess of 2 24 clocks for the corresponding 1951 ** Split Completion to arrive. 1952 ** 12 0b Master Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR# 1953 ** is conditionally asserted when a Master Abort occurs as a result of an attempt, 1954 ** by bridge, to retire a PMW upstream. 1955 ** 11 0b Target Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR# 1956 ** is conditionally asserted when a Target Abort occurs as a result of an attempt, 1957 ** by bridge, to retire a PMW upstream. 1958 ** 10 0b Upstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR# 1959 ** is conditionally asserted when bridge discards an upstream PMW transaction 1960 ** after receiving 2 24 target retries from the primary bus target 1961 ** 09 0b Upstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR# 1962 ** is conditionally asserted when a data parity error is detected by bridge 1963 ** while attempting to retire a PMW upstream 1964 ** 08 0b Secondary Bus Address Parity Error: This bit is set to a 1b and P_SERR# 1965 ** is conditionally asserted when bridge detects an address parity error on 1966 ** the secondary bus. 1967 ** 07 0b Downstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR# 1968 ** is conditionally asserted when the primary bus discard timer expires. 1969 ** 06 0b Downstream Delayed/Split Read Watchdog Timer Expired: 1970 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# 1971 ** is conditionally asserted when bridge discards a downstream delayed read ** ** transaction request after receiving 2 24 target retries 1972 ** from the secondary bus target. 1973 ** PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 1974 ** when bridge discards a downstream split read request 1975 ** after waiting in excess of 2 24 clocks for the corresponding 1976 ** Split Completion to arrive. 1977 ** 05 0b Downstream Delayed Write/Split Watchdog Timer Expired: 1978 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 1979 ** when bridge discards a downstream delayed write transaction request 1980 ** after receiving 2 24 target retries from the secondary bus target. 1981 ** PCI-X Mode: This bit is set to a 1b and P_SERR# 1982 ** is conditionally asserted when bridge discards a downstream 1983 ** split write request after waiting in excess of 2 24 clocks 1984 ** for the corresponding Split Completion to arrive. 1985 ** 04 0b Master Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR# 1986 ** is conditionally asserted when a Master Abort occurs as a result of an attempt, 1987 ** by bridge, to retire a PMW downstream. 1988 ** 03 0b Target Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR# is conditionally asserted 1989 ** when a Target Abort occurs as a result of an attempt, by bridge, 1990 ** to retire a PMW downstream. 1991 ** 02 0b Downstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR# 1992 ** is conditionally asserted when bridge discards a downstream PMW transaction 1993 ** after receiving 2 24 target retries from the secondary bus target 1994 ** 01 0b Downstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR# 1995 ** is conditionally asserted when a data parity error is detected by bridge 1996 ** while attempting to retire a PMW downstream. 1997 ** 00 0b Primary Bus Address Parity Error: This bit is set to a 1b and P_SERR# is conditionally asserted 1998 ** when bridge detects an address parity error on the primary bus. 1999 **================================================================================== 2000 ** 0x51-0x50: Bridge Multi-Transaction Timer Register - BMTTR 2001 ** Bit Default Description 2002 ** 15:13 000b Reserved 2003 ** 12:10 000b GRANT# Duration: This field specifies the count (PCI clocks) 2004 ** that a secondary bus master has its grant maintained in order to enable 2005 ** multiple transactions to execute within the same arbitration cycle. 2006 ** Bit[02:00] GNT# Extended Duration 2007 ** 000 MTT Disabled (Default=no GNT# extension) 2008 ** 001 16 clocks 2009 ** 010 32 clocks 2010 ** 011 64 clocks 2011 ** 100 128 clocks 2012 ** 101 256 clocks 2013 ** 110 Invalid (treated as 000) 2014 ** 111 Invalid (treated as 000) 2015 ** 09:08 00b Reserved 2016 ** 07:00 FFh MTT Mask: This field enables/disables MTT usage for each REQ#/GNT# 2017 ** pair supported by bridge secondary arbiter. 2018 ** Bit(7) corresponds to SATU internal REQ#/GNT# pair, 2019 ** bit(6) corresponds to bridge internal REQ#/GNT# pair, 2020 ** bit(5) corresponds to REQ#/GNT#(5) pair, etc. 2021 ** When a given bit is set to 1b, its corresponding REQ#/GNT# 2022 ** pair is enabled for MTT functionality as determined by bits(12:10) of this register. 2023 ** When a given bit is cleared to 0b, its corresponding REQ#/GNT# pair is disabled from using the MTT. 2024 **================================================================================== 2025 ** 0x53-0x52: Read Prefetch Policy Register - RPPR 2026 ** Bit Default Description 2027 ** 15:13 000b ReRead_Primary Bus: 3-bit field indicating the multiplication factor 2028 ** to be used in calculating the number of bytes to prefetch from the secondary bus interface on ** subsequent PreFetch operations given that the read demands were not satisfied 2029 ** using the FirstRead parameter. 2030 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs 2031 ** Memory Read Line 1 cache lines Memory Read Multiple 2 cache lines 2032 ** 12:10 000b FirstRead_Primary Bus: 3-bit field indicating the multiplication factor to be used in calculating 2033 ** the number of bytes to prefetch from the secondary bus interface 2034 ** on the initial PreFetch operation. 2035 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs 2036 ** Memory Read Line 1 cache line Memory Read Multiple 2 cache lines 2037 ** 09:07 010b ReRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used 2038 ** in calculating the number of bytes to prefetch from the primary 2039 ** bus interface on subsequent PreFetch operations given 2040 ** that the read demands were not satisfied using 2041 ** the FirstRead parameter. 2042 ** The default value of 010b correlates to: Command Type Hardwired pre-fetch a 2043 ** mount Memory Read 3 cache lines Memory Read Line 3 cache lines 2044 ** Memory Read Multiple 6 cache lines 2045 ** 06:04 000b FirstRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used 2046 ** in calculating the number of bytes to prefetch from 2047 ** the primary bus interface on the initial PreFetch operation. 2048 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount 2049 ** Memory Read 4 DWORDs Memory Read Line 1 cache line Memory Read Multiple 2 cache lines 2050 ** 03:00 1111b Staged Prefetch Enable: This field enables/disables the FirstRead/ReRead pre-fetch 2051 ** algorithm for the secondary and the primary bus interfaces. 2052 ** Bit(3) is a ganged enable bit for REQ#/GNT#[7:3], and bits(2:0) provide individual 2053 ** enable bits for REQ#/GNT#[2:0]. 2054 ** (bit(2) is the enable bit for REQ#/GNT#[2], etc...) 2055 ** 1b: enables the staged pre-fetch feature 2056 ** 0b: disables staged pre-fetch, 2057 ** and hardwires read pre-fetch policy to the following for 2058 ** Memory Read, 2059 ** Memory Read Line, 2060 ** and Memory Read Multiple commands: 2061 ** Command Type Hardwired Pre-Fetch Amount... 2062 ** Memory Read 4 DWORDs 2063 ** Memory Read Line 1 cache line 2064 ** Memory Read Multiple 2 cache lines 2065 ** NOTE: When the starting address is not cache line aligned, bridge pre-fetches Memory Read line commands 2066 ** only to the next higher cache line boundary.For non-cache line aligned Memory Read 2067 ** Multiple commands bridge pre-fetches only to the second cache line boundary encountered. 2068 **================================================================================== 2069 ** 0x55-0x54: P_SERR# Assertion Control - SERR_CTL 2070 ** Bit Default Description 2071 ** 15 0b Upstream Delayed Transaction Discard Timer Expired: Dictates the bridge behavior 2072 ** in response to its discarding of a delayed transaction that was initiated from the primary bus. 2073 ** 0b=bridge asserts P_SERR#. 2074 ** 1b=bridge does not assert P_SERR# 2075 ** 14 0b Upstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 2076 ** 0b=bridge asserts P_SERR#. 2077 ** 1b=bridge does not assert P_SERR# 2078 ** 13 0b Upstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 2079 ** 0b=bridge asserts P_SERR#. 2080 ** 1b=bridge does not assert P_SERR# 2081 ** 12 0b Master Abort during Upstream Posted Write: Dictates bridge behavior following 2082 ** its having detected a Master Abort while attempting to retire one of its PMWs upstream. 2083 ** 0b=bridge asserts P_SERR#. 2084 ** 1b=bridge does not assert P_SERR# 2085 ** 11 0b Target Abort during Upstream Posted Write: Dictates bridge behavior following 2086 ** its having been terminated with Target Abort while attempting to retire one of its PMWs upstream. 2087 ** 0b=bridge asserts P_SERR#. 2088 ** 1b=bridge does not assert P_SERR# 2089 ** 10 0b Upstream Posted Write Data Discarded: Dictates bridge behavior in the event that 2090 ** it discards an upstream posted write transaction. 2091 ** 0b=bridge asserts P_SERR#. 2092 ** 1b=bridge does not assert P_SERR# 2093 ** 09 0b Upstream Posted Write Data Parity Error: Dictates bridge behavior 2094 ** when a data parity error is detected while attempting to retire on of its PMWs upstream. 2095 ** 0b=bridge asserts P_SERR#. 2096 ** 1b=bridge does not assert P_SERR# 2097 ** 08 0b Secondary Bus Address Parity Error: This bit dictates bridge behavior 2098 ** when it detects an address parity error on the secondary bus. 2099 ** 0b=bridge asserts P_SERR#. 2100 ** 1b=bridge does not assert P_SERR# 2101 ** 07 0b Downstream Delayed Transaction Discard Timer Expired: Dictates bridge behavior in response to 2102 ** its discarding of a delayed transaction that was initiated on the secondary bus. 2103 ** 0b=bridge asserts P_SERR#. 2104 ** 1b=bridge does not assert P_SERR# 2105 ** 06 0b Downstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 2106 ** 0b=bridge asserts P_SERR#. 2107 ** 1b=bridge does not assert P_SERR# 2108 ** 05 0b Downstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 2109 ** 0b=bridge asserts P_SERR#. 2110 ** 1b=bridge does not assert P_SERR# 2111 ** 04 0b Master Abort during Downstream Posted Write: Dictates bridge behavior following 2112 ** its having detected a Master Abort while attempting to retire one of its PMWs downstream. 2113 ** 0b=bridge asserts P_SERR#. 2114 ** 1b=bridge does not assert P_SERR# 2115 ** 03 0b Target Abort during Downstream Posted Write: Dictates bridge behavior following 2116 ** its having been terminated with Target Abort while attempting to retire one of its PMWs downstream. 2117 ** 0b=bridge asserts P_SERR#. 2118 ** 1b=bridge does not assert P_SERR# 2119 ** 02 0b Downstream Posted Write Data Discarded: Dictates bridge behavior in the event 2120 ** that it discards a downstream posted write transaction. 2121 ** 0b=bridge asserts P_SERR#. 2122 ** 1b=bridge does not assert P_SERR# 2123 ** 01 0b Downstream Posted Write Data Parity Error: Dictates bridge behavior 2124 ** when a data parity error is detected while attempting to retire on of its PMWs downstream. 2125 ** 0b=bridge asserts P_SERR#. 2126 ** 1b=bridge does not assert P_SERR# 2127 ** 00 0b Primary Bus Address Parity Error: This bit dictates bridge behavior 2128 ** when it detects an address parity error on the primary bus. 2129 ** 0b=bridge asserts P_SERR#. 2130 ** 1b=bridge does not assert P_SERR# 2131 **=============================================================================== 2132 ** 0x56: Pre-Boot Status Register - PBSR 2133 ** Bit Default Description 2134 ** 07 1 Reserved 2135 ** 06 - Reserved - value indeterminate 2136 ** 05:02 0 Reserved 2137 ** 01 Varies with External State of S_133EN at PCI Bus Reset Secondary Bus Max Frequency Setting: 2138 ** This bit reflect captured S_133EN strap, 2139 ** indicating the maximum secondary bus clock frequency when in PCI-X mode. 2140 ** Max Allowable Secondary Bus Frequency 2141 ** ** S_133EN PCI-X Mode 2142 ** ** 0 100 MHz 2143 ** ** 1 133 MH 2144 ** 00 0b Reserved 2145 **=============================================================================== 2146 ** 0x59-0x58: Secondary Decode Enable Register - SDER 2147 ** Bit Default Description 2148 ** 15:03 FFF1h Preserved. 2149 ** 02 Varies with External State of PRIVMEM at PCI Bus Reset Private Memory Space Enable - when set, 2150 ** bridge overrides its secondary inverse decode logic and not 2151 ** forward upstream any secondary bus initiated DAC Memory transactions with AD(63)=1b. 2152 ** This creates a private memory space on the Secondary PCI bus 2153 ** that allows peer-to-peer transactions. 2154 ** 01:00 10 2 Preserved. 2155 **=============================================================================== 2156 ** 0x5D-0x5C: Secondary IDSEL Select Register - SISR 2157 ** Bit Default Description 2158 ** 15:10 000000 2 Reserved. 2159 ** 09 Varies with External State of PRIVDEV at PCI Bus Reset AD25- IDSEL Disable - When this bit is set, 2160 ** AD25 is deasserted for any possible Type 1 to Type 0 conversion. 2161 ** When this bit is clear, 2162 ** AD25 is asserted when Primary addresses AD[15:11]=01001 2 during a Type 1 to Type 0 conversion. 2163 ** 08 Varies with External State of PRIVDEV at PCI Bus Reset AD24- IDSEL Disable - When this bit is set, 2164 ** AD24 is deasserted for any possible Type 1 to Type 0 conversion. 2165 ** When this bit is clear, 2166 ** AD24 is asserted when Primary addresses AD[15:11]=01000 2 during a Type 1 to Type 0 conversion. 2167 ** 07 Varies with External State of PRIVDEV at PCI Bus Reset AD23- IDSEL Disable - When this bit is set, 2168 ** AD23 is deasserted for any possible Type 1 to Type 0 conversion. 2169 ** When this bit is clear, 2170 ** AD23 is asserted when Primary addresses AD[15:11]=00111 2 during a Type 1 to Type 0 conversion. 2171 ** 06 Varies with External State of PRIVDEV at PCI Bus Reset AD22- IDSEL Disable - When this bit is set, 2172 ** AD22 is deasserted for any possible Type 1 to Type 0 conversion. 2173 ** When this bit is clear, 2174 ** AD22 is asserted when Primary addresses AD[15:11]=00110 2 during a Type 1 to Type 0 conversion. 2175 ** 05 Varies with External State of PRIVDEV at PCI Bus Reset AD21- IDSEL Disable - When this bit is set, 2176 ** AD21 is deasserted for any possible Type 1 to Type 0 conversion. 2177 ** When this bit is clear, 2178 ** AD21 is asserted when Primary addresses AD[15:11]=00101 2 during a Type 1 to Type 0 conversion. 2179 ** 04 Varies with External State of PRIVDEV at PCI Bus Reset AD20- IDSEL Disable - When this bit is set, 2180 ** AD20 is deasserted for any possible Type 1 to Type 0 conversion. 2181 ** When this bit is clear, 2182 ** AD20 is asserted when Primary addresses AD[15:11]=00100 2 during a Type 1 to Type 0 conversion. 2183 ** 03 Varies with External State of PRIVDEV at PCI Bus Reset AD19- IDSEL Disable - When this bit is set, 2184 ** AD19 is deasserted for any possible Type 1 to Type 0 conversion. 2185 ** When this bit is clear, 2186 ** AD19 is asserted when Primary addresses AD[15:11]=00011 2 during a Type 1 to Type 0 conversion. 2187 ** 02 Varies with External State of PRIVDEV at PCI Bus Reset AD18- IDSEL Disable - When this bit is set, 2188 ** AD18 is deasserted for any possible Type 1 to Type 0 conversion. 2189 ** When this bit is clear, 2190 ** AD18 is asserted when Primary addresses AD[15:11]=00010 2 during a Type 1 to Type 0 conversion. 2191 ** 01 Varies with External State of PRIVDEV at PCI Bus Reset AD17- IDSEL Disable - When this bit is set, 2192 ** AD17 is deasserted for any possible Type 1 to Type 0 conversion. 2193 ** When this bit is clear, 2194 ** AD17 is asserted when Primary addresses AD[15:11]=00001 2 during a Type 1 to Type 0 conversion. 2195 ** 00 Varies with External State of PRIVDEV at PCI Bus Reset AD16- IDSEL Disable - When this bit is set, 2196 ** AD16 is deasserted for any possible Type 1 to Type 0 conversion. 2197 ** When this bit is clear, 2198 ** AD16 is asserted when Primary addresses AD[15:11]=00000 2 during a Type 1 to Type 0 conversion. 2199 ************************************************************************** 2200 */ 2201 /* 2202 ************************************************************************** 2203 ** Reserved A8-CBh 2204 ************************************************************************** 2205 */ 2206 /* 2207 ************************************************************************** 2208 ** PCI Extended Enhanced Capabilities List CC-FFh 2209 ************************************************************************** 2210 ** ---------------------------------------------------------------------------------------------------------- 2211 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 2212 ** ---------------------------------------------------------------------------------------------------------- 2213 ** | Power Management Capabilities | Next Item Ptr | Capability ID | DCh 2214 ** ---------------------------------------------------------------------------------------------------------- 2215 ** | PM Data | PPB Support | Extensions Power Management CSR | E0h 2216 ** ---------------------------------------------------------------------------------------------------------- 2217 ** | Reserved | Reserved | Reserved | E4h 2218 ** ---------------------------------------------------------------------------------------------------------- 2219 ** | Reserved | E8h 2220 ** ---------------------------------------------------------------------------------------------------------- 2221 ** | Reserved | Reserved | Reserved | Reserved | ECh 2222 ** ---------------------------------------------------------------------------------------------------------- 2223 ** | PCI-X Secondary Status | Next Item Ptr | Capability ID | F0h 2224 ** ---------------------------------------------------------------------------------------------------------- 2225 ** | PCI-X Bridge Status | F4h 2226 ** ---------------------------------------------------------------------------------------------------------- 2227 ** | PCI-X Upstream Split Transaction Control | F8h 2228 ** ---------------------------------------------------------------------------------------------------------- 2229 ** | PCI-X Downstream Split Transaction Control | FCh 2230 ** ---------------------------------------------------------------------------------------------------------- 2231 **=============================================================================== 2232 ** 0xDC: Power Management Capabilities Identifier - PM_CAPID 2233 ** Bit Default Description 2234 ** 07:00 01h Identifier (ID): PCI SIG assigned ID for PCI-PM register block 2235 **=============================================================================== 2236 ** 0xDD: Next Item Pointer - PM_NXTP 2237 ** Bit Default Description 2238 ** 07:00 F0H Next Capabilities Pointer (PTR): The register defaults to F0H pointing to the PCI-X Extended Capability Header. 2239 **=============================================================================== 2240 ** 0xDF-0xDE: Power Management Capabilities Register - PMCR 2241 ** Bit Default Description 2242 ** 15:11 00h PME Supported (PME): PME# cannot be asserted by bridge. 2243 ** 10 0h State D2 Supported (D2): Indicates no support for state D2. No power management action in this state. 2244 ** 09 1h State D1 Supported (D1): Indicates support for state D1. No power management action in this state. 2245 ** 08:06 0h Auxiliary Current (AUXC): This 3 bit field reports the 3.3Vaux auxiliary current requirements for the PCI function. 2246 ** This returns 000b as PME# wake-up for bridge is not implemented. 2247 ** 05 0 Special Initialization Required (SINT): Special initialization is not required for bridge. 2248 ** 04:03 00 Reserved 2249 ** 02:00 010 Version (VS): Indicates that this supports PCI Bus Power Management Interface Specification, Revision 1.1. 2250 **=============================================================================== 2251 ** 0xE1-0xE0: Power Management Control / Status - Register - PMCSR 2252 ** Bit Default Description 2253 ** 15:09 00h Reserved 2254 ** 08 0b PME_Enable: This bit, when set to 1b enables bridge to assert PME#. 2255 ** Note that bridge never has occasion to assert PME# and implements this dummy R/W bit only for the purpose of working around an OS PCI-PM bug. 2256 ** 07:02 00h Reserved 2257 ** 01:00 00 Power State (PSTATE): This 2-bit field is used both to determine the current power state of 2258 ** a function and to set the Function into a new power state. 2259 ** 00 - D0 state 2260 ** 01 - D1 state 2261 ** 10 - D2 state 2262 ** 11 - D3 hot state 2263 **=============================================================================== 2264 ** 0xE2: Power Management Control / Status PCI to PCI Bridge Support - PMCSR_BSE 2265 ** Bit Default Description 2266 ** 07 0 Bus Power/Clock Control Enable (BPCC_En): Indicates that the bus power/clock control policies have been disabled. 2267 ** 06 0 B2/B3 support for D3 Hot (B2_B3#): The state of this bit determines the action that 2268 ** is to occur as a direct result of programming the function to D3 hot. 2269 ** This bit is only meaningful when bit 7 (BPCC_En) is a ��1��. 2270 ** 05:00 00h Reserved 2271 **=============================================================================== 2272 ** 0xE3: Power Management Data Register - PMDR 2273 ** Bit Default Description 2274 ** 07:00 00h Reserved 2275 **=============================================================================== 2276 ** 0xF0: PCI-X Capabilities Identifier - PX_CAPID 2277 ** Bit Default Description 2278 ** 07:00 07h Identifier (ID): Indicates this is a PCI-X capabilities list. 2279 **=============================================================================== 2280 ** 0xF1: Next Item Pointer - PX_NXTP 2281 ** Bit Default Description 2282 ** 07:00 00h Next Item Pointer: Points to the next capability in the linked list The power on default value of this 2283 ** register is 00h indicating that this is the last entry in the linked list of capabilities. 2284 **=============================================================================== 2285 ** 0xF3-0xF2: PCI-X Secondary Status - PX_SSTS 2286 ** Bit Default Description 2287 ** 15:09 00h Reserved 2288 ** 08:06 Xxx Secondary Clock Frequency (SCF): This field is set with the frequency of the secondary bus. 2289 ** The values are: 2290 ** ** BitsMax FrequencyClock Period 2291 ** ** 000PCI ModeN/A 2292 ** ** 00166 15 2293 ** ** 01010010 2294 ** ** 0111337.5 2295 ** ** 1xxreservedreserved 2296 ** ** The default value for this register is the operating frequency of the secondary bus 2297 ** 05 0b Split Request Delayed. (SRD): This bit is supposed to be set by a bridge when it cannot forward a transaction on the 2298 ** secondary bus to the primary bus because there is not enough room within the limit 2299 ** specified in the Split Transaction Commitment Limit field in the Downstream Split 2300 ** Transaction Control register. The bridge does not set this bit. 2301 ** 04 0b Split Completion Overrun (SCO): This bit is supposed to be set when a bridge terminates a Split Completion on the ** ** secondary bus with retry or Disconnect at next ADB because its buffers are full. 2302 ** The bridge does not set this bit. 2303 ** 03 0b Unexpected Split Completion (USC): This bit is set when an unexpected split completion with a requester ID 2304 ** equal to bridge secondary bus number, device number 00h, 2305 ** and function number 0 is received on the secondary interface. 2306 ** This bit is cleared by software writing a '1'. 2307 ** 02 0b Split Completion Discarded (SCD): This bit is set 2308 ** when bridge discards a split completion moving toward the secondary bus 2309 ** because the requester would not accept it. This bit cleared by software writing a '1'. 2310 ** 01 1b 133 MHz Capable: Indicates that bridge is capable of running its secondary bus at 133 MHz 2311 ** 00 1b 64-bit Device (D64): Indicates the width of the secondary bus as 64-bits. 2312 **=============================================================================== 2313 ** 0xF7-0xF6-0xf5-0xF4: PCI-X Bridge Status - PX_BSTS 2314 ** Bit Default Description 2315 ** 31:22 0 Reserved 2316 ** 21 0 Split Request Delayed (SRD): This bit does not be set by bridge. 2317 ** 20 0 Split Completion Overrun (SCO): This bit does not be set by bridge 2318 ** because bridge throttles traffic on the completion side. 2319 ** 19 0 Unexpected Split Completion (USC): The bridge sets this bit to 1b 2320 ** when it encounters a corrupted Split Completion, possibly with an ** ** inconsistent remaining byte count.Software clears 2321 ** this bit by writing a 1b to it. 2322 ** 18 0 Split Completion Discarded (SCD): The bridge sets this bit to 1b 2323 ** when it has discarded a Split Completion.Software clears this bit by ** ** writing a 1b to it. 2324 ** 17 1 133 MHz Capable: This bit indicates that the bridge primary interface is ** capable of 133 MHz operation in PCI-X mode. 2325 ** 0=The maximum operating frequency is 66 MHz. 2326 ** 1=The maximum operating frequency is 133 MHz. 2327 ** 16 Varies with the external state of P_32BITPCI# at PCI Bus Reset 64-bit Device (D64): Indicates bus width of the Primary PCI bus interface. 2328 ** 0=Primary Interface is connected as a 32-bit PCI bus. 2329 ** 1=Primary Interface is connected as a 64-bit PCI bus. 2330 ** 15:08 00h Bus Number (BNUM): This field is simply an alias to the PBN field 2331 ** of the BNUM register at offset 18h. 2332 ** Apparently it was deemed necessary reflect it here for diagnostic purposes. 2333 ** 07:03 1fh Device Number (DNUM): Indicates which IDSEL bridge consumes. 2334 ** May be updated whenever a PCI-X 2335 ** configuration write cycle that targets bridge scores a hit. 2336 ** 02:00 0h Function Number (FNUM): The bridge Function # 2337 **=============================================================================== 2338 ** 0xFB-0xFA-0xF9-0xF8: PCI-X Upstream Split Transaction Control - PX_USTC 2339 ** Bit Default Description 2340 ** 31:16 003Eh Split Transaction Limit (STL): This register indicates the size of the commitment limit in units of ADQs. 2341 ** Software is permitted to program this register to any value greater than or equal to 2342 ** the contents of the Split Transaction Capacity register. A value less than the contents 2343 ** of the Split Transaction Capacity register causes unspecified results. 2344 ** A value of 003Eh or greater enables the bridge to forward all Split Requests of any 2345 ** size regardless of the amount of buffer space available. 2346 ** 15:00 003Eh Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing 2347 ** split completions. This register controls behavior of the bridge buffers for forwarding 2348 ** Split Transactions from a primary bus requester to a secondary bus completer. 2349 ** The default value of 003Eh indicates there is available buffer space for 62 ADQs (7936 bytes). 2350 **=============================================================================== 2351 ** 0xFF-0xFE-0xFD-0xFC: PCI-X Downstream Split Transaction Control - PX_DSTC 2352 ** Bit Default Description 2353 ** 31:16 003Eh Split Transaction Limit (STL): This register indicates the size of the commitment limit in units of ADQs. 2354 ** Software is permitted to program this register to any value greater than or equal to 2355 ** the contents of the Split Transaction Capacity register. A value less than the contents 2356 ** of the Split Transaction Capacity register causes unspecified results. 2357 ** A value of 003Eh or greater enables the bridge to forward all Split Requests of any 2358 ** size regardless of the amount of buffer space available. 2359 ** 15:00 003Eh Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing 2360 ** split completions. This register controls behavior of the bridge buffers for forwarding 2361 ** Split Transactions from a primary bus requester to a secondary bus completer. 2362 ** The default value of 003Eh indicates there is available buffer space for 62 ADQs 2363 ** (7936 bytes). 2364 ************************************************************************** 2365 */ 2366 2367 2368 2369 2370 /* 2371 ************************************************************************************************************************************* 2372 ** 80331 Address Translation Unit Register Definitions 2373 ** ATU Interface Configuration Header Format 2374 ** The ATU is programmed via a [Type 0] configuration command on the PCI interface. 2375 ************************************************************************************************************************************* 2376 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configuration Byte Offset 2377 **=================================================================================================================================== 2378 ** | ATU Device ID | Vendor ID | 00h 2379 ** ---------------------------------------------------------------------------------------------------------- 2380 ** | Status | Command | 04H 2381 ** ---------------------------------------------------------------------------------------------------------- 2382 ** | ATU Class Code | Revision ID | 08H 2383 ** ---------------------------------------------------------------------------------------------------------- 2384 ** | ATUBISTR | Header Type | Latency Timer | Cacheline Size | 0CH 2385 ** ---------------------------------------------------------------------------------------------------------- 2386 ** | Inbound ATU Base Address 0 | 10H 2387 ** ---------------------------------------------------------------------------------------------------------- 2388 ** | Inbound ATU Upper Base Address 0 | 14H 2389 ** ---------------------------------------------------------------------------------------------------------- 2390 ** | Inbound ATU Base Address 1 | 18H 2391 ** ---------------------------------------------------------------------------------------------------------- 2392 ** | Inbound ATU Upper Base Address 1 | 1CH 2393 ** ---------------------------------------------------------------------------------------------------------- 2394 ** | Inbound ATU Base Address 2 | 20H 2395 ** ---------------------------------------------------------------------------------------------------------- 2396 ** | Inbound ATU Upper Base Address 2 | 24H 2397 ** ---------------------------------------------------------------------------------------------------------- 2398 ** | Reserved | 28H 2399 ** ---------------------------------------------------------------------------------------------------------- 2400 ** | ATU Subsystem ID | ATU Subsystem Vendor ID | 2CH 2401 ** ---------------------------------------------------------------------------------------------------------- 2402 ** | Expansion ROM Base Address | 30H 2403 ** ---------------------------------------------------------------------------------------------------------- 2404 ** | Reserved Capabilities Pointer | 34H 2405 ** ---------------------------------------------------------------------------------------------------------- 2406 ** | Reserved | 38H 2407 ** ---------------------------------------------------------------------------------------------------------- 2408 ** | Maximum Latency | Minimum Grant | Interrupt Pin | Interrupt Line | 3CH 2409 ** ---------------------------------------------------------------------------------------------------------- 2410 ********************************************************************************************************************* 2411 */ 2412 /* 2413 *********************************************************************************** 2414 ** ATU Vendor ID Register - ATUVID 2415 ** ----------------------------------------------------------------- 2416 ** Bit Default Description 2417 ** 15:00 8086H (0x17D3) ATU Vendor ID - This is a 16-bit value assigned to Intel. 2418 ** This register, combined with the DID, uniquely identify the PCI device. 2419 ** Access type is Read/Write to allow the 80331 to configure the register as a different vendor ID 2420 ** to simulate the interface of a standard mechanism currently used by existing application software. 2421 *********************************************************************************** 2422 */ 2423 #define ARCMSR_ATU_VENDOR_ID_REG 0x00 /*word*/ 2424 /* 2425 *********************************************************************************** 2426 ** ATU Device ID Register - ATUDID 2427 ** ----------------------------------------------------------------- 2428 ** Bit Default Description 2429 ** 15:00 0336H (0x1110) ATU Device ID - This is a 16-bit value assigned to the ATU. 2430 ** This ID, combined with the VID, uniquely identify any PCI device. 2431 *********************************************************************************** 2432 */ 2433 #define ARCMSR_ATU_DEVICE_ID_REG 0x02 /*word*/ 2434 /* 2435 *********************************************************************************** 2436 ** ATU Command Register - ATUCMD 2437 ** ----------------------------------------------------------------- 2438 ** Bit Default Description 2439 ** 15:11 000000 2 Reserved 2440 ** 10 0 Interrupt Disable - This bit disables 80331 from asserting the ATU interrupt signal. 2441 ** 0=enables the assertion of interrupt signal. 2442 ** 1=disables the assertion of its interrupt signal. 2443 ** 09 0 2 Fast Back to Back Enable - When cleared, 2444 ** the ATU interface is not allowed to generate fast back-to-back cycles on its bus. 2445 ** Ignored when operating in the PCI-X mode. 2446 ** 08 0 2 SERR# Enable - When cleared, the ATU interface is not allowed to assert SERR# on the PCI interface. 2447 ** 07 1 2 Address/Data Stepping Control - Address stepping is implemented for configuration transactions. The 2448 ** ATU inserts 2 clock cycles of address stepping for Conventional Mode and 4 clock cycles 2449 ** of address stepping for PCI-X mode. 2450 ** 06 0 2 Parity Error Response - When set, the ATU takes normal action when a parity error 2451 ** is detected. When cleared, parity checking is disabled. 2452 ** 05 0 2 VGA Palette Snoop Enable - The ATU interface does not support I/O writes and therefore, 2453 ** does not perform VGA palette snooping. 2454 ** 04 0 2 Memory Write and Invalidate Enable - When set, ATU may generate MWI commands. 2455 ** When clear, ATU use Memory Write commands instead of MWI. Ignored when operating in the PCI-X mode. 2456 ** 03 0 2 Special Cycle Enable - The ATU interface does not respond to special cycle commands in any way. 2457 ** Not implemented and a reserved bit field. 2458 ** 02 0 2 Bus Master Enable - The ATU interface can act as a master on the PCI bus. 2459 ** When cleared, disables the device from generating PCI accesses. 2460 ** When set, allows the device to behave as a PCI bus master. 2461 ** When operating in the PCI-X mode, ATU initiates a split completion transaction regardless 2462 ** of the state of this bit. 2463 ** 01 0 2 Memory Enable - Controls the ATU interface��s response to PCI memory addresses. 2464 ** When cleared, the ATU interface does not respond to any memory access on the PCI bus. 2465 ** 00 0 2 I/O Space Enable - Controls the ATU interface response to I/O transactions. 2466 ** Not implemented and a reserved bit field. 2467 *********************************************************************************** 2468 */ 2469 #define ARCMSR_ATU_COMMAND_REG 0x04 /*word*/ 2470 /* 2471 *********************************************************************************** 2472 ** ATU Status Register - ATUSR (Sheet 1 of 2) 2473 ** ----------------------------------------------------------------- 2474 ** Bit Default Description 2475 ** 15 0 2 Detected Parity Error - set when a parity error is detected in data received by the ATU on the PCI bus even 2476 ** when the ATUCMD register��s Parity Error Response bit is cleared. Set under the following conditions: 2477 ** �E Write Data Parity Error when the ATU is a target (inbound write). 2478 ** �E Read Data Parity Error when the ATU is a requester (outbound read). 2479 ** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus ** ** ** (including one generated by the ATU). 2480 ** 14 0 2 SERR# Asserted - set when SERR# is asserted on the PCI bus by the ATU. 2481 ** 13 0 2 Master Abort - set when a transaction initiated by the ATU PCI master interface, ends in a Master-Abort 2482 ** or when the ATU receives a Master Abort Split Completion Error Message in PCI-X mode. 2483 ** 12 0 2 Target Abort (master) - set when a transaction initiated by the ATU PCI master interface, ends in a target 2484 ** abort or when the ATU receives a Target Abort Split Completion Error Message in PCI-X mode. 2485 ** 11 0 2 Target Abort (target) - set when the ATU interface, acting as a target, 2486 ** terminates the transaction on the PCI bus with a target abort. 2487 ** 10:09 01 2 DEVSEL# Timing - These bits are read-only and define the slowest DEVSEL# 2488 ** timing for a target device in Conventional PCI Mode regardless of the operating mode 2489 ** (except configuration accesses). 2490 ** 00 2=Fast 2491 ** 01 2=Medium 2492 ** 10 2=Slow 2493 ** 11 2=Reserved 2494 ** The ATU interface uses Medium timing. 2495 ** 08 0 2 Master Parity Error - The ATU interface sets this bit under the following conditions: 2496 ** �E The ATU asserted PERR# itself or the ATU observed PERR# asserted. 2497 ** �E And the ATU acted as the requester 2498 ** for the operation in which the error occurred. 2499 ** �E And the ATUCMD register��s Parity Error Response bit is set 2500 ** �E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message 2501 ** �E And the ATUCMD register��s Parity Error Response bit is set 2502 ** 07 1 2 (Conventional mode) 2503 ** 0 2 (PCI-X mode) 2504 ** Fast Back-to-Back - The ATU/Messaging Unit interface is capable of accepting fast back-to-back 2505 ** transactions in Conventional PCI mode when the transactions are not to the same target. Since fast 2506 ** back-to-back transactions do not exist in PCI-X mode, this bit is forced to 0 in the PCI-X mode. 2507 ** 06 0 2 UDF Supported - User Definable Features are not supported 2508 ** 05 1 2 66 MHz. Capable - 66 MHz operation is supported. 2509 ** 04 1 2 Capabilities - When set, this function implements extended capabilities. 2510 ** 03 0 Interrupt Status - reflects the state of the ATU interrupt 2511 ** when the Interrupt Disable bit in the command register is a 0. 2512 ** 0=ATU interrupt signal deasserted. 2513 ** 1=ATU interrupt signal asserted. 2514 ** NOTE: Setting the Interrupt Disable bit to a 1 has no effect on the state of this bit. Refer to 2515 ** Section 3.10.23, ��ATU Interrupt Pin Register - ATUIPR�� on page 236 for details on the ATU 2516 ** interrupt signal. 2517 ** 02:00 00000 2 Reserved. 2518 *********************************************************************************** 2519 */ 2520 #define ARCMSR_ATU_STATUS_REG 0x06 /*word*/ 2521 /* 2522 *********************************************************************************** 2523 ** ATU Revision ID Register - ATURID 2524 ** ----------------------------------------------------------------- 2525 ** Bit Default Description 2526 ** 07:00 00H ATU Revision - identifies the 80331 revision number. 2527 *********************************************************************************** 2528 */ 2529 #define ARCMSR_ATU_REVISION_REG 0x08 /*byte*/ 2530 /* 2531 *********************************************************************************** 2532 ** ATU Class Code Register - ATUCCR 2533 ** ----------------------------------------------------------------- 2534 ** Bit Default Description 2535 ** 23:16 05H Base Class - Memory Controller 2536 ** 15:08 80H Sub Class - Other Memory Controller 2537 ** 07:00 00H Programming Interface - None defined 2538 *********************************************************************************** 2539 */ 2540 #define ARCMSR_ATU_CLASS_CODE_REG 0x09 /*3bytes 0x0B,0x0A,0x09*/ 2541 /* 2542 *********************************************************************************** 2543 ** ATU Cacheline Size Register - ATUCLSR 2544 ** ----------------------------------------------------------------- 2545 ** Bit Default Description 2546 ** 07:00 00H ATU Cacheline Size - specifies the system cacheline size in DWORDs. Cacheline size is restricted to either 0, 8 or 16 DWORDs. 2547 *********************************************************************************** 2548 */ 2549 #define ARCMSR_ATU_CACHELINE_SIZE_REG 0x0C /*byte*/ 2550 /* 2551 *********************************************************************************** 2552 ** ATU Latency Timer Register - ATULT 2553 ** ----------------------------------------------------------------- 2554 ** Bit Default Description 2555 ** 07:03 00000 2 (for Conventional mode) 2556 ** 01000 2 (for PCI-X mode) 2557 ** Programmable Latency Timer - This field varies the latency timer for the interface from 0 to 248 clocks. 2558 ** The default value is 0 clocks for Conventional PCI mode, and 64 clocks for PCI-X mode. 2559 ** 02:00 000 2 Latency Timer Granularity - These Bits are read only giving a programmable granularity of 8 clocks for the latency timer. 2560 *********************************************************************************** 2561 */ 2562 #define ARCMSR_ATU_LATENCY_TIMER_REG 0x0D /*byte*/ 2563 /* 2564 *********************************************************************************** 2565 ** ATU Header Type Register - ATUHTR 2566 ** ----------------------------------------------------------------- 2567 ** Bit Default Description 2568 ** 07 0 2 Single Function/Multi-Function Device - Identifies the 80331 as a single-function PCI device. 2569 ** 06:00 000000 2 PCI Header Type - This bit field indicates the type of PCI header implemented. The ATU interface 2570 ** header conforms to PCI Local Bus Specification, Revision 2.3. 2571 *********************************************************************************** 2572 */ 2573 #define ARCMSR_ATU_HEADER_TYPE_REG 0x0E /*byte*/ 2574 /* 2575 *********************************************************************************** 2576 ** ATU BIST Register - ATUBISTR 2577 ** 2578 ** The ATU BIST Register controls the functions the Intel XScale core performs when BIST is 2579 ** initiated. This register is the interface between the host processor requesting BIST functions and 2580 ** the 80331 replying with the results from the software implementation of the BIST functionality. 2581 ** ----------------------------------------------------------------- 2582 ** Bit Default Description 2583 ** 07 0 2 BIST Capable - This bit value is always equal to the ATUCR ATU BIST Interrupt Enable bit. 2584 ** 06 0 2 Start BIST - When the ATUCR BIST Interrupt Enable bit is set: 2585 ** Setting this bit generates an interrupt to the Intel XScale core to perform a software BIST function. 2586 ** The Intel XScale core clears this bit when the BIST software has completed with the BIST results 2587 ** found in ATUBISTR register bits [3:0]. 2588 ** When the ATUCR BIST Interrupt Enable bit is clear: 2589 ** Setting this bit does not generate an interrupt to the Intel XScale core and no BIST functions is performed. 2590 ** The Intel XScale core does not clear this bit. 2591 ** 05:04 00 2 Reserved 2592 ** 03:00 0000 2 BIST Completion Code - when the ATUCR BIST Interrupt Enable bit is set and the ATUBISTR Start BIST bit is set (bit 6): 2593 ** The Intel XScale core places the results of the software BIST in these bits. 2594 ** A nonzero value indicates a device-specific error. 2595 *********************************************************************************** 2596 */ 2597 #define ARCMSR_ATU_BIST_REG 0x0F /*byte*/ 2598 2599 /* 2600 *************************************************************************************** 2601 ** ATU Base Registers and Associated Limit Registers 2602 *************************************************************************************** 2603 ** Base Address Register Limit Register Description 2604 ** Inbound ATU Base Address Register 0 Inbound ATU Limit Register 0 Defines the inbound translation window 0 from the PCI bus. 2605 ** Inbound ATU Upper Base Address Register 0 N/A Together with ATU Base Address Register 0 defines the inbound ** translation window 0 from the PCI bus for DACs. 2606 ** Inbound ATU Base Address Register 1 Inbound ATU Limit Register 1 Defines inbound window 1 from the PCI bus. 2607 ** Inbound ATU Upper Base Address Register 1 N/A Together with ATU Base Address Register 1 defines inbound window ** 1 from the PCI bus for DACs. 2608 ** Inbound ATU Base Address Register 2 Inbound ATU Limit Register 2 Defines the inbound translation window 2 from the PCI bus. 2609 ** Inbound ATU Upper Base Address Register 2 N/A Together with ATU Base Address Register 2 defines the inbound ** ** translation window 2 from the PCI bus for DACs. 2610 ** Inbound ATU Base Address Register 3 Inbound ATU Limit Register 3 Defines the inbound translation window 3 from the PCI bus. 2611 ** Inbound ATU Upper Base Address Register 3 N/A Together with ATU Base Address Register 3 defines the inbound ** ** translation window 3 from the PCI bus for DACs. 2612 ** NOTE: This is a private BAR that resides outside of the standard PCI configuration header space (offsets 00H-3FH). 2613 ** Expansion ROM Base Address Register Expansion ROM Limit Register Defines the window of addresses used by a bus master for reading ** from an Expansion ROM. 2614 **-------------------------------------------------------------------------------------- 2615 ** ATU Inbound Window 1 is not a translate window. 2616 ** The ATU does not claim any PCI accesses that fall within this range. 2617 ** This window is used to allocate host memory for use by Private Devices. 2618 ** When enabled, the ATU interrupts the Intel XScale core when either the IABAR1 register or the IAUBAR1 register is written from the PCI bus. 2619 *********************************************************************************** 2620 */ 2621 2622 /* 2623 *********************************************************************************** 2624 ** Inbound ATU Base Address Register 0 - IABAR0 2625 ** 2626 ** . The Inbound ATU Base Address Register 0 (IABAR0) together with the Inbound ATU Upper Base Address Register 0 (IAUBAR0) 2627 ** defines the block of memory addresses where the inbound translation window 0 begins. 2628 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 2629 ** . The IABAR0 and IAUBAR0 define the base address and describes the required memory block size. 2630 ** . Bits 31 through 12 of the IABAR0 is either read/write bits or read only with a value of 0 2631 ** depending on the value located within the IALR0. 2632 ** This configuration allows the IABAR0 to be programmed per PCI Local Bus Specification. 2633 ** The first 4 Kbytes of memory defined by the IABAR0, IAUBAR0 and the IALR0 is reserved for the Messaging Unit. 2634 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2635 ** Warning: 2636 ** When IALR0 is cleared prior to host configuration: 2637 ** the user should also clear the Prefetchable Indicator and the Type Indicator. 2638 ** Assuming IALR0 is not cleared: 2639 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 2640 ** when the Prefetchable Indicator is cleared prior to host configuration, 2641 ** the user should also set the Type Indicator for 32 bit addressability. 2642 ** b. For compliance to the PCI-X Addendum to the PCI Local Bus Specification, 2643 ** when the Prefetchable Indicator is set prior to host configuration, the user 2644 ** should also set the Type Indicator for 64 bit addressability. 2645 ** This is the default for IABAR0. 2646 ** ----------------------------------------------------------------- 2647 ** Bit Default Description 2648 ** 31:12 00000H Translation Base Address 0 - These bits define the actual location 2649 ** the translation function is to respond to when addressed from the PCI bus. 2650 ** 11:04 00H Reserved. 2651 ** 03 1 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 2652 ** 02:01 10 2 Type Indicator - Defines the width of the addressability for this memory window: 2653 ** 00 - Memory Window is locatable anywhere in 32 bit address space 2654 ** 10 - Memory Window is locatable anywhere in 64 bit address space 2655 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 2656 ** The ATU does not occupy I/O space, 2657 ** thus this bit must be zero. 2658 *********************************************************************************** 2659 */ 2660 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS0_REG 0x10 /*dword 0x13,0x12,0x11,0x10*/ 2661 #define ARCMSR_INBOUND_ATU_MEMORY_PREFETCHABLE 0x08 2662 #define ARCMSR_INBOUND_ATU_MEMORY_WINDOW64 0x04 2663 /* 2664 *********************************************************************************** 2665 ** Inbound ATU Upper Base Address Register 0 - IAUBAR0 2666 ** 2667 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 2668 ** Together with the Translation Base Address this register defines the actual location the translation 2669 ** function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 2670 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2671 ** Note: 2672 ** When the Type indicator of IABAR0 is set to indicate 32 bit addressability, 2673 ** the IAUBAR0 register attributes are read-only. 2674 ** ----------------------------------------------------------------- 2675 ** Bit Default Description 2676 ** 31:0 00000H Translation Upper Base Address 0 - Together with the Translation Base Address 0 these bits define the 2677 ** actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes. 2678 *********************************************************************************** 2679 */ 2680 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS0_REG 0x14 /*dword 0x17,0x16,0x15,0x14*/ 2681 /* 2682 *********************************************************************************** 2683 ** Inbound ATU Base Address Register 1 - IABAR1 2684 ** 2685 ** . The Inbound ATU Base Address Register (IABAR1) together with the Inbound ATU Upper Base Address Register 1 (IAUBAR1) 2686 ** defines the block of memory addresses where the inbound translation window 1 begins. 2687 ** . This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PCI bus transactions to this memory range. 2688 ** . The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2689 ** . When enabled, the ATU interrupts the Intel XScale core when the IABAR1 register is written from the PCI bus. 2690 ** Warning: 2691 ** When a non-zero value is not written to IALR1 prior to host configuration, 2692 ** the user should not set either the Prefetchable Indicator or the Type Indicator for 64 bit addressability. 2693 ** This is the default for IABAR1. 2694 ** Assuming a non-zero value is written to IALR1, 2695 ** the user may set the Prefetchable Indicator 2696 ** or the Type Indicator: 2697 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address 2698 ** boundary, when the Prefetchable Indicator is not set prior to host configuration, 2699 ** the user should also leave the Type Indicator set for 32 bit addressability. 2700 ** This is the default for IABAR1. 2701 ** b. when the Prefetchable Indicator is set prior to host configuration, 2702 ** the user should also set the Type Indicator for 64 bit addressability. 2703 ** ----------------------------------------------------------------- 2704 ** Bit Default Description 2705 ** 31:12 00000H Translation Base Address 1 - These bits define the actual location of window 1 on the PCI bus. 2706 ** 11:04 00H Reserved. 2707 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 2708 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 2709 ** 00 - Memory Window is locatable anywhere in 32 bit address space 2710 ** 10 - Memory Window is locatable anywhere in 64 bit address space 2711 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 2712 ** The ATU does not occupy I/O space, 2713 ** thus this bit must be zero. 2714 *********************************************************************************** 2715 */ 2716 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS1_REG 0x18 /*dword 0x1B,0x1A,0x19,0x18*/ 2717 /* 2718 *********************************************************************************** 2719 ** Inbound ATU Upper Base Address Register 1 - IAUBAR1 2720 ** 2721 ** This register contains the upper base address when locating this window for PCI addresses beyond 4 GBytes. 2722 ** Together with the IABAR1 this register defines the actual location for this memory window for addresses > 4GBytes (for DACs). 2723 ** This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PCI bus transactions to this memory range. 2724 ** The programmed value within the base address register must comply with the PCI programming 2725 ** requirements for address alignment. 2726 ** When enabled, the ATU interrupts the Intel XScale core when the IAUBAR1 register is written 2727 ** from the PCI bus. 2728 ** Note: 2729 ** When the Type indicator of IABAR1 is set to indicate 32 bit addressability, 2730 ** the IAUBAR1 register attributes are read-only. 2731 ** This is the default for IABAR1. 2732 ** ----------------------------------------------------------------- 2733 ** Bit Default Description 2734 ** 31:0 00000H Translation Upper Base Address 1 - Together with the Translation Base Address 1 2735 ** these bits define the actual location for this memory window on the PCI bus for addresses > 4GBytes. 2736 *********************************************************************************** 2737 */ 2738 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS1_REG 0x1C /*dword 0x1F,0x1E,0x1D,0x1C*/ 2739 /* 2740 *********************************************************************************** 2741 ** Inbound ATU Base Address Register 2 - IABAR2 2742 ** 2743 ** . The Inbound ATU Base Address Register 2 (IABAR2) together with the Inbound ATU Upper Base Address Register 2 (IAUBAR2) 2744 ** defines the block of memory addresses where the inbound translation window 2 begins. 2745 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 2746 ** . The IABAR2 and IAUBAR2 define the base address and describes the required memory block size 2747 ** . Bits 31 through 12 of the IABAR2 is either read/write bits or read only with a value of 0 depending on the value located within the IALR2. 2748 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2749 ** Warning: 2750 ** When a non-zero value is not written to IALR2 prior to host configuration, 2751 ** the user should not set either the Prefetchable Indicator 2752 ** or the Type Indicator for 64 bit addressability. 2753 ** This is the default for IABAR2. 2754 ** Assuming a non-zero value is written to IALR2, 2755 ** the user may set the Prefetchable Indicator 2756 ** or the Type Indicator: 2757 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 2758 ** when the Prefetchable Indicator is not set prior to host configuration, 2759 ** the user should also leave the Type Indicator set for 32 bit addressability. 2760 ** This is the default for IABAR2. 2761 ** b. when the Prefetchable Indicator is set prior to host configuration, 2762 ** the user should also set the Type Indicator for 64 bit addressability. 2763 ** ----------------------------------------------------------------- 2764 ** Bit Default Description 2765 ** 31:12 00000H Translation Base Address 2 - These bits define the actual location 2766 ** the translation function is to respond to when addressed from the PCI bus. 2767 ** 11:04 00H Reserved. 2768 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 2769 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 2770 ** 00 - Memory Window is locatable anywhere in 32 bit address space 2771 ** 10 - Memory Window is locatable anywhere in 64 bit address space 2772 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 2773 ** The ATU does not occupy I/O space, 2774 ** thus this bit must be zero. 2775 *********************************************************************************** 2776 */ 2777 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS2_REG 0x20 /*dword 0x23,0x22,0x21,0x20*/ 2778 /* 2779 *********************************************************************************** 2780 ** Inbound ATU Upper Base Address Register 2 - IAUBAR2 2781 ** 2782 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 2783 ** Together with the Translation Base Address this register defines the actual location 2784 ** the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 2785 ** The programmed value within the base address register must comply with the PCI programming 2786 ** requirements for address alignment. 2787 ** Note: 2788 ** When the Type indicator of IABAR2 is set to indicate 32 bit addressability, 2789 ** the IAUBAR2 register attributes are read-only. 2790 ** This is the default for IABAR2. 2791 ** ----------------------------------------------------------------- 2792 ** Bit Default Description 2793 ** 31:0 00000H Translation Upper Base Address 2 - Together with the Translation Base Address 2 2794 ** these bits define the actual location the translation function is to respond to 2795 ** when addressed from the PCI bus for addresses > 4GBytes. 2796 *********************************************************************************** 2797 */ 2798 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS2_REG 0x24 /*dword 0x27,0x26,0x25,0x24*/ 2799 /* 2800 *********************************************************************************** 2801 ** ATU Subsystem Vendor ID Register - ASVIR 2802 ** ----------------------------------------------------------------- 2803 ** Bit Default Description 2804 ** 15:0 0000H Subsystem Vendor ID - This register uniquely identifies the add-in board or subsystem vendor. 2805 *********************************************************************************** 2806 */ 2807 #define ARCMSR_ATU_SUBSYSTEM_VENDOR_ID_REG 0x2C /*word 0x2D,0x2C*/ 2808 /* 2809 *********************************************************************************** 2810 ** ATU Subsystem ID Register - ASIR 2811 ** ----------------------------------------------------------------- 2812 ** Bit Default Description 2813 ** 15:0 0000H Subsystem ID - uniquely identifies the add-in board or subsystem. 2814 *********************************************************************************** 2815 */ 2816 #define ARCMSR_ATU_SUBSYSTEM_ID_REG 0x2E /*word 0x2F,0x2E*/ 2817 /* 2818 *********************************************************************************** 2819 ** Expansion ROM Base Address Register -ERBAR 2820 ** ----------------------------------------------------------------- 2821 ** Bit Default Description 2822 ** 31:12 00000H Expansion ROM Base Address - These bits define the actual location 2823 ** where the Expansion ROM address window resides when addressed from the PCI bus on any 4 Kbyte boundary. 2824 ** 11:01 000H Reserved 2825 ** 00 0 2 Address Decode Enable - This bit field shows the ROM address 2826 ** decoder is enabled or disabled. When cleared, indicates the address decoder is disabled. 2827 *********************************************************************************** 2828 */ 2829 #define ARCMSR_EXPANSION_ROM_BASE_ADDRESS_REG 0x30 /*dword 0x33,0x32,0v31,0x30*/ 2830 #define ARCMSR_EXPANSION_ROM_ADDRESS_DECODE_ENABLE 0x01 2831 /* 2832 *********************************************************************************** 2833 ** ATU Capabilities Pointer Register - ATU_CAP_PTR 2834 ** ----------------------------------------------------------------- 2835 ** Bit Default Description 2836 ** 07:00 C0H Capability List Pointer - This provides an offset in this function��s configuration space 2837 ** that points to the 80331 PCl Bus Power Management extended capability. 2838 *********************************************************************************** 2839 */ 2840 #define ARCMSR_ATU_CAPABILITY_PTR_REG 0x34 /*byte*/ 2841 /* 2842 *********************************************************************************** 2843 ** Determining Block Sizes for Base Address Registers 2844 ** The required address size and type can be determined by writing ones to a base address register and 2845 ** reading from the registers. By scanning the returned value from the least-significant bit of the base 2846 ** address registers upwards, the programmer can determine the required address space size. The 2847 ** binary-weighted value of the first non-zero bit found indicates the required amount of space. 2848 ** Table 105 describes the relationship between the values read back and the byte sizes the base 2849 ** address register requires. 2850 ** As an example, assume that FFFF.FFFFH is written to the ATU Inbound Base Address Register 0 2851 ** (IABAR0) and the value read back is FFF0.0008H. Bit zero is a zero, so the device requires 2852 ** memory address space. Bit three is one, so the memory does supports prefetching. Scanning 2853 ** upwards starting at bit four, bit twenty is the first one bit found. The binary-weighted value of this 2854 ** bit is 1,048,576, indicated that the device requires 1 Mbyte of memory space. 2855 ** The ATU Base Address Registers and the Expansion ROM Base Address Register use their 2856 ** associated limit registers to enable which bits within the base address register are read/write and 2857 ** which bits are read only (0). This allows the programming of these registers in a manner similar to 2858 ** other PCI devices even though the limit is variable. 2859 ** Table 105. Memory Block Size Read Response 2860 ** Response After Writing all 1s 2861 ** to the Base Address Register 2862 ** Size 2863 ** (Bytes) 2864 ** Response After Writing all 1s 2865 ** to the Base Address Register 2866 ** Size 2867 ** (Bytes) 2868 ** FFFFFFF0H 16 FFF00000H 1 M 2869 ** FFFFFFE0H 32 FFE00000H 2 M 2870 ** FFFFFFC0H 64 FFC00000H 4 M 2871 ** FFFFFF80H 128 FF800000H 8 M 2872 ** FFFFFF00H 256 FF000000H 16 M 2873 ** FFFFFE00H 512 FE000000H 32 M 2874 ** FFFFFC00H 1K FC000000H 64 M 2875 ** FFFFF800H 2K F8000000H 128 M 2876 ** FFFFF000H 4K F0000000H 256 M 2877 ** FFFFE000H 8K E0000000H 512 M 2878 ** FFFFC000H 16K C0000000H 1 G 2879 ** FFFF8000H 32K 80000000H 2 G 2880 ** FFFF0000H 64K 2881 ** 00000000H 2882 ** Register not 2883 ** imple-mented, 2884 ** no 2885 ** address 2886 ** space 2887 ** required. 2888 ** FFFE0000H 128K 2889 ** FFFC0000H 256K 2890 ** FFF80000H 512K 2891 ** 2892 *************************************************************************************** 2893 */ 2894 2895 2896 2897 /* 2898 *********************************************************************************** 2899 ** ATU Interrupt Line Register - ATUILR 2900 ** ----------------------------------------------------------------- 2901 ** Bit Default Description 2902 ** 07:00 FFH Interrupt Assigned - system-assigned value identifies which system interrupt controller��s interrupt 2903 ** request line connects to the device's PCI interrupt request lines 2904 ** (as specified in the interrupt pin register). 2905 ** A value of FFH signifies ��no connection�� or ��unknown��. 2906 *********************************************************************************** 2907 */ 2908 #define ARCMSR_ATU_INTERRUPT_LINE_REG 0x3C /*byte*/ 2909 /* 2910 *********************************************************************************** 2911 ** ATU Interrupt Pin Register - ATUIPR 2912 ** ----------------------------------------------------------------- 2913 ** Bit Default Description 2914 ** 07:00 01H Interrupt Used - A value of 01H signifies that the ATU interface unit uses INTA# as the interrupt pin. 2915 *********************************************************************************** 2916 */ 2917 #define ARCMSR_ATU_INTERRUPT_PIN_REG 0x3D /*byte*/ 2918 /* 2919 *********************************************************************************** 2920 ** ATU Minimum Grant Register - ATUMGNT 2921 ** ----------------------------------------------------------------- 2922 ** Bit Default Description 2923 ** 07:00 80H This register specifies how long a burst period the device needs in increments of 8 PCI clocks. 2924 *********************************************************************************** 2925 */ 2926 #define ARCMSR_ATU_MINIMUM_GRANT_REG 0x3E /*byte*/ 2927 /* 2928 *********************************************************************************** 2929 ** ATU Maximum Latency Register - ATUMLAT 2930 ** ----------------------------------------------------------------- 2931 ** Bit Default Description 2932 ** 07:00 00H Specifies frequency (how often) the device needs to access the PCI bus 2933 ** in increments of 8 PCI clocks. A zero value indicates the device has no stringent requirement. 2934 *********************************************************************************** 2935 */ 2936 #define ARCMSR_ATU_MAXIMUM_LATENCY_REG 0x3F /*byte*/ 2937 /* 2938 *********************************************************************************** 2939 ** Inbound Address Translation 2940 ** 2941 ** The ATU allows external PCI bus initiators to directly access the internal bus. 2942 ** These PCI bus initiators can read or write 80331 memory-mapped registers or 80331 local memory space. 2943 ** The process of inbound address translation involves two steps: 2944 ** 1. Address Detection. 2945 ** �E Determine when the 32-bit PCI address (64-bit PCI address during DACs) is 2946 ** within the address windows defined for the inbound ATU. 2947 ** �E Claim the PCI transaction with medium DEVSEL# timing in the conventional PCI 2948 ** mode and with Decode A DEVSEL# timing in the PCI-X mode. 2949 ** 2. Address Translation. 2950 ** �E Translate the 32-bit PCI address (lower 32-bit PCI address during DACs) to a 32-bit 80331 internal bus address. 2951 ** The ATU uses the following registers in inbound address window 0 translation: 2952 ** �E Inbound ATU Base Address Register 0 2953 ** �E Inbound ATU Limit Register 0 2954 ** �E Inbound ATU Translate Value Register 0 2955 ** The ATU uses the following registers in inbound address window 2 translation: 2956 ** �E Inbound ATU Base Address Register 2 2957 ** �E Inbound ATU Limit Register 2 2958 ** �E Inbound ATU Translate Value Register 2 2959 ** The ATU uses the following registers in inbound address window 3 translation: 2960 ** �E Inbound ATU Base Address Register 3 2961 ** �E Inbound ATU Limit Register 3 2962 ** �E Inbound ATU Translate Value Register 3 2963 ** Note: Inbound Address window 1 is not a translate window. 2964 ** Instead, window 1 may be used to allocate host memory for Private Devices. 2965 ** Inbound Address window 3 does not reside in the standard section of the configuration header (offsets 00H - 3CH), 2966 ** thus the host BIOS does not configure window 3. 2967 ** Window 3 is intended to be used as a special window into local memory for private PCI 2968 ** agents controlled by the 80331 in conjunction with the Private Memory Space of the bridge. 2969 ** PCI-to-PCI Bridge in 80331 or 2970 ** Inbound address detection is determined from the 32-bit PCI address, 2971 ** (64-bit PCI address during DACs) the base address register and the limit register. 2972 ** In the case of DACs none of the upper 32-bits of the address is masked during address comparison. 2973 ** 2974 ** The algorithm for detection is: 2975 ** 2976 ** Equation 1. Inbound Address Detection 2977 ** When (PCI_Address [31:0] & Limit_Register[31:0]) == (Base_Register[31:0] & PCI_Address [63:32]) == Base_Register[63:32] (for DACs only) 2978 ** the PCI Address is claimed by the Inbound ATU. 2979 ** 2980 ** The incoming 32-bit PCI address (lower 32-bits of the address in case of DACs) is bitwise ANDed 2981 ** with the associated inbound limit register. 2982 ** When the result matches the base register (and upper base address matches upper PCI address in case of DACs), 2983 ** the inbound PCI address is detected as being within the inbound translation window and is claimed by the ATU. 2984 ** 2985 ** Note: The first 4 Kbytes of the ATU inbound address translation window 0 are reserved for the Messaging Unit. 2986 ** Once the transaction is claimed, the address must be translated from a PCI address to a 32-bit 2987 ** internal bus address. In case of DACs upper 32-bits of the address is simply discarded and only the 2988 ** lower 32-bits are used during address translation. 2989 ** The algorithm is: 2990 ** 2991 ** 2992 ** Equation 2. Inbound Translation 2993 ** Intel I/O processor Internal Bus Address=(PCI_Address[31:0] & ~Limit_Register[31:0]) | ATU_Translate_Value_Register[31:0]. 2994 ** 2995 ** The incoming 32-bit PCI address (lower 32-bits in case of DACs) is first bitwise ANDed with the 2996 ** bitwise inverse of the limit register. This result is bitwise ORed with the ATU Translate Value and 2997 ** the result is the internal bus address. This translation mechanism is used for all inbound memory 2998 ** read and write commands excluding inbound configuration read and writes. 2999 ** In the PCI mode for inbound memory transactions, the only burst order supported is Linear 3000 ** Incrementing. For any other burst order, the ATU signals a Disconnect after the first data phase. 3001 ** The PCI-X supports linear incrementing only, and hence above situation is not encountered in the PCI-X mode. 3002 ** example: 3003 ** Register Values 3004 ** Base_Register=3A00 0000H 3005 ** Limit_Register=FF80 0000H (8 Mbyte limit value) 3006 ** Value_Register=B100 0000H 3007 ** Inbound Translation Window ranges from 3A00 0000H to 3A7F FFFFH (8 Mbytes) 3008 ** 3009 ** Address Detection (32-bit address) 3010 ** 3011 ** PCI_Address & Limit_Register == Base_Register 3012 ** 3A45 012CH & FF80 0000H == 3A00 0000H 3013 ** 3014 ** ANS: PCI_Address is in the Inbound Translation Window 3015 ** Address Translation (to get internal bus address) 3016 ** 3017 ** IB_Address=(PCI_Address & ~Limit_Register) | Value_Reg 3018 ** IB_Address=(3A45 012CH & 007F FFFFH) | B100 0000H 3019 ** 3020 ** ANS:IB_Address=B145 012CH 3021 *********************************************************************************** 3022 */ 3023 3024 3025 3026 /* 3027 *********************************************************************************** 3028 ** Inbound ATU Limit Register 0 - IALR0 3029 ** 3030 ** Inbound address translation for memory window 0 occurs for data transfers occurring from the PCI 3031 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 3032 ** PCI addresses to internal bus addresses. 3033 ** The 80331 translate value register��s programmed value must be naturally aligned with the base 3034 ** address register��s programmed value. The limit register is used as a mask; thus, the lower address 3035 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 3036 ** Specification, Revision 2.3 for additional information on programming base address registers. 3037 ** Bits 31 to 12 within the IALR0 have a direct effect on the IABAR0 register, bits 31 to 12, with a 3038 ** one to one correspondence. A value of 0 in a bit within the IALR0 makes the corresponding bit 3039 ** within the IABAR0 a read only bit which always returns 0. A value of 1 in a bit within the IALR0 3040 ** makes the corresponding bit within the IABAR0 read/write from PCI. Note that a consequence of 3041 ** this programming scheme is that unless a valid value exists within the IALR0, all writes to the 3042 ** IABAR0 has no effect since a value of all zeros within the IALR0 makes the IABAR0 a read only register. 3043 ** ----------------------------------------------------------------- 3044 ** Bit Default Description 3045 ** 31:12 FF000H Inbound Translation Limit 0 - This readback value determines the memory block size required for 3046 ** inbound memory window 0 of the address translation unit. This defaults to an inbound window of 16MB. 3047 ** 11:00 000H Reserved 3048 *********************************************************************************** 3049 */ 3050 #define ARCMSR_INBOUND_ATU_LIMIT0_REG 0x40 /*dword 0x43,0x42,0x41,0x40*/ 3051 /* 3052 *********************************************************************************** 3053 ** Inbound ATU Translate Value Register 0 - IATVR0 3054 ** 3055 ** The Inbound ATU Translate Value Register 0 (IATVR0) contains the internal bus address used to 3056 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 3057 ** inbound ATU address translation. 3058 ** ----------------------------------------------------------------- 3059 ** Bit Default Description 3060 ** 31:12 FF000H Inbound ATU Translation Value 0 - This value is used to convert the PCI address to internal bus addresses. 3061 ** This value must be 64-bit aligned on the internal bus. 3062 ** The default address allows the ATU to access the internal 80331 memory-mapped registers. 3063 ** 11:00 000H Reserved 3064 *********************************************************************************** 3065 */ 3066 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE0_REG 0x44 /*dword 0x47,0x46,0x45,0x44*/ 3067 /* 3068 *********************************************************************************** 3069 ** Expansion ROM Limit Register - ERLR 3070 ** 3071 ** The Expansion ROM Limit Register (ERLR) defines the block size of addresses the ATU defines 3072 ** as Expansion ROM address space. The block size is programmed by writing a value into the ERLR. 3073 ** Bits 31 to 12 within the ERLR have a direct effect on the ERBAR register, bits 31 to 12, with a one 3074 ** to one correspondence. A value of 0 in a bit within the ERLR makes the corresponding bit within 3075 ** the ERBAR a read only bit which always returns 0. A value of 1 in a bit within the ERLR makes 3076 ** the corresponding bit within the ERBAR read/write from PCI. 3077 ** ----------------------------------------------------------------- 3078 ** Bit Default Description 3079 ** 31:12 000000H Expansion ROM Limit - Block size of memory required for the Expansion ROM translation unit. Default 3080 ** value is 0, which indicates no Expansion ROM address space and all bits within the ERBAR are read only with a value of 0. 3081 ** 11:00 000H Reserved. 3082 *********************************************************************************** 3083 */ 3084 #define ARCMSR_EXPANSION_ROM_LIMIT_REG 0x48 /*dword 0x4B,0x4A,0x49,0x48*/ 3085 /* 3086 *********************************************************************************** 3087 ** Expansion ROM Translate Value Register - ERTVR 3088 ** 3089 ** The Expansion ROM Translate Value Register contains the 80331 internal bus address which the 3090 ** ATU converts the PCI bus access. This address is driven on the internal bus as a result of the 3091 ** Expansion ROM address translation. 3092 ** ----------------------------------------------------------------- 3093 ** Bit Default Description 3094 ** 31:12 00000H Expansion ROM Translation Value - Used to convert PCI addresses to 80331 internal bus addresses 3095 ** for Expansion ROM accesses. The Expansion ROM address translation value must be word aligned on the internal bus. 3096 ** 11:00 000H Reserved 3097 *********************************************************************************** 3098 */ 3099 #define ARCMSR_EXPANSION_ROM_TRANSLATE_VALUE_REG 0x4C /*dword 0x4F,0x4E,0x4D,0x4C*/ 3100 /* 3101 *********************************************************************************** 3102 ** Inbound ATU Limit Register 1 - IALR1 3103 ** 3104 ** Bits 31 to 12 within the IALR1 have a direct effect on the IABAR1 register, bits 31 to 12, with a 3105 ** one to one correspondence. A value of 0 in a bit within the IALR1 makes the corresponding bit 3106 ** within the IABAR1 a read only bit which always returns 0. A value of 1 in a bit within the IALR1 3107 ** makes the corresponding bit within the IABAR1 read/write from PCI. Note that a consequence of 3108 ** this programming scheme is that unless a valid value exists within the IALR1, all writes to the 3109 ** IABAR1 has no effect since a value of all zeros within the IALR1 makes the IABAR1 a read only 3110 ** register. 3111 ** The inbound memory window 1 is used merely to allocate memory on the PCI bus. The ATU does 3112 ** not process any PCI bus transactions to this memory range. 3113 ** Warning: The ATU does not claim any PCI accesses that fall within the range defined by IABAR1, 3114 ** IAUBAR1, and IALR1. 3115 ** ----------------------------------------------------------------- 3116 ** Bit Default Description 3117 ** 31:12 00000H Inbound Translation Limit 1 - This readback value determines the memory block size 3118 ** required for the ATUs memory window 1. 3119 ** 11:00 000H Reserved 3120 *********************************************************************************** 3121 */ 3122 #define ARCMSR_INBOUND_ATU_LIMIT1_REG 0x50 /*dword 0x53,0x52,0x51,0x50*/ 3123 /* 3124 *********************************************************************************** 3125 ** Inbound ATU Limit Register 2 - IALR2 3126 ** 3127 ** Inbound address translation for memory window 2 occurs for data transfers occurring from the PCI 3128 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 3129 ** PCI addresses to internal bus addresses. 3130 ** The inbound translation base address for inbound window 2 is specified in Section 3.10.15. When 3131 ** determining block size requirements �X as described in Section 3.10.21 �X the translation limit 3132 ** register provides the block size requirements for the base address register. The remaining registers 3133 ** used for performing address translation are discussed in Section 3.2.1.1. 3134 ** The 80331 translate value register��s programmed value must be naturally aligned with the base 3135 ** address register��s programmed value. The limit register is used as a mask; thus, the lower address 3136 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 3137 ** Specification, Revision 2.3 for additional information on programming base address registers. 3138 ** Bits 31 to 12 within the IALR2 have a direct effect on the IABAR2 register, bits 31 to 12, with a 3139 ** one to one correspondence. A value of 0 in a bit within the IALR2 makes the corresponding bit 3140 ** within the IABAR2 a read only bit which always returns 0. A value of 1 in a bit within the IALR2 3141 ** makes the corresponding bit within the IABAR2 read/write from PCI. Note that a consequence of 3142 ** this programming scheme is that unless a valid value exists within the IALR2, all writes to the 3143 ** IABAR2 has no effect since a value of all zeros within the IALR2 makes the IABAR2 a read only 3144 ** register. 3145 ** ----------------------------------------------------------------- 3146 ** Bit Default Description 3147 ** 31:12 00000H Inbound Translation Limit 2 - This readback value determines the memory block size 3148 ** required for the ATUs memory window 2. 3149 ** 11:00 000H Reserved 3150 *********************************************************************************** 3151 */ 3152 #define ARCMSR_INBOUND_ATU_LIMIT2_REG 0x54 /*dword 0x57,0x56,0x55,0x54*/ 3153 /* 3154 *********************************************************************************** 3155 ** Inbound ATU Translate Value Register 2 - IATVR2 3156 ** 3157 ** The Inbound ATU Translate Value Register 2 (IATVR2) contains the internal bus address used to 3158 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 3159 ** inbound ATU address translation. 3160 ** ----------------------------------------------------------------- 3161 ** Bit Default Description 3162 ** 31:12 00000H Inbound ATU Translation Value 2 - This value is used to convert the PCI address to internal bus addresses. 3163 ** This value must be 64-bit aligned on the internal bus. 3164 ** The default address allows the ATU to access the internal 80331 ** ** memory-mapped registers. 3165 ** 11:00 000H Reserved 3166 *********************************************************************************** 3167 */ 3168 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE2_REG 0x58 /*dword 0x5B,0x5A,0x59,0x58*/ 3169 /* 3170 *********************************************************************************** 3171 ** Outbound I/O Window Translate Value Register - OIOWTVR 3172 ** 3173 ** The Outbound I/O Window Translate Value Register (OIOWTVR) contains the PCI I/O address 3174 ** used to convert the internal bus access to a PCI address. This address is driven on the PCI bus as a 3175 ** result of the outbound ATU address translation. 3176 ** The I/O window is from 80331 internal bus address 9000 000H to 9000 FFFFH with the fixed 3177 ** length of 64 Kbytes. 3178 ** ----------------------------------------------------------------- 3179 ** Bit Default Description 3180 ** 31:16 0000H Outbound I/O Window Translate Value - Used to convert internal bus addresses to PCI addresses. 3181 ** 15:00 0000H Reserved 3182 *********************************************************************************** 3183 */ 3184 #define ARCMSR_OUTBOUND_IO_WINDOW_TRANSLATE_VALUE_REG 0x5C /*dword 0x5F,0x5E,0x5D,0x5C*/ 3185 /* 3186 *********************************************************************************** 3187 ** Outbound Memory Window Translate Value Register 0 -OMWTVR0 3188 ** 3189 ** The Outbound Memory Window Translate Value Register 0 (OMWTVR0) contains the PCI 3190 ** address used to convert 80331 internal bus addresses for outbound transactions. This address is 3191 ** driven on the PCI bus as a result of the outbound ATU address translation. 3192 ** The memory window is from internal bus address 8000 000H to 83FF FFFFH with the fixed length 3193 ** of 64 Mbytes. 3194 ** ----------------------------------------------------------------- 3195 ** Bit Default Description 3196 ** 31:26 00H Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses. 3197 ** 25:02 00 0000H Reserved 3198 ** 01:00 00 2 Burst Order - This bit field shows the address sequence during a memory burst. 3199 ** Only linear incrementing mode is supported. 3200 *********************************************************************************** 3201 */ 3202 #define ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x60 /*dword 0x63,0x62,0x61,0x60*/ 3203 /* 3204 *********************************************************************************** 3205 ** Outbound Upper 32-bit Memory Window Translate Value Register 0 - OUMWTVR0 3206 ** 3207 ** The Outbound Upper 32-bit Memory Window Translate Value Register 0 (OUMWTVR0) defines 3208 ** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to 3209 ** directly address anywhere within the 64-bit host address space. When this register is all-zero, then 3210 ** a SAC is generated on the PCI bus. 3211 ** The memory window is from internal bus address 8000 000H to 83FF FFFFH with the fixed 3212 ** length of 64 Mbytes. 3213 ** ----------------------------------------------------------------- 3214 ** Bit Default Description 3215 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 3216 *********************************************************************************** 3217 */ 3218 #define ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x64 /*dword 0x67,0x66,0x65,0x64*/ 3219 /* 3220 *********************************************************************************** 3221 ** Outbound Memory Window Translate Value Register 1 -OMWTVR1 3222 ** 3223 ** The Outbound Memory Window Translate Value Register 1 (OMWTVR1) contains the PCI 3224 ** address used to convert 80331 internal bus addresses for outbound transactions. This address is 3225 ** driven on the PCI bus as a result of the outbound ATU address translation. 3226 ** The memory window is from internal bus address 8400 000H to 87FF FFFFH with the fixed length 3227 ** of 64 Mbytes. 3228 ** ----------------------------------------------------------------- 3229 ** Bit Default Description 3230 ** 31:26 00H Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses. 3231 ** 25:02 00 0000H Reserved 3232 ** 01:00 00 2 Burst Order - This bit field shows the address sequence during a memory burst. 3233 ** Only linear incrementing mode is supported. 3234 *********************************************************************************** 3235 */ 3236 #define ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x68 /*dword 0x6B,0x6A,0x69,0x68*/ 3237 /* 3238 *********************************************************************************** 3239 ** Outbound Upper 32-bit Memory Window Translate Value Register 1 - OUMWTVR1 3240 ** 3241 ** The Outbound Upper 32-bit Memory Window Translate Value Register 1 (OUMWTVR1) defines 3242 ** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to 3243 ** directly address anywhere within the 64-bit host address space. When this register is all-zero, then 3244 ** a SAC is generated on the PCI bus. 3245 ** The memory window is from internal bus address 8400 000H to 87FF FFFFH with the fixed length 3246 ** of 64 Mbytes. 3247 ** ----------------------------------------------------------------- 3248 ** Bit Default Description 3249 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 3250 *********************************************************************************** 3251 */ 3252 #define ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x6C /*dword 0x6F,0x6E,0x6D,0x6C*/ 3253 /* 3254 *********************************************************************************** 3255 ** Outbound Upper 32-bit Direct Window Translate Value Register - OUDWTVR 3256 ** 3257 ** The Outbound Upper 32-bit Direct Window Translate Value Register (OUDWTVR) defines the 3258 ** upper 32-bits of address used during a dual address cycle for the transactions via Direct Addressing 3259 ** Window. This enables the outbound ATU to directly address anywhere within the 64-bit host 3260 ** address space. When this register is all-zero, then a SAC is generated on the PCI bus. 3261 ** ----------------------------------------------------------------- 3262 ** Bit Default Description 3263 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 3264 *********************************************************************************** 3265 */ 3266 #define ARCMSR_OUTBOUND_UPPER32_DIRECT_WINDOW_TRANSLATE_VALUE_REG 0x78 /*dword 0x7B,0x7A,0x79,0x78*/ 3267 /* 3268 *********************************************************************************** 3269 ** ATU Configuration Register - ATUCR 3270 ** 3271 ** The ATU Configuration Register controls the outbound address translation for address translation 3272 ** unit. It also contains bits for Conventional PCI Delayed Read Command (DRC) aliasing, discard 3273 ** timer status, SERR# manual assertion, SERR# detection interrupt masking, and ATU BIST 3274 ** interrupt enabling. 3275 ** ----------------------------------------------------------------- 3276 ** Bit Default Description 3277 ** 31:20 00H Reserved 3278 ** 19 0 2 ATU DRC Alias - when set, the ATU does not distinguish read commands when attempting to match a 3279 ** current PCI read transaction with read data enqueued within the DRC buffer. When clear, a current read 3280 ** transaction must have the exact same read command as the DRR for the ATU to deliver DRC data. Not 3281 ** applicable in the PCI-X mode. 3282 ** 18 0 2 Direct Addressing Upper 2Gbytes Translation Enable - When set, 3283 ** with Direct Addressing enabled (bit 7 of the ATUCR set), 3284 ** the ATU forwards internal bus cycles with an address between 0000.0040H and 3285 ** 7FFF.FFFFH to the PCI bus with bit 31 of the address set (8000.0000H - FFFF.FFFFH). 3286 ** When clear, no translation occurs. 3287 ** 17 0 2 Reserved 3288 ** 16 0 2 SERR# Manual Assertion - when set, the ATU asserts SERR# for one clock on the PCI interface. Until 3289 ** cleared, SERR# may not be manually asserted again. Once cleared, operation proceeds as specified. 3290 ** 15 0 2 ATU Discard Timer Status - when set, one of the 4 discard timers within the ATU has expired and 3291 ** discarded the delayed completion transaction within the queue. When clear, no timer has expired. 3292 ** 14:10 00000 2 Reserved 3293 ** 09 0 2 SERR# Detected Interrupt Enable - When set, the Intel XScale core is signalled an HPI# interrupt 3294 ** when the ATU detects that SERR# was asserted. When clear, 3295 ** the Intel XScale core is not interrupted when SERR# is detected. 3296 ** 08 0 2 Direct Addressing Enable - Setting this bit enables direct outbound addressing through the ATU. 3297 ** Internal bus cycles with an address between 0000.0040H and 7FFF.FFFFH automatically forwards to 3298 ** the PCI bus with or without translation of address bit 31 based on the setting of bit 18 of 3299 ** the ATUCR. 3300 ** 07:04 0000 2 Reserved 3301 ** 03 0 2 ATU BIST Interrupt Enable - When set, enables an interrupt to the Intel XScale core when the start 3302 ** BIST bit is set in the ATUBISTR register. This bit is also reflected as the BIST Capable bit 7 3303 ** in the ATUBISTR register. 3304 ** 02 0 2 Reserved 3305 ** 01 0 2 Outbound ATU Enable - When set, enables the outbound address translation unit. 3306 ** When cleared, disables the outbound ATU. 3307 ** 00 0 2 Reserved 3308 *********************************************************************************** 3309 */ 3310 #define ARCMSR_ATU_CONFIGURATION_REG 0x80 /*dword 0x83,0x82,0x81,0x80*/ 3311 /* 3312 *********************************************************************************** 3313 ** PCI Configuration and Status Register - PCSR 3314 ** 3315 ** The PCI Configuration and Status Register has additional bits for controlling and monitoring 3316 ** various features of the PCI bus interface. 3317 ** ----------------------------------------------------------------- 3318 ** Bit Default Description 3319 ** 31:19 0000H Reserved 3320 ** 18 0 2 Detected Address or Attribute Parity Error - set when a parity error is detected during either the address 3321 ** or attribute phase of a transaction on the PCI bus even when the ATUCMD register Parity Error 3322 ** Response bit is cleared. Set under the following conditions: 3323 ** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus (including one generated by the ATU). 3324 ** 17:16 Varies with 3325 ** external state 3326 ** of DEVSEL#, 3327 ** STOP#, and 3328 ** TRDY#, 3329 ** during 3330 ** P_RST# 3331 ** PCI-X capability - These two bits define the mode of 3332 ** the PCI bus (conventional or PCI-X) as well as the 3333 ** operating frequency in the case of PCI-X mode. 3334 ** 00 - Conventional PCI mode 3335 ** 01 - PCI-X 66 3336 ** 10 - PCI-X 100 3337 ** 11 - PCI-X 133 3338 ** As defined by the PCI-X Addendum to the PCI Local Bus Specification, 3339 ** Revision 1.0a, the operating 3340 ** mode is determined by an initialization pattern on the PCI bus during 3341 ** P_RST# assertion: 3342 ** DEVSEL# STOP# TRDY# Mode 3343 ** Deasserted Deasserted Deasserted Conventional 3344 ** Deasserted Deasserted Asserted PCI-X 66 3345 ** Deasserted Asserted Deasserted PCI-X 100 3346 ** Deasserted Asserted Asserted PCI-X 133 3347 ** All other patterns are reserved. 3348 ** 15 0 2 3349 ** Outbound Transaction Queue Busy: 3350 ** 0=Outbound Transaction Queue Empty 3351 ** 1=Outbound Transaction Queue Busy 3352 ** 14 0 2 3353 ** Inbound Transaction Queue Busy: 3354 ** 0=Inbound Transaction Queue Empty 3355 ** 1=Inbound Transaction Queue Busy 3356 ** 13 0 2 Reserved. 3357 ** 12 0 2 Discard Timer Value - This bit controls the time-out value 3358 ** for the four discard timers attached to the queues holding read data. 3359 ** A value of 0 indicates the time-out value is 2 15 clocks. 3360 ** A value of 1 indicates the time-out value is 2 10 clocks. 3361 ** 11 0 2 Reserved. 3362 ** 10 Varies with 3363 ** external state 3364 ** of M66EN 3365 ** during 3366 ** P_RST# 3367 ** Bus Operating at 66 MHz - When set, the interface has been initialized to function at 66 MHz in 3368 ** Conventional PCI mode by the assertion of M66EN during bus initialization. 3369 ** When clear, the interface 3370 ** has been initialized as a 33 MHz bus. 3371 ** NOTE: When PCSR bits 17:16 are not equal to zero, then this bit is meaningless since the 80331 is operating in PCI-X mode. 3372 ** 09 0 2 Reserved 3373 ** 08 Varies with 3374 ** external state 3375 ** of REQ64# 3376 ** during 3377 ** P_RST# 3378 ** PCI Bus 64-Bit Capable - When clear, the PCI bus interface has been 3379 ** configured as 64-bit capable by 3380 ** the assertion of REQ64# on the rising edge of P_RST#. When set, 3381 ** the PCI interface is configured as 3382 ** 32-bit only. 3383 ** 07:06 00 2 Reserved. 3384 ** 05 0 2 Reset Internal Bus - This bit controls the reset of the Intel XScale core 3385 ** and all units on the internal 3386 ** bus. In addition to the internal bus initialization, 3387 ** this bit triggers the assertion of the M_RST# pin for 3388 ** initialization of registered DIMMs. When set: 3389 ** When operating in the conventional PCI mode: 3390 ** �E All current PCI transactions being mastered by the ATU completes, 3391 ** and the ATU master interfaces 3392 ** proceeds to an idle state. No additional transactions is mastered by these units 3393 ** until the internal bus reset is complete. 3394 ** �E All current transactions being slaved by the ATU on either the PCI bus 3395 ** or the internal bus 3396 ** completes, and the ATU target interfaces proceeds to an idle state. 3397 ** All future slave transactions master aborts, 3398 ** with the exception of the completion cycle for the transaction that set the Reset 3399 ** Internal Bus bit in the PCSR. 3400 ** �E When the value of the Core Processor Reset bit in the PCSR (upon P_RST# assertion) 3401 ** is set, the Intel XScale core is held in reset when the internal bus reset is complete. 3402 ** �E The ATU ignores configuration cycles, and they appears as master aborts for: 32 3403 ** Internal Bus clocks. 3404 ** �E The 80331 hardware clears this bit after the reset operation completes. 3405 ** When operating in the PCI-X mode: 3406 ** The ATU hardware responds the same as in Conventional PCI-X mode. 3407 ** However, this may create a problem in PCI-X mode for split requests in 3408 ** that there may still be an outstanding split completion that the 3409 ** ATU is either waiting to receive (Outbound Request) or initiate 3410 ** (Inbound Read Request). For a cleaner 3411 ** internal bus reset, host software can take the following steps prior 3412 ** to asserting Reset Internal bus: 3413 ** 1. Clear the Bus Master (bit 2 of the ATUCMD) and the Memory Enable (bit 1 of the ATUCMD) bits in 3414 ** the ATUCMD. This ensures that no new transactions, either outbound or inbound are enqueued. 3415 ** 2. Wait for both the Outbound (bit 15 of the PCSR) and Inbound Read (bit 14 of the PCSR) Transaction 3416 ** queue busy bits to be clear. 3417 ** 3. Set the Reset Internal Bus bit 3418 ** As a result, the ATU hardware resets the internal bus using the same logic as in conventional mode, 3419 ** however the user is now assured that the ATU no longer has any pending inbound or outbound split 3420 ** completion transactions. 3421 ** NOTE: Since the Reset Internal Bus bit is set using an inbound configuration cycle, the user is 3422 ** guaranteed that any prior configuration cycles have properly completed since there is only a one 3423 ** deep transaction queue for configuration transaction requests. The ATU sends the appropriate 3424 ** Split Write Completion Message to the Requester prior to the onset of Internal Bus Reset. 3425 ** 04 0 2 Bus Master Indicator Enable: Provides software control for the 3426 ** Bus Master Indicator signal P_BMI used 3427 ** for external RAIDIOS logic control of private devices. Only valid when operating with the bridge and 3428 ** central resource/arbiter disabled (BRG_EN =low, ARB_EN=low). 3429 ** 03 Varies with external state of PRIVDEV during 3430 ** P_RST# 3431 ** Private Device Enable - This bit indicates the state of the reset strap which enables the private device 3432 ** control mechanism within the PCI-to-PCI Bridge SISR configuration register. 3433 ** 0=Private Device control Disabled - SISR register bits default to zero 3434 ** 1=Private Device control Enabled - SISR register bits default to one 3435 ** 02 Varies with external state of RETRY during P_RST# 3436 ** Configuration Cycle Retry - When this bit is set, the PCI interface of the 80331 responds to all 3437 ** configuration cycles with a Retry condition. When clear, the 80331 responds to the appropriate 3438 ** configuration cycles. 3439 ** The default condition for this bit is based on the external state of the RETRY pin at the rising edge of 3440 ** P_RST#. When the external state of the pin is high, the bit is set. When the external state of the pin is 3441 ** low, the bit is cleared. 3442 ** 01 Varies with external state of CORE_RST# during P_RST# 3443 ** Core Processor Reset - This bit is set to its default value by the hardware when either P_RST# is 3444 ** asserted or the Reset Internal Bus bit in PCSR is set. When this bit is set, the Intel XScale core is 3445 ** being held in reset. Software cannot set this bit. Software is required to clear this bit to deassert Intel 3446 ** XScale core reset. 3447 ** The default condition for this bit is based on the external state of the CORE_RST# pin at the rising edge 3448 ** of P_RST#. When the external state of the pin is low, the bit is set. When the external state of the pin is 3449 ** high, the bit is clear. 3450 ** 00 Varies with external state of PRIVMEM during P_RST# 3451 ** Private Memory Enable - This bit indicates the state of the reset strap which enables the private device 3452 ** control mechanism within the PCI-to-PCI Bridge SDER configuration register. 3453 ** 0=Private Memory control Disabled - SDER register bit 2 default to zero 3454 ** 1=Private Memory control Enabled - SDER register bits 2 default to one 3455 *********************************************************************************** 3456 */ 3457 #define ARCMSR_PCI_CONFIGURATION_STATUS_REG 0x84 /*dword 0x87,0x86,0x85,0x84*/ 3458 /* 3459 *********************************************************************************** 3460 ** ATU Interrupt Status Register - ATUISR 3461 ** 3462 ** The ATU Interrupt Status Register is used to notify the core processor of the source of an ATU 3463 ** interrupt. In addition, this register is written to clear the source of the interrupt to the interrupt unit 3464 ** of the 80331. All bits in this register are Read/Clear. 3465 ** Bits 4:0 are a direct reflection of bits 14:11 and bit 8 (respectively) of the ATU Status Register 3466 ** (these bits are set at the same time by hardware but need to be cleared independently). Bit 7 is set 3467 ** by an error associated with the internal bus of the 80331. Bit 8 is for software BIST. The 3468 ** conditions that result in an ATU interrupt are cleared by writing a 1 to the appropriate bits in this 3469 ** register. 3470 ** Note: Bits 4:0, and bits 15 and 13:7 can result in an interrupt being driven to the Intel XScale core. 3471 ** ----------------------------------------------------------------- 3472 ** Bit Default Description 3473 ** 31:18 0000H Reserved 3474 ** 17 0 2 VPD Address Register Updated - This bit is set when a PCI bus configuration write occurs to the VPDAR 3475 ** register. Configuration register writes to the VPDAR does NOT result in bit 15 also being set. When set, 3476 ** this bit results in the assertion of the ATU Configure Register Write Interrupt. 3477 ** 16 0 2 Reserved 3478 ** 15 0 2 ATU Configuration Write - This bit is set when a PCI bus configuration write occurs to any ATU register. 3479 ** When set, this bit results in the assertion of the ATU Configure Register Write Interrupt. 3480 ** 14 0 2 ATU Inbound Memory Window 1 Base Updated - This bit is set when a PCI bus configuration write 3481 ** occurs to either the IABAR1 register or the IAUBAR1 register. Configuration register writes to these 3482 ** registers deos NOT result in bit 15 also being set. When set, this bit results in the assertion of the ATU 3483 ** Configure Register Write Interrupt. 3484 ** 13 0 2 Initiated Split Completion Error Message - This bit is set when the device initiates a Split Completion 3485 ** Message on the PCI Bus with the Split Completion Error attribute bit set. 3486 ** 12 0 2 Received Split Completion Error Message - This bit is set when the device receives a Split Completion 3487 ** Message from the PCI Bus with the Split Completion Error attribute bit set. 3488 ** 11 0 2 Power State Transition - When the Power State Field of the ATU Power Management Control/Status 3489 ** Register is written to transition the ATU function Power State from D0 to D3, D0 to D1, or D3 to D0 and 3490 ** the ATU Power State Transition Interrupt mask bit is cleared, this bit is set. 3491 ** 10 0 2 P_SERR# Asserted - set when P_SERR# is asserted on the PCI bus by the ATU. 3492 ** 09 0 2 Detected Parity Error - set when a parity error is detected on the PCI bus even when the ATUCMD 3493 ** register��s Parity Error Response bit is cleared. Set under the following conditions: 3494 ** �E Write Data Parity Error when the ATU is a target (inbound write). 3495 ** �E Read Data Parity Error when the ATU is an initiator (outbound read). 3496 ** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus. 3497 ** 08 0 2 ATU BIST Interrupt - When set, generates the ATU BIST Start Interrupt and indicates the host processor 3498 ** has set the Start BIST bit (ATUBISTR register bit 6), when the ATU BIST interrupt is enabled (ATUCR 3499 ** register bit 3). The Intel XScale core can initiate the software BIST and store the result in ATUBISTR 3500 ** register bits 3:0. 3501 ** Configuration register writes to the ATUBISTR does NOT result in bit 15 also being set or the assertion 3502 ** of the ATU Configure Register Write Interrupt. 3503 ** 07 0 2 Internal Bus Master Abort - set when a transaction initiated by the ATU internal bus initiator interface ends in a Master-abort. 3504 ** 06:05 00 2 Reserved. 3505 ** 04 0 2 P_SERR# Detected - set when P_SERR# is detected on the PCI bus by the ATU. 3506 ** 03 0 2 PCI Master Abort - set when a transaction initiated by the ATU PCI initiator interface ends in a Master-abort. 3507 ** 02 0 2 PCI Target Abort (master) - set when a transaction initiated by the ATU PCI master interface ends in a Target-abort. 3508 ** 01 0 2 PCI Target Abort (target) - set when the ATU interface, acting as a target, terminates the transaction on the PCI bus with a target abort. 3509 ** 00 0 2 PCI Master Parity Error - Master Parity Error - The ATU interface sets this bit under the following 3510 ** conditions: 3511 ** �E The ATU asserted PERR# itself or the ATU observed PERR# asserted. 3512 ** �E And the ATU acted as the requester for the operation in which the error occurred. 3513 ** �E And the ATUCMD register��s Parity Error Response bit is set 3514 ** �E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message 3515 ** �E And the ATUCMD register��s Parity Error Response bit is set 3516 *********************************************************************************** 3517 */ 3518 #define ARCMSR_ATU_INTERRUPT_STATUS_REG 0x88 /*dword 0x8B,0x8A,0x89,0x88*/ 3519 /* 3520 *********************************************************************************** 3521 ** ATU Interrupt Mask Register - ATUIMR 3522 ** 3523 ** The ATU Interrupt Mask Register contains the control bit to enable and disable interrupts 3524 ** generated by the ATU. 3525 ** ----------------------------------------------------------------- 3526 ** Bit Default Description 3527 ** 31:15 0 0000H Reserved 3528 ** 14 0 2 VPD Address Register Updated Mask - Controls the setting of bit 17 of the ATUISR and generation of the 3529 ** ATU Configuration Register Write interrupt when a PCI bus write occurs to the VPDAR register. 3530 ** 0=Not Masked 3531 ** 1=Masked 3532 ** 13 0 2 Reserved 3533 ** 12 0 2 Configuration Register Write Mask - Controls the setting of bit 15 of the ATUISR and generation of the 3534 ** ATU Configuration Register Write interrupt when a PCI bus write occurs to any ATU configuration register 3535 ** except those covered by mask bit 11 and bit 14 of this register, and ATU BIST enable bit 3 of the ATUCR. 3536 ** 0=Not Masked 3537 ** 1=Masked 3538 ** 11 1 2 ATU Inbound Memory Window 1 Base Updated Mask - Controls the setting of bit 14 of the ATUISR and 3539 ** generation of the ATU Configuration Register Write interrupt when a PCI bus write occurs to either the 3540 ** IABAR1 register or the IAUBAR1 register. 3541 ** 0=Not Masked 3542 ** 1=Masked 3543 ** 10 0 2 Initiated Split Completion Error Message Interrupt Mask - Controls the setting of bit 13 of the ATUISR and 3544 ** generation of the ATU Error interrupt when the ATU initiates a Split Completion Error Message. 3545 ** 0=Not Masked 3546 ** 1=Masked 3547 ** 09 0 2 Received Split Completion Error Message Interrupt Mask- Controls the setting of bit 12 of the ATUISR 3548 ** and generation of the ATU Error interrupt when a Split Completion Error Message results in bit 29 of the 3549 ** PCIXSR being set. 3550 ** 0=Not Masked 3551 ** 1=Masked 3552 ** 08 1 2 Power State Transition Interrupt Mask - Controls the setting of bit 12 of the ATUISR and generation of the 3553 ** ATU Error interrupt when ATU Power Management Control/Status Register is written to transition the 3554 ** ATU Function Power State from D0 to D3, D0 to D1, D1 to D3 or D3 to D0. 3555 ** 0=Not Masked 3556 ** 1=Masked 3557 ** 07 0 2 ATU Detected Parity Error Interrupt Mask - Controls the setting of bit 9 of the ATUISR and generation of 3558 ** the ATU Error interrupt when a parity error detected on the PCI bus that sets bit 15 of the ATUSR. 3559 ** 0=Not Masked 3560 ** 1=Masked 3561 ** 06 0 2 ATU SERR# Asserted Interrupt Mask - Controls the setting of bit 10 of the ATUISR and generation of the 3562 ** ATU Error interrupt when SERR# is asserted on the PCI interface resulting in bit 14 of the ATUSR being set. 3563 ** 0=Not Masked 3564 ** 1=Masked 3565 ** NOTE: This bit is specific to the ATU asserting SERR# and not detecting SERR# from another master. 3566 ** 05 0 2 ATU PCI Master Abort Interrupt Mask - Controls the setting of bit 3 of the ATUISR and generation of the 3567 ** ATU Error interrupt when a master abort error resulting in bit 13 of the ATUSR being set. 3568 ** 0=Not Masked 3569 ** 1=Masked 3570 ** 04 0 2 ATU PCI Target Abort (Master) Interrupt Mask- Controls the setting of bit 12 of the ATUISR and ATU Error 3571 ** generation of the interrupt when a target abort error resulting in bit 12 of the ATUSR being set 3572 ** 0=Not Masked 3573 ** 1=Masked 3574 ** 03 0 2 ATU PCI Target Abort (Target) Interrupt Mask- Controls the setting of bit 1 of the ATUISR and generation 3575 ** of the ATU Error interrupt when a target abort error resulting in bit 11 of the ATUSR being set. 3576 ** 0=Not Masked 3577 ** 1=Masked 3578 ** 02 0 2 ATU PCI Master Parity Error Interrupt Mask - Controls the setting of bit 0 of the ATUISR and generation 3579 ** of the ATU Error interrupt when a parity error resulting in bit 8 of the ATUSR being set. 3580 ** 0=Not Masked 3581 ** 1=Masked 3582 ** 01 0 2 ATU Inbound Error SERR# Enable - Controls when the ATU asserts (when enabled through the 3583 ** ATUCMD) SERR# on the PCI interface in response to a master abort on the internal bus during an 3584 ** inbound write transaction. 3585 ** 0=SERR# Not Asserted due to error 3586 ** 1=SERR# Asserted due to error 3587 ** 00 0 2 ATU ECC Target Abort Enable - Controls the ATU response on the PCI interface to a target abort (ECC 3588 ** error) from the memory controller on the internal bus. In conventional mode, this action only occurs 3589 ** during an inbound read transaction where the data phase that was target aborted on the internal bus is 3590 ** actually requested from the inbound read queue. 3591 ** 0=Disconnect with data 3592 ** (the data being up to 64 bits of 1��s) 3593 ** 1=Target Abort 3594 ** NOTE: In PCI-X Mode, The ATU initiates a Split Completion Error Message (with message class=2h - 3595 ** completer error and message index=81h - 80331 internal bus target abort) on the PCI bus, 3596 ** independent of the setting of this bit. 3597 *********************************************************************************** 3598 */ 3599 #define ARCMSR_ATU_INTERRUPT_MASK_REG 0x8C /*dword 0x8F,0x8E,0x8D,0x8C*/ 3600 /* 3601 *********************************************************************************** 3602 ** Inbound ATU Base Address Register 3 - IABAR3 3603 ** 3604 ** . The Inbound ATU Base Address Register 3 (IABAR3) together with the Inbound ATU Upper Base Address Register 3 (IAUBAR3) defines the block 3605 ** of memory addresses where the inbound translation window 3 begins. 3606 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 3607 ** . The IABAR3 and IAUBAR3 define the base address and describes the required memory block size. 3608 ** . Bits 31 through 12 of the IABAR3 is either read/write bits or read only with a value of 0 depending on the value located within the IALR3. 3609 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 3610 ** Note: 3611 ** Since IABAR3 does not appear in the standard PCI configuration header space (offsets 00H - 3CH), 3612 ** IABAR3 is not configured by the host during normal system initialization. 3613 ** Warning: 3614 ** When a non-zero value is not written to IALR3, 3615 ** the user should not set either the Prefetchable Indicator 3616 ** or the Type Indicator for 64 bit addressability. 3617 ** This is the default for IABAR3. 3618 ** Assuming a non-zero value is written to IALR3, 3619 ** the user may set the Prefetchable Indicator 3620 ** or the Type Indicator: 3621 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 3622 ** when the Prefetchable Indicator is not set, 3623 ** the user should also leave the Type Indicator set for 32 bit addressability. 3624 ** This is the default for IABAR3. 3625 ** b. when the Prefetchable Indicator is set, 3626 ** the user should also set the Type Indicator for 64 bit addressability. 3627 ** ----------------------------------------------------------------- 3628 ** Bit Default Description 3629 ** 31:12 00000H Translation Base Address 3 - These bits define the actual location 3630 ** the translation function is to respond to when addressed from the PCI bus. 3631 ** 11:04 00H Reserved. 3632 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 3633 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 3634 ** 00 - Memory Window is locatable anywhere in 32 bit address space 3635 ** 10 - Memory Window is locatable anywhere in 64 bit address space 3636 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 3637 ** The ATU does not occupy I/O space, 3638 ** thus this bit must be zero. 3639 *********************************************************************************** 3640 */ 3641 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS3_REG 0x90 /*dword 0x93,0x92,0x91,0x90*/ 3642 /* 3643 *********************************************************************************** 3644 ** Inbound ATU Upper Base Address Register 3 - IAUBAR3 3645 ** 3646 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 3647 ** Together with the Translation Base Address this register defines the actual location 3648 ** the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 3649 ** The programmed value within the base address register must comply with the PCI programming 3650 ** requirements for address alignment. 3651 ** Note: 3652 ** When the Type indicator of IABAR3 is set to indicate 32 bit addressability, 3653 ** the IAUBAR3 register attributes are read-only. 3654 ** This is the default for IABAR3. 3655 ** ----------------------------------------------------------------- 3656 ** Bit Default Description 3657 ** 31:0 00000H Translation Upper Base Address 3 - Together with the Translation Base Address 3 these bits define 3658 ** the actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes. 3659 *********************************************************************************** 3660 */ 3661 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS3_REG 0x94 /*dword 0x97,0x96,0x95,0x94*/ 3662 /* 3663 *********************************************************************************** 3664 ** Inbound ATU Limit Register 3 - IALR3 3665 ** 3666 ** Inbound address translation for memory window 3 occurs for data transfers occurring from the PCI 3667 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 3668 ** PCI addresses to internal bus addresses. 3669 ** The inbound translation base address for inbound window 3 is specified in Section 3.10.15. When 3670 ** determining block size requirements �X as described in Section 3.10.21 �X the translation limit 3671 ** register provides the block size requirements for the base address register. The remaining registers 3672 ** used for performing address translation are discussed in Section 3.2.1.1. 3673 ** The 80331 translate value register��s programmed value must be naturally aligned with the base 3674 ** address register��s programmed value. The limit register is used as a mask; thus, the lower address 3675 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 3676 ** Specification, Revision 2.3 for additional information on programming base address registers. 3677 ** Bits 31 to 12 within the IALR3 have a direct effect on the IABAR3 register, bits 31 to 12, with a 3678 ** one to one correspondence. A value of 0 in a bit within the IALR3 makes the corresponding bit 3679 ** within the IABAR3 a read only bit which always returns 0. A value of 1 in a bit within the IALR3 3680 ** makes the corresponding bit within the IABAR3 read/write from PCI. Note that a consequence of 3681 ** this programming scheme is that unless a valid value exists within the IALR3, all writes to the 3682 ** IABAR3 has no effect since a value of all zeros within the IALR3 makes the IABAR3 a read only 3683 ** register. 3684 ** ----------------------------------------------------------------- 3685 ** Bit Default Description 3686 ** 31:12 00000H Inbound Translation Limit 3 - This readback value determines the memory block size required 3687 ** for the ATUs memory window 3. 3688 ** 11:00 000H Reserved 3689 *********************************************************************************** 3690 */ 3691 #define ARCMSR_INBOUND_ATU_LIMIT3_REG 0x98 /*dword 0x9B,0x9A,0x99,0x98*/ 3692 /* 3693 *********************************************************************************** 3694 ** Inbound ATU Translate Value Register 3 - IATVR3 3695 ** 3696 ** The Inbound ATU Translate Value Register 3 (IATVR3) contains the internal bus address used to 3697 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 3698 ** inbound ATU address translation. 3699 ** ----------------------------------------------------------------- 3700 ** Bit Default Description 3701 ** 31:12 00000H Inbound ATU Translation Value 3 - This value is used to convert the PCI address to internal bus addresses. 3702 ** This value must be 64-bit aligned on the internal bus. The default address allows the ATU to 3703 ** access the internal 80331 memory-mapped registers. 3704 ** 11:00 000H Reserved 3705 *********************************************************************************** 3706 */ 3707 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE3_REG 0x9C /*dword 0x9F,0x9E,0x9D,0x9C*/ 3708 /* 3709 *********************************************************************************** 3710 ** Outbound Configuration Cycle Address Register - OCCAR 3711 ** 3712 ** The Outbound Configuration Cycle Address Register is used to hold the 32-bit PCI configuration 3713 ** cycle address. The Intel XScale core writes the PCI configuration cycles address which then 3714 ** enables the outbound configuration read or write. The Intel XScale core then performs a read or 3715 ** write to the Outbound Configuration Cycle Data Register to initiate the configuration cycle on the 3716 ** PCI bus. 3717 ** Note: Bits 15:11 of the configuration cycle address for Type 0 configuration cycles are defined differently 3718 ** for Conventional versus PCI-X modes. When 80331 software programs the OCCAR to initiate a 3719 ** Type 0 configuration cycle, the OCCAR should always be loaded based on the PCI-X definition for 3720 ** the Type 0 configuration cycle address. When operating in Conventional mode, the 80331 clears 3721 ** bits 15:11 of the OCCAR prior to initiating an outbound Type 0 configuration cycle. See the PCI-X 3722 ** Addendum to the PCI Local Bus Specification, Revision 1.0a for details on the two formats. 3723 ** ----------------------------------------------------------------- 3724 ** Bit Default Description 3725 ** 31:00 0000 0000H Configuration Cycle Address - These bits define the 32-bit PCI address used during an outbound 3726 ** configuration read or write cycle. 3727 *********************************************************************************** 3728 */ 3729 #define ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_ADDRESS_REG 0xA4 /*dword 0xA7,0xA6,0xA5,0xA4*/ 3730 /* 3731 *********************************************************************************** 3732 ** Outbound Configuration Cycle Data Register - OCCDR 3733 ** 3734 ** The Outbound Configuration Cycle Data Register is used to initiate a configuration read or write 3735 ** on the PCI bus. The register is logical rather than physical meaning that it is an address not a 3736 ** register. The Intel XScale core reads or writes the data registers memory-mapped address to 3737 ** initiate the configuration cycle on the PCI bus with the address found in the OCCAR. For a 3738 ** configuration write, the data is latched from the internal bus and forwarded directly to the OWQ. 3739 ** For a read, the data is returned directly from the ORQ to the Intel XScale core and is never 3740 ** actually entered into the data register (which does not physically exist). 3741 ** The OCCDR is only visible from 80331 internal bus address space and appears as a reserved value 3742 ** within the ATU configuration space. 3743 ** ----------------------------------------------------------------- 3744 ** Bit Default Description 3745 ** 31:00 0000 0000H Configuration Cycle Data - These bits define the data used during an outbound configuration read 3746 ** or write cycle. 3747 *********************************************************************************** 3748 */ 3749 #define ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_DATA_REG 0xAC /*dword 0xAF,0xAE,0xAD,0xAC*/ 3750 /* 3751 *********************************************************************************** 3752 ** VPD Capability Identifier Register - VPD_CAPID 3753 ** 3754 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 3755 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 3756 ** Capability contained in that header. In the case of the 80331, this is the VPD extended capability 3757 ** with an ID of 03H as defined by the PCI Local Bus Specification, Revision 2.3. 3758 ** ----------------------------------------------------------------- 3759 ** Bit Default Description 3760 ** 07:00 03H Cap_Id - This field with its�� 03H value identifies this item in the linked list of Extended Capability 3761 ** Headers as being the VPD capability registers. 3762 *********************************************************************************** 3763 */ 3764 #define ARCMSR_VPD_CAPABILITY_IDENTIFIER_REG 0xB8 /*byte*/ 3765 /* 3766 *********************************************************************************** 3767 ** VPD Next Item Pointer Register - VPD_NXTP 3768 ** 3769 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 3770 ** Revision 2.3. This register describes the location of the next item in the function��s capability list. 3771 ** For the 80331, this the final capability list, and hence, this register is set to 00H. 3772 ** ----------------------------------------------------------------- 3773 ** Bit Default Description 3774 ** 07:00 00H Next_ Item_ Pointer - This field provides an offset into the function��s configuration space pointing to the 3775 ** next item in the function��s capability list. Since the VPD capabilities are the last in the linked list of 3776 ** extended capabilities in the 80331, the register is set to 00H. 3777 *********************************************************************************** 3778 */ 3779 #define ARCMSR_VPD_NEXT_ITEM_PTR_REG 0xB9 /*byte*/ 3780 /* 3781 *********************************************************************************** 3782 ** VPD Address Register - VPD_AR 3783 ** 3784 ** The VPD Address register (VPDAR) contains the DWORD-aligned byte address of the VPD to be 3785 ** accessed. The register is read/write and the initial value at power-up is indeterminate. 3786 ** A PCI Configuration Write to the VPDAR interrupts the Intel XScale core. Software can use 3787 ** the Flag setting to determine whether the configuration write was intended to initiate a read or 3788 ** write of the VPD through the VPD Data Register. 3789 ** ----------------------------------------------------------------- 3790 ** Bit Default Description 3791 ** 15 0 2 Flag - A flag is used to indicate when a transfer of data between the VPD Data Register and the storage 3792 ** component has completed. Please see Section 3.9, ��Vital Product Data�� on page 201 for more details on 3793 ** how the 80331 handles the data transfer. 3794 ** 14:0 0000H VPD Address - This register is written to set the DWORD-aligned byte address used to read or write 3795 ** Vital Product Data from the VPD storage component. 3796 *********************************************************************************** 3797 */ 3798 #define ARCMSR_VPD_ADDRESS_REG 0xBA /*word 0xBB,0xBA*/ 3799 /* 3800 *********************************************************************************** 3801 ** VPD Data Register - VPD_DR 3802 ** 3803 ** This register is used to transfer data between the 80331 and the VPD storage component. 3804 ** ----------------------------------------------------------------- 3805 ** Bit Default Description 3806 ** 31:00 0000H VPD Data - Four bytes are always read or written through this register to/from the VPD storage component. 3807 *********************************************************************************** 3808 */ 3809 #define ARCMSR_VPD_DATA_REG 0xBC /*dword 0xBF,0xBE,0xBD,0xBC*/ 3810 /* 3811 *********************************************************************************** 3812 ** Power Management Capability Identifier Register -PM_CAPID 3813 ** 3814 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 3815 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 3816 ** Capability contained in that header. In the case of the 80331, this is the PCI Bus Power 3817 ** Management extended capability with an ID of 01H as defined by the PCI Bus Power Management 3818 ** Interface Specification, Revision 1.1. 3819 ** ----------------------------------------------------------------- 3820 ** Bit Default Description 3821 ** 07:00 01H Cap_Id - This field with its�� 01H value identifies this item in the linked list of Extended Capability 3822 ** Headers as being the PCI Power Management Registers. 3823 *********************************************************************************** 3824 */ 3825 #define ARCMSR_POWER_MANAGEMENT_CAPABILITY_IDENTIFIER_REG 0xC0 /*byte*/ 3826 /* 3827 *********************************************************************************** 3828 ** Power Management Next Item Pointer Register - PM_NXTP 3829 ** 3830 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 3831 ** Revision 2.3. This register describes the location of the next item in the function��s capability list. 3832 ** For the 80331, the next capability (MSI capability list) is located at off-set D0H. 3833 ** ----------------------------------------------------------------- 3834 ** Bit Default Description 3835 ** 07:00 D0H Next_ Item_ Pointer - This field provides an offset into the function��s configuration space pointing to the 3836 ** next item in the function��s capability list which in the 80331 is the MSI extended capabilities header. 3837 *********************************************************************************** 3838 */ 3839 #define ARCMSR_POWER_NEXT_ITEM_PTR_REG 0xC1 /*byte*/ 3840 /* 3841 *********************************************************************************** 3842 ** Power Management Capabilities Register - PM_CAP 3843 ** 3844 ** Power Management Capabilities bits adhere to the definitions in the PCI Bus Power Management 3845 ** Interface Specification, Revision 1.1. This register is a 16-bit read-only register which provides 3846 ** information on the capabilities of the ATU function related to power management. 3847 ** ----------------------------------------------------------------- 3848 ** Bit Default Description 3849 ** 15:11 00000 2 PME_Support - This function is not capable of asserting the PME# signal in any state, since PME# 3850 ** is not supported by the 80331. 3851 ** 10 0 2 D2_Support - This bit is set to 0 2 indicating that the 80331 does not support the D2 Power Management State 3852 ** 9 1 2 D1_Support - This bit is set to 1 2 indicating that the 80331 supports the D1 Power Management State 3853 ** 8:6 000 2 Aux_Current - This field is set to 000 2 indicating that the 80331 has no current requirements for the 3854 ** 3.3Vaux signal as defined in the PCI Bus Power Management Interface Specification, Revision 1.1 3855 ** 5 0 2 DSI - This field is set to 0 2 meaning that this function requires a device specific initialization sequence 3856 ** following the transition to the D0 uninitialized state. 3857 ** 4 0 2 Reserved. 3858 ** 3 0 2 PME Clock - Since the 80331 does not support PME# signal generation this bit is cleared to 0 2 . 3859 ** 2:0 010 2 Version - Setting these bits to 010 2 means that this function complies with PCI Bus Power Management 3860 ** Interface Specification, Revision 1.1 3861 *********************************************************************************** 3862 */ 3863 #define ARCMSR_POWER_MANAGEMENT_CAPABILITY_REG 0xC2 /*word 0xC3,0xC2*/ 3864 /* 3865 *********************************************************************************** 3866 ** Power Management Control/Status Register - PM_CSR 3867 ** 3868 ** Power Management Control/Status bits adhere to the definitions in the PCI Bus Power 3869 ** Management Interface Specification, Revision 1.1. This 16-bit register is the control and status 3870 ** interface for the power management extended capability. 3871 ** ----------------------------------------------------------------- 3872 ** Bit Default Description 3873 ** 15 0 2 PME_Status - This function is not capable of asserting the PME# signal in any state, since PME## is not 3874 ** supported by the 80331. 3875 ** 14:9 00H Reserved 3876 ** 8 0 2 PME_En - This bit is hardwired to read-only 0 2 since this function does not support PME# 3877 ** generation from any power state. 3878 ** 7:2 000000 2 Reserved 3879 ** 1:0 00 2 Power State - This 2-bit field is used both to determine the current power state 3880 ** of a function and to set the function into a new power state. The definition of the values is: 3881 ** 00 2 - D0 3882 ** 01 2 - D1 3883 ** 10 2 - D2 (Unsupported) 3884 ** 11 2 - D3 hot 3885 ** The 80331 supports only the D0 and D3 hot states. 3886 ** 3887 *********************************************************************************** 3888 */ 3889 #define ARCMSR_POWER_MANAGEMENT_CONTROL_STATUS_REG 0xC4 /*word 0xC5,0xC4*/ 3890 /* 3891 *********************************************************************************** 3892 ** PCI-X Capability Identifier Register - PX_CAPID 3893 ** 3894 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 3895 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 3896 ** Capability contained in that header. In the case of the 80331, this is the PCI-X extended capability with 3897 ** an ID of 07H as defined by the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a. 3898 ** ----------------------------------------------------------------- 3899 ** Bit Default Description 3900 ** 07:00 07H Cap_Id - This field with its�� 07H value identifies this item in the linked list of Extended Capability 3901 ** Headers as being the PCI-X capability registers. 3902 *********************************************************************************** 3903 */ 3904 #define ARCMSR_PCIX_CAPABILITY_IDENTIFIER_REG 0xE0 /*byte*/ 3905 /* 3906 *********************************************************************************** 3907 ** PCI-X Next Item Pointer Register - PX_NXTP 3908 ** 3909 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 3910 ** Revision 2.3. This register describes the location of the next item in the function��s capability list. 3911 ** By default, the PCI-X capability is the last capabilities list for the 80331, thus this register defaults 3912 ** to 00H. 3913 ** However, this register may be written to B8H prior to host configuration to include the VPD 3914 ** capability located at off-set B8H. 3915 ** Warning: Writing this register to any value other than 00H (default) or B8H is not supported and may 3916 ** produce unpredictable system behavior. 3917 ** In order to guarantee that this register is written prior to host configuration, the 80331 must be 3918 ** initialized at P_RST# assertion to Retry Type 0 configuration cycles (bit 2 of PCSR). Typically, 3919 ** the Intel XScale core would be enabled to boot immediately following P_RST# assertion in 3920 ** this case (bit 1 of PCSR), as well. Please see Table 125, ��PCI Configuration and Status Register - 3921 ** PCSR�� on page 253 for more details on the 80331 initialization modes. 3922 ** ----------------------------------------------------------------- 3923 ** Bit Default Description 3924 ** 07:00 00H Next_ Item_ Pointer - This field provides an offset into the function��s configuration space pointing to the 3925 ** next item in the function��s capability list. Since the PCI-X capabilities are the last in the linked list of 3926 ** extended capabilities in the 80331, the register is set to 00H. 3927 ** However, this field may be written prior to host configuration with B8H to extend the list to include the 3928 ** VPD extended capabilities header. 3929 *********************************************************************************** 3930 */ 3931 #define ARCMSR_PCIX_NEXT_ITEM_PTR_REG 0xE1 /*byte*/ 3932 /* 3933 *********************************************************************************** 3934 ** PCI-X Command Register - PX_CMD 3935 ** 3936 ** This register controls various modes and features of ATU and Message Unit when operating in the 3937 ** PCI-X mode. 3938 ** ----------------------------------------------------------------- 3939 ** Bit Default Description 3940 ** 15:7 000000000 2 Reserved. 3941 ** 6:4 011 2 Maximum Outstanding Split Transactions - This register sets the maximum number of Split Transactions 3942 ** the device is permitted to have outstanding at one time. 3943 ** Register Maximum Outstanding 3944 ** 0 1 3945 ** 1 2 3946 ** 2 3 3947 ** 3 4 3948 ** 4 8 3949 ** 5 12 3950 ** 6 16 3951 ** 7 32 3952 ** 3:2 00 2 Maximum Memory Read Byte Count - This register sets the maximum byte count the device uses when 3953 ** initiating a Sequence with one of the burst memory read commands. 3954 ** Register Maximum Byte Count 3955 ** 0 512 3956 ** 1 1024 3957 ** 2 2048 3958 ** 3 4096 3959 ** 1 0 2 3960 ** Enable Relaxed Ordering - The 80331 does not set the relaxed ordering bit in the Requester Attributes 3961 ** of Transactions. 3962 ** 0 0 2 Data Parity Error Recovery Enable - The device driver sets this bit to enable the device to attempt to 3963 ** recover from data parity errors. When this bit is 0 and the device is in PCI-X mode, the device asserts 3964 ** SERR# (when enabled) whenever the Master Data Parity Error bit (Status register, bit 8) is set. 3965 *********************************************************************************** 3966 */ 3967 #define ARCMSR_PCIX_COMMAND_REG 0xE2 /*word 0xE3,0xE2*/ 3968 /* 3969 *********************************************************************************** 3970 ** PCI-X Status Register - PX_SR 3971 ** 3972 ** This register identifies the capabilities and current operating mode of ATU, DMAs and Message 3973 ** Unit when operating in the PCI-X mode. 3974 ** ----------------------------------------------------------------- 3975 ** Bit Default Description 3976 ** 31:30 00 2 Reserved 3977 ** 29 0 2 Received Split Completion Error Message - This bit is set when the device receives a Split Completion 3978 ** Message with the Split Completion Error attribute bit set. Once set, this bit remains set until software 3979 ** writes a 1 to this location. 3980 ** 0=no Split Completion error message received. 3981 ** 1=a Split Completion error message has been received. 3982 ** 28:26 001 2 Designed Maximum Cumulative Read Size (DMCRS) - The value of this register depends on the setting 3983 ** of the Maximum Memory Read Byte Count field of the PCIXCMD register: 3984 ** DMCRS Max ADQs Maximum Memory Read Byte Count Register Setting 3985 ** 1 16 512 (Default) 3986 ** 2 32 1024 3987 ** 2 32 2048 3988 ** 2 32 4096 3989 ** 25:23 011 2 Designed Maximum Outstanding Split Transactions - The 80331 can have up to four outstanding split transactions. 3990 ** 22:21 01 2 Designed Maximum Memory Read Byte Count - The 80331 can generate memory reads with byte counts up 3991 ** to 1024 bytes. 3992 ** 20 1 2 80331 is a complex device. 3993 ** 19 0 2 Unexpected Split Completion - This bit is set when an unexpected Split Completion with this device��s 3994 ** Requester ID is received. Once set, this bit remains set until software writes a 1 to this location. 3995 ** 0=no unexpected Split Completion has been received. 3996 ** 1=an unexpected Split Completion has been received. 3997 ** 18 0 2 Split Completion Discarded - This bit is set when the device discards a Split Completion because the 3998 ** requester would not accept it. See Section 5.4.4 of the PCI-X Addendum to the PCI Local Bus 3999 ** Specification, Revision 1.0a for details. Once set, this bit remains set until software writes a 1 to this 4000 ** location. 4001 ** 0=no Split Completion has been discarded. 4002 ** 1=a Split Completion has been discarded. 4003 ** NOTE: The 80331 does not set this bit since there is no Inbound address responding to Inbound Read 4004 ** Requests with Split Responses (Memory or Register) that has ��read side effects.�� 4005 ** 17 1 2 80331 is a 133 MHz capable device. 4006 ** 16 1 2 or P_32BITPCI# 80331 with bridge enabled (BRG_EN=1) implements the ATU with a 64-bit interface on the secondary PCI bus, 4007 ** therefore this bit is always set. 4008 ** 80331 with no bridge and central resource disabled (BRG_EN=0, ARB_EN=0), 4009 ** use this bit to identify the add-in card to the system as 64-bit or 32-bit wide via a user-configurable strap (P_32BITPCI#). 4010 ** This strap, by default, identifies the add in card based on 80331 with bridge disabled 4011 ** as 64-bit unless the user attaches the appropriate pull-down resistor to the strap. 4012 ** 0=The bus is 32 bits wide. 4013 ** 1=The bus is 64 bits wide. 4014 ** 15:8 FFH Bus Number - This register is read for diagnostic purposes only. It indicates the number of the bus 4015 ** segment for the device containing this function. The function uses this number as part of its Requester 4016 ** ID and Completer ID. For all devices other than the source bridge, each time the function is addressed 4017 ** by a Configuration Write transaction, the function must update this register with the contents of AD[7::0] 4018 ** of the attribute phase of the Configuration Write, regardless of which register in the function is 4019 ** addressed by the transaction. The function is addressed by a Configuration Write transaction when all of 4020 ** the following are true: 4021 ** 1. The transaction uses a Configuration Write command. 4022 ** 2. IDSEL is asserted during the address phase. 4023 ** 3. AD[1::0] are 00b (Type 0 configuration transaction). 4024 ** 4. AD[10::08] of the configuration address contain the appropriate function number. 4025 ** 7:3 1FH Device Number - This register is read for diagnostic purposes only. It indicates the number of the device 4026 ** containing this function, i.e., the number in the Device Number field (AD[15::11]) of the address of a 4027 ** Type 0 configuration transaction that is assigned to the device containing this function by the connection 4028 ** of the system hardware. The system must assign a device number other than 00h (00h is reserved for 4029 ** the source bridge). The function uses this number as part of its Requester ID and Completer ID. Each 4030 ** time the function is addressed by a Configuration Write transaction, the device must update this register 4031 ** with the contents of AD[15::11] of the address phase of the Configuration Write, regardless of which 4032 ** register in the function is addressed by the transaction. The function is addressed by a Configuration 4033 ** Write transaction when all of the following are true: 4034 ** 1. The transaction uses a Configuration Write command. 4035 ** 2. IDSEL is asserted during the address phase. 4036 ** 3. AD[1::0] are 00b (Type 0 configuration transaction). 4037 ** 4. AD[10::08] of the configuration address contain the appropriate function number. 4038 ** 2:0 000 2 Function Number - This register is read for diagnostic purposes only. It indicates the number of this 4039 ** function; i.e., the number in the Function Number field (AD[10::08]) of the address of a Type 0 4040 ** configuration transaction to which this function responds. The function uses this number as part of its 4041 ** Requester ID and Completer ID. 4042 ** 4043 ************************************************************************** 4044 */ 4045 #define ARCMSR_PCIX_STATUS_REG 0xE4 /*dword 0xE7,0xE6,0xE5,0xE4*/ 4046 4047 /* 4048 ************************************************************************** 4049 ** Inbound Read Transaction 4050 ** ======================================================================== 4051 ** An inbound read transaction is initiated by a PCI initiator and is targeted at either 80331 local 4052 ** memory or a 80331 memory-mapped register space. The read transaction is propagated through 4053 ** the inbound transaction queue (ITQ) and read data is returned through the inbound read queue 4054 ** (IRQ). 4055 ** When operating in the conventional PCI mode, all inbound read transactions are processed as 4056 ** delayed read transactions. When operating in the PCI-X mode, all inbound read transactions are 4057 ** processed as split transactions. The ATUs PCI interface claims the read transaction and forwards 4058 ** the read request through to the internal bus and returns the read data to the PCI bus. Data flow for 4059 ** an inbound read transaction on the PCI bus is summarized in the following statements: 4060 ** �E The ATU claims the PCI read transaction when the PCI address is within the inbound 4061 ** translation window defined by ATU Inbound Base Address Register (and Inbound Upper Base 4062 ** Address Register during DACs) and Inbound Limit Register. 4063 ** �E When operating in the conventional PCI mode, when the ITQ is currently holding transaction 4064 ** information from a previous delayed read, the current transaction information is compared to 4065 ** the previous transaction information (based on the setting of the DRC Alias bit in 4066 ** Section 3.10.39, ��ATU Configuration Register - ATUCR�� on page 252). When there is a 4067 ** match and the data is in the IRQ, return the data to the master on the PCI bus. When there is a 4068 ** match and the data is not available, a Retry is signaled with no other action taken. When there 4069 ** is not a match and when the ITQ has less than eight entries, capture the transaction 4070 ** information, signal a Retry and initiate a delayed transaction. When there is not a match and 4071 ** when the ITQ is full, then signal a Retry with no other action taken. 4072 ** �X When an address parity error is detected, the address parity response defined in 4073 ** Section 3.7 is used. 4074 ** �E When operating in the conventional PCI mode, once read data is driven onto the PCI bus from 4075 ** the IRQ, it continues until one of the following is true: 4076 ** �X The initiator completes the PCI transaction. When there is data left unread in the IRQ, the 4077 ** data is flushed. 4078 ** �X An internal bus Target Abort was detected. In this case, the QWORD associated with the 4079 ** Target Abort is never entered into the IRQ, and therefore is never returned. 4080 ** �X Target Abort or a Disconnect with Data is returned in response to the Internal Bus Error. 4081 ** �X The IRQ becomes empty. In this case, the PCI interface signals a Disconnect with data to 4082 ** the initiator on the last data word available. 4083 ** �E When operating in the PCI-X mode, when ITQ is not full, the PCI address, attribute and 4084 ** command are latched into the available ITQ and a Split Response Termination is signalled to 4085 ** the initiator. 4086 ** �E When operating in the PCI-X mode, when the transaction does not cross a 1024 byte aligned 4087 ** boundary, then the ATU waits until it receives the full byte count from the internal bus target 4088 ** before returning read data by generating the split completion transaction on the PCI-X bus. 4089 ** When the read requested crosses at least one 1024 byte boundary, then ATU completes the 4090 ** transfer by returning data in 1024 byte aligned chunks. 4091 ** �E When operating in the PCI-X mode, once a split completion transaction has started, it 4092 ** continues until one of the following is true: 4093 ** �X The requester (now the target) generates a Retry Termination, or a Disconnection at Next 4094 ** ADB (when the requester is a bridge) 4095 ** �X The byte count is satisfied. 4096 ** �X An internal bus Target Abort was detected. The ATU generates a Split Completion 4097 ** Message (message class=2h - completer error, and message index=81h - target abort) to 4098 ** inform the requester about the abnormal condition. The ITQ for this transaction is flushed. 4099 ** Refer to Section 3.7.1. 4100 ** �X An internal bus Master Abort was detected. The ATU generates a Split Completion 4101 ** Message (message class=2h - completer error, and message index=80h - Master abort) to 4102 ** inform the requester about the abnormal condition. The ITQ for this transaction is flushed. 4103 ** Refer to Section 3.7.1 4104 ** �E When operating in the conventional PCI mode, when the master inserts wait states on the PCI 4105 ** bus, the ATU PCI slave interface waits with no premature disconnects. 4106 ** �E When a data parity error occurs signified by PERR# asserted from the initiator, no action is 4107 ** taken by the target interface. Refer to Section 3.7.2.5. 4108 ** �E When operating in the conventional PCI mode, when the read on the internal bus is 4109 ** target-aborted, either a target-abort or a disconnect with data is signaled to the initiator. This is 4110 ** based on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). When set, a 4111 ** target abort is used, when clear, a disconnect is used. 4112 ** �E When operating in the PCI-X mode (with the exception of the MU queue ports at offsets 40h 4113 ** and 44h), when the transaction on the internal bus resulted in a target abort, the ATU generates 4114 ** a Split Completion Message (message class=2h - completer error, and message index=81h - 4115 ** internal bus target abort) to inform the requester about the abnormal condition. For the MU 4116 ** queue ports, the ATU returns either a target abort or a single data phase disconnect depending 4117 ** on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). The ITQ for this 4118 ** transaction is flushed. Refer to Section 3.7.1. 4119 ** �E When operating in the conventional PCI mode, when the transaction on the internal bus 4120 ** resulted in a master abort, the ATU returns a target abort to inform the requester about the 4121 ** abnormal condition. The ITQ for this transaction is flushed. Refer to Section 3.7.1 4122 ** �E When operating in the PCI-X mode, when the transaction on the internal bus resulted in a 4123 ** master abort, the ATU generates a Split Completion Message (message class=2h - completer 4124 ** error, and message index=80h - internal bus master abort) to inform the requester about the 4125 ** abnormal condition. The ITQ for this transaction is flushed. Refer to Section 3.7.1. 4126 ** �E When operating in the PCI-X mode, when the Split Completion transaction completes with 4127 ** either Master-Abort or Target-Abort, the requester is indicating a failure condition that 4128 ** prevents it from accepting the completion it requested. In this case, since the Split Request 4129 ** addresses a location that has no read side effects, the completer must discard the Split 4130 ** Completion and take no further action. 4131 ** The data flow for an inbound read transaction on the internal bus is summarized in the following 4132 ** statements: 4133 ** �E The ATU internal bus master interface requests the internal bus when a PCI address appears in 4134 ** an ITQ and transaction ordering has been satisfied. When operating in the PCI-X mode the 4135 ** ATU does not use the information provided by the Relax Ordering Attribute bit. That is, ATU 4136 ** always uses conventional PCI ordering rules. 4137 ** �E Once the internal bus is granted, the internal bus master interface drives the translated address 4138 ** onto the bus and wait for IB_DEVSEL#. When a Retry is signaled, the request is repeated. 4139 ** When a master abort occurs, the transaction is considered complete and a target abort is loaded 4140 ** into the associated IRQ for return to the PCI initiator (transaction is flushed once the PCI 4141 ** master has been delivered the target abort). 4142 ** �E Once the translated address is on the bus and the transaction has been accepted, the internal 4143 ** bus target starts returning data with the assertion of IB_TRDY#. Read data is continuously 4144 ** received by the IRQ until one of the following is true: 4145 ** �X The full byte count requested by the ATU read request is received. The ATU internal bus 4146 ** initiator interface performs a initiator completion in this case. 4147 ** �X When operating in the conventional PCI mode, a Target Abort is received on the internal 4148 ** bus from the internal bus target. In this case, the transaction is aborted and the PCI side is 4149 ** informed. 4150 ** �X When operating in the PCI-X mode, a Target Abort is received on the internal bus from 4151 ** the internal bus target. In this case, the transaction is aborted. The ATU generates a Split 4152 ** Completion Message (message class=2h - completer error, and message index=81h - 4153 ** target abort) on the PCI bus to inform the requester about the abnormal condition. The 4154 ** ITQ for this transaction is flushed. 4155 ** �X When operating in the conventional PCI mode, a single data phase disconnection is 4156 ** received from the internal bus target. When the data has not been received up to the next 4157 ** QWORD boundary, the ATU internal bus master interface attempts to reacquire the bus. 4158 ** When not, the bus returns to idle. 4159 ** �X When operating in the PCI-X mode, a single data phase disconnection is received from 4160 ** the internal bus target. The ATU IB initiator interface attempts to reacquire the bus to 4161 ** obtain remaining data. 4162 ** �X When operating in the conventional PCI mode, a disconnection at Next ADB is received 4163 ** from the internal bus target. The bus returns to idle. 4164 ** �X When operating in the PCI-X mode, a disconnection at Next ADB is received from the 4165 ** internal bus target. The ATU IB initiator interface attempts to reacquire the bus to obtain 4166 ** remaining data. 4167 ** To support PCI Local Bus Specification, Revision 2.0 devices, the ATU can be programmed to 4168 ** ignore the memory read command (Memory Read, Memory Read Line, and Memory Read 4169 ** Multiple) when trying to match the current inbound read transaction with data in a DRC queue 4170 ** which was read previously (DRC on target bus). When the Read Command Alias Bit in the 4171 ** ATUCR register is set, the ATU does not distinguish the read commands on transactions. For 4172 ** example, the ATU enqueues a DRR with a Memory Read Multiple command and performs the read 4173 ** on the internal bus. Some time later, a PCI master attempts a Memory Read with the same address 4174 ** as the previous Memory Read Multiple. When the Read Command Bit is set, the ATU would return 4175 ** the read data from the DRC queue and consider the Delayed Read transaction complete. When the 4176 ** Read Command bit in the ATUCR was clear, the ATU would not return data since the PCI read 4177 ** commands did not match, only the address. 4178 ************************************************************************** 4179 */ 4180 /* 4181 ************************************************************************** 4182 ** Inbound Write Transaction 4183 **======================================================================== 4184 ** An inbound write transaction is initiated by a PCI master and is targeted at either 80331 local 4185 ** memory or a 80331 memory-mapped register. 4186 ** Data flow for an inbound write transaction on the PCI bus is summarized as: 4187 ** �E The ATU claims the PCI write transaction when the PCI address is within the inbound 4188 ** translation window defined by the ATU Inbound Base Address Register (and Inbound Upper 4189 ** Base Address Register during DACs) and Inbound Limit Register. 4190 ** �E When the IWADQ has at least one address entry available and the IWQ has at least one buffer 4191 ** available, the address is captured and the first data phase is accepted. 4192 ** �E The PCI interface continues to accept write data until one of the following is true: 4193 ** �X The initiator performs a disconnect. 4194 ** �X The transaction crosses a buffer boundary. 4195 ** �E When an address parity error is detected during the address phase of the transaction, the 4196 ** address parity error mechanisms are used. Refer to Section 3.7.1 for details of the address 4197 ** parity error response. 4198 ** �E When operating in the PCI-X mode when an attribute parity error is detected, the attribute 4199 ** parity error mechanism described in Section 3.7.1 is used. 4200 ** �E When a data parity error is detected while accepting data, the slave interface sets the 4201 ** appropriate bits based on PCI specifications. No other action is taken. Refer to Section 3.7.2.6 4202 ** for details of the inbound write data parity error response. 4203 ** Once the PCI interface places a PCI address in the IWADQ, when IWQ has received data sufficient 4204 ** to cross a buffer boundary or the master disconnects on the PCI bus, the ATUs internal bus 4205 ** interface becomes aware of the inbound write. When there are additional write transactions ahead 4206 ** in the IWQ/IWADQ, the current transaction remains posted until ordering and priority have been 4207 ** satisfied (Refer to Section 3.5.3) and the transaction is attempted on the internal bus by the ATU 4208 ** internal master interface. The ATU does not insert target wait states nor do data merging on the PCI 4209 ** interface, when operating in the PCI mode. 4210 ** In the PCI-X mode memory writes are always executed as immediate transactions, while 4211 ** configuration write transactions are processed as split transactions. The ATU generates a Split 4212 ** Completion Message, (with Message class=0h - Write Completion Class and Message index = 4213 ** 00h - Write Completion Message) once a configuration write is successfully executed. 4214 ** Also, when operating in the PCI-X mode a write sequence may contain multiple write transactions. 4215 ** The ATU handles such transactions as independent transactions. 4216 ** Data flow for the inbound write transaction on the internal bus is summarized as: 4217 ** �E The ATU internal bus master requests the internal bus when IWADQ has at least one entry 4218 ** with associated data in the IWQ. 4219 ** �E When the internal bus is granted, the internal bus master interface initiates the write 4220 ** transaction by driving the translated address onto the internal bus. For details on inbound 4221 ** address translation. 4222 ** �E When IB_DEVSEL# is not returned, a master abort condition is signaled on the internal bus. 4223 ** The current transaction is flushed from the queue and SERR# may be asserted on the PCI 4224 ** interface. 4225 ** �E The ATU initiator interface asserts IB_REQ64# to attempt a 64-bit transfer. When 4226 ** IB_ACK64# is not returned, a 32-bit transfer is used. Transfers of less than 64-bits use the 4227 ** IB_C/BE[7:0]# to mask the bytes not written in the 64-bit data phase. Write data is transferred 4228 ** from the IWQ to the internal bus when data is available and the internal bus interface retains 4229 ** internal bus ownership. 4230 ** �E The internal bus interface stops transferring data from the current transaction to the internal 4231 ** bus when one of the following conditions becomes true: 4232 ** �X The internal bus initiator interface loses bus ownership. The ATU internal initiator 4233 ** terminates the transfer (initiator disconnection) at the next ADB (for the internal bus ADB 4234 ** is defined as a naturally aligned 128-byte boundary) and attempt to reacquire the bus to 4235 ** complete the delivery of remaining data using the same sequence ID but with the 4236 ** modified starting address and byte count. 4237 ** �X A Disconnect at Next ADB is signaled on the internal bus from the internal target. When 4238 ** the transaction in the IWQ completes at that ADB, the initiator returns to idle. When the 4239 ** transaction in the IWQ is not complete, the initiator attempts to reacquire the bus to 4240 ** complete the delivery of remaining data using the same sequence ID but with the 4241 ** modified starting address and byte count. 4242 ** �X A Single Data Phase Disconnect is signaled on the internal bus from the internal target. 4243 ** When the transaction in the IWQ needs only a single data phase, the master returns to idle. 4244 ** When the transaction in the IWQ is not complete, the initiator attempts to reacquire the 4245 ** bus to complete the delivery of remaining data using the same sequence ID but with the 4246 ** modified starting address and byte count. 4247 ** �X The data from the current transaction has completed (satisfaction of byte count). An 4248 ** initiator termination is performed and the bus returns to idle. 4249 ** �X A Master Abort is signaled on the internal bus. SERR# may be asserted on the PCI bus. 4250 ** Data is flushed from the IWQ. 4251 ***************************************************************** 4252 */ 4253 4254 4255 4256 /* 4257 ************************************************************************** 4258 ** Inbound Read Completions Data Parity Errors 4259 **======================================================================== 4260 ** As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode. 4261 ** When as the completer of a Split Read Request the ATU observes PERR# assertion during the split 4262 ** completion transaction, the ATU attempts to complete the transaction normally and no further 4263 ** action is taken. 4264 ************************************************************************** 4265 */ 4266 4267 /* 4268 ************************************************************************** 4269 ** Inbound Configuration Write Completion Message Data Parity Errors 4270 **======================================================================== 4271 ** As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode. 4272 ** When as the completer of a Configuration (Split) Write Request the ATU observes PERR# 4273 ** assertion during the split completion transaction, the ATU attempts to complete the transaction 4274 ** normally and no further action is taken. 4275 ************************************************************************** 4276 */ 4277 4278 /* 4279 ************************************************************************** 4280 ** Inbound Read Request Data Parity Errors 4281 **===================== Immediate Data Transfer ========================== 4282 ** As a target, the ATU may encounter this error when operating in the Conventional PCI or PCI-X modes. 4283 ** Inbound read data parity errors occur when read data delivered from the IRQ is detected as having 4284 ** bad parity by the initiator of the transaction who is receiving the data. The initiator may optionally 4285 ** report the error to the system by asserting PERR#. As a target device in this scenario, no action is 4286 ** required and no error bits are set. 4287 **=====================Split Response Termination========================= 4288 ** As a target, the ATU may encounter this error when operating in the PCI-X mode. 4289 ** Inbound read data parity errors occur during the Split Response Termination. The initiator may 4290 ** optionally report the error to the system by asserting PERR#. As a target device in this scenario, no 4291 ** action is required and no error bits are set. 4292 ************************************************************************** 4293 */ 4294 4295 /* 4296 ************************************************************************** 4297 ** Inbound Write Request Data Parity Errors 4298 **======================================================================== 4299 ** As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes. 4300 ** Data parity errors occurring during write operations received by the ATU may assert PERR# on 4301 ** the PCI Bus. When an error occurs, the ATU continues accepting data until the initiator of the write 4302 ** transaction completes or a queue fill condition is reached. Specifically, the following actions with 4303 ** the given constraints are taken by the ATU: 4304 ** �E PERR# is asserted two clocks cycles (three clock cycles when operating in the PCI-X mode) 4305 ** following the data phase in which the data parity error is detected on the bus. This is only 4306 ** done when the Parity Error Response bit in the ATUCMD is set. 4307 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4308 ** actions is taken: 4309 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4310 ** Detected Parity Error bit in the ATUISR. When set, no action. 4311 *************************************************************************** 4312 */ 4313 4314 4315 /* 4316 *************************************************************************** 4317 ** Inbound Configuration Write Request 4318 ** ===================================================================== 4319 ** As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes. 4320 ** =============================================== 4321 ** Conventional PCI Mode 4322 ** =============================================== 4323 ** To allow for correct data parity calculations for delayed write transactions, the ATU delays the 4324 ** assertion of STOP# (signalling a Retry) until PAR is driven by the master. A parity error during a 4325 ** delayed write transaction (inbound configuration write cycle) can occur in any of the following 4326 ** parts of the transactions: 4327 ** �E During the initial Delayed Write Request cycle on the PCI bus when the ATU latches the 4328 ** address/command and data for delayed delivery to the internal configuration register. 4329 ** �E During the Delayed Write Completion cycle on the PCI bus when the ATU delivers the status 4330 ** of the operation back to the original master. 4331 ** The 80331 ATU PCI interface has the following responses to a delayed write parity error for 4332 ** inbound transactions during Delayed Write Request cycles with the given constraints: 4333 ** �E When the Parity Error Response bit in the ATUCMD is set, the ATU asserts TRDY# 4334 ** (disconnects with data) and two clock cycles later asserts PERR# notifying the initiator of the 4335 ** parity error. The delayed write cycle is not enqueued and forwarded to the internal bus. 4336 ** When the Parity Error Response bit in the ATUCMD is cleared, the ATU retries the 4337 ** transaction by asserting STOP# and enqueues the Delayed Write Request cycle to be 4338 ** forwarded to the internal bus. PERR# is not asserted. 4339 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4340 ** actions is taken: 4341 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4342 ** Detected Parity Error bit in the ATUISR. When set, no action. 4343 ** For the original write transaction to be completed, the initiator retries the transaction on the PCI 4344 ** bus and the ATU returns the status from the internal bus, completing the transaction. 4345 ** For the Delayed Write Completion transaction on the PCI bus where a data parity error occurs and 4346 ** therefore does not agree with the status being returned from the internal bus (i.e. status being 4347 ** returned is normal completion) the ATU performs the following actions with the given constraints: 4348 ** �E When the Parity Error Response Bit is set in the ATUCMD, the ATU asserts TRDY# 4349 ** (disconnects with data) and two clocks later asserts PERR#. The Delayed Completion cycle in 4350 ** the IDWQ remains since the data of retried command did not match the data within the queue. 4351 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4352 ** actions is taken: 4353 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4354 ** Detected Parity Error bit in the ATUISR. When set, no action. 4355 ** =================================================== 4356 ** PCI-X Mode 4357 ** =================================================== 4358 ** Data parity errors occurring during configuration write operations received by the ATU may cause 4359 ** PERR# assertion and delivery of a Split Completion Error Message on the PCI Bus. When an error 4360 ** occurs, the ATU accepts the write data and complete with a Split Response Termination. 4361 ** Specifically, the following actions with the given constraints are then taken by the ATU: 4362 ** �E When the Parity Error Response bit in the ATUCMD is set, PERR# is asserted three clocks 4363 ** cycles following the Split Response Termination in which the data parity error is detected on 4364 ** the bus. When the ATU asserts PERR#, additional actions is taken: 4365 ** �X A Split Write Data Parity Error message (with message class=2h - completer error and 4366 ** message index=01h - Split Write Data Parity Error) is initiated by the ATU on the PCI bus 4367 ** that addresses the requester of the configuration write. 4368 ** �X When the Initiated Split Completion Error Message Interrupt Mask in the ATUIMR is 4369 ** clear, set the Initiated Split Completion Error Message bit in the ATUISR. When set, no 4370 ** action. 4371 ** �X The Split Write Request is not enqueued and forwarded to the internal bus. 4372 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4373 ** actions is taken: 4374 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4375 ** Detected Parity Error bit in the ATUISR. When set, no action. 4376 ** 4377 *************************************************************************** 4378 */ 4379 4380 /* 4381 *************************************************************************** 4382 ** Split Completion Messages 4383 ** ======================================================================= 4384 ** As a target, the ATU may encounter this error when operating in the PCI-X mode. 4385 ** Data parity errors occurring during Split Completion Messages claimed by the ATU may assert 4386 ** PERR# (when enabled) or SERR# (when enabled) on the PCI Bus. When an error occurs, the 4387 ** ATU accepts the data and complete normally. Specifically, the following actions with the given 4388 ** constraints are taken by the ATU: 4389 ** �E PERR# is asserted three clocks cycles following the data phase in which the data parity error 4390 ** is detected on the bus. This is only done when the Parity Error Response bit in the ATUCMD 4391 ** is set. When the ATU asserts PERR#, additional actions is taken: 4392 ** �X The Master Parity Error bit in the ATUSR is set. 4393 ** �X When the ATU PCI Master Parity Error Interrupt Mask Bit in the ATUIMR is clear, set the 4394 ** PCI Master Parity Error bit in the ATUISR. When set, no action. 4395 ** �X When the SERR# Enable bit in the ATUCMD is set, and the Data Parity Error Recover 4396 ** Enable bit in the PCIXCMD register is clear, assert SERR#; otherwise no action is taken. 4397 ** When the ATU asserts SERR#, additional actions is taken: 4398 ** Set the SERR# Asserted bit in the ATUSR. 4399 ** When the ATU SERR# Asserted Interrupt Mask Bit in the ATUIMR is clear, set the 4400 ** SERR# Asserted bit in the ATUISR. When set, no action. 4401 ** When the ATU SERR# Detected Interrupt Enable Bit in the ATUCR is set, set the 4402 ** SERR# Detected bit in the ATUISR. When clear, no action. 4403 ** �E When the SCE bit (Split Completion Error -- bit 30 of the Completer Attributes) is set during 4404 ** the Attribute phase, the Received Split Completion Error Message bit in the PCIXSR is set. 4405 ** When the ATU sets this bit, additional actions is taken: 4406 ** �X When the ATU Received Split Completion Error Message Interrupt Mask bit in the 4407 ** ATUIMR is clear, set the Received Split Completion Error Message bit in the ATUISR. 4408 ** When set, no action. 4409 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4410 ** actions is taken: 4411 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4412 ** Detected Parity Error bit in the ATUISR. When set, no action. 4413 ** �E The transaction associated with the Split Completion Message is discarded. 4414 ** �E When the discarded transaction was a read, a completion error message (with message 4415 ** class=2h - completer error and message index=82h - PCI bus read parity error) is generated on 4416 ** the internal bus of the 80331. 4417 ***************************************************************************** 4418 */ 4419 4420 4421 /* 4422 ****************************************************************************************************** 4423 ** Messaging Unit (MU) of the Intel R 80331 I/O processor (80331) 4424 ** ================================================================================================== 4425 ** The Messaging Unit (MU) transfers data between the PCI system and the 80331 4426 ** notifies the respective system when new data arrives. 4427 ** The PCI window for messaging transactions is always the first 4 Kbytes of the inbound translation. 4428 ** window defined by: 4429 ** 1.Inbound ATU Base Address Register 0 (IABAR0) 4430 ** 2.Inbound ATU Limit Register 0 (IALR0) 4431 ** All of the Messaging Unit errors are reported in the same manner as ATU errors. 4432 ** Error conditions and status can be found in : 4433 ** 1.ATUSR 4434 ** 2.ATUISR 4435 **==================================================================================================== 4436 ** Mechanism Quantity Assert PCI Interrupt Signals Generate I/O Processor Interrupt 4437 **---------------------------------------------------------------------------------------------------- 4438 ** Message Registers 2 Inbound Optional Optional 4439 ** 2 Outbound 4440 **---------------------------------------------------------------------------------------------------- 4441 ** Doorbell Registers 1 Inbound Optional Optional 4442 ** 1 Outbound 4443 **---------------------------------------------------------------------------------------------------- 4444 ** Circular Queues 4 Circular Queues Under certain conditions Under certain conditions 4445 **---------------------------------------------------------------------------------------------------- 4446 ** Index Registers 1004 32-bit Memory Locations No Optional 4447 **==================================================================================================== 4448 ** PCI Memory Map: First 4 Kbytes of the ATU Inbound PCI Address Space 4449 **==================================================================================================== 4450 ** 0000H Reserved 4451 ** 0004H Reserved 4452 ** 0008H Reserved 4453 ** 000CH Reserved 4454 **------------------------------------------------------------------------ 4455 ** 0010H Inbound Message Register 0 ] 4456 ** 0014H Inbound Message Register 1 ] 4457 ** 0018H Outbound Message Register 0 ] 4458 ** 001CH Outbound Message Register 1 ] 4 Message Registers 4459 **------------------------------------------------------------------------ 4460 ** 0020H Inbound Doorbell Register ] 4461 ** 0024H Inbound Interrupt Status Register ] 4462 ** 0028H Inbound Interrupt Mask Register ] 4463 ** 002CH Outbound Doorbell Register ] 4464 ** 0030H Outbound Interrupt Status Register ] 4465 ** 0034H Outbound Interrupt Mask Register ] 2 Doorbell Registers and 4 Interrupt Registers 4466 **------------------------------------------------------------------------ 4467 ** 0038H Reserved 4468 ** 003CH Reserved 4469 **------------------------------------------------------------------------ 4470 ** 0040H Inbound Queue Port ] 4471 ** 0044H Outbound Queue Port ] 2 Queue Ports 4472 **------------------------------------------------------------------------ 4473 ** 0048H Reserved 4474 ** 004CH Reserved 4475 **------------------------------------------------------------------------ 4476 ** 0050H ] 4477 ** : ] 4478 ** : Intel Xscale Microarchitecture Local Memory ] 4479 ** : ] 4480 ** 0FFCH ] 1004 Index Registers 4481 ******************************************************************************* 4482 */ 4483 /* 4484 ***************************************************************************** 4485 ** Theory of MU Operation 4486 ***************************************************************************** 4487 **-------------------- 4488 ** inbound_msgaddr0: 4489 ** inbound_msgaddr1: 4490 ** outbound_msgaddr0: 4491 ** outbound_msgaddr1: 4492 ** . The MU has four independent messaging mechanisms. 4493 ** There are four Message Registers that are similar to a combination of mailbox and doorbell registers. 4494 ** Each holds a 32-bit value and generates an interrupt when written. 4495 **-------------------- 4496 ** inbound_doorbell: 4497 ** outbound_doorbell: 4498 ** . The two Doorbell Registers support software interrupts. 4499 ** When a bit is set in a Doorbell Register, an interrupt is generated. 4500 **-------------------- 4501 ** inbound_queueport: 4502 ** outbound_queueport: 4503 ** 4504 ** 4505 ** . The Circular Queues support a message passing scheme that uses 4 circular queues. 4506 ** The 4 circular queues are implemented in 80331 local memory. 4507 ** Two queues are used for inbound messages and two are used for outbound messages. 4508 ** Interrupts may be generated when the queue is written. 4509 **-------------------- 4510 ** local_buffer 0x0050 ....0x0FFF 4511 ** . The Index Registers use a portion of the 80331 local memory to implement a large set of message registers. 4512 ** When one of the Index Registers is written, an interrupt is generated and the address of the register written is captured. 4513 ** Interrupt status for all interrupts is recorded in the Inbound Interrupt Status Register and the Outbound Interrupt Status Register. 4514 ** Each interrupt generated by the Messaging Unit can be masked. 4515 **-------------------- 4516 ** . Multi-DWORD PCI burst accesses are not supported by the Messaging Unit, 4517 ** with the exception of Multi-DWORD reads to the index registers. 4518 ** In Conventional mode: the MU terminates Multi-DWORD PCI transactions 4519 ** (other than index register reads) with a disconnect at the next Qword boundary, with the exception of queue ports. 4520 ** In PCI-X mode : the MU terminates a Multi-DWORD PCI read transaction with a Split Response 4521 ** and the data is returned through split completion transaction(s). 4522 ** however, when the burst request crosses into or through the range of offsets 40h to 4Ch 4523 ** (e.g., this includes the queue ports) the transaction is signaled target-abort immediately on the PCI bus. 4524 ** In PCI-X mode, Multi-DWORD PCI writes is signaled a Single-Data-Phase Disconnect 4525 ** which means that no data beyond the first Qword (Dword when the MU does not assert P_ACK64#) is written. 4526 **-------------------- 4527 ** . All registers needed to configure and control the Messaging Unit are memory-mapped registers. 4528 ** The MU uses the first 4 Kbytes of the inbound translation window in the Address Translation Unit (ATU). 4529 ** This PCI address window is used for PCI transactions that access the 80331 local memory. 4530 ** The PCI address of the inbound translation window is contained in the Inbound ATU Base Address Register. 4531 **-------------------- 4532 ** . From the PCI perspective, the Messaging Unit is part of the Address Translation Unit. 4533 ** The Messaging Unit uses the PCI configuration registers of the ATU for control and status information. 4534 ** The Messaging Unit must observe all PCI control bits in the ATU Command Register and ATU Configuration Register. 4535 ** The Messaging Unit reports all PCI errors in the ATU Status Register. 4536 **-------------------- 4537 ** . Parts of the Messaging Unit can be accessed as a 64-bit PCI device. 4538 ** The register interface, message registers, doorbell registers, 4539 ** and index registers returns a P_ACK64# in response to a P_REQ64# on the PCI interface. 4540 ** Up to 1 Qword of data can be read or written per transaction (except Index Register reads). 4541 ** The Inbound and Outbound Queue Ports are always 32-bit addresses and the MU does not assert P_ACK64# to offsets 40H and 44H. 4542 ************************************************************************** 4543 */ 4544 /* 4545 ************************************************************************** 4546 ** Message Registers 4547 ** ============================== 4548 ** . Messages can be sent and received by the 80331 through the use of the Message Registers. 4549 ** . When written, the message registers may cause an interrupt to be generated to either the Intel XScale core or the host processor. 4550 ** . Inbound messages are sent by the host processor and received by the 80331. 4551 ** Outbound messages are sent by the 80331 and received by the host processor. 4552 ** . The interrupt status for outbound messages is recorded in the Outbound Interrupt Status Register. 4553 ** Interrupt status for inbound messages is recorded in the Inbound Interrupt Status Register. 4554 ** 4555 ** Inbound Messages: 4556 ** ----------------- 4557 ** . When an inbound message register is written by an external PCI agent, an interrupt may be generated to the Intel XScale core. 4558 ** . The interrupt may be masked by the mask bits in the Inbound Interrupt Mask Register. 4559 ** . The Intel XScale core interrupt is recorded in the Inbound Interrupt Status Register. 4560 ** The interrupt causes the Inbound Message Interrupt bit to be set in the Inbound Interrupt Status Register. 4561 ** This is a Read/Clear bit that is set by the MU hardware and cleared by software. 4562 ** The interrupt is cleared when the Intel XScale core writes a value of 4563 ** 1 to the Inbound Message Interrupt bit in the Inbound Interrupt Status Register. 4564 ** ------------------------------------------------------------------------ 4565 ** Inbound Message Register - IMRx 4566 ** 4567 ** . There are two Inbound Message Registers: IMR0 and IMR1. 4568 ** . When the IMR register is written, an interrupt to the Intel XScale core may be generated. 4569 ** The interrupt is recorded in the Inbound Interrupt Status Register and may be masked 4570 ** by the Inbound Message Interrupt Mask bit in the Inbound Interrupt Mask Register. 4571 ** ----------------------------------------------------------------- 4572 ** Bit Default Description 4573 ** 31:00 0000 0000H Inbound Message - This is a 32-bit message written by an external PCI agent. 4574 ** When written, an interrupt to the Intel XScale core may be generated. 4575 ************************************************************************** 4576 */ 4577 #define ARCMSR_MU_INBOUND_MESSAGE_REG0 0x10 /*dword 0x13,0x12,0x11,0x10*/ 4578 #define ARCMSR_MU_INBOUND_MESSAGE_REG1 0x14 /*dword 0x17,0x16,0x15,0x14*/ 4579 /* 4580 ************************************************************************** 4581 ** Outbound Message Register - OMRx 4582 ** -------------------------------- 4583 ** There are two Outbound Message Registers: OMR0 and OMR1. When the OMR register is 4584 ** written, a PCI interrupt may be generated. The interrupt is recorded in the Outbound Interrupt 4585 ** Status Register and may be masked by the Outbound Message Interrupt Mask bit in the Outbound 4586 ** Interrupt Mask Register. 4587 ** 4588 ** Bit Default Description 4589 ** 31:00 00000000H Outbound Message - This is 32-bit message written by the Intel XScale core. When written, an 4590 ** interrupt may be generated on the PCI Interrupt pin determined by the ATU Interrupt Pin Register. 4591 ************************************************************************** 4592 */ 4593 #define ARCMSR_MU_OUTBOUND_MESSAGE_REG0 0x18 /*dword 0x1B,0x1A,0x19,0x18*/ 4594 #define ARCMSR_MU_OUTBOUND_MESSAGE_REG1 0x1C /*dword 0x1F,0x1E,0x1D,0x1C*/ 4595 /* 4596 ************************************************************************** 4597 ** Doorbell Registers 4598 ** ============================== 4599 ** There are two Doorbell Registers: 4600 ** Inbound Doorbell Register 4601 ** Outbound Doorbell Register 4602 ** The Inbound Doorbell Register allows external PCI agents to generate interrupts to the Intel R XScale core. 4603 ** The Outbound Doorbell Register allows the Intel R XScale core to generate a PCI interrupt. 4604 ** Both Doorbell Registers may generate interrupts whenever a bit in the register is set. 4605 ** 4606 ** Inbound Doorbells: 4607 ** ------------------ 4608 ** . When the Inbound Doorbell Register is written by an external PCI agent, an interrupt may be generated to the Intel R XScale core. 4609 ** An interrupt is generated when any of the bits in the doorbell register is written to a value of 1. 4610 ** Writing a value of 0 to any bit does not change the value of that bit and does not cause an interrupt to be generated. 4611 ** . Once a bit is set in the Inbound Doorbell Register, it cannot be cleared by any external PCI agent. 4612 ** The interrupt is recorded in the Inbound Interrupt Status Register. 4613 ** . The interrupt may be masked by the Inbound Doorbell Interrupt mask bit in the Inbound Interrupt Mask Register. 4614 ** When the mask bit is set for a particular bit, no interrupt is generated for that bit. 4615 ** The Inbound Interrupt Mask Register affects only the generation of the normal messaging unit interrupt 4616 ** and not the values written to the Inbound Doorbell Register. 4617 ** One bit in the Inbound Doorbell Register is reserved for an Error Doorbell interrupt. 4618 ** . The interrupt is cleared when the Intel R XScale core writes a value of 1 to the bits in the Inbound Doorbell Register that are set. 4619 ** Writing a value of 0 to any bit does not change the value of that bit and does not clear the interrupt. 4620 ** ------------------------------------------------------------------------ 4621 ** Inbound Doorbell Register - IDR 4622 ** 4623 ** . The Inbound Doorbell Register (IDR) is used to generate interrupts to the Intel XScale core. 4624 ** . Bit 31 is reserved for generating an Error Doorbell interrupt. 4625 ** When bit 31 is set, an Error interrupt may be generated to the Intel XScale core. 4626 ** All other bits, when set, cause the Normal Messaging Unit interrupt line of the Intel XScale core to be asserted, 4627 ** when the interrupt is not masked by the Inbound Doorbell Interrupt Mask bit in the Inbound Interrupt Mask Register. 4628 ** The bits in the IDR register can only be set by an external PCI agent and can only be cleared by the Intel XScale core. 4629 ** ------------------------------------------------------------------------ 4630 ** Bit Default Description 4631 ** 31 0 2 Error Interrupt - Generate an Error Interrupt to the Intel XScale core. 4632 ** 30:00 00000000H Normal Interrupt - When any bit is set, generate a Normal interrupt to the Intel XScale core. 4633 ** When all bits are clear, do not generate a Normal Interrupt. 4634 ************************************************************************** 4635 */ 4636 #define ARCMSR_MU_INBOUND_DOORBELL_REG 0x20 /*dword 0x23,0x22,0x21,0x20*/ 4637 /* 4638 ************************************************************************** 4639 ** Inbound Interrupt Status Register - IISR 4640 ** 4641 ** . The Inbound Interrupt Status Register (IISR) contains hardware interrupt status. 4642 ** It records the status of Intel XScale core interrupts generated by the Message Registers, Doorbell Registers, and the Circular Queues. 4643 ** All interrupts are routed to the Normal Messaging Unit interrupt input of the Intel XScale core, 4644 ** except for the Error Doorbell Interrupt and the Outbound Free Queue Full interrupt; 4645 ** these two are routed to the Messaging Unit Error interrupt input. 4646 ** The generation of interrupts recorded in the Inbound Interrupt Status Register 4647 ** may be masked by setting the corresponding bit in the Inbound Interrupt Mask Register. 4648 ** Some of the bits in this register are Read Only. 4649 ** For those bits, the interrupt must be cleared through another register. 4650 ** 4651 ** Bit Default Description 4652 ** 31:07 0000000H 0 2 Reserved 4653 ** 06 0 2 Index Register Interrupt - This bit is set by the MU hardware 4654 ** when an Index Register has been written after a PCI transaction. 4655 ** 05 0 2 Outbound Free Queue Full Interrupt - This bit is set 4656 ** when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full. 4657 ** An Error interrupt is generated for this condition. 4658 ** 04 0 2 Inbound Post Queue Interrupt - This bit is set by the MU hardware when the Inbound Post Queue has been written. 4659 ** Once cleared, an interrupt does NOT be generated 4660 ** when the head and tail pointers remain unequal (i.e. queue status is Not Empty). 4661 ** Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared, 4662 ** software must retain the information that the Inbound Post queue status is not empty. 4663 ** NOTE: This interrupt is provided with dedicated support in the 80331 Interrupt Controller. 4664 ** 03 0 2 Error Doorbell Interrupt - This bit is set when the Error Interrupt of the Inbound Doorbell Register is set. 4665 ** To clear this bit (and the interrupt), the Error Interrupt bit of the Inbound Doorbell Register must be clear. 4666 ** 02 0 2 Inbound Doorbell Interrupt - This bit is set when at least one 4667 ** Normal Interrupt bit in the Inbound Doorbell Register is set. 4668 ** To clear this bit (and the interrupt), the Normal Interrupt bits in the Inbound Doorbell Register must all be clear. 4669 ** 01 0 2 Inbound Message 1 Interrupt - This bit is set by the MU hardware when the Inbound Message 1 Register has been written. 4670 ** 00 0 2 Inbound Message 0 Interrupt - This bit is set by the MU hardware when the Inbound Message 0 Register has been written. 4671 ************************************************************************** 4672 */ 4673 #define ARCMSR_MU_INBOUND_INTERRUPT_STATUS_REG 0x24 /*dword 0x27,0x26,0x25,0x24*/ 4674 #define ARCMSR_MU_INBOUND_INDEX_INT 0x40 4675 #define ARCMSR_MU_INBOUND_QUEUEFULL_INT 0x20 4676 #define ARCMSR_MU_INBOUND_POSTQUEUE_INT 0x10 4677 #define ARCMSR_MU_INBOUND_ERROR_DOORBELL_INT 0x08 4678 #define ARCMSR_MU_INBOUND_DOORBELL_INT 0x04 4679 #define ARCMSR_MU_INBOUND_MESSAGE1_INT 0x02 4680 #define ARCMSR_MU_INBOUND_MESSAGE0_INT 0x01 4681 /* 4682 ************************************************************************** 4683 ** Inbound Interrupt Mask Register - IIMR 4684 ** 4685 ** . The Inbound Interrupt Mask Register (IIMR) provides the ability to mask Intel XScale core interrupts generated by the Messaging Unit. 4686 ** Each bit in the Mask register corresponds to an interrupt bit in the Inbound Interrupt Status Register. 4687 ** Setting or clearing bits in this register does not affect the Inbound Interrupt Status Register. 4688 ** They only affect the generation of the Intel XScale core interrupt. 4689 ** ------------------------------------------------------------------------ 4690 ** Bit Default Description 4691 ** 31:07 000000H 0 2 Reserved 4692 ** 06 0 2 Index Register Interrupt Mask - When set, this bit masks the interrupt generated by the MU hardware 4693 ** when an Index Register has been written after a PCI transaction. 4694 ** 05 0 2 Outbound Free Queue Full Interrupt Mask - When set, this bit masks the Error interrupt generated 4695 ** when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full. 4696 ** 04 0 2 Inbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated 4697 ** by the MU hardware when the Inbound Post Queue has been written. 4698 ** 03 0 2 Error Doorbell Interrupt Mask - When set, this bit masks the Error Interrupt 4699 ** when the Error Interrupt bit of the Inbound Doorbell Register is set. 4700 ** 02 0 2 Inbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated 4701 ** when at least one Normal Interrupt bit in the Inbound Doorbell Register is set. 4702 ** 01 0 2 Inbound Message 1 Interrupt Mask - When set, this bit masks the Inbound Message 1 4703 ** Interrupt generated by a write to the Inbound Message 1 Register. 4704 ** 00 0 2 Inbound Message 0 Interrupt Mask - When set, 4705 ** this bit masks the Inbound Message 0 Interrupt generated by a write to the Inbound Message 0 Register. 4706 ************************************************************************** 4707 */ 4708 #define ARCMSR_MU_INBOUND_INTERRUPT_MASK_REG 0x28 /*dword 0x2B,0x2A,0x29,0x28*/ 4709 #define ARCMSR_MU_INBOUND_INDEX_INTMASKENABLE 0x40 4710 #define ARCMSR_MU_INBOUND_QUEUEFULL_INTMASKENABLE 0x20 4711 #define ARCMSR_MU_INBOUND_POSTQUEUE_INTMASKENABLE 0x10 4712 #define ARCMSR_MU_INBOUND_DOORBELL_ERROR_INTMASKENABLE 0x08 4713 #define ARCMSR_MU_INBOUND_DOORBELL_INTMASKENABLE 0x04 4714 #define ARCMSR_MU_INBOUND_MESSAGE1_INTMASKENABLE 0x02 4715 #define ARCMSR_MU_INBOUND_MESSAGE0_INTMASKENABLE 0x01 4716 /* 4717 ************************************************************************** 4718 ** Outbound Doorbell Register - ODR 4719 ** 4720 ** The Outbound Doorbell Register (ODR) allows software interrupt generation. It allows the Intel 4721 ** XScale core to generate PCI interrupts to the host processor by writing to this register. The 4722 ** generation of PCI interrupts through the Outbound Doorbell Register may be masked by setting the 4723 ** Outbound Doorbell Interrupt Mask bit in the Outbound Interrupt Mask Register. 4724 ** The Software Interrupt bits in this register can only be set by the Intel XScale core and can only 4725 ** be cleared by an external PCI agent. 4726 ** ---------------------------------------------------------------------- 4727 ** Bit Default Description 4728 ** 31 0 2 Reserved 4729 ** 30 0 2 Reserved. 4730 ** 29 0 2 Reserved 4731 ** 28 0000 0000H PCI Interrupt - When set, this bit causes the P_INTC# interrupt output 4732 ** (P_INTA# with BRG_EN and ARB_EN straps low) 4733 ** signal to be asserted or a Message-signaled Interrupt is generated (when enabled). 4734 ** When this bit is cleared, the P_INTC# interrupt output 4735 ** (P_INTA# with BRG_EN and ARB_EN straps low) 4736 ** signal is deasserted. 4737 ** 27:00 000 0000H Software Interrupts - When any bit is set the P_INTC# interrupt output 4738 ** (P_INTA# with BRG_EN and ARB_EN straps low) 4739 ** signal is asserted or a Message-signaled Interrupt is generated (when enabled). 4740 ** When all bits are cleared, the P_INTC# interrupt output (P_INTA# with BRG_EN and ARB_EN straps low) 4741 ** signal is deasserted. 4742 ************************************************************************** 4743 */ 4744 #define ARCMSR_MU_OUTBOUND_DOORBELL_REG 0x2C /*dword 0x2F,0x2E,0x2D,0x2C*/ 4745 /* 4746 ************************************************************************** 4747 ** Outbound Interrupt Status Register - OISR 4748 ** 4749 ** The Outbound Interrupt Status Register (OISR) contains hardware interrupt status. It records the 4750 ** status of PCI interrupts generated by the Message Registers, Doorbell Registers, and the Circular 4751 ** Queues. The generation of PCI interrupts recorded in the Outbound Interrupt Status Register may 4752 ** be masked by setting the corresponding bit in the Outbound Interrupt Mask Register. Some of the 4753 ** bits in this register are Read Only. For those bits, the interrupt must be cleared through another 4754 ** register. 4755 ** ---------------------------------------------------------------------- 4756 ** Bit Default Description 4757 ** 31:05 000000H 000 2 Reserved 4758 ** 04 0 2 PCI Interrupt - This bit is set when the PCI Interrupt bit (bit 28) is set in the Outbound Doorbell Register. 4759 ** To clear this bit (and the interrupt), the PCI Interrupt bit must be cleared. 4760 ** 03 0 2 Outbound Post Queue Interrupt - This bit is set when data in the prefetch buffer is valid. This bit is 4761 ** cleared when any prefetch data has been read from the Outbound Queue Port. 4762 ** 02 0 2 Outbound Doorbell Interrupt - This bit is set when at least one Software Interrupt bit in the Outbound 4763 ** Doorbell Register is set. To clear this bit (and the interrupt), the Software Interrupt bits in the Outbound 4764 ** Doorbell Register must all be clear. 4765 ** 01 0 2 Outbound Message 1 Interrupt - This bit is set by the MU when the Outbound Message 1 Register is 4766 ** written. Clearing this bit clears the interrupt. 4767 ** 00 0 2 Outbound Message 0 Interrupt - This bit is set by the MU when the Outbound Message 0 Register is 4768 ** written. Clearing this bit clears the interrupt. 4769 ************************************************************************** 4770 */ 4771 #define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30 /*dword 0x33,0x32,0x31,0x30*/ 4772 #define ARCMSR_MU_OUTBOUND_PCI_INT 0x10 4773 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08 4774 #define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04 4775 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02 4776 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01 4777 /* 4778 ************************************************************************** 4779 ** Outbound Interrupt Mask Register - OIMR 4780 ** The Outbound Interrupt Mask Register (OIMR) provides the ability to mask outbound PCI 4781 ** interrupts generated by the Messaging Unit. Each bit in the mask register corresponds to a 4782 ** hardware interrupt bit in the Outbound Interrupt Status Register. When the bit is set, the PCI 4783 ** interrupt is not generated. When the bit is clear, the interrupt is allowed to be generated. 4784 ** Setting or clearing bits in this register does not affect the Outbound Interrupt Status Register. They 4785 ** only affect the generation of the PCI interrupt. 4786 ** ---------------------------------------------------------------------- 4787 ** Bit Default Description 4788 ** 31:05 000000H Reserved 4789 ** 04 0 2 PCI Interrupt Mask - When set, this bit masks the interrupt generation when the PCI Interrupt bit (bit 28) 4790 ** in the Outbound Doorbell Register is set. 4791 ** 03 0 2 Outbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated when data in 4792 ** the prefetch buffer is valid. 4793 ** 02 0 2 Outbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated by the Outbound 4794 ** Doorbell Register. 4795 ** 01 0 2 Outbound Message 1 Interrupt Mask - When set, this bit masks the Outbound Message 1 Interrupt 4796 ** generated by a write to the Outbound Message 1 Register. 4797 ** 00 0 2 Outbound Message 0 Interrupt Mask- When set, this bit masks the Outbound Message 0 Interrupt 4798 ** generated by a write to the Outbound Message 0 Register. 4799 ************************************************************************** 4800 */ 4801 #define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34 /*dword 0x37,0x36,0x35,0x34*/ 4802 #define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10 4803 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08 4804 #define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04 4805 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02 4806 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01 4807 #define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F 4808 /* 4809 ************************************************************************** 4810 ** 4811 ************************************************************************** 4812 */ 4813 #define ARCMSR_MU_INBOUND_QUEUE_PORT_REG 0x40 /*dword 0x43,0x42,0x41,0x40*/ 4814 #define ARCMSR_MU_OUTBOUND_QUEUE_PORT_REG 0x44 /*dword 0x47,0x46,0x45,0x44*/ 4815 /* 4816 ************************************************************************** 4817 ** Circular Queues 4818 ** ====================================================================== 4819 ** The MU implements four circular queues. There are 2 inbound queues and 2 outbound queues. In 4820 ** this case, inbound and outbound refer to the direction of the flow of posted messages. 4821 ** Inbound messages are either: 4822 ** �E posted messages by other processors for the Intel XScale core to process or 4823 ** �E free (or empty) messages that can be reused by other processors. 4824 ** Outbound messages are either: 4825 ** �E posted messages by the Intel XScale core for other processors to process or 4826 ** �E free (or empty) messages that can be reused by the Intel XScale core. 4827 ** Therefore, free inbound messages flow away from the 80331 and free outbound messages flow toward the 80331. 4828 ** The four Circular Queues are used to pass messages in the following manner. 4829 ** . The two inbound queues are used to handle inbound messages 4830 ** and the two outbound queues are used to handle outbound messages. 4831 ** . One of the inbound queues is designated the Free queue and it contains inbound free messages. 4832 ** The other inbound queue is designated the Post queue and it contains inbound posted messages. 4833 ** Similarly, one of the outbound queues is designated the Free queue and the other outbound queue is designated the Post queue. 4834 ** 4835 ** ============================================================================================================= 4836 ** Circular Queue Summary 4837 ** _____________________________________________________________________________________________________________ 4838 ** | Queue Name | Purpose | Action on PCI Interface| 4839 ** |______________________|____________________________________________________________|_________________________| 4840 ** |Inbound Post Queue | Queue for inbound messages from other processors | Written | 4841 ** | | waiting to be processed by the 80331 | | 4842 ** |Inbound Free Queue | Queue for empty inbound messages from the 80331 | Read | 4843 ** | | available for use by other processors | | 4844 ** |Outbound Post Queue | Queue for outbound messages from the 80331 | Read | 4845 ** | | that are being posted to the other processors | | 4846 ** |Outbound Free Queue | Queue for empty outbound messages from other processors | Written | 4847 ** | | available for use by the 80331 | | 4848 ** |______________________|____________________________________________________________|_________________________| 4849 ** 4850 ** . The two inbound queues allow the host processor to post inbound messages for the 80331 in one 4851 ** queue and to receive free messages returning from the 80331. 4852 ** The host processor posts inbound messages, 4853 ** the Intel XScale core receives the posted message and when it is finished with the message, 4854 ** places it back on the inbound free queue for reuse by the host processor. 4855 ** 4856 ** The circular queues are accessed by external PCI agents through two port locations in the PCI 4857 ** address space: 4858 ** Inbound Queue Port 4859 ** and Outbound Queue Port. 4860 ** The Inbound Queue Port is used by external PCI agents to read the Inbound Free Queue and write the Inbound Post Queue. 4861 ** The Outbound Queue Port is used by external PCI agents to read the Outbound Post Queue and write the Outbound Free Queue. 4862 ** Note that a PCI transaction to the inbound or outbound queue ports with null byte enables (P_C/BE[3:0]#=1111 2 ) 4863 ** does not cause the MU hardware to increment the queue pointers. 4864 ** This is treated as when the PCI transaction did not occur. 4865 ** The Inbound and Outbound Queue Ports never respond with P_ACK64# on the PCI interface. 4866 ** ====================================================================================== 4867 ** Overview of Circular Queue Operation 4868 ** ====================================================================================== 4869 ** . The data storage for the circular queues must be provided by the 80331 local memory. 4870 ** . The base address of the circular queues is contained in the Queue Base Address Register. 4871 ** Each entry in the queue is a 32-bit data value. 4872 ** . Each read from or write to the queue may access only one queue entry. 4873 ** . Multi-DWORD accesses to the circular queues are not allowed. 4874 ** Sub-DWORD accesses are promoted to DWORD accesses. 4875 ** . Each circular queue has a head pointer and a tail pointer. 4876 ** The pointers are offsets from the Queue Base Address. 4877 ** . Writes to a queue occur at the head of the queue and reads occur from the tail. 4878 ** The head and tail pointers are incremented by either the Intel XScale core or the Messaging Unit hardware. 4879 ** Which unit maintains the pointer is determined by the writer of the queue. 4880 ** More details about the pointers are given in the queue descriptions below. 4881 ** The pointers are incremented after the queue access. 4882 ** Both pointers wrap around to the first address of the circular queue when they reach the circular queue size. 4883 ** 4884 ** Messaging Unit... 4885 ** 4886 ** The Messaging Unit generates an interrupt to the Intel XScale core or generate a PCI interrupt under certain conditions. 4887 ** . In general, when a Post queue is written, an interrupt is generated to notify the receiver that a message was posted. 4888 ** The size of each circular queue can range from 4K entries (16 Kbytes) to 64K entries (256 Kbytes). 4889 ** . All four queues must be the same size and may be contiguous. 4890 ** Therefore, the total amount of local memory needed by the circular queues ranges from 64 Kbytes to 1 Mbytes. 4891 ** The Queue size is determined by the Queue Size field in the MU Configuration Register. 4892 ** . There is one base address for all four queues. 4893 ** It is stored in the Queue Base Address Register (QBAR). 4894 ** The starting addresses of each queue is based on the Queue Base Address and the Queue Size field. 4895 ** here shows an example of how the circular queues should be set up based on the 4896 ** Intelligent I/O (I 2 O) Architecture Specification. 4897 ** Other ordering of the circular queues is possible. 4898 ** 4899 ** Queue Starting Address 4900 ** Inbound Free Queue QBAR 4901 ** Inbound Post Queue QBAR + Queue Size 4902 ** Outbound Post Queue QBAR + 2 * Queue Size 4903 ** Outbound Free Queue QBAR + 3 * Queue Size 4904 ** =================================================================================== 4905 ** Inbound Post Queue 4906 ** ------------------ 4907 ** The Inbound Post Queue holds posted messages placed there by other processors for the Intel XScale core to process. 4908 ** This queue is read from the queue tail by the Intel XScale core. It is written to the queue head by external PCI agents. 4909 ** The tail pointer is maintained by the Intel XScale core. The head pointer is maintained by the MU hardware. 4910 ** For a PCI write transaction that accesses the Inbound Queue Port, 4911 ** the MU writes the data to the local memory location address in the Inbound Post Head Pointer Register. 4912 ** When the data written to the Inbound Queue Port is written to local memory, the MU hardware increments the Inbound Post Head Pointer Register. 4913 ** An Intel XScale core interrupt may be generated when the Inbound Post Queue is written. 4914 ** The Inbound Post Queue Interrupt bit in the Inbound Interrupt Status Register indicates the interrupt status. 4915 ** The interrupt is cleared when the Inbound Post Queue Interrupt bit is cleared. 4916 ** The interrupt can be masked by the Inbound Interrupt Mask Register. 4917 ** Software must be aware of the state of the Inbound Post Queue Interrupt Mask bit to guarantee 4918 ** that the full condition is recognized by the core processor. 4919 ** In addition, to guarantee that the queue does not get overwritten, 4920 ** software must process messages from the tail of the queue before incrementing the tail pointer and clearing this interrupt. 4921 ** Once cleared, an interrupt is NOT generated when the head and tail pointers remain unequal (i.e. queue status is Not Empty). 4922 ** Only a new message posting the in the inbound queue generates a new interrupt. 4923 ** Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared, 4924 ** software must retain the information that the Inbound Post queue status. 4925 ** From the time that the PCI write transaction is received until the data is written 4926 ** in local memory and the Inbound Post Head Pointer Register is incremented, 4927 ** any PCI transaction that attempts to access the Inbound Post Queue Port is signalled a Retry. 4928 ** The Intel XScale core may read messages from the Inbound Post Queue 4929 ** by reading the data from the local memory location pointed to by the Inbound Post Tail Pointer Register. 4930 ** The Intel XScale core must then increment the Inbound Post Tail Pointer Register. 4931 ** When the Inbound Post Queue is full (head and tail pointers are equal and the head pointer was last updated by hardware), 4932 ** the hardware retries any PCI writes until a slot in the queue becomes available. 4933 ** A slot in the post queue becomes available by the Intel XScale core incrementing the tail pointer. 4934 ** =================================================================================== 4935 ** Inbound Free Queue 4936 ** ------------------ 4937 ** The Inbound Free Queue holds free inbound messages placed there by the Intel XScale core for other processors to use. 4938 ** This queue is read from the queue tail by external PCI agents. 4939 ** It is written to the queue head by the Intel XScale core. 4940 ** The tail pointer is maintained by the MU hardware. 4941 ** The head pointer is maintained by the Intel XScale core. 4942 ** For a PCI read transaction that accesses the Inbound Queue Port, 4943 ** the MU attempts to read the data at the local memory address in the Inbound Free Tail Pointer. 4944 ** When the queue is not empty (head and tail pointers are not equal) 4945 ** or full (head and tail pointers are equal but the head pointer was last written by software), the data is returned. 4946 ** When the queue is empty (head and tail pointers are equal and the head pointer was last updated by hardware), 4947 ** the value of -1 (FFFF.FFFFH) is returned. 4948 ** When the queue was not empty and the MU succeeded in returning the data at the tail, 4949 ** the MU hardware must increment the value in the Inbound Free Tail Pointer Register. 4950 ** To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate accesses to the Inbound Free Queue. 4951 ** The MU hardware prefetches the data at the tail of the Inbound Free Queue and load it into an internal prefetch register. 4952 ** When the PCI read access occurs, the data is read directly from the prefetch register. 4953 ** The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register 4954 ** when the head and tail pointers are equal and the queue is empty. 4955 ** In order to update the prefetch register when messages are added to the queue and it becomes non-empty, 4956 ** the prefetch mechanism automatically starts a prefetch when the prefetch register contains FFFF.FFFFH 4957 ** and the Inbound Free Head Pointer Register is written. 4958 ** The Intel XScale core needs to update the Inbound Free Head Pointer Register when it adds messages to the queue. 4959 ** A prefetch must appear atomic from the perspective of the external PCI agent. 4960 ** When a prefetch is started, any PCI transaction that attempts to access the Inbound Free Queue is signalled a Retry until the prefetch is completed. 4961 ** The Intel XScale core may place messages in the Inbound Free Queue by writing the data to the 4962 ** local memory location pointed to by the Inbound Free Head Pointer Register. 4963 ** The processor must then increment the Inbound Free Head Pointer Register. 4964 ** ================================================================================== 4965 ** Outbound Post Queue 4966 ** ------------------- 4967 ** The Outbound Post Queue holds outbound posted messages placed there by the Intel XScale 4968 ** core for other processors to process. This queue is read from the queue tail by external PCI agents. 4969 ** It is written to the queue head by the Intel XScale core. The tail pointer is maintained by the 4970 ** MU hardware. The head pointer is maintained by the Intel XScale core. 4971 ** For a PCI read transaction that accesses the Outbound Queue Port, the MU attempts to read the 4972 ** data at the local memory address in the Outbound Post Tail Pointer Register. When the queue is not 4973 ** empty (head and tail pointers are not equal) or full (head and tail pointers are equal but the head 4974 ** pointer was last written by software), the data is returned. When the queue is empty (head and tail 4975 ** pointers are equal and the head pointer was last updated by hardware), the value of -1 4976 ** (FFFF.FFFFH) is returned. When the queue was not empty and the MU succeeded in returning the 4977 ** data at the tail, the MU hardware must increment the value in the Outbound Post Tail Pointer 4978 ** Register. 4979 ** To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate 4980 ** accesses to the Outbound Post Queue. The MU hardware prefetches the data at the tail of the 4981 ** Outbound Post Queue and load it into an internal prefetch register. When the PCI read access 4982 ** occurs, the data is read directly from the prefetch register. 4983 ** The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register when the head 4984 ** and tail pointers are equal and the queue is empty. In order to update the prefetch register when 4985 ** messages are added to the queue and it becomes non-empty, the prefetch mechanism automatically 4986 ** starts a prefetch when the prefetch register contains FFFF.FFFFH and the Outbound Post Head 4987 ** Pointer Register is written. The Intel XScale core needs to update the Outbound Post Head 4988 ** Pointer Register when it adds messages to the queue. 4989 ** A prefetch must appear atomic from the perspective of the external PCI agent. When a prefetch is 4990 ** started, any PCI transaction that attempts to access the Outbound Post Queue is signalled a Retry 4991 ** until the prefetch is completed. 4992 ** A PCI interrupt may be generated when data in the prefetch buffer is valid. When the prefetch 4993 ** queue is clear, no interrupt is generated. The Outbound Post Queue Interrupt bit in the Outbound 4994 ** Interrupt Status Register shall indicate the status of the prefetch buffer data and therefore the 4995 ** interrupt status. The interrupt is cleared when any prefetched data has been read from the Outbound 4996 ** Queue Port. The interrupt can be masked by the Outbound Interrupt Mask Register. 4997 ** The Intel XScale core may place messages in the Outbound Post Queue by writing the data to 4998 ** the local memory address in the Outbound Post Head Pointer Register. The processor must then 4999 ** increment the Outbound Post Head Pointer Register. 5000 ** ================================================== 5001 ** Outbound Free Queue 5002 ** ----------------------- 5003 ** The Outbound Free Queue holds free messages placed there by other processors for the Intel 5004 ** XScale core to use. This queue is read from the queue tail by the Intel XScale core. It is 5005 ** written to the queue head by external PCI agents. The tail pointer is maintained by the Intel 5006 ** XScale core. The head pointer is maintained by the MU hardware. 5007 ** For a PCI write transaction that accesses the Outbound Queue Port, the MU writes the data to the 5008 ** local memory address in the Outbound Free Head Pointer Register. When the data written to the 5009 ** Outbound Queue Port is written to local memory, the MU hardware increments the Outbound Free 5010 ** Head Pointer Register. 5011 ** When the head pointer and the tail pointer become equal and the queue is full, the MU may signal 5012 ** an interrupt to the Intel XScale core to register the queue full condition. This interrupt is 5013 ** recorded in the Inbound Interrupt Status Register. The interrupt is cleared when the Outbound Free 5014 ** Queue Full Interrupt bit is cleared and not by writing to the head or tail pointers. The interrupt can 5015 ** be masked by the Inbound Interrupt Mask Register. Software must be aware of the state of the 5016 ** Outbound Free Queue Interrupt Mask bit to guarantee that the full condition is recognized by the 5017 ** core processor. 5018 ** From the time that a PCI write transaction is received until the data is written in local memory and 5019 ** the Outbound Free Head Pointer Register is incremented, any PCI transaction that attempts to 5020 ** access the Outbound Free Queue Port is signalled a retry. 5021 ** The Intel XScale core may read messages from the Outbound Free Queue by reading the data 5022 ** from the local memory address in the Outbound Free Tail Pointer Register. The processor must 5023 ** then increment the Outbound Free Tail Pointer Register. When the Outbound Free Queue is full, 5024 ** the hardware must retry any PCI writes until a slot in the queue becomes available. 5025 ** 5026 ** ================================================================================== 5027 ** Circular Queue Summary 5028 ** ---------------------- 5029 ** ________________________________________________________________________________________________________________________________________________ 5030 ** | Queue Name | PCI Port |Generate PCI Interrupt |Generate Intel Xscale Core Interrupt|Head Pointer maintained by|Tail Pointer maintained by| 5031 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 5032 ** |Inbound Post | Inbound Queue | | | | | 5033 ** | Queue | Port | NO | Yes, when queue is written | MU hardware | Intel XScale | 5034 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 5035 ** |Inbound Free | Inbound Queue | | | | | 5036 ** | Queue | Port | NO | NO | Intel XScale | MU hardware | 5037 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 5038 ** ================================================================================== 5039 ** Circular Queue Status Summary 5040 ** ---------------------- 5041 ** ____________________________________________________________________________________________________ 5042 ** | Queue Name | Queue Status | Head & Tail Pointer | Last Pointer Update | 5043 ** |_____________________|________________|_____________________|_______________________________________| 5044 ** | Inbound Post Queue | Empty | Equal | Tail pointer last updated by software | 5045 ** |_____________________|________________|_____________________|_______________________________________| 5046 ** | Inbound Free Queue | Empty | Equal | Head pointer last updated by hardware | 5047 ** |_____________________|________________|_____________________|_______________________________________| 5048 ************************************************************************** 5049 */ 5050 5051 /* 5052 ************************************************************************** 5053 ** Index Registers 5054 ** ======================== 5055 ** . The Index Registers are a set of 1004 registers that when written by an external PCI agent can generate an interrupt to the Intel XScale core. 5056 ** These registers are for inbound messages only. 5057 ** The interrupt is recorded in the Inbound Interrupt Status Register. 5058 ** The storage for the Index Registers is allocated from the 80331 local memory. 5059 ** PCI write accesses to the Index Registers write the data to local memory. 5060 ** PCI read accesses to the Index Registers read the data from local memory. 5061 ** . The local memory used for the Index Registers ranges from Inbound ATU Translate Value Register + 050H 5062 ** to Inbound ATU Translate Value Register + FFFH. 5063 ** . The address of the first write access is stored in the Index Address Register. 5064 ** This register is written during the earliest write access and provides a means to determine which Index Register was written. 5065 ** Once updated by the MU, the Index Address Register is not updated until the Index Register 5066 ** Interrupt bit in the Inbound Interrupt Status Register is cleared. 5067 ** . When the interrupt is cleared, the Index Address Register is re-enabled and stores the address of the next Index Register write access. 5068 ** Writes by the Intel XScale core to the local memory used by the Index Registers 5069 ** does not cause an interrupt and does not update the Index Address Register. 5070 ** . The index registers can be accessed with Multi-DWORD reads and single QWORD aligned writes. 5071 ************************************************************************** 5072 */ 5073 /* 5074 ************************************************************************** 5075 ** Messaging Unit Internal Bus Memory Map 5076 ** ======================================= 5077 ** Internal Bus Address___Register Description (Name)____________________|_PCI Configuration Space Register Number_ 5078 ** FFFF E300H reserved | 5079 ** .. .. | 5080 ** FFFF E30CH reserved | 5081 ** FFFF E310H Inbound Message Register 0 | Available through 5082 ** FFFF E314H Inbound Message Register 1 | ATU Inbound Translation Window 5083 ** FFFF E318H Outbound Message Register 0 | 5084 ** FFFF E31CH Outbound Message Register 1 | or 5085 ** FFFF E320H Inbound Doorbell Register | 5086 ** FFFF E324H Inbound Interrupt Status Register | must translate PCI address to 5087 ** FFFF E328H Inbound Interrupt Mask Register | the Intel Xscale Core 5088 ** FFFF E32CH Outbound Doorbell Register | Memory-Mapped Address 5089 ** FFFF E330H Outbound Interrupt Status Register | 5090 ** FFFF E334H Outbound Interrupt Mask Register | 5091 ** ______________________________________________________________________|________________________________________ 5092 ** FFFF E338H reserved | 5093 ** FFFF E33CH reserved | 5094 ** FFFF E340H reserved | 5095 ** FFFF E344H reserved | 5096 ** FFFF E348H reserved | 5097 ** FFFF E34CH reserved | 5098 ** FFFF E350H MU Configuration Register | 5099 ** FFFF E354H Queue Base Address Register | 5100 ** FFFF E358H reserved | 5101 ** FFFF E35CH reserved | must translate PCI address to 5102 ** FFFF E360H Inbound Free Head Pointer Register | the Intel Xscale Core 5103 ** FFFF E364H Inbound Free Tail Pointer Register | Memory-Mapped Address 5104 ** FFFF E368H Inbound Post Head pointer Register | 5105 ** FFFF E36CH Inbound Post Tail Pointer Register | 5106 ** FFFF E370H Outbound Free Head Pointer Register | 5107 ** FFFF E374H Outbound Free Tail Pointer Register | 5108 ** FFFF E378H Outbound Post Head pointer Register | 5109 ** FFFF E37CH Outbound Post Tail Pointer Register | 5110 ** FFFF E380H Index Address Register | 5111 ** FFFF E384H reserved | 5112 ** .. .. | 5113 ** FFFF E3FCH reserved | 5114 ** ______________________________________________________________________|_______________________________________ 5115 ************************************************************************** 5116 */ 5117 /* 5118 ************************************************************************** 5119 ** MU Configuration Register - MUCR FFFF.E350H 5120 ** 5121 ** . The MU Configuration Register (MUCR) contains the Circular Queue Enable bit and the size of one Circular Queue. 5122 ** . The Circular Queue Enable bit enables or disables the Circular Queues. 5123 ** The Circular Queues are disabled at reset to allow the software to initialize the head 5124 ** and tail pointer registers before any PCI accesses to the Queue Ports. 5125 ** . Each Circular Queue may range from 4 K entries (16 Kbytes) to 64 K entries (256 Kbytes) and there are four Circular Queues. 5126 ** ------------------------------------------------------------------------ 5127 ** Bit Default Description 5128 ** 31:06 000000H 00 2 Reserved 5129 ** 05:01 00001 2 Circular Queue Size - This field determines the size of each Circular Queue. 5130 ** All four queues are the same size. 5131 ** �E 00001 2 - 4K Entries (16 Kbytes) 5132 ** �E 00010 2 - 8K Entries (32 Kbytes) 5133 ** �E 00100 2 - 16K Entries (64 Kbytes) 5134 ** �E 01000 2 - 32K Entries (128 Kbytes) 5135 ** �E 10000 2 - 64K Entries (256 Kbytes) 5136 ** 00 0 2 Circular Queue Enable - This bit enables or disables the Circular Queues. When clear the Circular 5137 ** Queues are disabled, however the MU accepts PCI accesses to the Circular Queue Ports but ignores 5138 ** the data for Writes and return FFFF.FFFFH for Reads. Interrupts are not generated to the core when 5139 ** disabled. When set, the Circular Queues are fully enabled. 5140 ************************************************************************** 5141 */ 5142 #define ARCMSR_MU_CONFIGURATION_REG 0xFFFFE350 5143 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE64K 0x0020 5144 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE32K 0x0010 5145 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE16K 0x0008 5146 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE8K 0x0004 5147 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE4K 0x0002 5148 #define ARCMSR_MU_CIRCULAR_QUEUE_ENABLE 0x0001 /*0:disable 1:enable*/ 5149 /* 5150 ************************************************************************** 5151 ** Queue Base Address Register - QBAR 5152 ** 5153 ** . The Queue Base Address Register (QBAR) contains the local memory address of the Circular Queues. 5154 ** The base address is required to be located on a 1 Mbyte address boundary. 5155 ** . All Circular Queue head and tail pointers are based on the QBAR. 5156 ** When the head and tail pointer registers are read, the Queue Base Address is returned in the upper 12 bits. 5157 ** Writing to the upper 12 bits of the head and tail pointer registers does not affect the Queue Base Address or Queue Base Address Register. 5158 ** Warning: 5159 ** The QBAR must designate a range allocated to the 80331 DDR SDRAM interface 5160 ** ------------------------------------------------------------------------ 5161 ** Bit Default Description 5162 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5163 ** 19:00 00000H Reserved 5164 ************************************************************************** 5165 */ 5166 #define ARCMSR_MU_QUEUE_BASE_ADDRESS_REG 0xFFFFE354 5167 /* 5168 ************************************************************************** 5169 ** Inbound Free Head Pointer Register - IFHPR 5170 ** 5171 ** . The Inbound Free Head Pointer Register (IFHPR) contains the local memory offset from 5172 ** the Queue Base Address of the head pointer for the Inbound Free Queue. 5173 ** The Head Pointer must be aligned on a DWORD address boundary. 5174 ** When read, the Queue Base Address is provided in the upper 12 bits of the register. 5175 ** Writes to the upper 12 bits of the register are ignored. 5176 ** This register is maintained by software. 5177 ** ------------------------------------------------------------------------ 5178 ** Bit Default Description 5179 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5180 ** 19:02 0000H 00 2 Inbound Free Head Pointer - Local memory offset of the head pointer for the Inbound Free Queue. 5181 ** 01:00 00 2 Reserved 5182 ************************************************************************** 5183 */ 5184 #define ARCMSR_MU_INBOUND_FREE_HEAD_PTR_REG 0xFFFFE360 5185 /* 5186 ************************************************************************** 5187 ** Inbound Free Tail Pointer Register - IFTPR 5188 ** 5189 ** . The Inbound Free Tail Pointer Register (IFTPR) contains the local memory offset from the Queue 5190 ** Base Address of the tail pointer for the Inbound Free Queue. The Tail Pointer must be aligned on a 5191 ** DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 5192 ** of the register. Writes to the upper 12 bits of the register are ignored. 5193 ** ------------------------------------------------------------------------ 5194 ** Bit Default Description 5195 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5196 ** 19:02 0000H 00 2 Inbound Free Tail Pointer - Local memory offset of the tail pointer for the Inbound Free Queue. 5197 ** 01:00 00 2 Reserved 5198 ************************************************************************** 5199 */ 5200 #define ARCMSR_MU_INBOUND_FREE_TAIL_PTR_REG 0xFFFFE364 5201 /* 5202 ************************************************************************** 5203 ** Inbound Post Head Pointer Register - IPHPR 5204 ** 5205 ** . The Inbound Post Head Pointer Register (IPHPR) contains the local memory offset from the Queue 5206 ** Base Address of the head pointer for the Inbound Post Queue. The Head Pointer must be aligned on 5207 ** a DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 5208 ** of the register. Writes to the upper 12 bits of the register are ignored. 5209 ** ------------------------------------------------------------------------ 5210 ** Bit Default Description 5211 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5212 ** 19:02 0000H 00 2 Inbound Post Head Pointer - Local memory offset of the head pointer for the Inbound Post Queue. 5213 ** 01:00 00 2 Reserved 5214 ************************************************************************** 5215 */ 5216 #define ARCMSR_MU_INBOUND_POST_HEAD_PTR_REG 0xFFFFE368 5217 /* 5218 ************************************************************************** 5219 ** Inbound Post Tail Pointer Register - IPTPR 5220 ** 5221 ** . The Inbound Post Tail Pointer Register (IPTPR) contains the local memory offset from the Queue 5222 ** Base Address of the tail pointer for the Inbound Post Queue. The Tail Pointer must be aligned on a 5223 ** DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 5224 ** of the register. Writes to the upper 12 bits of the register are ignored. 5225 ** ------------------------------------------------------------------------ 5226 ** Bit Default Description 5227 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5228 ** 19:02 0000H 00 2 Inbound Post Tail Pointer - Local memory offset of the tail pointer for the Inbound Post Queue. 5229 ** 01:00 00 2 Reserved 5230 ************************************************************************** 5231 */ 5232 #define ARCMSR_MU_INBOUND_POST_TAIL_PTR_REG 0xFFFFE36C 5233 /* 5234 ************************************************************************** 5235 ** Index Address Register - IAR 5236 ** 5237 ** . The Index Address Register (IAR) contains the offset of the least recently accessed Index Register. 5238 ** It is written by the MU when the Index Registers are written by a PCI agent. 5239 ** The register is not updated until the Index Interrupt bit in the Inbound Interrupt Status Register is cleared. 5240 ** . The local memory address of the Index Register least recently accessed is computed 5241 ** by adding the Index Address Register to the Inbound ATU Translate Value Register. 5242 ** ------------------------------------------------------------------------ 5243 ** Bit Default Description 5244 ** 31:12 000000H Reserved 5245 ** 11:02 00H 00 2 Index Address - is the local memory offset of the Index Register written (050H to FFCH) 5246 ** 01:00 00 2 Reserved 5247 ************************************************************************** 5248 */ 5249 #define ARCMSR_MU_LOCAL_MEMORY_INDEX_REG 0xFFFFE380 /*1004 dwords 0x0050....0x0FFC, 4016 bytes 0x0050...0x0FFF*/ 5250 /* 5251 ********************************************************************************************************** 5252 ** RS-232 Interface for Areca Raid Controller 5253 ** The low level command interface is exclusive with VT100 terminal 5254 ** -------------------------------------------------------------------- 5255 ** 1. Sequence of command execution 5256 ** -------------------------------------------------------------------- 5257 ** (A) Header : 3 bytes sequence (0x5E, 0x01, 0x61) 5258 ** (B) Command block : variable length of data including length, command code, data and checksum byte 5259 ** (C) Return data : variable length of data 5260 ** -------------------------------------------------------------------- 5261 ** 2. Command block 5262 ** -------------------------------------------------------------------- 5263 ** (A) 1st byte : command block length (low byte) 5264 ** (B) 2nd byte : command block length (high byte) 5265 ** note ..command block length shouldn't > 2040 bytes, length excludes these two bytes 5266 ** (C) 3rd byte : command code 5267 ** (D) 4th and following bytes : variable length data bytes depends on command code 5268 ** (E) last byte : checksum byte (sum of 1st byte until last data byte) 5269 ** -------------------------------------------------------------------- 5270 ** 3. Command code and associated data 5271 ** -------------------------------------------------------------------- 5272 ** The following are command code defined in raid controller Command code 0x10--0x1? are used for system level management, 5273 ** no password checking is needed and should be implemented in separate well controlled utility and not for end user access. 5274 ** Command code 0x20--0x?? always check the password, password must be entered to enable these command. 5275 ** enum 5276 ** { 5277 ** GUI_SET_SERIAL=0x10, 5278 ** GUI_SET_VENDOR, 5279 ** GUI_SET_MODEL, 5280 ** GUI_IDENTIFY, 5281 ** GUI_CHECK_PASSWORD, 5282 ** GUI_LOGOUT, 5283 ** GUI_HTTP, 5284 ** GUI_SET_ETHERNET_ADDR, 5285 ** GUI_SET_LOGO, 5286 ** GUI_POLL_EVENT, 5287 ** GUI_GET_EVENT, 5288 ** GUI_GET_HW_MONITOR, 5289 ** 5290 ** // GUI_QUICK_CREATE=0x20, (function removed) 5291 ** GUI_GET_INFO_R=0x20, 5292 ** GUI_GET_INFO_V, 5293 ** GUI_GET_INFO_P, 5294 ** GUI_GET_INFO_S, 5295 ** GUI_CLEAR_EVENT, 5296 ** 5297 ** GUI_MUTE_BEEPER=0x30, 5298 ** GUI_BEEPER_SETTING, 5299 ** GUI_SET_PASSWORD, 5300 ** GUI_HOST_INTERFACE_MODE, 5301 ** GUI_REBUILD_PRIORITY, 5302 ** GUI_MAX_ATA_MODE, 5303 ** GUI_RESET_CONTROLLER, 5304 ** GUI_COM_PORT_SETTING, 5305 ** GUI_NO_OPERATION, 5306 ** GUI_DHCP_IP, 5307 ** 5308 ** GUI_CREATE_PASS_THROUGH=0x40, 5309 ** GUI_MODIFY_PASS_THROUGH, 5310 ** GUI_DELETE_PASS_THROUGH, 5311 ** GUI_IDENTIFY_DEVICE, 5312 ** 5313 ** GUI_CREATE_RAIDSET=0x50, 5314 ** GUI_DELETE_RAIDSET, 5315 ** GUI_EXPAND_RAIDSET, 5316 ** GUI_ACTIVATE_RAIDSET, 5317 ** GUI_CREATE_HOT_SPARE, 5318 ** GUI_DELETE_HOT_SPARE, 5319 ** 5320 ** GUI_CREATE_VOLUME=0x60, 5321 ** GUI_MODIFY_VOLUME, 5322 ** GUI_DELETE_VOLUME, 5323 ** GUI_START_CHECK_VOLUME, 5324 ** GUI_STOP_CHECK_VOLUME 5325 ** }; 5326 ** 5327 ** Command description : 5328 ** 5329 ** GUI_SET_SERIAL : Set the controller serial# 5330 ** byte 0,1 : length 5331 ** byte 2 : command code 0x10 5332 ** byte 3 : password length (should be 0x0f) 5333 ** byte 4-0x13 : should be "ArEcATecHnoLogY" 5334 ** byte 0x14--0x23 : Serial number string (must be 16 bytes) 5335 ** GUI_SET_VENDOR : Set vendor string for the controller 5336 ** byte 0,1 : length 5337 ** byte 2 : command code 0x11 5338 ** byte 3 : password length (should be 0x08) 5339 ** byte 4-0x13 : should be "ArEcAvAr" 5340 ** byte 0x14--0x3B : vendor string (must be 40 bytes) 5341 ** GUI_SET_MODEL : Set the model name of the controller 5342 ** byte 0,1 : length 5343 ** byte 2 : command code 0x12 5344 ** byte 3 : password length (should be 0x08) 5345 ** byte 4-0x13 : should be "ArEcAvAr" 5346 ** byte 0x14--0x1B : model string (must be 8 bytes) 5347 ** GUI_IDENTIFY : Identify device 5348 ** byte 0,1 : length 5349 ** byte 2 : command code 0x13 5350 ** return "Areca RAID Subsystem " 5351 ** GUI_CHECK_PASSWORD : Verify password 5352 ** byte 0,1 : length 5353 ** byte 2 : command code 0x14 5354 ** byte 3 : password length 5355 ** byte 4-0x?? : user password to be checked 5356 ** GUI_LOGOUT : Logout GUI (force password checking on next command) 5357 ** byte 0,1 : length 5358 ** byte 2 : command code 0x15 5359 ** GUI_HTTP : HTTP interface (reserved for Http proxy service)(0x16) 5360 ** 5361 ** GUI_SET_ETHERNET_ADDR : Set the ethernet MAC address 5362 ** byte 0,1 : length 5363 ** byte 2 : command code 0x17 5364 ** byte 3 : password length (should be 0x08) 5365 ** byte 4-0x13 : should be "ArEcAvAr" 5366 ** byte 0x14--0x19 : Ethernet MAC address (must be 6 bytes) 5367 ** GUI_SET_LOGO : Set logo in HTTP 5368 ** byte 0,1 : length 5369 ** byte 2 : command code 0x18 5370 ** byte 3 : Page# (0/1/2/3) (0xff --> clear OEM logo) 5371 ** byte 4/5/6/7 : 0x55/0xaa/0xa5/0x5a 5372 ** byte 8 : TITLE.JPG data (each page must be 2000 bytes) 5373 ** note .... page0 1st 2 byte must be actual length of the JPG file 5374 ** GUI_POLL_EVENT : Poll If Event Log Changed 5375 ** byte 0,1 : length 5376 ** byte 2 : command code 0x19 5377 ** GUI_GET_EVENT : Read Event 5378 ** byte 0,1 : length 5379 ** byte 2 : command code 0x1a 5380 ** byte 3 : Event Page (0:1st page/1/2/3:last page) 5381 ** GUI_GET_HW_MONITOR : Get HW monitor data 5382 ** byte 0,1 : length 5383 ** byte 2 : command code 0x1b 5384 ** byte 3 : # of FANs(example 2) 5385 ** byte 4 : # of Voltage sensor(example 3) 5386 ** byte 5 : # of temperature sensor(example 2) 5387 ** byte 6 : # of power 5388 ** byte 7/8 : Fan#0 (RPM) 5389 ** byte 9/10 : Fan#1 5390 ** byte 11/12 : Voltage#0 original value in *1000 5391 ** byte 13/14 : Voltage#0 value 5392 ** byte 15/16 : Voltage#1 org 5393 ** byte 17/18 : Voltage#1 5394 ** byte 19/20 : Voltage#2 org 5395 ** byte 21/22 : Voltage#2 5396 ** byte 23 : Temp#0 5397 ** byte 24 : Temp#1 5398 ** byte 25 : Power indicator (bit0 : power#0, bit1 : power#1) 5399 ** byte 26 : UPS indicator 5400 ** GUI_QUICK_CREATE : Quick create raid/volume set 5401 ** byte 0,1 : length 5402 ** byte 2 : command code 0x20 5403 ** byte 3/4/5/6 : raw capacity 5404 ** byte 7 : raid level 5405 ** byte 8 : stripe size 5406 ** byte 9 : spare 5407 ** byte 10/11/12/13: device mask (the devices to create raid/volume) 5408 ** This function is removed, application like to implement quick create function 5409 ** need to use GUI_CREATE_RAIDSET and GUI_CREATE_VOLUMESET function. 5410 ** GUI_GET_INFO_R : Get Raid Set Information 5411 ** byte 0,1 : length 5412 ** byte 2 : command code 0x20 5413 ** byte 3 : raidset# 5414 ** 5415 ** typedef struct sGUI_RAIDSET 5416 ** { 5417 ** BYTE grsRaidSetName[16]; 5418 ** DWORD grsCapacity; 5419 ** DWORD grsCapacityX; 5420 ** DWORD grsFailMask; 5421 ** BYTE grsDevArray[32]; 5422 ** BYTE grsMemberDevices; 5423 ** BYTE grsNewMemberDevices; 5424 ** BYTE grsRaidState; 5425 ** BYTE grsVolumes; 5426 ** BYTE grsVolumeList[16]; 5427 ** BYTE grsRes1; 5428 ** BYTE grsRes2; 5429 ** BYTE grsRes3; 5430 ** BYTE grsFreeSegments; 5431 ** DWORD grsRawStripes[8]; 5432 ** DWORD grsRes4; 5433 ** DWORD grsRes5; // Total to 128 bytes 5434 ** DWORD grsRes6; // Total to 128 bytes 5435 ** } sGUI_RAIDSET, *pGUI_RAIDSET; 5436 ** GUI_GET_INFO_V : Get Volume Set Information 5437 ** byte 0,1 : length 5438 ** byte 2 : command code 0x21 5439 ** byte 3 : volumeset# 5440 ** 5441 ** typedef struct sGUI_VOLUMESET 5442 ** { 5443 ** BYTE gvsVolumeName[16]; // 16 5444 ** DWORD gvsCapacity; 5445 ** DWORD gvsCapacityX; 5446 ** DWORD gvsFailMask; 5447 ** DWORD gvsStripeSize; 5448 ** DWORD gvsNewFailMask; 5449 ** DWORD gvsNewStripeSize; 5450 ** DWORD gvsVolumeStatus; 5451 ** DWORD gvsProgress; // 32 5452 ** sSCSI_ATTR gvsScsi; 5453 ** BYTE gvsMemberDisks; 5454 ** BYTE gvsRaidLevel; // 8 5455 ** 5456 ** BYTE gvsNewMemberDisks; 5457 ** BYTE gvsNewRaidLevel; 5458 ** BYTE gvsRaidSetNumber; 5459 ** BYTE gvsRes0; // 4 5460 ** BYTE gvsRes1[4]; // 64 bytes 5461 ** } sGUI_VOLUMESET, *pGUI_VOLUMESET; 5462 ** 5463 ** GUI_GET_INFO_P : Get Physical Drive Information 5464 ** byte 0,1 : length 5465 ** byte 2 : command code 0x22 5466 ** byte 3 : drive # (from 0 to max-channels - 1) 5467 ** 5468 ** typedef struct sGUI_PHY_DRV 5469 ** { 5470 ** BYTE gpdModelName[40]; 5471 ** BYTE gpdSerialNumber[20]; 5472 ** BYTE gpdFirmRev[8]; 5473 ** DWORD gpdCapacity; 5474 ** DWORD gpdCapacityX; // Reserved for expansion 5475 ** BYTE gpdDeviceState; 5476 ** BYTE gpdPioMode; 5477 ** BYTE gpdCurrentUdmaMode; 5478 ** BYTE gpdUdmaMode; 5479 ** BYTE gpdDriveSelect; 5480 ** BYTE gpdRaidNumber; // 0xff if not belongs to a raid set 5481 ** sSCSI_ATTR gpdScsi; 5482 ** BYTE gpdReserved[40]; // Total to 128 bytes 5483 ** } sGUI_PHY_DRV, *pGUI_PHY_DRV; 5484 ** 5485 ** GUI_GET_INFO_S : Get System Information 5486 ** byte 0,1 : length 5487 ** byte 2 : command code 0x23 5488 ** 5489 ** typedef struct sCOM_ATTR 5490 ** { 5491 ** BYTE comBaudRate; 5492 ** BYTE comDataBits; 5493 ** BYTE comStopBits; 5494 ** BYTE comParity; 5495 ** BYTE comFlowControl; 5496 ** } sCOM_ATTR, *pCOM_ATTR; 5497 ** 5498 ** typedef struct sSYSTEM_INFO 5499 ** { 5500 ** BYTE gsiVendorName[40]; 5501 ** BYTE gsiSerialNumber[16]; 5502 ** BYTE gsiFirmVersion[16]; 5503 ** BYTE gsiBootVersion[16]; 5504 ** BYTE gsiMbVersion[16]; 5505 ** BYTE gsiModelName[8]; 5506 ** BYTE gsiLocalIp[4]; 5507 ** BYTE gsiCurrentIp[4]; 5508 ** DWORD gsiTimeTick; 5509 ** DWORD gsiCpuSpeed; 5510 ** DWORD gsiICache; 5511 ** DWORD gsiDCache; 5512 ** DWORD gsiScache; 5513 ** DWORD gsiMemorySize; 5514 ** DWORD gsiMemorySpeed; 5515 ** DWORD gsiEvents; 5516 ** BYTE gsiMacAddress[6]; 5517 ** BYTE gsiDhcp; 5518 ** BYTE gsiBeeper; 5519 ** BYTE gsiChannelUsage; 5520 ** BYTE gsiMaxAtaMode; 5521 ** BYTE gsiSdramEcc; // 1:if ECC enabled 5522 ** BYTE gsiRebuildPriority; 5523 ** sCOM_ATTR gsiComA; // 5 bytes 5524 ** sCOM_ATTR gsiComB; // 5 bytes 5525 ** BYTE gsiIdeChannels; 5526 ** BYTE gsiScsiHostChannels; 5527 ** BYTE gsiIdeHostChannels; 5528 ** BYTE gsiMaxVolumeSet; 5529 ** BYTE gsiMaxRaidSet; 5530 ** BYTE gsiEtherPort; // 1:if ether net port supported 5531 ** BYTE gsiRaid6Engine; // 1:Raid6 engine supported 5532 ** BYTE gsiRes[75]; 5533 ** } sSYSTEM_INFO, *pSYSTEM_INFO; 5534 ** 5535 ** GUI_CLEAR_EVENT : Clear System Event 5536 ** byte 0,1 : length 5537 ** byte 2 : command code 0x24 5538 ** 5539 ** GUI_MUTE_BEEPER : Mute current beeper 5540 ** byte 0,1 : length 5541 ** byte 2 : command code 0x30 5542 ** 5543 ** GUI_BEEPER_SETTING : Disable beeper 5544 ** byte 0,1 : length 5545 ** byte 2 : command code 0x31 5546 ** byte 3 : 0->disable, 1->enable 5547 ** 5548 ** GUI_SET_PASSWORD : Change password 5549 ** byte 0,1 : length 5550 ** byte 2 : command code 0x32 5551 ** byte 3 : pass word length ( must <= 15 ) 5552 ** byte 4 : password (must be alpha-numerical) 5553 ** 5554 ** GUI_HOST_INTERFACE_MODE : Set host interface mode 5555 ** byte 0,1 : length 5556 ** byte 2 : command code 0x33 5557 ** byte 3 : 0->Independent, 1->cluster 5558 ** 5559 ** GUI_REBUILD_PRIORITY : Set rebuild priority 5560 ** byte 0,1 : length 5561 ** byte 2 : command code 0x34 5562 ** byte 3 : 0/1/2/3 (low->high) 5563 ** 5564 ** GUI_MAX_ATA_MODE : Set maximum ATA mode to be used 5565 ** byte 0,1 : length 5566 ** byte 2 : command code 0x35 5567 ** byte 3 : 0/1/2/3 (133/100/66/33) 5568 ** 5569 ** GUI_RESET_CONTROLLER : Reset Controller 5570 ** byte 0,1 : length 5571 ** byte 2 : command code 0x36 5572 ** *Response with VT100 screen (discard it) 5573 ** 5574 ** GUI_COM_PORT_SETTING : COM port setting 5575 ** byte 0,1 : length 5576 ** byte 2 : command code 0x37 5577 ** byte 3 : 0->COMA (term port), 1->COMB (debug port) 5578 ** byte 4 : 0/1/2/3/4/5/6/7 (1200/2400/4800/9600/19200/38400/57600/115200) 5579 ** byte 5 : data bit (0:7 bit, 1:8 bit : must be 8 bit) 5580 ** byte 6 : stop bit (0:1, 1:2 stop bits) 5581 ** byte 7 : parity (0:none, 1:off, 2:even) 5582 ** byte 8 : flow control (0:none, 1:xon/xoff, 2:hardware => must use none) 5583 ** 5584 ** GUI_NO_OPERATION : No operation 5585 ** byte 0,1 : length 5586 ** byte 2 : command code 0x38 5587 ** 5588 ** GUI_DHCP_IP : Set DHCP option and local IP address 5589 ** byte 0,1 : length 5590 ** byte 2 : command code 0x39 5591 ** byte 3 : 0:dhcp disabled, 1:dhcp enabled 5592 ** byte 4/5/6/7 : IP address 5593 ** 5594 ** GUI_CREATE_PASS_THROUGH : Create pass through disk 5595 ** byte 0,1 : length 5596 ** byte 2 : command code 0x40 5597 ** byte 3 : device # 5598 ** byte 4 : scsi channel (0/1) 5599 ** byte 5 : scsi id (0-->15) 5600 ** byte 6 : scsi lun (0-->7) 5601 ** byte 7 : tagged queue (1 : enabled) 5602 ** byte 8 : cache mode (1 : enabled) 5603 ** byte 9 : max speed (0/1/2/3/4, async/20/40/80/160 for scsi) 5604 ** (0/1/2/3/4, 33/66/100/133/150 for ide ) 5605 ** 5606 ** GUI_MODIFY_PASS_THROUGH : Modify pass through disk 5607 ** byte 0,1 : length 5608 ** byte 2 : command code 0x41 5609 ** byte 3 : device # 5610 ** byte 4 : scsi channel (0/1) 5611 ** byte 5 : scsi id (0-->15) 5612 ** byte 6 : scsi lun (0-->7) 5613 ** byte 7 : tagged queue (1 : enabled) 5614 ** byte 8 : cache mode (1 : enabled) 5615 ** byte 9 : max speed (0/1/2/3/4, async/20/40/80/160 for scsi) 5616 ** (0/1/2/3/4, 33/66/100/133/150 for ide ) 5617 ** 5618 ** GUI_DELETE_PASS_THROUGH : Delete pass through disk 5619 ** byte 0,1 : length 5620 ** byte 2 : command code 0x42 5621 ** byte 3 : device# to be deleted 5622 ** 5623 ** GUI_IDENTIFY_DEVICE : Identify Device 5624 ** byte 0,1 : length 5625 ** byte 2 : command code 0x43 5626 ** byte 3 : Flash Method(0:flash selected, 1:flash not selected) 5627 ** byte 4/5/6/7 : IDE device mask to be flashed 5628 ** note .... no response data available 5629 ** 5630 ** GUI_CREATE_RAIDSET : Create Raid Set 5631 ** byte 0,1 : length 5632 ** byte 2 : command code 0x50 5633 ** byte 3/4/5/6 : device mask 5634 ** byte 7-22 : raidset name (if byte 7 == 0:use default) 5635 ** 5636 ** GUI_DELETE_RAIDSET : Delete Raid Set 5637 ** byte 0,1 : length 5638 ** byte 2 : command code 0x51 5639 ** byte 3 : raidset# 5640 ** 5641 ** GUI_EXPAND_RAIDSET : Expand Raid Set 5642 ** byte 0,1 : length 5643 ** byte 2 : command code 0x52 5644 ** byte 3 : raidset# 5645 ** byte 4/5/6/7 : device mask for expansion 5646 ** byte 8/9/10 : (8:0 no change, 1 change, 0xff:terminate, 9:new raid level,10:new stripe size 0/1/2/3/4/5->4/8/16/32/64/128K ) 5647 ** byte 11/12/13 : repeat for each volume in the raidset .... 5648 ** 5649 ** GUI_ACTIVATE_RAIDSET : Activate incomplete raid set 5650 ** byte 0,1 : length 5651 ** byte 2 : command code 0x53 5652 ** byte 3 : raidset# 5653 ** 5654 ** GUI_CREATE_HOT_SPARE : Create hot spare disk 5655 ** byte 0,1 : length 5656 ** byte 2 : command code 0x54 5657 ** byte 3/4/5/6 : device mask for hot spare creation 5658 ** 5659 ** GUI_DELETE_HOT_SPARE : Delete hot spare disk 5660 ** byte 0,1 : length 5661 ** byte 2 : command code 0x55 5662 ** byte 3/4/5/6 : device mask for hot spare deletion 5663 ** 5664 ** GUI_CREATE_VOLUME : Create volume set 5665 ** byte 0,1 : length 5666 ** byte 2 : command code 0x60 5667 ** byte 3 : raidset# 5668 ** byte 4-19 : volume set name (if byte4 == 0, use default) 5669 ** byte 20-27 : volume capacity (blocks) 5670 ** byte 28 : raid level 5671 ** byte 29 : stripe size (0/1/2/3/4/5->4/8/16/32/64/128K) 5672 ** byte 30 : channel 5673 ** byte 31 : ID 5674 ** byte 32 : LUN 5675 ** byte 33 : 1 enable tag 5676 ** byte 34 : 1 enable cache 5677 ** byte 35 : speed (0/1/2/3/4->async/20/40/80/160 for scsi) 5678 ** (0/1/2/3/4->33/66/100/133/150 for IDE ) 5679 ** byte 36 : 1 to select quick init 5680 ** 5681 ** GUI_MODIFY_VOLUME : Modify volume Set 5682 ** byte 0,1 : length 5683 ** byte 2 : command code 0x61 5684 ** byte 3 : volumeset# 5685 ** byte 4-19 : new volume set name (if byte4 == 0, not change) 5686 ** byte 20-27 : new volume capacity (reserved) 5687 ** byte 28 : new raid level 5688 ** byte 29 : new stripe size (0/1/2/3/4/5->4/8/16/32/64/128K) 5689 ** byte 30 : new channel 5690 ** byte 31 : new ID 5691 ** byte 32 : new LUN 5692 ** byte 33 : 1 enable tag 5693 ** byte 34 : 1 enable cache 5694 ** byte 35 : speed (0/1/2/3/4->async/20/40/80/160 for scsi) 5695 ** (0/1/2/3/4->33/66/100/133/150 for IDE ) 5696 ** 5697 ** GUI_DELETE_VOLUME : Delete volume set 5698 ** byte 0,1 : length 5699 ** byte 2 : command code 0x62 5700 ** byte 3 : volumeset# 5701 ** 5702 ** GUI_START_CHECK_VOLUME : Start volume consistency check 5703 ** byte 0,1 : length 5704 ** byte 2 : command code 0x63 5705 ** byte 3 : volumeset# 5706 ** 5707 ** GUI_STOP_CHECK_VOLUME : Stop volume consistency check 5708 ** byte 0,1 : length 5709 ** byte 2 : command code 0x64 5710 ** --------------------------------------------------------------------- 5711 ** 4. Returned data 5712 ** --------------------------------------------------------------------- 5713 ** (A) Header : 3 bytes sequence (0x5E, 0x01, 0x61) 5714 ** (B) Length : 2 bytes (low byte 1st, excludes length and checksum byte) 5715 ** (C) status or data : 5716 ** <1> If length == 1 ==> 1 byte status code 5717 ** #define GUI_OK 0x41 5718 ** #define GUI_RAIDSET_NOT_NORMAL 0x42 5719 ** #define GUI_VOLUMESET_NOT_NORMAL 0x43 5720 ** #define GUI_NO_RAIDSET 0x44 5721 ** #define GUI_NO_VOLUMESET 0x45 5722 ** #define GUI_NO_PHYSICAL_DRIVE 0x46 5723 ** #define GUI_PARAMETER_ERROR 0x47 5724 ** #define GUI_UNSUPPORTED_COMMAND 0x48 5725 ** #define GUI_DISK_CONFIG_CHANGED 0x49 5726 ** #define GUI_INVALID_PASSWORD 0x4a 5727 ** #define GUI_NO_DISK_SPACE 0x4b 5728 ** #define GUI_CHECKSUM_ERROR 0x4c 5729 ** #define GUI_PASSWORD_REQUIRED 0x4d 5730 ** <2> If length > 1 ==> data block returned from controller and the contents depends on the command code 5731 ** (E) Checksum : checksum of length and status or data byte 5732 ************************************************************************** 5733 */ 5734