1 /* 2 ******************************************************************************** 3 ** OS : FreeBSD 4 ** FILE NAME : arcmsr.h 5 ** BY : Erich Chen, Ching Huang 6 ** Description: SCSI RAID Device Driver for 7 ** ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x) 8 ** SATA/SAS RAID HOST Adapter 9 ******************************************************************************** 10 ******************************************************************************** 11 ** SPDX-License-Identifier: BSD-3-Clause 12 ** 13 ** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved. 14 ** 15 ** Redistribution and use in source and binary forms,with or without 16 ** modification,are permitted provided that the following conditions 17 ** are met: 18 ** 1. Redistributions of source code must retain the above copyright 19 ** notice,this list of conditions and the following disclaimer. 20 ** 2. Redistributions in binary form must reproduce the above copyright 21 ** notice,this list of conditions and the following disclaimer in the 22 ** documentation and/or other materials provided with the distribution. 23 ** 3. The name of the author may not be used to endorse or promote products 24 ** derived from this software without specific prior written permission. 25 ** 26 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 27 ** IMPLIED WARRANTIES,INCLUDING,BUT NOT LIMITED TO,THE IMPLIED WARRANTIES 28 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,INDIRECT, 30 ** INCIDENTAL,SPECIAL,EXEMPLARY,OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT 31 ** NOT LIMITED TO,PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 ** DATA,OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 33 ** THEORY OF LIABILITY,WHETHER IN CONTRACT,STRICT LIABILITY,OR TORT 34 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 35 ** THIS SOFTWARE,EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 ************************************************************************** 37 */ 38 #define ARCMSR_SCSI_INITIATOR_ID 255 39 #define ARCMSR_DEV_SECTOR_SIZE 512 40 #define ARCMSR_MAX_XFER_SECTORS 4096 41 #define ARCMSR_MAX_TARGETID 17 /*16 max target id + 1*/ 42 #define ARCMSR_MAX_TARGETLUN 8 /*8*/ 43 #define ARCMSR_MAX_CHIPTYPE_NUM 4 44 #define ARCMSR_MAX_OUTSTANDING_CMD 256 45 #define ARCMSR_MAX_START_JOB 256 46 #define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_OUTSTANDING_CMD 47 #define ARCMSR_MAX_FREESRB_NUM 384 48 #define ARCMSR_MAX_QBUFFER 4096 /* ioctl QBUFFER */ 49 #define ARCMSR_MAX_SG_ENTRIES 38 /* max 38*/ 50 #define ARCMSR_MAX_ADAPTER 4 51 #define ARCMSR_RELEASE_SIMQ_LEVEL 230 52 #define ARCMSR_MAX_HBB_POSTQUEUE 264 /* (ARCMSR_MAX_OUTSTANDING_CMD+8) */ 53 #define ARCMSR_MAX_HBD_POSTQUEUE 256 54 #define ARCMSR_TIMEOUT_DELAY 60 /* in sec */ 55 #define ARCMSR_NUM_MSIX_VECTORS 4 56 /* 57 ********************************************************************* 58 */ 59 #ifndef TRUE 60 #define TRUE 1 61 #endif 62 #ifndef FALSE 63 #define FALSE 0 64 #endif 65 #ifndef INTR_ENTROPY 66 # define INTR_ENTROPY 0 67 #endif 68 69 #ifndef offsetof 70 #define offsetof(type, member) ((size_t)(&((type *)0)->member)) 71 #endif 72 73 #define ARCMSR_LOCK_INIT(l, s) mtx_init(l, s, NULL, MTX_DEF) 74 #define ARCMSR_LOCK_DESTROY(l) mtx_destroy(l) 75 #define ARCMSR_LOCK_ACQUIRE(l) mtx_lock(l) 76 #define ARCMSR_LOCK_RELEASE(l) mtx_unlock(l) 77 #define ARCMSR_LOCK_TRY(l) mtx_trylock(l) 78 #define arcmsr_htole32(x) htole32(x) 79 typedef struct mtx arcmsr_lock_t; 80 81 /* 82 ********************************************************************************** 83 ** 84 ********************************************************************************** 85 */ 86 #define PCI_VENDOR_ID_ARECA 0x17D3 /* Vendor ID */ 87 #define PCI_DEVICE_ID_ARECA_1110 0x1110 /* Device ID */ 88 #define PCI_DEVICE_ID_ARECA_1120 0x1120 /* Device ID */ 89 #define PCI_DEVICE_ID_ARECA_1130 0x1130 /* Device ID */ 90 #define PCI_DEVICE_ID_ARECA_1160 0x1160 /* Device ID */ 91 #define PCI_DEVICE_ID_ARECA_1170 0x1170 /* Device ID */ 92 #define PCI_DEVICE_ID_ARECA_1200 0x1200 /* Device ID */ 93 #define PCI_DEVICE_ID_ARECA_1201 0x1201 /* Device ID */ 94 #define PCI_DEVICE_ID_ARECA_1203 0x1203 /* Device ID */ 95 #define PCI_DEVICE_ID_ARECA_1210 0x1210 /* Device ID */ 96 #define PCI_DEVICE_ID_ARECA_1212 0x1212 /* Device ID */ 97 #define PCI_DEVICE_ID_ARECA_1214 0x1214 /* Device ID */ 98 #define PCI_DEVICE_ID_ARECA_1220 0x1220 /* Device ID */ 99 #define PCI_DEVICE_ID_ARECA_1222 0x1222 /* Device ID */ 100 #define PCI_DEVICE_ID_ARECA_1230 0x1230 /* Device ID */ 101 #define PCI_DEVICE_ID_ARECA_1231 0x1231 /* Device ID */ 102 #define PCI_DEVICE_ID_ARECA_1260 0x1260 /* Device ID */ 103 #define PCI_DEVICE_ID_ARECA_1261 0x1261 /* Device ID */ 104 #define PCI_DEVICE_ID_ARECA_1270 0x1270 /* Device ID */ 105 #define PCI_DEVICE_ID_ARECA_1280 0x1280 /* Device ID */ 106 #define PCI_DEVICE_ID_ARECA_1380 0x1380 /* Device ID */ 107 #define PCI_DEVICE_ID_ARECA_1381 0x1381 /* Device ID */ 108 #define PCI_DEVICE_ID_ARECA_1680 0x1680 /* Device ID */ 109 #define PCI_DEVICE_ID_ARECA_1681 0x1681 /* Device ID */ 110 #define PCI_DEVICE_ID_ARECA_1880 0x1880 /* Device ID */ 111 #define PCI_DEVICE_ID_ARECA_1884 0x1884 /* Device ID */ 112 113 #define ARECA_SUB_DEV_ID_1880 0x1880 /* Subsystem Device ID */ 114 #define ARECA_SUB_DEV_ID_1882 0x1882 /* Subsystem Device ID */ 115 #define ARECA_SUB_DEV_ID_1883 0x1883 /* Subsystem Device ID */ 116 #define ARECA_SUB_DEV_ID_1884 0x1884 /* Subsystem Device ID */ 117 #define ARECA_SUB_DEV_ID_1212 0x1212 /* Subsystem Device ID */ 118 #define ARECA_SUB_DEV_ID_1213 0x1213 /* Subsystem Device ID */ 119 #define ARECA_SUB_DEV_ID_1216 0x1216 /* Subsystem Device ID */ 120 #define ARECA_SUB_DEV_ID_1222 0x1222 /* Subsystem Device ID */ 121 #define ARECA_SUB_DEV_ID_1223 0x1223 /* Subsystem Device ID */ 122 #define ARECA_SUB_DEV_ID_1226 0x1226 /* Subsystem Device ID */ 123 124 #define PCIDevVenIDARC1110 0x111017D3 /* Vendor Device ID */ 125 #define PCIDevVenIDARC1120 0x112017D3 /* Vendor Device ID */ 126 #define PCIDevVenIDARC1130 0x113017D3 /* Vendor Device ID */ 127 #define PCIDevVenIDARC1160 0x116017D3 /* Vendor Device ID */ 128 #define PCIDevVenIDARC1170 0x117017D3 /* Vendor Device ID */ 129 #define PCIDevVenIDARC1200 0x120017D3 /* Vendor Device ID */ 130 #define PCIDevVenIDARC1201 0x120117D3 /* Vendor Device ID */ 131 #define PCIDevVenIDARC1203 0x120317D3 /* Vendor Device ID */ 132 #define PCIDevVenIDARC1210 0x121017D3 /* Vendor Device ID */ 133 #define PCIDevVenIDARC1212 0x121217D3 /* Vendor Device ID */ 134 #define PCIDevVenIDARC1213 0x121317D3 /* Vendor Device ID */ 135 #define PCIDevVenIDARC1214 0x121417D3 /* Vendor Device ID */ 136 #define PCIDevVenIDARC1220 0x122017D3 /* Vendor Device ID */ 137 #define PCIDevVenIDARC1222 0x122217D3 /* Vendor Device ID */ 138 #define PCIDevVenIDARC1223 0x122317D3 /* Vendor Device ID */ 139 #define PCIDevVenIDARC1230 0x123017D3 /* Vendor Device ID */ 140 #define PCIDevVenIDARC1231 0x123117D3 /* Vendor Device ID */ 141 #define PCIDevVenIDARC1260 0x126017D3 /* Vendor Device ID */ 142 #define PCIDevVenIDARC1261 0x126117D3 /* Vendor Device ID */ 143 #define PCIDevVenIDARC1270 0x127017D3 /* Vendor Device ID */ 144 #define PCIDevVenIDARC1280 0x128017D3 /* Vendor Device ID */ 145 #define PCIDevVenIDARC1380 0x138017D3 /* Vendor Device ID */ 146 #define PCIDevVenIDARC1381 0x138117D3 /* Vendor Device ID */ 147 #define PCIDevVenIDARC1680 0x168017D3 /* Vendor Device ID */ 148 #define PCIDevVenIDARC1681 0x168117D3 /* Vendor Device ID */ 149 #define PCIDevVenIDARC1880 0x188017D3 /* Vendor Device ID */ 150 #define PCIDevVenIDARC1882 0x188217D3 /* Vendor Device ID */ 151 #define PCIDevVenIDARC1884 0x188417D3 /* Vendor Device ID */ 152 #define PCIDevVenIDARC1886_ 0x188917D3 /* Vendor Device ID */ 153 #define PCIDevVenIDARC1886 0x188A17D3 /* Vendor Device ID */ 154 155 #ifndef PCIR_BARS 156 #define PCIR_BARS 0x10 157 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4) 158 #endif 159 160 #define PCI_BASE_ADDR0 0x10 161 #define PCI_BASE_ADDR1 0x14 162 #define PCI_BASE_ADDR2 0x18 163 #define PCI_BASE_ADDR3 0x1C 164 #define PCI_BASE_ADDR4 0x20 165 #define PCI_BASE_ADDR5 0x24 166 /* 167 ********************************************************************************** 168 ** 169 ********************************************************************************** 170 */ 171 #define ARCMSR_SCSICMD_IOCTL 0x77 172 #define ARCMSR_CDEVSW_IOCTL 0x88 173 #define ARCMSR_MESSAGE_FAIL 0x0001 174 #define ARCMSR_MESSAGE_SUCCESS 0x0000 175 /* 176 ********************************************************************************** 177 ** 178 ********************************************************************************** 179 */ 180 #define arcmsr_ccbsrb_ptr spriv_ptr0 181 #define arcmsr_ccbacb_ptr spriv_ptr1 182 #define dma_addr_hi32(addr) (u_int32_t) ((addr>>16)>>16) 183 #define dma_addr_lo32(addr) (u_int32_t) (addr & 0xffffffff) 184 #define get_min(x,y) ((x) < (y) ? (x) : (y)) 185 #define get_max(x,y) ((x) < (y) ? (y) : (x)) 186 /* 187 ************************************************************************** 188 ************************************************************************** 189 */ 190 #define CHIP_REG_READ32(s, b, r) bus_space_read_4(acb->btag[b], acb->bhandle[b], offsetof(struct s, r)) 191 #define CHIP_REG_WRITE32(s, b, r, d) bus_space_write_4(acb->btag[b], acb->bhandle[b], offsetof(struct s, r), d) 192 #define READ_CHIP_REG32(b, r) bus_space_read_4(acb->btag[b], acb->bhandle[b], r) 193 #define WRITE_CHIP_REG32(b, r, d) bus_space_write_4(acb->btag[b], acb->bhandle[b], r, d) 194 /* 195 ********************************************************************************** 196 ** IOCTL CONTROL Mail Box 197 ********************************************************************************** 198 */ 199 struct CMD_MESSAGE { 200 u_int32_t HeaderLength; 201 u_int8_t Signature[8]; 202 u_int32_t Timeout; 203 u_int32_t ControlCode; 204 u_int32_t ReturnCode; 205 u_int32_t Length; 206 }; 207 208 struct CMD_MESSAGE_FIELD { 209 struct CMD_MESSAGE cmdmessage; /* ioctl header */ 210 u_int8_t messagedatabuffer[1032]; /* areca gui program does not accept more than 1031 byte */ 211 }; 212 213 /************************************************************************/ 214 /************************************************************************/ 215 216 #define ARCMSR_IOP_ERROR_ILLEGALPCI 0x0001 217 #define ARCMSR_IOP_ERROR_VENDORID 0x0002 218 #define ARCMSR_IOP_ERROR_DEVICEID 0x0002 219 #define ARCMSR_IOP_ERROR_ILLEGALCDB 0x0003 220 #define ARCMSR_IOP_ERROR_UNKNOW_CDBERR 0x0004 221 #define ARCMSR_SYS_ERROR_MEMORY_ALLOCATE 0x0005 222 #define ARCMSR_SYS_ERROR_MEMORY_CROSS4G 0x0006 223 #define ARCMSR_SYS_ERROR_MEMORY_LACK 0x0007 224 #define ARCMSR_SYS_ERROR_MEMORY_RANGE 0x0008 225 #define ARCMSR_SYS_ERROR_DEVICE_BASE 0x0009 226 #define ARCMSR_SYS_ERROR_PORT_VALIDATE 0x000A 227 228 /*DeviceType*/ 229 #define ARECA_SATA_RAID 0x90000000 230 231 /*FunctionCode*/ 232 #define FUNCTION_READ_RQBUFFER 0x0801 233 #define FUNCTION_WRITE_WQBUFFER 0x0802 234 #define FUNCTION_CLEAR_RQBUFFER 0x0803 235 #define FUNCTION_CLEAR_WQBUFFER 0x0804 236 #define FUNCTION_CLEAR_ALLQBUFFER 0x0805 237 #define FUNCTION_REQUEST_RETURNCODE_3F 0x0806 238 #define FUNCTION_SAY_HELLO 0x0807 239 #define FUNCTION_SAY_GOODBYE 0x0808 240 #define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809 241 /* 242 ************************************************************************ 243 ** IOCTL CONTROL CODE 244 ************************************************************************ 245 */ 246 /* ARECA IO CONTROL CODE*/ 247 #define ARCMSR_MESSAGE_READ_RQBUFFER _IOWR('F', FUNCTION_READ_RQBUFFER, struct CMD_MESSAGE_FIELD) 248 #define ARCMSR_MESSAGE_WRITE_WQBUFFER _IOWR('F', FUNCTION_WRITE_WQBUFFER, struct CMD_MESSAGE_FIELD) 249 #define ARCMSR_MESSAGE_CLEAR_RQBUFFER _IOWR('F', FUNCTION_CLEAR_RQBUFFER, struct CMD_MESSAGE_FIELD) 250 #define ARCMSR_MESSAGE_CLEAR_WQBUFFER _IOWR('F', FUNCTION_CLEAR_WQBUFFER, struct CMD_MESSAGE_FIELD) 251 #define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER _IOWR('F', FUNCTION_CLEAR_ALLQBUFFER, struct CMD_MESSAGE_FIELD) 252 #define ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F _IOWR('F', FUNCTION_REQUEST_RETURNCODE_3F, struct CMD_MESSAGE_FIELD) 253 #define ARCMSR_MESSAGE_SAY_HELLO _IOWR('F', FUNCTION_SAY_HELLO, struct CMD_MESSAGE_FIELD) 254 #define ARCMSR_MESSAGE_SAY_GOODBYE _IOWR('F', FUNCTION_SAY_GOODBYE, struct CMD_MESSAGE_FIELD) 255 #define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE _IOWR('F', FUNCTION_FLUSH_ADAPTER_CACHE, struct CMD_MESSAGE_FIELD) 256 257 /* ARECA IOCTL ReturnCode */ 258 #define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001 259 #define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006 260 #define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F 261 #define ARCMSR_IOCTL_RETURNCODE_BUS_HANG_ON 0x00000088 262 /* 263 ************************************************************************ 264 ** SPEC. for Areca HBA adapter 265 ************************************************************************ 266 */ 267 /* signature of set and get firmware config */ 268 #define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060 269 #define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063 270 /* message code of inbound message register */ 271 #define ARCMSR_INBOUND_MESG0_NOP 0x00000000 272 #define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001 273 #define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002 274 #define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003 275 #define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004 276 #define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005 277 #define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006 278 #define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007 279 #define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008 280 /* doorbell interrupt generator */ 281 #define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001 282 #define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002 283 #define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001 284 #define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002 285 /* srb areca cdb flag */ 286 #define ARCMSR_SRBPOST_FLAG_SGL_BSIZE 0x80000000 287 #define ARCMSR_SRBPOST_FLAG_IAM_BIOS 0x40000000 288 #define ARCMSR_SRBREPLY_FLAG_IAM_BIOS 0x40000000 289 #define ARCMSR_SRBREPLY_FLAG_ERROR 0x10000000 290 #define ARCMSR_SRBREPLY_FLAG_ERROR_MODE0 0x10000000 291 #define ARCMSR_SRBREPLY_FLAG_ERROR_MODE1 0x00000001 292 /* outbound firmware ok */ 293 #define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000 294 295 #define ARCMSR_ARC1680_BUS_RESET 0x00000003 296 /* 297 ************************************************************************ 298 ** SPEC. for Areca HBB adapter 299 ************************************************************************ 300 */ 301 /* ARECA HBB COMMAND for its FIRMWARE */ 302 #define ARCMSR_DRV2IOP_DOORBELL 0x00020400 /* window of "instruction flags" from driver to iop */ 303 #define ARCMSR_DRV2IOP_DOORBELL_MASK 0x00020404 304 #define ARCMSR_IOP2DRV_DOORBELL 0x00020408 /* window of "instruction flags" from iop to driver */ 305 #define ARCMSR_IOP2DRV_DOORBELL_MASK 0x0002040C 306 307 #define ARCMSR_IOP2DRV_DOORBELL_1203 0x00021870 /* window of "instruction flags" from iop to driver */ 308 #define ARCMSR_IOP2DRV_DOORBELL_MASK_1203 0x00021874 309 #define ARCMSR_DRV2IOP_DOORBELL_1203 0x00021878 /* window of "instruction flags" from driver to iop */ 310 #define ARCMSR_DRV2IOP_DOORBELL_MASK_1203 0x0002187C 311 312 /* ARECA FLAG LANGUAGE */ 313 #define ARCMSR_IOP2DRV_DATA_WRITE_OK 0x00000001 /* ioctl transfer */ 314 #define ARCMSR_IOP2DRV_DATA_READ_OK 0x00000002 /* ioctl transfer */ 315 #define ARCMSR_IOP2DRV_CDB_DONE 0x00000004 316 #define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 317 318 #define ARCMSR_DOORBELL_HANDLE_INT 0x0000000F 319 #define ARCMSR_DOORBELL_INT_CLEAR_PATTERN 0xFF00FFF0 320 #define ARCMSR_MESSAGE_INT_CLEAR_PATTERN 0xFF00FFF7 321 322 #define ARCMSR_MESSAGE_GET_CONFIG 0x00010008 /* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 323 #define ARCMSR_MESSAGE_SET_CONFIG 0x00020008 /* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 324 #define ARCMSR_MESSAGE_ABORT_CMD 0x00030008 /* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 325 #define ARCMSR_MESSAGE_STOP_BGRB 0x00040008 /* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 326 #define ARCMSR_MESSAGE_FLUSH_CACHE 0x00050008 /* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 327 #define ARCMSR_MESSAGE_START_BGRB 0x00060008 /* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 328 #define ARCMSR_MESSAGE_START_DRIVER_MODE 0x000E0008 329 #define ARCMSR_MESSAGE_SET_POST_WINDOW 0x000F0008 330 #define ARCMSR_MESSAGE_ACTIVE_EOI_MODE 0x00100008 331 #define ARCMSR_MESSAGE_FIRMWARE_OK 0x80000000 /* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */ 332 333 #define ARCMSR_DRV2IOP_DATA_WRITE_OK 0x00000001 /* ioctl transfer */ 334 #define ARCMSR_DRV2IOP_DATA_READ_OK 0x00000002 /* ioctl transfer */ 335 #define ARCMSR_DRV2IOP_CDB_POSTED 0x00000004 336 #define ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED 0x00000008 337 #define ARCMSR_DRV2IOP_END_OF_INTERRUPT 0x00000010 /* */ 338 339 /* data tunnel buffer between user space program and its firmware */ 340 #define ARCMSR_MSGCODE_RWBUFFER 0x0000fa00 /* iop msgcode_rwbuffer for message command */ 341 #define ARCMSR_IOCTL_WBUFFER 0x0000fe00 /* user space data to iop 128bytes */ 342 #define ARCMSR_IOCTL_RBUFFER 0x0000ff00 /* iop data to user space 128bytes */ 343 #define ARCMSR_HBB_BASE0_OFFSET 0x00000010 344 #define ARCMSR_HBB_BASE1_OFFSET 0x00000018 345 #define ARCMSR_HBB_BASE0_LEN 0x00021000 346 #define ARCMSR_HBB_BASE1_LEN 0x00010000 347 /* 348 ************************************************************************ 349 ** SPEC. for Areca HBC adapter 350 ************************************************************************ 351 */ 352 #define ARCMSR_HBC_ISR_THROTTLING_LEVEL 12 353 #define ARCMSR_HBC_ISR_MAX_DONE_QUEUE 20 354 /* Host Interrupt Mask */ 355 #define ARCMSR_HBCMU_UTILITY_A_ISR_MASK 0x00000001 /* When clear, the Utility_A interrupt routes to the host.*/ 356 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK 0x00000004 /* When clear, the General Outbound Doorbell interrupt routes to the host.*/ 357 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK 0x00000008 /* When clear, the Outbound Post List FIFO Not Empty interrupt routes to the host.*/ 358 #define ARCMSR_HBCMU_ALL_INTMASKENABLE 0x0000000D /* disable all ISR */ 359 /* Host Interrupt Status */ 360 #define ARCMSR_HBCMU_UTILITY_A_ISR 0x00000001 361 /* 362 ** Set when the Utility_A Interrupt bit is set in the Outbound Doorbell Register. 363 ** It clears by writing a 1 to the Utility_A bit in the Outbound Doorbell Clear Register or through automatic clearing (if enabled). 364 */ 365 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR 0x00000004 366 /* 367 ** Set if Outbound Doorbell register bits 30:1 have a non-zero 368 ** value. This bit clears only when Outbound Doorbell bits 369 ** 30:1 are ALL clear. Only a write to the Outbound Doorbell 370 ** Clear register clears bits in the Outbound Doorbell register. 371 */ 372 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR 0x00000008 373 /* 374 ** Set whenever the Outbound Post List Producer/Consumer 375 ** Register (FIFO) is not empty. It clears when the Outbound 376 ** Post List FIFO is empty. 377 */ 378 #define ARCMSR_HBCMU_SAS_ALL_INT 0x00000010 379 /* 380 ** This bit indicates a SAS interrupt from a source external to 381 ** the PCIe core. This bit is not maskable. 382 */ 383 /* DoorBell*/ 384 #define ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK 0x00000002/**/ 385 #define ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK 0x00000004/**/ 386 #define ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008/*inbound message 0 ready*/ 387 #define ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING 0x00000010/*more than 12 request completed in a time*/ 388 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK 0x00000002/**/ 389 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR 0x00000002/*outbound DATA WRITE isr door bell clear*/ 390 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK 0x00000004/**/ 391 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR 0x00000004/*outbound DATA READ isr door bell clear*/ 392 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008/*outbound message 0 ready*/ 393 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR 0x00000008/*outbound message cmd isr door bell clear*/ 394 #define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK 0x80000000/*ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK*/ 395 #define ARCMSR_HBCMU_RESET_ADAPTER 0x00000024 396 #define ARCMSR_HBCMU_DiagWrite_ENABLE 0x00000080 397 398 /* 399 ************************************************************************ 400 ** SPEC. for Areca HBD adapter 401 ************************************************************************ 402 */ 403 #define ARCMSR_HBDMU_CHIP_ID 0x00004 404 #define ARCMSR_HBDMU_CPU_MEMORY_CONFIGURATION 0x00008 405 #define ARCMSR_HBDMU_I2_HOST_INTERRUPT_MASK 0x00034 406 #define ARCMSR_HBDMU_MAIN_INTERRUPT_STATUS 0x00200 407 #define ARCMSR_HBDMU_PCIE_F0_INTERRUPT_ENABLE 0x0020C 408 #define ARCMSR_HBDMU_INBOUND_MESSAGE0 0x00400 409 #define ARCMSR_HBDMU_INBOUND_MESSAGE1 0x00404 410 #define ARCMSR_HBDMU_OUTBOUND_MESSAGE0 0x00420 411 #define ARCMSR_HBDMU_OUTBOUND_MESSAGE1 0x00424 412 #define ARCMSR_HBDMU_INBOUND_DOORBELL 0x00460 413 #define ARCMSR_HBDMU_OUTBOUND_DOORBELL 0x00480 414 #define ARCMSR_HBDMU_OUTBOUND_DOORBELL_ENABLE 0x00484 415 #define ARCMSR_HBDMU_INBOUND_LIST_BASE_LOW 0x01000 416 #define ARCMSR_HBDMU_INBOUND_LIST_BASE_HIGH 0x01004 417 #define ARCMSR_HBDMU_INBOUND_LIST_WRITE_POINTER 0x01018 418 #define ARCMSR_HBDMU_OUTBOUND_LIST_BASE_LOW 0x01060 419 #define ARCMSR_HBDMU_OUTBOUND_LIST_BASE_HIGH 0x01064 420 #define ARCMSR_HBDMU_OUTBOUND_LIST_COPY_POINTER 0x0106C 421 #define ARCMSR_HBDMU_OUTBOUND_LIST_READ_POINTER 0x01070 422 #define ARCMSR_HBDMU_OUTBOUND_INTERRUPT_CAUSE 0x01088 423 #define ARCMSR_HBDMU_OUTBOUND_INTERRUPT_ENABLE 0x0108C 424 425 #define ARCMSR_HBDMU_MESSAGE_WBUFFER 0x02000 426 #define ARCMSR_HBDMU_MESSAGE_RBUFFER 0x02100 427 #define ARCMSR_HBDMU_MESSAGE_RWBUFFER 0x02200 428 429 #define ARCMSR_HBDMU_ISR_THROTTLING_LEVEL 16 430 #define ARCMSR_HBDMU_ISR_MAX_DONE_QUEUE 20 431 432 /* Host Interrupt Mask */ 433 #define ARCMSR_HBDMU_ALL_INT_ENABLE 0x00001010 /* enable all ISR */ 434 #define ARCMSR_HBDMU_ALL_INT_DISABLE 0x00000000 /* disable all ISR */ 435 436 /* Host Interrupt Status */ 437 #define ARCMSR_HBDMU_OUTBOUND_INT 0x00001010 438 #define ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT 0x00001000 439 #define ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT 0x00000010 440 441 /* DoorBell*/ 442 #define ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY 0x00000001 443 #define ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ 0x00000002 444 445 #define ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK 0x00000001 446 #define ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK 0x00000002 447 448 /*outbound message 0 ready*/ 449 #define ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE 0x02000000 450 451 #define ARCMSR_HBDMU_F0_DOORBELL_CAUSE 0x02000003 452 453 /*outbound message cmd isr door bell clear*/ 454 #define ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR 0x02000000 455 456 /*outbound list */ 457 #define ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT 0x00000001 458 #define ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR 0x00000001 459 460 /*ARCMSR_HBAMU_MESSAGE_FIRMWARE_OK*/ 461 #define ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK 0x80000000 462 /* 463 ******************************************************************************* 464 ** SPEC. for Areca HBE adapter 465 ******************************************************************************* 466 */ 467 #define ARCMSR_SIGNATURE_1884 0x188417D3 468 #define ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR 0x00000001 469 #define ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR 0x00000008 470 #define ARCMSR_HBEMU_ALL_INTMASKENABLE 0x00000009 /* disable all ISR */ 471 472 #define ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK 0x00000002 473 #define ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK 0x00000004 474 #define ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008 /* inbound message 0 ready */ 475 #define ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK 0x00000002 476 #define ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK 0x00000004 477 #define ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 /* outbound message 0 ready */ 478 #define ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK 0x80000000 /* ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK */ 479 /* ARC-1884 doorbell sync */ 480 #define ARCMSR_HBEMU_DOORBELL_SYNC 0x100 481 #define ARCMSR_ARC188X_RESET_ADAPTER 0x00000004 482 /* 483 ******************************************************************************* 484 ** SPEC. for Areca HBF adapter 485 ******************************************************************************* 486 */ 487 #define ARCMSR_SIGNATURE_1886 0x188617D3 488 // Doorbell and interrupt definition are same as Type E adapter 489 /* ARC-1886 doorbell sync */ 490 #define ARCMSR_HBFMU_DOORBELL_SYNC 0x100 491 //set host rw buffer physical address at inbound message 0, 1 (low,high) 492 #define ARCMSR_HBFMU_DOORBELL_SYNC1 0x300 493 #define ARCMSR_HBFMU_MESSAGE_FIRMWARE_OK 0x80000000 494 #define ARCMSR_HBFMU_MESSAGE_NO_VOLUME_CHANGE 0x20000000 495 496 /* 497 ********************************************************************* 498 ** Messaging Unit (MU) of Type A processor 499 ********************************************************************* 500 */ 501 struct HBA_MessageUnit 502 { 503 u_int32_t resrved0[4]; /*0000 000F*/ 504 u_int32_t inbound_msgaddr0; /*0010 0013*/ 505 u_int32_t inbound_msgaddr1; /*0014 0017*/ 506 u_int32_t outbound_msgaddr0; /*0018 001B*/ 507 u_int32_t outbound_msgaddr1; /*001C 001F*/ 508 u_int32_t inbound_doorbell; /*0020 0023*/ 509 u_int32_t inbound_intstatus; /*0024 0027*/ 510 u_int32_t inbound_intmask; /*0028 002B*/ 511 u_int32_t outbound_doorbell; /*002C 002F*/ 512 u_int32_t outbound_intstatus; /*0030 0033*/ 513 u_int32_t outbound_intmask; /*0034 0037*/ 514 u_int32_t reserved1[2]; /*0038 003F*/ 515 u_int32_t inbound_queueport; /*0040 0043*/ 516 u_int32_t outbound_queueport; /*0044 0047*/ 517 u_int32_t reserved2[2]; /*0048 004F*/ 518 u_int32_t reserved3[492]; /*0050 07FF ......local_buffer 492*/ 519 u_int32_t reserved4[128]; /*0800 09FF 128*/ 520 u_int32_t msgcode_rwbuffer[256]; /*0a00 0DFF 256*/ 521 u_int32_t message_wbuffer[32]; /*0E00 0E7F 32*/ 522 u_int32_t reserved5[32]; /*0E80 0EFF 32*/ 523 u_int32_t message_rbuffer[32]; /*0F00 0F7F 32*/ 524 u_int32_t reserved6[32]; /*0F80 0FFF 32*/ 525 }; 526 /* 527 ********************************************************************* 528 ** 529 ********************************************************************* 530 */ 531 struct HBB_DOORBELL_1203 532 { 533 u_int8_t doorbell_reserved[ARCMSR_IOP2DRV_DOORBELL_1203]; /*reserved */ 534 u_int32_t iop2drv_doorbell; /*offset 0x00021870:00,01,02,03: window of "instruction flags" from iop to driver */ 535 u_int32_t iop2drv_doorbell_mask; /* 04,05,06,07: doorbell mask */ 536 u_int32_t drv2iop_doorbell; /* 08,09,10,11: window of "instruction flags" from driver to iop */ 537 u_int32_t drv2iop_doorbell_mask; /* 12,13,14,15: doorbell mask */ 538 }; 539 struct HBB_DOORBELL 540 { 541 u_int8_t doorbell_reserved[ARCMSR_DRV2IOP_DOORBELL]; /*reserved */ 542 u_int32_t drv2iop_doorbell; /*offset 0x00020400:00,01,02,03: window of "instruction flags" from driver to iop */ 543 u_int32_t drv2iop_doorbell_mask; /* 04,05,06,07: doorbell mask */ 544 u_int32_t iop2drv_doorbell; /* 08,09,10,11: window of "instruction flags" from iop to driver */ 545 u_int32_t iop2drv_doorbell_mask; /* 12,13,14,15: doorbell mask */ 546 }; 547 /* 548 ********************************************************************* 549 ** 550 ********************************************************************* 551 */ 552 struct HBB_RWBUFFER 553 { 554 u_int8_t message_reserved0[ARCMSR_MSGCODE_RWBUFFER]; /*reserved */ 555 u_int32_t msgcode_rwbuffer[256]; /*offset 0x0000fa00: 0, 1, 2, 3,...,1023: message code read write 1024bytes */ 556 u_int32_t message_wbuffer[32]; /*offset 0x0000fe00:1024,1025,1026,1027,...,1151: user space data to iop 128bytes */ 557 u_int32_t message_reserved1[32]; /* 1152,1153,1154,1155,...,1279: message reserved*/ 558 u_int32_t message_rbuffer[32]; /*offset 0x0000ff00:1280,1281,1282,1283,...,1407: iop data to user space 128bytes */ 559 }; 560 /* 561 ********************************************************************* 562 ** Messaging Unit (MU) of Type B processor(MARVEL) 563 ********************************************************************* 564 */ 565 struct HBB_MessageUnit 566 { 567 u_int32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* post queue buffer for iop */ 568 u_int32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* done queue buffer for iop */ 569 int32_t postq_index; /* post queue index */ 570 int32_t doneq_index; /* done queue index */ 571 struct HBB_DOORBELL *hbb_doorbell; 572 struct HBB_RWBUFFER *hbb_rwbuffer; 573 bus_size_t drv2iop_doorbell; /* window of "instruction flags" from driver to iop */ 574 bus_size_t drv2iop_doorbell_mask; /* doorbell mask */ 575 bus_size_t iop2drv_doorbell; /* window of "instruction flags" from iop to driver */ 576 bus_size_t iop2drv_doorbell_mask; /* doorbell mask */ 577 }; 578 579 /* 580 ********************************************************************* 581 ** Messaging Unit (MU) of Type C processor(LSI) 582 ********************************************************************* 583 */ 584 struct HBC_MessageUnit { 585 u_int32_t message_unit_status; /*0000 0003*/ 586 u_int32_t slave_error_attribute; /*0004 0007*/ 587 u_int32_t slave_error_address; /*0008 000B*/ 588 u_int32_t posted_outbound_doorbell; /*000C 000F*/ 589 u_int32_t master_error_attribute; /*0010 0013*/ 590 u_int32_t master_error_address_low; /*0014 0017*/ 591 u_int32_t master_error_address_high; /*0018 001B*/ 592 u_int32_t hcb_size; /*001C 001F size of the PCIe window used for HCB_Mode accesses*/ 593 u_int32_t inbound_doorbell; /*0020 0023*/ 594 u_int32_t diagnostic_rw_data; /*0024 0027*/ 595 u_int32_t diagnostic_rw_address_low; /*0028 002B*/ 596 u_int32_t diagnostic_rw_address_high; /*002C 002F*/ 597 u_int32_t host_int_status; /*0030 0033 host interrupt status*/ 598 u_int32_t host_int_mask; /*0034 0037 host interrupt mask*/ 599 u_int32_t dcr_data; /*0038 003B*/ 600 u_int32_t dcr_address; /*003C 003F*/ 601 u_int32_t inbound_queueport; /*0040 0043 port32 host inbound queue port*/ 602 u_int32_t outbound_queueport; /*0044 0047 port32 host outbound queue port*/ 603 u_int32_t hcb_pci_address_low; /*0048 004B*/ 604 u_int32_t hcb_pci_address_high; /*004C 004F*/ 605 u_int32_t iop_int_status; /*0050 0053*/ 606 u_int32_t iop_int_mask; /*0054 0057*/ 607 u_int32_t iop_inbound_queue_port; /*0058 005B*/ 608 u_int32_t iop_outbound_queue_port; /*005C 005F*/ 609 u_int32_t inbound_free_list_index; /*0060 0063 inbound free list producer consumer index*/ 610 u_int32_t inbound_post_list_index; /*0064 0067 inbound post list producer consumer index*/ 611 u_int32_t outbound_free_list_index; /*0068 006B outbound free list producer consumer index*/ 612 u_int32_t outbound_post_list_index; /*006C 006F outbound post list producer consumer index*/ 613 u_int32_t inbound_doorbell_clear; /*0070 0073*/ 614 u_int32_t i2o_message_unit_control; /*0074 0077*/ 615 u_int32_t last_used_message_source_address_low; /*0078 007B*/ 616 u_int32_t last_used_message_source_address_high; /*007C 007F*/ 617 u_int32_t pull_mode_data_byte_count[4]; /*0080 008F pull mode data byte count0..count7*/ 618 u_int32_t message_dest_address_index; /*0090 0093*/ 619 u_int32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/ 620 u_int32_t utility_A_int_counter_timer; /*0098 009B*/ 621 u_int32_t outbound_doorbell; /*009C 009F*/ 622 u_int32_t outbound_doorbell_clear; /*00A0 00A3*/ 623 u_int32_t message_source_address_index; /*00A4 00A7 message accelerator source address consumer producer index*/ 624 u_int32_t message_done_queue_index; /*00A8 00AB message accelerator completion queue consumer producer index*/ 625 u_int32_t reserved0; /*00AC 00AF*/ 626 u_int32_t inbound_msgaddr0; /*00B0 00B3 scratchpad0*/ 627 u_int32_t inbound_msgaddr1; /*00B4 00B7 scratchpad1*/ 628 u_int32_t outbound_msgaddr0; /*00B8 00BB scratchpad2*/ 629 u_int32_t outbound_msgaddr1; /*00BC 00BF scratchpad3*/ 630 u_int32_t inbound_queueport_low; /*00C0 00C3 port64 host inbound queue port low*/ 631 u_int32_t inbound_queueport_high; /*00C4 00C7 port64 host inbound queue port high*/ 632 u_int32_t outbound_queueport_low; /*00C8 00CB port64 host outbound queue port low*/ 633 u_int32_t outbound_queueport_high; /*00CC 00CF port64 host outbound queue port high*/ 634 u_int32_t iop_inbound_queue_port_low; /*00D0 00D3*/ 635 u_int32_t iop_inbound_queue_port_high; /*00D4 00D7*/ 636 u_int32_t iop_outbound_queue_port_low; /*00D8 00DB*/ 637 u_int32_t iop_outbound_queue_port_high; /*00DC 00DF*/ 638 u_int32_t message_dest_queue_port_low; /*00E0 00E3 message accelerator destination queue port low*/ 639 u_int32_t message_dest_queue_port_high; /*00E4 00E7 message accelerator destination queue port high*/ 640 u_int32_t last_used_message_dest_address_low; /*00E8 00EB last used message accelerator destination address low*/ 641 u_int32_t last_used_message_dest_address_high; /*00EC 00EF last used message accelerator destination address high*/ 642 u_int32_t message_done_queue_base_address_low; /*00F0 00F3 message accelerator completion queue base address low*/ 643 u_int32_t message_done_queue_base_address_high; /*00F4 00F7 message accelerator completion queue base address high*/ 644 u_int32_t host_diagnostic; /*00F8 00FB*/ 645 u_int32_t write_sequence; /*00FC 00FF*/ 646 u_int32_t reserved1[34]; /*0100 0187*/ 647 u_int32_t reserved2[1950]; /*0188 1FFF*/ 648 u_int32_t message_wbuffer[32]; /*2000 207F*/ 649 u_int32_t reserved3[32]; /*2080 20FF*/ 650 u_int32_t message_rbuffer[32]; /*2100 217F*/ 651 u_int32_t reserved4[32]; /*2180 21FF*/ 652 u_int32_t msgcode_rwbuffer[256]; /*2200 23FF*/ 653 }; 654 /* 655 ********************************************************************* 656 ** Messaging Unit (MU) of Type D processor 657 ********************************************************************* 658 */ 659 struct InBound_SRB { 660 uint32_t addressLow; //pointer to SRB block 661 uint32_t addressHigh; 662 uint32_t length; // in DWORDs 663 uint32_t reserved0; 664 }; 665 666 struct OutBound_SRB { 667 uint32_t addressLow; //pointer to SRB block 668 uint32_t addressHigh; 669 }; 670 671 struct HBD_MessageUnit { 672 uint32_t reserved0; 673 uint32_t chip_id; //0x0004 674 uint32_t cpu_mem_config; //0x0008 675 uint32_t reserved1[10]; //0x000C 676 uint32_t i2o_host_interrupt_mask; //0x0034 677 uint32_t reserved2[114]; //0x0038 678 uint32_t host_int_status; //0x0200 679 uint32_t host_int_enable; //0x0204 680 uint32_t reserved3[1]; //0x0208 681 uint32_t pcief0_int_enable; //0x020C 682 uint32_t reserved4[124]; //0x0210 683 uint32_t inbound_msgaddr0; //0x0400 684 uint32_t inbound_msgaddr1; //0x0404 685 uint32_t reserved5[6]; //0x0408 686 uint32_t outbound_msgaddr0; //0x0420 687 uint32_t outbound_msgaddr1; //0x0424 688 uint32_t reserved6[14]; //0x0428 689 uint32_t inbound_doorbell; //0x0460 690 uint32_t reserved7[7]; //0x0464 691 uint32_t outbound_doorbell; //0x0480 692 uint32_t outbound_doorbell_enable; //0x0484 693 uint32_t reserved8[734]; //0x0488 694 uint32_t inboundlist_base_low; //0x1000 695 uint32_t inboundlist_base_high; //0x1004 696 uint32_t reserved9[4]; //0x1008 697 uint32_t inboundlist_write_pointer; //0x1018 698 uint32_t inboundlist_read_pointer; //0x101C 699 uint32_t reserved10[16]; //0x1020 700 uint32_t outboundlist_base_low; //0x1060 701 uint32_t outboundlist_base_high; //0x1064 702 uint32_t reserved11; //0x1068 703 uint32_t outboundlist_copy_pointer; //0x106C 704 uint32_t outboundlist_read_pointer; //0x1070 0x1072 705 uint32_t reserved12[5]; //0x1074 706 uint32_t outboundlist_interrupt_cause; //0x1088 707 uint32_t outboundlist_interrupt_enable; //0x108C 708 uint32_t reserved13[988]; //0x1090 709 uint32_t message_wbuffer[32]; //0x2000 710 uint32_t reserved14[32]; //0x2080 711 uint32_t message_rbuffer[32]; //0x2100 712 uint32_t reserved15[32]; //0x2180 713 uint32_t msgcode_rwbuffer[256]; //0x2200 714 }; 715 716 struct HBD_MessageUnit0 { 717 struct InBound_SRB post_qbuffer[ARCMSR_MAX_HBD_POSTQUEUE]; 718 struct OutBound_SRB done_qbuffer[ARCMSR_MAX_HBD_POSTQUEUE+1]; 719 uint16_t postq_index; 720 uint16_t doneq_index; 721 struct HBD_MessageUnit *phbdmu; 722 }; 723 /* 724 ********************************************************************* 725 ** Messaging Unit (MU) of Type E processor(LSI) 726 ********************************************************************* 727 */ 728 struct HBE_MessageUnit { 729 u_int32_t iobound_doorbell; /*0000 0003*/ 730 u_int32_t write_sequence_3xxx; /*0004 0007*/ 731 u_int32_t host_diagnostic_3xxx; /*0008 000B*/ 732 u_int32_t posted_outbound_doorbell; /*000C 000F*/ 733 u_int32_t master_error_attribute; /*0010 0013*/ 734 u_int32_t master_error_address_low; /*0014 0017*/ 735 u_int32_t master_error_address_high; /*0018 001B*/ 736 u_int32_t hcb_size; /*001C 001F*/ 737 u_int32_t inbound_doorbell; /*0020 0023*/ 738 u_int32_t diagnostic_rw_data; /*0024 0027*/ 739 u_int32_t diagnostic_rw_address_low; /*0028 002B*/ 740 u_int32_t diagnostic_rw_address_high; /*002C 002F*/ 741 u_int32_t host_int_status; /*0030 0033 host interrupt status*/ 742 u_int32_t host_int_mask; /*0034 0037 host interrupt mask*/ 743 u_int32_t dcr_data; /*0038 003B*/ 744 u_int32_t dcr_address; /*003C 003F*/ 745 u_int32_t inbound_queueport; /*0040 0043 port32 host inbound queue port*/ 746 u_int32_t outbound_queueport; /*0044 0047 port32 host outbound queue port*/ 747 u_int32_t hcb_pci_address_low; /*0048 004B*/ 748 u_int32_t hcb_pci_address_high; /*004C 004F*/ 749 u_int32_t iop_int_status; /*0050 0053*/ 750 u_int32_t iop_int_mask; /*0054 0057*/ 751 u_int32_t iop_inbound_queue_port; /*0058 005B*/ 752 u_int32_t iop_outbound_queue_port; /*005C 005F*/ 753 u_int32_t inbound_free_list_index; /*0060 0063*/ 754 u_int32_t inbound_post_list_index; /*0064 0067*/ 755 u_int32_t outbound_free_list_index; /*0068 006B*/ 756 u_int32_t outbound_post_list_index; /*006C 006F*/ 757 u_int32_t inbound_doorbell_clear; /*0070 0073*/ 758 u_int32_t i2o_message_unit_control; /*0074 0077*/ 759 u_int32_t last_used_message_source_address_low; /*0078 007B*/ 760 u_int32_t last_used_message_source_address_high; /*007C 007F*/ 761 u_int32_t pull_mode_data_byte_count[4]; /*0080 008F*/ 762 u_int32_t message_dest_address_index; /*0090 0093*/ 763 u_int32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/ 764 u_int32_t utility_A_int_counter_timer; /*0098 009B*/ 765 u_int32_t outbound_doorbell; /*009C 009F*/ 766 u_int32_t outbound_doorbell_clear; /*00A0 00A3*/ 767 u_int32_t message_source_address_index; /*00A4 00A7*/ 768 u_int32_t message_done_queue_index; /*00A8 00AB*/ 769 u_int32_t reserved0; /*00AC 00AF*/ 770 u_int32_t inbound_msgaddr0; /*00B0 00B3 scratchpad0*/ 771 u_int32_t inbound_msgaddr1; /*00B4 00B7 scratchpad1*/ 772 u_int32_t outbound_msgaddr0; /*00B8 00BB scratchpad2*/ 773 u_int32_t outbound_msgaddr1; /*00BC 00BF scratchpad3*/ 774 u_int32_t inbound_queueport_low; /*00C0 00C3 port64 host inbound queue port low*/ 775 u_int32_t inbound_queueport_high; /*00C4 00C7 port64 host inbound queue port high*/ 776 u_int32_t outbound_queueport_low; /*00C8 00CB port64 host outbound queue port low*/ 777 u_int32_t outbound_queueport_high; /*00CC 00CF port64 host outbound queue port high*/ 778 u_int32_t iop_inbound_queue_port_low; /*00D0 00D3*/ 779 u_int32_t iop_inbound_queue_port_high; /*00D4 00D7*/ 780 u_int32_t iop_outbound_queue_port_low; /*00D8 00DB*/ 781 u_int32_t iop_outbound_queue_port_high; /*00DC 00DF*/ 782 u_int32_t message_dest_queue_port_low; /*00E0 00E3*/ 783 u_int32_t message_dest_queue_port_high; /*00E4 00E7*/ 784 u_int32_t last_used_message_dest_address_low; /*00E8 00EB*/ 785 u_int32_t last_used_message_dest_address_high; /*00EC 00EF*/ 786 u_int32_t message_done_queue_base_address_low; /*00F0 00F3*/ 787 u_int32_t message_done_queue_base_address_high; /*00F4 00F7*/ 788 u_int32_t host_diagnostic; /*00F8 00FB*/ 789 u_int32_t write_sequence; /*00FC 00FF*/ 790 u_int32_t reserved1[46]; /*0100 01B7*/ 791 u_int32_t reply_post_producer_index; /*01B8 01BB*/ 792 u_int32_t reply_post_consumer_index; /*01BC 01BF*/ 793 u_int32_t reserved2[1936]; /*01C0 1FFF*/ 794 u_int32_t message_wbuffer[32]; /*2000 207F*/ 795 u_int32_t reserved3[32]; /*2080 20FF*/ 796 u_int32_t message_rbuffer[32]; /*2100 217F*/ 797 u_int32_t reserved4[32]; /*2180 21FF*/ 798 u_int32_t msgcode_rwbuffer[256]; /*2200 23FF*/ 799 }; 800 801 /* 802 ********************************************************************* 803 ** Messaging Unit (MU) of Type F processor(LSI) 804 ********************************************************************* 805 */ 806 struct HBF_MessageUnit { 807 u_int32_t iobound_doorbell; /*0000 0003*/ 808 u_int32_t write_sequence_3xxx; /*0004 0007*/ 809 u_int32_t host_diagnostic_3xxx; /*0008 000B*/ 810 u_int32_t posted_outbound_doorbell; /*000C 000F*/ 811 u_int32_t master_error_attribute; /*0010 0013*/ 812 u_int32_t master_error_address_low; /*0014 0017*/ 813 u_int32_t master_error_address_high; /*0018 001B*/ 814 u_int32_t hcb_size; /*001C 001F*/ 815 u_int32_t inbound_doorbell; /*0020 0023*/ 816 u_int32_t diagnostic_rw_data; /*0024 0027*/ 817 u_int32_t diagnostic_rw_address_low; /*0028 002B*/ 818 u_int32_t diagnostic_rw_address_high; /*002C 002F*/ 819 u_int32_t host_int_status; /*0030 0033 host interrupt status*/ 820 u_int32_t host_int_mask; /*0034 0037 host interrupt mask*/ 821 u_int32_t dcr_data; /*0038 003B*/ 822 u_int32_t dcr_address; /*003C 003F*/ 823 u_int32_t inbound_queueport; /*0040 0043 port32 host inbound queue port*/ 824 u_int32_t outbound_queueport; /*0044 0047 port32 host outbound queue port*/ 825 u_int32_t hcb_pci_address_low; /*0048 004B*/ 826 u_int32_t hcb_pci_address_high; /*004C 004F*/ 827 u_int32_t iop_int_status; /*0050 0053*/ 828 u_int32_t iop_int_mask; /*0054 0057*/ 829 u_int32_t iop_inbound_queue_port; /*0058 005B*/ 830 u_int32_t iop_outbound_queue_port; /*005C 005F*/ 831 u_int32_t inbound_free_list_index; /*0060 0063*/ 832 u_int32_t inbound_post_list_index; /*0064 0067*/ 833 u_int32_t reply_post_producer_index; /*0068 006B*/ 834 u_int32_t reply_post_consumer_index; /*006C 006F*/ 835 u_int32_t inbound_doorbell_clear; /*0070 0073*/ 836 u_int32_t i2o_message_unit_control; /*0074 0077*/ 837 u_int32_t last_used_message_source_address_low; /*0078 007B*/ 838 u_int32_t last_used_message_source_address_high; /*007C 007F*/ 839 u_int32_t pull_mode_data_byte_count[4]; /*0080 008F*/ 840 u_int32_t message_dest_address_index; /*0090 0093*/ 841 u_int32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/ 842 u_int32_t utility_A_int_counter_timer; /*0098 009B*/ 843 u_int32_t outbound_doorbell; /*009C 009F*/ 844 u_int32_t outbound_doorbell_clear; /*00A0 00A3*/ 845 u_int32_t message_source_address_index; /*00A4 00A7*/ 846 u_int32_t message_done_queue_index; /*00A8 00AB*/ 847 u_int32_t reserved0; /*00AC 00AF*/ 848 u_int32_t inbound_msgaddr0; /*00B0 00B3 scratchpad0*/ 849 u_int32_t inbound_msgaddr1; /*00B4 00B7 scratchpad1*/ 850 u_int32_t outbound_msgaddr0; /*00B8 00BB scratchpad2*/ 851 u_int32_t outbound_msgaddr1; /*00BC 00BF scratchpad3*/ 852 u_int32_t inbound_queueport_low; /*00C0 00C3 port64 host inbound queue port low*/ 853 u_int32_t inbound_queueport_high; /*00C4 00C7 port64 host inbound queue port high*/ 854 u_int32_t outbound_queueport_low; /*00C8 00CB port64 host outbound queue port low*/ 855 u_int32_t outbound_queueport_high; /*00CC 00CF port64 host outbound queue port high*/ 856 u_int32_t iop_inbound_queue_port_low; /*00D0 00D3*/ 857 u_int32_t iop_inbound_queue_port_high; /*00D4 00D7*/ 858 u_int32_t iop_outbound_queue_port_low; /*00D8 00DB*/ 859 u_int32_t iop_outbound_queue_port_high; /*00DC 00DF*/ 860 u_int32_t message_dest_queue_port_low; /*00E0 00E3*/ 861 u_int32_t message_dest_queue_port_high; /*00E4 00E7*/ 862 u_int32_t last_used_message_dest_address_low; /*00E8 00EB*/ 863 u_int32_t last_used_message_dest_address_high; /*00EC 00EF*/ 864 u_int32_t message_done_queue_base_address_low; /*00F0 00F3*/ 865 u_int32_t message_done_queue_base_address_high; /*00F4 00F7*/ 866 u_int32_t host_diagnostic; /*00F8 00FB*/ 867 u_int32_t write_sequence; /*00FC 00FF*/ 868 u_int32_t reserved1[46]; /*0100 01B7*/ 869 u_int32_t reply_post_producer_index1; /*01B8 01BB*/ 870 u_int32_t reply_post_consumer_index1; /*01BC 01BF*/ 871 }; 872 873 #define MESG_RW_BUFFER_SIZE (256 * 3) 874 875 typedef struct deliver_completeQ { 876 u_int16_t cmdFlag; 877 u_int16_t cmdSMID; 878 u_int16_t cmdLMID; // reserved (0) 879 u_int16_t cmdFlag2; // reserved (0) 880 } DeliverQ, CompletionQ, *pDeliver_Q, *pCompletion_Q; 881 882 #define COMPLETION_Q_POOL_SIZE (sizeof(struct deliver_completeQ) * 512 + 128) 883 884 /* 885 ********************************************************************* 886 ** 887 ********************************************************************* 888 */ 889 struct MessageUnit_UNION 890 { 891 union { 892 struct HBA_MessageUnit hbamu; 893 struct HBB_MessageUnit hbbmu; 894 struct HBC_MessageUnit hbcmu; 895 struct HBD_MessageUnit0 hbdmu; 896 struct HBE_MessageUnit hbemu; 897 struct HBF_MessageUnit hbfmu; 898 } muu; 899 }; 900 /* 901 ************************************************************* 902 ** structure for holding DMA address data 903 ************************************************************* 904 */ 905 #define IS_SG64_ADDR 0x01000000 /* bit24 */ 906 /* 907 ************************************************************************************************ 908 ** ARECA FIRMWARE SPEC 909 ************************************************************************************************ 910 ** Usage of IOP331 adapter 911 ** (All In/Out is in IOP331's view) 912 ** 1. Message 0 --> InitThread message and retrun code 913 ** 2. Doorbell is used for RS-232 emulation 914 ** inDoorBell : bit0 -- data in ready (DRIVER DATA WRITE OK) 915 ** bit1 -- data out has been read (DRIVER DATA READ OK) 916 ** outDooeBell: bit0 -- data out ready (IOP331 DATA WRITE OK) 917 ** bit1 -- data in has been read (IOP331 DATA READ OK) 918 ** 3. Index Memory Usage 919 ** offset 0xf00 : for RS232 out (request buffer) 920 ** offset 0xe00 : for RS232 in (scratch buffer) 921 ** offset 0xa00 : for inbound message code msgcode_rwbuffer (driver send to IOP331) 922 ** offset 0xa00 : for outbound message code msgcode_rwbuffer (IOP331 send to driver) 923 ** 4. RS-232 emulation 924 ** Currently 128 byte buffer is used 925 ** 1st u_int32_t : Data length (1--124) 926 ** Byte 4--127 : Max 124 bytes of data 927 ** 5. PostQ 928 ** All SCSI Command must be sent through postQ: 929 ** (inbound queue port) Request frame must be 32 bytes aligned 930 ** # bit27--bit31 => flag for post ccb 931 ** # bit0--bit26 => real address (bit27--bit31) of post arcmsr_cdb 932 ** bit31 : 0 : 256 bytes frame 933 ** 1 : 512 bytes frame 934 ** bit30 : 0 : normal request 935 ** 1 : BIOS request 936 ** bit29 : reserved 937 ** bit28 : reserved 938 ** bit27 : reserved 939 ** ------------------------------------------------------------------------------- 940 ** (outbount queue port) Request reply 941 ** # bit27--bit31 => flag for reply 942 ** # bit0--bit26 => real address (bit27--bit31) of reply arcmsr_cdb 943 ** bit31 : must be 0 (for this type of reply) 944 ** bit30 : reserved for BIOS handshake 945 ** bit29 : reserved 946 ** bit28 : 0 : no error, ignore AdapStatus/DevStatus/SenseData 947 ** 1 : Error, error code in AdapStatus/DevStatus/SenseData 948 ** bit27 : reserved 949 ** 6. BIOS request 950 ** All BIOS request is the same with request from PostQ 951 ** Except : 952 ** Request frame is sent from configuration space 953 ** offset: 0x78 : Request Frame (bit30 == 1) 954 ** offset: 0x18 : writeonly to generate IRQ to IOP331 955 ** Completion of request: 956 ** (bit30 == 0, bit28==err flag) 957 ** 7. Definition of SGL entry (structure) 958 ** 8. Message1 Out - Diag Status Code (????) 959 ** 9. Message0 message code : 960 ** 0x00 : NOP 961 ** 0x01 : Get Config ->offset 0xa00 :for outbound message code msgcode_rwbuffer (IOP331 send to driver) 962 ** Signature 0x87974060(4) 963 ** Request len 0x00000200(4) 964 ** numbers of queue 0x00000100(4) 965 ** SDRAM Size 0x00000100(4)-->256 MB 966 ** IDE Channels 0x00000008(4) 967 ** vendor 40 bytes char 968 ** model 8 bytes char 969 ** FirmVer 16 bytes char 970 ** Device Map 16 bytes char 971 ** 972 ** FirmwareVersion DWORD <== Added for checking of new firmware capability 973 ** 0x02 : Set Config ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver send to IOP331) 974 ** Signature 0x87974063(4) 975 ** UPPER32 of Request Frame (4)-->Driver Only 976 ** 0x03 : Reset (Abort all queued Command) 977 ** 0x04 : Stop Background Activity 978 ** 0x05 : Flush Cache 979 ** 0x06 : Start Background Activity (re-start if background is halted) 980 ** 0x07 : Check If Host Command Pending (Novell May Need This Function) 981 ** 0x08 : Set controller time ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver to IOP331) 982 ** byte 0 : 0xaa <-- signature 983 ** byte 1 : 0x55 <-- signature 984 ** byte 2 : year (04) 985 ** byte 3 : month (1..12) 986 ** byte 4 : date (1..31) 987 ** byte 5 : hour (0..23) 988 ** byte 6 : minute (0..59) 989 ** byte 7 : second (0..59) 990 ** ********************************************************************************* 991 ** Porting Of LSI2108/2116 Based PCIE SAS/6G host raid adapter 992 ** ==> Difference from IOP348 993 ** <1> Message Register 0,1 (the same usage) Init Thread message and retrun code 994 ** Inbound Message 0 (inbound_msgaddr0) : at offset 0xB0 (Scratchpad0) for inbound message code msgcode_rwbuffer (driver send to IOP) 995 ** Inbound Message 1 (inbound_msgaddr1) : at offset 0xB4 (Scratchpad1) Out.... Diag Status Code 996 ** Outbound Message 0 (outbound_msgaddr0): at offset 0xB8 (Scratchpad3) Out.... Diag Status Code 997 ** Outbound Message 1 (outbound_msgaddr1): at offset 0xBC (Scratchpad2) for outbound message code msgcode_rwbuffer (IOP send to driver) 998 ** <A> use doorbell to generate interrupt 999 ** 1000 ** inbound doorbell: bit3 -- inbound message 0 ready (driver to iop) 1001 ** outbound doorbell: bit3 -- outbound message 0 ready (iop to driver) 1002 ** 1003 ** a. Message1: Out - Diag Status Code (????) 1004 ** 1005 ** b. Message0: message code 1006 ** 0x00 : NOP 1007 ** 0x01 : Get Config ->offset 0xB8 :for outbound message code msgcode_rwbuffer (IOP send to driver) 1008 ** Signature 0x87974060(4) 1009 ** Request len 0x00000200(4) 1010 ** numbers of queue 0x00000100(4) 1011 ** SDRAM Size 0x00000100(4)-->256 MB 1012 ** IDE Channels 0x00000008(4) 1013 ** vendor 40 bytes char 1014 ** model 8 bytes char 1015 ** FirmVer 16 bytes char 1016 ** Device Map 16 bytes char 1017 ** cfgVersion ULONG <== Added for checking of new firmware capability 1018 ** 0x02 : Set Config ->offset 0xB0 :for inbound message code msgcode_rwbuffer (driver send to IOP) 1019 ** Signature 0x87974063(4) 1020 ** UPPER32 of Request Frame (4)-->Driver Only 1021 ** 0x03 : Reset (Abort all queued Command) 1022 ** 0x04 : Stop Background Activity 1023 ** 0x05 : Flush Cache 1024 ** 0x06 : Start Background Activity (re-start if background is halted) 1025 ** 0x07 : Check If Host Command Pending (Novell May Need This Function) 1026 ** 0x08 : Set controller time ->offset 0xB0 : for inbound message code msgcode_rwbuffer (driver to IOP) 1027 ** byte 0 : 0xaa <-- signature 1028 ** byte 1 : 0x55 <-- signature 1029 ** byte 2 : year (04) 1030 ** byte 3 : month (1..12) 1031 ** byte 4 : date (1..31) 1032 ** byte 5 : hour (0..23) 1033 ** byte 6 : minute (0..59) 1034 ** byte 7 : second (0..59) 1035 ** 1036 ** <2> Doorbell Register is used for RS-232 emulation 1037 ** <A> different clear register 1038 ** <B> different bit0 definition (bit0 is reserved) 1039 ** 1040 ** inbound doorbell : at offset 0x20 1041 ** inbound doorbell clear : at offset 0x70 1042 ** 1043 ** inbound doorbell : bit0 -- reserved 1044 ** bit1 -- data in ready (DRIVER DATA WRITE OK) 1045 ** bit2 -- data out has been read (DRIVER DATA READ OK) 1046 ** bit3 -- inbound message 0 ready 1047 ** bit4 -- more than 12 request completed in a time 1048 ** 1049 ** outbound doorbell : at offset 0x9C 1050 ** outbound doorbell clear : at offset 0xA0 1051 ** 1052 ** outbound doorbell : bit0 -- reserved 1053 ** bit1 -- data out ready (IOP DATA WRITE OK) 1054 ** bit2 -- data in has been read (IOP DATA READ OK) 1055 ** bit3 -- outbound message 0 ready 1056 ** 1057 ** <3> Index Memory Usage (Buffer Area) 1058 ** COMPORT_IN at 0x2000: message_wbuffer -- 128 bytes (to be sent to ROC) : for RS232 in (scratch buffer) 1059 ** COMPORT_OUT at 0x2100: message_rbuffer -- 128 bytes (to be sent to host): for RS232 out (request buffer) 1060 ** BIOS_CFG_AREA at 0x2200: msgcode_rwbuffer -- 1024 bytes for outbound message code msgcode_rwbuffer (IOP send to driver) 1061 ** BIOS_CFG_AREA at 0x2200: msgcode_rwbuffer -- 1024 bytes for inbound message code msgcode_rwbuffer (driver send to IOP) 1062 ** 1063 ** <4> PostQ (Command Post Address) 1064 ** All SCSI Command must be sent through postQ: 1065 ** inbound queue port32 at offset 0x40 , 0x41, 0x42, 0x43 1066 ** inbound queue port64 at offset 0xC0 (lower)/0xC4 (upper) 1067 ** outbound queue port32 at offset 0x44 1068 ** outbound queue port64 at offset 0xC8 (lower)/0xCC (upper) 1069 ** <A> For 32bit queue, access low part is enough to send/receive request 1070 ** i.e. write 0x40/0xC0, ROC will get the request with high part == 0, the 1071 ** same for outbound queue port 1072 ** <B> For 64bit queue, if 64bit instruction is supported, use 64bit instruction 1073 ** to post inbound request in a single instruction, and use 64bit instruction 1074 ** to retrieve outbound request in a single instruction. 1075 ** If in 32bit environment, when sending inbound queue, write high part first 1076 ** then write low part. For receiving outbound request, read high part first 1077 ** then low part, to check queue empty, ONLY check high part to be 0xFFFFFFFF. 1078 ** If high part is 0xFFFFFFFF, DO NOT read low part, this may corrupt the 1079 ** consistency of the FIFO. Another way to check empty is to check status flag 1080 ** at 0x30 bit3. 1081 ** <C> Post Address IS NOT shifted (must be 16 bytes aligned) 1082 ** For BIOS, 16bytes aligned is OK 1083 ** For Driver, 32bytes alignment is recommended. 1084 ** POST Command bit0 to bit3 is defined differently 1085 ** ---------------------------- 1086 ** bit0:1 for PULL mode (must be 1) 1087 ** ---------------------------- 1088 ** bit3/2/1: for arcmsr cdb size (arccdbsize) 1089 ** 000: <= 0x0080 (128) 1090 ** 001: <= 0x0100 (256) 1091 ** 010: <= 0x0180 (384) 1092 ** 011: <= 0x0200 (512) 1093 ** 100: <= 0x0280 (640) 1094 ** 101: <= 0x0300 (768) 1095 ** 110: <= 0x0300 (reserved) 1096 ** 111: <= 0x0300 (reserved) 1097 ** ----------------------------- 1098 ** if len > 0x300 the len always set as 0x300 1099 ** ----------------------------- 1100 ** post addr = addr | ((len-1) >> 6) | 1 1101 ** ----------------------------- 1102 ** page length in command buffer still required, 1103 ** 1104 ** if page length > 3, 1105 ** firmware will assume more request data need to be retrieved 1106 ** 1107 ** <D> Outbound Posting 1108 ** bit0:0 , no error, 1 with error, refer to status buffer 1109 ** bit1:0 , reserved (will be 0) 1110 ** bit2:0 , reserved (will be 0) 1111 ** bit3:0 , reserved (will be 0) 1112 ** bit63-4: Completed command address 1113 ** 1114 ** <E> BIOS support, no special support is required. 1115 ** LSI2108 support I/O register 1116 ** All driver functionality is supported through I/O address 1117 ** 1118 ************************************************************************************************ 1119 */ 1120 /* 1121 ********************************** 1122 ** 1123 ********************************** 1124 */ 1125 /* size 8 bytes */ 1126 /* 32bit Scatter-Gather list */ 1127 struct SG32ENTRY { /* length bit 24 == 0 */ 1128 u_int32_t length; /* high 8 bit == flag,low 24 bit == length */ 1129 u_int32_t address; 1130 }; 1131 /* size 12 bytes */ 1132 /* 64bit Scatter-Gather list */ 1133 struct SG64ENTRY { /* length bit 24 == 1 */ 1134 u_int32_t length; /* high 8 bit == flag,low 24 bit == length */ 1135 u_int32_t address; 1136 u_int32_t addresshigh; 1137 }; 1138 struct SGENTRY_UNION { 1139 union { 1140 struct SG32ENTRY sg32entry; /* 30h Scatter gather address */ 1141 struct SG64ENTRY sg64entry; /* 30h */ 1142 }u; 1143 }; 1144 /* 1145 ********************************** 1146 ** 1147 ********************************** 1148 */ 1149 struct QBUFFER { 1150 u_int32_t data_len; 1151 u_int8_t data[124]; 1152 }; 1153 /* 1154 ********************************** 1155 */ 1156 typedef struct PHYS_ADDR64 { 1157 u_int32_t phyadd_low; 1158 u_int32_t phyadd_high; 1159 }PHYSADDR64; 1160 /* 1161 ************************************************************************************************ 1162 ** FIRMWARE INFO 1163 ************************************************************************************************ 1164 */ 1165 #define ARCMSR_FW_MODEL_OFFSET 15 1166 #define ARCMSR_FW_VERS_OFFSET 17 1167 #define ARCMSR_FW_DEVMAP_OFFSET 21 1168 #define ARCMSR_FW_CFGVER_OFFSET 25 1169 1170 struct FIRMWARE_INFO { 1171 u_int32_t signature; /*0,00-03*/ 1172 u_int32_t request_len; /*1,04-07*/ 1173 u_int32_t numbers_queue; /*2,08-11*/ 1174 u_int32_t sdram_size; /*3,12-15*/ 1175 u_int32_t ide_channels; /*4,16-19*/ 1176 char vendor[40]; /*5,20-59*/ 1177 char model[8]; /*15,60-67*/ 1178 char firmware_ver[16]; /*17,68-83*/ 1179 char device_map[16]; /*21,84-99*/ 1180 u_int32_t cfgVersion; /*25,100-103 Added for checking of new firmware capability*/ 1181 char cfgSerial[16]; /*26,104-119*/ 1182 u_int32_t cfgPicStatus; /*30,120-123*/ 1183 }; 1184 /* (A) For cfgVersion in FIRMWARE_INFO 1185 ** if low BYTE (byte#0) >= 3 (version 3) 1186 ** then byte#1 report the capability of the firmware can xfer in a single request 1187 ** 1188 ** byte#1 1189 ** 0 256K 1190 ** 1 512K 1191 ** 2 1M 1192 ** 3 2M 1193 ** 4 4M 1194 ** 5 8M 1195 ** 6 16M 1196 ** (B) Byte offset 7 (Reserved1) of CDB is changed to msgPages 1197 ** Driver support new xfer method need to set this field to indicate 1198 ** large CDB block in 0x100 unit (we use 0x100 byte as one page) 1199 ** e.g. If the length of CDB including MSG header and SGL is 0x1508 1200 ** driver need to set the msgPages to 0x16 1201 ** (C) REQ_LEN_512BYTE must be used also to indicate SRB length 1202 ** e.g. CDB len msgPages REQ_LEN_512BYTE flag 1203 ** <= 0x100 1 0 1204 ** <= 0x200 2 1 1205 ** <= 0x300 3 1 1206 ** <= 0x400 4 1 1207 ** . 1208 ** . 1209 */ 1210 1211 /* 1212 ************************************************************************************************ 1213 ** size 0x1F8 (504) 1214 ************************************************************************************************ 1215 */ 1216 struct ARCMSR_CDB { 1217 u_int8_t Bus; /* 00h should be 0 */ 1218 u_int8_t TargetID; /* 01h should be 0--15 */ 1219 u_int8_t LUN; /* 02h should be 0--7 */ 1220 u_int8_t Function; /* 03h should be 1 */ 1221 1222 u_int8_t CdbLength; /* 04h not used now */ 1223 u_int8_t sgcount; /* 05h */ 1224 u_int8_t Flags; /* 06h */ 1225 u_int8_t msgPages; /* 07h */ 1226 1227 u_int32_t Context; /* 08h Address of this request */ 1228 u_int32_t DataLength; /* 0ch not used now */ 1229 1230 u_int8_t Cdb[16]; /* 10h SCSI CDB */ 1231 /* 1232 ******************************************************** 1233 ** Device Status : the same from SCSI bus if error occur 1234 ** SCSI bus status codes. 1235 ******************************************************** 1236 */ 1237 u_int8_t DeviceStatus; /* 20h if error */ 1238 1239 u_int8_t SenseData[15]; /* 21h output */ 1240 1241 union { 1242 struct SG32ENTRY sg32entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h Scatter gather address */ 1243 struct SG64ENTRY sg64entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h */ 1244 } u; 1245 }; 1246 /* CDB flag */ 1247 #define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01 /* bit 0: 0(256) / 1(512) bytes */ 1248 #define ARCMSR_CDB_FLAG_BIOS 0x02 /* bit 1: 0(from driver) / 1(from BIOS) */ 1249 #define ARCMSR_CDB_FLAG_WRITE 0x04 /* bit 2: 0(Data in) / 1(Data out) */ 1250 #define ARCMSR_CDB_FLAG_SIMPLEQ 0x00 /* bit 4/3 ,00 : simple Q,01 : head of Q,10 : ordered Q */ 1251 #define ARCMSR_CDB_FLAG_HEADQ 0x08 1252 #define ARCMSR_CDB_FLAG_ORDEREDQ 0x10 1253 /* scsi status */ 1254 #define SCSISTAT_GOOD 0x00 1255 #define SCSISTAT_CHECK_CONDITION 0x02 1256 #define SCSISTAT_CONDITION_MET 0x04 1257 #define SCSISTAT_BUSY 0x08 1258 #define SCSISTAT_INTERMEDIATE 0x10 1259 #define SCSISTAT_INTERMEDIATE_COND_MET 0x14 1260 #define SCSISTAT_RESERVATION_CONFLICT 0x18 1261 #define SCSISTAT_COMMAND_TERMINATED 0x22 1262 #define SCSISTAT_QUEUE_FULL 0x28 1263 /* DeviceStatus */ 1264 #define ARCMSR_DEV_SELECT_TIMEOUT 0xF0 1265 #define ARCMSR_DEV_ABORTED 0xF1 1266 #define ARCMSR_DEV_INIT_FAIL 0xF2 1267 /* 1268 ********************************************************************* 1269 ** Command Control Block (SrbExtension) 1270 ** SRB must be not cross page boundary,and the order from offset 0 1271 ** structure describing an ATA disk request 1272 ** this SRB length must be 32 bytes boundary 1273 ********************************************************************* 1274 */ 1275 struct CommandControlBlock { 1276 struct ARCMSR_CDB arcmsr_cdb; /* 0 -503 (size of CDB=504): arcmsr messenger scsi command descriptor size 504 bytes */ 1277 u_int32_t cdb_phyaddr_low; /* 504-507 */ 1278 u_int32_t arc_cdb_size; /* 508-511 */ 1279 /* ======================512+32 bytes============================ */ 1280 union ccb *pccb; /* 512-515 516-519 pointer of freebsd scsi command */ 1281 struct AdapterControlBlock *acb; /* 520-523 524-527 */ 1282 bus_dmamap_t dm_segs_dmamap; /* 528-531 532-535 */ 1283 u_int16_t srb_flags; /* 536-537 */ 1284 u_int16_t srb_state; /* 538-539 */ 1285 u_int32_t cdb_phyaddr_high; /* 540-543 */ 1286 struct callout ccb_callout; 1287 u_int32_t smid; 1288 /* ========================================================== */ 1289 }; 1290 /* srb_flags */ 1291 #define SRB_FLAG_READ 0x0000 1292 #define SRB_FLAG_WRITE 0x0001 1293 #define SRB_FLAG_ERROR 0x0002 1294 #define SRB_FLAG_FLUSHCACHE 0x0004 1295 #define SRB_FLAG_MASTER_ABORTED 0x0008 1296 #define SRB_FLAG_DMAVALID 0x0010 1297 #define SRB_FLAG_DMACONSISTENT 0x0020 1298 #define SRB_FLAG_DMAWRITE 0x0040 1299 #define SRB_FLAG_PKTBIND 0x0080 1300 #define SRB_FLAG_TIMER_START 0x0080 1301 /* srb_state */ 1302 #define ARCMSR_SRB_DONE 0x0000 1303 #define ARCMSR_SRB_UNBUILD 0x0000 1304 #define ARCMSR_SRB_TIMEOUT 0x1111 1305 #define ARCMSR_SRB_RETRY 0x2222 1306 #define ARCMSR_SRB_START 0x55AA 1307 #define ARCMSR_SRB_PENDING 0xAA55 1308 #define ARCMSR_SRB_RESET 0xA5A5 1309 #define ARCMSR_SRB_ABORTED 0x5A5A 1310 #define ARCMSR_SRB_ILLEGAL 0xFFFF 1311 1312 #define SRB_SIZE ((sizeof(struct CommandControlBlock)+0x1f) & 0xffe0) 1313 #define ARCMSR_SRBS_POOL_SIZE (SRB_SIZE * ARCMSR_MAX_FREESRB_NUM) 1314 1315 /* 1316 ********************************************************************* 1317 ** Adapter Control Block 1318 ********************************************************************* 1319 */ 1320 #define ACB_ADAPTER_TYPE_A 0x00000000 /* hba I IOP */ 1321 #define ACB_ADAPTER_TYPE_B 0x00000001 /* hbb M IOP */ 1322 #define ACB_ADAPTER_TYPE_C 0x00000002 /* hbc L IOP */ 1323 #define ACB_ADAPTER_TYPE_D 0x00000003 /* hbd M IOP */ 1324 #define ACB_ADAPTER_TYPE_E 0x00000004 /* hbd L IOP */ 1325 #define ACB_ADAPTER_TYPE_F 0x00000005 /* hbd L IOP */ 1326 1327 struct AdapterControlBlock { 1328 u_int32_t adapter_type; /* adapter A,B..... */ 1329 1330 bus_space_tag_t btag[2]; 1331 bus_space_handle_t bhandle[2]; 1332 bus_dma_tag_t parent_dmat; 1333 bus_dma_tag_t dm_segs_dmat; /* dmat for buffer I/O */ 1334 bus_dma_tag_t srb_dmat; /* dmat for freesrb */ 1335 bus_dmamap_t srb_dmamap; 1336 device_t pci_dev; 1337 struct cdev *ioctl_dev; 1338 int pci_unit; 1339 1340 struct resource *sys_res_arcmsr[2]; 1341 struct resource *irqres[ARCMSR_NUM_MSIX_VECTORS]; 1342 void *ih[ARCMSR_NUM_MSIX_VECTORS]; /* interrupt handle */ 1343 int irq_id[ARCMSR_NUM_MSIX_VECTORS]; 1344 1345 /* Hooks into the CAM XPT */ 1346 struct cam_sim *psim; 1347 struct cam_path *ppath; 1348 u_int8_t *uncacheptr; 1349 unsigned long vir2phy_offset; 1350 union { 1351 unsigned long phyaddr; 1352 struct { 1353 u_int32_t phyadd_low; 1354 u_int32_t phyadd_high; 1355 }B; 1356 }srb_phyaddr; 1357 // unsigned long srb_phyaddr; 1358 /* Offset is used in making arc cdb physical to virtual calculations */ 1359 u_int32_t outbound_int_enable; 1360 1361 struct MessageUnit_UNION *pmu; /* message unit ATU inbound base address0 */ 1362 uint32_t *message_wbuffer; //0x000 - COMPORT_IN (to be sent to ROC) 1363 uint32_t *message_rbuffer; //0x100 - COMPORT_OUT (to be sent to Host) 1364 uint32_t *msgcode_rwbuffer; //0x200 - BIOS_AREA 1365 1366 u_int8_t adapter_index; 1367 u_int8_t irq; 1368 u_int16_t acb_flags; 1369 1370 struct CommandControlBlock *psrb_pool[ARCMSR_MAX_FREESRB_NUM]; /* serial srb pointer array */ 1371 struct CommandControlBlock *srbworkingQ[ARCMSR_MAX_FREESRB_NUM]; /* working srb pointer array */ 1372 int32_t workingsrb_doneindex; /* done srb array index */ 1373 int32_t workingsrb_startindex; /* start srb array index */ 1374 int32_t srboutstandingcount; 1375 1376 u_int8_t rqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for read from 80331 */ 1377 u_int32_t rqbuf_firstindex; /* first of read buffer */ 1378 u_int32_t rqbuf_lastindex; /* last of read buffer */ 1379 1380 u_int8_t wqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for write to 80331 */ 1381 u_int32_t wqbuf_firstindex; /* first of write buffer */ 1382 u_int32_t wqbuf_lastindex; /* last of write buffer */ 1383 1384 arcmsr_lock_t isr_lock; 1385 arcmsr_lock_t srb_lock; 1386 arcmsr_lock_t postDone_lock; 1387 arcmsr_lock_t qbuffer_lock; 1388 1389 u_int8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN]; /* id0 ..... id15,lun0...lun7 */ 1390 u_int32_t num_resets; 1391 u_int32_t num_aborts; 1392 u_int32_t firm_request_len; /*1,04-07*/ 1393 u_int32_t firm_numbers_queue; /*2,08-11*/ 1394 u_int32_t firm_sdram_size; /*3,12-15*/ 1395 u_int32_t firm_ide_channels; /*4,16-19*/ 1396 u_int32_t firm_cfg_version; 1397 char firm_model[12]; /*15,60-67*/ 1398 char firm_version[20]; /*17,68-83*/ 1399 char device_map[20]; /*21,84-99 */ 1400 struct callout devmap_callout; 1401 u_int32_t pktRequestCount; 1402 u_int32_t pktReturnCount; 1403 u_int32_t vendor_device_id; 1404 u_int32_t adapter_bus_speed; 1405 u_int32_t maxOutstanding; 1406 u_int16_t sub_device_id; 1407 u_int32_t doneq_index; 1408 u_int32_t in_doorbell; 1409 u_int32_t out_doorbell; 1410 u_int32_t completionQ_entry; 1411 pCompletion_Q pCompletionQ; 1412 int msix_vectors; 1413 int rid[2]; 1414 unsigned long completeQ_phys; 1415 };/* HW_DEVICE_EXTENSION */ 1416 /* acb_flags */ 1417 #define ACB_F_SCSISTOPADAPTER 0x0001 1418 #define ACB_F_MSG_STOP_BGRB 0x0002 /* stop RAID background rebuild */ 1419 #define ACB_F_MSG_START_BGRB 0x0004 /* stop RAID background rebuild */ 1420 #define ACB_F_IOPDATA_OVERFLOW 0x0008 /* iop ioctl data rqbuffer overflow */ 1421 #define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010 /* ioctl clear wqbuffer */ 1422 #define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020 /* ioctl clear rqbuffer */ 1423 #define ACB_F_MESSAGE_WQBUFFER_READ 0x0040 1424 #define ACB_F_BUS_RESET 0x0080 1425 #define ACB_F_IOP_INITED 0x0100 /* iop init */ 1426 #define ACB_F_MAPFREESRB_FAILD 0x0200 /* arcmsr_map_freesrb failed */ 1427 #define ACB_F_CAM_DEV_QFRZN 0x0400 1428 #define ACB_F_BUS_HANG_ON 0x0800 /* need hardware reset bus */ 1429 #define ACB_F_SRB_FUNCTION_POWER 0x1000 1430 #define ACB_F_MSIX_ENABLED 0x2000 1431 /* devstate */ 1432 #define ARECA_RAID_GONE 0x55 1433 #define ARECA_RAID_GOOD 0xaa 1434 /* adapter_bus_speed */ 1435 #define ACB_BUS_SPEED_3G 0 1436 #define ACB_BUS_SPEED_6G 1 1437 #define ACB_BUS_SPEED_12G 2 1438 /* 1439 ************************************************************* 1440 ************************************************************* 1441 */ 1442 struct SENSE_DATA { 1443 u_int8_t ErrorCode:7; 1444 u_int8_t Valid:1; 1445 u_int8_t SegmentNumber; 1446 u_int8_t SenseKey:4; 1447 u_int8_t Reserved:1; 1448 u_int8_t IncorrectLength:1; 1449 u_int8_t EndOfMedia:1; 1450 u_int8_t FileMark:1; 1451 u_int8_t Information[4]; 1452 u_int8_t AdditionalSenseLength; 1453 u_int8_t CommandSpecificInformation[4]; 1454 u_int8_t AdditionalSenseCode; 1455 u_int8_t AdditionalSenseCodeQualifier; 1456 u_int8_t FieldReplaceableUnitCode; 1457 u_int8_t SenseKeySpecific[3]; 1458 }; 1459 /* 1460 ********************************** 1461 ** Peripheral Device Type definitions 1462 ********************************** 1463 */ 1464 #define SCSI_DASD 0x00 /* Direct-access Device */ 1465 #define SCSI_SEQACESS 0x01 /* Sequential-access device */ 1466 #define SCSI_PRINTER 0x02 /* Printer device */ 1467 #define SCSI_PROCESSOR 0x03 /* Processor device */ 1468 #define SCSI_WRITEONCE 0x04 /* Write-once device */ 1469 #define SCSI_CDROM 0x05 /* CD-ROM device */ 1470 #define SCSI_SCANNER 0x06 /* Scanner device */ 1471 #define SCSI_OPTICAL 0x07 /* Optical memory device */ 1472 #define SCSI_MEDCHGR 0x08 /* Medium changer device */ 1473 #define SCSI_COMM 0x09 /* Communications device */ 1474 #define SCSI_NODEV 0x1F /* Unknown or no device type */ 1475 /* 1476 ************************************************************************************************************ 1477 ** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 1478 ** 80331 PCI-to-PCI Bridge 1479 ** PCI Configuration Space 1480 ** 1481 ** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 1482 ** Programming Interface 1483 ** ======================== 1484 ** Configuration Register Address Space Groupings and Ranges 1485 ** ============================================================= 1486 ** Register Group Configuration Offset 1487 ** ------------------------------------------------------------- 1488 ** Standard PCI Configuration 00-3Fh 1489 ** ------------------------------------------------------------- 1490 ** Device Specific Registers 40-A7h 1491 ** ------------------------------------------------------------- 1492 ** Reserved A8-CBh 1493 ** ------------------------------------------------------------- 1494 ** Enhanced Capability List CC-FFh 1495 ** ========================================================================================================== 1496 ** Standard PCI [Type 1] Configuration Space Address Map 1497 ** ********************************************************************************************************** 1498 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 1499 ** ---------------------------------------------------------------------------------------------------------- 1500 ** | Device ID | Vendor ID | 00h 1501 ** ---------------------------------------------------------------------------------------------------------- 1502 ** | Primary Status | Primary Command | 04h 1503 ** ---------------------------------------------------------------------------------------------------------- 1504 ** | Class Code | RevID | 08h 1505 ** ---------------------------------------------------------------------------------------------------------- 1506 ** | reserved | Header Type | Primary MLT | Primary CLS | 0Ch 1507 ** ---------------------------------------------------------------------------------------------------------- 1508 ** | Reserved | 10h 1509 ** ---------------------------------------------------------------------------------------------------------- 1510 ** | Reserved | 14h 1511 ** ---------------------------------------------------------------------------------------------------------- 1512 ** | Secondary MLT | Subordinate Bus Number | Secondary Bus Number | Primary Bus Number | 18h 1513 ** ---------------------------------------------------------------------------------------------------------- 1514 ** | Secondary Status | I/O Limit | I/O Base | 1Ch 1515 ** ---------------------------------------------------------------------------------------------------------- 1516 ** | Non-prefetchable Memory Limit Address | Non-prefetchable Memory Base Address | 20h 1517 ** ---------------------------------------------------------------------------------------------------------- 1518 ** | Prefetchable Memory Limit Address | Prefetchable Memory Base Address | 24h 1519 ** ---------------------------------------------------------------------------------------------------------- 1520 ** | Prefetchable Memory Base Address Upper 32 Bits | 28h 1521 ** ---------------------------------------------------------------------------------------------------------- 1522 ** | Prefetchable Memory Limit Address Upper 32 Bits | 2Ch 1523 ** ---------------------------------------------------------------------------------------------------------- 1524 ** | I/O Limit Upper 16 Bits | I/O Base Upper 16 | 30h 1525 ** ---------------------------------------------------------------------------------------------------------- 1526 ** | Reserved | Capabilities Pointer | 34h 1527 ** ---------------------------------------------------------------------------------------------------------- 1528 ** | Reserved | 38h 1529 ** ---------------------------------------------------------------------------------------------------------- 1530 ** | Bridge Control | Primary Interrupt Pin | Primary Interrupt Line | 3Ch 1531 **============================================================================================================= 1532 */ 1533 /* 1534 **============================================================================================================= 1535 ** 0x03-0x00 : 1536 ** Bit Default Description 1537 **31:16 0335h Device ID (DID): Indicates the unique device ID that is assigned to bridge by the PCI SIG. 1538 ** ID is unique per product speed as indicated. 1539 **15:00 8086h Vendor ID (VID): 16-bit field which indicates that Intel is the vendor. 1540 **============================================================================================================= 1541 */ 1542 #define ARCMSR_PCI2PCI_VENDORID_REG 0x00 /*word*/ 1543 #define ARCMSR_PCI2PCI_DEVICEID_REG 0x02 /*word*/ 1544 /* 1545 **============================================================================== 1546 ** 0x05-0x04 : command register 1547 ** Bit Default Description 1548 **15:11 00h Reserved 1549 ** 10 0 Interrupt Disable: Disables/Enables the generation of Interrupts on the primary bus. 1550 ** The bridge does not support interrupts. 1551 ** 09 0 FB2B Enable: Enables/Disables the generation of fast back to back 1552 ** transactions on the primary bus. 1553 ** The bridge does not generate fast back to back 1554 ** transactions on the primary bus. 1555 ** 08 0 SERR# Enable (SEE): Enables primary bus SERR# assertions. 1556 ** 0=The bridge does not assert P_SERR#. 1557 ** 1=The bridge may assert P_SERR#, subject to other programmable criteria. 1558 ** 07 0 Wait Cycle Control (WCC): Always returns 0bzero indicating 1559 ** that bridge does not perform address or data stepping, 1560 ** 06 0 Parity Error Response (PER): Controls bridge response to a detected primary bus parity error. 1561 ** 0=When a data parity error is detected bridge does not assert S_PERR#. 1562 ** Also bridge does not assert P_SERR# in response to 1563 ** a detected address or attribute parity error. 1564 ** 1=When a data parity error is detected bridge asserts S_PERR#. 1565 ** The bridge also asserts P_SERR# 1566 ** (when enabled globally via bit(8) of this register) 1567 ** in response to a detected address or attribute parity error. 1568 ** 05 0 VGA Palette Snoop Enable (VGA_PSE): Controls bridge response to VGA-compatible palette write transactions. 1569 ** VGA palette write transactions are I/O transactions 1570 ** whose address bits are: P_AD[9:0] equal to 3C6h, 3C8h or 3C9h 1571 ** P_AD[15:10] are not decoded (i.e. aliases are claimed), 1572 ** or are fully decoding 1573 ** (i.e., must be all 0's depending upon the VGA 1574 ** aliasing bit in the Bridge Control Register, offset 3Eh. 1575 ** P_AD[31:16] equal to 0000h 1576 ** 0=The bridge ignores VGA palette write transactions, 1577 ** unless decoded by the standard I/O address range window. 1578 ** 1=The bridge responds to VGA palette write transactions 1579 ** with medium DEVSEL# timing and forwards them to the secondary bus. 1580 ** 04 0 Memory Write and Invalidate Enable (MWIE): The bridge does not promote MW transactions to MWI transactions. 1581 ** MWI transactions targeting resources on the opposite side of the bridge, 1582 ** however, are forwarded as MWI transactions. 1583 ** 03 0 Special Cycle Enable (SCE): The bridge ignores special cycle transactions. 1584 ** This bit is read only and always returns 0 when read 1585 ** 02 0 Bus Master Enable (BME): Enables bridge to initiate memory and I/O transactions on the primary interface. 1586 ** Initiation of configuration transactions is not affected by the state of this bit. 1587 ** 0=The bridge does not initiate memory or I/O transactions on the primary interface. 1588 ** 1=The bridge is enabled to function as an initiator on the primary interface. 1589 ** 01 0 Memory Space Enable (MSE): Controls target response to memory transactions on the primary interface. 1590 ** 0=The bridge target response to memory transactions on the primary interface is disabled. 1591 ** 1=The bridge target response to memory transactions on the primary interface is enabled. 1592 ** 00 0 I/O Space Enable (IOSE): Controls target response to I/O transactions on the primary interface. 1593 ** 0=The bridge target response to I/O transactions on the primary interface is disabled. 1594 ** 1=The bridge target response to I/O transactions on the primary interface is enabled. 1595 **============================================================================== 1596 */ 1597 #define ARCMSR_PCI2PCI_PRIMARY_COMMAND_REG 0x04 /*word*/ 1598 #define PCI_DISABLE_INTERRUPT 0x0400 1599 /* 1600 **============================================================================== 1601 ** 0x07-0x06 : status register 1602 ** Bit Default Description 1603 ** 15 0 Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address, 1604 ** attribute or data parity error. 1605 ** This bit is set regardless of the state of the PER bit in the command register. 1606 ** 14 0 Signaled System Error: The bridge sets this bit to a 1b whenever it asserts SERR# on the primary bus. 1607 ** 13 0 Received Master Abort: The bridge sets this bit to a 1b when, 1608 ** acting as the initiator on the primary bus, 1609 ** its transaction (with the exception of special cycles) 1610 ** has been terminated with a Master Abort. 1611 ** 12 0 Received Target Abort: The bridge sets this bit to a 1b when, 1612 ** acting as the initiator on the primary bus, 1613 ** its transaction has been terminated with a Target Abort. 1614 ** 11 0 Signaled Target Abort: The bridge sets this bit to a 1b when it, 1615 ** as the target of a transaction, terminates it with a Target Abort. 1616 ** In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code. 1617 ** 10:09 01 DEVSEL# Timing: Indicates slowest response to a non-configuration command on the primary interface. 1618 ** Returns ��01b�� when read, indicating that bridge responds no slower than with medium timing. 1619 ** 08 0 Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true: 1620 ** The bridge is the current master on the primary bus 1621 ** S_PERR# is detected asserted or is asserted by bridge 1622 ** The Parity Error Response bit is set in the Command register 1623 ** 07 1 Fast Back to Back Capable: Returns a 1b when read indicating that bridge 1624 ** is able to respond to fast back to back transactions on its primary interface. 1625 ** 06 0 Reserved 1626 ** 05 1 66 MHz Capable Indication: Returns a 1b when read indicating that bridge primary interface is 66 MHz capable. 1627 ** 1 = 1628 ** 04 1 Capabilities List Enable: Returns 1b when read indicating that bridge supports PCI standard enhanced capabilities. 1629 ** Offset 34h (Capability Pointer register) 1630 ** provides the offset for the first entry 1631 ** in the linked list of enhanced capabilities. 1632 ** 03 0 Interrupt Status: Reflects the state of the interrupt in the device/function. 1633 ** The bridge does not support interrupts. 1634 ** 02:00 000 Reserved 1635 **============================================================================== 1636 */ 1637 #define ARCMSR_PCI2PCI_PRIMARY_STATUS_REG 0x06 /*word: 06,07 */ 1638 #define ARCMSR_ADAP_66MHZ 0x20 1639 /* 1640 **============================================================================== 1641 ** 0x08 : revision ID 1642 ** Bit Default Description 1643 ** 07:00 00000000 Revision ID (RID): '00h' indicating bridge A-0 stepping. 1644 **============================================================================== 1645 */ 1646 #define ARCMSR_PCI2PCI_REVISIONID_REG 0x08 /*byte*/ 1647 /* 1648 **============================================================================== 1649 ** 0x0b-0x09 : 0180_00 (class code 1,native pci mode ) 1650 ** Bit Default Description 1651 ** 23:16 06h Base Class Code (BCC): Indicates that this is a bridge device. 1652 ** 15:08 04h Sub Class Code (SCC): Indicates this is of type PCI-to-PCI bridge. 1653 ** 07:00 00h Programming Interface (PIF): Indicates that this is standard (non-subtractive) PCI-PCI bridge. 1654 **============================================================================== 1655 */ 1656 #define ARCMSR_PCI2PCI_CLASSCODE_REG 0x09 /*3bytes*/ 1657 /* 1658 **============================================================================== 1659 ** 0x0c : cache line size 1660 ** Bit Default Description 1661 ** 07:00 00h Cache Line Size (CLS): Designates the cache line size in 32-bit dword units. 1662 ** The contents of this register are factored into 1663 ** internal policy decisions associated with memory read prefetching, 1664 ** and the promotion of Memory Write transactions to MWI transactions. 1665 ** Valid cache line sizes are 8 and 16 dwords. 1666 ** When the cache line size is set to an invalid value, 1667 ** bridge behaves as though the cache line size was set to 00h. 1668 **============================================================================== 1669 */ 1670 #define ARCMSR_PCI2PCI_PRIMARY_CACHELINESIZE_REG 0x0C /*byte*/ 1671 /* 1672 **============================================================================== 1673 ** 0x0d : latency timer (number of pci clock 00-ff ) 1674 ** Bit Default Description 1675 ** Primary Latency Timer (PTV): 1676 ** 07:00 00h (Conventional PCI) Conventional PCI Mode: Primary bus Master latency timer. Indicates the number of PCI clock cycles, 1677 ** referenced from the assertion of FRAME# to the expiration of the timer, 1678 ** when bridge may continue as master of the current transaction. All bits are writable, 1679 ** resulting in a granularity of 1 PCI clock cycle. 1680 ** When the timer expires (i.e., equals 00h) 1681 ** bridge relinquishes the bus after the first data transfer 1682 ** when its PCI bus grant has been deasserted. 1683 ** or 40h (PCI-X) PCI-X Mode: Primary bus Master latency timer. 1684 ** Indicates the number of PCI clock cycles, 1685 ** referenced from the assertion of FRAME# to the expiration of the timer, 1686 ** when bridge may continue as master of the current transaction. 1687 ** All bits are writable, resulting in a granularity of 1 PCI clock cycle. 1688 ** When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB. 1689 ** (Except in the case where MLT expires within 3 data phases 1690 ** of an ADB.In this case bridge continues on 1691 ** until it reaches the next ADB before relinquishing the bus.) 1692 **============================================================================== 1693 */ 1694 #define ARCMSR_PCI2PCI_PRIMARY_LATENCYTIMER_REG 0x0D /*byte*/ 1695 /* 1696 **============================================================================== 1697 ** 0x0e : (header type,single function ) 1698 ** Bit Default Description 1699 ** 07 0 Multi-function device (MVD): 80331 is a single-function device. 1700 ** 06:00 01h Header Type (HTYPE): Defines the layout of addresses 10h through 3Fh in configuration space. 1701 ** Returns ��01h�� when read indicating 1702 ** that the register layout conforms to the standard PCI-to-PCI bridge layout. 1703 **============================================================================== 1704 */ 1705 #define ARCMSR_PCI2PCI_HEADERTYPE_REG 0x0E /*byte*/ 1706 /* 1707 **============================================================================== 1708 ** 0x0f : 1709 **============================================================================== 1710 */ 1711 /* 1712 **============================================================================== 1713 ** 0x13-0x10 : 1714 ** PCI CFG Base Address #0 (0x10) 1715 **============================================================================== 1716 */ 1717 /* 1718 **============================================================================== 1719 ** 0x17-0x14 : 1720 ** PCI CFG Base Address #1 (0x14) 1721 **============================================================================== 1722 */ 1723 /* 1724 **============================================================================== 1725 ** 0x1b-0x18 : 1726 ** PCI CFG Base Address #2 (0x18) 1727 **-----------------0x1A,0x19,0x18--Bus Number Register - BNR 1728 ** Bit Default Description 1729 ** 23:16 00h Subordinate Bus Number (SBBN): Indicates the highest PCI bus number below this bridge. 1730 ** Any Type 1 configuration cycle 1731 ** on the primary bus whose bus number is greater than the secondary bus number, 1732 ** and less than or equal to the subordinate bus number 1733 ** is forwarded unaltered as a Type 1 configuration cycle on the secondary PCI bus. 1734 ** 15:08 00h Secondary Bus Number (SCBN): Indicates the bus number of PCI to which the secondary interface is connected. 1735 ** Any Type 1 configuration cycle matching this bus number 1736 ** is translated to a Type 0 configuration cycle (or a Special Cycle) 1737 ** before being executed on bridge's secondary PCI bus. 1738 ** 07:00 00h Primary Bus Number (PBN): Indicates bridge primary bus number. 1739 ** Any Type 1 configuration cycle on the primary interface 1740 ** with a bus number that is less than the contents 1741 ** of this register field does not be claimed by bridge. 1742 **-----------------0x1B--Secondary Latency Timer Register - SLTR 1743 ** Bit Default Description 1744 ** Secondary Latency Timer (STV): 1745 ** 07:00 00h (Conventional PCI) Conventional PCI Mode: Secondary bus Master latency timer. 1746 ** Indicates the number of PCI clock cycles, 1747 ** referenced from the assertion of FRAME# to the expiration of the timer, 1748 ** when bridge may continue as master of the current transaction. All bits are writable, 1749 ** resulting in a granularity of 1 PCI clock cycle. 1750 ** When the timer expires (i.e., equals 00h) 1751 ** bridge relinquishes the bus after the first data transfer 1752 ** when its PCI bus grant has been deasserted. 1753 ** or 40h (PCI-X) PCI-X Mode: Secondary bus Master latency timer. 1754 ** Indicates the number of PCI clock cycles,referenced from the assertion of FRAME# 1755 ** to the expiration of the timer, 1756 ** when bridge may continue as master of the current transaction. All bits are writable, 1757 ** resulting in a granularity of 1 PCI clock cycle. 1758 ** When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB. 1759 ** (Except in the case where MLT expires within 3 data phases of an ADB. 1760 ** In this case bridge continues on until it reaches the next ADB 1761 ** before relinquishing the bus) 1762 **============================================================================== 1763 */ 1764 #define ARCMSR_PCI2PCI_PRIMARY_BUSNUMBER_REG 0x18 /*3byte 0x1A,0x19,0x18*/ 1765 #define ARCMSR_PCI2PCI_SECONDARY_BUSNUMBER_REG 0x19 /*byte*/ 1766 #define ARCMSR_PCI2PCI_SUBORDINATE_BUSNUMBER_REG 0x1A /*byte*/ 1767 #define ARCMSR_PCI2PCI_SECONDARY_LATENCYTIMER_REG 0x1B /*byte*/ 1768 /* 1769 **============================================================================== 1770 ** 0x1f-0x1c : 1771 ** PCI CFG Base Address #3 (0x1C) 1772 **-----------------0x1D,0x1C--I/O Base and Limit Register - IOBL 1773 ** Bit Default Description 1774 ** 15:12 0h I/O Limit Address Bits [15:12]: Defines the top address of an address range to 1775 ** determine when to forward I/O transactions from one interface to the other. 1776 ** These bits correspond to address lines 15:12 for 4KB alignment. 1777 ** Bits 11:0 are assumed to be FFFh. 1778 ** 11:08 1h I/O Limit Addressing Capability: This field is hard-wired to 1h, indicating support 32-bit I/O addressing. 1779 ** 07:04 0h I/O Base Address Bits [15:12]: Defines the bottom address of 1780 ** an address range to determine when to forward I/O transactions 1781 ** from one interface to the other. 1782 ** These bits correspond to address lines 15:12 for 4KB alignment. 1783 ** Bits 11:0 are assumed to be 000h. 1784 ** 03:00 1h I/O Base Addressing Capability: This is hard-wired to 1h, indicating support for 32-bit I/O addressing. 1785 **-----------------0x1F,0x1E--Secondary Status Register - SSR 1786 ** Bit Default Description 1787 ** 15 0b Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address, 1788 ** attribute or data parity error on its secondary interface. 1789 ** 14 0b Received System Error: The bridge sets this bit when it samples SERR# asserted on its secondary bus interface. 1790 ** 13 0b Received Master Abort: The bridge sets this bit to a 1b when, 1791 ** acting as the initiator on the secondary bus, 1792 ** it's transaction (with the exception of special cycles) 1793 ** has been terminated with a Master Abort. 1794 ** 12 0b Received Target Abort: The bridge sets this bit to a 1b when, 1795 ** acting as the initiator on the secondary bus, 1796 ** it's transaction has been terminated with a Target Abort. 1797 ** 11 0b Signaled Target Abort: The bridge sets this bit to a 1b when it, 1798 ** as the target of a transaction, terminates it with a Target Abort. 1799 ** In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code. 1800 ** 10:09 01b DEVSEL# Timing: Indicates slowest response to a non-configuration command on the secondary interface. 1801 ** Returns ��01b�� when read, indicating that bridge responds no slower than with medium timing. 1802 ** 08 0b Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true: 1803 ** The bridge is the current master on the secondary bus 1804 ** S_PERR# is detected asserted or is asserted by bridge 1805 ** The Parity Error Response bit is set in the Command register 1806 ** 07 1b Fast Back-to-Back Capable (FBC): Indicates that the secondary interface of bridge can receive fast back-to-back cycles. 1807 ** 06 0b Reserved 1808 ** 05 1b 66 MHz Capable (C66): Indicates the secondary interface of the bridge is 66 MHz capable. 1809 ** 1 = 1810 ** 04:00 00h Reserved 1811 **============================================================================== 1812 */ 1813 #define ARCMSR_PCI2PCI_IO_BASE_REG 0x1C /*byte*/ 1814 #define ARCMSR_PCI2PCI_IO_LIMIT_REG 0x1D /*byte*/ 1815 #define ARCMSR_PCI2PCI_SECONDARY_STATUS_REG 0x1E /*word: 0x1F,0x1E */ 1816 /* 1817 **============================================================================== 1818 ** 0x23-0x20 : 1819 ** PCI CFG Base Address #4 (0x20) 1820 **-----------------0x23,0x22,0x21,0x20--Memory Base and Limit Register - MBL 1821 ** Bit Default Description 1822 ** 31:20 000h Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine 1823 ** the upper 1MB aligned value (exclusive) of the range. 1824 ** The incoming address must be less than or equal to this value. 1825 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0] 1826 ** are assumed to be F FFFFh. 1827 ** 19:16 0h Reserved. 1828 ** 15:04 000h Memory Base: These 12 bits are compared with bits P_AD[31:20] 1829 ** of the incoming address to determine the lower 1MB 1830 ** aligned value (inclusive) of the range. 1831 ** The incoming address must be greater than or equal to this value. 1832 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0]) 1833 ** are assumed to be 0 0000h. 1834 ** 03:00 0h Reserved. 1835 **============================================================================== 1836 */ 1837 #define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_BASE_REG 0x20 /*word: 0x21,0x20 */ 1838 #define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_LIMIT_REG 0x22 /*word: 0x23,0x22 */ 1839 /* 1840 **============================================================================== 1841 ** 0x27-0x24 : 1842 ** PCI CFG Base Address #5 (0x24) 1843 **-----------------0x27,0x26,0x25,0x24--Prefetchable Memory Base and Limit Register - PMBL 1844 ** Bit Default Description 1845 ** 31:20 000h Prefetchable Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine 1846 ** the upper 1MB aligned value (exclusive) of the range. 1847 ** The incoming address must be less than or equal to this value. 1848 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0] 1849 ** are assumed to be F FFFFh. 1850 ** 19:16 1h 64-bit Indicator: Indicates that 64-bit addressing is supported. 1851 ** 15:04 000h Prefetchable Memory Base: These 12 bits are compared with bits P_AD[31:20] 1852 ** of the incoming address to determine the lower 1MB aligned value (inclusive) 1853 ** of the range. 1854 ** The incoming address must be greater than or equal to this value. 1855 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0]) 1856 ** are assumed to be 0 0000h. 1857 ** 03:00 1h 64-bit Indicator: Indicates that 64-bit addressing is supported. 1858 **============================================================================== 1859 */ 1860 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_REG 0x24 /*word: 0x25,0x24 */ 1861 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_REG 0x26 /*word: 0x27,0x26 */ 1862 /* 1863 **============================================================================== 1864 ** 0x2b-0x28 : 1865 ** Bit Default Description 1866 ** 31:00 00000000h Prefetchable Memory Base Upper Portion: All bits are read/writable 1867 ** bridge supports full 64-bit addressing. 1868 **============================================================================== 1869 */ 1870 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_UPPER32_REG 0x28 /*dword: 0x2b,0x2a,0x29,0x28 */ 1871 /* 1872 **============================================================================== 1873 ** 0x2f-0x2c : 1874 ** Bit Default Description 1875 ** 31:00 00000000h Prefetchable Memory Limit Upper Portion: All bits are read/writable 1876 ** bridge supports full 64-bit addressing. 1877 **============================================================================== 1878 */ 1879 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_UPPER32_REG 0x2C /*dword: 0x2f,0x2e,0x2d,0x2c */ 1880 /* 1881 **============================================================================== 1882 ** 0x33-0x30 : 1883 ** Bit Default Description 1884 ** 07:00 DCh Capabilities Pointer: Pointer to the first CAP ID entry in the capabilities list is at DCh in PCI configuration 1885 ** space. (Power Management Capability Registers) 1886 **============================================================================== 1887 */ 1888 #define ARCMSR_PCI2PCI_CAPABILITIES_POINTER_REG 0x34 /*byte*/ 1889 /* 1890 **============================================================================== 1891 ** 0x3b-0x35 : reserved 1892 **============================================================================== 1893 */ 1894 /* 1895 **============================================================================== 1896 ** 0x3d-0x3c : 1897 ** 1898 ** Bit Default Description 1899 ** 15:08 00h Interrupt Pin (PIN): Bridges do not support the generation of interrupts. 1900 ** 07:00 00h Interrupt Line (LINE): The bridge does not generate interrupts, so this is reserved as '00h'. 1901 **============================================================================== 1902 */ 1903 #define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_LINE_REG 0x3C /*byte*/ 1904 #define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_PIN_REG 0x3D /*byte*/ 1905 /* 1906 **============================================================================== 1907 ** 0x3f-0x3e : 1908 ** Bit Default Description 1909 ** 15:12 0h Reserved 1910 ** 11 0b Discard Timer SERR# Enable: Controls the generation of SERR# on the primary interface (P_SERR#) in response 1911 ** to a timer discard on either the primary or secondary interface. 1912 ** 0b=SERR# is not asserted. 1913 ** 1b=SERR# is asserted. 1914 ** 10 0b Discard Timer Status (DTS): This bit is set to a '1b' when either the primary or secondary discard timer expires. 1915 ** The delayed completion is then discarded. 1916 ** 09 0b Secondary Discard Timer (SDT): Sets the maximum number of PCI clock cycles 1917 ** that bridge waits for an initiator on the secondary bus 1918 ** to repeat a delayed transaction request. 1919 ** The counter starts when the delayed transaction completion is ready 1920 ** to be returned to the initiator. 1921 ** When the initiator has not repeated the transaction 1922 ** at least once before the counter expires,bridge 1923 ** discards the delayed transaction from its queues. 1924 ** 0b=The secondary master time-out counter is 2 15 PCI clock cycles. 1925 ** 1b=The secondary master time-out counter is 2 10 PCI clock cycles. 1926 ** 08 0b Primary Discard Timer (PDT): Sets the maximum number of PCI clock cycles 1927 ** that bridge waits for an initiator on the primary bus 1928 ** to repeat a delayed transaction request. 1929 ** The counter starts when the delayed transaction completion 1930 ** is ready to be returned to the initiator. 1931 ** When the initiator has not repeated the transaction 1932 ** at least once before the counter expires, 1933 ** bridge discards the delayed transaction from its queues. 1934 ** 0b=The primary master time-out counter is 2 15 PCI clock cycles. 1935 ** 1b=The primary master time-out counter is 2 10 PCI clock cycles. 1936 ** 07 0b Fast Back-to-Back Enable (FBE): The bridge does not initiate back to back transactions. 1937 ** 06 0b Secondary Bus Reset (SBR): 1938 ** When cleared to 0b: The bridge deasserts S_RST#, 1939 ** when it had been asserted by writing this bit to a 1b. 1940 ** When set to 1b: The bridge asserts S_RST#. 1941 ** 05 0b Master Abort Mode (MAM): Dictates bridge behavior on the initiator bus 1942 ** when a master abort termination occurs in response to 1943 ** a delayed transaction initiated by bridge on the target bus. 1944 ** 0b=The bridge asserts TRDY# in response to a non-locked delayed transaction, 1945 ** and returns FFFF FFFFh when a read. 1946 ** 1b=When the transaction had not yet been completed on the initiator bus 1947 ** (e.g.,delayed reads, or non-posted writes), 1948 ** then bridge returns a Target Abort in response to the original requester 1949 ** when it returns looking for its delayed completion on the initiator bus. 1950 ** When the transaction had completed on the initiator bus (e.g., a PMW), 1951 ** then bridge asserts P_SERR# (when enabled). 1952 ** For PCI-X transactions this bit is an enable for the assertion of P_SERR# due to a master abort 1953 ** while attempting to deliver a posted memory write on the destination bus. 1954 ** 04 0b VGA Alias Filter Enable: This bit dictates bridge behavior in conjunction with the VGA enable bit 1955 ** (also of this register), 1956 ** and the VGA Palette Snoop Enable bit (Command Register). 1957 ** When the VGA enable, or VGA Palette Snoop enable bits are on (i.e., 1b) 1958 ** the VGA Aliasing bit for the corresponding enabled functionality,: 1959 ** 0b=Ignores address bits AD[15:10] when decoding VGA I/O addresses. 1960 ** 1b=Ensures that address bits AD[15:10] equal 000000b when decoding VGA I/O addresses. 1961 ** When all VGA cycle forwarding is disabled, (i.e., VGA Enable bit =0b and VGA Palette Snoop bit =0b), 1962 ** then this bit has no impact on bridge behavior. 1963 ** 03 0b VGA Enable: Setting this bit enables address decoding 1964 ** and transaction forwarding of the following VGA transactions from the primary bus 1965 ** to the secondary bus: 1966 ** frame buffer memory addresses 000A0000h:000BFFFFh, 1967 ** VGA I/O addresses 3B0:3BBh and 3C0h:3DFh, where AD[31:16]=��0000h?** ?and AD[15:10] are either not decoded (i.e., don't cares), 1968 ** or must be ��000000b�� 1969 ** depending upon the state of the VGA Alias Filter Enable bit. (bit(4) of this register) 1970 ** I/O and Memory Enable bits must be set in the Command register 1971 ** to enable forwarding of VGA cycles. 1972 ** 02 0b ISA Enable: Setting this bit enables special handling 1973 ** for the forwarding of ISA I/O transactions that fall within the address range 1974 ** specified by the I/O Base and Limit registers, 1975 ** and are within the lowest 64Kbyte of the I/O address map 1976 ** (i.e., 0000 0000h - 0000 FFFFh). 1977 ** 0b=All I/O transactions that fall within the I/O Base 1978 ** and Limit registers' specified range are forwarded 1979 ** from primary to secondary unfiltered. 1980 ** 1b=Blocks the forwarding from primary to secondary 1981 ** of the top 768 bytes of each 1Kbyte alias. 1982 ** On the secondary the top 768 bytes of each 1K alias 1983 ** are inversely decoded and forwarded 1984 ** from secondary to primary. 1985 ** 01 0b SERR# Forward Enable: 0b=The bridge does not assert P_SERR# as a result of an S_SERR# assertion. 1986 ** 1b=The bridge asserts P_SERR# whenever S_SERR# is detected 1987 ** asserted provided the SERR# Enable bit is set (PCI Command Register bit(8)=1b). 1988 ** 00 0b Parity Error Response: This bit controls bridge response to a parity error 1989 ** that is detected on its secondary interface. 1990 ** 0b=When a data parity error is detected bridge does not assert S_PERR#. 1991 ** Also bridge does not assert P_SERR# in response to a detected address 1992 ** or attribute parity error. 1993 ** 1b=When a data parity error is detected bridge asserts S_PERR#. 1994 ** The bridge also asserts P_SERR# (when enabled globally via bit(8) 1995 ** of the Command register) 1996 ** in response to a detected address or attribute parity error. 1997 **============================================================================== 1998 */ 1999 #define ARCMSR_PCI2PCI_BRIDGE_CONTROL_REG 0x3E /*word*/ 2000 /* 2001 ************************************************************************** 2002 ** Device Specific Registers 40-A7h 2003 ************************************************************************** 2004 ** ---------------------------------------------------------------------------------------------------------- 2005 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 2006 ** ---------------------------------------------------------------------------------------------------------- 2007 ** | Bridge Control 0 | Arbiter Control/Status | Reserved | 40h 2008 ** ---------------------------------------------------------------------------------------------------------- 2009 ** | Bridge Control 2 | Bridge Control 1 | 44h 2010 ** ---------------------------------------------------------------------------------------------------------- 2011 ** | Reserved | Bridge Status | 48h 2012 ** ---------------------------------------------------------------------------------------------------------- 2013 ** | Reserved | 4Ch 2014 ** ---------------------------------------------------------------------------------------------------------- 2015 ** | Prefetch Policy | Multi-Transaction Timer | 50h 2016 ** ---------------------------------------------------------------------------------------------------------- 2017 ** | Reserved | Pre-boot Status | P_SERR# Assertion Control | 54h 2018 ** ---------------------------------------------------------------------------------------------------------- 2019 ** | Reserved | Reserved | Secondary Decode Enable | 58h 2020 ** ---------------------------------------------------------------------------------------------------------- 2021 ** | Reserved | Secondary IDSEL | 5Ch 2022 ** ---------------------------------------------------------------------------------------------------------- 2023 ** | Reserved | 5Ch 2024 ** ---------------------------------------------------------------------------------------------------------- 2025 ** | Reserved | 68h:CBh 2026 ** ---------------------------------------------------------------------------------------------------------- 2027 ************************************************************************** 2028 **============================================================================== 2029 ** 0x42-0x41: Secondary Arbiter Control/Status Register - SACSR 2030 ** Bit Default Description 2031 ** 15:12 1111b Grant Time-out Violator: This field indicates the agent that violated the Grant Time-out rule 2032 ** (PCI=16 clocks,PCI-X=6 clocks). 2033 ** Note that this field is only meaningful when: 2034 ** # Bit[11] of this register is set to 1b, 2035 ** indicating that a Grant Time-out violation had occurred. 2036 ** # bridge internal arbiter is enabled. 2037 ** Bits[15:12] Violating Agent (REQ#/GNT# pair number) 2038 ** 0000b REQ#/GNT#[0] 2039 ** 0001b REQ#/GNT#[1] 2040 ** 0010b REQ#/GNT#[2] 2041 ** 0011b REQ#/GNT#[3] 2042 ** 1111b Default Value (no violation detected) 2043 ** When bit[11] is cleared by software, this field reverts back to its default value. 2044 ** All other values are Reserved 2045 ** 11 0b Grant Time-out Occurred: When set to 1b, 2046 ** this indicates that a Grant Time-out error had occurred involving one of the secondary bus agents. 2047 ** Software clears this bit by writing a 1b to it. 2048 ** 10 0b Bus Parking Control: 0=During bus idle, bridge parks the bus on the last master to use the bus. 2049 ** 1=During bus idle, bridge parks the bus on itself. 2050 ** The bus grant is removed from the last master and internally asserted to bridge. 2051 ** 09:08 00b Reserved 2052 ** 07:00 0000 0000b Secondary Bus Arbiter Priority Configuration: The bridge secondary arbiter provides two rings of arbitration priority. 2053 ** Each bit of this field assigns its corresponding secondary 2054 ** bus master to either the high priority arbiter ring (1b) 2055 ** or to the low priority arbiter ring (0b). 2056 ** Bits [3:0] correspond to request inputs S_REQ#[3:0], respectively. 2057 ** Bit [6] corresponds to the bridge internal secondary bus request 2058 ** while Bit [7] corresponds to the SATU secondary bus request. 2059 ** Bits [5:4] are unused. 2060 ** 0b=Indicates that the master belongs to the low priority group. 2061 ** 1b=Indicates that the master belongs to the high priority group 2062 **================================================================================= 2063 ** 0x43: Bridge Control Register 0 - BCR0 2064 ** Bit Default Description 2065 ** 07 0b Fully Dynamic Queue Mode: 0=The number of Posted write transactions is limited to eight 2066 ** and the Posted Write data is limited to 4KB. 2067 ** 1=Operation in fully dynamic queue mode. The bridge enqueues up to 2068 ** 14 Posted Memory Write transactions and 8KB of posted write data. 2069 ** 06:03 0H Reserved. 2070 ** 02 0b Upstream Prefetch Disable: This bit disables bridge ability 2071 ** to perform upstream prefetch operations for Memory 2072 ** Read requests received on its secondary interface. 2073 ** This bit also controls the bridge's ability to generate advanced read commands 2074 ** when forwarding a Memory Read Block transaction request upstream from a PCI-X bus 2075 ** to a Conventional PCI bus. 2076 ** 0b=bridge treats all upstream Memory Read requests as though they target prefetchable memory. 2077 ** The use of Memory Read Line and Memory Read 2078 ** Multiple is enabled when forwarding a PCI-X Memory Read Block request 2079 ** to an upstream bus operating in Conventional PCI mode. 2080 ** 1b=bridge treats upstream PCI Memory Read requests as though 2081 ** they target non-prefetchable memory and forwards upstream PCI-X Memory 2082 ** Read Block commands as Memory Read 2083 ** when the primary bus is operating 2084 ** in Conventional PCI mode. 2085 ** NOTE: This bit does not affect bridge ability to perform read prefetching 2086 ** when the received command is Memory Read Line or Memory Read Multiple. 2087 **================================================================================= 2088 ** 0x45-0x44: Bridge Control Register 1 - BCR1 (Sheet 2 of 2) 2089 ** Bit Default Description 2090 ** 15:08 0000000b Reserved 2091 ** 07:06 00b Alias Command Mapping: This two bit field determines how bridge handles PCI-X ��Alias�� commands, 2092 ** specifically the Alias to Memory Read Block and Alias to Memory Write Block commands. 2093 ** The three options for handling these alias commands are to either pass it as is, 2094 ** re-map to the actual block memory read/write command encoding, or ignore 2095 ** the transaction forcing a Master Abort to occur on the Origination Bus. 2096 ** Bit (7:6) Handling of command 2097 ** 0 0 Re-map to Memory Read/Write Block before forwarding 2098 ** 0 1 Enqueue and forward the alias command code unaltered 2099 ** 1 0 Ignore the transaction, forcing Master Abort 2100 ** 1 1 Reserved 2101 ** 05 1b Watchdog Timers Disable: Disables or enables all 2 24 Watchdog Timers in both directions. 2102 ** The watchdog timers are used to detect prohibitively long latencies in the system. 2103 ** The watchdog timer expires when any Posted Memory Write (PMW), Delayed Request, 2104 ** or Split Requests (PCI-X mode) is not completed within 2 24 events 2105 ** (��events�� are defined as PCI Clocks when operating in PCI-X mode, 2106 ** and as the number of times being retried when operating in Conventional PCI mode) 2107 ** 0b=All 2 24 watchdog timers are enabled. 2108 ** 1b=All 2 24 watchdog timers are disabled and there is no limits to 2109 ** the number of attempts bridge makes when initiating a PMW, 2110 ** transacting a Delayed Transaction, or how long it waits for 2111 ** a split completion corresponding to one of its requests. 2112 ** 04 0b GRANT# time-out disable: This bit enables/disables the GNT# time-out mechanism. 2113 ** Grant time-out is 16 clocks for conventional PCI, and 6 clocks for PCI-X. 2114 ** 0b=The Secondary bus arbiter times out an agent 2115 ** that does not assert FRAME# within 16/6 clocks of receiving its grant, 2116 ** once the bus has gone idle. 2117 ** The time-out counter begins as soon as the bus goes idle with the new GNT# asserted. 2118 ** An infringing agent does not receive a subsequent GNT# 2119 ** until it de-asserts its REQ# for at least one clock cycle. 2120 ** 1b=GNT# time-out mechanism is disabled. 2121 ** 03 00b Reserved. 2122 ** 02 0b Secondary Discard Timer Disable: This bit enables/disables bridge secondary delayed transaction discard mechanism. 2123 ** The time out mechanism is used to ensure that initiators 2124 ** of delayed transactions return for their delayed completion data/status 2125 ** within a reasonable amount of time after it is available from bridge. 2126 ** 0b=The secondary master time-out counter is enabled 2127 ** and uses the value specified by the Secondary Discard Timer bit 2128 ** (see Bridge Control Register). 2129 ** 1b=The secondary master time-out counter is disabled. 2130 ** The bridge waits indefinitely for a secondary bus master 2131 ** to repeat a delayed transaction. 2132 ** 01 0b Primary Discard Timer Disable: This bit enables/disables bridge primary delayed transaction discard mechanism. 2133 ** The time out mechanism is used to ensure that initiators 2134 ** of delayed transactions return for their delayed completion data/status 2135 ** within a reasonable amount of time after it is available from bridge. 2136 ** 0b=The primary master time-out counter is enabled and uses the value specified 2137 ** by the Primary Discard Timer bit (see Bridge Control Register). 2138 ** 1b=The secondary master time-out counter is disabled. 2139 ** The bridge waits indefinitely for a secondary bus master 2140 ** to repeat a delayed transaction. 2141 ** 00 0b Reserved 2142 **================================================================================= 2143 ** 0x47-0x46: Bridge Control Register 2 - BCR2 2144 ** Bit Default Description 2145 ** 15:07 0000b Reserved. 2146 ** 06 0b Global Clock Out Disable (External Secondary Bus Clock Source Enable): 2147 ** This bit disables all of the secondary PCI clock outputs including 2148 ** the feedback clock S_CLKOUT. 2149 ** This means that the user is required to provide an S_CLKIN input source. 2150 ** 05:04 11 (66 MHz) Preserved. 2151 ** 01 (100 MHz) 2152 ** 00 (133 MHz) 2153 ** 03:00 Fh (100 MHz & 66 MHz) 2154 ** 7h (133 MHz) 2155 ** This 4 bit field provides individual enable/disable mask bits for each of bridge 2156 ** secondary PCI clock outputs. Some, or all secondary clock outputs (S_CLKO[3:0]) 2157 ** default to being enabled following the rising edge of P_RST#, depending on the 2158 ** frequency of the secondary bus clock: 2159 ** �E Designs with 100 MHz (or lower) Secondary PCI clock power up with 2160 ** all four S_CLKOs enabled by default. (SCLKO[3:0])�P 2161 ** �E Designs with 133 MHz Secondary PCI clock power up 2162 ** with the lower order 3 S_CLKOs enabled by default. 2163 ** (S_CLKO[2:0]) Only those SCLKs that power up enabled by can be connected 2164 ** to downstream device clock inputs. 2165 **================================================================================= 2166 ** 0x49-0x48: Bridge Status Register - BSR 2167 ** Bit Default Description 2168 ** 15 0b Upstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR# 2169 ** is conditionally asserted when the secondary discard timer expires. 2170 ** 14 0b Upstream Delayed/Split Read Watchdog Timer Expired: 2171 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# 2172 ** is conditionally asserted when bridge discards an upstream delayed read ** ** transaction request after 2 24 retries following the initial retry. 2173 ** PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 2174 ** when bridge discards an upstream split read request 2175 ** after waiting in excess of 2 24 clocks for the corresponding 2176 ** Split Completion to arrive. 2177 ** 13 0b Upstream Delayed/Split Write Watchdog Timer Expired: 2178 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# 2179 ** is conditionally asserted when bridge discards an upstream delayed write ** ** transaction request after 2 24 retries following the initial retry. 2180 ** PCI-X Mode: This bit is set to a 1b and P_SERR# 2181 ** is conditionally asserted when bridge discards an upstream split write request ** after waiting in excess of 2 24 clocks for the corresponding 2182 ** Split Completion to arrive. 2183 ** 12 0b Master Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR# 2184 ** is conditionally asserted when a Master Abort occurs as a result of an attempt, 2185 ** by bridge, to retire a PMW upstream. 2186 ** 11 0b Target Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR# 2187 ** is conditionally asserted when a Target Abort occurs as a result of an attempt, 2188 ** by bridge, to retire a PMW upstream. 2189 ** 10 0b Upstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR# 2190 ** is conditionally asserted when bridge discards an upstream PMW transaction 2191 ** after receiving 2 24 target retries from the primary bus target 2192 ** 09 0b Upstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR# 2193 ** is conditionally asserted when a data parity error is detected by bridge 2194 ** while attempting to retire a PMW upstream 2195 ** 08 0b Secondary Bus Address Parity Error: This bit is set to a 1b and P_SERR# 2196 ** is conditionally asserted when bridge detects an address parity error on 2197 ** the secondary bus. 2198 ** 07 0b Downstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR# 2199 ** is conditionally asserted when the primary bus discard timer expires. 2200 ** 06 0b Downstream Delayed/Split Read Watchdog Timer Expired: 2201 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# 2202 ** is conditionally asserted when bridge discards a downstream delayed read ** ** transaction request after receiving 2 24 target retries 2203 ** from the secondary bus target. 2204 ** PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 2205 ** when bridge discards a downstream split read request 2206 ** after waiting in excess of 2 24 clocks for the corresponding 2207 ** Split Completion to arrive. 2208 ** 05 0b Downstream Delayed Write/Split Watchdog Timer Expired: 2209 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 2210 ** when bridge discards a downstream delayed write transaction request 2211 ** after receiving 2 24 target retries from the secondary bus target. 2212 ** PCI-X Mode: This bit is set to a 1b and P_SERR# 2213 ** is conditionally asserted when bridge discards a downstream 2214 ** split write request after waiting in excess of 2 24 clocks 2215 ** for the corresponding Split Completion to arrive. 2216 ** 04 0b Master Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR# 2217 ** is conditionally asserted when a Master Abort occurs as a result of an attempt, 2218 ** by bridge, to retire a PMW downstream. 2219 ** 03 0b Target Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR# is conditionally asserted 2220 ** when a Target Abort occurs as a result of an attempt, by bridge, 2221 ** to retire a PMW downstream. 2222 ** 02 0b Downstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR# 2223 ** is conditionally asserted when bridge discards a downstream PMW transaction 2224 ** after receiving 2 24 target retries from the secondary bus target 2225 ** 01 0b Downstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR# 2226 ** is conditionally asserted when a data parity error is detected by bridge 2227 ** while attempting to retire a PMW downstream. 2228 ** 00 0b Primary Bus Address Parity Error: This bit is set to a 1b and P_SERR# is conditionally asserted 2229 ** when bridge detects an address parity error on the primary bus. 2230 **================================================================================== 2231 ** 0x51-0x50: Bridge Multi-Transaction Timer Register - BMTTR 2232 ** Bit Default Description 2233 ** 15:13 000b Reserved 2234 ** 12:10 000b GRANT# Duration: This field specifies the count (PCI clocks) 2235 ** that a secondary bus master has its grant maintained in order to enable 2236 ** multiple transactions to execute within the same arbitration cycle. 2237 ** Bit[02:00] GNT# Extended Duration 2238 ** 000 MTT Disabled (Default=no GNT# extension) 2239 ** 001 16 clocks 2240 ** 010 32 clocks 2241 ** 011 64 clocks 2242 ** 100 128 clocks 2243 ** 101 256 clocks 2244 ** 110 Invalid (treated as 000) 2245 ** 111 Invalid (treated as 000) 2246 ** 09:08 00b Reserved 2247 ** 07:00 FFh MTT Mask: This field enables/disables MTT usage for each REQ#/GNT# 2248 ** pair supported by bridge secondary arbiter. 2249 ** Bit(7) corresponds to SATU internal REQ#/GNT# pair, 2250 ** bit(6) corresponds to bridge internal REQ#/GNT# pair, 2251 ** bit(5) corresponds to REQ#/GNT#(5) pair, etc. 2252 ** When a given bit is set to 1b, its corresponding REQ#/GNT# 2253 ** pair is enabled for MTT functionality as determined by bits(12:10) of this register. 2254 ** When a given bit is cleared to 0b, its corresponding REQ#/GNT# pair is disabled from using the MTT. 2255 **================================================================================== 2256 ** 0x53-0x52: Read Prefetch Policy Register - RPPR 2257 ** Bit Default Description 2258 ** 15:13 000b ReRead_Primary Bus: 3-bit field indicating the multiplication factor 2259 ** to be used in calculating the number of bytes to prefetch from the secondary bus interface on ** subsequent PreFetch operations given that the read demands were not satisfied 2260 ** using the FirstRead parameter. 2261 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs 2262 ** Memory Read Line 1 cache lines Memory Read Multiple 2 cache lines 2263 ** 12:10 000b FirstRead_Primary Bus: 3-bit field indicating the multiplication factor to be used in calculating 2264 ** the number of bytes to prefetch from the secondary bus interface 2265 ** on the initial PreFetch operation. 2266 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs 2267 ** Memory Read Line 1 cache line Memory Read Multiple 2 cache lines 2268 ** 09:07 010b ReRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used 2269 ** in calculating the number of bytes to prefetch from the primary 2270 ** bus interface on subsequent PreFetch operations given 2271 ** that the read demands were not satisfied using 2272 ** the FirstRead parameter. 2273 ** The default value of 010b correlates to: Command Type Hardwired pre-fetch a 2274 ** mount Memory Read 3 cache lines Memory Read Line 3 cache lines 2275 ** Memory Read Multiple 6 cache lines 2276 ** 06:04 000b FirstRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used 2277 ** in calculating the number of bytes to prefetch from 2278 ** the primary bus interface on the initial PreFetch operation. 2279 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount 2280 ** Memory Read 4 DWORDs Memory Read Line 1 cache line Memory Read Multiple 2 cache lines 2281 ** 03:00 1111b Staged Prefetch Enable: This field enables/disables the FirstRead/ReRead pre-fetch 2282 ** algorithm for the secondary and the primary bus interfaces. 2283 ** Bit(3) is a ganged enable bit for REQ#/GNT#[7:3], and bits(2:0) provide individual 2284 ** enable bits for REQ#/GNT#[2:0]. 2285 ** (bit(2) is the enable bit for REQ#/GNT#[2], etc...) 2286 ** 1b: enables the staged pre-fetch feature 2287 ** 0b: disables staged pre-fetch, 2288 ** and hardwires read pre-fetch policy to the following for 2289 ** Memory Read, 2290 ** Memory Read Line, 2291 ** and Memory Read Multiple commands: 2292 ** Command Type Hardwired Pre-Fetch Amount... 2293 ** Memory Read 4 DWORDs 2294 ** Memory Read Line 1 cache line 2295 ** Memory Read Multiple 2 cache lines 2296 ** NOTE: When the starting address is not cache line aligned, bridge pre-fetches Memory Read line commands 2297 ** only to the next higher cache line boundary.For non-cache line aligned Memory Read 2298 ** Multiple commands bridge pre-fetches only to the second cache line boundary encountered. 2299 **================================================================================== 2300 ** 0x55-0x54: P_SERR# Assertion Control - SERR_CTL 2301 ** Bit Default Description 2302 ** 15 0b Upstream Delayed Transaction Discard Timer Expired: Dictates the bridge behavior 2303 ** in response to its discarding of a delayed transaction that was initiated from the primary bus. 2304 ** 0b=bridge asserts P_SERR#. 2305 ** 1b=bridge does not assert P_SERR# 2306 ** 14 0b Upstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 2307 ** 0b=bridge asserts P_SERR#. 2308 ** 1b=bridge does not assert P_SERR# 2309 ** 13 0b Upstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 2310 ** 0b=bridge asserts P_SERR#. 2311 ** 1b=bridge does not assert P_SERR# 2312 ** 12 0b Master Abort during Upstream Posted Write: Dictates bridge behavior following 2313 ** its having detected a Master Abort while attempting to retire one of its PMWs upstream. 2314 ** 0b=bridge asserts P_SERR#. 2315 ** 1b=bridge does not assert P_SERR# 2316 ** 11 0b Target Abort during Upstream Posted Write: Dictates bridge behavior following 2317 ** its having been terminated with Target Abort while attempting to retire one of its PMWs upstream. 2318 ** 0b=bridge asserts P_SERR#. 2319 ** 1b=bridge does not assert P_SERR# 2320 ** 10 0b Upstream Posted Write Data Discarded: Dictates bridge behavior in the event that 2321 ** it discards an upstream posted write transaction. 2322 ** 0b=bridge asserts P_SERR#. 2323 ** 1b=bridge does not assert P_SERR# 2324 ** 09 0b Upstream Posted Write Data Parity Error: Dictates bridge behavior 2325 ** when a data parity error is detected while attempting to retire on of its PMWs upstream. 2326 ** 0b=bridge asserts P_SERR#. 2327 ** 1b=bridge does not assert P_SERR# 2328 ** 08 0b Secondary Bus Address Parity Error: This bit dictates bridge behavior 2329 ** when it detects an address parity error on the secondary bus. 2330 ** 0b=bridge asserts P_SERR#. 2331 ** 1b=bridge does not assert P_SERR# 2332 ** 07 0b Downstream Delayed Transaction Discard Timer Expired: Dictates bridge behavior in response to 2333 ** its discarding of a delayed transaction that was initiated on the secondary bus. 2334 ** 0b=bridge asserts P_SERR#. 2335 ** 1b=bridge does not assert P_SERR# 2336 ** 06 0b Downstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 2337 ** 0b=bridge asserts P_SERR#. 2338 ** 1b=bridge does not assert P_SERR# 2339 ** 05 0b Downstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 2340 ** 0b=bridge asserts P_SERR#. 2341 ** 1b=bridge does not assert P_SERR# 2342 ** 04 0b Master Abort during Downstream Posted Write: Dictates bridge behavior following 2343 ** its having detected a Master Abort while attempting to retire one of its PMWs downstream. 2344 ** 0b=bridge asserts P_SERR#. 2345 ** 1b=bridge does not assert P_SERR# 2346 ** 03 0b Target Abort during Downstream Posted Write: Dictates bridge behavior following 2347 ** its having been terminated with Target Abort while attempting to retire one of its PMWs downstream. 2348 ** 0b=bridge asserts P_SERR#. 2349 ** 1b=bridge does not assert P_SERR# 2350 ** 02 0b Downstream Posted Write Data Discarded: Dictates bridge behavior in the event 2351 ** that it discards a downstream posted write transaction. 2352 ** 0b=bridge asserts P_SERR#. 2353 ** 1b=bridge does not assert P_SERR# 2354 ** 01 0b Downstream Posted Write Data Parity Error: Dictates bridge behavior 2355 ** when a data parity error is detected while attempting to retire on of its PMWs downstream. 2356 ** 0b=bridge asserts P_SERR#. 2357 ** 1b=bridge does not assert P_SERR# 2358 ** 00 0b Primary Bus Address Parity Error: This bit dictates bridge behavior 2359 ** when it detects an address parity error on the primary bus. 2360 ** 0b=bridge asserts P_SERR#. 2361 ** 1b=bridge does not assert P_SERR# 2362 **=============================================================================== 2363 ** 0x56: Pre-Boot Status Register - PBSR 2364 ** Bit Default Description 2365 ** 07 1 Reserved 2366 ** 06 - Reserved - value indeterminate 2367 ** 05:02 0 Reserved 2368 ** 01 Varies with External State of S_133EN at PCI Bus Reset Secondary Bus Max Frequency Setting: 2369 ** This bit reflect captured S_133EN strap, 2370 ** indicating the maximum secondary bus clock frequency when in PCI-X mode. 2371 ** Max Allowable Secondary Bus Frequency 2372 ** ** S_133EN PCI-X Mode 2373 ** ** 0 100 MHz 2374 ** ** 1 133 MH 2375 ** 00 0b Reserved 2376 **=============================================================================== 2377 ** 0x59-0x58: Secondary Decode Enable Register - SDER 2378 ** Bit Default Description 2379 ** 15:03 FFF1h Preserved. 2380 ** 02 Varies with External State of PRIVMEM at PCI Bus Reset Private Memory Space Enable - when set, 2381 ** bridge overrides its secondary inverse decode logic and not 2382 ** forward upstream any secondary bus initiated DAC Memory transactions with AD(63)=1b. 2383 ** This creates a private memory space on the Secondary PCI bus 2384 ** that allows peer-to-peer transactions. 2385 ** 01:00 10 2 Preserved. 2386 **=============================================================================== 2387 ** 0x5D-0x5C: Secondary IDSEL Select Register - SISR 2388 ** Bit Default Description 2389 ** 15:10 000000 2 Reserved. 2390 ** 09 Varies with External State of PRIVDEV at PCI Bus Reset AD25- IDSEL Disable - When this bit is set, 2391 ** AD25 is deasserted for any possible Type 1 to Type 0 conversion. 2392 ** When this bit is clear, 2393 ** AD25 is asserted when Primary addresses AD[15:11]=01001 2 during a Type 1 to Type 0 conversion. 2394 ** 08 Varies with External State of PRIVDEV at PCI Bus Reset AD24- IDSEL Disable - When this bit is set, 2395 ** AD24 is deasserted for any possible Type 1 to Type 0 conversion. 2396 ** When this bit is clear, 2397 ** AD24 is asserted when Primary addresses AD[15:11]=01000 2 during a Type 1 to Type 0 conversion. 2398 ** 07 Varies with External State of PRIVDEV at PCI Bus Reset AD23- IDSEL Disable - When this bit is set, 2399 ** AD23 is deasserted for any possible Type 1 to Type 0 conversion. 2400 ** When this bit is clear, 2401 ** AD23 is asserted when Primary addresses AD[15:11]=00111 2 during a Type 1 to Type 0 conversion. 2402 ** 06 Varies with External State of PRIVDEV at PCI Bus Reset AD22- IDSEL Disable - When this bit is set, 2403 ** AD22 is deasserted for any possible Type 1 to Type 0 conversion. 2404 ** When this bit is clear, 2405 ** AD22 is asserted when Primary addresses AD[15:11]=00110 2 during a Type 1 to Type 0 conversion. 2406 ** 05 Varies with External State of PRIVDEV at PCI Bus Reset AD21- IDSEL Disable - When this bit is set, 2407 ** AD21 is deasserted for any possible Type 1 to Type 0 conversion. 2408 ** When this bit is clear, 2409 ** AD21 is asserted when Primary addresses AD[15:11]=00101 2 during a Type 1 to Type 0 conversion. 2410 ** 04 Varies with External State of PRIVDEV at PCI Bus Reset AD20- IDSEL Disable - When this bit is set, 2411 ** AD20 is deasserted for any possible Type 1 to Type 0 conversion. 2412 ** When this bit is clear, 2413 ** AD20 is asserted when Primary addresses AD[15:11]=00100 2 during a Type 1 to Type 0 conversion. 2414 ** 03 Varies with External State of PRIVDEV at PCI Bus Reset AD19- IDSEL Disable - When this bit is set, 2415 ** AD19 is deasserted for any possible Type 1 to Type 0 conversion. 2416 ** When this bit is clear, 2417 ** AD19 is asserted when Primary addresses AD[15:11]=00011 2 during a Type 1 to Type 0 conversion. 2418 ** 02 Varies with External State of PRIVDEV at PCI Bus Reset AD18- IDSEL Disable - When this bit is set, 2419 ** AD18 is deasserted for any possible Type 1 to Type 0 conversion. 2420 ** When this bit is clear, 2421 ** AD18 is asserted when Primary addresses AD[15:11]=00010 2 during a Type 1 to Type 0 conversion. 2422 ** 01 Varies with External State of PRIVDEV at PCI Bus Reset AD17- IDSEL Disable - When this bit is set, 2423 ** AD17 is deasserted for any possible Type 1 to Type 0 conversion. 2424 ** When this bit is clear, 2425 ** AD17 is asserted when Primary addresses AD[15:11]=00001 2 during a Type 1 to Type 0 conversion. 2426 ** 00 Varies with External State of PRIVDEV at PCI Bus Reset AD16- IDSEL Disable - When this bit is set, 2427 ** AD16 is deasserted for any possible Type 1 to Type 0 conversion. 2428 ** When this bit is clear, 2429 ** AD16 is asserted when Primary addresses AD[15:11]=00000 2 during a Type 1 to Type 0 conversion. 2430 ************************************************************************** 2431 */ 2432 /* 2433 ************************************************************************** 2434 ** Reserved A8-CBh 2435 ************************************************************************** 2436 */ 2437 /* 2438 ************************************************************************** 2439 ** PCI Extended Enhanced Capabilities List CC-FFh 2440 ************************************************************************** 2441 ** ---------------------------------------------------------------------------------------------------------- 2442 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 2443 ** ---------------------------------------------------------------------------------------------------------- 2444 ** | Power Management Capabilities | Next Item Ptr | Capability ID | DCh 2445 ** ---------------------------------------------------------------------------------------------------------- 2446 ** | PM Data | PPB Support | Extensions Power Management CSR | E0h 2447 ** ---------------------------------------------------------------------------------------------------------- 2448 ** | Reserved | Reserved | Reserved | E4h 2449 ** ---------------------------------------------------------------------------------------------------------- 2450 ** | Reserved | E8h 2451 ** ---------------------------------------------------------------------------------------------------------- 2452 ** | Reserved | Reserved | Reserved | Reserved | ECh 2453 ** ---------------------------------------------------------------------------------------------------------- 2454 ** | PCI-X Secondary Status | Next Item Ptr | Capability ID | F0h 2455 ** ---------------------------------------------------------------------------------------------------------- 2456 ** | PCI-X Bridge Status | F4h 2457 ** ---------------------------------------------------------------------------------------------------------- 2458 ** | PCI-X Upstream Split Transaction Control | F8h 2459 ** ---------------------------------------------------------------------------------------------------------- 2460 ** | PCI-X Downstream Split Transaction Control | FCh 2461 ** ---------------------------------------------------------------------------------------------------------- 2462 **=============================================================================== 2463 ** 0xDC: Power Management Capabilities Identifier - PM_CAPID 2464 ** Bit Default Description 2465 ** 07:00 01h Identifier (ID): PCI SIG assigned ID for PCI-PM register block 2466 **=============================================================================== 2467 ** 0xDD: Next Item Pointer - PM_NXTP 2468 ** Bit Default Description 2469 ** 07:00 F0H Next Capabilities Pointer (PTR): The register defaults to F0H pointing to the PCI-X Extended Capability Header. 2470 **=============================================================================== 2471 ** 0xDF-0xDE: Power Management Capabilities Register - PMCR 2472 ** Bit Default Description 2473 ** 15:11 00h PME Supported (PME): PME# cannot be asserted by bridge. 2474 ** 10 0h State D2 Supported (D2): Indicates no support for state D2. No power management action in this state. 2475 ** 09 1h State D1 Supported (D1): Indicates support for state D1. No power management action in this state. 2476 ** 08:06 0h Auxiliary Current (AUXC): This 3 bit field reports the 3.3Vaux auxiliary current requirements for the PCI function. 2477 ** This returns 000b as PME# wake-up for bridge is not implemented. 2478 ** 05 0 Special Initialization Required (SINT): Special initialization is not required for bridge. 2479 ** 04:03 00 Reserved 2480 ** 02:00 010 Version (VS): Indicates that this supports PCI Bus Power Management Interface Specification, Revision 1.1. 2481 **=============================================================================== 2482 ** 0xE1-0xE0: Power Management Control / Status - Register - PMCSR 2483 ** Bit Default Description 2484 ** 15:09 00h Reserved 2485 ** 08 0b PME_Enable: This bit, when set to 1b enables bridge to assert PME#. 2486 ** Note that bridge never has occasion to assert PME# and implements this dummy R/W bit only for the purpose of working around an OS PCI-PM bug. 2487 ** 07:02 00h Reserved 2488 ** 01:00 00 Power State (PSTATE): This 2-bit field is used both to determine the current power state of 2489 ** a function and to set the Function into a new power state. 2490 ** 00 - D0 state 2491 ** 01 - D1 state 2492 ** 10 - D2 state 2493 ** 11 - D3 hot state 2494 **=============================================================================== 2495 ** 0xE2: Power Management Control / Status PCI to PCI Bridge Support - PMCSR_BSE 2496 ** Bit Default Description 2497 ** 07 0 Bus Power/Clock Control Enable (BPCC_En): Indicates that the bus power/clock control policies have been disabled. 2498 ** 06 0 B2/B3 support for D3 Hot (B2_B3#): The state of this bit determines the action that 2499 ** is to occur as a direct result of programming the function to D3 hot. 2500 ** This bit is only meaningful when bit 7 (BPCC_En) is a ��1��. 2501 ** 05:00 00h Reserved 2502 **=============================================================================== 2503 ** 0xE3: Power Management Data Register - PMDR 2504 ** Bit Default Description 2505 ** 07:00 00h Reserved 2506 **=============================================================================== 2507 ** 0xF0: PCI-X Capabilities Identifier - PX_CAPID 2508 ** Bit Default Description 2509 ** 07:00 07h Identifier (ID): Indicates this is a PCI-X capabilities list. 2510 **=============================================================================== 2511 ** 0xF1: Next Item Pointer - PX_NXTP 2512 ** Bit Default Description 2513 ** 07:00 00h Next Item Pointer: Points to the next capability in the linked list The power on default value of this 2514 ** register is 00h indicating that this is the last entry in the linked list of capabilities. 2515 **=============================================================================== 2516 ** 0xF3-0xF2: PCI-X Secondary Status - PX_SSTS 2517 ** Bit Default Description 2518 ** 15:09 00h Reserved 2519 ** 08:06 Xxx Secondary Clock Frequency (SCF): This field is set with the frequency of the secondary bus. 2520 ** The values are: 2521 ** ** BitsMax FrequencyClock Period 2522 ** ** 000PCI ModeN/A 2523 ** ** 00166 15 2524 ** ** 01010010 2525 ** ** 0111337.5 2526 ** ** 1xxreservedreserved 2527 ** ** The default value for this register is the operating frequency of the secondary bus 2528 ** 05 0b Split Request Delayed. (SRD): This bit is supposed to be set by a bridge when it cannot forward a transaction on the 2529 ** secondary bus to the primary bus because there is not enough room within the limit 2530 ** specified in the Split Transaction Commitment Limit field in the Downstream Split 2531 ** Transaction Control register. The bridge does not set this bit. 2532 ** 04 0b Split Completion Overrun (SCO): This bit is supposed to be set when a bridge terminates a Split Completion on the ** ** secondary bus with retry or Disconnect at next ADB because its buffers are full. 2533 ** The bridge does not set this bit. 2534 ** 03 0b Unexpected Split Completion (USC): This bit is set when an unexpected split completion with a requester ID 2535 ** equal to bridge secondary bus number, device number 00h, 2536 ** and function number 0 is received on the secondary interface. 2537 ** This bit is cleared by software writing a '1'. 2538 ** 02 0b Split Completion Discarded (SCD): This bit is set 2539 ** when bridge discards a split completion moving toward the secondary bus 2540 ** because the requester would not accept it. This bit cleared by software writing a '1'. 2541 ** 01 1b 133 MHz Capable: Indicates that bridge is capable of running its secondary bus at 133 MHz 2542 ** 00 1b 64-bit Device (D64): Indicates the width of the secondary bus as 64-bits. 2543 **=============================================================================== 2544 ** 0xF7-0xF6-0xf5-0xF4: PCI-X Bridge Status - PX_BSTS 2545 ** Bit Default Description 2546 ** 31:22 0 Reserved 2547 ** 21 0 Split Request Delayed (SRD): This bit does not be set by bridge. 2548 ** 20 0 Split Completion Overrun (SCO): This bit does not be set by bridge 2549 ** because bridge throttles traffic on the completion side. 2550 ** 19 0 Unexpected Split Completion (USC): The bridge sets this bit to 1b 2551 ** when it encounters a corrupted Split Completion, possibly with an ** ** inconsistent remaining byte count.Software clears 2552 ** this bit by writing a 1b to it. 2553 ** 18 0 Split Completion Discarded (SCD): The bridge sets this bit to 1b 2554 ** when it has discarded a Split Completion.Software clears this bit by ** ** writing a 1b to it. 2555 ** 17 1 133 MHz Capable: This bit indicates that the bridge primary interface is ** capable of 133 MHz operation in PCI-X mode. 2556 ** 0=The maximum operating frequency is 66 MHz. 2557 ** 1=The maximum operating frequency is 133 MHz. 2558 ** 16 Varies with the external state of P_32BITPCI# at PCI Bus Reset 64-bit Device (D64): Indicates bus width of the Primary PCI bus interface. 2559 ** 0=Primary Interface is connected as a 32-bit PCI bus. 2560 ** 1=Primary Interface is connected as a 64-bit PCI bus. 2561 ** 15:08 00h Bus Number (BNUM): This field is simply an alias to the PBN field 2562 ** of the BNUM register at offset 18h. 2563 ** Apparently it was deemed necessary reflect it here for diagnostic purposes. 2564 ** 07:03 1fh Device Number (DNUM): Indicates which IDSEL bridge consumes. 2565 ** May be updated whenever a PCI-X 2566 ** configuration write cycle that targets bridge scores a hit. 2567 ** 02:00 0h Function Number (FNUM): The bridge Function # 2568 **=============================================================================== 2569 ** 0xFB-0xFA-0xF9-0xF8: PCI-X Upstream Split Transaction Control - PX_USTC 2570 ** Bit Default Description 2571 ** 31:16 003Eh Split Transaction Limit (STL): This register indicates the size of the commitment limit in units of ADQs. 2572 ** Software is permitted to program this register to any value greater than or equal to 2573 ** the contents of the Split Transaction Capacity register. A value less than the contents 2574 ** of the Split Transaction Capacity register causes unspecified results. 2575 ** A value of 003Eh or greater enables the bridge to forward all Split Requests of any 2576 ** size regardless of the amount of buffer space available. 2577 ** 15:00 003Eh Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing 2578 ** split completions. This register controls behavior of the bridge buffers for forwarding 2579 ** Split Transactions from a primary bus requester to a secondary bus completer. 2580 ** The default value of 003Eh indicates there is available buffer space for 62 ADQs (7936 bytes). 2581 **=============================================================================== 2582 ** 0xFF-0xFE-0xFD-0xFC: PCI-X Downstream Split Transaction Control - PX_DSTC 2583 ** Bit Default Description 2584 ** 31:16 003Eh Split Transaction Limit (STL): This register indicates the size of the commitment limit in units of ADQs. 2585 ** Software is permitted to program this register to any value greater than or equal to 2586 ** the contents of the Split Transaction Capacity register. A value less than the contents 2587 ** of the Split Transaction Capacity register causes unspecified results. 2588 ** A value of 003Eh or greater enables the bridge to forward all Split Requests of any 2589 ** size regardless of the amount of buffer space available. 2590 ** 15:00 003Eh Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing 2591 ** split completions. This register controls behavior of the bridge buffers for forwarding 2592 ** Split Transactions from a primary bus requester to a secondary bus completer. 2593 ** The default value of 003Eh indicates there is available buffer space for 62 ADQs 2594 ** (7936 bytes). 2595 ************************************************************************** 2596 */ 2597 2598 /* 2599 ************************************************************************************************************************************* 2600 ** 80331 Address Translation Unit Register Definitions 2601 ** ATU Interface Configuration Header Format 2602 ** The ATU is programmed via a [Type 0] configuration command on the PCI interface. 2603 ************************************************************************************************************************************* 2604 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configuration Byte Offset 2605 **=================================================================================================================================== 2606 ** | ATU Device ID | Vendor ID | 00h 2607 ** ---------------------------------------------------------------------------------------------------------- 2608 ** | Status | Command | 04H 2609 ** ---------------------------------------------------------------------------------------------------------- 2610 ** | ATU Class Code | Revision ID | 08H 2611 ** ---------------------------------------------------------------------------------------------------------- 2612 ** | ATUBISTR | Header Type | Latency Timer | Cacheline Size | 0CH 2613 ** ---------------------------------------------------------------------------------------------------------- 2614 ** | Inbound ATU Base Address 0 | 10H 2615 ** ---------------------------------------------------------------------------------------------------------- 2616 ** | Inbound ATU Upper Base Address 0 | 14H 2617 ** ---------------------------------------------------------------------------------------------------------- 2618 ** | Inbound ATU Base Address 1 | 18H 2619 ** ---------------------------------------------------------------------------------------------------------- 2620 ** | Inbound ATU Upper Base Address 1 | 1CH 2621 ** ---------------------------------------------------------------------------------------------------------- 2622 ** | Inbound ATU Base Address 2 | 20H 2623 ** ---------------------------------------------------------------------------------------------------------- 2624 ** | Inbound ATU Upper Base Address 2 | 24H 2625 ** ---------------------------------------------------------------------------------------------------------- 2626 ** | Reserved | 28H 2627 ** ---------------------------------------------------------------------------------------------------------- 2628 ** | ATU Subsystem ID | ATU Subsystem Vendor ID | 2CH 2629 ** ---------------------------------------------------------------------------------------------------------- 2630 ** | Expansion ROM Base Address | 30H 2631 ** ---------------------------------------------------------------------------------------------------------- 2632 ** | Reserved Capabilities Pointer | 34H 2633 ** ---------------------------------------------------------------------------------------------------------- 2634 ** | Reserved | 38H 2635 ** ---------------------------------------------------------------------------------------------------------- 2636 ** | Maximum Latency | Minimum Grant | Interrupt Pin | Interrupt Line | 3CH 2637 ** ---------------------------------------------------------------------------------------------------------- 2638 ********************************************************************************************************************* 2639 */ 2640 /* 2641 *********************************************************************************** 2642 ** ATU Vendor ID Register - ATUVID 2643 ** ----------------------------------------------------------------- 2644 ** Bit Default Description 2645 ** 15:00 8086H (0x17D3) ATU Vendor ID - This is a 16-bit value assigned to Intel. 2646 ** This register, combined with the DID, uniquely identify the PCI device. 2647 ** Access type is Read/Write to allow the 80331 to configure the register as a different vendor ID 2648 ** to simulate the interface of a standard mechanism currently used by existing application software. 2649 *********************************************************************************** 2650 */ 2651 #define ARCMSR_ATU_VENDOR_ID_REG 0x00 /*word*/ 2652 /* 2653 *********************************************************************************** 2654 ** ATU Device ID Register - ATUDID 2655 ** ----------------------------------------------------------------- 2656 ** Bit Default Description 2657 ** 15:00 0336H (0x1110) ATU Device ID - This is a 16-bit value assigned to the ATU. 2658 ** This ID, combined with the VID, uniquely identify any PCI device. 2659 *********************************************************************************** 2660 */ 2661 #define ARCMSR_ATU_DEVICE_ID_REG 0x02 /*word*/ 2662 /* 2663 *********************************************************************************** 2664 ** ATU Command Register - ATUCMD 2665 ** ----------------------------------------------------------------- 2666 ** Bit Default Description 2667 ** 15:11 000000 2 Reserved 2668 ** 10 0 Interrupt Disable - This bit disables 80331 from asserting the ATU interrupt signal. 2669 ** 0=enables the assertion of interrupt signal. 2670 ** 1=disables the assertion of its interrupt signal. 2671 ** 09 0 2 Fast Back to Back Enable - When cleared, 2672 ** the ATU interface is not allowed to generate fast back-to-back cycles on its bus. 2673 ** Ignored when operating in the PCI-X mode. 2674 ** 08 0 2 SERR# Enable - When cleared, the ATU interface is not allowed to assert SERR# on the PCI interface. 2675 ** 07 1 2 Address/Data Stepping Control - Address stepping is implemented for configuration transactions. The 2676 ** ATU inserts 2 clock cycles of address stepping for Conventional Mode and 4 clock cycles 2677 ** of address stepping for PCI-X mode. 2678 ** 06 0 2 Parity Error Response - When set, the ATU takes normal action when a parity error 2679 ** is detected. When cleared, parity checking is disabled. 2680 ** 05 0 2 VGA Palette Snoop Enable - The ATU interface does not support I/O writes and therefore, 2681 ** does not perform VGA palette snooping. 2682 ** 04 0 2 Memory Write and Invalidate Enable - When set, ATU may generate MWI commands. 2683 ** When clear, ATU use Memory Write commands instead of MWI. Ignored when operating in the PCI-X mode. 2684 ** 03 0 2 Special Cycle Enable - The ATU interface does not respond to special cycle commands in any way. 2685 ** Not implemented and a reserved bit field. 2686 ** 02 0 2 Bus Master Enable - The ATU interface can act as a master on the PCI bus. 2687 ** When cleared, disables the device from generating PCI accesses. 2688 ** When set, allows the device to behave as a PCI bus master. 2689 ** When operating in the PCI-X mode, ATU initiates a split completion transaction regardless 2690 ** of the state of this bit. 2691 ** 01 0 2 Memory Enable - Controls the ATU interface��s response to PCI memory addresses. 2692 ** When cleared, the ATU interface does not respond to any memory access on the PCI bus. 2693 ** 00 0 2 I/O Space Enable - Controls the ATU interface response to I/O transactions. 2694 ** Not implemented and a reserved bit field. 2695 *********************************************************************************** 2696 */ 2697 #define ARCMSR_ATU_COMMAND_REG 0x04 /*word*/ 2698 /* 2699 *********************************************************************************** 2700 ** ATU Status Register - ATUSR (Sheet 1 of 2) 2701 ** ----------------------------------------------------------------- 2702 ** Bit Default Description 2703 ** 15 0 2 Detected Parity Error - set when a parity error is detected in data received by the ATU on the PCI bus even 2704 ** when the ATUCMD register��s Parity Error Response bit is cleared. Set under the following conditions: 2705 ** �E Write Data Parity Error when the ATU is a target (inbound write). 2706 ** �E Read Data Parity Error when the ATU is a requester (outbound read). 2707 ** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus ** ** ** (including one generated by the ATU). 2708 ** 14 0 2 SERR# Asserted - set when SERR# is asserted on the PCI bus by the ATU. 2709 ** 13 0 2 Master Abort - set when a transaction initiated by the ATU PCI master interface, ends in a Master-Abort 2710 ** or when the ATU receives a Master Abort Split Completion Error Message in PCI-X mode. 2711 ** 12 0 2 Target Abort (master) - set when a transaction initiated by the ATU PCI master interface, ends in a target 2712 ** abort or when the ATU receives a Target Abort Split Completion Error Message in PCI-X mode. 2713 ** 11 0 2 Target Abort (target) - set when the ATU interface, acting as a target, 2714 ** terminates the transaction on the PCI bus with a target abort. 2715 ** 10:09 01 2 DEVSEL# Timing - These bits are read-only and define the slowest DEVSEL# 2716 ** timing for a target device in Conventional PCI Mode regardless of the operating mode 2717 ** (except configuration accesses). 2718 ** 00 2=Fast 2719 ** 01 2=Medium 2720 ** 10 2=Slow 2721 ** 11 2=Reserved 2722 ** The ATU interface uses Medium timing. 2723 ** 08 0 2 Master Parity Error - The ATU interface sets this bit under the following conditions: 2724 ** �E The ATU asserted PERR# itself or the ATU observed PERR# asserted. 2725 ** �E And the ATU acted as the requester 2726 ** for the operation in which the error occurred. 2727 ** �E And the ATUCMD register��s Parity Error Response bit is set 2728 ** �E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message 2729 ** �E And the ATUCMD register��s Parity Error Response bit is set 2730 ** 07 1 2 (Conventional mode) 2731 ** 0 2 (PCI-X mode) 2732 ** Fast Back-to-Back - The ATU/Messaging Unit interface is capable of accepting fast back-to-back 2733 ** transactions in Conventional PCI mode when the transactions are not to the same target. Since fast 2734 ** back-to-back transactions do not exist in PCI-X mode, this bit is forced to 0 in the PCI-X mode. 2735 ** 06 0 2 UDF Supported - User Definable Features are not supported 2736 ** 05 1 2 66 MHz. Capable - 66 MHz operation is supported. 2737 ** 04 1 2 Capabilities - When set, this function implements extended capabilities. 2738 ** 03 0 Interrupt Status - reflects the state of the ATU interrupt 2739 ** when the Interrupt Disable bit in the command register is a 0. 2740 ** 0=ATU interrupt signal deasserted. 2741 ** 1=ATU interrupt signal asserted. 2742 ** NOTE: Setting the Interrupt Disable bit to a 1 has no effect on the state of this bit. Refer to 2743 ** Section 3.10.23, ��ATU Interrupt Pin Register - ATUIPR�� on page 236 for details on the ATU 2744 ** interrupt signal. 2745 ** 02:00 00000 2 Reserved. 2746 *********************************************************************************** 2747 */ 2748 #define ARCMSR_ATU_STATUS_REG 0x06 /*word*/ 2749 /* 2750 *********************************************************************************** 2751 ** ATU Revision ID Register - ATURID 2752 ** ----------------------------------------------------------------- 2753 ** Bit Default Description 2754 ** 07:00 00H ATU Revision - identifies the 80331 revision number. 2755 *********************************************************************************** 2756 */ 2757 #define ARCMSR_ATU_REVISION_REG 0x08 /*byte*/ 2758 /* 2759 *********************************************************************************** 2760 ** ATU Class Code Register - ATUCCR 2761 ** ----------------------------------------------------------------- 2762 ** Bit Default Description 2763 ** 23:16 05H Base Class - Memory Controller 2764 ** 15:08 80H Sub Class - Other Memory Controller 2765 ** 07:00 00H Programming Interface - None defined 2766 *********************************************************************************** 2767 */ 2768 #define ARCMSR_ATU_CLASS_CODE_REG 0x09 /*3bytes 0x0B,0x0A,0x09*/ 2769 /* 2770 *********************************************************************************** 2771 ** ATU Cacheline Size Register - ATUCLSR 2772 ** ----------------------------------------------------------------- 2773 ** Bit Default Description 2774 ** 07:00 00H ATU Cacheline Size - specifies the system cacheline size in DWORDs. Cacheline size is restricted to either 0, 8 or 16 DWORDs. 2775 *********************************************************************************** 2776 */ 2777 #define ARCMSR_ATU_CACHELINE_SIZE_REG 0x0C /*byte*/ 2778 /* 2779 *********************************************************************************** 2780 ** ATU Latency Timer Register - ATULT 2781 ** ----------------------------------------------------------------- 2782 ** Bit Default Description 2783 ** 07:03 00000 2 (for Conventional mode) 2784 ** 01000 2 (for PCI-X mode) 2785 ** Programmable Latency Timer - This field varies the latency timer for the interface from 0 to 248 clocks. 2786 ** The default value is 0 clocks for Conventional PCI mode, and 64 clocks for PCI-X mode. 2787 ** 02:00 000 2 Latency Timer Granularity - These Bits are read only giving a programmable granularity of 8 clocks for the latency timer. 2788 *********************************************************************************** 2789 */ 2790 #define ARCMSR_ATU_LATENCY_TIMER_REG 0x0D /*byte*/ 2791 /* 2792 *********************************************************************************** 2793 ** ATU Header Type Register - ATUHTR 2794 ** ----------------------------------------------------------------- 2795 ** Bit Default Description 2796 ** 07 0 2 Single Function/Multi-Function Device - Identifies the 80331 as a single-function PCI device. 2797 ** 06:00 000000 2 PCI Header Type - This bit field indicates the type of PCI header implemented. The ATU interface 2798 ** header conforms to PCI Local Bus Specification, Revision 2.3. 2799 *********************************************************************************** 2800 */ 2801 #define ARCMSR_ATU_HEADER_TYPE_REG 0x0E /*byte*/ 2802 /* 2803 *********************************************************************************** 2804 ** ATU BIST Register - ATUBISTR 2805 ** 2806 ** The ATU BIST Register controls the functions the Intel XScale core performs when BIST is 2807 ** initiated. This register is the interface between the host processor requesting BIST functions and 2808 ** the 80331 replying with the results from the software implementation of the BIST functionality. 2809 ** ----------------------------------------------------------------- 2810 ** Bit Default Description 2811 ** 07 0 2 BIST Capable - This bit value is always equal to the ATUCR ATU BIST Interrupt Enable bit. 2812 ** 06 0 2 Start BIST - When the ATUCR BIST Interrupt Enable bit is set: 2813 ** Setting this bit generates an interrupt to the Intel XScale core to perform a software BIST function. 2814 ** The Intel XScale core clears this bit when the BIST software has completed with the BIST results 2815 ** found in ATUBISTR register bits [3:0]. 2816 ** When the ATUCR BIST Interrupt Enable bit is clear: 2817 ** Setting this bit does not generate an interrupt to the Intel XScale core and no BIST functions is performed. 2818 ** The Intel XScale core does not clear this bit. 2819 ** 05:04 00 2 Reserved 2820 ** 03:00 0000 2 BIST Completion Code - when the ATUCR BIST Interrupt Enable bit is set and the ATUBISTR Start BIST bit is set (bit 6): 2821 ** The Intel XScale core places the results of the software BIST in these bits. 2822 ** A nonzero value indicates a device-specific error. 2823 *********************************************************************************** 2824 */ 2825 #define ARCMSR_ATU_BIST_REG 0x0F /*byte*/ 2826 2827 /* 2828 *************************************************************************************** 2829 ** ATU Base Registers and Associated Limit Registers 2830 *************************************************************************************** 2831 ** Base Address Register Limit Register Description 2832 ** Inbound ATU Base Address Register 0 Inbound ATU Limit Register 0 Defines the inbound translation window 0 from the PCI bus. 2833 ** Inbound ATU Upper Base Address Register 0 N/A Together with ATU Base Address Register 0 defines the inbound ** translation window 0 from the PCI bus for DACs. 2834 ** Inbound ATU Base Address Register 1 Inbound ATU Limit Register 1 Defines inbound window 1 from the PCI bus. 2835 ** Inbound ATU Upper Base Address Register 1 N/A Together with ATU Base Address Register 1 defines inbound window ** 1 from the PCI bus for DACs. 2836 ** Inbound ATU Base Address Register 2 Inbound ATU Limit Register 2 Defines the inbound translation window 2 from the PCI bus. 2837 ** Inbound ATU Upper Base Address Register 2 N/A Together with ATU Base Address Register 2 defines the inbound ** ** translation window 2 from the PCI bus for DACs. 2838 ** Inbound ATU Base Address Register 3 Inbound ATU Limit Register 3 Defines the inbound translation window 3 from the PCI bus. 2839 ** Inbound ATU Upper Base Address Register 3 N/A Together with ATU Base Address Register 3 defines the inbound ** ** translation window 3 from the PCI bus for DACs. 2840 ** NOTE: This is a private BAR that resides outside of the standard PCI configuration header space (offsets 00H-3FH). 2841 ** Expansion ROM Base Address Register Expansion ROM Limit Register Defines the window of addresses used by a bus master for reading ** from an Expansion ROM. 2842 **-------------------------------------------------------------------------------------- 2843 ** ATU Inbound Window 1 is not a translate window. 2844 ** The ATU does not claim any PCI accesses that fall within this range. 2845 ** This window is used to allocate host memory for use by Private Devices. 2846 ** When enabled, the ATU interrupts the Intel XScale core when either the IABAR1 register or the IAUBAR1 register is written from the PCI bus. 2847 *********************************************************************************** 2848 */ 2849 2850 /* 2851 *********************************************************************************** 2852 ** Inbound ATU Base Address Register 0 - IABAR0 2853 ** 2854 ** . The Inbound ATU Base Address Register 0 (IABAR0) together with the Inbound ATU Upper Base Address Register 0 (IAUBAR0) 2855 ** defines the block of memory addresses where the inbound translation window 0 begins. 2856 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 2857 ** . The IABAR0 and IAUBAR0 define the base address and describes the required memory block size. 2858 ** . Bits 31 through 12 of the IABAR0 is either read/write bits or read only with a value of 0 2859 ** depending on the value located within the IALR0. 2860 ** This configuration allows the IABAR0 to be programmed per PCI Local Bus Specification. 2861 ** The first 4 Kbytes of memory defined by the IABAR0, IAUBAR0 and the IALR0 is reserved for the Messaging Unit. 2862 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2863 ** Warning: 2864 ** When IALR0 is cleared prior to host configuration: 2865 ** the user should also clear the Prefetchable Indicator and the Type Indicator. 2866 ** Assuming IALR0 is not cleared: 2867 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 2868 ** when the Prefetchable Indicator is cleared prior to host configuration, 2869 ** the user should also set the Type Indicator for 32 bit addressability. 2870 ** b. For compliance to the PCI-X Addendum to the PCI Local Bus Specification, 2871 ** when the Prefetchable Indicator is set prior to host configuration, the user 2872 ** should also set the Type Indicator for 64 bit addressability. 2873 ** This is the default for IABAR0. 2874 ** ----------------------------------------------------------------- 2875 ** Bit Default Description 2876 ** 31:12 00000H Translation Base Address 0 - These bits define the actual location 2877 ** the translation function is to respond to when addressed from the PCI bus. 2878 ** 11:04 00H Reserved. 2879 ** 03 1 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 2880 ** 02:01 10 2 Type Indicator - Defines the width of the addressability for this memory window: 2881 ** 00 - Memory Window is locatable anywhere in 32 bit address space 2882 ** 10 - Memory Window is locatable anywhere in 64 bit address space 2883 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 2884 ** The ATU does not occupy I/O space, 2885 ** thus this bit must be zero. 2886 *********************************************************************************** 2887 */ 2888 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS0_REG 0x10 /*dword 0x13,0x12,0x11,0x10*/ 2889 #define ARCMSR_INBOUND_ATU_MEMORY_PREFETCHABLE 0x08 2890 #define ARCMSR_INBOUND_ATU_MEMORY_WINDOW64 0x04 2891 /* 2892 *********************************************************************************** 2893 ** Inbound ATU Upper Base Address Register 0 - IAUBAR0 2894 ** 2895 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 2896 ** Together with the Translation Base Address this register defines the actual location the translation 2897 ** function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 2898 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2899 ** Note: 2900 ** When the Type indicator of IABAR0 is set to indicate 32 bit addressability, 2901 ** the IAUBAR0 register attributes are read-only. 2902 ** ----------------------------------------------------------------- 2903 ** Bit Default Description 2904 ** 31:0 00000H Translation Upper Base Address 0 - Together with the Translation Base Address 0 these bits define the 2905 ** actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes. 2906 *********************************************************************************** 2907 */ 2908 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS0_REG 0x14 /*dword 0x17,0x16,0x15,0x14*/ 2909 /* 2910 *********************************************************************************** 2911 ** Inbound ATU Base Address Register 1 - IABAR1 2912 ** 2913 ** . The Inbound ATU Base Address Register (IABAR1) together with the Inbound ATU Upper Base Address Register 1 (IAUBAR1) 2914 ** defines the block of memory addresses where the inbound translation window 1 begins. 2915 ** . This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PCI bus transactions to this memory range. 2916 ** . The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2917 ** . When enabled, the ATU interrupts the Intel XScale core when the IABAR1 register is written from the PCI bus. 2918 ** Warning: 2919 ** When a non-zero value is not written to IALR1 prior to host configuration, 2920 ** the user should not set either the Prefetchable Indicator or the Type Indicator for 64 bit addressability. 2921 ** This is the default for IABAR1. 2922 ** Assuming a non-zero value is written to IALR1, 2923 ** the user may set the Prefetchable Indicator 2924 ** or the Type Indicator: 2925 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address 2926 ** boundary, when the Prefetchable Indicator is not set prior to host configuration, 2927 ** the user should also leave the Type Indicator set for 32 bit addressability. 2928 ** This is the default for IABAR1. 2929 ** b. when the Prefetchable Indicator is set prior to host configuration, 2930 ** the user should also set the Type Indicator for 64 bit addressability. 2931 ** ----------------------------------------------------------------- 2932 ** Bit Default Description 2933 ** 31:12 00000H Translation Base Address 1 - These bits define the actual location of window 1 on the PCI bus. 2934 ** 11:04 00H Reserved. 2935 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 2936 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 2937 ** 00 - Memory Window is locatable anywhere in 32 bit address space 2938 ** 10 - Memory Window is locatable anywhere in 64 bit address space 2939 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 2940 ** The ATU does not occupy I/O space, 2941 ** thus this bit must be zero. 2942 *********************************************************************************** 2943 */ 2944 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS1_REG 0x18 /*dword 0x1B,0x1A,0x19,0x18*/ 2945 /* 2946 *********************************************************************************** 2947 ** Inbound ATU Upper Base Address Register 1 - IAUBAR1 2948 ** 2949 ** This register contains the upper base address when locating this window for PCI addresses beyond 4 GBytes. 2950 ** Together with the IABAR1 this register defines the actual location for this memory window for addresses > 4GBytes (for DACs). 2951 ** This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PCI bus transactions to this memory range. 2952 ** The programmed value within the base address register must comply with the PCI programming 2953 ** requirements for address alignment. 2954 ** When enabled, the ATU interrupts the Intel XScale core when the IAUBAR1 register is written 2955 ** from the PCI bus. 2956 ** Note: 2957 ** When the Type indicator of IABAR1 is set to indicate 32 bit addressability, 2958 ** the IAUBAR1 register attributes are read-only. 2959 ** This is the default for IABAR1. 2960 ** ----------------------------------------------------------------- 2961 ** Bit Default Description 2962 ** 31:0 00000H Translation Upper Base Address 1 - Together with the Translation Base Address 1 2963 ** these bits define the actual location for this memory window on the PCI bus for addresses > 4GBytes. 2964 *********************************************************************************** 2965 */ 2966 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS1_REG 0x1C /*dword 0x1F,0x1E,0x1D,0x1C*/ 2967 /* 2968 *********************************************************************************** 2969 ** Inbound ATU Base Address Register 2 - IABAR2 2970 ** 2971 ** . The Inbound ATU Base Address Register 2 (IABAR2) together with the Inbound ATU Upper Base Address Register 2 (IAUBAR2) 2972 ** defines the block of memory addresses where the inbound translation window 2 begins. 2973 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 2974 ** . The IABAR2 and IAUBAR2 define the base address and describes the required memory block size 2975 ** . Bits 31 through 12 of the IABAR2 is either read/write bits or read only with a value of 0 depending on the value located within the IALR2. 2976 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2977 ** Warning: 2978 ** When a non-zero value is not written to IALR2 prior to host configuration, 2979 ** the user should not set either the Prefetchable Indicator 2980 ** or the Type Indicator for 64 bit addressability. 2981 ** This is the default for IABAR2. 2982 ** Assuming a non-zero value is written to IALR2, 2983 ** the user may set the Prefetchable Indicator 2984 ** or the Type Indicator: 2985 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 2986 ** when the Prefetchable Indicator is not set prior to host configuration, 2987 ** the user should also leave the Type Indicator set for 32 bit addressability. 2988 ** This is the default for IABAR2. 2989 ** b. when the Prefetchable Indicator is set prior to host configuration, 2990 ** the user should also set the Type Indicator for 64 bit addressability. 2991 ** ----------------------------------------------------------------- 2992 ** Bit Default Description 2993 ** 31:12 00000H Translation Base Address 2 - These bits define the actual location 2994 ** the translation function is to respond to when addressed from the PCI bus. 2995 ** 11:04 00H Reserved. 2996 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 2997 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 2998 ** 00 - Memory Window is locatable anywhere in 32 bit address space 2999 ** 10 - Memory Window is locatable anywhere in 64 bit address space 3000 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 3001 ** The ATU does not occupy I/O space, 3002 ** thus this bit must be zero. 3003 *********************************************************************************** 3004 */ 3005 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS2_REG 0x20 /*dword 0x23,0x22,0x21,0x20*/ 3006 /* 3007 *********************************************************************************** 3008 ** Inbound ATU Upper Base Address Register 2 - IAUBAR2 3009 ** 3010 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 3011 ** Together with the Translation Base Address this register defines the actual location 3012 ** the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 3013 ** The programmed value within the base address register must comply with the PCI programming 3014 ** requirements for address alignment. 3015 ** Note: 3016 ** When the Type indicator of IABAR2 is set to indicate 32 bit addressability, 3017 ** the IAUBAR2 register attributes are read-only. 3018 ** This is the default for IABAR2. 3019 ** ----------------------------------------------------------------- 3020 ** Bit Default Description 3021 ** 31:0 00000H Translation Upper Base Address 2 - Together with the Translation Base Address 2 3022 ** these bits define the actual location the translation function is to respond to 3023 ** when addressed from the PCI bus for addresses > 4GBytes. 3024 *********************************************************************************** 3025 */ 3026 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS2_REG 0x24 /*dword 0x27,0x26,0x25,0x24*/ 3027 /* 3028 *********************************************************************************** 3029 ** ATU Subsystem Vendor ID Register - ASVIR 3030 ** ----------------------------------------------------------------- 3031 ** Bit Default Description 3032 ** 15:0 0000H Subsystem Vendor ID - This register uniquely identifies the add-in board or subsystem vendor. 3033 *********************************************************************************** 3034 */ 3035 #define ARCMSR_ATU_SUBSYSTEM_VENDOR_ID_REG 0x2C /*word 0x2D,0x2C*/ 3036 /* 3037 *********************************************************************************** 3038 ** ATU Subsystem ID Register - ASIR 3039 ** ----------------------------------------------------------------- 3040 ** Bit Default Description 3041 ** 15:0 0000H Subsystem ID - uniquely identifies the add-in board or subsystem. 3042 *********************************************************************************** 3043 */ 3044 #define ARCMSR_ATU_SUBSYSTEM_ID_REG 0x2E /*word 0x2F,0x2E*/ 3045 /* 3046 *********************************************************************************** 3047 ** Expansion ROM Base Address Register -ERBAR 3048 ** ----------------------------------------------------------------- 3049 ** Bit Default Description 3050 ** 31:12 00000H Expansion ROM Base Address - These bits define the actual location 3051 ** where the Expansion ROM address window resides when addressed from the PCI bus on any 4 Kbyte boundary. 3052 ** 11:01 000H Reserved 3053 ** 00 0 2 Address Decode Enable - This bit field shows the ROM address 3054 ** decoder is enabled or disabled. When cleared, indicates the address decoder is disabled. 3055 *********************************************************************************** 3056 */ 3057 #define ARCMSR_EXPANSION_ROM_BASE_ADDRESS_REG 0x30 /*dword 0x33,0x32,0v31,0x30*/ 3058 #define ARCMSR_EXPANSION_ROM_ADDRESS_DECODE_ENABLE 0x01 3059 /* 3060 *********************************************************************************** 3061 ** ATU Capabilities Pointer Register - ATU_CAP_PTR 3062 ** ----------------------------------------------------------------- 3063 ** Bit Default Description 3064 ** 07:00 C0H Capability List Pointer - This provides an offset in this function��s configuration space 3065 ** that points to the 80331 PCl Bus Power Management extended capability. 3066 *********************************************************************************** 3067 */ 3068 #define ARCMSR_ATU_CAPABILITY_PTR_REG 0x34 /*byte*/ 3069 /* 3070 *********************************************************************************** 3071 ** Determining Block Sizes for Base Address Registers 3072 ** The required address size and type can be determined by writing ones to a base address register and 3073 ** reading from the registers. By scanning the returned value from the least-significant bit of the base 3074 ** address registers upwards, the programmer can determine the required address space size. The 3075 ** binary-weighted value of the first non-zero bit found indicates the required amount of space. 3076 ** Table 105 describes the relationship between the values read back and the byte sizes the base 3077 ** address register requires. 3078 ** As an example, assume that FFFF.FFFFH is written to the ATU Inbound Base Address Register 0 3079 ** (IABAR0) and the value read back is FFF0.0008H. Bit zero is a zero, so the device requires 3080 ** memory address space. Bit three is one, so the memory does supports prefetching. Scanning 3081 ** upwards starting at bit four, bit twenty is the first one bit found. The binary-weighted value of this 3082 ** bit is 1,048,576, indicated that the device requires 1 Mbyte of memory space. 3083 ** The ATU Base Address Registers and the Expansion ROM Base Address Register use their 3084 ** associated limit registers to enable which bits within the base address register are read/write and 3085 ** which bits are read only (0). This allows the programming of these registers in a manner similar to 3086 ** other PCI devices even though the limit is variable. 3087 ** Table 105. Memory Block Size Read Response 3088 ** Response After Writing all 1s 3089 ** to the Base Address Register 3090 ** Size 3091 ** (Bytes) 3092 ** Response After Writing all 1s 3093 ** to the Base Address Register 3094 ** Size 3095 ** (Bytes) 3096 ** FFFFFFF0H 16 FFF00000H 1 M 3097 ** FFFFFFE0H 32 FFE00000H 2 M 3098 ** FFFFFFC0H 64 FFC00000H 4 M 3099 ** FFFFFF80H 128 FF800000H 8 M 3100 ** FFFFFF00H 256 FF000000H 16 M 3101 ** FFFFFE00H 512 FE000000H 32 M 3102 ** FFFFFC00H 1K FC000000H 64 M 3103 ** FFFFF800H 2K F8000000H 128 M 3104 ** FFFFF000H 4K F0000000H 256 M 3105 ** FFFFE000H 8K E0000000H 512 M 3106 ** FFFFC000H 16K C0000000H 1 G 3107 ** FFFF8000H 32K 80000000H 2 G 3108 ** FFFF0000H 64K 3109 ** 00000000H 3110 ** Register not 3111 ** imple-mented, 3112 ** no 3113 ** address 3114 ** space 3115 ** required. 3116 ** FFFE0000H 128K 3117 ** FFFC0000H 256K 3118 ** FFF80000H 512K 3119 ** 3120 *************************************************************************************** 3121 */ 3122 3123 /* 3124 *********************************************************************************** 3125 ** ATU Interrupt Line Register - ATUILR 3126 ** ----------------------------------------------------------------- 3127 ** Bit Default Description 3128 ** 07:00 FFH Interrupt Assigned - system-assigned value identifies which system interrupt controller��s interrupt 3129 ** request line connects to the device's PCI interrupt request lines 3130 ** (as specified in the interrupt pin register). 3131 ** A value of FFH signifies ��no connection�� or ��unknown��. 3132 *********************************************************************************** 3133 */ 3134 #define ARCMSR_ATU_INTERRUPT_LINE_REG 0x3C /*byte*/ 3135 /* 3136 *********************************************************************************** 3137 ** ATU Interrupt Pin Register - ATUIPR 3138 ** ----------------------------------------------------------------- 3139 ** Bit Default Description 3140 ** 07:00 01H Interrupt Used - A value of 01H signifies that the ATU interface unit uses INTA# as the interrupt pin. 3141 *********************************************************************************** 3142 */ 3143 #define ARCMSR_ATU_INTERRUPT_PIN_REG 0x3D /*byte*/ 3144 /* 3145 *********************************************************************************** 3146 ** ATU Minimum Grant Register - ATUMGNT 3147 ** ----------------------------------------------------------------- 3148 ** Bit Default Description 3149 ** 07:00 80H This register specifies how long a burst period the device needs in increments of 8 PCI clocks. 3150 *********************************************************************************** 3151 */ 3152 #define ARCMSR_ATU_MINIMUM_GRANT_REG 0x3E /*byte*/ 3153 /* 3154 *********************************************************************************** 3155 ** ATU Maximum Latency Register - ATUMLAT 3156 ** ----------------------------------------------------------------- 3157 ** Bit Default Description 3158 ** 07:00 00H Specifies frequency (how often) the device needs to access the PCI bus 3159 ** in increments of 8 PCI clocks. A zero value indicates the device has no stringent requirement. 3160 *********************************************************************************** 3161 */ 3162 #define ARCMSR_ATU_MAXIMUM_LATENCY_REG 0x3F /*byte*/ 3163 /* 3164 *********************************************************************************** 3165 ** Inbound Address Translation 3166 ** 3167 ** The ATU allows external PCI bus initiators to directly access the internal bus. 3168 ** These PCI bus initiators can read or write 80331 memory-mapped registers or 80331 local memory space. 3169 ** The process of inbound address translation involves two steps: 3170 ** 1. Address Detection. 3171 ** �E Determine when the 32-bit PCI address (64-bit PCI address during DACs) is 3172 ** within the address windows defined for the inbound ATU. 3173 ** �E Claim the PCI transaction with medium DEVSEL# timing in the conventional PCI 3174 ** mode and with Decode A DEVSEL# timing in the PCI-X mode. 3175 ** 2. Address Translation. 3176 ** �E Translate the 32-bit PCI address (lower 32-bit PCI address during DACs) to a 32-bit 80331 internal bus address. 3177 ** The ATU uses the following registers in inbound address window 0 translation: 3178 ** �E Inbound ATU Base Address Register 0 3179 ** �E Inbound ATU Limit Register 0 3180 ** �E Inbound ATU Translate Value Register 0 3181 ** The ATU uses the following registers in inbound address window 2 translation: 3182 ** �E Inbound ATU Base Address Register 2 3183 ** �E Inbound ATU Limit Register 2 3184 ** �E Inbound ATU Translate Value Register 2 3185 ** The ATU uses the following registers in inbound address window 3 translation: 3186 ** �E Inbound ATU Base Address Register 3 3187 ** �E Inbound ATU Limit Register 3 3188 ** �E Inbound ATU Translate Value Register 3 3189 ** Note: Inbound Address window 1 is not a translate window. 3190 ** Instead, window 1 may be used to allocate host memory for Private Devices. 3191 ** Inbound Address window 3 does not reside in the standard section of the configuration header (offsets 00H - 3CH), 3192 ** thus the host BIOS does not configure window 3. 3193 ** Window 3 is intended to be used as a special window into local memory for private PCI 3194 ** agents controlled by the 80331 in conjunction with the Private Memory Space of the bridge. 3195 ** PCI-to-PCI Bridge in 80331 or 3196 ** Inbound address detection is determined from the 32-bit PCI address, 3197 ** (64-bit PCI address during DACs) the base address register and the limit register. 3198 ** In the case of DACs none of the upper 32-bits of the address is masked during address comparison. 3199 ** 3200 ** The algorithm for detection is: 3201 ** 3202 ** Equation 1. Inbound Address Detection 3203 ** When (PCI_Address [31:0] & Limit_Register[31:0]) == (Base_Register[31:0] & PCI_Address [63:32]) == Base_Register[63:32] (for DACs only) 3204 ** the PCI Address is claimed by the Inbound ATU. 3205 ** 3206 ** The incoming 32-bit PCI address (lower 32-bits of the address in case of DACs) is bitwise ANDed 3207 ** with the associated inbound limit register. 3208 ** When the result matches the base register (and upper base address matches upper PCI address in case of DACs), 3209 ** the inbound PCI address is detected as being within the inbound translation window and is claimed by the ATU. 3210 ** 3211 ** Note: The first 4 Kbytes of the ATU inbound address translation window 0 are reserved for the Messaging Unit. 3212 ** Once the transaction is claimed, the address must be translated from a PCI address to a 32-bit 3213 ** internal bus address. In case of DACs upper 32-bits of the address is simply discarded and only the 3214 ** lower 32-bits are used during address translation. 3215 ** The algorithm is: 3216 ** 3217 ** 3218 ** Equation 2. Inbound Translation 3219 ** Intel I/O processor Internal Bus Address=(PCI_Address[31:0] & ~Limit_Register[31:0]) | ATU_Translate_Value_Register[31:0]. 3220 ** 3221 ** The incoming 32-bit PCI address (lower 32-bits in case of DACs) is first bitwise ANDed with the 3222 ** bitwise inverse of the limit register. This result is bitwise ORed with the ATU Translate Value and 3223 ** the result is the internal bus address. This translation mechanism is used for all inbound memory 3224 ** read and write commands excluding inbound configuration read and writes. 3225 ** In the PCI mode for inbound memory transactions, the only burst order supported is Linear 3226 ** Incrementing. For any other burst order, the ATU signals a Disconnect after the first data phase. 3227 ** The PCI-X supports linear incrementing only, and hence above situation is not encountered in the PCI-X mode. 3228 ** example: 3229 ** Register Values 3230 ** Base_Register=3A00 0000H 3231 ** Limit_Register=FF80 0000H (8 Mbyte limit value) 3232 ** Value_Register=B100 0000H 3233 ** Inbound Translation Window ranges from 3A00 0000H to 3A7F FFFFH (8 Mbytes) 3234 ** 3235 ** Address Detection (32-bit address) 3236 ** 3237 ** PCI_Address & Limit_Register == Base_Register 3238 ** 3A45 012CH & FF80 0000H == 3A00 0000H 3239 ** 3240 ** ANS: PCI_Address is in the Inbound Translation Window 3241 ** Address Translation (to get internal bus address) 3242 ** 3243 ** IB_Address=(PCI_Address & ~Limit_Register) | Value_Reg 3244 ** IB_Address=(3A45 012CH & 007F FFFFH) | B100 0000H 3245 ** 3246 ** ANS:IB_Address=B145 012CH 3247 *********************************************************************************** 3248 */ 3249 3250 /* 3251 *********************************************************************************** 3252 ** Inbound ATU Limit Register 0 - IALR0 3253 ** 3254 ** Inbound address translation for memory window 0 occurs for data transfers occurring from the PCI 3255 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 3256 ** PCI addresses to internal bus addresses. 3257 ** The 80331 translate value register��s programmed value must be naturally aligned with the base 3258 ** address register��s programmed value. The limit register is used as a mask; thus, the lower address 3259 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 3260 ** Specification, Revision 2.3 for additional information on programming base address registers. 3261 ** Bits 31 to 12 within the IALR0 have a direct effect on the IABAR0 register, bits 31 to 12, with a 3262 ** one to one correspondence. A value of 0 in a bit within the IALR0 makes the corresponding bit 3263 ** within the IABAR0 a read only bit which always returns 0. A value of 1 in a bit within the IALR0 3264 ** makes the corresponding bit within the IABAR0 read/write from PCI. Note that a consequence of 3265 ** this programming scheme is that unless a valid value exists within the IALR0, all writes to the 3266 ** IABAR0 has no effect since a value of all zeros within the IALR0 makes the IABAR0 a read only register. 3267 ** ----------------------------------------------------------------- 3268 ** Bit Default Description 3269 ** 31:12 FF000H Inbound Translation Limit 0 - This readback value determines the memory block size required for 3270 ** inbound memory window 0 of the address translation unit. This defaults to an inbound window of 16MB. 3271 ** 11:00 000H Reserved 3272 *********************************************************************************** 3273 */ 3274 #define ARCMSR_INBOUND_ATU_LIMIT0_REG 0x40 /*dword 0x43,0x42,0x41,0x40*/ 3275 /* 3276 *********************************************************************************** 3277 ** Inbound ATU Translate Value Register 0 - IATVR0 3278 ** 3279 ** The Inbound ATU Translate Value Register 0 (IATVR0) contains the internal bus address used to 3280 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 3281 ** inbound ATU address translation. 3282 ** ----------------------------------------------------------------- 3283 ** Bit Default Description 3284 ** 31:12 FF000H Inbound ATU Translation Value 0 - This value is used to convert the PCI address to internal bus addresses. 3285 ** This value must be 64-bit aligned on the internal bus. 3286 ** The default address allows the ATU to access the internal 80331 memory-mapped registers. 3287 ** 11:00 000H Reserved 3288 *********************************************************************************** 3289 */ 3290 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE0_REG 0x44 /*dword 0x47,0x46,0x45,0x44*/ 3291 /* 3292 *********************************************************************************** 3293 ** Expansion ROM Limit Register - ERLR 3294 ** 3295 ** The Expansion ROM Limit Register (ERLR) defines the block size of addresses the ATU defines 3296 ** as Expansion ROM address space. The block size is programmed by writing a value into the ERLR. 3297 ** Bits 31 to 12 within the ERLR have a direct effect on the ERBAR register, bits 31 to 12, with a one 3298 ** to one correspondence. A value of 0 in a bit within the ERLR makes the corresponding bit within 3299 ** the ERBAR a read only bit which always returns 0. A value of 1 in a bit within the ERLR makes 3300 ** the corresponding bit within the ERBAR read/write from PCI. 3301 ** ----------------------------------------------------------------- 3302 ** Bit Default Description 3303 ** 31:12 000000H Expansion ROM Limit - Block size of memory required for the Expansion ROM translation unit. Default 3304 ** value is 0, which indicates no Expansion ROM address space and all bits within the ERBAR are read only with a value of 0. 3305 ** 11:00 000H Reserved. 3306 *********************************************************************************** 3307 */ 3308 #define ARCMSR_EXPANSION_ROM_LIMIT_REG 0x48 /*dword 0x4B,0x4A,0x49,0x48*/ 3309 /* 3310 *********************************************************************************** 3311 ** Expansion ROM Translate Value Register - ERTVR 3312 ** 3313 ** The Expansion ROM Translate Value Register contains the 80331 internal bus address which the 3314 ** ATU converts the PCI bus access. This address is driven on the internal bus as a result of the 3315 ** Expansion ROM address translation. 3316 ** ----------------------------------------------------------------- 3317 ** Bit Default Description 3318 ** 31:12 00000H Expansion ROM Translation Value - Used to convert PCI addresses to 80331 internal bus addresses 3319 ** for Expansion ROM accesses. The Expansion ROM address translation value must be word aligned on the internal bus. 3320 ** 11:00 000H Reserved 3321 *********************************************************************************** 3322 */ 3323 #define ARCMSR_EXPANSION_ROM_TRANSLATE_VALUE_REG 0x4C /*dword 0x4F,0x4E,0x4D,0x4C*/ 3324 /* 3325 *********************************************************************************** 3326 ** Inbound ATU Limit Register 1 - IALR1 3327 ** 3328 ** Bits 31 to 12 within the IALR1 have a direct effect on the IABAR1 register, bits 31 to 12, with a 3329 ** one to one correspondence. A value of 0 in a bit within the IALR1 makes the corresponding bit 3330 ** within the IABAR1 a read only bit which always returns 0. A value of 1 in a bit within the IALR1 3331 ** makes the corresponding bit within the IABAR1 read/write from PCI. Note that a consequence of 3332 ** this programming scheme is that unless a valid value exists within the IALR1, all writes to the 3333 ** IABAR1 has no effect since a value of all zeros within the IALR1 makes the IABAR1 a read only 3334 ** register. 3335 ** The inbound memory window 1 is used merely to allocate memory on the PCI bus. The ATU does 3336 ** not process any PCI bus transactions to this memory range. 3337 ** Warning: The ATU does not claim any PCI accesses that fall within the range defined by IABAR1, 3338 ** IAUBAR1, and IALR1. 3339 ** ----------------------------------------------------------------- 3340 ** Bit Default Description 3341 ** 31:12 00000H Inbound Translation Limit 1 - This readback value determines the memory block size 3342 ** required for the ATUs memory window 1. 3343 ** 11:00 000H Reserved 3344 *********************************************************************************** 3345 */ 3346 #define ARCMSR_INBOUND_ATU_LIMIT1_REG 0x50 /*dword 0x53,0x52,0x51,0x50*/ 3347 /* 3348 *********************************************************************************** 3349 ** Inbound ATU Limit Register 2 - IALR2 3350 ** 3351 ** Inbound address translation for memory window 2 occurs for data transfers occurring from the PCI 3352 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 3353 ** PCI addresses to internal bus addresses. 3354 ** The inbound translation base address for inbound window 2 is specified in Section 3.10.15. When 3355 ** determining block size requirements �X as described in Section 3.10.21 �X the translation limit 3356 ** register provides the block size requirements for the base address register. The remaining registers 3357 ** used for performing address translation are discussed in Section 3.2.1.1. 3358 ** The 80331 translate value register��s programmed value must be naturally aligned with the base 3359 ** address register��s programmed value. The limit register is used as a mask; thus, the lower address 3360 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 3361 ** Specification, Revision 2.3 for additional information on programming base address registers. 3362 ** Bits 31 to 12 within the IALR2 have a direct effect on the IABAR2 register, bits 31 to 12, with a 3363 ** one to one correspondence. A value of 0 in a bit within the IALR2 makes the corresponding bit 3364 ** within the IABAR2 a read only bit which always returns 0. A value of 1 in a bit within the IALR2 3365 ** makes the corresponding bit within the IABAR2 read/write from PCI. Note that a consequence of 3366 ** this programming scheme is that unless a valid value exists within the IALR2, all writes to the 3367 ** IABAR2 has no effect since a value of all zeros within the IALR2 makes the IABAR2 a read only 3368 ** register. 3369 ** ----------------------------------------------------------------- 3370 ** Bit Default Description 3371 ** 31:12 00000H Inbound Translation Limit 2 - This readback value determines the memory block size 3372 ** required for the ATUs memory window 2. 3373 ** 11:00 000H Reserved 3374 *********************************************************************************** 3375 */ 3376 #define ARCMSR_INBOUND_ATU_LIMIT2_REG 0x54 /*dword 0x57,0x56,0x55,0x54*/ 3377 /* 3378 *********************************************************************************** 3379 ** Inbound ATU Translate Value Register 2 - IATVR2 3380 ** 3381 ** The Inbound ATU Translate Value Register 2 (IATVR2) contains the internal bus address used to 3382 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 3383 ** inbound ATU address translation. 3384 ** ----------------------------------------------------------------- 3385 ** Bit Default Description 3386 ** 31:12 00000H Inbound ATU Translation Value 2 - This value is used to convert the PCI address to internal bus addresses. 3387 ** This value must be 64-bit aligned on the internal bus. 3388 ** The default address allows the ATU to access the internal 80331 ** ** memory-mapped registers. 3389 ** 11:00 000H Reserved 3390 *********************************************************************************** 3391 */ 3392 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE2_REG 0x58 /*dword 0x5B,0x5A,0x59,0x58*/ 3393 /* 3394 *********************************************************************************** 3395 ** Outbound I/O Window Translate Value Register - OIOWTVR 3396 ** 3397 ** The Outbound I/O Window Translate Value Register (OIOWTVR) contains the PCI I/O address 3398 ** used to convert the internal bus access to a PCI address. This address is driven on the PCI bus as a 3399 ** result of the outbound ATU address translation. 3400 ** The I/O window is from 80331 internal bus address 9000 000H to 9000 FFFFH with the fixed 3401 ** length of 64 Kbytes. 3402 ** ----------------------------------------------------------------- 3403 ** Bit Default Description 3404 ** 31:16 0000H Outbound I/O Window Translate Value - Used to convert internal bus addresses to PCI addresses. 3405 ** 15:00 0000H Reserved 3406 *********************************************************************************** 3407 */ 3408 #define ARCMSR_OUTBOUND_IO_WINDOW_TRANSLATE_VALUE_REG 0x5C /*dword 0x5F,0x5E,0x5D,0x5C*/ 3409 /* 3410 *********************************************************************************** 3411 ** Outbound Memory Window Translate Value Register 0 -OMWTVR0 3412 ** 3413 ** The Outbound Memory Window Translate Value Register 0 (OMWTVR0) contains the PCI 3414 ** address used to convert 80331 internal bus addresses for outbound transactions. This address is 3415 ** driven on the PCI bus as a result of the outbound ATU address translation. 3416 ** The memory window is from internal bus address 8000 000H to 83FF FFFFH with the fixed length 3417 ** of 64 Mbytes. 3418 ** ----------------------------------------------------------------- 3419 ** Bit Default Description 3420 ** 31:26 00H Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses. 3421 ** 25:02 00 0000H Reserved 3422 ** 01:00 00 2 Burst Order - This bit field shows the address sequence during a memory burst. 3423 ** Only linear incrementing mode is supported. 3424 *********************************************************************************** 3425 */ 3426 #define ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x60 /*dword 0x63,0x62,0x61,0x60*/ 3427 /* 3428 *********************************************************************************** 3429 ** Outbound Upper 32-bit Memory Window Translate Value Register 0 - OUMWTVR0 3430 ** 3431 ** The Outbound Upper 32-bit Memory Window Translate Value Register 0 (OUMWTVR0) defines 3432 ** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to 3433 ** directly address anywhere within the 64-bit host address space. When this register is all-zero, then 3434 ** a SAC is generated on the PCI bus. 3435 ** The memory window is from internal bus address 8000 000H to 83FF FFFFH with the fixed 3436 ** length of 64 Mbytes. 3437 ** ----------------------------------------------------------------- 3438 ** Bit Default Description 3439 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 3440 *********************************************************************************** 3441 */ 3442 #define ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x64 /*dword 0x67,0x66,0x65,0x64*/ 3443 /* 3444 *********************************************************************************** 3445 ** Outbound Memory Window Translate Value Register 1 -OMWTVR1 3446 ** 3447 ** The Outbound Memory Window Translate Value Register 1 (OMWTVR1) contains the PCI 3448 ** address used to convert 80331 internal bus addresses for outbound transactions. This address is 3449 ** driven on the PCI bus as a result of the outbound ATU address translation. 3450 ** The memory window is from internal bus address 8400 000H to 87FF FFFFH with the fixed length 3451 ** of 64 Mbytes. 3452 ** ----------------------------------------------------------------- 3453 ** Bit Default Description 3454 ** 31:26 00H Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses. 3455 ** 25:02 00 0000H Reserved 3456 ** 01:00 00 2 Burst Order - This bit field shows the address sequence during a memory burst. 3457 ** Only linear incrementing mode is supported. 3458 *********************************************************************************** 3459 */ 3460 #define ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x68 /*dword 0x6B,0x6A,0x69,0x68*/ 3461 /* 3462 *********************************************************************************** 3463 ** Outbound Upper 32-bit Memory Window Translate Value Register 1 - OUMWTVR1 3464 ** 3465 ** The Outbound Upper 32-bit Memory Window Translate Value Register 1 (OUMWTVR1) defines 3466 ** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to 3467 ** directly address anywhere within the 64-bit host address space. When this register is all-zero, then 3468 ** a SAC is generated on the PCI bus. 3469 ** The memory window is from internal bus address 8400 000H to 87FF FFFFH with the fixed length 3470 ** of 64 Mbytes. 3471 ** ----------------------------------------------------------------- 3472 ** Bit Default Description 3473 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 3474 *********************************************************************************** 3475 */ 3476 #define ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x6C /*dword 0x6F,0x6E,0x6D,0x6C*/ 3477 /* 3478 *********************************************************************************** 3479 ** Outbound Upper 32-bit Direct Window Translate Value Register - OUDWTVR 3480 ** 3481 ** The Outbound Upper 32-bit Direct Window Translate Value Register (OUDWTVR) defines the 3482 ** upper 32-bits of address used during a dual address cycle for the transactions via Direct Addressing 3483 ** Window. This enables the outbound ATU to directly address anywhere within the 64-bit host 3484 ** address space. When this register is all-zero, then a SAC is generated on the PCI bus. 3485 ** ----------------------------------------------------------------- 3486 ** Bit Default Description 3487 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 3488 *********************************************************************************** 3489 */ 3490 #define ARCMSR_OUTBOUND_UPPER32_DIRECT_WINDOW_TRANSLATE_VALUE_REG 0x78 /*dword 0x7B,0x7A,0x79,0x78*/ 3491 /* 3492 *********************************************************************************** 3493 ** ATU Configuration Register - ATUCR 3494 ** 3495 ** The ATU Configuration Register controls the outbound address translation for address translation 3496 ** unit. It also contains bits for Conventional PCI Delayed Read Command (DRC) aliasing, discard 3497 ** timer status, SERR# manual assertion, SERR# detection interrupt masking, and ATU BIST 3498 ** interrupt enabling. 3499 ** ----------------------------------------------------------------- 3500 ** Bit Default Description 3501 ** 31:20 00H Reserved 3502 ** 19 0 2 ATU DRC Alias - when set, the ATU does not distinguish read commands when attempting to match a 3503 ** current PCI read transaction with read data enqueued within the DRC buffer. When clear, a current read 3504 ** transaction must have the exact same read command as the DRR for the ATU to deliver DRC data. Not 3505 ** applicable in the PCI-X mode. 3506 ** 18 0 2 Direct Addressing Upper 2Gbytes Translation Enable - When set, 3507 ** with Direct Addressing enabled (bit 7 of the ATUCR set), 3508 ** the ATU forwards internal bus cycles with an address between 0000.0040H and 3509 ** 7FFF.FFFFH to the PCI bus with bit 31 of the address set (8000.0000H - FFFF.FFFFH). 3510 ** When clear, no translation occurs. 3511 ** 17 0 2 Reserved 3512 ** 16 0 2 SERR# Manual Assertion - when set, the ATU asserts SERR# for one clock on the PCI interface. Until 3513 ** cleared, SERR# may not be manually asserted again. Once cleared, operation proceeds as specified. 3514 ** 15 0 2 ATU Discard Timer Status - when set, one of the 4 discard timers within the ATU has expired and 3515 ** discarded the delayed completion transaction within the queue. When clear, no timer has expired. 3516 ** 14:10 00000 2 Reserved 3517 ** 09 0 2 SERR# Detected Interrupt Enable - When set, the Intel XScale core is signalled an HPI# interrupt 3518 ** when the ATU detects that SERR# was asserted. When clear, 3519 ** the Intel XScale core is not interrupted when SERR# is detected. 3520 ** 08 0 2 Direct Addressing Enable - Setting this bit enables direct outbound addressing through the ATU. 3521 ** Internal bus cycles with an address between 0000.0040H and 7FFF.FFFFH automatically forwards to 3522 ** the PCI bus with or without translation of address bit 31 based on the setting of bit 18 of 3523 ** the ATUCR. 3524 ** 07:04 0000 2 Reserved 3525 ** 03 0 2 ATU BIST Interrupt Enable - When set, enables an interrupt to the Intel XScale core when the start 3526 ** BIST bit is set in the ATUBISTR register. This bit is also reflected as the BIST Capable bit 7 3527 ** in the ATUBISTR register. 3528 ** 02 0 2 Reserved 3529 ** 01 0 2 Outbound ATU Enable - When set, enables the outbound address translation unit. 3530 ** When cleared, disables the outbound ATU. 3531 ** 00 0 2 Reserved 3532 *********************************************************************************** 3533 */ 3534 #define ARCMSR_ATU_CONFIGURATION_REG 0x80 /*dword 0x83,0x82,0x81,0x80*/ 3535 /* 3536 *********************************************************************************** 3537 ** PCI Configuration and Status Register - PCSR 3538 ** 3539 ** The PCI Configuration and Status Register has additional bits for controlling and monitoring 3540 ** various features of the PCI bus interface. 3541 ** ----------------------------------------------------------------- 3542 ** Bit Default Description 3543 ** 31:19 0000H Reserved 3544 ** 18 0 2 Detected Address or Attribute Parity Error - set when a parity error is detected during either the address 3545 ** or attribute phase of a transaction on the PCI bus even when the ATUCMD register Parity Error 3546 ** Response bit is cleared. Set under the following conditions: 3547 ** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus (including one generated by the ATU). 3548 ** 17:16 Varies with 3549 ** external state 3550 ** of DEVSEL#, 3551 ** STOP#, and 3552 ** TRDY#, 3553 ** during 3554 ** P_RST# 3555 ** PCI-X capability - These two bits define the mode of 3556 ** the PCI bus (conventional or PCI-X) as well as the 3557 ** operating frequency in the case of PCI-X mode. 3558 ** 00 - Conventional PCI mode 3559 ** 01 - PCI-X 66 3560 ** 10 - PCI-X 100 3561 ** 11 - PCI-X 133 3562 ** As defined by the PCI-X Addendum to the PCI Local Bus Specification, 3563 ** Revision 1.0a, the operating 3564 ** mode is determined by an initialization pattern on the PCI bus during 3565 ** P_RST# assertion: 3566 ** DEVSEL# STOP# TRDY# Mode 3567 ** Deasserted Deasserted Deasserted Conventional 3568 ** Deasserted Deasserted Asserted PCI-X 66 3569 ** Deasserted Asserted Deasserted PCI-X 100 3570 ** Deasserted Asserted Asserted PCI-X 133 3571 ** All other patterns are reserved. 3572 ** 15 0 2 3573 ** Outbound Transaction Queue Busy: 3574 ** 0=Outbound Transaction Queue Empty 3575 ** 1=Outbound Transaction Queue Busy 3576 ** 14 0 2 3577 ** Inbound Transaction Queue Busy: 3578 ** 0=Inbound Transaction Queue Empty 3579 ** 1=Inbound Transaction Queue Busy 3580 ** 13 0 2 Reserved. 3581 ** 12 0 2 Discard Timer Value - This bit controls the time-out value 3582 ** for the four discard timers attached to the queues holding read data. 3583 ** A value of 0 indicates the time-out value is 2 15 clocks. 3584 ** A value of 1 indicates the time-out value is 2 10 clocks. 3585 ** 11 0 2 Reserved. 3586 ** 10 Varies with 3587 ** external state 3588 ** of M66EN 3589 ** during 3590 ** P_RST# 3591 ** Bus Operating at 66 MHz - When set, the interface has been initialized to function at 66 MHz in 3592 ** Conventional PCI mode by the assertion of M66EN during bus initialization. 3593 ** When clear, the interface 3594 ** has been initialized as a 33 MHz bus. 3595 ** NOTE: When PCSR bits 17:16 are not equal to zero, then this bit is meaningless since the 80331 is operating in PCI-X mode. 3596 ** 09 0 2 Reserved 3597 ** 08 Varies with 3598 ** external state 3599 ** of REQ64# 3600 ** during 3601 ** P_RST# 3602 ** PCI Bus 64-Bit Capable - When clear, the PCI bus interface has been 3603 ** configured as 64-bit capable by 3604 ** the assertion of REQ64# on the rising edge of P_RST#. When set, 3605 ** the PCI interface is configured as 3606 ** 32-bit only. 3607 ** 07:06 00 2 Reserved. 3608 ** 05 0 2 Reset Internal Bus - This bit controls the reset of the Intel XScale core 3609 ** and all units on the internal 3610 ** bus. In addition to the internal bus initialization, 3611 ** this bit triggers the assertion of the M_RST# pin for 3612 ** initialization of registered DIMMs. When set: 3613 ** When operating in the conventional PCI mode: 3614 ** �E All current PCI transactions being mastered by the ATU completes, 3615 ** and the ATU master interfaces 3616 ** proceeds to an idle state. No additional transactions is mastered by these units 3617 ** until the internal bus reset is complete. 3618 ** �E All current transactions being slaved by the ATU on either the PCI bus 3619 ** or the internal bus 3620 ** completes, and the ATU target interfaces proceeds to an idle state. 3621 ** All future slave transactions master aborts, 3622 ** with the exception of the completion cycle for the transaction that set the Reset 3623 ** Internal Bus bit in the PCSR. 3624 ** �E When the value of the Core Processor Reset bit in the PCSR (upon P_RST# assertion) 3625 ** is set, the Intel XScale core is held in reset when the internal bus reset is complete. 3626 ** �E The ATU ignores configuration cycles, and they appears as master aborts for: 32 3627 ** Internal Bus clocks. 3628 ** �E The 80331 hardware clears this bit after the reset operation completes. 3629 ** When operating in the PCI-X mode: 3630 ** The ATU hardware responds the same as in Conventional PCI-X mode. 3631 ** However, this may create a problem in PCI-X mode for split requests in 3632 ** that there may still be an outstanding split completion that the 3633 ** ATU is either waiting to receive (Outbound Request) or initiate 3634 ** (Inbound Read Request). For a cleaner 3635 ** internal bus reset, host software can take the following steps prior 3636 ** to asserting Reset Internal bus: 3637 ** 1. Clear the Bus Master (bit 2 of the ATUCMD) and the Memory Enable (bit 1 of the ATUCMD) bits in 3638 ** the ATUCMD. This ensures that no new transactions, either outbound or inbound are enqueued. 3639 ** 2. Wait for both the Outbound (bit 15 of the PCSR) and Inbound Read (bit 14 of the PCSR) Transaction 3640 ** queue busy bits to be clear. 3641 ** 3. Set the Reset Internal Bus bit 3642 ** As a result, the ATU hardware resets the internal bus using the same logic as in conventional mode, 3643 ** however the user is now assured that the ATU no longer has any pending inbound or outbound split 3644 ** completion transactions. 3645 ** NOTE: Since the Reset Internal Bus bit is set using an inbound configuration cycle, the user is 3646 ** guaranteed that any prior configuration cycles have properly completed since there is only a one 3647 ** deep transaction queue for configuration transaction requests. The ATU sends the appropriate 3648 ** Split Write Completion Message to the Requester prior to the onset of Internal Bus Reset. 3649 ** 04 0 2 Bus Master Indicator Enable: Provides software control for the 3650 ** Bus Master Indicator signal P_BMI used 3651 ** for external RAIDIOS logic control of private devices. Only valid when operating with the bridge and 3652 ** central resource/arbiter disabled (BRG_EN =low, ARB_EN=low). 3653 ** 03 Varies with external state of PRIVDEV during 3654 ** P_RST# 3655 ** Private Device Enable - This bit indicates the state of the reset strap which enables the private device 3656 ** control mechanism within the PCI-to-PCI Bridge SISR configuration register. 3657 ** 0=Private Device control Disabled - SISR register bits default to zero 3658 ** 1=Private Device control Enabled - SISR register bits default to one 3659 ** 02 Varies with external state of RETRY during P_RST# 3660 ** Configuration Cycle Retry - When this bit is set, the PCI interface of the 80331 responds to all 3661 ** configuration cycles with a Retry condition. When clear, the 80331 responds to the appropriate 3662 ** configuration cycles. 3663 ** The default condition for this bit is based on the external state of the RETRY pin at the rising edge of 3664 ** P_RST#. When the external state of the pin is high, the bit is set. When the external state of the pin is 3665 ** low, the bit is cleared. 3666 ** 01 Varies with external state of CORE_RST# during P_RST# 3667 ** Core Processor Reset - This bit is set to its default value by the hardware when either P_RST# is 3668 ** asserted or the Reset Internal Bus bit in PCSR is set. When this bit is set, the Intel XScale core is 3669 ** being held in reset. Software cannot set this bit. Software is required to clear this bit to deassert Intel 3670 ** XScale core reset. 3671 ** The default condition for this bit is based on the external state of the CORE_RST# pin at the rising edge 3672 ** of P_RST#. When the external state of the pin is low, the bit is set. When the external state of the pin is 3673 ** high, the bit is clear. 3674 ** 00 Varies with external state of PRIVMEM during P_RST# 3675 ** Private Memory Enable - This bit indicates the state of the reset strap which enables the private device 3676 ** control mechanism within the PCI-to-PCI Bridge SDER configuration register. 3677 ** 0=Private Memory control Disabled - SDER register bit 2 default to zero 3678 ** 1=Private Memory control Enabled - SDER register bits 2 default to one 3679 *********************************************************************************** 3680 */ 3681 #define ARCMSR_PCI_CONFIGURATION_STATUS_REG 0x84 /*dword 0x87,0x86,0x85,0x84*/ 3682 /* 3683 *********************************************************************************** 3684 ** ATU Interrupt Status Register - ATUISR 3685 ** 3686 ** The ATU Interrupt Status Register is used to notify the core processor of the source of an ATU 3687 ** interrupt. In addition, this register is written to clear the source of the interrupt to the interrupt unit 3688 ** of the 80331. All bits in this register are Read/Clear. 3689 ** Bits 4:0 are a direct reflection of bits 14:11 and bit 8 (respectively) of the ATU Status Register 3690 ** (these bits are set at the same time by hardware but need to be cleared independently). Bit 7 is set 3691 ** by an error associated with the internal bus of the 80331. Bit 8 is for software BIST. The 3692 ** conditions that result in an ATU interrupt are cleared by writing a 1 to the appropriate bits in this 3693 ** register. 3694 ** Note: Bits 4:0, and bits 15 and 13:7 can result in an interrupt being driven to the Intel XScale core. 3695 ** ----------------------------------------------------------------- 3696 ** Bit Default Description 3697 ** 31:18 0000H Reserved 3698 ** 17 0 2 VPD Address Register Updated - This bit is set when a PCI bus configuration write occurs to the VPDAR 3699 ** register. Configuration register writes to the VPDAR does NOT result in bit 15 also being set. When set, 3700 ** this bit results in the assertion of the ATU Configure Register Write Interrupt. 3701 ** 16 0 2 Reserved 3702 ** 15 0 2 ATU Configuration Write - This bit is set when a PCI bus configuration write occurs to any ATU register. 3703 ** When set, this bit results in the assertion of the ATU Configure Register Write Interrupt. 3704 ** 14 0 2 ATU Inbound Memory Window 1 Base Updated - This bit is set when a PCI bus configuration write 3705 ** occurs to either the IABAR1 register or the IAUBAR1 register. Configuration register writes to these 3706 ** registers deos NOT result in bit 15 also being set. When set, this bit results in the assertion of the ATU 3707 ** Configure Register Write Interrupt. 3708 ** 13 0 2 Initiated Split Completion Error Message - This bit is set when the device initiates a Split Completion 3709 ** Message on the PCI Bus with the Split Completion Error attribute bit set. 3710 ** 12 0 2 Received Split Completion Error Message - This bit is set when the device receives a Split Completion 3711 ** Message from the PCI Bus with the Split Completion Error attribute bit set. 3712 ** 11 0 2 Power State Transition - When the Power State Field of the ATU Power Management Control/Status 3713 ** Register is written to transition the ATU function Power State from D0 to D3, D0 to D1, or D3 to D0 and 3714 ** the ATU Power State Transition Interrupt mask bit is cleared, this bit is set. 3715 ** 10 0 2 P_SERR# Asserted - set when P_SERR# is asserted on the PCI bus by the ATU. 3716 ** 09 0 2 Detected Parity Error - set when a parity error is detected on the PCI bus even when the ATUCMD 3717 ** register��s Parity Error Response bit is cleared. Set under the following conditions: 3718 ** �E Write Data Parity Error when the ATU is a target (inbound write). 3719 ** �E Read Data Parity Error when the ATU is an initiator (outbound read). 3720 ** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus. 3721 ** 08 0 2 ATU BIST Interrupt - When set, generates the ATU BIST Start Interrupt and indicates the host processor 3722 ** has set the Start BIST bit (ATUBISTR register bit 6), when the ATU BIST interrupt is enabled (ATUCR 3723 ** register bit 3). The Intel XScale core can initiate the software BIST and store the result in ATUBISTR 3724 ** register bits 3:0. 3725 ** Configuration register writes to the ATUBISTR does NOT result in bit 15 also being set or the assertion 3726 ** of the ATU Configure Register Write Interrupt. 3727 ** 07 0 2 Internal Bus Master Abort - set when a transaction initiated by the ATU internal bus initiator interface ends in a Master-abort. 3728 ** 06:05 00 2 Reserved. 3729 ** 04 0 2 P_SERR# Detected - set when P_SERR# is detected on the PCI bus by the ATU. 3730 ** 03 0 2 PCI Master Abort - set when a transaction initiated by the ATU PCI initiator interface ends in a Master-abort. 3731 ** 02 0 2 PCI Target Abort (master) - set when a transaction initiated by the ATU PCI master interface ends in a Target-abort. 3732 ** 01 0 2 PCI Target Abort (target) - set when the ATU interface, acting as a target, terminates the transaction on the PCI bus with a target abort. 3733 ** 00 0 2 PCI Master Parity Error - Master Parity Error - The ATU interface sets this bit under the following 3734 ** conditions: 3735 ** �E The ATU asserted PERR# itself or the ATU observed PERR# asserted. 3736 ** �E And the ATU acted as the requester for the operation in which the error occurred. 3737 ** �E And the ATUCMD register��s Parity Error Response bit is set 3738 ** �E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message 3739 ** �E And the ATUCMD register��s Parity Error Response bit is set 3740 *********************************************************************************** 3741 */ 3742 #define ARCMSR_ATU_INTERRUPT_STATUS_REG 0x88 /*dword 0x8B,0x8A,0x89,0x88*/ 3743 /* 3744 *********************************************************************************** 3745 ** ATU Interrupt Mask Register - ATUIMR 3746 ** 3747 ** The ATU Interrupt Mask Register contains the control bit to enable and disable interrupts 3748 ** generated by the ATU. 3749 ** ----------------------------------------------------------------- 3750 ** Bit Default Description 3751 ** 31:15 0 0000H Reserved 3752 ** 14 0 2 VPD Address Register Updated Mask - Controls the setting of bit 17 of the ATUISR and generation of the 3753 ** ATU Configuration Register Write interrupt when a PCI bus write occurs to the VPDAR register. 3754 ** 0=Not Masked 3755 ** 1=Masked 3756 ** 13 0 2 Reserved 3757 ** 12 0 2 Configuration Register Write Mask - Controls the setting of bit 15 of the ATUISR and generation of the 3758 ** ATU Configuration Register Write interrupt when a PCI bus write occurs to any ATU configuration register 3759 ** except those covered by mask bit 11 and bit 14 of this register, and ATU BIST enable bit 3 of the ATUCR. 3760 ** 0=Not Masked 3761 ** 1=Masked 3762 ** 11 1 2 ATU Inbound Memory Window 1 Base Updated Mask - Controls the setting of bit 14 of the ATUISR and 3763 ** generation of the ATU Configuration Register Write interrupt when a PCI bus write occurs to either the 3764 ** IABAR1 register or the IAUBAR1 register. 3765 ** 0=Not Masked 3766 ** 1=Masked 3767 ** 10 0 2 Initiated Split Completion Error Message Interrupt Mask - Controls the setting of bit 13 of the ATUISR and 3768 ** generation of the ATU Error interrupt when the ATU initiates a Split Completion Error Message. 3769 ** 0=Not Masked 3770 ** 1=Masked 3771 ** 09 0 2 Received Split Completion Error Message Interrupt Mask- Controls the setting of bit 12 of the ATUISR 3772 ** and generation of the ATU Error interrupt when a Split Completion Error Message results in bit 29 of the 3773 ** PCIXSR being set. 3774 ** 0=Not Masked 3775 ** 1=Masked 3776 ** 08 1 2 Power State Transition Interrupt Mask - Controls the setting of bit 12 of the ATUISR and generation of the 3777 ** ATU Error interrupt when ATU Power Management Control/Status Register is written to transition the 3778 ** ATU Function Power State from D0 to D3, D0 to D1, D1 to D3 or D3 to D0. 3779 ** 0=Not Masked 3780 ** 1=Masked 3781 ** 07 0 2 ATU Detected Parity Error Interrupt Mask - Controls the setting of bit 9 of the ATUISR and generation of 3782 ** the ATU Error interrupt when a parity error detected on the PCI bus that sets bit 15 of the ATUSR. 3783 ** 0=Not Masked 3784 ** 1=Masked 3785 ** 06 0 2 ATU SERR# Asserted Interrupt Mask - Controls the setting of bit 10 of the ATUISR and generation of the 3786 ** ATU Error interrupt when SERR# is asserted on the PCI interface resulting in bit 14 of the ATUSR being set. 3787 ** 0=Not Masked 3788 ** 1=Masked 3789 ** NOTE: This bit is specific to the ATU asserting SERR# and not detecting SERR# from another master. 3790 ** 05 0 2 ATU PCI Master Abort Interrupt Mask - Controls the setting of bit 3 of the ATUISR and generation of the 3791 ** ATU Error interrupt when a master abort error resulting in bit 13 of the ATUSR being set. 3792 ** 0=Not Masked 3793 ** 1=Masked 3794 ** 04 0 2 ATU PCI Target Abort (Master) Interrupt Mask- Controls the setting of bit 12 of the ATUISR and ATU Error 3795 ** generation of the interrupt when a target abort error resulting in bit 12 of the ATUSR being set 3796 ** 0=Not Masked 3797 ** 1=Masked 3798 ** 03 0 2 ATU PCI Target Abort (Target) Interrupt Mask- Controls the setting of bit 1 of the ATUISR and generation 3799 ** of the ATU Error interrupt when a target abort error resulting in bit 11 of the ATUSR being set. 3800 ** 0=Not Masked 3801 ** 1=Masked 3802 ** 02 0 2 ATU PCI Master Parity Error Interrupt Mask - Controls the setting of bit 0 of the ATUISR and generation 3803 ** of the ATU Error interrupt when a parity error resulting in bit 8 of the ATUSR being set. 3804 ** 0=Not Masked 3805 ** 1=Masked 3806 ** 01 0 2 ATU Inbound Error SERR# Enable - Controls when the ATU asserts (when enabled through the 3807 ** ATUCMD) SERR# on the PCI interface in response to a master abort on the internal bus during an 3808 ** inbound write transaction. 3809 ** 0=SERR# Not Asserted due to error 3810 ** 1=SERR# Asserted due to error 3811 ** 00 0 2 ATU ECC Target Abort Enable - Controls the ATU response on the PCI interface to a target abort (ECC 3812 ** error) from the memory controller on the internal bus. In conventional mode, this action only occurs 3813 ** during an inbound read transaction where the data phase that was target aborted on the internal bus is 3814 ** actually requested from the inbound read queue. 3815 ** 0=Disconnect with data 3816 ** (the data being up to 64 bits of 1��s) 3817 ** 1=Target Abort 3818 ** NOTE: In PCI-X Mode, The ATU initiates a Split Completion Error Message (with message class=2h - 3819 ** completer error and message index=81h - 80331 internal bus target abort) on the PCI bus, 3820 ** independent of the setting of this bit. 3821 *********************************************************************************** 3822 */ 3823 #define ARCMSR_ATU_INTERRUPT_MASK_REG 0x8C /*dword 0x8F,0x8E,0x8D,0x8C*/ 3824 /* 3825 *********************************************************************************** 3826 ** Inbound ATU Base Address Register 3 - IABAR3 3827 ** 3828 ** . The Inbound ATU Base Address Register 3 (IABAR3) together with the Inbound ATU Upper Base Address Register 3 (IAUBAR3) defines the block 3829 ** of memory addresses where the inbound translation window 3 begins. 3830 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 3831 ** . The IABAR3 and IAUBAR3 define the base address and describes the required memory block size. 3832 ** . Bits 31 through 12 of the IABAR3 is either read/write bits or read only with a value of 0 depending on the value located within the IALR3. 3833 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 3834 ** Note: 3835 ** Since IABAR3 does not appear in the standard PCI configuration header space (offsets 00H - 3CH), 3836 ** IABAR3 is not configured by the host during normal system initialization. 3837 ** Warning: 3838 ** When a non-zero value is not written to IALR3, 3839 ** the user should not set either the Prefetchable Indicator 3840 ** or the Type Indicator for 64 bit addressability. 3841 ** This is the default for IABAR3. 3842 ** Assuming a non-zero value is written to IALR3, 3843 ** the user may set the Prefetchable Indicator 3844 ** or the Type Indicator: 3845 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 3846 ** when the Prefetchable Indicator is not set, 3847 ** the user should also leave the Type Indicator set for 32 bit addressability. 3848 ** This is the default for IABAR3. 3849 ** b. when the Prefetchable Indicator is set, 3850 ** the user should also set the Type Indicator for 64 bit addressability. 3851 ** ----------------------------------------------------------------- 3852 ** Bit Default Description 3853 ** 31:12 00000H Translation Base Address 3 - These bits define the actual location 3854 ** the translation function is to respond to when addressed from the PCI bus. 3855 ** 11:04 00H Reserved. 3856 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 3857 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 3858 ** 00 - Memory Window is locatable anywhere in 32 bit address space 3859 ** 10 - Memory Window is locatable anywhere in 64 bit address space 3860 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 3861 ** The ATU does not occupy I/O space, 3862 ** thus this bit must be zero. 3863 *********************************************************************************** 3864 */ 3865 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS3_REG 0x90 /*dword 0x93,0x92,0x91,0x90*/ 3866 /* 3867 *********************************************************************************** 3868 ** Inbound ATU Upper Base Address Register 3 - IAUBAR3 3869 ** 3870 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 3871 ** Together with the Translation Base Address this register defines the actual location 3872 ** the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 3873 ** The programmed value within the base address register must comply with the PCI programming 3874 ** requirements for address alignment. 3875 ** Note: 3876 ** When the Type indicator of IABAR3 is set to indicate 32 bit addressability, 3877 ** the IAUBAR3 register attributes are read-only. 3878 ** This is the default for IABAR3. 3879 ** ----------------------------------------------------------------- 3880 ** Bit Default Description 3881 ** 31:0 00000H Translation Upper Base Address 3 - Together with the Translation Base Address 3 these bits define 3882 ** the actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes. 3883 *********************************************************************************** 3884 */ 3885 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS3_REG 0x94 /*dword 0x97,0x96,0x95,0x94*/ 3886 /* 3887 *********************************************************************************** 3888 ** Inbound ATU Limit Register 3 - IALR3 3889 ** 3890 ** Inbound address translation for memory window 3 occurs for data transfers occurring from the PCI 3891 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 3892 ** PCI addresses to internal bus addresses. 3893 ** The inbound translation base address for inbound window 3 is specified in Section 3.10.15. When 3894 ** determining block size requirements �X as described in Section 3.10.21 �X the translation limit 3895 ** register provides the block size requirements for the base address register. The remaining registers 3896 ** used for performing address translation are discussed in Section 3.2.1.1. 3897 ** The 80331 translate value register��s programmed value must be naturally aligned with the base 3898 ** address register��s programmed value. The limit register is used as a mask; thus, the lower address 3899 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 3900 ** Specification, Revision 2.3 for additional information on programming base address registers. 3901 ** Bits 31 to 12 within the IALR3 have a direct effect on the IABAR3 register, bits 31 to 12, with a 3902 ** one to one correspondence. A value of 0 in a bit within the IALR3 makes the corresponding bit 3903 ** within the IABAR3 a read only bit which always returns 0. A value of 1 in a bit within the IALR3 3904 ** makes the corresponding bit within the IABAR3 read/write from PCI. Note that a consequence of 3905 ** this programming scheme is that unless a valid value exists within the IALR3, all writes to the 3906 ** IABAR3 has no effect since a value of all zeros within the IALR3 makes the IABAR3 a read only 3907 ** register. 3908 ** ----------------------------------------------------------------- 3909 ** Bit Default Description 3910 ** 31:12 00000H Inbound Translation Limit 3 - This readback value determines the memory block size required 3911 ** for the ATUs memory window 3. 3912 ** 11:00 000H Reserved 3913 *********************************************************************************** 3914 */ 3915 #define ARCMSR_INBOUND_ATU_LIMIT3_REG 0x98 /*dword 0x9B,0x9A,0x99,0x98*/ 3916 /* 3917 *********************************************************************************** 3918 ** Inbound ATU Translate Value Register 3 - IATVR3 3919 ** 3920 ** The Inbound ATU Translate Value Register 3 (IATVR3) contains the internal bus address used to 3921 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 3922 ** inbound ATU address translation. 3923 ** ----------------------------------------------------------------- 3924 ** Bit Default Description 3925 ** 31:12 00000H Inbound ATU Translation Value 3 - This value is used to convert the PCI address to internal bus addresses. 3926 ** This value must be 64-bit aligned on the internal bus. The default address allows the ATU to 3927 ** access the internal 80331 memory-mapped registers. 3928 ** 11:00 000H Reserved 3929 *********************************************************************************** 3930 */ 3931 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE3_REG 0x9C /*dword 0x9F,0x9E,0x9D,0x9C*/ 3932 /* 3933 *********************************************************************************** 3934 ** Outbound Configuration Cycle Address Register - OCCAR 3935 ** 3936 ** The Outbound Configuration Cycle Address Register is used to hold the 32-bit PCI configuration 3937 ** cycle address. The Intel XScale core writes the PCI configuration cycles address which then 3938 ** enables the outbound configuration read or write. The Intel XScale core then performs a read or 3939 ** write to the Outbound Configuration Cycle Data Register to initiate the configuration cycle on the 3940 ** PCI bus. 3941 ** Note: Bits 15:11 of the configuration cycle address for Type 0 configuration cycles are defined differently 3942 ** for Conventional versus PCI-X modes. When 80331 software programs the OCCAR to initiate a 3943 ** Type 0 configuration cycle, the OCCAR should always be loaded based on the PCI-X definition for 3944 ** the Type 0 configuration cycle address. When operating in Conventional mode, the 80331 clears 3945 ** bits 15:11 of the OCCAR prior to initiating an outbound Type 0 configuration cycle. See the PCI-X 3946 ** Addendum to the PCI Local Bus Specification, Revision 1.0a for details on the two formats. 3947 ** ----------------------------------------------------------------- 3948 ** Bit Default Description 3949 ** 31:00 0000 0000H Configuration Cycle Address - These bits define the 32-bit PCI address used during an outbound 3950 ** configuration read or write cycle. 3951 *********************************************************************************** 3952 */ 3953 #define ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_ADDRESS_REG 0xA4 /*dword 0xA7,0xA6,0xA5,0xA4*/ 3954 /* 3955 *********************************************************************************** 3956 ** Outbound Configuration Cycle Data Register - OCCDR 3957 ** 3958 ** The Outbound Configuration Cycle Data Register is used to initiate a configuration read or write 3959 ** on the PCI bus. The register is logical rather than physical meaning that it is an address not a 3960 ** register. The Intel XScale core reads or writes the data registers memory-mapped address to 3961 ** initiate the configuration cycle on the PCI bus with the address found in the OCCAR. For a 3962 ** configuration write, the data is latched from the internal bus and forwarded directly to the OWQ. 3963 ** For a read, the data is returned directly from the ORQ to the Intel XScale core and is never 3964 ** actually entered into the data register (which does not physically exist). 3965 ** The OCCDR is only visible from 80331 internal bus address space and appears as a reserved value 3966 ** within the ATU configuration space. 3967 ** ----------------------------------------------------------------- 3968 ** Bit Default Description 3969 ** 31:00 0000 0000H Configuration Cycle Data - These bits define the data used during an outbound configuration read 3970 ** or write cycle. 3971 *********************************************************************************** 3972 */ 3973 #define ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_DATA_REG 0xAC /*dword 0xAF,0xAE,0xAD,0xAC*/ 3974 /* 3975 *********************************************************************************** 3976 ** VPD Capability Identifier Register - VPD_CAPID 3977 ** 3978 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 3979 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 3980 ** Capability contained in that header. In the case of the 80331, this is the VPD extended capability 3981 ** with an ID of 03H as defined by the PCI Local Bus Specification, Revision 2.3. 3982 ** ----------------------------------------------------------------- 3983 ** Bit Default Description 3984 ** 07:00 03H Cap_Id - This field with its�� 03H value identifies this item in the linked list of Extended Capability 3985 ** Headers as being the VPD capability registers. 3986 *********************************************************************************** 3987 */ 3988 #define ARCMSR_VPD_CAPABILITY_IDENTIFIER_REG 0xB8 /*byte*/ 3989 /* 3990 *********************************************************************************** 3991 ** VPD Next Item Pointer Register - VPD_NXTP 3992 ** 3993 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 3994 ** Revision 2.3. This register describes the location of the next item in the function��s capability list. 3995 ** For the 80331, this the final capability list, and hence, this register is set to 00H. 3996 ** ----------------------------------------------------------------- 3997 ** Bit Default Description 3998 ** 07:00 00H Next_ Item_ Pointer - This field provides an offset into the function��s configuration space pointing to the 3999 ** next item in the function��s capability list. Since the VPD capabilities are the last in the linked list of 4000 ** extended capabilities in the 80331, the register is set to 00H. 4001 *********************************************************************************** 4002 */ 4003 #define ARCMSR_VPD_NEXT_ITEM_PTR_REG 0xB9 /*byte*/ 4004 /* 4005 *********************************************************************************** 4006 ** VPD Address Register - VPD_AR 4007 ** 4008 ** The VPD Address register (VPDAR) contains the DWORD-aligned byte address of the VPD to be 4009 ** accessed. The register is read/write and the initial value at power-up is indeterminate. 4010 ** A PCI Configuration Write to the VPDAR interrupts the Intel XScale core. Software can use 4011 ** the Flag setting to determine whether the configuration write was intended to initiate a read or 4012 ** write of the VPD through the VPD Data Register. 4013 ** ----------------------------------------------------------------- 4014 ** Bit Default Description 4015 ** 15 0 2 Flag - A flag is used to indicate when a transfer of data between the VPD Data Register and the storage 4016 ** component has completed. Please see Section 3.9, ��Vital Product Data�� on page 201 for more details on 4017 ** how the 80331 handles the data transfer. 4018 ** 14:0 0000H VPD Address - This register is written to set the DWORD-aligned byte address used to read or write 4019 ** Vital Product Data from the VPD storage component. 4020 *********************************************************************************** 4021 */ 4022 #define ARCMSR_VPD_ADDRESS_REG 0xBA /*word 0xBB,0xBA*/ 4023 /* 4024 *********************************************************************************** 4025 ** VPD Data Register - VPD_DR 4026 ** 4027 ** This register is used to transfer data between the 80331 and the VPD storage component. 4028 ** ----------------------------------------------------------------- 4029 ** Bit Default Description 4030 ** 31:00 0000H VPD Data - Four bytes are always read or written through this register to/from the VPD storage component. 4031 *********************************************************************************** 4032 */ 4033 #define ARCMSR_VPD_DATA_REG 0xBC /*dword 0xBF,0xBE,0xBD,0xBC*/ 4034 /* 4035 *********************************************************************************** 4036 ** Power Management Capability Identifier Register -PM_CAPID 4037 ** 4038 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 4039 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 4040 ** Capability contained in that header. In the case of the 80331, this is the PCI Bus Power 4041 ** Management extended capability with an ID of 01H as defined by the PCI Bus Power Management 4042 ** Interface Specification, Revision 1.1. 4043 ** ----------------------------------------------------------------- 4044 ** Bit Default Description 4045 ** 07:00 01H Cap_Id - This field with its�� 01H value identifies this item in the linked list of Extended Capability 4046 ** Headers as being the PCI Power Management Registers. 4047 *********************************************************************************** 4048 */ 4049 #define ARCMSR_POWER_MANAGEMENT_CAPABILITY_IDENTIFIER_REG 0xC0 /*byte*/ 4050 /* 4051 *********************************************************************************** 4052 ** Power Management Next Item Pointer Register - PM_NXTP 4053 ** 4054 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 4055 ** Revision 2.3. This register describes the location of the next item in the function��s capability list. 4056 ** For the 80331, the next capability (MSI capability list) is located at off-set D0H. 4057 ** ----------------------------------------------------------------- 4058 ** Bit Default Description 4059 ** 07:00 D0H Next_ Item_ Pointer - This field provides an offset into the function��s configuration space pointing to the 4060 ** next item in the function��s capability list which in the 80331 is the MSI extended capabilities header. 4061 *********************************************************************************** 4062 */ 4063 #define ARCMSR_POWER_NEXT_ITEM_PTR_REG 0xC1 /*byte*/ 4064 /* 4065 *********************************************************************************** 4066 ** Power Management Capabilities Register - PM_CAP 4067 ** 4068 ** Power Management Capabilities bits adhere to the definitions in the PCI Bus Power Management 4069 ** Interface Specification, Revision 1.1. This register is a 16-bit read-only register which provides 4070 ** information on the capabilities of the ATU function related to power management. 4071 ** ----------------------------------------------------------------- 4072 ** Bit Default Description 4073 ** 15:11 00000 2 PME_Support - This function is not capable of asserting the PME# signal in any state, since PME# 4074 ** is not supported by the 80331. 4075 ** 10 0 2 D2_Support - This bit is set to 0 2 indicating that the 80331 does not support the D2 Power Management State 4076 ** 9 1 2 D1_Support - This bit is set to 1 2 indicating that the 80331 supports the D1 Power Management State 4077 ** 8:6 000 2 Aux_Current - This field is set to 000 2 indicating that the 80331 has no current requirements for the 4078 ** 3.3Vaux signal as defined in the PCI Bus Power Management Interface Specification, Revision 1.1 4079 ** 5 0 2 DSI - This field is set to 0 2 meaning that this function requires a device specific initialization sequence 4080 ** following the transition to the D0 uninitialized state. 4081 ** 4 0 2 Reserved. 4082 ** 3 0 2 PME Clock - Since the 80331 does not support PME# signal generation this bit is cleared to 0 2 . 4083 ** 2:0 010 2 Version - Setting these bits to 010 2 means that this function complies with PCI Bus Power Management 4084 ** Interface Specification, Revision 1.1 4085 *********************************************************************************** 4086 */ 4087 #define ARCMSR_POWER_MANAGEMENT_CAPABILITY_REG 0xC2 /*word 0xC3,0xC2*/ 4088 /* 4089 *********************************************************************************** 4090 ** Power Management Control/Status Register - PM_CSR 4091 ** 4092 ** Power Management Control/Status bits adhere to the definitions in the PCI Bus Power 4093 ** Management Interface Specification, Revision 1.1. This 16-bit register is the control and status 4094 ** interface for the power management extended capability. 4095 ** ----------------------------------------------------------------- 4096 ** Bit Default Description 4097 ** 15 0 2 PME_Status - This function is not capable of asserting the PME# signal in any state, since PME## is not 4098 ** supported by the 80331. 4099 ** 14:9 00H Reserved 4100 ** 8 0 2 PME_En - This bit is hardwired to read-only 0 2 since this function does not support PME# 4101 ** generation from any power state. 4102 ** 7:2 000000 2 Reserved 4103 ** 1:0 00 2 Power State - This 2-bit field is used both to determine the current power state 4104 ** of a function and to set the function into a new power state. The definition of the values is: 4105 ** 00 2 - D0 4106 ** 01 2 - D1 4107 ** 10 2 - D2 (Unsupported) 4108 ** 11 2 - D3 hot 4109 ** The 80331 supports only the D0 and D3 hot states. 4110 ** 4111 *********************************************************************************** 4112 */ 4113 #define ARCMSR_POWER_MANAGEMENT_CONTROL_STATUS_REG 0xC4 /*word 0xC5,0xC4*/ 4114 /* 4115 *********************************************************************************** 4116 ** PCI-X Capability Identifier Register - PX_CAPID 4117 ** 4118 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 4119 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 4120 ** Capability contained in that header. In the case of the 80331, this is the PCI-X extended capability with 4121 ** an ID of 07H as defined by the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a. 4122 ** ----------------------------------------------------------------- 4123 ** Bit Default Description 4124 ** 07:00 07H Cap_Id - This field with its�� 07H value identifies this item in the linked list of Extended Capability 4125 ** Headers as being the PCI-X capability registers. 4126 *********************************************************************************** 4127 */ 4128 #define ARCMSR_PCIX_CAPABILITY_IDENTIFIER_REG 0xE0 /*byte*/ 4129 /* 4130 *********************************************************************************** 4131 ** PCI-X Next Item Pointer Register - PX_NXTP 4132 ** 4133 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 4134 ** Revision 2.3. This register describes the location of the next item in the function��s capability list. 4135 ** By default, the PCI-X capability is the last capabilities list for the 80331, thus this register defaults 4136 ** to 00H. 4137 ** However, this register may be written to B8H prior to host configuration to include the VPD 4138 ** capability located at off-set B8H. 4139 ** Warning: Writing this register to any value other than 00H (default) or B8H is not supported and may 4140 ** produce unpredictable system behavior. 4141 ** In order to guarantee that this register is written prior to host configuration, the 80331 must be 4142 ** initialized at P_RST# assertion to Retry Type 0 configuration cycles (bit 2 of PCSR). Typically, 4143 ** the Intel XScale core would be enabled to boot immediately following P_RST# assertion in 4144 ** this case (bit 1 of PCSR), as well. Please see Table 125, ��PCI Configuration and Status Register - 4145 ** PCSR�� on page 253 for more details on the 80331 initialization modes. 4146 ** ----------------------------------------------------------------- 4147 ** Bit Default Description 4148 ** 07:00 00H Next_ Item_ Pointer - This field provides an offset into the function��s configuration space pointing to the 4149 ** next item in the function��s capability list. Since the PCI-X capabilities are the last in the linked list of 4150 ** extended capabilities in the 80331, the register is set to 00H. 4151 ** However, this field may be written prior to host configuration with B8H to extend the list to include the 4152 ** VPD extended capabilities header. 4153 *********************************************************************************** 4154 */ 4155 #define ARCMSR_PCIX_NEXT_ITEM_PTR_REG 0xE1 /*byte*/ 4156 /* 4157 *********************************************************************************** 4158 ** PCI-X Command Register - PX_CMD 4159 ** 4160 ** This register controls various modes and features of ATU and Message Unit when operating in the 4161 ** PCI-X mode. 4162 ** ----------------------------------------------------------------- 4163 ** Bit Default Description 4164 ** 15:7 000000000 2 Reserved. 4165 ** 6:4 011 2 Maximum Outstanding Split Transactions - This register sets the maximum number of Split Transactions 4166 ** the device is permitted to have outstanding at one time. 4167 ** Register Maximum Outstanding 4168 ** 0 1 4169 ** 1 2 4170 ** 2 3 4171 ** 3 4 4172 ** 4 8 4173 ** 5 12 4174 ** 6 16 4175 ** 7 32 4176 ** 3:2 00 2 Maximum Memory Read Byte Count - This register sets the maximum byte count the device uses when 4177 ** initiating a Sequence with one of the burst memory read commands. 4178 ** Register Maximum Byte Count 4179 ** 0 512 4180 ** 1 1024 4181 ** 2 2048 4182 ** 3 4096 4183 ** 1 0 2 4184 ** Enable Relaxed Ordering - The 80331 does not set the relaxed ordering bit in the Requester Attributes 4185 ** of Transactions. 4186 ** 0 0 2 Data Parity Error Recovery Enable - The device driver sets this bit to enable the device to attempt to 4187 ** recover from data parity errors. When this bit is 0 and the device is in PCI-X mode, the device asserts 4188 ** SERR# (when enabled) whenever the Master Data Parity Error bit (Status register, bit 8) is set. 4189 *********************************************************************************** 4190 */ 4191 #define ARCMSR_PCIX_COMMAND_REG 0xE2 /*word 0xE3,0xE2*/ 4192 /* 4193 *********************************************************************************** 4194 ** PCI-X Status Register - PX_SR 4195 ** 4196 ** This register identifies the capabilities and current operating mode of ATU, DMAs and Message 4197 ** Unit when operating in the PCI-X mode. 4198 ** ----------------------------------------------------------------- 4199 ** Bit Default Description 4200 ** 31:30 00 2 Reserved 4201 ** 29 0 2 Received Split Completion Error Message - This bit is set when the device receives a Split Completion 4202 ** Message with the Split Completion Error attribute bit set. Once set, this bit remains set until software 4203 ** writes a 1 to this location. 4204 ** 0=no Split Completion error message received. 4205 ** 1=a Split Completion error message has been received. 4206 ** 28:26 001 2 Designed Maximum Cumulative Read Size (DMCRS) - The value of this register depends on the setting 4207 ** of the Maximum Memory Read Byte Count field of the PCIXCMD register: 4208 ** DMCRS Max ADQs Maximum Memory Read Byte Count Register Setting 4209 ** 1 16 512 (Default) 4210 ** 2 32 1024 4211 ** 2 32 2048 4212 ** 2 32 4096 4213 ** 25:23 011 2 Designed Maximum Outstanding Split Transactions - The 80331 can have up to four outstanding split transactions. 4214 ** 22:21 01 2 Designed Maximum Memory Read Byte Count - The 80331 can generate memory reads with byte counts up 4215 ** to 1024 bytes. 4216 ** 20 1 2 80331 is a complex device. 4217 ** 19 0 2 Unexpected Split Completion - This bit is set when an unexpected Split Completion with this device��s 4218 ** Requester ID is received. Once set, this bit remains set until software writes a 1 to this location. 4219 ** 0=no unexpected Split Completion has been received. 4220 ** 1=an unexpected Split Completion has been received. 4221 ** 18 0 2 Split Completion Discarded - This bit is set when the device discards a Split Completion because the 4222 ** requester would not accept it. See Section 5.4.4 of the PCI-X Addendum to the PCI Local Bus 4223 ** Specification, Revision 1.0a for details. Once set, this bit remains set until software writes a 1 to this 4224 ** location. 4225 ** 0=no Split Completion has been discarded. 4226 ** 1=a Split Completion has been discarded. 4227 ** NOTE: The 80331 does not set this bit since there is no Inbound address responding to Inbound Read 4228 ** Requests with Split Responses (Memory or Register) that has ��read side effects.�� 4229 ** 17 1 2 80331 is a 133 MHz capable device. 4230 ** 16 1 2 or P_32BITPCI# 80331 with bridge enabled (BRG_EN=1) implements the ATU with a 64-bit interface on the secondary PCI bus, 4231 ** therefore this bit is always set. 4232 ** 80331 with no bridge and central resource disabled (BRG_EN=0, ARB_EN=0), 4233 ** use this bit to identify the add-in card to the system as 64-bit or 32-bit wide via a user-configurable strap (P_32BITPCI#). 4234 ** This strap, by default, identifies the add in card based on 80331 with bridge disabled 4235 ** as 64-bit unless the user attaches the appropriate pull-down resistor to the strap. 4236 ** 0=The bus is 32 bits wide. 4237 ** 1=The bus is 64 bits wide. 4238 ** 15:8 FFH Bus Number - This register is read for diagnostic purposes only. It indicates the number of the bus 4239 ** segment for the device containing this function. The function uses this number as part of its Requester 4240 ** ID and Completer ID. For all devices other than the source bridge, each time the function is addressed 4241 ** by a Configuration Write transaction, the function must update this register with the contents of AD[7::0] 4242 ** of the attribute phase of the Configuration Write, regardless of which register in the function is 4243 ** addressed by the transaction. The function is addressed by a Configuration Write transaction when all of 4244 ** the following are true: 4245 ** 1. The transaction uses a Configuration Write command. 4246 ** 2. IDSEL is asserted during the address phase. 4247 ** 3. AD[1::0] are 00b (Type 0 configuration transaction). 4248 ** 4. AD[10::08] of the configuration address contain the appropriate function number. 4249 ** 7:3 1FH Device Number - This register is read for diagnostic purposes only. It indicates the number of the device 4250 ** containing this function, i.e., the number in the Device Number field (AD[15::11]) of the address of a 4251 ** Type 0 configuration transaction that is assigned to the device containing this function by the connection 4252 ** of the system hardware. The system must assign a device number other than 00h (00h is reserved for 4253 ** the source bridge). The function uses this number as part of its Requester ID and Completer ID. Each 4254 ** time the function is addressed by a Configuration Write transaction, the device must update this register 4255 ** with the contents of AD[15::11] of the address phase of the Configuration Write, regardless of which 4256 ** register in the function is addressed by the transaction. The function is addressed by a Configuration 4257 ** Write transaction when all of the following are true: 4258 ** 1. The transaction uses a Configuration Write command. 4259 ** 2. IDSEL is asserted during the address phase. 4260 ** 3. AD[1::0] are 00b (Type 0 configuration transaction). 4261 ** 4. AD[10::08] of the configuration address contain the appropriate function number. 4262 ** 2:0 000 2 Function Number - This register is read for diagnostic purposes only. It indicates the number of this 4263 ** function; i.e., the number in the Function Number field (AD[10::08]) of the address of a Type 0 4264 ** configuration transaction to which this function responds. The function uses this number as part of its 4265 ** Requester ID and Completer ID. 4266 ** 4267 ************************************************************************** 4268 */ 4269 #define ARCMSR_PCIX_STATUS_REG 0xE4 /*dword 0xE7,0xE6,0xE5,0xE4*/ 4270 4271 /* 4272 ************************************************************************** 4273 ** Inbound Read Transaction 4274 ** ======================================================================== 4275 ** An inbound read transaction is initiated by a PCI initiator and is targeted at either 80331 local 4276 ** memory or a 80331 memory-mapped register space. The read transaction is propagated through 4277 ** the inbound transaction queue (ITQ) and read data is returned through the inbound read queue 4278 ** (IRQ). 4279 ** When operating in the conventional PCI mode, all inbound read transactions are processed as 4280 ** delayed read transactions. When operating in the PCI-X mode, all inbound read transactions are 4281 ** processed as split transactions. The ATUs PCI interface claims the read transaction and forwards 4282 ** the read request through to the internal bus and returns the read data to the PCI bus. Data flow for 4283 ** an inbound read transaction on the PCI bus is summarized in the following statements: 4284 ** �E The ATU claims the PCI read transaction when the PCI address is within the inbound 4285 ** translation window defined by ATU Inbound Base Address Register (and Inbound Upper Base 4286 ** Address Register during DACs) and Inbound Limit Register. 4287 ** �E When operating in the conventional PCI mode, when the ITQ is currently holding transaction 4288 ** information from a previous delayed read, the current transaction information is compared to 4289 ** the previous transaction information (based on the setting of the DRC Alias bit in 4290 ** Section 3.10.39, ��ATU Configuration Register - ATUCR�� on page 252). When there is a 4291 ** match and the data is in the IRQ, return the data to the master on the PCI bus. When there is a 4292 ** match and the data is not available, a Retry is signaled with no other action taken. When there 4293 ** is not a match and when the ITQ has less than eight entries, capture the transaction 4294 ** information, signal a Retry and initiate a delayed transaction. When there is not a match and 4295 ** when the ITQ is full, then signal a Retry with no other action taken. 4296 ** �X When an address parity error is detected, the address parity response defined in 4297 ** Section 3.7 is used. 4298 ** �E When operating in the conventional PCI mode, once read data is driven onto the PCI bus from 4299 ** the IRQ, it continues until one of the following is true: 4300 ** �X The initiator completes the PCI transaction. When there is data left unread in the IRQ, the 4301 ** data is flushed. 4302 ** �X An internal bus Target Abort was detected. In this case, the QWORD associated with the 4303 ** Target Abort is never entered into the IRQ, and therefore is never returned. 4304 ** �X Target Abort or a Disconnect with Data is returned in response to the Internal Bus Error. 4305 ** �X The IRQ becomes empty. In this case, the PCI interface signals a Disconnect with data to 4306 ** the initiator on the last data word available. 4307 ** �E When operating in the PCI-X mode, when ITQ is not full, the PCI address, attribute and 4308 ** command are latched into the available ITQ and a Split Response Termination is signalled to 4309 ** the initiator. 4310 ** �E When operating in the PCI-X mode, when the transaction does not cross a 1024 byte aligned 4311 ** boundary, then the ATU waits until it receives the full byte count from the internal bus target 4312 ** before returning read data by generating the split completion transaction on the PCI-X bus. 4313 ** When the read requested crosses at least one 1024 byte boundary, then ATU completes the 4314 ** transfer by returning data in 1024 byte aligned chunks. 4315 ** �E When operating in the PCI-X mode, once a split completion transaction has started, it 4316 ** continues until one of the following is true: 4317 ** �X The requester (now the target) generates a Retry Termination, or a Disconnection at Next 4318 ** ADB (when the requester is a bridge) 4319 ** �X The byte count is satisfied. 4320 ** �X An internal bus Target Abort was detected. The ATU generates a Split Completion 4321 ** Message (message class=2h - completer error, and message index=81h - target abort) to 4322 ** inform the requester about the abnormal condition. The ITQ for this transaction is flushed. 4323 ** Refer to Section 3.7.1. 4324 ** �X An internal bus Master Abort was detected. The ATU generates a Split Completion 4325 ** Message (message class=2h - completer error, and message index=80h - Master abort) to 4326 ** inform the requester about the abnormal condition. The ITQ for this transaction is flushed. 4327 ** Refer to Section 3.7.1 4328 ** �E When operating in the conventional PCI mode, when the master inserts wait states on the PCI 4329 ** bus, the ATU PCI slave interface waits with no premature disconnects. 4330 ** �E When a data parity error occurs signified by PERR# asserted from the initiator, no action is 4331 ** taken by the target interface. Refer to Section 3.7.2.5. 4332 ** �E When operating in the conventional PCI mode, when the read on the internal bus is 4333 ** target-aborted, either a target-abort or a disconnect with data is signaled to the initiator. This is 4334 ** based on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). When set, a 4335 ** target abort is used, when clear, a disconnect is used. 4336 ** �E When operating in the PCI-X mode (with the exception of the MU queue ports at offsets 40h 4337 ** and 44h), when the transaction on the internal bus resulted in a target abort, the ATU generates 4338 ** a Split Completion Message (message class=2h - completer error, and message index=81h - 4339 ** internal bus target abort) to inform the requester about the abnormal condition. For the MU 4340 ** queue ports, the ATU returns either a target abort or a single data phase disconnect depending 4341 ** on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). The ITQ for this 4342 ** transaction is flushed. Refer to Section 3.7.1. 4343 ** �E When operating in the conventional PCI mode, when the transaction on the internal bus 4344 ** resulted in a master abort, the ATU returns a target abort to inform the requester about the 4345 ** abnormal condition. The ITQ for this transaction is flushed. Refer to Section 3.7.1 4346 ** �E When operating in the PCI-X mode, when the transaction on the internal bus resulted in a 4347 ** master abort, the ATU generates a Split Completion Message (message class=2h - completer 4348 ** error, and message index=80h - internal bus master abort) to inform the requester about the 4349 ** abnormal condition. The ITQ for this transaction is flushed. Refer to Section 3.7.1. 4350 ** �E When operating in the PCI-X mode, when the Split Completion transaction completes with 4351 ** either Master-Abort or Target-Abort, the requester is indicating a failure condition that 4352 ** prevents it from accepting the completion it requested. In this case, since the Split Request 4353 ** addresses a location that has no read side effects, the completer must discard the Split 4354 ** Completion and take no further action. 4355 ** The data flow for an inbound read transaction on the internal bus is summarized in the following 4356 ** statements: 4357 ** �E The ATU internal bus master interface requests the internal bus when a PCI address appears in 4358 ** an ITQ and transaction ordering has been satisfied. When operating in the PCI-X mode the 4359 ** ATU does not use the information provided by the Relax Ordering Attribute bit. That is, ATU 4360 ** always uses conventional PCI ordering rules. 4361 ** �E Once the internal bus is granted, the internal bus master interface drives the translated address 4362 ** onto the bus and wait for IB_DEVSEL#. When a Retry is signaled, the request is repeated. 4363 ** When a master abort occurs, the transaction is considered complete and a target abort is loaded 4364 ** into the associated IRQ for return to the PCI initiator (transaction is flushed once the PCI 4365 ** master has been delivered the target abort). 4366 ** �E Once the translated address is on the bus and the transaction has been accepted, the internal 4367 ** bus target starts returning data with the assertion of IB_TRDY#. Read data is continuously 4368 ** received by the IRQ until one of the following is true: 4369 ** �X The full byte count requested by the ATU read request is received. The ATU internal bus 4370 ** initiator interface performs a initiator completion in this case. 4371 ** �X When operating in the conventional PCI mode, a Target Abort is received on the internal 4372 ** bus from the internal bus target. In this case, the transaction is aborted and the PCI side is 4373 ** informed. 4374 ** �X When operating in the PCI-X mode, a Target Abort is received on the internal bus from 4375 ** the internal bus target. In this case, the transaction is aborted. The ATU generates a Split 4376 ** Completion Message (message class=2h - completer error, and message index=81h - 4377 ** target abort) on the PCI bus to inform the requester about the abnormal condition. The 4378 ** ITQ for this transaction is flushed. 4379 ** �X When operating in the conventional PCI mode, a single data phase disconnection is 4380 ** received from the internal bus target. When the data has not been received up to the next 4381 ** QWORD boundary, the ATU internal bus master interface attempts to reacquire the bus. 4382 ** When not, the bus returns to idle. 4383 ** �X When operating in the PCI-X mode, a single data phase disconnection is received from 4384 ** the internal bus target. The ATU IB initiator interface attempts to reacquire the bus to 4385 ** obtain remaining data. 4386 ** �X When operating in the conventional PCI mode, a disconnection at Next ADB is received 4387 ** from the internal bus target. The bus returns to idle. 4388 ** �X When operating in the PCI-X mode, a disconnection at Next ADB is received from the 4389 ** internal bus target. The ATU IB initiator interface attempts to reacquire the bus to obtain 4390 ** remaining data. 4391 ** To support PCI Local Bus Specification, Revision 2.0 devices, the ATU can be programmed to 4392 ** ignore the memory read command (Memory Read, Memory Read Line, and Memory Read 4393 ** Multiple) when trying to match the current inbound read transaction with data in a DRC queue 4394 ** which was read previously (DRC on target bus). When the Read Command Alias Bit in the 4395 ** ATUCR register is set, the ATU does not distinguish the read commands on transactions. For 4396 ** example, the ATU enqueues a DRR with a Memory Read Multiple command and performs the read 4397 ** on the internal bus. Some time later, a PCI master attempts a Memory Read with the same address 4398 ** as the previous Memory Read Multiple. When the Read Command Bit is set, the ATU would return 4399 ** the read data from the DRC queue and consider the Delayed Read transaction complete. When the 4400 ** Read Command bit in the ATUCR was clear, the ATU would not return data since the PCI read 4401 ** commands did not match, only the address. 4402 ************************************************************************** 4403 */ 4404 /* 4405 ************************************************************************** 4406 ** Inbound Write Transaction 4407 **======================================================================== 4408 ** An inbound write transaction is initiated by a PCI master and is targeted at either 80331 local 4409 ** memory or a 80331 memory-mapped register. 4410 ** Data flow for an inbound write transaction on the PCI bus is summarized as: 4411 ** �E The ATU claims the PCI write transaction when the PCI address is within the inbound 4412 ** translation window defined by the ATU Inbound Base Address Register (and Inbound Upper 4413 ** Base Address Register during DACs) and Inbound Limit Register. 4414 ** �E When the IWADQ has at least one address entry available and the IWQ has at least one buffer 4415 ** available, the address is captured and the first data phase is accepted. 4416 ** �E The PCI interface continues to accept write data until one of the following is true: 4417 ** �X The initiator performs a disconnect. 4418 ** �X The transaction crosses a buffer boundary. 4419 ** �E When an address parity error is detected during the address phase of the transaction, the 4420 ** address parity error mechanisms are used. Refer to Section 3.7.1 for details of the address 4421 ** parity error response. 4422 ** �E When operating in the PCI-X mode when an attribute parity error is detected, the attribute 4423 ** parity error mechanism described in Section 3.7.1 is used. 4424 ** �E When a data parity error is detected while accepting data, the slave interface sets the 4425 ** appropriate bits based on PCI specifications. No other action is taken. Refer to Section 3.7.2.6 4426 ** for details of the inbound write data parity error response. 4427 ** Once the PCI interface places a PCI address in the IWADQ, when IWQ has received data sufficient 4428 ** to cross a buffer boundary or the master disconnects on the PCI bus, the ATUs internal bus 4429 ** interface becomes aware of the inbound write. When there are additional write transactions ahead 4430 ** in the IWQ/IWADQ, the current transaction remains posted until ordering and priority have been 4431 ** satisfied (Refer to Section 3.5.3) and the transaction is attempted on the internal bus by the ATU 4432 ** internal master interface. The ATU does not insert target wait states nor do data merging on the PCI 4433 ** interface, when operating in the PCI mode. 4434 ** In the PCI-X mode memory writes are always executed as immediate transactions, while 4435 ** configuration write transactions are processed as split transactions. The ATU generates a Split 4436 ** Completion Message, (with Message class=0h - Write Completion Class and Message index = 4437 ** 00h - Write Completion Message) once a configuration write is successfully executed. 4438 ** Also, when operating in the PCI-X mode a write sequence may contain multiple write transactions. 4439 ** The ATU handles such transactions as independent transactions. 4440 ** Data flow for the inbound write transaction on the internal bus is summarized as: 4441 ** �E The ATU internal bus master requests the internal bus when IWADQ has at least one entry 4442 ** with associated data in the IWQ. 4443 ** �E When the internal bus is granted, the internal bus master interface initiates the write 4444 ** transaction by driving the translated address onto the internal bus. For details on inbound 4445 ** address translation. 4446 ** �E When IB_DEVSEL# is not returned, a master abort condition is signaled on the internal bus. 4447 ** The current transaction is flushed from the queue and SERR# may be asserted on the PCI 4448 ** interface. 4449 ** �E The ATU initiator interface asserts IB_REQ64# to attempt a 64-bit transfer. When 4450 ** IB_ACK64# is not returned, a 32-bit transfer is used. Transfers of less than 64-bits use the 4451 ** IB_C/BE[7:0]# to mask the bytes not written in the 64-bit data phase. Write data is transferred 4452 ** from the IWQ to the internal bus when data is available and the internal bus interface retains 4453 ** internal bus ownership. 4454 ** �E The internal bus interface stops transferring data from the current transaction to the internal 4455 ** bus when one of the following conditions becomes true: 4456 ** �X The internal bus initiator interface loses bus ownership. The ATU internal initiator 4457 ** terminates the transfer (initiator disconnection) at the next ADB (for the internal bus ADB 4458 ** is defined as a naturally aligned 128-byte boundary) and attempt to reacquire the bus to 4459 ** complete the delivery of remaining data using the same sequence ID but with the 4460 ** modified starting address and byte count. 4461 ** �X A Disconnect at Next ADB is signaled on the internal bus from the internal target. When 4462 ** the transaction in the IWQ completes at that ADB, the initiator returns to idle. When the 4463 ** transaction in the IWQ is not complete, the initiator attempts to reacquire the bus to 4464 ** complete the delivery of remaining data using the same sequence ID but with the 4465 ** modified starting address and byte count. 4466 ** �X A Single Data Phase Disconnect is signaled on the internal bus from the internal target. 4467 ** When the transaction in the IWQ needs only a single data phase, the master returns to idle. 4468 ** When the transaction in the IWQ is not complete, the initiator attempts to reacquire the 4469 ** bus to complete the delivery of remaining data using the same sequence ID but with the 4470 ** modified starting address and byte count. 4471 ** �X The data from the current transaction has completed (satisfaction of byte count). An 4472 ** initiator termination is performed and the bus returns to idle. 4473 ** �X A Master Abort is signaled on the internal bus. SERR# may be asserted on the PCI bus. 4474 ** Data is flushed from the IWQ. 4475 ***************************************************************** 4476 */ 4477 4478 /* 4479 ************************************************************************** 4480 ** Inbound Read Completions Data Parity Errors 4481 **======================================================================== 4482 ** As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode. 4483 ** When as the completer of a Split Read Request the ATU observes PERR# assertion during the split 4484 ** completion transaction, the ATU attempts to complete the transaction normally and no further 4485 ** action is taken. 4486 ************************************************************************** 4487 */ 4488 4489 /* 4490 ************************************************************************** 4491 ** Inbound Configuration Write Completion Message Data Parity Errors 4492 **======================================================================== 4493 ** As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode. 4494 ** When as the completer of a Configuration (Split) Write Request the ATU observes PERR# 4495 ** assertion during the split completion transaction, the ATU attempts to complete the transaction 4496 ** normally and no further action is taken. 4497 ************************************************************************** 4498 */ 4499 4500 /* 4501 ************************************************************************** 4502 ** Inbound Read Request Data Parity Errors 4503 **===================== Immediate Data Transfer ========================== 4504 ** As a target, the ATU may encounter this error when operating in the Conventional PCI or PCI-X modes. 4505 ** Inbound read data parity errors occur when read data delivered from the IRQ is detected as having 4506 ** bad parity by the initiator of the transaction who is receiving the data. The initiator may optionally 4507 ** report the error to the system by asserting PERR#. As a target device in this scenario, no action is 4508 ** required and no error bits are set. 4509 **=====================Split Response Termination========================= 4510 ** As a target, the ATU may encounter this error when operating in the PCI-X mode. 4511 ** Inbound read data parity errors occur during the Split Response Termination. The initiator may 4512 ** optionally report the error to the system by asserting PERR#. As a target device in this scenario, no 4513 ** action is required and no error bits are set. 4514 ************************************************************************** 4515 */ 4516 4517 /* 4518 ************************************************************************** 4519 ** Inbound Write Request Data Parity Errors 4520 **======================================================================== 4521 ** As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes. 4522 ** Data parity errors occurring during write operations received by the ATU may assert PERR# on 4523 ** the PCI Bus. When an error occurs, the ATU continues accepting data until the initiator of the write 4524 ** transaction completes or a queue fill condition is reached. Specifically, the following actions with 4525 ** the given constraints are taken by the ATU: 4526 ** �E PERR# is asserted two clocks cycles (three clock cycles when operating in the PCI-X mode) 4527 ** following the data phase in which the data parity error is detected on the bus. This is only 4528 ** done when the Parity Error Response bit in the ATUCMD is set. 4529 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4530 ** actions is taken: 4531 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4532 ** Detected Parity Error bit in the ATUISR. When set, no action. 4533 *************************************************************************** 4534 */ 4535 4536 /* 4537 *************************************************************************** 4538 ** Inbound Configuration Write Request 4539 ** ===================================================================== 4540 ** As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes. 4541 ** =============================================== 4542 ** Conventional PCI Mode 4543 ** =============================================== 4544 ** To allow for correct data parity calculations for delayed write transactions, the ATU delays the 4545 ** assertion of STOP# (signalling a Retry) until PAR is driven by the master. A parity error during a 4546 ** delayed write transaction (inbound configuration write cycle) can occur in any of the following 4547 ** parts of the transactions: 4548 ** �E During the initial Delayed Write Request cycle on the PCI bus when the ATU latches the 4549 ** address/command and data for delayed delivery to the internal configuration register. 4550 ** �E During the Delayed Write Completion cycle on the PCI bus when the ATU delivers the status 4551 ** of the operation back to the original master. 4552 ** The 80331 ATU PCI interface has the following responses to a delayed write parity error for 4553 ** inbound transactions during Delayed Write Request cycles with the given constraints: 4554 ** �E When the Parity Error Response bit in the ATUCMD is set, the ATU asserts TRDY# 4555 ** (disconnects with data) and two clock cycles later asserts PERR# notifying the initiator of the 4556 ** parity error. The delayed write cycle is not enqueued and forwarded to the internal bus. 4557 ** When the Parity Error Response bit in the ATUCMD is cleared, the ATU retries the 4558 ** transaction by asserting STOP# and enqueues the Delayed Write Request cycle to be 4559 ** forwarded to the internal bus. PERR# is not asserted. 4560 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4561 ** actions is taken: 4562 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4563 ** Detected Parity Error bit in the ATUISR. When set, no action. 4564 ** For the original write transaction to be completed, the initiator retries the transaction on the PCI 4565 ** bus and the ATU returns the status from the internal bus, completing the transaction. 4566 ** For the Delayed Write Completion transaction on the PCI bus where a data parity error occurs and 4567 ** therefore does not agree with the status being returned from the internal bus (i.e. status being 4568 ** returned is normal completion) the ATU performs the following actions with the given constraints: 4569 ** �E When the Parity Error Response Bit is set in the ATUCMD, the ATU asserts TRDY# 4570 ** (disconnects with data) and two clocks later asserts PERR#. The Delayed Completion cycle in 4571 ** the IDWQ remains since the data of retried command did not match the data within the queue. 4572 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4573 ** actions is taken: 4574 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4575 ** Detected Parity Error bit in the ATUISR. When set, no action. 4576 ** =================================================== 4577 ** PCI-X Mode 4578 ** =================================================== 4579 ** Data parity errors occurring during configuration write operations received by the ATU may cause 4580 ** PERR# assertion and delivery of a Split Completion Error Message on the PCI Bus. When an error 4581 ** occurs, the ATU accepts the write data and complete with a Split Response Termination. 4582 ** Specifically, the following actions with the given constraints are then taken by the ATU: 4583 ** �E When the Parity Error Response bit in the ATUCMD is set, PERR# is asserted three clocks 4584 ** cycles following the Split Response Termination in which the data parity error is detected on 4585 ** the bus. When the ATU asserts PERR#, additional actions is taken: 4586 ** �X A Split Write Data Parity Error message (with message class=2h - completer error and 4587 ** message index=01h - Split Write Data Parity Error) is initiated by the ATU on the PCI bus 4588 ** that addresses the requester of the configuration write. 4589 ** �X When the Initiated Split Completion Error Message Interrupt Mask in the ATUIMR is 4590 ** clear, set the Initiated Split Completion Error Message bit in the ATUISR. When set, no 4591 ** action. 4592 ** �X The Split Write Request is not enqueued and forwarded to the internal bus. 4593 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4594 ** actions is taken: 4595 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4596 ** Detected Parity Error bit in the ATUISR. When set, no action. 4597 ** 4598 *************************************************************************** 4599 */ 4600 4601 /* 4602 *************************************************************************** 4603 ** Split Completion Messages 4604 ** ======================================================================= 4605 ** As a target, the ATU may encounter this error when operating in the PCI-X mode. 4606 ** Data parity errors occurring during Split Completion Messages claimed by the ATU may assert 4607 ** PERR# (when enabled) or SERR# (when enabled) on the PCI Bus. When an error occurs, the 4608 ** ATU accepts the data and complete normally. Specifically, the following actions with the given 4609 ** constraints are taken by the ATU: 4610 ** �E PERR# is asserted three clocks cycles following the data phase in which the data parity error 4611 ** is detected on the bus. This is only done when the Parity Error Response bit in the ATUCMD 4612 ** is set. When the ATU asserts PERR#, additional actions is taken: 4613 ** �X The Master Parity Error bit in the ATUSR is set. 4614 ** �X When the ATU PCI Master Parity Error Interrupt Mask Bit in the ATUIMR is clear, set the 4615 ** PCI Master Parity Error bit in the ATUISR. When set, no action. 4616 ** �X When the SERR# Enable bit in the ATUCMD is set, and the Data Parity Error Recover 4617 ** Enable bit in the PCIXCMD register is clear, assert SERR#; otherwise no action is taken. 4618 ** When the ATU asserts SERR#, additional actions is taken: 4619 ** Set the SERR# Asserted bit in the ATUSR. 4620 ** When the ATU SERR# Asserted Interrupt Mask Bit in the ATUIMR is clear, set the 4621 ** SERR# Asserted bit in the ATUISR. When set, no action. 4622 ** When the ATU SERR# Detected Interrupt Enable Bit in the ATUCR is set, set the 4623 ** SERR# Detected bit in the ATUISR. When clear, no action. 4624 ** �E When the SCE bit (Split Completion Error -- bit 30 of the Completer Attributes) is set during 4625 ** the Attribute phase, the Received Split Completion Error Message bit in the PCIXSR is set. 4626 ** When the ATU sets this bit, additional actions is taken: 4627 ** �X When the ATU Received Split Completion Error Message Interrupt Mask bit in the 4628 ** ATUIMR is clear, set the Received Split Completion Error Message bit in the ATUISR. 4629 ** When set, no action. 4630 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4631 ** actions is taken: 4632 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4633 ** Detected Parity Error bit in the ATUISR. When set, no action. 4634 ** �E The transaction associated with the Split Completion Message is discarded. 4635 ** �E When the discarded transaction was a read, a completion error message (with message 4636 ** class=2h - completer error and message index=82h - PCI bus read parity error) is generated on 4637 ** the internal bus of the 80331. 4638 ***************************************************************************** 4639 */ 4640 4641 /* 4642 ****************************************************************************************************** 4643 ** Messaging Unit (MU) of the Intel R 80331 I/O processor (80331) 4644 ** ================================================================================================== 4645 ** The Messaging Unit (MU) transfers data between the PCI system and the 80331 4646 ** notifies the respective system when new data arrives. 4647 ** The PCI window for messaging transactions is always the first 4 Kbytes of the inbound translation. 4648 ** window defined by: 4649 ** 1.Inbound ATU Base Address Register 0 (IABAR0) 4650 ** 2.Inbound ATU Limit Register 0 (IALR0) 4651 ** All of the Messaging Unit errors are reported in the same manner as ATU errors. 4652 ** Error conditions and status can be found in : 4653 ** 1.ATUSR 4654 ** 2.ATUISR 4655 **==================================================================================================== 4656 ** Mechanism Quantity Assert PCI Interrupt Signals Generate I/O Processor Interrupt 4657 **---------------------------------------------------------------------------------------------------- 4658 ** Message Registers 2 Inbound Optional Optional 4659 ** 2 Outbound 4660 **---------------------------------------------------------------------------------------------------- 4661 ** Doorbell Registers 1 Inbound Optional Optional 4662 ** 1 Outbound 4663 **---------------------------------------------------------------------------------------------------- 4664 ** Circular Queues 4 Circular Queues Under certain conditions Under certain conditions 4665 **---------------------------------------------------------------------------------------------------- 4666 ** Index Registers 1004 32-bit Memory Locations No Optional 4667 **==================================================================================================== 4668 ** PCI Memory Map: First 4 Kbytes of the ATU Inbound PCI Address Space 4669 **==================================================================================================== 4670 ** 0000H Reserved 4671 ** 0004H Reserved 4672 ** 0008H Reserved 4673 ** 000CH Reserved 4674 **------------------------------------------------------------------------ 4675 ** 0010H Inbound Message Register 0 ] 4676 ** 0014H Inbound Message Register 1 ] 4677 ** 0018H Outbound Message Register 0 ] 4678 ** 001CH Outbound Message Register 1 ] 4 Message Registers 4679 **------------------------------------------------------------------------ 4680 ** 0020H Inbound Doorbell Register ] 4681 ** 0024H Inbound Interrupt Status Register ] 4682 ** 0028H Inbound Interrupt Mask Register ] 4683 ** 002CH Outbound Doorbell Register ] 4684 ** 0030H Outbound Interrupt Status Register ] 4685 ** 0034H Outbound Interrupt Mask Register ] 2 Doorbell Registers and 4 Interrupt Registers 4686 **------------------------------------------------------------------------ 4687 ** 0038H Reserved 4688 ** 003CH Reserved 4689 **------------------------------------------------------------------------ 4690 ** 0040H Inbound Queue Port ] 4691 ** 0044H Outbound Queue Port ] 2 Queue Ports 4692 **------------------------------------------------------------------------ 4693 ** 0048H Reserved 4694 ** 004CH Reserved 4695 **------------------------------------------------------------------------ 4696 ** 0050H ] 4697 ** : ] 4698 ** : Intel Xscale Microarchitecture Local Memory ] 4699 ** : ] 4700 ** 0FFCH ] 1004 Index Registers 4701 ******************************************************************************* 4702 */ 4703 /* 4704 ***************************************************************************** 4705 ** Theory of MU Operation 4706 ***************************************************************************** 4707 **-------------------- 4708 ** inbound_msgaddr0: 4709 ** inbound_msgaddr1: 4710 ** outbound_msgaddr0: 4711 ** outbound_msgaddr1: 4712 ** . The MU has four independent messaging mechanisms. 4713 ** There are four Message Registers that are similar to a combination of mailbox and doorbell registers. 4714 ** Each holds a 32-bit value and generates an interrupt when written. 4715 **-------------------- 4716 ** inbound_doorbell: 4717 ** outbound_doorbell: 4718 ** . The two Doorbell Registers support software interrupts. 4719 ** When a bit is set in a Doorbell Register, an interrupt is generated. 4720 **-------------------- 4721 ** inbound_queueport: 4722 ** outbound_queueport: 4723 ** 4724 ** 4725 ** . The Circular Queues support a message passing scheme that uses 4 circular queues. 4726 ** The 4 circular queues are implemented in 80331 local memory. 4727 ** Two queues are used for inbound messages and two are used for outbound messages. 4728 ** Interrupts may be generated when the queue is written. 4729 **-------------------- 4730 ** local_buffer 0x0050 ....0x0FFF 4731 ** . The Index Registers use a portion of the 80331 local memory to implement a large set of message registers. 4732 ** When one of the Index Registers is written, an interrupt is generated and the address of the register written is captured. 4733 ** Interrupt status for all interrupts is recorded in the Inbound Interrupt Status Register and the Outbound Interrupt Status Register. 4734 ** Each interrupt generated by the Messaging Unit can be masked. 4735 **-------------------- 4736 ** . Multi-DWORD PCI burst accesses are not supported by the Messaging Unit, 4737 ** with the exception of Multi-DWORD reads to the index registers. 4738 ** In Conventional mode: the MU terminates Multi-DWORD PCI transactions 4739 ** (other than index register reads) with a disconnect at the next Qword boundary, with the exception of queue ports. 4740 ** In PCI-X mode : the MU terminates a Multi-DWORD PCI read transaction with a Split Response 4741 ** and the data is returned through split completion transaction(s). 4742 ** however, when the burst request crosses into or through the range of offsets 40h to 4Ch 4743 ** (e.g., this includes the queue ports) the transaction is signaled target-abort immediately on the PCI bus. 4744 ** In PCI-X mode, Multi-DWORD PCI writes is signaled a Single-Data-Phase Disconnect 4745 ** which means that no data beyond the first Qword (Dword when the MU does not assert P_ACK64#) is written. 4746 **-------------------- 4747 ** . All registers needed to configure and control the Messaging Unit are memory-mapped registers. 4748 ** The MU uses the first 4 Kbytes of the inbound translation window in the Address Translation Unit (ATU). 4749 ** This PCI address window is used for PCI transactions that access the 80331 local memory. 4750 ** The PCI address of the inbound translation window is contained in the Inbound ATU Base Address Register. 4751 **-------------------- 4752 ** . From the PCI perspective, the Messaging Unit is part of the Address Translation Unit. 4753 ** The Messaging Unit uses the PCI configuration registers of the ATU for control and status information. 4754 ** The Messaging Unit must observe all PCI control bits in the ATU Command Register and ATU Configuration Register. 4755 ** The Messaging Unit reports all PCI errors in the ATU Status Register. 4756 **-------------------- 4757 ** . Parts of the Messaging Unit can be accessed as a 64-bit PCI device. 4758 ** The register interface, message registers, doorbell registers, 4759 ** and index registers returns a P_ACK64# in response to a P_REQ64# on the PCI interface. 4760 ** Up to 1 Qword of data can be read or written per transaction (except Index Register reads). 4761 ** The Inbound and Outbound Queue Ports are always 32-bit addresses and the MU does not assert P_ACK64# to offsets 40H and 44H. 4762 ************************************************************************** 4763 */ 4764 /* 4765 ************************************************************************** 4766 ** Message Registers 4767 ** ============================== 4768 ** . Messages can be sent and received by the 80331 through the use of the Message Registers. 4769 ** . When written, the message registers may cause an interrupt to be generated to either the Intel XScale core or the host processor. 4770 ** . Inbound messages are sent by the host processor and received by the 80331. 4771 ** Outbound messages are sent by the 80331 and received by the host processor. 4772 ** . The interrupt status for outbound messages is recorded in the Outbound Interrupt Status Register. 4773 ** Interrupt status for inbound messages is recorded in the Inbound Interrupt Status Register. 4774 ** 4775 ** Inbound Messages: 4776 ** ----------------- 4777 ** . When an inbound message register is written by an external PCI agent, an interrupt may be generated to the Intel XScale core. 4778 ** . The interrupt may be masked by the mask bits in the Inbound Interrupt Mask Register. 4779 ** . The Intel XScale core interrupt is recorded in the Inbound Interrupt Status Register. 4780 ** The interrupt causes the Inbound Message Interrupt bit to be set in the Inbound Interrupt Status Register. 4781 ** This is a Read/Clear bit that is set by the MU hardware and cleared by software. 4782 ** The interrupt is cleared when the Intel XScale core writes a value of 4783 ** 1 to the Inbound Message Interrupt bit in the Inbound Interrupt Status Register. 4784 ** ------------------------------------------------------------------------ 4785 ** Inbound Message Register - IMRx 4786 ** 4787 ** . There are two Inbound Message Registers: IMR0 and IMR1. 4788 ** . When the IMR register is written, an interrupt to the Intel XScale core may be generated. 4789 ** The interrupt is recorded in the Inbound Interrupt Status Register and may be masked 4790 ** by the Inbound Message Interrupt Mask bit in the Inbound Interrupt Mask Register. 4791 ** ----------------------------------------------------------------- 4792 ** Bit Default Description 4793 ** 31:00 0000 0000H Inbound Message - This is a 32-bit message written by an external PCI agent. 4794 ** When written, an interrupt to the Intel XScale core may be generated. 4795 ************************************************************************** 4796 */ 4797 #define ARCMSR_MU_INBOUND_MESSAGE_REG0 0x10 /*dword 0x13,0x12,0x11,0x10*/ 4798 #define ARCMSR_MU_INBOUND_MESSAGE_REG1 0x14 /*dword 0x17,0x16,0x15,0x14*/ 4799 /* 4800 ************************************************************************** 4801 ** Outbound Message Register - OMRx 4802 ** -------------------------------- 4803 ** There are two Outbound Message Registers: OMR0 and OMR1. When the OMR register is 4804 ** written, a PCI interrupt may be generated. The interrupt is recorded in the Outbound Interrupt 4805 ** Status Register and may be masked by the Outbound Message Interrupt Mask bit in the Outbound 4806 ** Interrupt Mask Register. 4807 ** 4808 ** Bit Default Description 4809 ** 31:00 00000000H Outbound Message - This is 32-bit message written by the Intel XScale core. When written, an 4810 ** interrupt may be generated on the PCI Interrupt pin determined by the ATU Interrupt Pin Register. 4811 ************************************************************************** 4812 */ 4813 #define ARCMSR_MU_OUTBOUND_MESSAGE_REG0 0x18 /*dword 0x1B,0x1A,0x19,0x18*/ 4814 #define ARCMSR_MU_OUTBOUND_MESSAGE_REG1 0x1C /*dword 0x1F,0x1E,0x1D,0x1C*/ 4815 /* 4816 ************************************************************************** 4817 ** Doorbell Registers 4818 ** ============================== 4819 ** There are two Doorbell Registers: 4820 ** Inbound Doorbell Register 4821 ** Outbound Doorbell Register 4822 ** The Inbound Doorbell Register allows external PCI agents to generate interrupts to the Intel R XScale core. 4823 ** The Outbound Doorbell Register allows the Intel R XScale core to generate a PCI interrupt. 4824 ** Both Doorbell Registers may generate interrupts whenever a bit in the register is set. 4825 ** 4826 ** Inbound Doorbells: 4827 ** ------------------ 4828 ** . When the Inbound Doorbell Register is written by an external PCI agent, an interrupt may be generated to the Intel R XScale core. 4829 ** An interrupt is generated when any of the bits in the doorbell register is written to a value of 1. 4830 ** Writing a value of 0 to any bit does not change the value of that bit and does not cause an interrupt to be generated. 4831 ** . Once a bit is set in the Inbound Doorbell Register, it cannot be cleared by any external PCI agent. 4832 ** The interrupt is recorded in the Inbound Interrupt Status Register. 4833 ** . The interrupt may be masked by the Inbound Doorbell Interrupt mask bit in the Inbound Interrupt Mask Register. 4834 ** When the mask bit is set for a particular bit, no interrupt is generated for that bit. 4835 ** The Inbound Interrupt Mask Register affects only the generation of the normal messaging unit interrupt 4836 ** and not the values written to the Inbound Doorbell Register. 4837 ** One bit in the Inbound Doorbell Register is reserved for an Error Doorbell interrupt. 4838 ** . The interrupt is cleared when the Intel R XScale core writes a value of 1 to the bits in the Inbound Doorbell Register that are set. 4839 ** Writing a value of 0 to any bit does not change the value of that bit and does not clear the interrupt. 4840 ** ------------------------------------------------------------------------ 4841 ** Inbound Doorbell Register - IDR 4842 ** 4843 ** . The Inbound Doorbell Register (IDR) is used to generate interrupts to the Intel XScale core. 4844 ** . Bit 31 is reserved for generating an Error Doorbell interrupt. 4845 ** When bit 31 is set, an Error interrupt may be generated to the Intel XScale core. 4846 ** All other bits, when set, cause the Normal Messaging Unit interrupt line of the Intel XScale core to be asserted, 4847 ** when the interrupt is not masked by the Inbound Doorbell Interrupt Mask bit in the Inbound Interrupt Mask Register. 4848 ** The bits in the IDR register can only be set by an external PCI agent and can only be cleared by the Intel XScale core. 4849 ** ------------------------------------------------------------------------ 4850 ** Bit Default Description 4851 ** 31 0 2 Error Interrupt - Generate an Error Interrupt to the Intel XScale core. 4852 ** 30:00 00000000H Normal Interrupt - When any bit is set, generate a Normal interrupt to the Intel XScale core. 4853 ** When all bits are clear, do not generate a Normal Interrupt. 4854 ************************************************************************** 4855 */ 4856 #define ARCMSR_MU_INBOUND_DOORBELL_REG 0x20 /*dword 0x23,0x22,0x21,0x20*/ 4857 /* 4858 ************************************************************************** 4859 ** Inbound Interrupt Status Register - IISR 4860 ** 4861 ** . The Inbound Interrupt Status Register (IISR) contains hardware interrupt status. 4862 ** It records the status of Intel XScale core interrupts generated by the Message Registers, Doorbell Registers, and the Circular Queues. 4863 ** All interrupts are routed to the Normal Messaging Unit interrupt input of the Intel XScale core, 4864 ** except for the Error Doorbell Interrupt and the Outbound Free Queue Full interrupt; 4865 ** these two are routed to the Messaging Unit Error interrupt input. 4866 ** The generation of interrupts recorded in the Inbound Interrupt Status Register 4867 ** may be masked by setting the corresponding bit in the Inbound Interrupt Mask Register. 4868 ** Some of the bits in this register are Read Only. 4869 ** For those bits, the interrupt must be cleared through another register. 4870 ** 4871 ** Bit Default Description 4872 ** 31:07 0000000H 0 2 Reserved 4873 ** 06 0 2 Index Register Interrupt - This bit is set by the MU hardware 4874 ** when an Index Register has been written after a PCI transaction. 4875 ** 05 0 2 Outbound Free Queue Full Interrupt - This bit is set 4876 ** when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full. 4877 ** An Error interrupt is generated for this condition. 4878 ** 04 0 2 Inbound Post Queue Interrupt - This bit is set by the MU hardware when the Inbound Post Queue has been written. 4879 ** Once cleared, an interrupt does NOT be generated 4880 ** when the head and tail pointers remain unequal (i.e. queue status is Not Empty). 4881 ** Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared, 4882 ** software must retain the information that the Inbound Post queue status is not empty. 4883 ** NOTE: This interrupt is provided with dedicated support in the 80331 Interrupt Controller. 4884 ** 03 0 2 Error Doorbell Interrupt - This bit is set when the Error Interrupt of the Inbound Doorbell Register is set. 4885 ** To clear this bit (and the interrupt), the Error Interrupt bit of the Inbound Doorbell Register must be clear. 4886 ** 02 0 2 Inbound Doorbell Interrupt - This bit is set when at least one 4887 ** Normal Interrupt bit in the Inbound Doorbell Register is set. 4888 ** To clear this bit (and the interrupt), the Normal Interrupt bits in the Inbound Doorbell Register must all be clear. 4889 ** 01 0 2 Inbound Message 1 Interrupt - This bit is set by the MU hardware when the Inbound Message 1 Register has been written. 4890 ** 00 0 2 Inbound Message 0 Interrupt - This bit is set by the MU hardware when the Inbound Message 0 Register has been written. 4891 ************************************************************************** 4892 */ 4893 #define ARCMSR_MU_INBOUND_INTERRUPT_STATUS_REG 0x24 /*dword 0x27,0x26,0x25,0x24*/ 4894 #define ARCMSR_MU_INBOUND_INDEX_INT 0x40 4895 #define ARCMSR_MU_INBOUND_QUEUEFULL_INT 0x20 4896 #define ARCMSR_MU_INBOUND_POSTQUEUE_INT 0x10 4897 #define ARCMSR_MU_INBOUND_ERROR_DOORBELL_INT 0x08 4898 #define ARCMSR_MU_INBOUND_DOORBELL_INT 0x04 4899 #define ARCMSR_MU_INBOUND_MESSAGE1_INT 0x02 4900 #define ARCMSR_MU_INBOUND_MESSAGE0_INT 0x01 4901 /* 4902 ************************************************************************** 4903 ** Inbound Interrupt Mask Register - IIMR 4904 ** 4905 ** . The Inbound Interrupt Mask Register (IIMR) provides the ability to mask Intel XScale core interrupts generated by the Messaging Unit. 4906 ** Each bit in the Mask register corresponds to an interrupt bit in the Inbound Interrupt Status Register. 4907 ** Setting or clearing bits in this register does not affect the Inbound Interrupt Status Register. 4908 ** They only affect the generation of the Intel XScale core interrupt. 4909 ** ------------------------------------------------------------------------ 4910 ** Bit Default Description 4911 ** 31:07 000000H 0 2 Reserved 4912 ** 06 0 2 Index Register Interrupt Mask - When set, this bit masks the interrupt generated by the MU hardware 4913 ** when an Index Register has been written after a PCI transaction. 4914 ** 05 0 2 Outbound Free Queue Full Interrupt Mask - When set, this bit masks the Error interrupt generated 4915 ** when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full. 4916 ** 04 0 2 Inbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated 4917 ** by the MU hardware when the Inbound Post Queue has been written. 4918 ** 03 0 2 Error Doorbell Interrupt Mask - When set, this bit masks the Error Interrupt 4919 ** when the Error Interrupt bit of the Inbound Doorbell Register is set. 4920 ** 02 0 2 Inbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated 4921 ** when at least one Normal Interrupt bit in the Inbound Doorbell Register is set. 4922 ** 01 0 2 Inbound Message 1 Interrupt Mask - When set, this bit masks the Inbound Message 1 4923 ** Interrupt generated by a write to the Inbound Message 1 Register. 4924 ** 00 0 2 Inbound Message 0 Interrupt Mask - When set, 4925 ** this bit masks the Inbound Message 0 Interrupt generated by a write to the Inbound Message 0 Register. 4926 ************************************************************************** 4927 */ 4928 #define ARCMSR_MU_INBOUND_INTERRUPT_MASK_REG 0x28 /*dword 0x2B,0x2A,0x29,0x28*/ 4929 #define ARCMSR_MU_INBOUND_INDEX_INTMASKENABLE 0x40 4930 #define ARCMSR_MU_INBOUND_QUEUEFULL_INTMASKENABLE 0x20 4931 #define ARCMSR_MU_INBOUND_POSTQUEUE_INTMASKENABLE 0x10 4932 #define ARCMSR_MU_INBOUND_DOORBELL_ERROR_INTMASKENABLE 0x08 4933 #define ARCMSR_MU_INBOUND_DOORBELL_INTMASKENABLE 0x04 4934 #define ARCMSR_MU_INBOUND_MESSAGE1_INTMASKENABLE 0x02 4935 #define ARCMSR_MU_INBOUND_MESSAGE0_INTMASKENABLE 0x01 4936 /* 4937 ************************************************************************** 4938 ** Outbound Doorbell Register - ODR 4939 ** 4940 ** The Outbound Doorbell Register (ODR) allows software interrupt generation. It allows the Intel 4941 ** XScale core to generate PCI interrupts to the host processor by writing to this register. The 4942 ** generation of PCI interrupts through the Outbound Doorbell Register may be masked by setting the 4943 ** Outbound Doorbell Interrupt Mask bit in the Outbound Interrupt Mask Register. 4944 ** The Software Interrupt bits in this register can only be set by the Intel XScale core and can only 4945 ** be cleared by an external PCI agent. 4946 ** ---------------------------------------------------------------------- 4947 ** Bit Default Description 4948 ** 31 0 2 Reserved 4949 ** 30 0 2 Reserved. 4950 ** 29 0 2 Reserved 4951 ** 28 0000 0000H PCI Interrupt - When set, this bit causes the P_INTC# interrupt output 4952 ** (P_INTA# with BRG_EN and ARB_EN straps low) 4953 ** signal to be asserted or a Message-signaled Interrupt is generated (when enabled). 4954 ** When this bit is cleared, the P_INTC# interrupt output 4955 ** (P_INTA# with BRG_EN and ARB_EN straps low) 4956 ** signal is deasserted. 4957 ** 27:00 000 0000H Software Interrupts - When any bit is set the P_INTC# interrupt output 4958 ** (P_INTA# with BRG_EN and ARB_EN straps low) 4959 ** signal is asserted or a Message-signaled Interrupt is generated (when enabled). 4960 ** When all bits are cleared, the P_INTC# interrupt output (P_INTA# with BRG_EN and ARB_EN straps low) 4961 ** signal is deasserted. 4962 ************************************************************************** 4963 */ 4964 #define ARCMSR_MU_OUTBOUND_DOORBELL_REG 0x2C /*dword 0x2F,0x2E,0x2D,0x2C*/ 4965 /* 4966 ************************************************************************** 4967 ** Outbound Interrupt Status Register - OISR 4968 ** 4969 ** The Outbound Interrupt Status Register (OISR) contains hardware interrupt status. It records the 4970 ** status of PCI interrupts generated by the Message Registers, Doorbell Registers, and the Circular 4971 ** Queues. The generation of PCI interrupts recorded in the Outbound Interrupt Status Register may 4972 ** be masked by setting the corresponding bit in the Outbound Interrupt Mask Register. Some of the 4973 ** bits in this register are Read Only. For those bits, the interrupt must be cleared through another 4974 ** register. 4975 ** ---------------------------------------------------------------------- 4976 ** Bit Default Description 4977 ** 31:05 000000H 000 2 Reserved 4978 ** 04 0 2 PCI Interrupt - This bit is set when the PCI Interrupt bit (bit 28) is set in the Outbound Doorbell Register. 4979 ** To clear this bit (and the interrupt), the PCI Interrupt bit must be cleared. 4980 ** 03 0 2 Outbound Post Queue Interrupt - This bit is set when data in the prefetch buffer is valid. This bit is 4981 ** cleared when any prefetch data has been read from the Outbound Queue Port. 4982 ** 02 0 2 Outbound Doorbell Interrupt - This bit is set when at least one Software Interrupt bit in the Outbound 4983 ** Doorbell Register is set. To clear this bit (and the interrupt), the Software Interrupt bits in the Outbound 4984 ** Doorbell Register must all be clear. 4985 ** 01 0 2 Outbound Message 1 Interrupt - This bit is set by the MU when the Outbound Message 1 Register is 4986 ** written. Clearing this bit clears the interrupt. 4987 ** 00 0 2 Outbound Message 0 Interrupt - This bit is set by the MU when the Outbound Message 0 Register is 4988 ** written. Clearing this bit clears the interrupt. 4989 ************************************************************************** 4990 */ 4991 #define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30 /*dword 0x33,0x32,0x31,0x30*/ 4992 #define ARCMSR_MU_OUTBOUND_PCI_INT 0x10 4993 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08 4994 #define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04 4995 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02 4996 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01 4997 /* 4998 ************************************************************************** 4999 ** Outbound Interrupt Mask Register - OIMR 5000 ** The Outbound Interrupt Mask Register (OIMR) provides the ability to mask outbound PCI 5001 ** interrupts generated by the Messaging Unit. Each bit in the mask register corresponds to a 5002 ** hardware interrupt bit in the Outbound Interrupt Status Register. When the bit is set, the PCI 5003 ** interrupt is not generated. When the bit is clear, the interrupt is allowed to be generated. 5004 ** Setting or clearing bits in this register does not affect the Outbound Interrupt Status Register. They 5005 ** only affect the generation of the PCI interrupt. 5006 ** ---------------------------------------------------------------------- 5007 ** Bit Default Description 5008 ** 31:05 000000H Reserved 5009 ** 04 0 2 PCI Interrupt Mask - When set, this bit masks the interrupt generation when the PCI Interrupt bit (bit 28) 5010 ** in the Outbound Doorbell Register is set. 5011 ** 03 0 2 Outbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated when data in 5012 ** the prefetch buffer is valid. 5013 ** 02 0 2 Outbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated by the Outbound 5014 ** Doorbell Register. 5015 ** 01 0 2 Outbound Message 1 Interrupt Mask - When set, this bit masks the Outbound Message 1 Interrupt 5016 ** generated by a write to the Outbound Message 1 Register. 5017 ** 00 0 2 Outbound Message 0 Interrupt Mask- When set, this bit masks the Outbound Message 0 Interrupt 5018 ** generated by a write to the Outbound Message 0 Register. 5019 ************************************************************************** 5020 */ 5021 #define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34 /*dword 0x37,0x36,0x35,0x34*/ 5022 #define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10 5023 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08 5024 #define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04 5025 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02 5026 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01 5027 #define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F 5028 /* 5029 ************************************************************************** 5030 ** 5031 ************************************************************************** 5032 */ 5033 #define ARCMSR_MU_INBOUND_QUEUE_PORT_REG 0x40 /*dword 0x43,0x42,0x41,0x40*/ 5034 #define ARCMSR_MU_OUTBOUND_QUEUE_PORT_REG 0x44 /*dword 0x47,0x46,0x45,0x44*/ 5035 /* 5036 ************************************************************************** 5037 ** Circular Queues 5038 ** ====================================================================== 5039 ** The MU implements four circular queues. There are 2 inbound queues and 2 outbound queues. In 5040 ** this case, inbound and outbound refer to the direction of the flow of posted messages. 5041 ** Inbound messages are either: 5042 ** �E posted messages by other processors for the Intel XScale core to process or 5043 ** �E free (or empty) messages that can be reused by other processors. 5044 ** Outbound messages are either: 5045 ** �E posted messages by the Intel XScale core for other processors to process or 5046 ** �E free (or empty) messages that can be reused by the Intel XScale core. 5047 ** Therefore, free inbound messages flow away from the 80331 and free outbound messages flow toward the 80331. 5048 ** The four Circular Queues are used to pass messages in the following manner. 5049 ** . The two inbound queues are used to handle inbound messages 5050 ** and the two outbound queues are used to handle outbound messages. 5051 ** . One of the inbound queues is designated the Free queue and it contains inbound free messages. 5052 ** The other inbound queue is designated the Post queue and it contains inbound posted messages. 5053 ** Similarly, one of the outbound queues is designated the Free queue and the other outbound queue is designated the Post queue. 5054 ** 5055 ** ============================================================================================================= 5056 ** Circular Queue Summary 5057 ** _____________________________________________________________________________________________________________ 5058 ** | Queue Name | Purpose | Action on PCI Interface| 5059 ** |______________________|____________________________________________________________|_________________________| 5060 ** |Inbound Post Queue | Queue for inbound messages from other processors | Written | 5061 ** | | waiting to be processed by the 80331 | | 5062 ** |Inbound Free Queue | Queue for empty inbound messages from the 80331 | Read | 5063 ** | | available for use by other processors | | 5064 ** |Outbound Post Queue | Queue for outbound messages from the 80331 | Read | 5065 ** | | that are being posted to the other processors | | 5066 ** |Outbound Free Queue | Queue for empty outbound messages from other processors | Written | 5067 ** | | available for use by the 80331 | | 5068 ** |______________________|____________________________________________________________|_________________________| 5069 ** 5070 ** . The two inbound queues allow the host processor to post inbound messages for the 80331 in one 5071 ** queue and to receive free messages returning from the 80331. 5072 ** The host processor posts inbound messages, 5073 ** the Intel XScale core receives the posted message and when it is finished with the message, 5074 ** places it back on the inbound free queue for reuse by the host processor. 5075 ** 5076 ** The circular queues are accessed by external PCI agents through two port locations in the PCI 5077 ** address space: 5078 ** Inbound Queue Port 5079 ** and Outbound Queue Port. 5080 ** The Inbound Queue Port is used by external PCI agents to read the Inbound Free Queue and write the Inbound Post Queue. 5081 ** The Outbound Queue Port is used by external PCI agents to read the Outbound Post Queue and write the Outbound Free Queue. 5082 ** Note that a PCI transaction to the inbound or outbound queue ports with null byte enables (P_C/BE[3:0]#=1111 2 ) 5083 ** does not cause the MU hardware to increment the queue pointers. 5084 ** This is treated as when the PCI transaction did not occur. 5085 ** The Inbound and Outbound Queue Ports never respond with P_ACK64# on the PCI interface. 5086 ** ====================================================================================== 5087 ** Overview of Circular Queue Operation 5088 ** ====================================================================================== 5089 ** . The data storage for the circular queues must be provided by the 80331 local memory. 5090 ** . The base address of the circular queues is contained in the Queue Base Address Register. 5091 ** Each entry in the queue is a 32-bit data value. 5092 ** . Each read from or write to the queue may access only one queue entry. 5093 ** . Multi-DWORD accesses to the circular queues are not allowed. 5094 ** Sub-DWORD accesses are promoted to DWORD accesses. 5095 ** . Each circular queue has a head pointer and a tail pointer. 5096 ** The pointers are offsets from the Queue Base Address. 5097 ** . Writes to a queue occur at the head of the queue and reads occur from the tail. 5098 ** The head and tail pointers are incremented by either the Intel XScale core or the Messaging Unit hardware. 5099 ** Which unit maintains the pointer is determined by the writer of the queue. 5100 ** More details about the pointers are given in the queue descriptions below. 5101 ** The pointers are incremented after the queue access. 5102 ** Both pointers wrap around to the first address of the circular queue when they reach the circular queue size. 5103 ** 5104 ** Messaging Unit... 5105 ** 5106 ** The Messaging Unit generates an interrupt to the Intel XScale core or generate a PCI interrupt under certain conditions. 5107 ** . In general, when a Post queue is written, an interrupt is generated to notify the receiver that a message was posted. 5108 ** The size of each circular queue can range from 4K entries (16 Kbytes) to 64K entries (256 Kbytes). 5109 ** . All four queues must be the same size and may be contiguous. 5110 ** Therefore, the total amount of local memory needed by the circular queues ranges from 64 Kbytes to 1 Mbytes. 5111 ** The Queue size is determined by the Queue Size field in the MU Configuration Register. 5112 ** . There is one base address for all four queues. 5113 ** It is stored in the Queue Base Address Register (QBAR). 5114 ** The starting addresses of each queue is based on the Queue Base Address and the Queue Size field. 5115 ** here shows an example of how the circular queues should be set up based on the 5116 ** Intelligent I/O (I 2 O) Architecture Specification. 5117 ** Other ordering of the circular queues is possible. 5118 ** 5119 ** Queue Starting Address 5120 ** Inbound Free Queue QBAR 5121 ** Inbound Post Queue QBAR + Queue Size 5122 ** Outbound Post Queue QBAR + 2 * Queue Size 5123 ** Outbound Free Queue QBAR + 3 * Queue Size 5124 ** =================================================================================== 5125 ** Inbound Post Queue 5126 ** ------------------ 5127 ** The Inbound Post Queue holds posted messages placed there by other processors for the Intel XScale core to process. 5128 ** This queue is read from the queue tail by the Intel XScale core. It is written to the queue head by external PCI agents. 5129 ** The tail pointer is maintained by the Intel XScale core. The head pointer is maintained by the MU hardware. 5130 ** For a PCI write transaction that accesses the Inbound Queue Port, 5131 ** the MU writes the data to the local memory location address in the Inbound Post Head Pointer Register. 5132 ** When the data written to the Inbound Queue Port is written to local memory, the MU hardware increments the Inbound Post Head Pointer Register. 5133 ** An Intel XScale core interrupt may be generated when the Inbound Post Queue is written. 5134 ** The Inbound Post Queue Interrupt bit in the Inbound Interrupt Status Register indicates the interrupt status. 5135 ** The interrupt is cleared when the Inbound Post Queue Interrupt bit is cleared. 5136 ** The interrupt can be masked by the Inbound Interrupt Mask Register. 5137 ** Software must be aware of the state of the Inbound Post Queue Interrupt Mask bit to guarantee 5138 ** that the full condition is recognized by the core processor. 5139 ** In addition, to guarantee that the queue does not get overwritten, 5140 ** software must process messages from the tail of the queue before incrementing the tail pointer and clearing this interrupt. 5141 ** Once cleared, an interrupt is NOT generated when the head and tail pointers remain unequal (i.e. queue status is Not Empty). 5142 ** Only a new message posting the in the inbound queue generates a new interrupt. 5143 ** Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared, 5144 ** software must retain the information that the Inbound Post queue status. 5145 ** From the time that the PCI write transaction is received until the data is written 5146 ** in local memory and the Inbound Post Head Pointer Register is incremented, 5147 ** any PCI transaction that attempts to access the Inbound Post Queue Port is signalled a Retry. 5148 ** The Intel XScale core may read messages from the Inbound Post Queue 5149 ** by reading the data from the local memory location pointed to by the Inbound Post Tail Pointer Register. 5150 ** The Intel XScale core must then increment the Inbound Post Tail Pointer Register. 5151 ** When the Inbound Post Queue is full (head and tail pointers are equal and the head pointer was last updated by hardware), 5152 ** the hardware retries any PCI writes until a slot in the queue becomes available. 5153 ** A slot in the post queue becomes available by the Intel XScale core incrementing the tail pointer. 5154 ** =================================================================================== 5155 ** Inbound Free Queue 5156 ** ------------------ 5157 ** The Inbound Free Queue holds free inbound messages placed there by the Intel XScale core for other processors to use. 5158 ** This queue is read from the queue tail by external PCI agents. 5159 ** It is written to the queue head by the Intel XScale core. 5160 ** The tail pointer is maintained by the MU hardware. 5161 ** The head pointer is maintained by the Intel XScale core. 5162 ** For a PCI read transaction that accesses the Inbound Queue Port, 5163 ** the MU attempts to read the data at the local memory address in the Inbound Free Tail Pointer. 5164 ** When the queue is not empty (head and tail pointers are not equal) 5165 ** or full (head and tail pointers are equal but the head pointer was last written by software), the data is returned. 5166 ** When the queue is empty (head and tail pointers are equal and the head pointer was last updated by hardware), 5167 ** the value of -1 (FFFF.FFFFH) is returned. 5168 ** When the queue was not empty and the MU succeeded in returning the data at the tail, 5169 ** the MU hardware must increment the value in the Inbound Free Tail Pointer Register. 5170 ** To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate accesses to the Inbound Free Queue. 5171 ** The MU hardware prefetches the data at the tail of the Inbound Free Queue and load it into an internal prefetch register. 5172 ** When the PCI read access occurs, the data is read directly from the prefetch register. 5173 ** The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register 5174 ** when the head and tail pointers are equal and the queue is empty. 5175 ** In order to update the prefetch register when messages are added to the queue and it becomes non-empty, 5176 ** the prefetch mechanism automatically starts a prefetch when the prefetch register contains FFFF.FFFFH 5177 ** and the Inbound Free Head Pointer Register is written. 5178 ** The Intel XScale core needs to update the Inbound Free Head Pointer Register when it adds messages to the queue. 5179 ** A prefetch must appear atomic from the perspective of the external PCI agent. 5180 ** When a prefetch is started, any PCI transaction that attempts to access the Inbound Free Queue is signalled a Retry until the prefetch is completed. 5181 ** The Intel XScale core may place messages in the Inbound Free Queue by writing the data to the 5182 ** local memory location pointed to by the Inbound Free Head Pointer Register. 5183 ** The processor must then increment the Inbound Free Head Pointer Register. 5184 ** ================================================================================== 5185 ** Outbound Post Queue 5186 ** ------------------- 5187 ** The Outbound Post Queue holds outbound posted messages placed there by the Intel XScale 5188 ** core for other processors to process. This queue is read from the queue tail by external PCI agents. 5189 ** It is written to the queue head by the Intel XScale core. The tail pointer is maintained by the 5190 ** MU hardware. The head pointer is maintained by the Intel XScale core. 5191 ** For a PCI read transaction that accesses the Outbound Queue Port, the MU attempts to read the 5192 ** data at the local memory address in the Outbound Post Tail Pointer Register. When the queue is not 5193 ** empty (head and tail pointers are not equal) or full (head and tail pointers are equal but the head 5194 ** pointer was last written by software), the data is returned. When the queue is empty (head and tail 5195 ** pointers are equal and the head pointer was last updated by hardware), the value of -1 5196 ** (FFFF.FFFFH) is returned. When the queue was not empty and the MU succeeded in returning the 5197 ** data at the tail, the MU hardware must increment the value in the Outbound Post Tail Pointer 5198 ** Register. 5199 ** To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate 5200 ** accesses to the Outbound Post Queue. The MU hardware prefetches the data at the tail of the 5201 ** Outbound Post Queue and load it into an internal prefetch register. When the PCI read access 5202 ** occurs, the data is read directly from the prefetch register. 5203 ** The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register when the head 5204 ** and tail pointers are equal and the queue is empty. In order to update the prefetch register when 5205 ** messages are added to the queue and it becomes non-empty, the prefetch mechanism automatically 5206 ** starts a prefetch when the prefetch register contains FFFF.FFFFH and the Outbound Post Head 5207 ** Pointer Register is written. The Intel XScale core needs to update the Outbound Post Head 5208 ** Pointer Register when it adds messages to the queue. 5209 ** A prefetch must appear atomic from the perspective of the external PCI agent. When a prefetch is 5210 ** started, any PCI transaction that attempts to access the Outbound Post Queue is signalled a Retry 5211 ** until the prefetch is completed. 5212 ** A PCI interrupt may be generated when data in the prefetch buffer is valid. When the prefetch 5213 ** queue is clear, no interrupt is generated. The Outbound Post Queue Interrupt bit in the Outbound 5214 ** Interrupt Status Register shall indicate the status of the prefetch buffer data and therefore the 5215 ** interrupt status. The interrupt is cleared when any prefetched data has been read from the Outbound 5216 ** Queue Port. The interrupt can be masked by the Outbound Interrupt Mask Register. 5217 ** The Intel XScale core may place messages in the Outbound Post Queue by writing the data to 5218 ** the local memory address in the Outbound Post Head Pointer Register. The processor must then 5219 ** increment the Outbound Post Head Pointer Register. 5220 ** ================================================== 5221 ** Outbound Free Queue 5222 ** ----------------------- 5223 ** The Outbound Free Queue holds free messages placed there by other processors for the Intel 5224 ** XScale core to use. This queue is read from the queue tail by the Intel XScale core. It is 5225 ** written to the queue head by external PCI agents. The tail pointer is maintained by the Intel 5226 ** XScale core. The head pointer is maintained by the MU hardware. 5227 ** For a PCI write transaction that accesses the Outbound Queue Port, the MU writes the data to the 5228 ** local memory address in the Outbound Free Head Pointer Register. When the data written to the 5229 ** Outbound Queue Port is written to local memory, the MU hardware increments the Outbound Free 5230 ** Head Pointer Register. 5231 ** When the head pointer and the tail pointer become equal and the queue is full, the MU may signal 5232 ** an interrupt to the Intel XScale core to register the queue full condition. This interrupt is 5233 ** recorded in the Inbound Interrupt Status Register. The interrupt is cleared when the Outbound Free 5234 ** Queue Full Interrupt bit is cleared and not by writing to the head or tail pointers. The interrupt can 5235 ** be masked by the Inbound Interrupt Mask Register. Software must be aware of the state of the 5236 ** Outbound Free Queue Interrupt Mask bit to guarantee that the full condition is recognized by the 5237 ** core processor. 5238 ** From the time that a PCI write transaction is received until the data is written in local memory and 5239 ** the Outbound Free Head Pointer Register is incremented, any PCI transaction that attempts to 5240 ** access the Outbound Free Queue Port is signalled a retry. 5241 ** The Intel XScale core may read messages from the Outbound Free Queue by reading the data 5242 ** from the local memory address in the Outbound Free Tail Pointer Register. The processor must 5243 ** then increment the Outbound Free Tail Pointer Register. When the Outbound Free Queue is full, 5244 ** the hardware must retry any PCI writes until a slot in the queue becomes available. 5245 ** 5246 ** ================================================================================== 5247 ** Circular Queue Summary 5248 ** ---------------------- 5249 ** ________________________________________________________________________________________________________________________________________________ 5250 ** | Queue Name | PCI Port |Generate PCI Interrupt |Generate Intel Xscale Core Interrupt|Head Pointer maintained by|Tail Pointer maintained by| 5251 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 5252 ** |Inbound Post | Inbound Queue | | | | | 5253 ** | Queue | Port | NO | Yes, when queue is written | MU hardware | Intel XScale | 5254 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 5255 ** |Inbound Free | Inbound Queue | | | | | 5256 ** | Queue | Port | NO | NO | Intel XScale | MU hardware | 5257 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 5258 ** ================================================================================== 5259 ** Circular Queue Status Summary 5260 ** ---------------------- 5261 ** ____________________________________________________________________________________________________ 5262 ** | Queue Name | Queue Status | Head & Tail Pointer | Last Pointer Update | 5263 ** |_____________________|________________|_____________________|_______________________________________| 5264 ** | Inbound Post Queue | Empty | Equal | Tail pointer last updated by software | 5265 ** |_____________________|________________|_____________________|_______________________________________| 5266 ** | Inbound Free Queue | Empty | Equal | Head pointer last updated by hardware | 5267 ** |_____________________|________________|_____________________|_______________________________________| 5268 ************************************************************************** 5269 */ 5270 5271 /* 5272 ************************************************************************** 5273 ** Index Registers 5274 ** ======================== 5275 ** . The Index Registers are a set of 1004 registers that when written by an external PCI agent can generate an interrupt to the Intel XScale core. 5276 ** These registers are for inbound messages only. 5277 ** The interrupt is recorded in the Inbound Interrupt Status Register. 5278 ** The storage for the Index Registers is allocated from the 80331 local memory. 5279 ** PCI write accesses to the Index Registers write the data to local memory. 5280 ** PCI read accesses to the Index Registers read the data from local memory. 5281 ** . The local memory used for the Index Registers ranges from Inbound ATU Translate Value Register + 050H 5282 ** to Inbound ATU Translate Value Register + FFFH. 5283 ** . The address of the first write access is stored in the Index Address Register. 5284 ** This register is written during the earliest write access and provides a means to determine which Index Register was written. 5285 ** Once updated by the MU, the Index Address Register is not updated until the Index Register 5286 ** Interrupt bit in the Inbound Interrupt Status Register is cleared. 5287 ** . When the interrupt is cleared, the Index Address Register is re-enabled and stores the address of the next Index Register write access. 5288 ** Writes by the Intel XScale core to the local memory used by the Index Registers 5289 ** does not cause an interrupt and does not update the Index Address Register. 5290 ** . The index registers can be accessed with Multi-DWORD reads and single QWORD aligned writes. 5291 ************************************************************************** 5292 */ 5293 /* 5294 ************************************************************************** 5295 ** Messaging Unit Internal Bus Memory Map 5296 ** ======================================= 5297 ** Internal Bus Address___Register Description (Name)____________________|_PCI Configuration Space Register Number_ 5298 ** FFFF E300H reserved | 5299 ** .. .. | 5300 ** FFFF E30CH reserved | 5301 ** FFFF E310H Inbound Message Register 0 | Available through 5302 ** FFFF E314H Inbound Message Register 1 | ATU Inbound Translation Window 5303 ** FFFF E318H Outbound Message Register 0 | 5304 ** FFFF E31CH Outbound Message Register 1 | or 5305 ** FFFF E320H Inbound Doorbell Register | 5306 ** FFFF E324H Inbound Interrupt Status Register | must translate PCI address to 5307 ** FFFF E328H Inbound Interrupt Mask Register | the Intel Xscale Core 5308 ** FFFF E32CH Outbound Doorbell Register | Memory-Mapped Address 5309 ** FFFF E330H Outbound Interrupt Status Register | 5310 ** FFFF E334H Outbound Interrupt Mask Register | 5311 ** ______________________________________________________________________|________________________________________ 5312 ** FFFF E338H reserved | 5313 ** FFFF E33CH reserved | 5314 ** FFFF E340H reserved | 5315 ** FFFF E344H reserved | 5316 ** FFFF E348H reserved | 5317 ** FFFF E34CH reserved | 5318 ** FFFF E350H MU Configuration Register | 5319 ** FFFF E354H Queue Base Address Register | 5320 ** FFFF E358H reserved | 5321 ** FFFF E35CH reserved | must translate PCI address to 5322 ** FFFF E360H Inbound Free Head Pointer Register | the Intel Xscale Core 5323 ** FFFF E364H Inbound Free Tail Pointer Register | Memory-Mapped Address 5324 ** FFFF E368H Inbound Post Head pointer Register | 5325 ** FFFF E36CH Inbound Post Tail Pointer Register | 5326 ** FFFF E370H Outbound Free Head Pointer Register | 5327 ** FFFF E374H Outbound Free Tail Pointer Register | 5328 ** FFFF E378H Outbound Post Head pointer Register | 5329 ** FFFF E37CH Outbound Post Tail Pointer Register | 5330 ** FFFF E380H Index Address Register | 5331 ** FFFF E384H reserved | 5332 ** .. .. | 5333 ** FFFF E3FCH reserved | 5334 ** ______________________________________________________________________|_______________________________________ 5335 ************************************************************************** 5336 */ 5337 /* 5338 ************************************************************************** 5339 ** MU Configuration Register - MUCR FFFF.E350H 5340 ** 5341 ** . The MU Configuration Register (MUCR) contains the Circular Queue Enable bit and the size of one Circular Queue. 5342 ** . The Circular Queue Enable bit enables or disables the Circular Queues. 5343 ** The Circular Queues are disabled at reset to allow the software to initialize the head 5344 ** and tail pointer registers before any PCI accesses to the Queue Ports. 5345 ** . Each Circular Queue may range from 4 K entries (16 Kbytes) to 64 K entries (256 Kbytes) and there are four Circular Queues. 5346 ** ------------------------------------------------------------------------ 5347 ** Bit Default Description 5348 ** 31:06 000000H 00 2 Reserved 5349 ** 05:01 00001 2 Circular Queue Size - This field determines the size of each Circular Queue. 5350 ** All four queues are the same size. 5351 ** �E 00001 2 - 4K Entries (16 Kbytes) 5352 ** �E 00010 2 - 8K Entries (32 Kbytes) 5353 ** �E 00100 2 - 16K Entries (64 Kbytes) 5354 ** �E 01000 2 - 32K Entries (128 Kbytes) 5355 ** �E 10000 2 - 64K Entries (256 Kbytes) 5356 ** 00 0 2 Circular Queue Enable - This bit enables or disables the Circular Queues. When clear the Circular 5357 ** Queues are disabled, however the MU accepts PCI accesses to the Circular Queue Ports but ignores 5358 ** the data for Writes and return FFFF.FFFFH for Reads. Interrupts are not generated to the core when 5359 ** disabled. When set, the Circular Queues are fully enabled. 5360 ************************************************************************** 5361 */ 5362 #define ARCMSR_MU_CONFIGURATION_REG 0xFFFFE350 5363 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE64K 0x0020 5364 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE32K 0x0010 5365 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE16K 0x0008 5366 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE8K 0x0004 5367 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE4K 0x0002 5368 #define ARCMSR_MU_CIRCULAR_QUEUE_ENABLE 0x0001 /*0:disable 1:enable*/ 5369 /* 5370 ************************************************************************** 5371 ** Queue Base Address Register - QBAR 5372 ** 5373 ** . The Queue Base Address Register (QBAR) contains the local memory address of the Circular Queues. 5374 ** The base address is required to be located on a 1 Mbyte address boundary. 5375 ** . All Circular Queue head and tail pointers are based on the QBAR. 5376 ** When the head and tail pointer registers are read, the Queue Base Address is returned in the upper 12 bits. 5377 ** Writing to the upper 12 bits of the head and tail pointer registers does not affect the Queue Base Address or Queue Base Address Register. 5378 ** Warning: 5379 ** The QBAR must designate a range allocated to the 80331 DDR SDRAM interface 5380 ** ------------------------------------------------------------------------ 5381 ** Bit Default Description 5382 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5383 ** 19:00 00000H Reserved 5384 ************************************************************************** 5385 */ 5386 #define ARCMSR_MU_QUEUE_BASE_ADDRESS_REG 0xFFFFE354 5387 /* 5388 ************************************************************************** 5389 ** Inbound Free Head Pointer Register - IFHPR 5390 ** 5391 ** . The Inbound Free Head Pointer Register (IFHPR) contains the local memory offset from 5392 ** the Queue Base Address of the head pointer for the Inbound Free Queue. 5393 ** The Head Pointer must be aligned on a DWORD address boundary. 5394 ** When read, the Queue Base Address is provided in the upper 12 bits of the register. 5395 ** Writes to the upper 12 bits of the register are ignored. 5396 ** This register is maintained by software. 5397 ** ------------------------------------------------------------------------ 5398 ** Bit Default Description 5399 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5400 ** 19:02 0000H 00 2 Inbound Free Head Pointer - Local memory offset of the head pointer for the Inbound Free Queue. 5401 ** 01:00 00 2 Reserved 5402 ************************************************************************** 5403 */ 5404 #define ARCMSR_MU_INBOUND_FREE_HEAD_PTR_REG 0xFFFFE360 5405 /* 5406 ************************************************************************** 5407 ** Inbound Free Tail Pointer Register - IFTPR 5408 ** 5409 ** . The Inbound Free Tail Pointer Register (IFTPR) contains the local memory offset from the Queue 5410 ** Base Address of the tail pointer for the Inbound Free Queue. The Tail Pointer must be aligned on a 5411 ** DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 5412 ** of the register. Writes to the upper 12 bits of the register are ignored. 5413 ** ------------------------------------------------------------------------ 5414 ** Bit Default Description 5415 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5416 ** 19:02 0000H 00 2 Inbound Free Tail Pointer - Local memory offset of the tail pointer for the Inbound Free Queue. 5417 ** 01:00 00 2 Reserved 5418 ************************************************************************** 5419 */ 5420 #define ARCMSR_MU_INBOUND_FREE_TAIL_PTR_REG 0xFFFFE364 5421 /* 5422 ************************************************************************** 5423 ** Inbound Post Head Pointer Register - IPHPR 5424 ** 5425 ** . The Inbound Post Head Pointer Register (IPHPR) contains the local memory offset from the Queue 5426 ** Base Address of the head pointer for the Inbound Post Queue. The Head Pointer must be aligned on 5427 ** a DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 5428 ** of the register. Writes to the upper 12 bits of the register are ignored. 5429 ** ------------------------------------------------------------------------ 5430 ** Bit Default Description 5431 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5432 ** 19:02 0000H 00 2 Inbound Post Head Pointer - Local memory offset of the head pointer for the Inbound Post Queue. 5433 ** 01:00 00 2 Reserved 5434 ************************************************************************** 5435 */ 5436 #define ARCMSR_MU_INBOUND_POST_HEAD_PTR_REG 0xFFFFE368 5437 /* 5438 ************************************************************************** 5439 ** Inbound Post Tail Pointer Register - IPTPR 5440 ** 5441 ** . The Inbound Post Tail Pointer Register (IPTPR) contains the local memory offset from the Queue 5442 ** Base Address of the tail pointer for the Inbound Post Queue. The Tail Pointer must be aligned on a 5443 ** DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 5444 ** of the register. Writes to the upper 12 bits of the register are ignored. 5445 ** ------------------------------------------------------------------------ 5446 ** Bit Default Description 5447 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5448 ** 19:02 0000H 00 2 Inbound Post Tail Pointer - Local memory offset of the tail pointer for the Inbound Post Queue. 5449 ** 01:00 00 2 Reserved 5450 ************************************************************************** 5451 */ 5452 #define ARCMSR_MU_INBOUND_POST_TAIL_PTR_REG 0xFFFFE36C 5453 /* 5454 ************************************************************************** 5455 ** Index Address Register - IAR 5456 ** 5457 ** . The Index Address Register (IAR) contains the offset of the least recently accessed Index Register. 5458 ** It is written by the MU when the Index Registers are written by a PCI agent. 5459 ** The register is not updated until the Index Interrupt bit in the Inbound Interrupt Status Register is cleared. 5460 ** . The local memory address of the Index Register least recently accessed is computed 5461 ** by adding the Index Address Register to the Inbound ATU Translate Value Register. 5462 ** ------------------------------------------------------------------------ 5463 ** Bit Default Description 5464 ** 31:12 000000H Reserved 5465 ** 11:02 00H 00 2 Index Address - is the local memory offset of the Index Register written (050H to FFCH) 5466 ** 01:00 00 2 Reserved 5467 ************************************************************************** 5468 */ 5469 #define ARCMSR_MU_LOCAL_MEMORY_INDEX_REG 0xFFFFE380 /*1004 dwords 0x0050....0x0FFC, 4016 bytes 0x0050...0x0FFF*/ 5470 /* 5471 ********************************************************************************************************** 5472 ** RS-232 Interface for Areca Raid Controller 5473 ** The low level command interface is exclusive with VT100 terminal 5474 ** -------------------------------------------------------------------- 5475 ** 1. Sequence of command execution 5476 ** -------------------------------------------------------------------- 5477 ** (A) Header : 3 bytes sequence (0x5E, 0x01, 0x61) 5478 ** (B) Command block : variable length of data including length, command code, data and checksum byte 5479 ** (C) Return data : variable length of data 5480 ** -------------------------------------------------------------------- 5481 ** 2. Command block 5482 ** -------------------------------------------------------------------- 5483 ** (A) 1st byte : command block length (low byte) 5484 ** (B) 2nd byte : command block length (high byte) 5485 ** note ..command block length shouldn't > 2040 bytes, length excludes these two bytes 5486 ** (C) 3rd byte : command code 5487 ** (D) 4th and following bytes : variable length data bytes depends on command code 5488 ** (E) last byte : checksum byte (sum of 1st byte until last data byte) 5489 ** -------------------------------------------------------------------- 5490 ** 3. Command code and associated data 5491 ** -------------------------------------------------------------------- 5492 ** The following are command code defined in raid controller Command code 0x10--0x1? are used for system level management, 5493 ** no password checking is needed and should be implemented in separate well controlled utility and not for end user access. 5494 ** Command code 0x20--0x?? always check the password, password must be entered to enable these command. 5495 ** enum 5496 ** { 5497 ** GUI_SET_SERIAL=0x10, 5498 ** GUI_SET_VENDOR, 5499 ** GUI_SET_MODEL, 5500 ** GUI_IDENTIFY, 5501 ** GUI_CHECK_PASSWORD, 5502 ** GUI_LOGOUT, 5503 ** GUI_HTTP, 5504 ** GUI_SET_ETHERNET_ADDR, 5505 ** GUI_SET_LOGO, 5506 ** GUI_POLL_EVENT, 5507 ** GUI_GET_EVENT, 5508 ** GUI_GET_HW_MONITOR, 5509 ** 5510 ** // GUI_QUICK_CREATE=0x20, (function removed) 5511 ** GUI_GET_INFO_R=0x20, 5512 ** GUI_GET_INFO_V, 5513 ** GUI_GET_INFO_P, 5514 ** GUI_GET_INFO_S, 5515 ** GUI_CLEAR_EVENT, 5516 ** 5517 ** GUI_MUTE_BEEPER=0x30, 5518 ** GUI_BEEPER_SETTING, 5519 ** GUI_SET_PASSWORD, 5520 ** GUI_HOST_INTERFACE_MODE, 5521 ** GUI_REBUILD_PRIORITY, 5522 ** GUI_MAX_ATA_MODE, 5523 ** GUI_RESET_CONTROLLER, 5524 ** GUI_COM_PORT_SETTING, 5525 ** GUI_NO_OPERATION, 5526 ** GUI_DHCP_IP, 5527 ** 5528 ** GUI_CREATE_PASS_THROUGH=0x40, 5529 ** GUI_MODIFY_PASS_THROUGH, 5530 ** GUI_DELETE_PASS_THROUGH, 5531 ** GUI_IDENTIFY_DEVICE, 5532 ** 5533 ** GUI_CREATE_RAIDSET=0x50, 5534 ** GUI_DELETE_RAIDSET, 5535 ** GUI_EXPAND_RAIDSET, 5536 ** GUI_ACTIVATE_RAIDSET, 5537 ** GUI_CREATE_HOT_SPARE, 5538 ** GUI_DELETE_HOT_SPARE, 5539 ** 5540 ** GUI_CREATE_VOLUME=0x60, 5541 ** GUI_MODIFY_VOLUME, 5542 ** GUI_DELETE_VOLUME, 5543 ** GUI_START_CHECK_VOLUME, 5544 ** GUI_STOP_CHECK_VOLUME 5545 ** }; 5546 ** 5547 ** Command description : 5548 ** 5549 ** GUI_SET_SERIAL : Set the controller serial# 5550 ** byte 0,1 : length 5551 ** byte 2 : command code 0x10 5552 ** byte 3 : password length (should be 0x0f) 5553 ** byte 4-0x13 : should be "ArEcATecHnoLogY" 5554 ** byte 0x14--0x23 : Serial number string (must be 16 bytes) 5555 ** GUI_SET_VENDOR : Set vendor string for the controller 5556 ** byte 0,1 : length 5557 ** byte 2 : command code 0x11 5558 ** byte 3 : password length (should be 0x08) 5559 ** byte 4-0x13 : should be "ArEcAvAr" 5560 ** byte 0x14--0x3B : vendor string (must be 40 bytes) 5561 ** GUI_SET_MODEL : Set the model name of the controller 5562 ** byte 0,1 : length 5563 ** byte 2 : command code 0x12 5564 ** byte 3 : password length (should be 0x08) 5565 ** byte 4-0x13 : should be "ArEcAvAr" 5566 ** byte 0x14--0x1B : model string (must be 8 bytes) 5567 ** GUI_IDENTIFY : Identify device 5568 ** byte 0,1 : length 5569 ** byte 2 : command code 0x13 5570 ** return "Areca RAID Subsystem " 5571 ** GUI_CHECK_PASSWORD : Verify password 5572 ** byte 0,1 : length 5573 ** byte 2 : command code 0x14 5574 ** byte 3 : password length 5575 ** byte 4-0x?? : user password to be checked 5576 ** GUI_LOGOUT : Logout GUI (force password checking on next command) 5577 ** byte 0,1 : length 5578 ** byte 2 : command code 0x15 5579 ** GUI_HTTP : HTTP interface (reserved for Http proxy service)(0x16) 5580 ** 5581 ** GUI_SET_ETHERNET_ADDR : Set the ethernet MAC address 5582 ** byte 0,1 : length 5583 ** byte 2 : command code 0x17 5584 ** byte 3 : password length (should be 0x08) 5585 ** byte 4-0x13 : should be "ArEcAvAr" 5586 ** byte 0x14--0x19 : Ethernet MAC address (must be 6 bytes) 5587 ** GUI_SET_LOGO : Set logo in HTTP 5588 ** byte 0,1 : length 5589 ** byte 2 : command code 0x18 5590 ** byte 3 : Page# (0/1/2/3) (0xff --> clear OEM logo) 5591 ** byte 4/5/6/7 : 0x55/0xaa/0xa5/0x5a 5592 ** byte 8 : TITLE.JPG data (each page must be 2000 bytes) 5593 ** note .... page0 1st 2 byte must be actual length of the JPG file 5594 ** GUI_POLL_EVENT : Poll If Event Log Changed 5595 ** byte 0,1 : length 5596 ** byte 2 : command code 0x19 5597 ** GUI_GET_EVENT : Read Event 5598 ** byte 0,1 : length 5599 ** byte 2 : command code 0x1a 5600 ** byte 3 : Event Page (0:1st page/1/2/3:last page) 5601 ** GUI_GET_HW_MONITOR : Get HW monitor data 5602 ** byte 0,1 : length 5603 ** byte 2 : command code 0x1b 5604 ** byte 3 : # of FANs(example 2) 5605 ** byte 4 : # of Voltage sensor(example 3) 5606 ** byte 5 : # of temperature sensor(example 2) 5607 ** byte 6 : # of power 5608 ** byte 7/8 : Fan#0 (RPM) 5609 ** byte 9/10 : Fan#1 5610 ** byte 11/12 : Voltage#0 original value in *1000 5611 ** byte 13/14 : Voltage#0 value 5612 ** byte 15/16 : Voltage#1 org 5613 ** byte 17/18 : Voltage#1 5614 ** byte 19/20 : Voltage#2 org 5615 ** byte 21/22 : Voltage#2 5616 ** byte 23 : Temp#0 5617 ** byte 24 : Temp#1 5618 ** byte 25 : Power indicator (bit0 : power#0, bit1 : power#1) 5619 ** byte 26 : UPS indicator 5620 ** GUI_QUICK_CREATE : Quick create raid/volume set 5621 ** byte 0,1 : length 5622 ** byte 2 : command code 0x20 5623 ** byte 3/4/5/6 : raw capacity 5624 ** byte 7 : raid level 5625 ** byte 8 : stripe size 5626 ** byte 9 : spare 5627 ** byte 10/11/12/13: device mask (the devices to create raid/volume) 5628 ** This function is removed, application like to implement quick create function 5629 ** need to use GUI_CREATE_RAIDSET and GUI_CREATE_VOLUMESET function. 5630 ** GUI_GET_INFO_R : Get Raid Set Information 5631 ** byte 0,1 : length 5632 ** byte 2 : command code 0x20 5633 ** byte 3 : raidset# 5634 ** 5635 ** typedef struct sGUI_RAIDSET 5636 ** { 5637 ** BYTE grsRaidSetName[16]; 5638 ** DWORD grsCapacity; 5639 ** DWORD grsCapacityX; 5640 ** DWORD grsFailMask; 5641 ** BYTE grsDevArray[32]; 5642 ** BYTE grsMemberDevices; 5643 ** BYTE grsNewMemberDevices; 5644 ** BYTE grsRaidState; 5645 ** BYTE grsVolumes; 5646 ** BYTE grsVolumeList[16]; 5647 ** BYTE grsRes1; 5648 ** BYTE grsRes2; 5649 ** BYTE grsRes3; 5650 ** BYTE grsFreeSegments; 5651 ** DWORD grsRawStripes[8]; 5652 ** DWORD grsRes4; 5653 ** DWORD grsRes5; // Total to 128 bytes 5654 ** DWORD grsRes6; // Total to 128 bytes 5655 ** } sGUI_RAIDSET, *pGUI_RAIDSET; 5656 ** GUI_GET_INFO_V : Get Volume Set Information 5657 ** byte 0,1 : length 5658 ** byte 2 : command code 0x21 5659 ** byte 3 : volumeset# 5660 ** 5661 ** typedef struct sGUI_VOLUMESET 5662 ** { 5663 ** BYTE gvsVolumeName[16]; // 16 5664 ** DWORD gvsCapacity; 5665 ** DWORD gvsCapacityX; 5666 ** DWORD gvsFailMask; 5667 ** DWORD gvsStripeSize; 5668 ** DWORD gvsNewFailMask; 5669 ** DWORD gvsNewStripeSize; 5670 ** DWORD gvsVolumeStatus; 5671 ** DWORD gvsProgress; // 32 5672 ** sSCSI_ATTR gvsScsi; 5673 ** BYTE gvsMemberDisks; 5674 ** BYTE gvsRaidLevel; // 8 5675 ** 5676 ** BYTE gvsNewMemberDisks; 5677 ** BYTE gvsNewRaidLevel; 5678 ** BYTE gvsRaidSetNumber; 5679 ** BYTE gvsRes0; // 4 5680 ** BYTE gvsRes1[4]; // 64 bytes 5681 ** } sGUI_VOLUMESET, *pGUI_VOLUMESET; 5682 ** 5683 ** GUI_GET_INFO_P : Get Physical Drive Information 5684 ** byte 0,1 : length 5685 ** byte 2 : command code 0x22 5686 ** byte 3 : drive # (from 0 to max-channels - 1) 5687 ** 5688 ** typedef struct sGUI_PHY_DRV 5689 ** { 5690 ** BYTE gpdModelName[40]; 5691 ** BYTE gpdSerialNumber[20]; 5692 ** BYTE gpdFirmRev[8]; 5693 ** DWORD gpdCapacity; 5694 ** DWORD gpdCapacityX; // Reserved for expansion 5695 ** BYTE gpdDeviceState; 5696 ** BYTE gpdPioMode; 5697 ** BYTE gpdCurrentUdmaMode; 5698 ** BYTE gpdUdmaMode; 5699 ** BYTE gpdDriveSelect; 5700 ** BYTE gpdRaidNumber; // 0xff if not belongs to a raid set 5701 ** sSCSI_ATTR gpdScsi; 5702 ** BYTE gpdReserved[40]; // Total to 128 bytes 5703 ** } sGUI_PHY_DRV, *pGUI_PHY_DRV; 5704 ** 5705 ** GUI_GET_INFO_S : Get System Information 5706 ** byte 0,1 : length 5707 ** byte 2 : command code 0x23 5708 ** 5709 ** typedef struct sCOM_ATTR 5710 ** { 5711 ** BYTE comBaudRate; 5712 ** BYTE comDataBits; 5713 ** BYTE comStopBits; 5714 ** BYTE comParity; 5715 ** BYTE comFlowControl; 5716 ** } sCOM_ATTR, *pCOM_ATTR; 5717 ** 5718 ** typedef struct sSYSTEM_INFO 5719 ** { 5720 ** BYTE gsiVendorName[40]; 5721 ** BYTE gsiSerialNumber[16]; 5722 ** BYTE gsiFirmVersion[16]; 5723 ** BYTE gsiBootVersion[16]; 5724 ** BYTE gsiMbVersion[16]; 5725 ** BYTE gsiModelName[8]; 5726 ** BYTE gsiLocalIp[4]; 5727 ** BYTE gsiCurrentIp[4]; 5728 ** DWORD gsiTimeTick; 5729 ** DWORD gsiCpuSpeed; 5730 ** DWORD gsiICache; 5731 ** DWORD gsiDCache; 5732 ** DWORD gsiScache; 5733 ** DWORD gsiMemorySize; 5734 ** DWORD gsiMemorySpeed; 5735 ** DWORD gsiEvents; 5736 ** BYTE gsiMacAddress[6]; 5737 ** BYTE gsiDhcp; 5738 ** BYTE gsiBeeper; 5739 ** BYTE gsiChannelUsage; 5740 ** BYTE gsiMaxAtaMode; 5741 ** BYTE gsiSdramEcc; // 1:if ECC enabled 5742 ** BYTE gsiRebuildPriority; 5743 ** sCOM_ATTR gsiComA; // 5 bytes 5744 ** sCOM_ATTR gsiComB; // 5 bytes 5745 ** BYTE gsiIdeChannels; 5746 ** BYTE gsiScsiHostChannels; 5747 ** BYTE gsiIdeHostChannels; 5748 ** BYTE gsiMaxVolumeSet; 5749 ** BYTE gsiMaxRaidSet; 5750 ** BYTE gsiEtherPort; // 1:if ether net port supported 5751 ** BYTE gsiRaid6Engine; // 1:Raid6 engine supported 5752 ** BYTE gsiRes[75]; 5753 ** } sSYSTEM_INFO, *pSYSTEM_INFO; 5754 ** 5755 ** GUI_CLEAR_EVENT : Clear System Event 5756 ** byte 0,1 : length 5757 ** byte 2 : command code 0x24 5758 ** 5759 ** GUI_MUTE_BEEPER : Mute current beeper 5760 ** byte 0,1 : length 5761 ** byte 2 : command code 0x30 5762 ** 5763 ** GUI_BEEPER_SETTING : Disable beeper 5764 ** byte 0,1 : length 5765 ** byte 2 : command code 0x31 5766 ** byte 3 : 0->disable, 1->enable 5767 ** 5768 ** GUI_SET_PASSWORD : Change password 5769 ** byte 0,1 : length 5770 ** byte 2 : command code 0x32 5771 ** byte 3 : pass word length ( must <= 15 ) 5772 ** byte 4 : password (must be alpha-numerical) 5773 ** 5774 ** GUI_HOST_INTERFACE_MODE : Set host interface mode 5775 ** byte 0,1 : length 5776 ** byte 2 : command code 0x33 5777 ** byte 3 : 0->Independent, 1->cluster 5778 ** 5779 ** GUI_REBUILD_PRIORITY : Set rebuild priority 5780 ** byte 0,1 : length 5781 ** byte 2 : command code 0x34 5782 ** byte 3 : 0/1/2/3 (low->high) 5783 ** 5784 ** GUI_MAX_ATA_MODE : Set maximum ATA mode to be used 5785 ** byte 0,1 : length 5786 ** byte 2 : command code 0x35 5787 ** byte 3 : 0/1/2/3 (133/100/66/33) 5788 ** 5789 ** GUI_RESET_CONTROLLER : Reset Controller 5790 ** byte 0,1 : length 5791 ** byte 2 : command code 0x36 5792 ** *Response with VT100 screen (discard it) 5793 ** 5794 ** GUI_COM_PORT_SETTING : COM port setting 5795 ** byte 0,1 : length 5796 ** byte 2 : command code 0x37 5797 ** byte 3 : 0->COMA (term port), 1->COMB (debug port) 5798 ** byte 4 : 0/1/2/3/4/5/6/7 (1200/2400/4800/9600/19200/38400/57600/115200) 5799 ** byte 5 : data bit (0:7 bit, 1:8 bit : must be 8 bit) 5800 ** byte 6 : stop bit (0:1, 1:2 stop bits) 5801 ** byte 7 : parity (0:none, 1:off, 2:even) 5802 ** byte 8 : flow control (0:none, 1:xon/xoff, 2:hardware => must use none) 5803 ** 5804 ** GUI_NO_OPERATION : No operation 5805 ** byte 0,1 : length 5806 ** byte 2 : command code 0x38 5807 ** 5808 ** GUI_DHCP_IP : Set DHCP option and local IP address 5809 ** byte 0,1 : length 5810 ** byte 2 : command code 0x39 5811 ** byte 3 : 0:dhcp disabled, 1:dhcp enabled 5812 ** byte 4/5/6/7 : IP address 5813 ** 5814 ** GUI_CREATE_PASS_THROUGH : Create pass through disk 5815 ** byte 0,1 : length 5816 ** byte 2 : command code 0x40 5817 ** byte 3 : device # 5818 ** byte 4 : scsi channel (0/1) 5819 ** byte 5 : scsi id (0-->15) 5820 ** byte 6 : scsi lun (0-->7) 5821 ** byte 7 : tagged queue (1 : enabled) 5822 ** byte 8 : cache mode (1 : enabled) 5823 ** byte 9 : max speed (0/1/2/3/4, async/20/40/80/160 for scsi) 5824 ** (0/1/2/3/4, 33/66/100/133/150 for ide ) 5825 ** 5826 ** GUI_MODIFY_PASS_THROUGH : Modify pass through disk 5827 ** byte 0,1 : length 5828 ** byte 2 : command code 0x41 5829 ** byte 3 : device # 5830 ** byte 4 : scsi channel (0/1) 5831 ** byte 5 : scsi id (0-->15) 5832 ** byte 6 : scsi lun (0-->7) 5833 ** byte 7 : tagged queue (1 : enabled) 5834 ** byte 8 : cache mode (1 : enabled) 5835 ** byte 9 : max speed (0/1/2/3/4, async/20/40/80/160 for scsi) 5836 ** (0/1/2/3/4, 33/66/100/133/150 for ide ) 5837 ** 5838 ** GUI_DELETE_PASS_THROUGH : Delete pass through disk 5839 ** byte 0,1 : length 5840 ** byte 2 : command code 0x42 5841 ** byte 3 : device# to be deleted 5842 ** 5843 ** GUI_IDENTIFY_DEVICE : Identify Device 5844 ** byte 0,1 : length 5845 ** byte 2 : command code 0x43 5846 ** byte 3 : Flash Method(0:flash selected, 1:flash not selected) 5847 ** byte 4/5/6/7 : IDE device mask to be flashed 5848 ** note .... no response data available 5849 ** 5850 ** GUI_CREATE_RAIDSET : Create Raid Set 5851 ** byte 0,1 : length 5852 ** byte 2 : command code 0x50 5853 ** byte 3/4/5/6 : device mask 5854 ** byte 7-22 : raidset name (if byte 7 == 0:use default) 5855 ** 5856 ** GUI_DELETE_RAIDSET : Delete Raid Set 5857 ** byte 0,1 : length 5858 ** byte 2 : command code 0x51 5859 ** byte 3 : raidset# 5860 ** 5861 ** GUI_EXPAND_RAIDSET : Expand Raid Set 5862 ** byte 0,1 : length 5863 ** byte 2 : command code 0x52 5864 ** byte 3 : raidset# 5865 ** byte 4/5/6/7 : device mask for expansion 5866 ** byte 8/9/10 : (8:0 no change, 1 change, 0xff:terminate, 9:new raid level,10:new stripe size 0/1/2/3/4/5->4/8/16/32/64/128K ) 5867 ** byte 11/12/13 : repeat for each volume in the raidset .... 5868 ** 5869 ** GUI_ACTIVATE_RAIDSET : Activate incomplete raid set 5870 ** byte 0,1 : length 5871 ** byte 2 : command code 0x53 5872 ** byte 3 : raidset# 5873 ** 5874 ** GUI_CREATE_HOT_SPARE : Create hot spare disk 5875 ** byte 0,1 : length 5876 ** byte 2 : command code 0x54 5877 ** byte 3/4/5/6 : device mask for hot spare creation 5878 ** 5879 ** GUI_DELETE_HOT_SPARE : Delete hot spare disk 5880 ** byte 0,1 : length 5881 ** byte 2 : command code 0x55 5882 ** byte 3/4/5/6 : device mask for hot spare deletion 5883 ** 5884 ** GUI_CREATE_VOLUME : Create volume set 5885 ** byte 0,1 : length 5886 ** byte 2 : command code 0x60 5887 ** byte 3 : raidset# 5888 ** byte 4-19 : volume set name (if byte4 == 0, use default) 5889 ** byte 20-27 : volume capacity (blocks) 5890 ** byte 28 : raid level 5891 ** byte 29 : stripe size (0/1/2/3/4/5->4/8/16/32/64/128K) 5892 ** byte 30 : channel 5893 ** byte 31 : ID 5894 ** byte 32 : LUN 5895 ** byte 33 : 1 enable tag 5896 ** byte 34 : 1 enable cache 5897 ** byte 35 : speed (0/1/2/3/4->async/20/40/80/160 for scsi) 5898 ** (0/1/2/3/4->33/66/100/133/150 for IDE ) 5899 ** byte 36 : 1 to select quick init 5900 ** 5901 ** GUI_MODIFY_VOLUME : Modify volume Set 5902 ** byte 0,1 : length 5903 ** byte 2 : command code 0x61 5904 ** byte 3 : volumeset# 5905 ** byte 4-19 : new volume set name (if byte4 == 0, not change) 5906 ** byte 20-27 : new volume capacity (reserved) 5907 ** byte 28 : new raid level 5908 ** byte 29 : new stripe size (0/1/2/3/4/5->4/8/16/32/64/128K) 5909 ** byte 30 : new channel 5910 ** byte 31 : new ID 5911 ** byte 32 : new LUN 5912 ** byte 33 : 1 enable tag 5913 ** byte 34 : 1 enable cache 5914 ** byte 35 : speed (0/1/2/3/4->async/20/40/80/160 for scsi) 5915 ** (0/1/2/3/4->33/66/100/133/150 for IDE ) 5916 ** 5917 ** GUI_DELETE_VOLUME : Delete volume set 5918 ** byte 0,1 : length 5919 ** byte 2 : command code 0x62 5920 ** byte 3 : volumeset# 5921 ** 5922 ** GUI_START_CHECK_VOLUME : Start volume consistency check 5923 ** byte 0,1 : length 5924 ** byte 2 : command code 0x63 5925 ** byte 3 : volumeset# 5926 ** 5927 ** GUI_STOP_CHECK_VOLUME : Stop volume consistency check 5928 ** byte 0,1 : length 5929 ** byte 2 : command code 0x64 5930 ** --------------------------------------------------------------------- 5931 ** 4. Returned data 5932 ** --------------------------------------------------------------------- 5933 ** (A) Header : 3 bytes sequence (0x5E, 0x01, 0x61) 5934 ** (B) Length : 2 bytes (low byte 1st, excludes length and checksum byte) 5935 ** (C) status or data : 5936 ** <1> If length == 1 ==> 1 byte status code 5937 ** #define GUI_OK 0x41 5938 ** #define GUI_RAIDSET_NOT_NORMAL 0x42 5939 ** #define GUI_VOLUMESET_NOT_NORMAL 0x43 5940 ** #define GUI_NO_RAIDSET 0x44 5941 ** #define GUI_NO_VOLUMESET 0x45 5942 ** #define GUI_NO_PHYSICAL_DRIVE 0x46 5943 ** #define GUI_PARAMETER_ERROR 0x47 5944 ** #define GUI_UNSUPPORTED_COMMAND 0x48 5945 ** #define GUI_DISK_CONFIG_CHANGED 0x49 5946 ** #define GUI_INVALID_PASSWORD 0x4a 5947 ** #define GUI_NO_DISK_SPACE 0x4b 5948 ** #define GUI_CHECKSUM_ERROR 0x4c 5949 ** #define GUI_PASSWORD_REQUIRED 0x4d 5950 ** <2> If length > 1 ==> data block returned from controller and the contents depends on the command code 5951 ** (E) Checksum : checksum of length and status or data byte 5952 ************************************************************************** 5953 */ 5954