1 /* 2 *********************************************************************************************** 3 ** O.S : FreeBSD 4 ** FILE NAME : arcmsr.h 5 ** BY : Erich Chen, Ching Huang 6 ** Description: SCSI RAID Device Driver for 7 ** ARECA SATA/SAS RAID HOST Adapter 8 ** [RAID controller:INTEL 331(PCI-X) 341(PCI-EXPRESS) chip set] 9 *********************************************************************************************** 10 ************************************************************************ 11 ** Copyright (C) 2002 - 2010, Areca Technology Corporation All rights reserved. 12 ** 13 ** Web site: www.areca.com.tw 14 ** E-mail: erich@areca.com.tw; ching2048@areca.com.tw 15 ** 16 ** Redistribution and use in source and binary forms,with or without 17 ** modification,are permitted provided that the following conditions 18 ** are met: 19 ** 1. Redistributions of source code must retain the above copyright 20 ** notice,this list of conditions and the following disclaimer. 21 ** 2. Redistributions in binary form must reproduce the above copyright 22 ** notice,this list of conditions and the following disclaimer in the 23 ** documentation and/or other materials provided with the distribution. 24 ** 3. The name of the author may not be used to endorse or promote products 25 ** derived from this software without specific prior written permission. 26 ** 27 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 28 ** IMPLIED WARRANTIES,INCLUDING,BUT NOT LIMITED TO,THE IMPLIED WARRANTIES 29 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,INDIRECT, 31 ** INCIDENTAL,SPECIAL,EXEMPLARY,OR CONSEQUENTIAL DAMAGES(INCLUDING,BUT 32 ** NOT LIMITED TO,PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33 ** DATA,OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 34 ** THEORY OF LIABILITY,WHETHER IN CONTRACT,STRICT LIABILITY,OR TORT 35 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 36 ** THIS SOFTWARE,EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 ************************************************************************** 38 * $FreeBSD$ 39 */ 40 #define ARCMSR_SCSI_INITIATOR_ID 255 41 #define ARCMSR_DEV_SECTOR_SIZE 512 42 #define ARCMSR_MAX_XFER_SECTORS 4096 43 #define ARCMSR_MAX_TARGETID 17 /*16 max target id + 1*/ 44 #define ARCMSR_MAX_TARGETLUN 8 /*8*/ 45 #define ARCMSR_MAX_CHIPTYPE_NUM 4 46 #define ARCMSR_MAX_OUTSTANDING_CMD 256 47 #define ARCMSR_MAX_START_JOB 257 48 #define ARCMSR_MAX_CMD_PERLUN ARCMSR_MAX_OUTSTANDING_CMD 49 #define ARCMSR_MAX_FREESRB_NUM 384 50 #define ARCMSR_MAX_QBUFFER 4096 /* ioctl QBUFFER */ 51 #define ARCMSR_MAX_SG_ENTRIES 38 /* max 38*/ 52 #define ARCMSR_MAX_ADAPTER 4 53 #define ARCMSR_RELEASE_SIMQ_LEVEL 230 54 #define ARCMSR_MAX_HBB_POSTQUEUE 264 /* (ARCMSR_MAX_OUTSTANDING_CMD+8) */ 55 #define ARCMSR_TIMEOUT_DELAY 60 /* in sec */ 56 /* 57 ********************************************************************* 58 */ 59 #ifndef TRUE 60 #define TRUE 1 61 #endif 62 #ifndef FALSE 63 #define FALSE 0 64 #endif 65 #ifndef INTR_ENTROPY 66 # define INTR_ENTROPY 0 67 #endif 68 69 #ifndef offsetof 70 #define offsetof(type, member) ((size_t)(&((type *)0)->member)) 71 #endif 72 /* 73 ********************************************************************************** 74 ** 75 ********************************************************************************** 76 */ 77 #define PCI_VENDOR_ID_ARECA 0x17D3 /* Vendor ID */ 78 #define PCI_DEVICE_ID_ARECA_1110 0x1110 /* Device ID */ 79 #define PCI_DEVICE_ID_ARECA_1120 0x1120 /* Device ID */ 80 #define PCI_DEVICE_ID_ARECA_1130 0x1130 /* Device ID */ 81 #define PCI_DEVICE_ID_ARECA_1160 0x1160 /* Device ID */ 82 #define PCI_DEVICE_ID_ARECA_1170 0x1170 /* Device ID */ 83 #define PCI_DEVICE_ID_ARECA_1200 0x1200 /* Device ID */ 84 #define PCI_DEVICE_ID_ARECA_1201 0x1201 /* Device ID */ 85 #define PCI_DEVICE_ID_ARECA_1210 0x1210 /* Device ID */ 86 #define PCI_DEVICE_ID_ARECA_1212 0x1212 /* Device ID */ 87 #define PCI_DEVICE_ID_ARECA_1220 0x1220 /* Device ID */ 88 #define PCI_DEVICE_ID_ARECA_1222 0x1222 /* Device ID */ 89 #define PCI_DEVICE_ID_ARECA_1230 0x1230 /* Device ID */ 90 #define PCI_DEVICE_ID_ARECA_1231 0x1231 /* Device ID */ 91 #define PCI_DEVICE_ID_ARECA_1260 0x1260 /* Device ID */ 92 #define PCI_DEVICE_ID_ARECA_1261 0x1261 /* Device ID */ 93 #define PCI_DEVICE_ID_ARECA_1270 0x1270 /* Device ID */ 94 #define PCI_DEVICE_ID_ARECA_1280 0x1280 /* Device ID */ 95 #define PCI_DEVICE_ID_ARECA_1380 0x1380 /* Device ID */ 96 #define PCI_DEVICE_ID_ARECA_1381 0x1381 /* Device ID */ 97 #define PCI_DEVICE_ID_ARECA_1680 0x1680 /* Device ID */ 98 #define PCI_DEVICE_ID_ARECA_1681 0x1681 /* Device ID */ 99 #define PCI_DEVICE_ID_ARECA_1880 0x1880 /* Device ID */ 100 101 #define ARECA_SUB_DEV_ID_1880 0x1880 /* Subsystem Device ID */ 102 #define ARECA_SUB_DEV_ID_1882 0x1882 /* Subsystem Device ID */ 103 #define ARECA_SUB_DEV_ID_1212 0x1212 /* Subsystem Device ID */ 104 #define ARECA_SUB_DEV_ID_1213 0x1213 /* Subsystem Device ID */ 105 #define ARECA_SUB_DEV_ID_1222 0x1222 /* Subsystem Device ID */ 106 #define ARECA_SUB_DEV_ID_1223 0x1223 /* Subsystem Device ID */ 107 108 #define PCIDevVenIDARC1110 0x111017D3 /* Vendor Device ID */ 109 #define PCIDevVenIDARC1120 0x112017D3 /* Vendor Device ID */ 110 #define PCIDevVenIDARC1130 0x113017D3 /* Vendor Device ID */ 111 #define PCIDevVenIDARC1160 0x116017D3 /* Vendor Device ID */ 112 #define PCIDevVenIDARC1170 0x117017D3 /* Vendor Device ID */ 113 #define PCIDevVenIDARC1200 0x120017D3 /* Vendor Device ID */ 114 #define PCIDevVenIDARC1201 0x120117D3 /* Vendor Device ID */ 115 #define PCIDevVenIDARC1210 0x121017D3 /* Vendor Device ID */ 116 #define PCIDevVenIDARC1212 0x121217D3 /* Vendor Device ID */ 117 #define PCIDevVenIDARC1213 0x121317D3 /* Vendor Device ID */ 118 #define PCIDevVenIDARC1220 0x122017D3 /* Vendor Device ID */ 119 #define PCIDevVenIDARC1222 0x122217D3 /* Vendor Device ID */ 120 #define PCIDevVenIDARC1223 0x122317D3 /* Vendor Device ID */ 121 #define PCIDevVenIDARC1230 0x123017D3 /* Vendor Device ID */ 122 #define PCIDevVenIDARC1231 0x123117D3 /* Vendor Device ID */ 123 #define PCIDevVenIDARC1260 0x126017D3 /* Vendor Device ID */ 124 #define PCIDevVenIDARC1261 0x126117D3 /* Vendor Device ID */ 125 #define PCIDevVenIDARC1270 0x127017D3 /* Vendor Device ID */ 126 #define PCIDevVenIDARC1280 0x128017D3 /* Vendor Device ID */ 127 #define PCIDevVenIDARC1380 0x138017D3 /* Vendor Device ID */ 128 #define PCIDevVenIDARC1381 0x138117D3 /* Vendor Device ID */ 129 #define PCIDevVenIDARC1680 0x168017D3 /* Vendor Device ID */ 130 #define PCIDevVenIDARC1681 0x168117D3 /* Vendor Device ID */ 131 #define PCIDevVenIDARC1880 0x188017D3 /* Vendor Device ID */ 132 #define PCIDevVenIDARC1882 0x188217D3 /* Vendor Device ID */ 133 134 #ifndef PCIR_BARS 135 #define PCIR_BARS 0x10 136 #define PCIR_BAR(x) (PCIR_BARS + (x) * 4) 137 #endif 138 139 #define PCI_BASE_ADDR0 0x10 140 #define PCI_BASE_ADDR1 0x14 141 #define PCI_BASE_ADDR2 0x18 142 #define PCI_BASE_ADDR3 0x1C 143 #define PCI_BASE_ADDR4 0x20 144 #define PCI_BASE_ADDR5 0x24 145 /* 146 ********************************************************************************** 147 ** 148 ********************************************************************************** 149 */ 150 #define ARCMSR_SCSICMD_IOCTL 0x77 151 #define ARCMSR_CDEVSW_IOCTL 0x88 152 #define ARCMSR_MESSAGE_FAIL 0x0001 153 #define ARCMSR_MESSAGE_SUCCESS 0x0000 154 /* 155 ********************************************************************************** 156 ** 157 ********************************************************************************** 158 */ 159 #define arcmsr_ccbsrb_ptr spriv_ptr0 160 #define arcmsr_ccbacb_ptr spriv_ptr1 161 #define dma_addr_hi32(addr) (u_int32_t) ((addr>>16)>>16) 162 #define dma_addr_lo32(addr) (u_int32_t) (addr & 0xffffffff) 163 #define get_min(x,y) ((x) < (y) ? (x) : (y)) 164 #define get_max(x,y) ((x) < (y) ? (y) : (x)) 165 /* 166 ********************************************************************************** 167 ** 168 ********************************************************************************** 169 */ 170 struct CMD_MESSAGE { 171 u_int32_t HeaderLength; 172 u_int8_t Signature[8]; 173 u_int32_t Timeout; 174 u_int32_t ControlCode; 175 u_int32_t ReturnCode; 176 u_int32_t Length; 177 }; 178 179 struct CMD_MESSAGE_FIELD { 180 struct CMD_MESSAGE cmdmessage; /* ioctl header */ 181 u_int8_t messagedatabuffer[1032]; /* areca gui program does not accept more than 1031 byte */ 182 }; 183 184 /************************************************************************/ 185 /************************************************************************/ 186 187 #define ARCMSR_IOP_ERROR_ILLEGALPCI 0x0001 188 #define ARCMSR_IOP_ERROR_VENDORID 0x0002 189 #define ARCMSR_IOP_ERROR_DEVICEID 0x0002 190 #define ARCMSR_IOP_ERROR_ILLEGALCDB 0x0003 191 #define ARCMSR_IOP_ERROR_UNKNOW_CDBERR 0x0004 192 #define ARCMSR_SYS_ERROR_MEMORY_ALLOCATE 0x0005 193 #define ARCMSR_SYS_ERROR_MEMORY_CROSS4G 0x0006 194 #define ARCMSR_SYS_ERROR_MEMORY_LACK 0x0007 195 #define ARCMSR_SYS_ERROR_MEMORY_RANGE 0x0008 196 #define ARCMSR_SYS_ERROR_DEVICE_BASE 0x0009 197 #define ARCMSR_SYS_ERROR_PORT_VALIDATE 0x000A 198 199 /*DeviceType*/ 200 #define ARECA_SATA_RAID 0x90000000 201 202 /*FunctionCode*/ 203 #define FUNCTION_READ_RQBUFFER 0x0801 204 #define FUNCTION_WRITE_WQBUFFER 0x0802 205 #define FUNCTION_CLEAR_RQBUFFER 0x0803 206 #define FUNCTION_CLEAR_WQBUFFER 0x0804 207 #define FUNCTION_CLEAR_ALLQBUFFER 0x0805 208 #define FUNCTION_REQUEST_RETURNCODE_3F 0x0806 209 #define FUNCTION_SAY_HELLO 0x0807 210 #define FUNCTION_SAY_GOODBYE 0x0808 211 #define FUNCTION_FLUSH_ADAPTER_CACHE 0x0809 212 /* 213 ************************************************************************ 214 ** IOCTL CONTROL CODE 215 ************************************************************************ 216 */ 217 /* ARECA IO CONTROL CODE*/ 218 #define ARCMSR_MESSAGE_READ_RQBUFFER _IOWR('F', FUNCTION_READ_RQBUFFER, struct CMD_MESSAGE_FIELD) 219 #define ARCMSR_MESSAGE_WRITE_WQBUFFER _IOWR('F', FUNCTION_WRITE_WQBUFFER, struct CMD_MESSAGE_FIELD) 220 #define ARCMSR_MESSAGE_CLEAR_RQBUFFER _IOWR('F', FUNCTION_CLEAR_RQBUFFER, struct CMD_MESSAGE_FIELD) 221 #define ARCMSR_MESSAGE_CLEAR_WQBUFFER _IOWR('F', FUNCTION_CLEAR_WQBUFFER, struct CMD_MESSAGE_FIELD) 222 #define ARCMSR_MESSAGE_CLEAR_ALLQBUFFER _IOWR('F', FUNCTION_CLEAR_ALLQBUFFER, struct CMD_MESSAGE_FIELD) 223 #define ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F _IOWR('F', FUNCTION_REQUEST_RETURNCODE_3F, struct CMD_MESSAGE_FIELD) 224 #define ARCMSR_MESSAGE_SAY_HELLO _IOWR('F', FUNCTION_SAY_HELLO, struct CMD_MESSAGE_FIELD) 225 #define ARCMSR_MESSAGE_SAY_GOODBYE _IOWR('F', FUNCTION_SAY_GOODBYE, struct CMD_MESSAGE_FIELD) 226 #define ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE _IOWR('F', FUNCTION_FLUSH_ADAPTER_CACHE, struct CMD_MESSAGE_FIELD) 227 228 /* ARECA IOCTL ReturnCode */ 229 #define ARCMSR_MESSAGE_RETURNCODE_OK 0x00000001 230 #define ARCMSR_MESSAGE_RETURNCODE_ERROR 0x00000006 231 #define ARCMSR_MESSAGE_RETURNCODE_3F 0x0000003F 232 #define ARCMSR_IOCTL_RETURNCODE_BUS_HANG_ON 0x00000088 233 /* 234 ************************************************************************ 235 ** SPEC. for Areca HBB adapter 236 ************************************************************************ 237 */ 238 /* ARECA HBB COMMAND for its FIRMWARE */ 239 #define ARCMSR_DRV2IOP_DOORBELL 0x00020400 /* window of "instruction flags" from driver to iop */ 240 #define ARCMSR_DRV2IOP_DOORBELL_MASK 0x00020404 241 #define ARCMSR_IOP2DRV_DOORBELL 0x00020408 /* window of "instruction flags" from iop to driver */ 242 #define ARCMSR_IOP2DRV_DOORBELL_MASK 0x0002040C 243 244 /* ARECA FLAG LANGUAGE */ 245 #define ARCMSR_IOP2DRV_DATA_WRITE_OK 0x00000001 /* ioctl transfer */ 246 #define ARCMSR_IOP2DRV_DATA_READ_OK 0x00000002 /* ioctl transfer */ 247 #define ARCMSR_IOP2DRV_CDB_DONE 0x00000004 248 #define ARCMSR_IOP2DRV_MESSAGE_CMD_DONE 0x00000008 249 250 #define ARCMSR_DOORBELL_HANDLE_INT 0x0000000F 251 #define ARCMSR_DOORBELL_INT_CLEAR_PATTERN 0xFF00FFF0 252 #define ARCMSR_MESSAGE_INT_CLEAR_PATTERN 0xFF00FFF7 253 254 #define ARCMSR_MESSAGE_GET_CONFIG 0x00010008 /* (ARCMSR_INBOUND_MESG0_GET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 255 #define ARCMSR_MESSAGE_SET_CONFIG 0x00020008 /* (ARCMSR_INBOUND_MESG0_SET_CONFIG<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 256 #define ARCMSR_MESSAGE_ABORT_CMD 0x00030008 /* (ARCMSR_INBOUND_MESG0_ABORT_CMD<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 257 #define ARCMSR_MESSAGE_STOP_BGRB 0x00040008 /* (ARCMSR_INBOUND_MESG0_STOP_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 258 #define ARCMSR_MESSAGE_FLUSH_CACHE 0x00050008 /* (ARCMSR_INBOUND_MESG0_FLUSH_CACHE<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 259 #define ARCMSR_MESSAGE_START_BGRB 0x00060008 /* (ARCMSR_INBOUND_MESG0_START_BGRB<<16)|ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED) */ 260 #define ARCMSR_MESSAGE_START_DRIVER_MODE 0x000E0008 261 #define ARCMSR_MESSAGE_SET_POST_WINDOW 0x000F0008 262 #define ARCMSR_MESSAGE_ACTIVE_EOI_MODE 0x00100008 263 #define ARCMSR_MESSAGE_FIRMWARE_OK 0x80000000 /* ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK */ 264 265 #define ARCMSR_DRV2IOP_DATA_WRITE_OK 0x00000001 /* ioctl transfer */ 266 #define ARCMSR_DRV2IOP_DATA_READ_OK 0x00000002 /* ioctl transfer */ 267 #define ARCMSR_DRV2IOP_CDB_POSTED 0x00000004 268 #define ARCMSR_DRV2IOP_MESSAGE_CMD_POSTED 0x00000008 269 #define ARCMSR_DRV2IOP_END_OF_INTERRUPT 0x00000010 /* */ 270 271 /* data tunnel buffer between user space program and its firmware */ 272 #define ARCMSR_MSGCODE_RWBUFFER 0x0000fa00 /* iop msgcode_rwbuffer for message command */ 273 #define ARCMSR_IOCTL_WBUFFER 0x0000fe00 /* user space data to iop 128bytes */ 274 #define ARCMSR_IOCTL_RBUFFER 0x0000ff00 /* iop data to user space 128bytes */ 275 #define ARCMSR_HBB_BASE0_OFFSET 0x00000010 276 #define ARCMSR_HBB_BASE1_OFFSET 0x00000018 277 #define ARCMSR_HBB_BASE0_LEN 0x00021000 278 #define ARCMSR_HBB_BASE1_LEN 0x00010000 279 /* 280 ************************************************************************ 281 ** SPEC. for Areca HBC adapter 282 ************************************************************************ 283 */ 284 #define ARCMSR_HBC_ISR_THROTTLING_LEVEL 12 285 #define ARCMSR_HBC_ISR_MAX_DONE_QUEUE 20 286 /* Host Interrupt Mask */ 287 #define ARCMSR_HBCMU_UTILITY_A_ISR_MASK 0x00000001 /* When clear, the Utility_A interrupt routes to the host.*/ 288 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK 0x00000004 /* When clear, the General Outbound Doorbell interrupt routes to the host.*/ 289 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK 0x00000008 /* When clear, the Outbound Post List FIFO Not Empty interrupt routes to the host.*/ 290 #define ARCMSR_HBCMU_ALL_INTMASKENABLE 0x0000000D /* disable all ISR */ 291 /* Host Interrupt Status */ 292 #define ARCMSR_HBCMU_UTILITY_A_ISR 0x00000001 293 /* 294 ** Set when the Utility_A Interrupt bit is set in the Outbound Doorbell Register. 295 ** It clears by writing a 1 to the Utility_A bit in the Outbound Doorbell Clear Register or through automatic clearing (if enabled). 296 */ 297 #define ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR 0x00000004 298 /* 299 ** Set if Outbound Doorbell register bits 30:1 have a non-zero 300 ** value. This bit clears only when Outbound Doorbell bits 301 ** 30:1 are ALL clear. Only a write to the Outbound Doorbell 302 ** Clear register clears bits in the Outbound Doorbell register. 303 */ 304 #define ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR 0x00000008 305 /* 306 ** Set whenever the Outbound Post List Producer/Consumer 307 ** Register (FIFO) is not empty. It clears when the Outbound 308 ** Post List FIFO is empty. 309 */ 310 #define ARCMSR_HBCMU_SAS_ALL_INT 0x00000010 311 /* 312 ** This bit indicates a SAS interrupt from a source external to 313 ** the PCIe core. This bit is not maskable. 314 */ 315 /* DoorBell*/ 316 #define ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK 0x00000002/**/ 317 #define ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK 0x00000004/**/ 318 #define ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE 0x00000008/*inbound message 0 ready*/ 319 #define ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING 0x00000010/*more than 12 request completed in a time*/ 320 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK 0x00000002/**/ 321 #define ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_DOORBELL_CLEAR 0x00000002/*outbound DATA WRITE isr door bell clear*/ 322 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK 0x00000004/**/ 323 #define ARCMSR_HBCMU_IOP2DRV_DATA_READ_DOORBELL_CLEAR 0x00000004/*outbound DATA READ isr door bell clear*/ 324 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE 0x00000008/*outbound message 0 ready*/ 325 #define ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR 0x00000008/*outbound message cmd isr door bell clear*/ 326 #define ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK 0x80000000/*ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK*/ 327 328 /* 329 ************************************************************* 330 ** structure for holding DMA address data 331 ************************************************************* 332 */ 333 #define IS_SG64_ADDR 0x01000000 /* bit24 */ 334 /* 335 ************************************************************************************************ 336 ** ARECA FIRMWARE SPEC 337 ************************************************************************************************ 338 ** Usage of IOP331 adapter 339 ** (All In/Out is in IOP331's view) 340 ** 1. Message 0 --> InitThread message and retrun code 341 ** 2. Doorbell is used for RS-232 emulation 342 ** inDoorBell : bit0 -- data in ready (DRIVER DATA WRITE OK) 343 ** bit1 -- data out has been read (DRIVER DATA READ OK) 344 ** outDooeBell: bit0 -- data out ready (IOP331 DATA WRITE OK) 345 ** bit1 -- data in has been read (IOP331 DATA READ OK) 346 ** 3. Index Memory Usage 347 ** offset 0xf00 : for RS232 out (request buffer) 348 ** offset 0xe00 : for RS232 in (scratch buffer) 349 ** offset 0xa00 : for inbound message code msgcode_rwbuffer (driver send to IOP331) 350 ** offset 0xa00 : for outbound message code msgcode_rwbuffer (IOP331 send to driver) 351 ** 4. RS-232 emulation 352 ** Currently 128 byte buffer is used 353 ** 1st u_int32_t : Data length (1--124) 354 ** Byte 4--127 : Max 124 bytes of data 355 ** 5. PostQ 356 ** All SCSI Command must be sent through postQ: 357 ** (inbound queue port) Request frame must be 32 bytes aligned 358 ** # bit27--bit31 => flag for post ccb 359 ** # bit0--bit26 => real address (bit27--bit31) of post arcmsr_cdb 360 ** bit31 : 0 : 256 bytes frame 361 ** 1 : 512 bytes frame 362 ** bit30 : 0 : normal request 363 ** 1 : BIOS request 364 ** bit29 : reserved 365 ** bit28 : reserved 366 ** bit27 : reserved 367 ** ------------------------------------------------------------------------------- 368 ** (outbount queue port) Request reply 369 ** # bit27--bit31 => flag for reply 370 ** # bit0--bit26 => real address (bit27--bit31) of reply arcmsr_cdb 371 ** bit31 : must be 0 (for this type of reply) 372 ** bit30 : reserved for BIOS handshake 373 ** bit29 : reserved 374 ** bit28 : 0 : no error, ignore AdapStatus/DevStatus/SenseData 375 ** 1 : Error, error code in AdapStatus/DevStatus/SenseData 376 ** bit27 : reserved 377 ** 6. BIOS request 378 ** All BIOS request is the same with request from PostQ 379 ** Except : 380 ** Request frame is sent from configuration space 381 ** offset: 0x78 : Request Frame (bit30 == 1) 382 ** offset: 0x18 : writeonly to generate IRQ to IOP331 383 ** Completion of request: 384 ** (bit30 == 0, bit28==err flag) 385 ** 7. Definition of SGL entry (structure) 386 ** 8. Message1 Out - Diag Status Code (????) 387 ** 9. Message0 message code : 388 ** 0x00 : NOP 389 ** 0x01 : Get Config ->offset 0xa00 :for outbound message code msgcode_rwbuffer (IOP331 send to driver) 390 ** Signature 0x87974060(4) 391 ** Request len 0x00000200(4) 392 ** numbers of queue 0x00000100(4) 393 ** SDRAM Size 0x00000100(4)-->256 MB 394 ** IDE Channels 0x00000008(4) 395 ** vendor 40 bytes char 396 ** model 8 bytes char 397 ** FirmVer 16 bytes char 398 ** Device Map 16 bytes char 399 ** 400 ** FirmwareVersion DWORD <== Added for checking of new firmware capability 401 ** 0x02 : Set Config ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver send to IOP331) 402 ** Signature 0x87974063(4) 403 ** UPPER32 of Request Frame (4)-->Driver Only 404 ** 0x03 : Reset (Abort all queued Command) 405 ** 0x04 : Stop Background Activity 406 ** 0x05 : Flush Cache 407 ** 0x06 : Start Background Activity (re-start if background is halted) 408 ** 0x07 : Check If Host Command Pending (Novell May Need This Function) 409 ** 0x08 : Set controller time ->offset 0xa00 : for inbound message code msgcode_rwbuffer (driver to IOP331) 410 ** byte 0 : 0xaa <-- signature 411 ** byte 1 : 0x55 <-- signature 412 ** byte 2 : year (04) 413 ** byte 3 : month (1..12) 414 ** byte 4 : date (1..31) 415 ** byte 5 : hour (0..23) 416 ** byte 6 : minute (0..59) 417 ** byte 7 : second (0..59) 418 ** ********************************************************************************* 419 ** Porting Of LSI2108/2116 Based PCIE SAS/6G host raid adapter 420 ** ==> Difference from IOP348 421 ** <1> Message Register 0,1 (the same usage) Init Thread message and retrun code 422 ** Inbound Message 0 (inbound_msgaddr0) : at offset 0xB0 (Scratchpad0) for inbound message code msgcode_rwbuffer (driver send to IOP) 423 ** Inbound Message 1 (inbound_msgaddr1) : at offset 0xB4 (Scratchpad1) Out.... Diag Status Code 424 ** Outbound Message 0 (outbound_msgaddr0): at offset 0xB8 (Scratchpad3) Out.... Diag Status Code 425 ** Outbound Message 1 (outbound_msgaddr1): at offset 0xBC (Scratchpad2) for outbound message code msgcode_rwbuffer (IOP send to driver) 426 ** <A> use doorbell to generate interrupt 427 ** 428 ** inbound doorbell: bit3 -- inbound message 0 ready (driver to iop) 429 ** outbound doorbell: bit3 -- outbound message 0 ready (iop to driver) 430 ** 431 ** a. Message1: Out - Diag Status Code (????) 432 ** 433 ** b. Message0: message code 434 ** 0x00 : NOP 435 ** 0x01 : Get Config ->offset 0xB8 :for outbound message code msgcode_rwbuffer (IOP send to driver) 436 ** Signature 0x87974060(4) 437 ** Request len 0x00000200(4) 438 ** numbers of queue 0x00000100(4) 439 ** SDRAM Size 0x00000100(4)-->256 MB 440 ** IDE Channels 0x00000008(4) 441 ** vendor 40 bytes char 442 ** model 8 bytes char 443 ** FirmVer 16 bytes char 444 ** Device Map 16 bytes char 445 ** cfgVersion ULONG <== Added for checking of new firmware capability 446 ** 0x02 : Set Config ->offset 0xB0 :for inbound message code msgcode_rwbuffer (driver send to IOP) 447 ** Signature 0x87974063(4) 448 ** UPPER32 of Request Frame (4)-->Driver Only 449 ** 0x03 : Reset (Abort all queued Command) 450 ** 0x04 : Stop Background Activity 451 ** 0x05 : Flush Cache 452 ** 0x06 : Start Background Activity (re-start if background is halted) 453 ** 0x07 : Check If Host Command Pending (Novell May Need This Function) 454 ** 0x08 : Set controller time ->offset 0xB0 : for inbound message code msgcode_rwbuffer (driver to IOP) 455 ** byte 0 : 0xaa <-- signature 456 ** byte 1 : 0x55 <-- signature 457 ** byte 2 : year (04) 458 ** byte 3 : month (1..12) 459 ** byte 4 : date (1..31) 460 ** byte 5 : hour (0..23) 461 ** byte 6 : minute (0..59) 462 ** byte 7 : second (0..59) 463 ** 464 ** <2> Doorbell Register is used for RS-232 emulation 465 ** <A> different clear register 466 ** <B> different bit0 definition (bit0 is reserved) 467 ** 468 ** inbound doorbell : at offset 0x20 469 ** inbound doorbell clear : at offset 0x70 470 ** 471 ** inbound doorbell : bit0 -- reserved 472 ** bit1 -- data in ready (DRIVER DATA WRITE OK) 473 ** bit2 -- data out has been read (DRIVER DATA READ OK) 474 ** bit3 -- inbound message 0 ready 475 ** bit4 -- more than 12 request completed in a time 476 ** 477 ** outbound doorbell : at offset 0x9C 478 ** outbound doorbell clear : at offset 0xA0 479 ** 480 ** outbound doorbell : bit0 -- reserved 481 ** bit1 -- data out ready (IOP DATA WRITE OK) 482 ** bit2 -- data in has been read (IOP DATA READ OK) 483 ** bit3 -- outbound message 0 ready 484 ** 485 ** <3> Index Memory Usage (Buffer Area) 486 ** COMPORT_IN at 0x2000: message_wbuffer -- 128 bytes (to be sent to ROC) : for RS232 in (scratch buffer) 487 ** COMPORT_OUT at 0x2100: message_rbuffer -- 128 bytes (to be sent to host): for RS232 out (request buffer) 488 ** BIOS_CFG_AREA at 0x2200: msgcode_rwbuffer -- 1024 bytes for outbound message code msgcode_rwbuffer (IOP send to driver) 489 ** BIOS_CFG_AREA at 0x2200: msgcode_rwbuffer -- 1024 bytes for inbound message code msgcode_rwbuffer (driver send to IOP) 490 ** 491 ** <4> PostQ (Command Post Address) 492 ** All SCSI Command must be sent through postQ: 493 ** inbound queue port32 at offset 0x40 , 0x41, 0x42, 0x43 494 ** inbound queue port64 at offset 0xC0 (lower)/0xC4 (upper) 495 ** outbound queue port32 at offset 0x44 496 ** outbound queue port64 at offset 0xC8 (lower)/0xCC (upper) 497 ** <A> For 32bit queue, access low part is enough to send/receive request 498 ** i.e. write 0x40/0xC0, ROC will get the request with high part == 0, the 499 ** same for outbound queue port 500 ** <B> For 64bit queue, if 64bit instruction is supported, use 64bit instruction 501 ** to post inbound request in a single instruction, and use 64bit instruction 502 ** to retrieve outbound request in a single instruction. 503 ** If in 32bit environment, when sending inbound queue, write high part first 504 ** then write low part. For receiving outbound request, read high part first 505 ** then low part, to check queue empty, ONLY check high part to be 0xFFFFFFFF. 506 ** If high part is 0xFFFFFFFF, DO NOT read low part, this may corrupt the 507 ** consistency of the FIFO. Another way to check empty is to check status flag 508 ** at 0x30 bit3. 509 ** <C> Post Address IS NOT shifted (must be 16 bytes aligned) 510 ** For BIOS, 16bytes aligned is OK 511 ** For Driver, 32bytes alignment is recommended. 512 ** POST Command bit0 to bit3 is defined differently 513 ** ---------------------------- 514 ** bit0:1 for PULL mode (must be 1) 515 ** ---------------------------- 516 ** bit3/2/1: for arcmsr cdb size (arccdbsize) 517 ** 000: <= 0x0080 (128) 518 ** 001: <= 0x0100 (256) 519 ** 010: <= 0x0180 (384) 520 ** 011: <= 0x0200 (512) 521 ** 100: <= 0x0280 (640) 522 ** 101: <= 0x0300 (768) 523 ** 110: <= 0x0300 (reserved) 524 ** 111: <= 0x0300 (reserved) 525 ** ----------------------------- 526 ** if len > 0x300 the len always set as 0x300 527 ** ----------------------------- 528 ** post addr = addr | ((len-1) >> 6) | 1 529 ** ----------------------------- 530 ** page length in command buffer still required, 531 ** 532 ** if page length > 3, 533 ** firmware will assume more request data need to be retrieved 534 ** 535 ** <D> Outbound Posting 536 ** bit0:0 , no error, 1 with error, refer to status buffer 537 ** bit1:0 , reserved (will be 0) 538 ** bit2:0 , reserved (will be 0) 539 ** bit3:0 , reserved (will be 0) 540 ** bit63-4: Completed command address 541 ** 542 ** <E> BIOS support, no special support is required. 543 ** LSI2108 support I/O register 544 ** All driver functionality is supported through I/O address 545 ** 546 ** For further spec, refer to 547 ** \spec\lsi\2108 for Areca\2108\LSISAS2108_PG_NoEncryption.pdf : Chapter 8 (8-11/8-28) 548 ** \spec\lsi\2108 for Areca\2108\SAS2108_RM_20.pdf : for configuration space 549 ************************************************************************************************ 550 */ 551 /* signature of set and get firmware config */ 552 #define ARCMSR_SIGNATURE_GET_CONFIG 0x87974060 553 #define ARCMSR_SIGNATURE_SET_CONFIG 0x87974063 554 /* message code of inbound message register */ 555 #define ARCMSR_INBOUND_MESG0_NOP 0x00000000 556 #define ARCMSR_INBOUND_MESG0_GET_CONFIG 0x00000001 557 #define ARCMSR_INBOUND_MESG0_SET_CONFIG 0x00000002 558 #define ARCMSR_INBOUND_MESG0_ABORT_CMD 0x00000003 559 #define ARCMSR_INBOUND_MESG0_STOP_BGRB 0x00000004 560 #define ARCMSR_INBOUND_MESG0_FLUSH_CACHE 0x00000005 561 #define ARCMSR_INBOUND_MESG0_START_BGRB 0x00000006 562 #define ARCMSR_INBOUND_MESG0_CHK331PENDING 0x00000007 563 #define ARCMSR_INBOUND_MESG0_SYNC_TIMER 0x00000008 564 /* doorbell interrupt generator */ 565 #define ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK 0x00000001 566 #define ARCMSR_INBOUND_DRIVER_DATA_READ_OK 0x00000002 567 #define ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK 0x00000001 568 #define ARCMSR_OUTBOUND_IOP331_DATA_READ_OK 0x00000002 569 /* srb areca cdb flag */ 570 #define ARCMSR_SRBPOST_FLAG_SGL_BSIZE 0x80000000 571 #define ARCMSR_SRBPOST_FLAG_IAM_BIOS 0x40000000 572 #define ARCMSR_SRBREPLY_FLAG_IAM_BIOS 0x40000000 573 #define ARCMSR_SRBREPLY_FLAG_ERROR 0x10000000 574 #define ARCMSR_SRBREPLY_FLAG_ERROR_MODE0 0x10000000 575 #define ARCMSR_SRBREPLY_FLAG_ERROR_MODE1 0x00000001 576 /* outbound firmware ok */ 577 #define ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK 0x80000000 578 /* 579 ********************************** 580 ** 581 ********************************** 582 */ 583 /* size 8 bytes */ 584 /* 32bit Scatter-Gather list */ 585 struct SG32ENTRY { /* length bit 24 == 0 */ 586 u_int32_t length; /* high 8 bit == flag,low 24 bit == length */ 587 u_int32_t address; 588 }; 589 /* size 12 bytes */ 590 /* 64bit Scatter-Gather list */ 591 struct SG64ENTRY { /* length bit 24 == 1 */ 592 u_int32_t length; /* high 8 bit == flag,low 24 bit == length */ 593 u_int32_t address; 594 u_int32_t addresshigh; 595 }; 596 struct SGENTRY_UNION { 597 union { 598 struct SG32ENTRY sg32entry; /* 30h Scatter gather address */ 599 struct SG64ENTRY sg64entry; /* 30h */ 600 }u; 601 }; 602 /* 603 ********************************** 604 ** 605 ********************************** 606 */ 607 struct QBUFFER { 608 u_int32_t data_len; 609 u_int8_t data[124]; 610 }; 611 /* 612 ************************************************************************************************ 613 ** FIRMWARE INFO 614 ************************************************************************************************ 615 */ 616 #define ARCMSR_FW_MODEL_OFFSET 15 617 #define ARCMSR_FW_VERS_OFFSET 17 618 #define ARCMSR_FW_DEVMAP_OFFSET 21 619 #define ARCMSR_FW_CFGVER_OFFSET 25 620 621 struct FIRMWARE_INFO { 622 u_int32_t signature; /*0,00-03*/ 623 u_int32_t request_len; /*1,04-07*/ 624 u_int32_t numbers_queue; /*2,08-11*/ 625 u_int32_t sdram_size; /*3,12-15*/ 626 u_int32_t ide_channels; /*4,16-19*/ 627 char vendor[40]; /*5,20-59*/ 628 char model[8]; /*15,60-67*/ 629 char firmware_ver[16]; /*17,68-83*/ 630 char device_map[16]; /*21,84-99*/ 631 u_int32_t cfgVersion; /*25,100-103 Added for checking of new firmware capability*/ 632 char cfgSerial[16]; /*26,104-119*/ 633 u_int32_t cfgPicStatus; /*30,120-123*/ 634 }; 635 /* (A) For cfgVersion in FIRMWARE_INFO 636 ** if low BYTE (byte#0) >= 3 (version 3) 637 ** then byte#1 report the capability of the firmware can xfer in a single request 638 ** 639 ** byte#1 640 ** 0 256K 641 ** 1 512K 642 ** 2 1M 643 ** 3 2M 644 ** 4 4M 645 ** 5 8M 646 ** 6 16M 647 ** (B) Byte offset 7 (Reserved1) of CDB is changed to msgPages 648 ** Driver support new xfer method need to set this field to indicate 649 ** large CDB block in 0x100 unit (we use 0x100 byte as one page) 650 ** e.g. If the length of CDB including MSG header and SGL is 0x1508 651 ** driver need to set the msgPages to 0x16 652 ** (C) REQ_LEN_512BYTE must be used also to indicate SRB length 653 ** e.g. CDB len msgPages REQ_LEN_512BYTE flag 654 ** <= 0x100 1 0 655 ** <= 0x200 2 1 656 ** <= 0x300 3 1 657 ** <= 0x400 4 1 658 ** . 659 ** . 660 */ 661 662 /* 663 ************************************************************************************************ 664 ** size 0x1F8 (504) 665 ************************************************************************************************ 666 */ 667 struct ARCMSR_CDB { 668 u_int8_t Bus; /* 00h should be 0 */ 669 u_int8_t TargetID; /* 01h should be 0--15 */ 670 u_int8_t LUN; /* 02h should be 0--7 */ 671 u_int8_t Function; /* 03h should be 1 */ 672 673 u_int8_t CdbLength; /* 04h not used now */ 674 u_int8_t sgcount; /* 05h */ 675 u_int8_t Flags; /* 06h */ 676 #define ARCMSR_CDB_FLAG_SGL_BSIZE 0x01 /* bit 0: 0(256) / 1(512) bytes */ 677 #define ARCMSR_CDB_FLAG_BIOS 0x02 /* bit 1: 0(from driver) / 1(from BIOS) */ 678 #define ARCMSR_CDB_FLAG_WRITE 0x04 /* bit 2: 0(Data in) / 1(Data out) */ 679 #define ARCMSR_CDB_FLAG_SIMPLEQ 0x00 /* bit 4/3 ,00 : simple Q,01 : head of Q,10 : ordered Q */ 680 #define ARCMSR_CDB_FLAG_HEADQ 0x08 681 #define ARCMSR_CDB_FLAG_ORDEREDQ 0x10 682 u_int8_t msgPages; /* 07h */ 683 684 u_int32_t Context; /* 08h Address of this request */ 685 u_int32_t DataLength; /* 0ch not used now */ 686 687 u_int8_t Cdb[16]; /* 10h SCSI CDB */ 688 /* 689 ******************************************************** 690 **Device Status : the same from SCSI bus if error occur 691 ** SCSI bus status codes. 692 ******************************************************** 693 */ 694 u_int8_t DeviceStatus; /* 20h if error */ 695 #define SCSISTAT_GOOD 0x00 696 #define SCSISTAT_CHECK_CONDITION 0x02 697 #define SCSISTAT_CONDITION_MET 0x04 698 #define SCSISTAT_BUSY 0x08 699 #define SCSISTAT_INTERMEDIATE 0x10 700 #define SCSISTAT_INTERMEDIATE_COND_MET 0x14 701 #define SCSISTAT_RESERVATION_CONFLICT 0x18 702 #define SCSISTAT_COMMAND_TERMINATED 0x22 703 #define SCSISTAT_QUEUE_FULL 0x28 704 #define ARCMSR_DEV_SELECT_TIMEOUT 0xF0 705 #define ARCMSR_DEV_ABORTED 0xF1 706 #define ARCMSR_DEV_INIT_FAIL 0xF2 707 708 u_int8_t SenseData[15]; /* 21h output */ 709 710 union { 711 struct SG32ENTRY sg32entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h Scatter gather address */ 712 struct SG64ENTRY sg64entry[ARCMSR_MAX_SG_ENTRIES]; /* 30h */ 713 } u; 714 }; 715 /* 716 ********************************************************************* 717 ** Command Control Block (SrbExtension) 718 ** SRB must be not cross page boundary,and the order from offset 0 719 ** structure describing an ATA disk request 720 ** this SRB length must be 32 bytes boundary 721 ********************************************************************* 722 */ 723 struct CommandControlBlock { 724 struct ARCMSR_CDB arcmsr_cdb; /* 0 -503 (size of CDB=504): arcmsr messenger scsi command descriptor size 504 bytes */ 725 u_int32_t cdb_shifted_phyaddr; /* 504-507 */ 726 u_int32_t arc_cdb_size; /* 508-511 */ 727 /* ======================512+32 bytes============================ */ 728 union ccb *pccb; /* 512-515 516-519 pointer of freebsd scsi command */ 729 struct AdapterControlBlock *acb; /* 520-523 524-527 */ 730 bus_dmamap_t dm_segs_dmamap; /* 528-531 532-535 */ 731 u_int16_t srb_flags; /* 536-537 */ 732 u_int16_t srb_state; /* 538-539 */ 733 struct callout ccb_callout; 734 /* ========================================================== */ 735 }; 736 /* srb_flags */ 737 #define SRB_FLAG_READ 0x0000 738 #define SRB_FLAG_WRITE 0x0001 739 #define SRB_FLAG_ERROR 0x0002 740 #define SRB_FLAG_FLUSHCACHE 0x0004 741 #define SRB_FLAG_MASTER_ABORTED 0x0008 742 #define SRB_FLAG_DMAVALID 0x0010 743 #define SRB_FLAG_DMACONSISTENT 0x0020 744 #define SRB_FLAG_DMAWRITE 0x0040 745 #define SRB_FLAG_PKTBIND 0x0080 746 #define SRB_FLAG_TIMER_START 0x0080 747 /* srb_state */ 748 #define ARCMSR_SRB_DONE 0x0000 749 #define ARCMSR_SRB_UNBUILD 0x0000 750 #define ARCMSR_SRB_TIMEOUT 0x1111 751 #define ARCMSR_SRB_RETRY 0x2222 752 #define ARCMSR_SRB_START 0x55AA 753 #define ARCMSR_SRB_PENDING 0xAA55 754 #define ARCMSR_SRB_RESET 0xA5A5 755 #define ARCMSR_SRB_ABORTED 0x5A5A 756 #define ARCMSR_SRB_ILLEGAL 0xFFFF 757 /* 758 ********************************************************************* 759 ** Adapter Control Block 760 ********************************************************************* 761 */ 762 #define ACB_ADAPTER_TYPE_A 0x00000001 /* hba I IOP */ 763 #define ACB_ADAPTER_TYPE_B 0x00000002 /* hbb M IOP */ 764 #define ACB_ADAPTER_TYPE_C 0x00000004 /* hbc L IOP */ 765 #define ACB_ADAPTER_TYPE_D 0x00000008 /* hbd A IOP */ 766 767 struct AdapterControlBlock { 768 u_int32_t adapter_type; /* adapter A,B..... */ 769 770 bus_space_tag_t btag[2]; 771 bus_space_handle_t bhandle[2]; 772 bus_dma_tag_t parent_dmat; 773 bus_dma_tag_t dm_segs_dmat; /* dmat for buffer I/O */ 774 bus_dma_tag_t srb_dmat; /* dmat for freesrb */ 775 bus_dmamap_t srb_dmamap; 776 device_t pci_dev; 777 #if __FreeBSD_version < 503000 778 dev_t ioctl_dev; 779 #else 780 struct cdev *ioctl_dev; 781 #endif 782 int pci_unit; 783 784 struct resource *sys_res_arcmsr[2]; 785 struct resource *irqres; 786 void *ih; /* interrupt handle */ 787 788 /* Hooks into the CAM XPT */ 789 struct cam_sim *psim; 790 struct cam_path *ppath; 791 u_int8_t *uncacheptr; 792 unsigned long vir2phy_offset; 793 union { 794 unsigned long phyaddr; 795 struct { 796 u_int32_t phyadd_low; 797 u_int32_t phyadd_high; 798 }B; 799 } srb_phyaddr; 800 // unsigned long srb_phyaddr; 801 /* Offset is used in making arc cdb physical to virtual calculations */ 802 u_int32_t outbound_int_enable; 803 804 struct MessageUnit_UNION *pmu; /* message unit ATU inbound base address0 */ 805 806 u_int8_t adapter_index; /* */ 807 u_int8_t irq; 808 u_int16_t acb_flags; /* */ 809 810 struct CommandControlBlock *psrb_pool[ARCMSR_MAX_FREESRB_NUM]; /* serial srb pointer array */ 811 struct CommandControlBlock *srbworkingQ[ARCMSR_MAX_FREESRB_NUM]; /* working srb pointer array */ 812 int32_t workingsrb_doneindex; /* done srb array index */ 813 int32_t workingsrb_startindex; /* start srb array index */ 814 int32_t srboutstandingcount; 815 816 u_int8_t rqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for read from 80331 */ 817 u_int32_t rqbuf_firstindex; /* first of read buffer */ 818 u_int32_t rqbuf_lastindex; /* last of read buffer */ 819 820 u_int8_t wqbuffer[ARCMSR_MAX_QBUFFER]; /* data collection buffer for write to 80331 */ 821 u_int32_t wqbuf_firstindex; /* first of write buffer */ 822 u_int32_t wqbuf_lastindex; /* last of write buffer */ 823 824 arcmsr_lock_t workingQ_done_lock; 825 arcmsr_lock_t workingQ_start_lock; 826 arcmsr_lock_t qbuffer_lock; 827 828 u_int8_t devstate[ARCMSR_MAX_TARGETID][ARCMSR_MAX_TARGETLUN]; /* id0 ..... id15,lun0...lun7 */ 829 u_int32_t num_resets; 830 u_int32_t num_aborts; 831 u_int32_t firm_request_len; /*1,04-07*/ 832 u_int32_t firm_numbers_queue; /*2,08-11*/ 833 u_int32_t firm_sdram_size; /*3,12-15*/ 834 u_int32_t firm_ide_channels; /*4,16-19*/ 835 u_int32_t firm_cfg_version; 836 char firm_model[12]; /*15,60-67*/ 837 char firm_version[20]; /*17,68-83*/ 838 char device_map[20]; /*21,84-99 */ 839 struct callout devmap_callout; 840 #ifdef ARCMSR_DEBUG1 841 u_int32_t pktRequestCount; 842 u_int32_t pktReturnCount; 843 #endif 844 u_int32_t vendor_device_id; 845 u_int32_t adapter_bus_speed; 846 };/* HW_DEVICE_EXTENSION */ 847 /* acb_flags */ 848 #define ACB_F_SCSISTOPADAPTER 0x0001 849 #define ACB_F_MSG_STOP_BGRB 0x0002 /* stop RAID background rebuild */ 850 #define ACB_F_MSG_START_BGRB 0x0004 /* stop RAID background rebuild */ 851 #define ACB_F_IOPDATA_OVERFLOW 0x0008 /* iop ioctl data rqbuffer overflow */ 852 #define ACB_F_MESSAGE_WQBUFFER_CLEARED 0x0010 /* ioctl clear wqbuffer */ 853 #define ACB_F_MESSAGE_RQBUFFER_CLEARED 0x0020 /* ioctl clear rqbuffer */ 854 #define ACB_F_MESSAGE_WQBUFFER_READ 0x0040 855 #define ACB_F_BUS_RESET 0x0080 856 #define ACB_F_IOP_INITED 0x0100 /* iop init */ 857 #define ACB_F_MAPFREESRB_FAILD 0x0200 /* arcmsr_map_freesrb faild */ 858 #define ACB_F_CAM_DEV_QFRZN 0x0400 859 #define ACB_F_BUS_HANG_ON 0x0800 /* need hardware reset bus */ 860 #define ACB_F_SRB_FUNCTION_POWER 0x1000 861 /* devstate */ 862 #define ARECA_RAID_GONE 0x55 863 #define ARECA_RAID_GOOD 0xaa 864 /* adapter_bus_speed */ 865 #define ACB_BUS_SPEED_3G 0 866 #define ACB_BUS_SPEED_6G 1 867 #define ACB_BUS_SPEED_12G 2 868 /* 869 ********************************************************************* 870 ** Message Unit structure 871 ********************************************************************* 872 */ 873 struct HBA_MessageUnit 874 { 875 u_int32_t resrved0[4]; /*0000 000F*/ 876 u_int32_t inbound_msgaddr0; /*0010 0013*/ 877 u_int32_t inbound_msgaddr1; /*0014 0017*/ 878 u_int32_t outbound_msgaddr0; /*0018 001B*/ 879 u_int32_t outbound_msgaddr1; /*001C 001F*/ 880 u_int32_t inbound_doorbell; /*0020 0023*/ 881 u_int32_t inbound_intstatus; /*0024 0027*/ 882 u_int32_t inbound_intmask; /*0028 002B*/ 883 u_int32_t outbound_doorbell; /*002C 002F*/ 884 u_int32_t outbound_intstatus; /*0030 0033*/ 885 u_int32_t outbound_intmask; /*0034 0037*/ 886 u_int32_t reserved1[2]; /*0038 003F*/ 887 u_int32_t inbound_queueport; /*0040 0043*/ 888 u_int32_t outbound_queueport; /*0044 0047*/ 889 u_int32_t reserved2[2]; /*0048 004F*/ 890 u_int32_t reserved3[492]; /*0050 07FF ......local_buffer 492*/ 891 u_int32_t reserved4[128]; /*0800 09FF 128*/ 892 u_int32_t msgcode_rwbuffer[256]; /*0a00 0DFF 256*/ 893 u_int32_t message_wbuffer[32]; /*0E00 0E7F 32*/ 894 u_int32_t reserved5[32]; /*0E80 0EFF 32*/ 895 u_int32_t message_rbuffer[32]; /*0F00 0F7F 32*/ 896 u_int32_t reserved6[32]; /*0F80 0FFF 32*/ 897 }; 898 /* 899 ********************************************************************* 900 ** 901 ********************************************************************* 902 */ 903 struct HBB_DOORBELL 904 { 905 u_int8_t doorbell_reserved[ARCMSR_DRV2IOP_DOORBELL]; /*reserved */ 906 u_int32_t drv2iop_doorbell; /*offset 0x00020400:00,01,02,03: window of "instruction flags" from driver to iop */ 907 u_int32_t drv2iop_doorbell_mask; /* 04,05,06,07: doorbell mask */ 908 u_int32_t iop2drv_doorbell; /* 08,09,10,11: window of "instruction flags" from iop to driver */ 909 u_int32_t iop2drv_doorbell_mask; /* 12,13,14,15: doorbell mask */ 910 }; 911 /* 912 ********************************************************************* 913 ** 914 ********************************************************************* 915 */ 916 struct HBB_RWBUFFER 917 { 918 u_int8_t message_reserved0[ARCMSR_MSGCODE_RWBUFFER]; /*reserved */ 919 u_int32_t msgcode_rwbuffer[256]; /*offset 0x0000fa00: 0, 1, 2, 3,...,1023: message code read write 1024bytes */ 920 u_int32_t message_wbuffer[32]; /*offset 0x0000fe00:1024,1025,1026,1027,...,1151: user space data to iop 128bytes */ 921 u_int32_t message_reserved1[32]; /* 1152,1153,1154,1155,...,1279: message reserved*/ 922 u_int32_t message_rbuffer[32]; /*offset 0x0000ff00:1280,1281,1282,1283,...,1407: iop data to user space 128bytes */ 923 }; 924 /* 925 ********************************************************************* 926 ** 927 ********************************************************************* 928 */ 929 struct HBB_MessageUnit 930 { 931 u_int32_t post_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* post queue buffer for iop */ 932 u_int32_t done_qbuffer[ARCMSR_MAX_HBB_POSTQUEUE]; /* done queue buffer for iop */ 933 int32_t postq_index; /* post queue index */ 934 int32_t doneq_index; /* done queue index */ 935 struct HBB_DOORBELL *hbb_doorbell; 936 struct HBB_RWBUFFER *hbb_rwbuffer; 937 }; 938 939 /* 940 ********************************************************************* 941 ** 942 ********************************************************************* 943 */ 944 struct HBC_MessageUnit { 945 u_int32_t message_unit_status; /*0000 0003*/ 946 u_int32_t slave_error_attribute; /*0004 0007*/ 947 u_int32_t slave_error_address; /*0008 000B*/ 948 u_int32_t posted_outbound_doorbell; /*000C 000F*/ 949 u_int32_t master_error_attribute; /*0010 0013*/ 950 u_int32_t master_error_address_low; /*0014 0017*/ 951 u_int32_t master_error_address_high; /*0018 001B*/ 952 u_int32_t hcb_size; /*001C 001F size of the PCIe window used for HCB_Mode accesses*/ 953 u_int32_t inbound_doorbell; /*0020 0023*/ 954 u_int32_t diagnostic_rw_data; /*0024 0027*/ 955 u_int32_t diagnostic_rw_address_low; /*0028 002B*/ 956 u_int32_t diagnostic_rw_address_high; /*002C 002F*/ 957 u_int32_t host_int_status; /*0030 0033 host interrupt status*/ 958 u_int32_t host_int_mask; /*0034 0037 host interrupt mask*/ 959 u_int32_t dcr_data; /*0038 003B*/ 960 u_int32_t dcr_address; /*003C 003F*/ 961 u_int32_t inbound_queueport; /*0040 0043 port32 host inbound queue port*/ 962 u_int32_t outbound_queueport; /*0044 0047 port32 host outbound queue port*/ 963 u_int32_t hcb_pci_address_low; /*0048 004B*/ 964 u_int32_t hcb_pci_address_high; /*004C 004F*/ 965 u_int32_t iop_int_status; /*0050 0053*/ 966 u_int32_t iop_int_mask; /*0054 0057*/ 967 u_int32_t iop_inbound_queue_port; /*0058 005B*/ 968 u_int32_t iop_outbound_queue_port; /*005C 005F*/ 969 u_int32_t inbound_free_list_index; /*0060 0063 inbound free list producer consumer index*/ 970 u_int32_t inbound_post_list_index; /*0064 0067 inbound post list producer consumer index*/ 971 u_int32_t outbound_free_list_index; /*0068 006B outbound free list producer consumer index*/ 972 u_int32_t outbound_post_list_index; /*006C 006F outbound post list producer consumer index*/ 973 u_int32_t inbound_doorbell_clear; /*0070 0073*/ 974 u_int32_t i2o_message_unit_control; /*0074 0077*/ 975 u_int32_t last_used_message_source_address_low; /*0078 007B*/ 976 u_int32_t last_used_message_source_address_high; /*007C 007F*/ 977 u_int32_t pull_mode_data_byte_count[4]; /*0080 008F pull mode data byte count0..count7*/ 978 u_int32_t message_dest_address_index; /*0090 0093*/ 979 u_int32_t done_queue_not_empty_int_counter_timer; /*0094 0097*/ 980 u_int32_t utility_A_int_counter_timer; /*0098 009B*/ 981 u_int32_t outbound_doorbell; /*009C 009F*/ 982 u_int32_t outbound_doorbell_clear; /*00A0 00A3*/ 983 u_int32_t message_source_address_index; /*00A4 00A7 message accelerator source address consumer producer index*/ 984 u_int32_t message_done_queue_index; /*00A8 00AB message accelerator completion queue consumer producer index*/ 985 u_int32_t reserved0; /*00AC 00AF*/ 986 u_int32_t inbound_msgaddr0; /*00B0 00B3 scratchpad0*/ 987 u_int32_t inbound_msgaddr1; /*00B4 00B7 scratchpad1*/ 988 u_int32_t outbound_msgaddr0; /*00B8 00BB scratchpad2*/ 989 u_int32_t outbound_msgaddr1; /*00BC 00BF scratchpad3*/ 990 u_int32_t inbound_queueport_low; /*00C0 00C3 port64 host inbound queue port low*/ 991 u_int32_t inbound_queueport_high; /*00C4 00C7 port64 host inbound queue port high*/ 992 u_int32_t outbound_queueport_low; /*00C8 00CB port64 host outbound queue port low*/ 993 u_int32_t outbound_queueport_high; /*00CC 00CF port64 host outbound queue port high*/ 994 u_int32_t iop_inbound_queue_port_low; /*00D0 00D3*/ 995 u_int32_t iop_inbound_queue_port_high; /*00D4 00D7*/ 996 u_int32_t iop_outbound_queue_port_low; /*00D8 00DB*/ 997 u_int32_t iop_outbound_queue_port_high; /*00DC 00DF*/ 998 u_int32_t message_dest_queue_port_low; /*00E0 00E3 message accelerator destination queue port low*/ 999 u_int32_t message_dest_queue_port_high; /*00E4 00E7 message accelerator destination queue port high*/ 1000 u_int32_t last_used_message_dest_address_low; /*00E8 00EB last used message accelerator destination address low*/ 1001 u_int32_t last_used_message_dest_address_high; /*00EC 00EF last used message accelerator destination address high*/ 1002 u_int32_t message_done_queue_base_address_low; /*00F0 00F3 message accelerator completion queue base address low*/ 1003 u_int32_t message_done_queue_base_address_high; /*00F4 00F7 message accelerator completion queue base address high*/ 1004 u_int32_t host_diagnostic; /*00F8 00FB*/ 1005 u_int32_t write_sequence; /*00FC 00FF*/ 1006 u_int32_t reserved1[34]; /*0100 0187*/ 1007 u_int32_t reserved2[1950]; /*0188 1FFF*/ 1008 u_int32_t message_wbuffer[32]; /*2000 207F*/ 1009 u_int32_t reserved3[32]; /*2080 20FF*/ 1010 u_int32_t message_rbuffer[32]; /*2100 217F*/ 1011 u_int32_t reserved4[32]; /*2180 21FF*/ 1012 u_int32_t msgcode_rwbuffer[256]; /*2200 23FF*/ 1013 }; 1014 1015 /* 1016 ********************************************************************* 1017 ** 1018 ********************************************************************* 1019 */ 1020 struct MessageUnit_UNION 1021 { 1022 union { 1023 struct HBA_MessageUnit hbamu; 1024 struct HBB_MessageUnit hbbmu; 1025 struct HBC_MessageUnit hbcmu; 1026 } muu; 1027 }; 1028 1029 /* 1030 ************************************************************* 1031 ************************************************************* 1032 */ 1033 struct SENSE_DATA { 1034 u_int8_t ErrorCode:7; 1035 u_int8_t Valid:1; 1036 u_int8_t SegmentNumber; 1037 u_int8_t SenseKey:4; 1038 u_int8_t Reserved:1; 1039 u_int8_t IncorrectLength:1; 1040 u_int8_t EndOfMedia:1; 1041 u_int8_t FileMark:1; 1042 u_int8_t Information[4]; 1043 u_int8_t AdditionalSenseLength; 1044 u_int8_t CommandSpecificInformation[4]; 1045 u_int8_t AdditionalSenseCode; 1046 u_int8_t AdditionalSenseCodeQualifier; 1047 u_int8_t FieldReplaceableUnitCode; 1048 u_int8_t SenseKeySpecific[3]; 1049 }; 1050 /* 1051 ********************************** 1052 ** Peripheral Device Type definitions 1053 ********************************** 1054 */ 1055 #define SCSI_DASD 0x00 /* Direct-access Device */ 1056 #define SCSI_SEQACESS 0x01 /* Sequential-access device */ 1057 #define SCSI_PRINTER 0x02 /* Printer device */ 1058 #define SCSI_PROCESSOR 0x03 /* Processor device */ 1059 #define SCSI_WRITEONCE 0x04 /* Write-once device */ 1060 #define SCSI_CDROM 0x05 /* CD-ROM device */ 1061 #define SCSI_SCANNER 0x06 /* Scanner device */ 1062 #define SCSI_OPTICAL 0x07 /* Optical memory device */ 1063 #define SCSI_MEDCHGR 0x08 /* Medium changer device */ 1064 #define SCSI_COMM 0x09 /* Communications device */ 1065 #define SCSI_NODEV 0x1F /* Unknown or no device type */ 1066 /* 1067 ************************************************************************************************************ 1068 ** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 1069 ** 80331 PCI-to-PCI Bridge 1070 ** PCI Configuration Space 1071 ** 1072 ** @@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@ 1073 ** Programming Interface 1074 ** ======================== 1075 ** Configuration Register Address Space Groupings and Ranges 1076 ** ============================================================= 1077 ** Register Group Configuration Offset 1078 ** ------------------------------------------------------------- 1079 ** Standard PCI Configuration 00-3Fh 1080 ** ------------------------------------------------------------- 1081 ** Device Specific Registers 40-A7h 1082 ** ------------------------------------------------------------- 1083 ** Reserved A8-CBh 1084 ** ------------------------------------------------------------- 1085 ** Enhanced Capability List CC-FFh 1086 ** ========================================================================================================== 1087 ** Standard PCI [Type 1] Configuration Space Address Map 1088 ** ********************************************************************************************************** 1089 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 1090 ** ---------------------------------------------------------------------------------------------------------- 1091 ** | Device ID | Vendor ID | 00h 1092 ** ---------------------------------------------------------------------------------------------------------- 1093 ** | Primary Status | Primary Command | 04h 1094 ** ---------------------------------------------------------------------------------------------------------- 1095 ** | Class Code | RevID | 08h 1096 ** ---------------------------------------------------------------------------------------------------------- 1097 ** | reserved | Header Type | Primary MLT | Primary CLS | 0Ch 1098 ** ---------------------------------------------------------------------------------------------------------- 1099 ** | Reserved | 10h 1100 ** ---------------------------------------------------------------------------------------------------------- 1101 ** | Reserved | 14h 1102 ** ---------------------------------------------------------------------------------------------------------- 1103 ** | Secondary MLT | Subordinate Bus Number | Secondary Bus Number | Primary Bus Number | 18h 1104 ** ---------------------------------------------------------------------------------------------------------- 1105 ** | Secondary Status | I/O Limit | I/O Base | 1Ch 1106 ** ---------------------------------------------------------------------------------------------------------- 1107 ** | Non-prefetchable Memory Limit Address | Non-prefetchable Memory Base Address | 20h 1108 ** ---------------------------------------------------------------------------------------------------------- 1109 ** | Prefetchable Memory Limit Address | Prefetchable Memory Base Address | 24h 1110 ** ---------------------------------------------------------------------------------------------------------- 1111 ** | Prefetchable Memory Base Address Upper 32 Bits | 28h 1112 ** ---------------------------------------------------------------------------------------------------------- 1113 ** | Prefetchable Memory Limit Address Upper 32 Bits | 2Ch 1114 ** ---------------------------------------------------------------------------------------------------------- 1115 ** | I/O Limit Upper 16 Bits | I/O Base Upper 16 | 30h 1116 ** ---------------------------------------------------------------------------------------------------------- 1117 ** | Reserved | Capabilities Pointer | 34h 1118 ** ---------------------------------------------------------------------------------------------------------- 1119 ** | Reserved | 38h 1120 ** ---------------------------------------------------------------------------------------------------------- 1121 ** | Bridge Control | Primary Interrupt Pin | Primary Interrupt Line | 3Ch 1122 **============================================================================================================= 1123 */ 1124 /* 1125 **============================================================================================================= 1126 ** 0x03-0x00 : 1127 ** Bit Default Description 1128 **31:16 0335h Device ID (DID): Indicates the unique device ID that is assigned to bridge by the PCI SIG. 1129 ** ID is unique per product speed as indicated. 1130 **15:00 8086h Vendor ID (VID): 16-bit field which indicates that Intel is the vendor. 1131 **============================================================================================================= 1132 */ 1133 #define ARCMSR_PCI2PCI_VENDORID_REG 0x00 /*word*/ 1134 #define ARCMSR_PCI2PCI_DEVICEID_REG 0x02 /*word*/ 1135 /* 1136 **============================================================================== 1137 ** 0x05-0x04 : command register 1138 ** Bit Default Description 1139 **15:11 00h Reserved 1140 ** 10 0 Interrupt Disable: Disables/Enables the generation of Interrupts on the primary bus. 1141 ** The bridge does not support interrupts. 1142 ** 09 0 FB2B Enable: Enables/Disables the generation of fast back to back 1143 ** transactions on the primary bus. 1144 ** The bridge does not generate fast back to back 1145 ** transactions on the primary bus. 1146 ** 08 0 SERR# Enable (SEE): Enables primary bus SERR# assertions. 1147 ** 0=The bridge does not assert P_SERR#. 1148 ** 1=The bridge may assert P_SERR#, subject to other programmable criteria. 1149 ** 07 0 Wait Cycle Control (WCC): Always returns 0bzero indicating 1150 ** that bridge does not perform address or data stepping, 1151 ** 06 0 Parity Error Response (PER): Controls bridge response to a detected primary bus parity error. 1152 ** 0=When a data parity error is detected bridge does not assert S_PERR#. 1153 ** Also bridge does not assert P_SERR# in response to 1154 ** a detected address or attribute parity error. 1155 ** 1=When a data parity error is detected bridge asserts S_PERR#. 1156 ** The bridge also asserts P_SERR# 1157 ** (when enabled globally via bit(8) of this register) 1158 ** in response to a detected address or attribute parity error. 1159 ** 05 0 VGA Palette Snoop Enable (VGA_PSE): Controls bridge response to VGA-compatible palette write transactions. 1160 ** VGA palette write transactions are I/O transactions 1161 ** whose address bits are: P_AD[9:0] equal to 3C6h, 3C8h or 3C9h 1162 ** P_AD[15:10] are not decoded (i.e. aliases are claimed), 1163 ** or are fully decoding 1164 ** (i.e., must be all 0's depending upon the VGA 1165 ** aliasing bit in the Bridge Control Register, offset 3Eh. 1166 ** P_AD[31:16] equal to 0000h 1167 ** 0=The bridge ignores VGA palette write transactions, 1168 ** unless decoded by the standard I/O address range window. 1169 ** 1=The bridge responds to VGA palette write transactions 1170 ** with medium DEVSEL# timing and forwards them to the secondary bus. 1171 ** 04 0 Memory Write and Invalidate Enable (MWIE): The bridge does not promote MW transactions to MWI transactions. 1172 ** MWI transactions targeting resources on the opposite side of the bridge, 1173 ** however, are forwarded as MWI transactions. 1174 ** 03 0 Special Cycle Enable (SCE): The bridge ignores special cycle transactions. 1175 ** This bit is read only and always returns 0 when read 1176 ** 02 0 Bus Master Enable (BME): Enables bridge to initiate memory and I/O transactions on the primary interface. 1177 ** Initiation of configuration transactions is not affected by the state of this bit. 1178 ** 0=The bridge does not initiate memory or I/O transactions on the primary interface. 1179 ** 1=The bridge is enabled to function as an initiator on the primary interface. 1180 ** 01 0 Memory Space Enable (MSE): Controls target response to memory transactions on the primary interface. 1181 ** 0=The bridge target response to memory transactions on the primary interface is disabled. 1182 ** 1=The bridge target response to memory transactions on the primary interface is enabled. 1183 ** 00 0 I/O Space Enable (IOSE): Controls target response to I/O transactions on the primary interface. 1184 ** 0=The bridge target response to I/O transactions on the primary interface is disabled. 1185 ** 1=The bridge target response to I/O transactions on the primary interface is enabled. 1186 **============================================================================== 1187 */ 1188 #define ARCMSR_PCI2PCI_PRIMARY_COMMAND_REG 0x04 /*word*/ 1189 #define PCI_DISABLE_INTERRUPT 0x0400 1190 /* 1191 **============================================================================== 1192 ** 0x07-0x06 : status register 1193 ** Bit Default Description 1194 ** 15 0 Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address, 1195 ** attribute or data parity error. 1196 ** This bit is set regardless of the state of the PER bit in the command register. 1197 ** 14 0 Signaled System Error: The bridge sets this bit to a 1b whenever it asserts SERR# on the primary bus. 1198 ** 13 0 Received Master Abort: The bridge sets this bit to a 1b when, 1199 ** acting as the initiator on the primary bus, 1200 ** its transaction (with the exception of special cycles) 1201 ** has been terminated with a Master Abort. 1202 ** 12 0 Received Target Abort: The bridge sets this bit to a 1b when, 1203 ** acting as the initiator on the primary bus, 1204 ** its transaction has been terminated with a Target Abort. 1205 ** 11 0 Signaled Target Abort: The bridge sets this bit to a 1b when it, 1206 ** as the target of a transaction, terminates it with a Target Abort. 1207 ** In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code. 1208 ** 10:09 01 DEVSEL# Timing: Indicates slowest response to a non-configuration command on the primary interface. 1209 ** Returns ��01b�� when read, indicating that bridge responds no slower than with medium timing. 1210 ** 08 0 Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true: 1211 ** The bridge is the current master on the primary bus 1212 ** S_PERR# is detected asserted or is asserted by bridge 1213 ** The Parity Error Response bit is set in the Command register 1214 ** 07 1 Fast Back to Back Capable: Returns a 1b when read indicating that bridge 1215 ** is able to respond to fast back to back transactions on its primary interface. 1216 ** 06 0 Reserved 1217 ** 05 1 66 MHz Capable Indication: Returns a 1b when read indicating that bridge primary interface is 66 MHz capable. 1218 ** 1 = 1219 ** 04 1 Capabilities List Enable: Returns 1b when read indicating that bridge supports PCI standard enhanced capabilities. 1220 ** Offset 34h (Capability Pointer register) 1221 ** provides the offset for the first entry 1222 ** in the linked list of enhanced capabilities. 1223 ** 03 0 Interrupt Status: Reflects the state of the interrupt in the device/function. 1224 ** The bridge does not support interrupts. 1225 ** 02:00 000 Reserved 1226 **============================================================================== 1227 */ 1228 #define ARCMSR_PCI2PCI_PRIMARY_STATUS_REG 0x06 /*word: 06,07 */ 1229 #define ARCMSR_ADAP_66MHZ 0x20 1230 /* 1231 **============================================================================== 1232 ** 0x08 : revision ID 1233 ** Bit Default Description 1234 ** 07:00 00000000 Revision ID (RID): '00h' indicating bridge A-0 stepping. 1235 **============================================================================== 1236 */ 1237 #define ARCMSR_PCI2PCI_REVISIONID_REG 0x08 /*byte*/ 1238 /* 1239 **============================================================================== 1240 ** 0x0b-0x09 : 0180_00 (class code 1,native pci mode ) 1241 ** Bit Default Description 1242 ** 23:16 06h Base Class Code (BCC): Indicates that this is a bridge device. 1243 ** 15:08 04h Sub Class Code (SCC): Indicates this is of type PCI-to-PCI bridge. 1244 ** 07:00 00h Programming Interface (PIF): Indicates that this is standard (non-subtractive) PCI-PCI bridge. 1245 **============================================================================== 1246 */ 1247 #define ARCMSR_PCI2PCI_CLASSCODE_REG 0x09 /*3bytes*/ 1248 /* 1249 **============================================================================== 1250 ** 0x0c : cache line size 1251 ** Bit Default Description 1252 ** 07:00 00h Cache Line Size (CLS): Designates the cache line size in 32-bit dword units. 1253 ** The contents of this register are factored into 1254 ** internal policy decisions associated with memory read prefetching, 1255 ** and the promotion of Memory Write transactions to MWI transactions. 1256 ** Valid cache line sizes are 8 and 16 dwords. 1257 ** When the cache line size is set to an invalid value, 1258 ** bridge behaves as though the cache line size was set to 00h. 1259 **============================================================================== 1260 */ 1261 #define ARCMSR_PCI2PCI_PRIMARY_CACHELINESIZE_REG 0x0C /*byte*/ 1262 /* 1263 **============================================================================== 1264 ** 0x0d : latency timer (number of pci clock 00-ff ) 1265 ** Bit Default Description 1266 ** Primary Latency Timer (PTV): 1267 ** 07:00 00h (Conventional PCI) Conventional PCI Mode: Primary bus Master latency timer. Indicates the number of PCI clock cycles, 1268 ** referenced from the assertion of FRAME# to the expiration of the timer, 1269 ** when bridge may continue as master of the current transaction. All bits are writable, 1270 ** resulting in a granularity of 1 PCI clock cycle. 1271 ** When the timer expires (i.e., equals 00h) 1272 ** bridge relinquishes the bus after the first data transfer 1273 ** when its PCI bus grant has been deasserted. 1274 ** or 40h (PCI-X) PCI-X Mode: Primary bus Master latency timer. 1275 ** Indicates the number of PCI clock cycles, 1276 ** referenced from the assertion of FRAME# to the expiration of the timer, 1277 ** when bridge may continue as master of the current transaction. 1278 ** All bits are writable, resulting in a granularity of 1 PCI clock cycle. 1279 ** When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB. 1280 ** (Except in the case where MLT expires within 3 data phases 1281 ** of an ADB.In this case bridge continues on 1282 ** until it reaches the next ADB before relinquishing the bus.) 1283 **============================================================================== 1284 */ 1285 #define ARCMSR_PCI2PCI_PRIMARY_LATENCYTIMER_REG 0x0D /*byte*/ 1286 /* 1287 **============================================================================== 1288 ** 0x0e : (header type,single function ) 1289 ** Bit Default Description 1290 ** 07 0 Multi-function device (MVD): 80331 is a single-function device. 1291 ** 06:00 01h Header Type (HTYPE): Defines the layout of addresses 10h through 3Fh in configuration space. 1292 ** Returns ��01h�� when read indicating 1293 ** that the register layout conforms to the standard PCI-to-PCI bridge layout. 1294 **============================================================================== 1295 */ 1296 #define ARCMSR_PCI2PCI_HEADERTYPE_REG 0x0E /*byte*/ 1297 /* 1298 **============================================================================== 1299 ** 0x0f : 1300 **============================================================================== 1301 */ 1302 /* 1303 **============================================================================== 1304 ** 0x13-0x10 : 1305 ** PCI CFG Base Address #0 (0x10) 1306 **============================================================================== 1307 */ 1308 /* 1309 **============================================================================== 1310 ** 0x17-0x14 : 1311 ** PCI CFG Base Address #1 (0x14) 1312 **============================================================================== 1313 */ 1314 /* 1315 **============================================================================== 1316 ** 0x1b-0x18 : 1317 ** PCI CFG Base Address #2 (0x18) 1318 **-----------------0x1A,0x19,0x18--Bus Number Register - BNR 1319 ** Bit Default Description 1320 ** 23:16 00h Subordinate Bus Number (SBBN): Indicates the highest PCI bus number below this bridge. 1321 ** Any Type 1 configuration cycle 1322 ** on the primary bus whose bus number is greater than the secondary bus number, 1323 ** and less than or equal to the subordinate bus number 1324 ** is forwarded unaltered as a Type 1 configuration cycle on the secondary PCI bus. 1325 ** 15:08 00h Secondary Bus Number (SCBN): Indicates the bus number of PCI to which the secondary interface is connected. 1326 ** Any Type 1 configuration cycle matching this bus number 1327 ** is translated to a Type 0 configuration cycle (or a Special Cycle) 1328 ** before being executed on bridge's secondary PCI bus. 1329 ** 07:00 00h Primary Bus Number (PBN): Indicates bridge primary bus number. 1330 ** Any Type 1 configuration cycle on the primary interface 1331 ** with a bus number that is less than the contents 1332 ** of this register field does not be claimed by bridge. 1333 **-----------------0x1B--Secondary Latency Timer Register - SLTR 1334 ** Bit Default Description 1335 ** Secondary Latency Timer (STV): 1336 ** 07:00 00h (Conventional PCI) Conventional PCI Mode: Secondary bus Master latency timer. 1337 ** Indicates the number of PCI clock cycles, 1338 ** referenced from the assertion of FRAME# to the expiration of the timer, 1339 ** when bridge may continue as master of the current transaction. All bits are writable, 1340 ** resulting in a granularity of 1 PCI clock cycle. 1341 ** When the timer expires (i.e., equals 00h) 1342 ** bridge relinquishes the bus after the first data transfer 1343 ** when its PCI bus grant has been deasserted. 1344 ** or 40h (PCI-X) PCI-X Mode: Secondary bus Master latency timer. 1345 ** Indicates the number of PCI clock cycles,referenced from the assertion of FRAME# 1346 ** to the expiration of the timer, 1347 ** when bridge may continue as master of the current transaction. All bits are writable, 1348 ** resulting in a granularity of 1 PCI clock cycle. 1349 ** When the timer expires (i.e., equals 00h) bridge relinquishes the bus at the next ADB. 1350 ** (Except in the case where MLT expires within 3 data phases of an ADB. 1351 ** In this case bridge continues on until it reaches the next ADB 1352 ** before relinquishing the bus) 1353 **============================================================================== 1354 */ 1355 #define ARCMSR_PCI2PCI_PRIMARY_BUSNUMBER_REG 0x18 /*3byte 0x1A,0x19,0x18*/ 1356 #define ARCMSR_PCI2PCI_SECONDARY_BUSNUMBER_REG 0x19 /*byte*/ 1357 #define ARCMSR_PCI2PCI_SUBORDINATE_BUSNUMBER_REG 0x1A /*byte*/ 1358 #define ARCMSR_PCI2PCI_SECONDARY_LATENCYTIMER_REG 0x1B /*byte*/ 1359 /* 1360 **============================================================================== 1361 ** 0x1f-0x1c : 1362 ** PCI CFG Base Address #3 (0x1C) 1363 **-----------------0x1D,0x1C--I/O Base and Limit Register - IOBL 1364 ** Bit Default Description 1365 ** 15:12 0h I/O Limit Address Bits [15:12]: Defines the top address of an address range to 1366 ** determine when to forward I/O transactions from one interface to the other. 1367 ** These bits correspond to address lines 15:12 for 4KB alignment. 1368 ** Bits 11:0 are assumed to be FFFh. 1369 ** 11:08 1h I/O Limit Addressing Capability: This field is hard-wired to 1h, indicating support 32-bit I/O addressing. 1370 ** 07:04 0h I/O Base Address Bits [15:12]: Defines the bottom address of 1371 ** an address range to determine when to forward I/O transactions 1372 ** from one interface to the other. 1373 ** These bits correspond to address lines 15:12 for 4KB alignment. 1374 ** Bits 11:0 are assumed to be 000h. 1375 ** 03:00 1h I/O Base Addressing Capability: This is hard-wired to 1h, indicating support for 32-bit I/O addressing. 1376 **-----------------0x1F,0x1E--Secondary Status Register - SSR 1377 ** Bit Default Description 1378 ** 15 0b Detected Parity Error: The bridge sets this bit to a 1b whenever it detects an address, 1379 ** attribute or data parity error on its secondary interface. 1380 ** 14 0b Received System Error: The bridge sets this bit when it samples SERR# asserted on its secondary bus interface. 1381 ** 13 0b Received Master Abort: The bridge sets this bit to a 1b when, 1382 ** acting as the initiator on the secondary bus, 1383 ** it's transaction (with the exception of special cycles) 1384 ** has been terminated with a Master Abort. 1385 ** 12 0b Received Target Abort: The bridge sets this bit to a 1b when, 1386 ** acting as the initiator on the secondary bus, 1387 ** it's transaction has been terminated with a Target Abort. 1388 ** 11 0b Signaled Target Abort: The bridge sets this bit to a 1b when it, 1389 ** as the target of a transaction, terminates it with a Target Abort. 1390 ** In PCI-X mode this bit is also set when it forwards a SCM with a target abort error code. 1391 ** 10:09 01b DEVSEL# Timing: Indicates slowest response to a non-configuration command on the secondary interface. 1392 ** Returns ��01b�� when read, indicating that bridge responds no slower than with medium timing. 1393 ** 08 0b Master Data Parity Error: The bridge sets this bit to a 1b when all of the following conditions are true: 1394 ** The bridge is the current master on the secondary bus 1395 ** S_PERR# is detected asserted or is asserted by bridge 1396 ** The Parity Error Response bit is set in the Command register 1397 ** 07 1b Fast Back-to-Back Capable (FBC): Indicates that the secondary interface of bridge can receive fast back-to-back cycles. 1398 ** 06 0b Reserved 1399 ** 05 1b 66 MHz Capable (C66): Indicates the secondary interface of the bridge is 66 MHz capable. 1400 ** 1 = 1401 ** 04:00 00h Reserved 1402 **============================================================================== 1403 */ 1404 #define ARCMSR_PCI2PCI_IO_BASE_REG 0x1C /*byte*/ 1405 #define ARCMSR_PCI2PCI_IO_LIMIT_REG 0x1D /*byte*/ 1406 #define ARCMSR_PCI2PCI_SECONDARY_STATUS_REG 0x1E /*word: 0x1F,0x1E */ 1407 /* 1408 **============================================================================== 1409 ** 0x23-0x20 : 1410 ** PCI CFG Base Address #4 (0x20) 1411 **-----------------0x23,0x22,0x21,0x20--Memory Base and Limit Register - MBL 1412 ** Bit Default Description 1413 ** 31:20 000h Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine 1414 ** the upper 1MB aligned value (exclusive) of the range. 1415 ** The incoming address must be less than or equal to this value. 1416 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0] 1417 ** are assumed to be F FFFFh. 1418 ** 19:16 0h Reserved. 1419 ** 15:04 000h Memory Base: These 12 bits are compared with bits P_AD[31:20] 1420 ** of the incoming address to determine the lower 1MB 1421 ** aligned value (inclusive) of the range. 1422 ** The incoming address must be greater than or equal to this value. 1423 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0]) 1424 ** are assumed to be 0 0000h. 1425 ** 03:00 0h Reserved. 1426 **============================================================================== 1427 */ 1428 #define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_BASE_REG 0x20 /*word: 0x21,0x20 */ 1429 #define ARCMSR_PCI2PCI_NONPREFETCHABLE_MEMORY_LIMIT_REG 0x22 /*word: 0x23,0x22 */ 1430 /* 1431 **============================================================================== 1432 ** 0x27-0x24 : 1433 ** PCI CFG Base Address #5 (0x24) 1434 **-----------------0x27,0x26,0x25,0x24--Prefetchable Memory Base and Limit Register - PMBL 1435 ** Bit Default Description 1436 ** 31:20 000h Prefetchable Memory Limit: These 12 bits are compared with P_AD[31:20] of the incoming address to determine 1437 ** the upper 1MB aligned value (exclusive) of the range. 1438 ** The incoming address must be less than or equal to this value. 1439 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0] 1440 ** are assumed to be F FFFFh. 1441 ** 19:16 1h 64-bit Indicator: Indicates that 64-bit addressing is supported. 1442 ** 15:04 000h Prefetchable Memory Base: These 12 bits are compared with bits P_AD[31:20] 1443 ** of the incoming address to determine the lower 1MB aligned value (inclusive) 1444 ** of the range. 1445 ** The incoming address must be greater than or equal to this value. 1446 ** For the purposes of address decoding the lower 20 address bits (P_AD[19:0]) 1447 ** are assumed to be 0 0000h. 1448 ** 03:00 1h 64-bit Indicator: Indicates that 64-bit addressing is supported. 1449 **============================================================================== 1450 */ 1451 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_REG 0x24 /*word: 0x25,0x24 */ 1452 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_REG 0x26 /*word: 0x27,0x26 */ 1453 /* 1454 **============================================================================== 1455 ** 0x2b-0x28 : 1456 ** Bit Default Description 1457 ** 31:00 00000000h Prefetchable Memory Base Upper Portion: All bits are read/writable 1458 ** bridge supports full 64-bit addressing. 1459 **============================================================================== 1460 */ 1461 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_BASE_UPPER32_REG 0x28 /*dword: 0x2b,0x2a,0x29,0x28 */ 1462 /* 1463 **============================================================================== 1464 ** 0x2f-0x2c : 1465 ** Bit Default Description 1466 ** 31:00 00000000h Prefetchable Memory Limit Upper Portion: All bits are read/writable 1467 ** bridge supports full 64-bit addressing. 1468 **============================================================================== 1469 */ 1470 #define ARCMSR_PCI2PCI_PREFETCHABLE_MEMORY_LIMIT_UPPER32_REG 0x2C /*dword: 0x2f,0x2e,0x2d,0x2c */ 1471 /* 1472 **============================================================================== 1473 ** 0x33-0x30 : 1474 ** Bit Default Description 1475 ** 07:00 DCh Capabilities Pointer: Pointer to the first CAP ID entry in the capabilities list is at DCh in PCI configuration 1476 ** space. (Power Management Capability Registers) 1477 **============================================================================== 1478 */ 1479 #define ARCMSR_PCI2PCI_CAPABILITIES_POINTER_REG 0x34 /*byte*/ 1480 /* 1481 **============================================================================== 1482 ** 0x3b-0x35 : reserved 1483 **============================================================================== 1484 */ 1485 /* 1486 **============================================================================== 1487 ** 0x3d-0x3c : 1488 ** 1489 ** Bit Default Description 1490 ** 15:08 00h Interrupt Pin (PIN): Bridges do not support the generation of interrupts. 1491 ** 07:00 00h Interrupt Line (LINE): The bridge does not generate interrupts, so this is reserved as '00h'. 1492 **============================================================================== 1493 */ 1494 #define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_LINE_REG 0x3C /*byte*/ 1495 #define ARCMSR_PCI2PCI_PRIMARY_INTERRUPT_PIN_REG 0x3D /*byte*/ 1496 /* 1497 **============================================================================== 1498 ** 0x3f-0x3e : 1499 ** Bit Default Description 1500 ** 15:12 0h Reserved 1501 ** 11 0b Discard Timer SERR# Enable: Controls the generation of SERR# on the primary interface (P_SERR#) in response 1502 ** to a timer discard on either the primary or secondary interface. 1503 ** 0b=SERR# is not asserted. 1504 ** 1b=SERR# is asserted. 1505 ** 10 0b Discard Timer Status (DTS): This bit is set to a '1b' when either the primary or secondary discard timer expires. 1506 ** The delayed completion is then discarded. 1507 ** 09 0b Secondary Discard Timer (SDT): Sets the maximum number of PCI clock cycles 1508 ** that bridge waits for an initiator on the secondary bus 1509 ** to repeat a delayed transaction request. 1510 ** The counter starts when the delayed transaction completion is ready 1511 ** to be returned to the initiator. 1512 ** When the initiator has not repeated the transaction 1513 ** at least once before the counter expires,bridge 1514 ** discards the delayed transaction from its queues. 1515 ** 0b=The secondary master time-out counter is 2 15 PCI clock cycles. 1516 ** 1b=The secondary master time-out counter is 2 10 PCI clock cycles. 1517 ** 08 0b Primary Discard Timer (PDT): Sets the maximum number of PCI clock cycles 1518 ** that bridge waits for an initiator on the primary bus 1519 ** to repeat a delayed transaction request. 1520 ** The counter starts when the delayed transaction completion 1521 ** is ready to be returned to the initiator. 1522 ** When the initiator has not repeated the transaction 1523 ** at least once before the counter expires, 1524 ** bridge discards the delayed transaction from its queues. 1525 ** 0b=The primary master time-out counter is 2 15 PCI clock cycles. 1526 ** 1b=The primary master time-out counter is 2 10 PCI clock cycles. 1527 ** 07 0b Fast Back-to-Back Enable (FBE): The bridge does not initiate back to back transactions. 1528 ** 06 0b Secondary Bus Reset (SBR): 1529 ** When cleared to 0b: The bridge deasserts S_RST#, 1530 ** when it had been asserted by writing this bit to a 1b. 1531 ** When set to 1b: The bridge asserts S_RST#. 1532 ** 05 0b Master Abort Mode (MAM): Dictates bridge behavior on the initiator bus 1533 ** when a master abort termination occurs in response to 1534 ** a delayed transaction initiated by bridge on the target bus. 1535 ** 0b=The bridge asserts TRDY# in response to a non-locked delayed transaction, 1536 ** and returns FFFF FFFFh when a read. 1537 ** 1b=When the transaction had not yet been completed on the initiator bus 1538 ** (e.g.,delayed reads, or non-posted writes), 1539 ** then bridge returns a Target Abort in response to the original requester 1540 ** when it returns looking for its delayed completion on the initiator bus. 1541 ** When the transaction had completed on the initiator bus (e.g., a PMW), 1542 ** then bridge asserts P_SERR# (when enabled). 1543 ** For PCI-X transactions this bit is an enable for the assertion of P_SERR# due to a master abort 1544 ** while attempting to deliver a posted memory write on the destination bus. 1545 ** 04 0b VGA Alias Filter Enable: This bit dictates bridge behavior in conjunction with the VGA enable bit 1546 ** (also of this register), 1547 ** and the VGA Palette Snoop Enable bit (Command Register). 1548 ** When the VGA enable, or VGA Palette Snoop enable bits are on (i.e., 1b) 1549 ** the VGA Aliasing bit for the corresponding enabled functionality,: 1550 ** 0b=Ignores address bits AD[15:10] when decoding VGA I/O addresses. 1551 ** 1b=Ensures that address bits AD[15:10] equal 000000b when decoding VGA I/O addresses. 1552 ** When all VGA cycle forwarding is disabled, (i.e., VGA Enable bit =0b and VGA Palette Snoop bit =0b), 1553 ** then this bit has no impact on bridge behavior. 1554 ** 03 0b VGA Enable: Setting this bit enables address decoding 1555 ** and transaction forwarding of the following VGA transactions from the primary bus 1556 ** to the secondary bus: 1557 ** frame buffer memory addresses 000A0000h:000BFFFFh, 1558 ** VGA I/O addresses 3B0:3BBh and 3C0h:3DFh, where AD[31:16]=��0000h?** ?and AD[15:10] are either not decoded (i.e., don't cares), 1559 ** or must be ��000000b�� 1560 ** depending upon the state of the VGA Alias Filter Enable bit. (bit(4) of this register) 1561 ** I/O and Memory Enable bits must be set in the Command register 1562 ** to enable forwarding of VGA cycles. 1563 ** 02 0b ISA Enable: Setting this bit enables special handling 1564 ** for the forwarding of ISA I/O transactions that fall within the address range 1565 ** specified by the I/O Base and Limit registers, 1566 ** and are within the lowest 64Kbyte of the I/O address map 1567 ** (i.e., 0000 0000h - 0000 FFFFh). 1568 ** 0b=All I/O transactions that fall within the I/O Base 1569 ** and Limit registers' specified range are forwarded 1570 ** from primary to secondary unfiltered. 1571 ** 1b=Blocks the forwarding from primary to secondary 1572 ** of the top 768 bytes of each 1Kbyte alias. 1573 ** On the secondary the top 768 bytes of each 1K alias 1574 ** are inversely decoded and forwarded 1575 ** from secondary to primary. 1576 ** 01 0b SERR# Forward Enable: 0b=The bridge does not assert P_SERR# as a result of an S_SERR# assertion. 1577 ** 1b=The bridge asserts P_SERR# whenever S_SERR# is detected 1578 ** asserted provided the SERR# Enable bit is set (PCI Command Register bit(8)=1b). 1579 ** 00 0b Parity Error Response: This bit controls bridge response to a parity error 1580 ** that is detected on its secondary interface. 1581 ** 0b=When a data parity error is detected bridge does not assert S_PERR#. 1582 ** Also bridge does not assert P_SERR# in response to a detected address 1583 ** or attribute parity error. 1584 ** 1b=When a data parity error is detected bridge asserts S_PERR#. 1585 ** The bridge also asserts P_SERR# (when enabled globally via bit(8) 1586 ** of the Command register) 1587 ** in response to a detected address or attribute parity error. 1588 **============================================================================== 1589 */ 1590 #define ARCMSR_PCI2PCI_BRIDGE_CONTROL_REG 0x3E /*word*/ 1591 /* 1592 ************************************************************************** 1593 ** Device Specific Registers 40-A7h 1594 ************************************************************************** 1595 ** ---------------------------------------------------------------------------------------------------------- 1596 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 1597 ** ---------------------------------------------------------------------------------------------------------- 1598 ** | Bridge Control 0 | Arbiter Control/Status | Reserved | 40h 1599 ** ---------------------------------------------------------------------------------------------------------- 1600 ** | Bridge Control 2 | Bridge Control 1 | 44h 1601 ** ---------------------------------------------------------------------------------------------------------- 1602 ** | Reserved | Bridge Status | 48h 1603 ** ---------------------------------------------------------------------------------------------------------- 1604 ** | Reserved | 4Ch 1605 ** ---------------------------------------------------------------------------------------------------------- 1606 ** | Prefetch Policy | Multi-Transaction Timer | 50h 1607 ** ---------------------------------------------------------------------------------------------------------- 1608 ** | Reserved | Pre-boot Status | P_SERR# Assertion Control | 54h 1609 ** ---------------------------------------------------------------------------------------------------------- 1610 ** | Reserved | Reserved | Secondary Decode Enable | 58h 1611 ** ---------------------------------------------------------------------------------------------------------- 1612 ** | Reserved | Secondary IDSEL | 5Ch 1613 ** ---------------------------------------------------------------------------------------------------------- 1614 ** | Reserved | 5Ch 1615 ** ---------------------------------------------------------------------------------------------------------- 1616 ** | Reserved | 68h:CBh 1617 ** ---------------------------------------------------------------------------------------------------------- 1618 ************************************************************************** 1619 **============================================================================== 1620 ** 0x42-0x41: Secondary Arbiter Control/Status Register - SACSR 1621 ** Bit Default Description 1622 ** 15:12 1111b Grant Time-out Violator: This field indicates the agent that violated the Grant Time-out rule 1623 ** (PCI=16 clocks,PCI-X=6 clocks). 1624 ** Note that this field is only meaningful when: 1625 ** # Bit[11] of this register is set to 1b, 1626 ** indicating that a Grant Time-out violation had occurred. 1627 ** # bridge internal arbiter is enabled. 1628 ** Bits[15:12] Violating Agent (REQ#/GNT# pair number) 1629 ** 0000b REQ#/GNT#[0] 1630 ** 0001b REQ#/GNT#[1] 1631 ** 0010b REQ#/GNT#[2] 1632 ** 0011b REQ#/GNT#[3] 1633 ** 1111b Default Value (no violation detected) 1634 ** When bit[11] is cleared by software, this field reverts back to its default value. 1635 ** All other values are Reserved 1636 ** 11 0b Grant Time-out Occurred: When set to 1b, 1637 ** this indicates that a Grant Time-out error had occurred involving one of the secondary bus agents. 1638 ** Software clears this bit by writing a 1b to it. 1639 ** 10 0b Bus Parking Control: 0=During bus idle, bridge parks the bus on the last master to use the bus. 1640 ** 1=During bus idle, bridge parks the bus on itself. 1641 ** The bus grant is removed from the last master and internally asserted to bridge. 1642 ** 09:08 00b Reserved 1643 ** 07:00 0000 0000b Secondary Bus Arbiter Priority Configuration: The bridge secondary arbiter provides two rings of arbitration priority. 1644 ** Each bit of this field assigns its corresponding secondary 1645 ** bus master to either the high priority arbiter ring (1b) 1646 ** or to the low priority arbiter ring (0b). 1647 ** Bits [3:0] correspond to request inputs S_REQ#[3:0], respectively. 1648 ** Bit [6] corresponds to the bridge internal secondary bus request 1649 ** while Bit [7] corresponds to the SATU secondary bus request. 1650 ** Bits [5:4] are unused. 1651 ** 0b=Indicates that the master belongs to the low priority group. 1652 ** 1b=Indicates that the master belongs to the high priority group 1653 **================================================================================= 1654 ** 0x43: Bridge Control Register 0 - BCR0 1655 ** Bit Default Description 1656 ** 07 0b Fully Dynamic Queue Mode: 0=The number of Posted write transactions is limited to eight 1657 ** and the Posted Write data is limited to 4KB. 1658 ** 1=Operation in fully dynamic queue mode. The bridge enqueues up to 1659 ** 14 Posted Memory Write transactions and 8KB of posted write data. 1660 ** 06:03 0H Reserved. 1661 ** 02 0b Upstream Prefetch Disable: This bit disables bridge ability 1662 ** to perform upstream prefetch operations for Memory 1663 ** Read requests received on its secondary interface. 1664 ** This bit also controls the bridge's ability to generate advanced read commands 1665 ** when forwarding a Memory Read Block transaction request upstream from a PCI-X bus 1666 ** to a Conventional PCI bus. 1667 ** 0b=bridge treats all upstream Memory Read requests as though they target prefetchable memory. 1668 ** The use of Memory Read Line and Memory Read 1669 ** Multiple is enabled when forwarding a PCI-X Memory Read Block request 1670 ** to an upstream bus operating in Conventional PCI mode. 1671 ** 1b=bridge treats upstream PCI Memory Read requests as though 1672 ** they target non-prefetchable memory and forwards upstream PCI-X Memory 1673 ** Read Block commands as Memory Read 1674 ** when the primary bus is operating 1675 ** in Conventional PCI mode. 1676 ** NOTE: This bit does not affect bridge ability to perform read prefetching 1677 ** when the received command is Memory Read Line or Memory Read Multiple. 1678 **================================================================================= 1679 ** 0x45-0x44: Bridge Control Register 1 - BCR1 (Sheet 2 of 2) 1680 ** Bit Default Description 1681 ** 15:08 0000000b Reserved 1682 ** 07:06 00b Alias Command Mapping: This two bit field determines how bridge handles PCI-X ��Alias�� commands, 1683 ** specifically the Alias to Memory Read Block and Alias to Memory Write Block commands. 1684 ** The three options for handling these alias commands are to either pass it as is, 1685 ** re-map to the actual block memory read/write command encoding, or ignore 1686 ** the transaction forcing a Master Abort to occur on the Origination Bus. 1687 ** Bit (7:6) Handling of command 1688 ** 0 0 Re-map to Memory Read/Write Block before forwarding 1689 ** 0 1 Enqueue and forward the alias command code unaltered 1690 ** 1 0 Ignore the transaction, forcing Master Abort 1691 ** 1 1 Reserved 1692 ** 05 1b Watchdog Timers Disable: Disables or enables all 2 24 Watchdog Timers in both directions. 1693 ** The watchdog timers are used to detect prohibitively long latencies in the system. 1694 ** The watchdog timer expires when any Posted Memory Write (PMW), Delayed Request, 1695 ** or Split Requests (PCI-X mode) is not completed within 2 24 events 1696 ** (��events�� are defined as PCI Clocks when operating in PCI-X mode, 1697 ** and as the number of times being retried when operating in Conventional PCI mode) 1698 ** 0b=All 2 24 watchdog timers are enabled. 1699 ** 1b=All 2 24 watchdog timers are disabled and there is no limits to 1700 ** the number of attempts bridge makes when initiating a PMW, 1701 ** transacting a Delayed Transaction, or how long it waits for 1702 ** a split completion corresponding to one of its requests. 1703 ** 04 0b GRANT# time-out disable: This bit enables/disables the GNT# time-out mechanism. 1704 ** Grant time-out is 16 clocks for conventional PCI, and 6 clocks for PCI-X. 1705 ** 0b=The Secondary bus arbiter times out an agent 1706 ** that does not assert FRAME# within 16/6 clocks of receiving its grant, 1707 ** once the bus has gone idle. 1708 ** The time-out counter begins as soon as the bus goes idle with the new GNT# asserted. 1709 ** An infringing agent does not receive a subsequent GNT# 1710 ** until it de-asserts its REQ# for at least one clock cycle. 1711 ** 1b=GNT# time-out mechanism is disabled. 1712 ** 03 00b Reserved. 1713 ** 02 0b Secondary Discard Timer Disable: This bit enables/disables bridge secondary delayed transaction discard mechanism. 1714 ** The time out mechanism is used to ensure that initiators 1715 ** of delayed transactions return for their delayed completion data/status 1716 ** within a reasonable amount of time after it is available from bridge. 1717 ** 0b=The secondary master time-out counter is enabled 1718 ** and uses the value specified by the Secondary Discard Timer bit 1719 ** (see Bridge Control Register). 1720 ** 1b=The secondary master time-out counter is disabled. 1721 ** The bridge waits indefinitely for a secondary bus master 1722 ** to repeat a delayed transaction. 1723 ** 01 0b Primary Discard Timer Disable: This bit enables/disables bridge primary delayed transaction discard mechanism. 1724 ** The time out mechanism is used to ensure that initiators 1725 ** of delayed transactions return for their delayed completion data/status 1726 ** within a reasonable amount of time after it is available from bridge. 1727 ** 0b=The primary master time-out counter is enabled and uses the value specified 1728 ** by the Primary Discard Timer bit (see Bridge Control Register). 1729 ** 1b=The secondary master time-out counter is disabled. 1730 ** The bridge waits indefinitely for a secondary bus master 1731 ** to repeat a delayed transaction. 1732 ** 00 0b Reserved 1733 **================================================================================= 1734 ** 0x47-0x46: Bridge Control Register 2 - BCR2 1735 ** Bit Default Description 1736 ** 15:07 0000b Reserved. 1737 ** 06 0b Global Clock Out Disable (External Secondary Bus Clock Source Enable): 1738 ** This bit disables all of the secondary PCI clock outputs including 1739 ** the feedback clock S_CLKOUT. 1740 ** This means that the user is required to provide an S_CLKIN input source. 1741 ** 05:04 11 (66 MHz) Preserved. 1742 ** 01 (100 MHz) 1743 ** 00 (133 MHz) 1744 ** 03:00 Fh (100 MHz & 66 MHz) 1745 ** 7h (133 MHz) 1746 ** This 4 bit field provides individual enable/disable mask bits for each of bridge 1747 ** secondary PCI clock outputs. Some, or all secondary clock outputs (S_CLKO[3:0]) 1748 ** default to being enabled following the rising edge of P_RST#, depending on the 1749 ** frequency of the secondary bus clock: 1750 ** �E Designs with 100 MHz (or lower) Secondary PCI clock power up with 1751 ** all four S_CLKOs enabled by default. (SCLKO[3:0])�P 1752 ** �E Designs with 133 MHz Secondary PCI clock power up 1753 ** with the lower order 3 S_CLKOs enabled by default. 1754 ** (S_CLKO[2:0]) Only those SCLKs that power up enabled by can be connected 1755 ** to downstream device clock inputs. 1756 **================================================================================= 1757 ** 0x49-0x48: Bridge Status Register - BSR 1758 ** Bit Default Description 1759 ** 15 0b Upstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR# 1760 ** is conditionally asserted when the secondary discard timer expires. 1761 ** 14 0b Upstream Delayed/Split Read Watchdog Timer Expired: 1762 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# 1763 ** is conditionally asserted when bridge discards an upstream delayed read ** ** transaction request after 2 24 retries following the initial retry. 1764 ** PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 1765 ** when bridge discards an upstream split read request 1766 ** after waiting in excess of 2 24 clocks for the corresponding 1767 ** Split Completion to arrive. 1768 ** 13 0b Upstream Delayed/Split Write Watchdog Timer Expired: 1769 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# 1770 ** is conditionally asserted when bridge discards an upstream delayed write ** ** transaction request after 2 24 retries following the initial retry. 1771 ** PCI-X Mode: This bit is set to a 1b and P_SERR# 1772 ** is conditionally asserted when bridge discards an upstream split write request ** after waiting in excess of 2 24 clocks for the corresponding 1773 ** Split Completion to arrive. 1774 ** 12 0b Master Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR# 1775 ** is conditionally asserted when a Master Abort occurs as a result of an attempt, 1776 ** by bridge, to retire a PMW upstream. 1777 ** 11 0b Target Abort during Upstream Posted Write: This bit is set to a 1b and P_SERR# 1778 ** is conditionally asserted when a Target Abort occurs as a result of an attempt, 1779 ** by bridge, to retire a PMW upstream. 1780 ** 10 0b Upstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR# 1781 ** is conditionally asserted when bridge discards an upstream PMW transaction 1782 ** after receiving 2 24 target retries from the primary bus target 1783 ** 09 0b Upstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR# 1784 ** is conditionally asserted when a data parity error is detected by bridge 1785 ** while attempting to retire a PMW upstream 1786 ** 08 0b Secondary Bus Address Parity Error: This bit is set to a 1b and P_SERR# 1787 ** is conditionally asserted when bridge detects an address parity error on 1788 ** the secondary bus. 1789 ** 07 0b Downstream Delayed Transaction Discard Timer Expired: This bit is set to a 1b and P_SERR# 1790 ** is conditionally asserted when the primary bus discard timer expires. 1791 ** 06 0b Downstream Delayed/Split Read Watchdog Timer Expired: 1792 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# 1793 ** is conditionally asserted when bridge discards a downstream delayed read ** ** transaction request after receiving 2 24 target retries 1794 ** from the secondary bus target. 1795 ** PCI-X Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 1796 ** when bridge discards a downstream split read request 1797 ** after waiting in excess of 2 24 clocks for the corresponding 1798 ** Split Completion to arrive. 1799 ** 05 0b Downstream Delayed Write/Split Watchdog Timer Expired: 1800 ** Conventional PCI Mode: This bit is set to a 1b and P_SERR# is conditionally asserted 1801 ** when bridge discards a downstream delayed write transaction request 1802 ** after receiving 2 24 target retries from the secondary bus target. 1803 ** PCI-X Mode: This bit is set to a 1b and P_SERR# 1804 ** is conditionally asserted when bridge discards a downstream 1805 ** split write request after waiting in excess of 2 24 clocks 1806 ** for the corresponding Split Completion to arrive. 1807 ** 04 0b Master Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR# 1808 ** is conditionally asserted when a Master Abort occurs as a result of an attempt, 1809 ** by bridge, to retire a PMW downstream. 1810 ** 03 0b Target Abort during Downstream Posted Write: This bit is set to a 1b and P_SERR# is conditionally asserted 1811 ** when a Target Abort occurs as a result of an attempt, by bridge, 1812 ** to retire a PMW downstream. 1813 ** 02 0b Downstream Posted Write Data Discarded: This bit is set to a 1b and P_SERR# 1814 ** is conditionally asserted when bridge discards a downstream PMW transaction 1815 ** after receiving 2 24 target retries from the secondary bus target 1816 ** 01 0b Downstream Posted Write Data Parity Error: This bit is set to a 1b and P_SERR# 1817 ** is conditionally asserted when a data parity error is detected by bridge 1818 ** while attempting to retire a PMW downstream. 1819 ** 00 0b Primary Bus Address Parity Error: This bit is set to a 1b and P_SERR# is conditionally asserted 1820 ** when bridge detects an address parity error on the primary bus. 1821 **================================================================================== 1822 ** 0x51-0x50: Bridge Multi-Transaction Timer Register - BMTTR 1823 ** Bit Default Description 1824 ** 15:13 000b Reserved 1825 ** 12:10 000b GRANT# Duration: This field specifies the count (PCI clocks) 1826 ** that a secondary bus master has its grant maintained in order to enable 1827 ** multiple transactions to execute within the same arbitration cycle. 1828 ** Bit[02:00] GNT# Extended Duration 1829 ** 000 MTT Disabled (Default=no GNT# extension) 1830 ** 001 16 clocks 1831 ** 010 32 clocks 1832 ** 011 64 clocks 1833 ** 100 128 clocks 1834 ** 101 256 clocks 1835 ** 110 Invalid (treated as 000) 1836 ** 111 Invalid (treated as 000) 1837 ** 09:08 00b Reserved 1838 ** 07:00 FFh MTT Mask: This field enables/disables MTT usage for each REQ#/GNT# 1839 ** pair supported by bridge secondary arbiter. 1840 ** Bit(7) corresponds to SATU internal REQ#/GNT# pair, 1841 ** bit(6) corresponds to bridge internal REQ#/GNT# pair, 1842 ** bit(5) corresponds to REQ#/GNT#(5) pair, etc. 1843 ** When a given bit is set to 1b, its corresponding REQ#/GNT# 1844 ** pair is enabled for MTT functionality as determined by bits(12:10) of this register. 1845 ** When a given bit is cleared to 0b, its corresponding REQ#/GNT# pair is disabled from using the MTT. 1846 **================================================================================== 1847 ** 0x53-0x52: Read Prefetch Policy Register - RPPR 1848 ** Bit Default Description 1849 ** 15:13 000b ReRead_Primary Bus: 3-bit field indicating the multiplication factor 1850 ** to be used in calculating the number of bytes to prefetch from the secondary bus interface on ** subsequent PreFetch operations given that the read demands were not satisfied 1851 ** using the FirstRead parameter. 1852 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs 1853 ** Memory Read Line 1 cache lines Memory Read Multiple 2 cache lines 1854 ** 12:10 000b FirstRead_Primary Bus: 3-bit field indicating the multiplication factor to be used in calculating 1855 ** the number of bytes to prefetch from the secondary bus interface 1856 ** on the initial PreFetch operation. 1857 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount Memory Read 4 DWORDs 1858 ** Memory Read Line 1 cache line Memory Read Multiple 2 cache lines 1859 ** 09:07 010b ReRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used 1860 ** in calculating the number of bytes to prefetch from the primary 1861 ** bus interface on subsequent PreFetch operations given 1862 ** that the read demands were not satisfied using 1863 ** the FirstRead parameter. 1864 ** The default value of 010b correlates to: Command Type Hardwired pre-fetch a 1865 ** mount Memory Read 3 cache lines Memory Read Line 3 cache lines 1866 ** Memory Read Multiple 6 cache lines 1867 ** 06:04 000b FirstRead_Secondary Bus: 3-bit field indicating the multiplication factor to be used 1868 ** in calculating the number of bytes to prefetch from 1869 ** the primary bus interface on the initial PreFetch operation. 1870 ** The default value of 000b correlates to: Command Type Hardwired pre-fetch amount 1871 ** Memory Read 4 DWORDs Memory Read Line 1 cache line Memory Read Multiple 2 cache lines 1872 ** 03:00 1111b Staged Prefetch Enable: This field enables/disables the FirstRead/ReRead pre-fetch 1873 ** algorithm for the secondary and the primary bus interfaces. 1874 ** Bit(3) is a ganged enable bit for REQ#/GNT#[7:3], and bits(2:0) provide individual 1875 ** enable bits for REQ#/GNT#[2:0]. 1876 ** (bit(2) is the enable bit for REQ#/GNT#[2], etc...) 1877 ** 1b: enables the staged pre-fetch feature 1878 ** 0b: disables staged pre-fetch, 1879 ** and hardwires read pre-fetch policy to the following for 1880 ** Memory Read, 1881 ** Memory Read Line, 1882 ** and Memory Read Multiple commands: 1883 ** Command Type Hardwired Pre-Fetch Amount... 1884 ** Memory Read 4 DWORDs 1885 ** Memory Read Line 1 cache line 1886 ** Memory Read Multiple 2 cache lines 1887 ** NOTE: When the starting address is not cache line aligned, bridge pre-fetches Memory Read line commands 1888 ** only to the next higher cache line boundary.For non-cache line aligned Memory Read 1889 ** Multiple commands bridge pre-fetches only to the second cache line boundary encountered. 1890 **================================================================================== 1891 ** 0x55-0x54: P_SERR# Assertion Control - SERR_CTL 1892 ** Bit Default Description 1893 ** 15 0b Upstream Delayed Transaction Discard Timer Expired: Dictates the bridge behavior 1894 ** in response to its discarding of a delayed transaction that was initiated from the primary bus. 1895 ** 0b=bridge asserts P_SERR#. 1896 ** 1b=bridge does not assert P_SERR# 1897 ** 14 0b Upstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 1898 ** 0b=bridge asserts P_SERR#. 1899 ** 1b=bridge does not assert P_SERR# 1900 ** 13 0b Upstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 1901 ** 0b=bridge asserts P_SERR#. 1902 ** 1b=bridge does not assert P_SERR# 1903 ** 12 0b Master Abort during Upstream Posted Write: Dictates bridge behavior following 1904 ** its having detected a Master Abort while attempting to retire one of its PMWs upstream. 1905 ** 0b=bridge asserts P_SERR#. 1906 ** 1b=bridge does not assert P_SERR# 1907 ** 11 0b Target Abort during Upstream Posted Write: Dictates bridge behavior following 1908 ** its having been terminated with Target Abort while attempting to retire one of its PMWs upstream. 1909 ** 0b=bridge asserts P_SERR#. 1910 ** 1b=bridge does not assert P_SERR# 1911 ** 10 0b Upstream Posted Write Data Discarded: Dictates bridge behavior in the event that 1912 ** it discards an upstream posted write transaction. 1913 ** 0b=bridge asserts P_SERR#. 1914 ** 1b=bridge does not assert P_SERR# 1915 ** 09 0b Upstream Posted Write Data Parity Error: Dictates bridge behavior 1916 ** when a data parity error is detected while attempting to retire on of its PMWs upstream. 1917 ** 0b=bridge asserts P_SERR#. 1918 ** 1b=bridge does not assert P_SERR# 1919 ** 08 0b Secondary Bus Address Parity Error: This bit dictates bridge behavior 1920 ** when it detects an address parity error on the secondary bus. 1921 ** 0b=bridge asserts P_SERR#. 1922 ** 1b=bridge does not assert P_SERR# 1923 ** 07 0b Downstream Delayed Transaction Discard Timer Expired: Dictates bridge behavior in response to 1924 ** its discarding of a delayed transaction that was initiated on the secondary bus. 1925 ** 0b=bridge asserts P_SERR#. 1926 ** 1b=bridge does not assert P_SERR# 1927 ** 06 0b Downstream Delayed/Split Read Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 1928 ** 0b=bridge asserts P_SERR#. 1929 ** 1b=bridge does not assert P_SERR# 1930 ** 05 0b Downstream Delayed/Split Write Watchdog Timer Expired: Dictates bridge behavior following expiration of the subject watchdog timer. 1931 ** 0b=bridge asserts P_SERR#. 1932 ** 1b=bridge does not assert P_SERR# 1933 ** 04 0b Master Abort during Downstream Posted Write: Dictates bridge behavior following 1934 ** its having detected a Master Abort while attempting to retire one of its PMWs downstream. 1935 ** 0b=bridge asserts P_SERR#. 1936 ** 1b=bridge does not assert P_SERR# 1937 ** 03 0b Target Abort during Downstream Posted Write: Dictates bridge behavior following 1938 ** its having been terminated with Target Abort while attempting to retire one of its PMWs downstream. 1939 ** 0b=bridge asserts P_SERR#. 1940 ** 1b=bridge does not assert P_SERR# 1941 ** 02 0b Downstream Posted Write Data Discarded: Dictates bridge behavior in the event 1942 ** that it discards a downstream posted write transaction. 1943 ** 0b=bridge asserts P_SERR#. 1944 ** 1b=bridge does not assert P_SERR# 1945 ** 01 0b Downstream Posted Write Data Parity Error: Dictates bridge behavior 1946 ** when a data parity error is detected while attempting to retire on of its PMWs downstream. 1947 ** 0b=bridge asserts P_SERR#. 1948 ** 1b=bridge does not assert P_SERR# 1949 ** 00 0b Primary Bus Address Parity Error: This bit dictates bridge behavior 1950 ** when it detects an address parity error on the primary bus. 1951 ** 0b=bridge asserts P_SERR#. 1952 ** 1b=bridge does not assert P_SERR# 1953 **=============================================================================== 1954 ** 0x56: Pre-Boot Status Register - PBSR 1955 ** Bit Default Description 1956 ** 07 1 Reserved 1957 ** 06 - Reserved - value indeterminate 1958 ** 05:02 0 Reserved 1959 ** 01 Varies with External State of S_133EN at PCI Bus Reset Secondary Bus Max Frequency Setting: 1960 ** This bit reflect captured S_133EN strap, 1961 ** indicating the maximum secondary bus clock frequency when in PCI-X mode. 1962 ** Max Allowable Secondary Bus Frequency 1963 ** ** S_133EN PCI-X Mode 1964 ** ** 0 100 MHz 1965 ** ** 1 133 MH 1966 ** 00 0b Reserved 1967 **=============================================================================== 1968 ** 0x59-0x58: Secondary Decode Enable Register - SDER 1969 ** Bit Default Description 1970 ** 15:03 FFF1h Preserved. 1971 ** 02 Varies with External State of PRIVMEM at PCI Bus Reset Private Memory Space Enable - when set, 1972 ** bridge overrides its secondary inverse decode logic and not 1973 ** forward upstream any secondary bus initiated DAC Memory transactions with AD(63)=1b. 1974 ** This creates a private memory space on the Secondary PCI bus 1975 ** that allows peer-to-peer transactions. 1976 ** 01:00 10 2 Preserved. 1977 **=============================================================================== 1978 ** 0x5D-0x5C: Secondary IDSEL Select Register - SISR 1979 ** Bit Default Description 1980 ** 15:10 000000 2 Reserved. 1981 ** 09 Varies with External State of PRIVDEV at PCI Bus Reset AD25- IDSEL Disable - When this bit is set, 1982 ** AD25 is deasserted for any possible Type 1 to Type 0 conversion. 1983 ** When this bit is clear, 1984 ** AD25 is asserted when Primary addresses AD[15:11]=01001 2 during a Type 1 to Type 0 conversion. 1985 ** 08 Varies with External State of PRIVDEV at PCI Bus Reset AD24- IDSEL Disable - When this bit is set, 1986 ** AD24 is deasserted for any possible Type 1 to Type 0 conversion. 1987 ** When this bit is clear, 1988 ** AD24 is asserted when Primary addresses AD[15:11]=01000 2 during a Type 1 to Type 0 conversion. 1989 ** 07 Varies with External State of PRIVDEV at PCI Bus Reset AD23- IDSEL Disable - When this bit is set, 1990 ** AD23 is deasserted for any possible Type 1 to Type 0 conversion. 1991 ** When this bit is clear, 1992 ** AD23 is asserted when Primary addresses AD[15:11]=00111 2 during a Type 1 to Type 0 conversion. 1993 ** 06 Varies with External State of PRIVDEV at PCI Bus Reset AD22- IDSEL Disable - When this bit is set, 1994 ** AD22 is deasserted for any possible Type 1 to Type 0 conversion. 1995 ** When this bit is clear, 1996 ** AD22 is asserted when Primary addresses AD[15:11]=00110 2 during a Type 1 to Type 0 conversion. 1997 ** 05 Varies with External State of PRIVDEV at PCI Bus Reset AD21- IDSEL Disable - When this bit is set, 1998 ** AD21 is deasserted for any possible Type 1 to Type 0 conversion. 1999 ** When this bit is clear, 2000 ** AD21 is asserted when Primary addresses AD[15:11]=00101 2 during a Type 1 to Type 0 conversion. 2001 ** 04 Varies with External State of PRIVDEV at PCI Bus Reset AD20- IDSEL Disable - When this bit is set, 2002 ** AD20 is deasserted for any possible Type 1 to Type 0 conversion. 2003 ** When this bit is clear, 2004 ** AD20 is asserted when Primary addresses AD[15:11]=00100 2 during a Type 1 to Type 0 conversion. 2005 ** 03 Varies with External State of PRIVDEV at PCI Bus Reset AD19- IDSEL Disable - When this bit is set, 2006 ** AD19 is deasserted for any possible Type 1 to Type 0 conversion. 2007 ** When this bit is clear, 2008 ** AD19 is asserted when Primary addresses AD[15:11]=00011 2 during a Type 1 to Type 0 conversion. 2009 ** 02 Varies with External State of PRIVDEV at PCI Bus Reset AD18- IDSEL Disable - When this bit is set, 2010 ** AD18 is deasserted for any possible Type 1 to Type 0 conversion. 2011 ** When this bit is clear, 2012 ** AD18 is asserted when Primary addresses AD[15:11]=00010 2 during a Type 1 to Type 0 conversion. 2013 ** 01 Varies with External State of PRIVDEV at PCI Bus Reset AD17- IDSEL Disable - When this bit is set, 2014 ** AD17 is deasserted for any possible Type 1 to Type 0 conversion. 2015 ** When this bit is clear, 2016 ** AD17 is asserted when Primary addresses AD[15:11]=00001 2 during a Type 1 to Type 0 conversion. 2017 ** 00 Varies with External State of PRIVDEV at PCI Bus Reset AD16- IDSEL Disable - When this bit is set, 2018 ** AD16 is deasserted for any possible Type 1 to Type 0 conversion. 2019 ** When this bit is clear, 2020 ** AD16 is asserted when Primary addresses AD[15:11]=00000 2 during a Type 1 to Type 0 conversion. 2021 ************************************************************************** 2022 */ 2023 /* 2024 ************************************************************************** 2025 ** Reserved A8-CBh 2026 ************************************************************************** 2027 */ 2028 /* 2029 ************************************************************************** 2030 ** PCI Extended Enhanced Capabilities List CC-FFh 2031 ************************************************************************** 2032 ** ---------------------------------------------------------------------------------------------------------- 2033 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configu-ration Byte Offset 2034 ** ---------------------------------------------------------------------------------------------------------- 2035 ** | Power Management Capabilities | Next Item Ptr | Capability ID | DCh 2036 ** ---------------------------------------------------------------------------------------------------------- 2037 ** | PM Data | PPB Support | Extensions Power Management CSR | E0h 2038 ** ---------------------------------------------------------------------------------------------------------- 2039 ** | Reserved | Reserved | Reserved | E4h 2040 ** ---------------------------------------------------------------------------------------------------------- 2041 ** | Reserved | E8h 2042 ** ---------------------------------------------------------------------------------------------------------- 2043 ** | Reserved | Reserved | Reserved | Reserved | ECh 2044 ** ---------------------------------------------------------------------------------------------------------- 2045 ** | PCI-X Secondary Status | Next Item Ptr | Capability ID | F0h 2046 ** ---------------------------------------------------------------------------------------------------------- 2047 ** | PCI-X Bridge Status | F4h 2048 ** ---------------------------------------------------------------------------------------------------------- 2049 ** | PCI-X Upstream Split Transaction Control | F8h 2050 ** ---------------------------------------------------------------------------------------------------------- 2051 ** | PCI-X Downstream Split Transaction Control | FCh 2052 ** ---------------------------------------------------------------------------------------------------------- 2053 **=============================================================================== 2054 ** 0xDC: Power Management Capabilities Identifier - PM_CAPID 2055 ** Bit Default Description 2056 ** 07:00 01h Identifier (ID): PCI SIG assigned ID for PCI-PM register block 2057 **=============================================================================== 2058 ** 0xDD: Next Item Pointer - PM_NXTP 2059 ** Bit Default Description 2060 ** 07:00 F0H Next Capabilities Pointer (PTR): The register defaults to F0H pointing to the PCI-X Extended Capability Header. 2061 **=============================================================================== 2062 ** 0xDF-0xDE: Power Management Capabilities Register - PMCR 2063 ** Bit Default Description 2064 ** 15:11 00h PME Supported (PME): PME# cannot be asserted by bridge. 2065 ** 10 0h State D2 Supported (D2): Indicates no support for state D2. No power management action in this state. 2066 ** 09 1h State D1 Supported (D1): Indicates support for state D1. No power management action in this state. 2067 ** 08:06 0h Auxiliary Current (AUXC): This 3 bit field reports the 3.3Vaux auxiliary current requirements for the PCI function. 2068 ** This returns 000b as PME# wake-up for bridge is not implemented. 2069 ** 05 0 Special Initialization Required (SINT): Special initialization is not required for bridge. 2070 ** 04:03 00 Reserved 2071 ** 02:00 010 Version (VS): Indicates that this supports PCI Bus Power Management Interface Specification, Revision 1.1. 2072 **=============================================================================== 2073 ** 0xE1-0xE0: Power Management Control / Status - Register - PMCSR 2074 ** Bit Default Description 2075 ** 15:09 00h Reserved 2076 ** 08 0b PME_Enable: This bit, when set to 1b enables bridge to assert PME#. 2077 ** Note that bridge never has occasion to assert PME# and implements this dummy R/W bit only for the purpose of working around an OS PCI-PM bug. 2078 ** 07:02 00h Reserved 2079 ** 01:00 00 Power State (PSTATE): This 2-bit field is used both to determine the current power state of 2080 ** a function and to set the Function into a new power state. 2081 ** 00 - D0 state 2082 ** 01 - D1 state 2083 ** 10 - D2 state 2084 ** 11 - D3 hot state 2085 **=============================================================================== 2086 ** 0xE2: Power Management Control / Status PCI to PCI Bridge Support - PMCSR_BSE 2087 ** Bit Default Description 2088 ** 07 0 Bus Power/Clock Control Enable (BPCC_En): Indicates that the bus power/clock control policies have been disabled. 2089 ** 06 0 B2/B3 support for D3 Hot (B2_B3#): The state of this bit determines the action that 2090 ** is to occur as a direct result of programming the function to D3 hot. 2091 ** This bit is only meaningful when bit 7 (BPCC_En) is a ��1��. 2092 ** 05:00 00h Reserved 2093 **=============================================================================== 2094 ** 0xE3: Power Management Data Register - PMDR 2095 ** Bit Default Description 2096 ** 07:00 00h Reserved 2097 **=============================================================================== 2098 ** 0xF0: PCI-X Capabilities Identifier - PX_CAPID 2099 ** Bit Default Description 2100 ** 07:00 07h Identifier (ID): Indicates this is a PCI-X capabilities list. 2101 **=============================================================================== 2102 ** 0xF1: Next Item Pointer - PX_NXTP 2103 ** Bit Default Description 2104 ** 07:00 00h Next Item Pointer: Points to the next capability in the linked list The power on default value of this 2105 ** register is 00h indicating that this is the last entry in the linked list of capabilities. 2106 **=============================================================================== 2107 ** 0xF3-0xF2: PCI-X Secondary Status - PX_SSTS 2108 ** Bit Default Description 2109 ** 15:09 00h Reserved 2110 ** 08:06 Xxx Secondary Clock Frequency (SCF): This field is set with the frequency of the secondary bus. 2111 ** The values are: 2112 ** ** BitsMax FrequencyClock Period 2113 ** ** 000PCI ModeN/A 2114 ** ** 00166 15 2115 ** ** 01010010 2116 ** ** 0111337.5 2117 ** ** 1xxreservedreserved 2118 ** ** The default value for this register is the operating frequency of the secondary bus 2119 ** 05 0b Split Request Delayed. (SRD): This bit is supposed to be set by a bridge when it cannot forward a transaction on the 2120 ** secondary bus to the primary bus because there is not enough room within the limit 2121 ** specified in the Split Transaction Commitment Limit field in the Downstream Split 2122 ** Transaction Control register. The bridge does not set this bit. 2123 ** 04 0b Split Completion Overrun (SCO): This bit is supposed to be set when a bridge terminates a Split Completion on the ** ** secondary bus with retry or Disconnect at next ADB because its buffers are full. 2124 ** The bridge does not set this bit. 2125 ** 03 0b Unexpected Split Completion (USC): This bit is set when an unexpected split completion with a requester ID 2126 ** equal to bridge secondary bus number, device number 00h, 2127 ** and function number 0 is received on the secondary interface. 2128 ** This bit is cleared by software writing a '1'. 2129 ** 02 0b Split Completion Discarded (SCD): This bit is set 2130 ** when bridge discards a split completion moving toward the secondary bus 2131 ** because the requester would not accept it. This bit cleared by software writing a '1'. 2132 ** 01 1b 133 MHz Capable: Indicates that bridge is capable of running its secondary bus at 133 MHz 2133 ** 00 1b 64-bit Device (D64): Indicates the width of the secondary bus as 64-bits. 2134 **=============================================================================== 2135 ** 0xF7-0xF6-0xf5-0xF4: PCI-X Bridge Status - PX_BSTS 2136 ** Bit Default Description 2137 ** 31:22 0 Reserved 2138 ** 21 0 Split Request Delayed (SRD): This bit does not be set by bridge. 2139 ** 20 0 Split Completion Overrun (SCO): This bit does not be set by bridge 2140 ** because bridge throttles traffic on the completion side. 2141 ** 19 0 Unexpected Split Completion (USC): The bridge sets this bit to 1b 2142 ** when it encounters a corrupted Split Completion, possibly with an ** ** inconsistent remaining byte count.Software clears 2143 ** this bit by writing a 1b to it. 2144 ** 18 0 Split Completion Discarded (SCD): The bridge sets this bit to 1b 2145 ** when it has discarded a Split Completion.Software clears this bit by ** ** writing a 1b to it. 2146 ** 17 1 133 MHz Capable: This bit indicates that the bridge primary interface is ** capable of 133 MHz operation in PCI-X mode. 2147 ** 0=The maximum operating frequency is 66 MHz. 2148 ** 1=The maximum operating frequency is 133 MHz. 2149 ** 16 Varies with the external state of P_32BITPCI# at PCI Bus Reset 64-bit Device (D64): Indicates bus width of the Primary PCI bus interface. 2150 ** 0=Primary Interface is connected as a 32-bit PCI bus. 2151 ** 1=Primary Interface is connected as a 64-bit PCI bus. 2152 ** 15:08 00h Bus Number (BNUM): This field is simply an alias to the PBN field 2153 ** of the BNUM register at offset 18h. 2154 ** Apparently it was deemed necessary reflect it here for diagnostic purposes. 2155 ** 07:03 1fh Device Number (DNUM): Indicates which IDSEL bridge consumes. 2156 ** May be updated whenever a PCI-X 2157 ** configuration write cycle that targets bridge scores a hit. 2158 ** 02:00 0h Function Number (FNUM): The bridge Function # 2159 **=============================================================================== 2160 ** 0xFB-0xFA-0xF9-0xF8: PCI-X Upstream Split Transaction Control - PX_USTC 2161 ** Bit Default Description 2162 ** 31:16 003Eh Split Transaction Limit (STL): This register indicates the size of the commitment limit in units of ADQs. 2163 ** Software is permitted to program this register to any value greater than or equal to 2164 ** the contents of the Split Transaction Capacity register. A value less than the contents 2165 ** of the Split Transaction Capacity register causes unspecified results. 2166 ** A value of 003Eh or greater enables the bridge to forward all Split Requests of any 2167 ** size regardless of the amount of buffer space available. 2168 ** 15:00 003Eh Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing 2169 ** split completions. This register controls behavior of the bridge buffers for forwarding 2170 ** Split Transactions from a primary bus requester to a secondary bus completer. 2171 ** The default value of 003Eh indicates there is available buffer space for 62 ADQs (7936 bytes). 2172 **=============================================================================== 2173 ** 0xFF-0xFE-0xFD-0xFC: PCI-X Downstream Split Transaction Control - PX_DSTC 2174 ** Bit Default Description 2175 ** 31:16 003Eh Split Transaction Limit (STL): This register indicates the size of the commitment limit in units of ADQs. 2176 ** Software is permitted to program this register to any value greater than or equal to 2177 ** the contents of the Split Transaction Capacity register. A value less than the contents 2178 ** of the Split Transaction Capacity register causes unspecified results. 2179 ** A value of 003Eh or greater enables the bridge to forward all Split Requests of any 2180 ** size regardless of the amount of buffer space available. 2181 ** 15:00 003Eh Split Transaction Capacity (STC): This read-only field indicates the size of the buffer (number of ADQs) for storing 2182 ** split completions. This register controls behavior of the bridge buffers for forwarding 2183 ** Split Transactions from a primary bus requester to a secondary bus completer. 2184 ** The default value of 003Eh indicates there is available buffer space for 62 ADQs 2185 ** (7936 bytes). 2186 ************************************************************************** 2187 */ 2188 2189 2190 2191 2192 /* 2193 ************************************************************************************************************************************* 2194 ** 80331 Address Translation Unit Register Definitions 2195 ** ATU Interface Configuration Header Format 2196 ** The ATU is programmed via a [Type 0] configuration command on the PCI interface. 2197 ************************************************************************************************************************************* 2198 ** | Byte 3 | Byte 2 | Byte 1 | Byte 0 | Configuration Byte Offset 2199 **=================================================================================================================================== 2200 ** | ATU Device ID | Vendor ID | 00h 2201 ** ---------------------------------------------------------------------------------------------------------- 2202 ** | Status | Command | 04H 2203 ** ---------------------------------------------------------------------------------------------------------- 2204 ** | ATU Class Code | Revision ID | 08H 2205 ** ---------------------------------------------------------------------------------------------------------- 2206 ** | ATUBISTR | Header Type | Latency Timer | Cacheline Size | 0CH 2207 ** ---------------------------------------------------------------------------------------------------------- 2208 ** | Inbound ATU Base Address 0 | 10H 2209 ** ---------------------------------------------------------------------------------------------------------- 2210 ** | Inbound ATU Upper Base Address 0 | 14H 2211 ** ---------------------------------------------------------------------------------------------------------- 2212 ** | Inbound ATU Base Address 1 | 18H 2213 ** ---------------------------------------------------------------------------------------------------------- 2214 ** | Inbound ATU Upper Base Address 1 | 1CH 2215 ** ---------------------------------------------------------------------------------------------------------- 2216 ** | Inbound ATU Base Address 2 | 20H 2217 ** ---------------------------------------------------------------------------------------------------------- 2218 ** | Inbound ATU Upper Base Address 2 | 24H 2219 ** ---------------------------------------------------------------------------------------------------------- 2220 ** | Reserved | 28H 2221 ** ---------------------------------------------------------------------------------------------------------- 2222 ** | ATU Subsystem ID | ATU Subsystem Vendor ID | 2CH 2223 ** ---------------------------------------------------------------------------------------------------------- 2224 ** | Expansion ROM Base Address | 30H 2225 ** ---------------------------------------------------------------------------------------------------------- 2226 ** | Reserved Capabilities Pointer | 34H 2227 ** ---------------------------------------------------------------------------------------------------------- 2228 ** | Reserved | 38H 2229 ** ---------------------------------------------------------------------------------------------------------- 2230 ** | Maximum Latency | Minimum Grant | Interrupt Pin | Interrupt Line | 3CH 2231 ** ---------------------------------------------------------------------------------------------------------- 2232 ********************************************************************************************************************* 2233 */ 2234 /* 2235 *********************************************************************************** 2236 ** ATU Vendor ID Register - ATUVID 2237 ** ----------------------------------------------------------------- 2238 ** Bit Default Description 2239 ** 15:00 8086H (0x17D3) ATU Vendor ID - This is a 16-bit value assigned to Intel. 2240 ** This register, combined with the DID, uniquely identify the PCI device. 2241 ** Access type is Read/Write to allow the 80331 to configure the register as a different vendor ID 2242 ** to simulate the interface of a standard mechanism currently used by existing application software. 2243 *********************************************************************************** 2244 */ 2245 #define ARCMSR_ATU_VENDOR_ID_REG 0x00 /*word*/ 2246 /* 2247 *********************************************************************************** 2248 ** ATU Device ID Register - ATUDID 2249 ** ----------------------------------------------------------------- 2250 ** Bit Default Description 2251 ** 15:00 0336H (0x1110) ATU Device ID - This is a 16-bit value assigned to the ATU. 2252 ** This ID, combined with the VID, uniquely identify any PCI device. 2253 *********************************************************************************** 2254 */ 2255 #define ARCMSR_ATU_DEVICE_ID_REG 0x02 /*word*/ 2256 /* 2257 *********************************************************************************** 2258 ** ATU Command Register - ATUCMD 2259 ** ----------------------------------------------------------------- 2260 ** Bit Default Description 2261 ** 15:11 000000 2 Reserved 2262 ** 10 0 Interrupt Disable - This bit disables 80331 from asserting the ATU interrupt signal. 2263 ** 0=enables the assertion of interrupt signal. 2264 ** 1=disables the assertion of its interrupt signal. 2265 ** 09 0 2 Fast Back to Back Enable - When cleared, 2266 ** the ATU interface is not allowed to generate fast back-to-back cycles on its bus. 2267 ** Ignored when operating in the PCI-X mode. 2268 ** 08 0 2 SERR# Enable - When cleared, the ATU interface is not allowed to assert SERR# on the PCI interface. 2269 ** 07 1 2 Address/Data Stepping Control - Address stepping is implemented for configuration transactions. The 2270 ** ATU inserts 2 clock cycles of address stepping for Conventional Mode and 4 clock cycles 2271 ** of address stepping for PCI-X mode. 2272 ** 06 0 2 Parity Error Response - When set, the ATU takes normal action when a parity error 2273 ** is detected. When cleared, parity checking is disabled. 2274 ** 05 0 2 VGA Palette Snoop Enable - The ATU interface does not support I/O writes and therefore, 2275 ** does not perform VGA palette snooping. 2276 ** 04 0 2 Memory Write and Invalidate Enable - When set, ATU may generate MWI commands. 2277 ** When clear, ATU use Memory Write commands instead of MWI. Ignored when operating in the PCI-X mode. 2278 ** 03 0 2 Special Cycle Enable - The ATU interface does not respond to special cycle commands in any way. 2279 ** Not implemented and a reserved bit field. 2280 ** 02 0 2 Bus Master Enable - The ATU interface can act as a master on the PCI bus. 2281 ** When cleared, disables the device from generating PCI accesses. 2282 ** When set, allows the device to behave as a PCI bus master. 2283 ** When operating in the PCI-X mode, ATU initiates a split completion transaction regardless 2284 ** of the state of this bit. 2285 ** 01 0 2 Memory Enable - Controls the ATU interface��s response to PCI memory addresses. 2286 ** When cleared, the ATU interface does not respond to any memory access on the PCI bus. 2287 ** 00 0 2 I/O Space Enable - Controls the ATU interface response to I/O transactions. 2288 ** Not implemented and a reserved bit field. 2289 *********************************************************************************** 2290 */ 2291 #define ARCMSR_ATU_COMMAND_REG 0x04 /*word*/ 2292 /* 2293 *********************************************************************************** 2294 ** ATU Status Register - ATUSR (Sheet 1 of 2) 2295 ** ----------------------------------------------------------------- 2296 ** Bit Default Description 2297 ** 15 0 2 Detected Parity Error - set when a parity error is detected in data received by the ATU on the PCI bus even 2298 ** when the ATUCMD register��s Parity Error Response bit is cleared. Set under the following conditions: 2299 ** �E Write Data Parity Error when the ATU is a target (inbound write). 2300 ** �E Read Data Parity Error when the ATU is a requester (outbound read). 2301 ** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus ** ** ** (including one generated by the ATU). 2302 ** 14 0 2 SERR# Asserted - set when SERR# is asserted on the PCI bus by the ATU. 2303 ** 13 0 2 Master Abort - set when a transaction initiated by the ATU PCI master interface, ends in a Master-Abort 2304 ** or when the ATU receives a Master Abort Split Completion Error Message in PCI-X mode. 2305 ** 12 0 2 Target Abort (master) - set when a transaction initiated by the ATU PCI master interface, ends in a target 2306 ** abort or when the ATU receives a Target Abort Split Completion Error Message in PCI-X mode. 2307 ** 11 0 2 Target Abort (target) - set when the ATU interface, acting as a target, 2308 ** terminates the transaction on the PCI bus with a target abort. 2309 ** 10:09 01 2 DEVSEL# Timing - These bits are read-only and define the slowest DEVSEL# 2310 ** timing for a target device in Conventional PCI Mode regardless of the operating mode 2311 ** (except configuration accesses). 2312 ** 00 2=Fast 2313 ** 01 2=Medium 2314 ** 10 2=Slow 2315 ** 11 2=Reserved 2316 ** The ATU interface uses Medium timing. 2317 ** 08 0 2 Master Parity Error - The ATU interface sets this bit under the following conditions: 2318 ** �E The ATU asserted PERR# itself or the ATU observed PERR# asserted. 2319 ** �E And the ATU acted as the requester 2320 ** for the operation in which the error occurred. 2321 ** �E And the ATUCMD register��s Parity Error Response bit is set 2322 ** �E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message 2323 ** �E And the ATUCMD register��s Parity Error Response bit is set 2324 ** 07 1 2 (Conventional mode) 2325 ** 0 2 (PCI-X mode) 2326 ** Fast Back-to-Back - The ATU/Messaging Unit interface is capable of accepting fast back-to-back 2327 ** transactions in Conventional PCI mode when the transactions are not to the same target. Since fast 2328 ** back-to-back transactions do not exist in PCI-X mode, this bit is forced to 0 in the PCI-X mode. 2329 ** 06 0 2 UDF Supported - User Definable Features are not supported 2330 ** 05 1 2 66 MHz. Capable - 66 MHz operation is supported. 2331 ** 04 1 2 Capabilities - When set, this function implements extended capabilities. 2332 ** 03 0 Interrupt Status - reflects the state of the ATU interrupt 2333 ** when the Interrupt Disable bit in the command register is a 0. 2334 ** 0=ATU interrupt signal deasserted. 2335 ** 1=ATU interrupt signal asserted. 2336 ** NOTE: Setting the Interrupt Disable bit to a 1 has no effect on the state of this bit. Refer to 2337 ** Section 3.10.23, ��ATU Interrupt Pin Register - ATUIPR�� on page 236 for details on the ATU 2338 ** interrupt signal. 2339 ** 02:00 00000 2 Reserved. 2340 *********************************************************************************** 2341 */ 2342 #define ARCMSR_ATU_STATUS_REG 0x06 /*word*/ 2343 /* 2344 *********************************************************************************** 2345 ** ATU Revision ID Register - ATURID 2346 ** ----------------------------------------------------------------- 2347 ** Bit Default Description 2348 ** 07:00 00H ATU Revision - identifies the 80331 revision number. 2349 *********************************************************************************** 2350 */ 2351 #define ARCMSR_ATU_REVISION_REG 0x08 /*byte*/ 2352 /* 2353 *********************************************************************************** 2354 ** ATU Class Code Register - ATUCCR 2355 ** ----------------------------------------------------------------- 2356 ** Bit Default Description 2357 ** 23:16 05H Base Class - Memory Controller 2358 ** 15:08 80H Sub Class - Other Memory Controller 2359 ** 07:00 00H Programming Interface - None defined 2360 *********************************************************************************** 2361 */ 2362 #define ARCMSR_ATU_CLASS_CODE_REG 0x09 /*3bytes 0x0B,0x0A,0x09*/ 2363 /* 2364 *********************************************************************************** 2365 ** ATU Cacheline Size Register - ATUCLSR 2366 ** ----------------------------------------------------------------- 2367 ** Bit Default Description 2368 ** 07:00 00H ATU Cacheline Size - specifies the system cacheline size in DWORDs. Cacheline size is restricted to either 0, 8 or 16 DWORDs. 2369 *********************************************************************************** 2370 */ 2371 #define ARCMSR_ATU_CACHELINE_SIZE_REG 0x0C /*byte*/ 2372 /* 2373 *********************************************************************************** 2374 ** ATU Latency Timer Register - ATULT 2375 ** ----------------------------------------------------------------- 2376 ** Bit Default Description 2377 ** 07:03 00000 2 (for Conventional mode) 2378 ** 01000 2 (for PCI-X mode) 2379 ** Programmable Latency Timer - This field varies the latency timer for the interface from 0 to 248 clocks. 2380 ** The default value is 0 clocks for Conventional PCI mode, and 64 clocks for PCI-X mode. 2381 ** 02:00 000 2 Latency Timer Granularity - These Bits are read only giving a programmable granularity of 8 clocks for the latency timer. 2382 *********************************************************************************** 2383 */ 2384 #define ARCMSR_ATU_LATENCY_TIMER_REG 0x0D /*byte*/ 2385 /* 2386 *********************************************************************************** 2387 ** ATU Header Type Register - ATUHTR 2388 ** ----------------------------------------------------------------- 2389 ** Bit Default Description 2390 ** 07 0 2 Single Function/Multi-Function Device - Identifies the 80331 as a single-function PCI device. 2391 ** 06:00 000000 2 PCI Header Type - This bit field indicates the type of PCI header implemented. The ATU interface 2392 ** header conforms to PCI Local Bus Specification, Revision 2.3. 2393 *********************************************************************************** 2394 */ 2395 #define ARCMSR_ATU_HEADER_TYPE_REG 0x0E /*byte*/ 2396 /* 2397 *********************************************************************************** 2398 ** ATU BIST Register - ATUBISTR 2399 ** 2400 ** The ATU BIST Register controls the functions the Intel XScale core performs when BIST is 2401 ** initiated. This register is the interface between the host processor requesting BIST functions and 2402 ** the 80331 replying with the results from the software implementation of the BIST functionality. 2403 ** ----------------------------------------------------------------- 2404 ** Bit Default Description 2405 ** 07 0 2 BIST Capable - This bit value is always equal to the ATUCR ATU BIST Interrupt Enable bit. 2406 ** 06 0 2 Start BIST - When the ATUCR BIST Interrupt Enable bit is set: 2407 ** Setting this bit generates an interrupt to the Intel XScale core to perform a software BIST function. 2408 ** The Intel XScale core clears this bit when the BIST software has completed with the BIST results 2409 ** found in ATUBISTR register bits [3:0]. 2410 ** When the ATUCR BIST Interrupt Enable bit is clear: 2411 ** Setting this bit does not generate an interrupt to the Intel XScale core and no BIST functions is performed. 2412 ** The Intel XScale core does not clear this bit. 2413 ** 05:04 00 2 Reserved 2414 ** 03:00 0000 2 BIST Completion Code - when the ATUCR BIST Interrupt Enable bit is set and the ATUBISTR Start BIST bit is set (bit 6): 2415 ** The Intel XScale core places the results of the software BIST in these bits. 2416 ** A nonzero value indicates a device-specific error. 2417 *********************************************************************************** 2418 */ 2419 #define ARCMSR_ATU_BIST_REG 0x0F /*byte*/ 2420 2421 /* 2422 *************************************************************************************** 2423 ** ATU Base Registers and Associated Limit Registers 2424 *************************************************************************************** 2425 ** Base Address Register Limit Register Description 2426 ** Inbound ATU Base Address Register 0 Inbound ATU Limit Register 0 Defines the inbound translation window 0 from the PCI bus. 2427 ** Inbound ATU Upper Base Address Register 0 N/A Together with ATU Base Address Register 0 defines the inbound ** translation window 0 from the PCI bus for DACs. 2428 ** Inbound ATU Base Address Register 1 Inbound ATU Limit Register 1 Defines inbound window 1 from the PCI bus. 2429 ** Inbound ATU Upper Base Address Register 1 N/A Together with ATU Base Address Register 1 defines inbound window ** 1 from the PCI bus for DACs. 2430 ** Inbound ATU Base Address Register 2 Inbound ATU Limit Register 2 Defines the inbound translation window 2 from the PCI bus. 2431 ** Inbound ATU Upper Base Address Register 2 N/A Together with ATU Base Address Register 2 defines the inbound ** ** translation window 2 from the PCI bus for DACs. 2432 ** Inbound ATU Base Address Register 3 Inbound ATU Limit Register 3 Defines the inbound translation window 3 from the PCI bus. 2433 ** Inbound ATU Upper Base Address Register 3 N/A Together with ATU Base Address Register 3 defines the inbound ** ** translation window 3 from the PCI bus for DACs. 2434 ** NOTE: This is a private BAR that resides outside of the standard PCI configuration header space (offsets 00H-3FH). 2435 ** Expansion ROM Base Address Register Expansion ROM Limit Register Defines the window of addresses used by a bus master for reading ** from an Expansion ROM. 2436 **-------------------------------------------------------------------------------------- 2437 ** ATU Inbound Window 1 is not a translate window. 2438 ** The ATU does not claim any PCI accesses that fall within this range. 2439 ** This window is used to allocate host memory for use by Private Devices. 2440 ** When enabled, the ATU interrupts the Intel XScale core when either the IABAR1 register or the IAUBAR1 register is written from the PCI bus. 2441 *********************************************************************************** 2442 */ 2443 2444 /* 2445 *********************************************************************************** 2446 ** Inbound ATU Base Address Register 0 - IABAR0 2447 ** 2448 ** . The Inbound ATU Base Address Register 0 (IABAR0) together with the Inbound ATU Upper Base Address Register 0 (IAUBAR0) 2449 ** defines the block of memory addresses where the inbound translation window 0 begins. 2450 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 2451 ** . The IABAR0 and IAUBAR0 define the base address and describes the required memory block size. 2452 ** . Bits 31 through 12 of the IABAR0 is either read/write bits or read only with a value of 0 2453 ** depending on the value located within the IALR0. 2454 ** This configuration allows the IABAR0 to be programmed per PCI Local Bus Specification. 2455 ** The first 4 Kbytes of memory defined by the IABAR0, IAUBAR0 and the IALR0 is reserved for the Messaging Unit. 2456 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2457 ** Warning: 2458 ** When IALR0 is cleared prior to host configuration: 2459 ** the user should also clear the Prefetchable Indicator and the Type Indicator. 2460 ** Assuming IALR0 is not cleared: 2461 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 2462 ** when the Prefetchable Indicator is cleared prior to host configuration, 2463 ** the user should also set the Type Indicator for 32 bit addressability. 2464 ** b. For compliance to the PCI-X Addendum to the PCI Local Bus Specification, 2465 ** when the Prefetchable Indicator is set prior to host configuration, the user 2466 ** should also set the Type Indicator for 64 bit addressability. 2467 ** This is the default for IABAR0. 2468 ** ----------------------------------------------------------------- 2469 ** Bit Default Description 2470 ** 31:12 00000H Translation Base Address 0 - These bits define the actual location 2471 ** the translation function is to respond to when addressed from the PCI bus. 2472 ** 11:04 00H Reserved. 2473 ** 03 1 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 2474 ** 02:01 10 2 Type Indicator - Defines the width of the addressability for this memory window: 2475 ** 00 - Memory Window is locatable anywhere in 32 bit address space 2476 ** 10 - Memory Window is locatable anywhere in 64 bit address space 2477 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 2478 ** The ATU does not occupy I/O space, 2479 ** thus this bit must be zero. 2480 *********************************************************************************** 2481 */ 2482 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS0_REG 0x10 /*dword 0x13,0x12,0x11,0x10*/ 2483 #define ARCMSR_INBOUND_ATU_MEMORY_PREFETCHABLE 0x08 2484 #define ARCMSR_INBOUND_ATU_MEMORY_WINDOW64 0x04 2485 /* 2486 *********************************************************************************** 2487 ** Inbound ATU Upper Base Address Register 0 - IAUBAR0 2488 ** 2489 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 2490 ** Together with the Translation Base Address this register defines the actual location the translation 2491 ** function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 2492 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2493 ** Note: 2494 ** When the Type indicator of IABAR0 is set to indicate 32 bit addressability, 2495 ** the IAUBAR0 register attributes are read-only. 2496 ** ----------------------------------------------------------------- 2497 ** Bit Default Description 2498 ** 31:0 00000H Translation Upper Base Address 0 - Together with the Translation Base Address 0 these bits define the 2499 ** actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes. 2500 *********************************************************************************** 2501 */ 2502 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS0_REG 0x14 /*dword 0x17,0x16,0x15,0x14*/ 2503 /* 2504 *********************************************************************************** 2505 ** Inbound ATU Base Address Register 1 - IABAR1 2506 ** 2507 ** . The Inbound ATU Base Address Register (IABAR1) together with the Inbound ATU Upper Base Address Register 1 (IAUBAR1) 2508 ** defines the block of memory addresses where the inbound translation window 1 begins. 2509 ** . This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PCI bus transactions to this memory range. 2510 ** . The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2511 ** . When enabled, the ATU interrupts the Intel XScale core when the IABAR1 register is written from the PCI bus. 2512 ** Warning: 2513 ** When a non-zero value is not written to IALR1 prior to host configuration, 2514 ** the user should not set either the Prefetchable Indicator or the Type Indicator for 64 bit addressability. 2515 ** This is the default for IABAR1. 2516 ** Assuming a non-zero value is written to IALR1, 2517 ** the user may set the Prefetchable Indicator 2518 ** or the Type Indicator: 2519 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address 2520 ** boundary, when the Prefetchable Indicator is not set prior to host configuration, 2521 ** the user should also leave the Type Indicator set for 32 bit addressability. 2522 ** This is the default for IABAR1. 2523 ** b. when the Prefetchable Indicator is set prior to host configuration, 2524 ** the user should also set the Type Indicator for 64 bit addressability. 2525 ** ----------------------------------------------------------------- 2526 ** Bit Default Description 2527 ** 31:12 00000H Translation Base Address 1 - These bits define the actual location of window 1 on the PCI bus. 2528 ** 11:04 00H Reserved. 2529 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 2530 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 2531 ** 00 - Memory Window is locatable anywhere in 32 bit address space 2532 ** 10 - Memory Window is locatable anywhere in 64 bit address space 2533 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 2534 ** The ATU does not occupy I/O space, 2535 ** thus this bit must be zero. 2536 *********************************************************************************** 2537 */ 2538 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS1_REG 0x18 /*dword 0x1B,0x1A,0x19,0x18*/ 2539 /* 2540 *********************************************************************************** 2541 ** Inbound ATU Upper Base Address Register 1 - IAUBAR1 2542 ** 2543 ** This register contains the upper base address when locating this window for PCI addresses beyond 4 GBytes. 2544 ** Together with the IABAR1 this register defines the actual location for this memory window for addresses > 4GBytes (for DACs). 2545 ** This window is used merely to allocate memory on the PCI bus and, the ATU does not process any PCI bus transactions to this memory range. 2546 ** The programmed value within the base address register must comply with the PCI programming 2547 ** requirements for address alignment. 2548 ** When enabled, the ATU interrupts the Intel XScale core when the IAUBAR1 register is written 2549 ** from the PCI bus. 2550 ** Note: 2551 ** When the Type indicator of IABAR1 is set to indicate 32 bit addressability, 2552 ** the IAUBAR1 register attributes are read-only. 2553 ** This is the default for IABAR1. 2554 ** ----------------------------------------------------------------- 2555 ** Bit Default Description 2556 ** 31:0 00000H Translation Upper Base Address 1 - Together with the Translation Base Address 1 2557 ** these bits define the actual location for this memory window on the PCI bus for addresses > 4GBytes. 2558 *********************************************************************************** 2559 */ 2560 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS1_REG 0x1C /*dword 0x1F,0x1E,0x1D,0x1C*/ 2561 /* 2562 *********************************************************************************** 2563 ** Inbound ATU Base Address Register 2 - IABAR2 2564 ** 2565 ** . The Inbound ATU Base Address Register 2 (IABAR2) together with the Inbound ATU Upper Base Address Register 2 (IAUBAR2) 2566 ** defines the block of memory addresses where the inbound translation window 2 begins. 2567 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 2568 ** . The IABAR2 and IAUBAR2 define the base address and describes the required memory block size 2569 ** . Bits 31 through 12 of the IABAR2 is either read/write bits or read only with a value of 0 depending on the value located within the IALR2. 2570 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 2571 ** Warning: 2572 ** When a non-zero value is not written to IALR2 prior to host configuration, 2573 ** the user should not set either the Prefetchable Indicator 2574 ** or the Type Indicator for 64 bit addressability. 2575 ** This is the default for IABAR2. 2576 ** Assuming a non-zero value is written to IALR2, 2577 ** the user may set the Prefetchable Indicator 2578 ** or the Type Indicator: 2579 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 2580 ** when the Prefetchable Indicator is not set prior to host configuration, 2581 ** the user should also leave the Type Indicator set for 32 bit addressability. 2582 ** This is the default for IABAR2. 2583 ** b. when the Prefetchable Indicator is set prior to host configuration, 2584 ** the user should also set the Type Indicator for 64 bit addressability. 2585 ** ----------------------------------------------------------------- 2586 ** Bit Default Description 2587 ** 31:12 00000H Translation Base Address 2 - These bits define the actual location 2588 ** the translation function is to respond to when addressed from the PCI bus. 2589 ** 11:04 00H Reserved. 2590 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 2591 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 2592 ** 00 - Memory Window is locatable anywhere in 32 bit address space 2593 ** 10 - Memory Window is locatable anywhere in 64 bit address space 2594 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 2595 ** The ATU does not occupy I/O space, 2596 ** thus this bit must be zero. 2597 *********************************************************************************** 2598 */ 2599 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS2_REG 0x20 /*dword 0x23,0x22,0x21,0x20*/ 2600 /* 2601 *********************************************************************************** 2602 ** Inbound ATU Upper Base Address Register 2 - IAUBAR2 2603 ** 2604 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 2605 ** Together with the Translation Base Address this register defines the actual location 2606 ** the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 2607 ** The programmed value within the base address register must comply with the PCI programming 2608 ** requirements for address alignment. 2609 ** Note: 2610 ** When the Type indicator of IABAR2 is set to indicate 32 bit addressability, 2611 ** the IAUBAR2 register attributes are read-only. 2612 ** This is the default for IABAR2. 2613 ** ----------------------------------------------------------------- 2614 ** Bit Default Description 2615 ** 31:0 00000H Translation Upper Base Address 2 - Together with the Translation Base Address 2 2616 ** these bits define the actual location the translation function is to respond to 2617 ** when addressed from the PCI bus for addresses > 4GBytes. 2618 *********************************************************************************** 2619 */ 2620 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS2_REG 0x24 /*dword 0x27,0x26,0x25,0x24*/ 2621 /* 2622 *********************************************************************************** 2623 ** ATU Subsystem Vendor ID Register - ASVIR 2624 ** ----------------------------------------------------------------- 2625 ** Bit Default Description 2626 ** 15:0 0000H Subsystem Vendor ID - This register uniquely identifies the add-in board or subsystem vendor. 2627 *********************************************************************************** 2628 */ 2629 #define ARCMSR_ATU_SUBSYSTEM_VENDOR_ID_REG 0x2C /*word 0x2D,0x2C*/ 2630 /* 2631 *********************************************************************************** 2632 ** ATU Subsystem ID Register - ASIR 2633 ** ----------------------------------------------------------------- 2634 ** Bit Default Description 2635 ** 15:0 0000H Subsystem ID - uniquely identifies the add-in board or subsystem. 2636 *********************************************************************************** 2637 */ 2638 #define ARCMSR_ATU_SUBSYSTEM_ID_REG 0x2E /*word 0x2F,0x2E*/ 2639 /* 2640 *********************************************************************************** 2641 ** Expansion ROM Base Address Register -ERBAR 2642 ** ----------------------------------------------------------------- 2643 ** Bit Default Description 2644 ** 31:12 00000H Expansion ROM Base Address - These bits define the actual location 2645 ** where the Expansion ROM address window resides when addressed from the PCI bus on any 4 Kbyte boundary. 2646 ** 11:01 000H Reserved 2647 ** 00 0 2 Address Decode Enable - This bit field shows the ROM address 2648 ** decoder is enabled or disabled. When cleared, indicates the address decoder is disabled. 2649 *********************************************************************************** 2650 */ 2651 #define ARCMSR_EXPANSION_ROM_BASE_ADDRESS_REG 0x30 /*dword 0x33,0x32,0v31,0x30*/ 2652 #define ARCMSR_EXPANSION_ROM_ADDRESS_DECODE_ENABLE 0x01 2653 /* 2654 *********************************************************************************** 2655 ** ATU Capabilities Pointer Register - ATU_CAP_PTR 2656 ** ----------------------------------------------------------------- 2657 ** Bit Default Description 2658 ** 07:00 C0H Capability List Pointer - This provides an offset in this function��s configuration space 2659 ** that points to the 80331 PCl Bus Power Management extended capability. 2660 *********************************************************************************** 2661 */ 2662 #define ARCMSR_ATU_CAPABILITY_PTR_REG 0x34 /*byte*/ 2663 /* 2664 *********************************************************************************** 2665 ** Determining Block Sizes for Base Address Registers 2666 ** The required address size and type can be determined by writing ones to a base address register and 2667 ** reading from the registers. By scanning the returned value from the least-significant bit of the base 2668 ** address registers upwards, the programmer can determine the required address space size. The 2669 ** binary-weighted value of the first non-zero bit found indicates the required amount of space. 2670 ** Table 105 describes the relationship between the values read back and the byte sizes the base 2671 ** address register requires. 2672 ** As an example, assume that FFFF.FFFFH is written to the ATU Inbound Base Address Register 0 2673 ** (IABAR0) and the value read back is FFF0.0008H. Bit zero is a zero, so the device requires 2674 ** memory address space. Bit three is one, so the memory does supports prefetching. Scanning 2675 ** upwards starting at bit four, bit twenty is the first one bit found. The binary-weighted value of this 2676 ** bit is 1,048,576, indicated that the device requires 1 Mbyte of memory space. 2677 ** The ATU Base Address Registers and the Expansion ROM Base Address Register use their 2678 ** associated limit registers to enable which bits within the base address register are read/write and 2679 ** which bits are read only (0). This allows the programming of these registers in a manner similar to 2680 ** other PCI devices even though the limit is variable. 2681 ** Table 105. Memory Block Size Read Response 2682 ** Response After Writing all 1s 2683 ** to the Base Address Register 2684 ** Size 2685 ** (Bytes) 2686 ** Response After Writing all 1s 2687 ** to the Base Address Register 2688 ** Size 2689 ** (Bytes) 2690 ** FFFFFFF0H 16 FFF00000H 1 M 2691 ** FFFFFFE0H 32 FFE00000H 2 M 2692 ** FFFFFFC0H 64 FFC00000H 4 M 2693 ** FFFFFF80H 128 FF800000H 8 M 2694 ** FFFFFF00H 256 FF000000H 16 M 2695 ** FFFFFE00H 512 FE000000H 32 M 2696 ** FFFFFC00H 1K FC000000H 64 M 2697 ** FFFFF800H 2K F8000000H 128 M 2698 ** FFFFF000H 4K F0000000H 256 M 2699 ** FFFFE000H 8K E0000000H 512 M 2700 ** FFFFC000H 16K C0000000H 1 G 2701 ** FFFF8000H 32K 80000000H 2 G 2702 ** FFFF0000H 64K 2703 ** 00000000H 2704 ** Register not 2705 ** imple-mented, 2706 ** no 2707 ** address 2708 ** space 2709 ** required. 2710 ** FFFE0000H 128K 2711 ** FFFC0000H 256K 2712 ** FFF80000H 512K 2713 ** 2714 *************************************************************************************** 2715 */ 2716 2717 2718 2719 /* 2720 *********************************************************************************** 2721 ** ATU Interrupt Line Register - ATUILR 2722 ** ----------------------------------------------------------------- 2723 ** Bit Default Description 2724 ** 07:00 FFH Interrupt Assigned - system-assigned value identifies which system interrupt controller��s interrupt 2725 ** request line connects to the device's PCI interrupt request lines 2726 ** (as specified in the interrupt pin register). 2727 ** A value of FFH signifies ��no connection�� or ��unknown��. 2728 *********************************************************************************** 2729 */ 2730 #define ARCMSR_ATU_INTERRUPT_LINE_REG 0x3C /*byte*/ 2731 /* 2732 *********************************************************************************** 2733 ** ATU Interrupt Pin Register - ATUIPR 2734 ** ----------------------------------------------------------------- 2735 ** Bit Default Description 2736 ** 07:00 01H Interrupt Used - A value of 01H signifies that the ATU interface unit uses INTA# as the interrupt pin. 2737 *********************************************************************************** 2738 */ 2739 #define ARCMSR_ATU_INTERRUPT_PIN_REG 0x3D /*byte*/ 2740 /* 2741 *********************************************************************************** 2742 ** ATU Minimum Grant Register - ATUMGNT 2743 ** ----------------------------------------------------------------- 2744 ** Bit Default Description 2745 ** 07:00 80H This register specifies how long a burst period the device needs in increments of 8 PCI clocks. 2746 *********************************************************************************** 2747 */ 2748 #define ARCMSR_ATU_MINIMUM_GRANT_REG 0x3E /*byte*/ 2749 /* 2750 *********************************************************************************** 2751 ** ATU Maximum Latency Register - ATUMLAT 2752 ** ----------------------------------------------------------------- 2753 ** Bit Default Description 2754 ** 07:00 00H Specifies frequency (how often) the device needs to access the PCI bus 2755 ** in increments of 8 PCI clocks. A zero value indicates the device has no stringent requirement. 2756 *********************************************************************************** 2757 */ 2758 #define ARCMSR_ATU_MAXIMUM_LATENCY_REG 0x3F /*byte*/ 2759 /* 2760 *********************************************************************************** 2761 ** Inbound Address Translation 2762 ** 2763 ** The ATU allows external PCI bus initiators to directly access the internal bus. 2764 ** These PCI bus initiators can read or write 80331 memory-mapped registers or 80331 local memory space. 2765 ** The process of inbound address translation involves two steps: 2766 ** 1. Address Detection. 2767 ** �E Determine when the 32-bit PCI address (64-bit PCI address during DACs) is 2768 ** within the address windows defined for the inbound ATU. 2769 ** �E Claim the PCI transaction with medium DEVSEL# timing in the conventional PCI 2770 ** mode and with Decode A DEVSEL# timing in the PCI-X mode. 2771 ** 2. Address Translation. 2772 ** �E Translate the 32-bit PCI address (lower 32-bit PCI address during DACs) to a 32-bit 80331 internal bus address. 2773 ** The ATU uses the following registers in inbound address window 0 translation: 2774 ** �E Inbound ATU Base Address Register 0 2775 ** �E Inbound ATU Limit Register 0 2776 ** �E Inbound ATU Translate Value Register 0 2777 ** The ATU uses the following registers in inbound address window 2 translation: 2778 ** �E Inbound ATU Base Address Register 2 2779 ** �E Inbound ATU Limit Register 2 2780 ** �E Inbound ATU Translate Value Register 2 2781 ** The ATU uses the following registers in inbound address window 3 translation: 2782 ** �E Inbound ATU Base Address Register 3 2783 ** �E Inbound ATU Limit Register 3 2784 ** �E Inbound ATU Translate Value Register 3 2785 ** Note: Inbound Address window 1 is not a translate window. 2786 ** Instead, window 1 may be used to allocate host memory for Private Devices. 2787 ** Inbound Address window 3 does not reside in the standard section of the configuration header (offsets 00H - 3CH), 2788 ** thus the host BIOS does not configure window 3. 2789 ** Window 3 is intended to be used as a special window into local memory for private PCI 2790 ** agents controlled by the 80331 in conjunction with the Private Memory Space of the bridge. 2791 ** PCI-to-PCI Bridge in 80331 or 2792 ** Inbound address detection is determined from the 32-bit PCI address, 2793 ** (64-bit PCI address during DACs) the base address register and the limit register. 2794 ** In the case of DACs none of the upper 32-bits of the address is masked during address comparison. 2795 ** 2796 ** The algorithm for detection is: 2797 ** 2798 ** Equation 1. Inbound Address Detection 2799 ** When (PCI_Address [31:0] & Limit_Register[31:0]) == (Base_Register[31:0] & PCI_Address [63:32]) == Base_Register[63:32] (for DACs only) 2800 ** the PCI Address is claimed by the Inbound ATU. 2801 ** 2802 ** The incoming 32-bit PCI address (lower 32-bits of the address in case of DACs) is bitwise ANDed 2803 ** with the associated inbound limit register. 2804 ** When the result matches the base register (and upper base address matches upper PCI address in case of DACs), 2805 ** the inbound PCI address is detected as being within the inbound translation window and is claimed by the ATU. 2806 ** 2807 ** Note: The first 4 Kbytes of the ATU inbound address translation window 0 are reserved for the Messaging Unit. 2808 ** Once the transaction is claimed, the address must be translated from a PCI address to a 32-bit 2809 ** internal bus address. In case of DACs upper 32-bits of the address is simply discarded and only the 2810 ** lower 32-bits are used during address translation. 2811 ** The algorithm is: 2812 ** 2813 ** 2814 ** Equation 2. Inbound Translation 2815 ** Intel I/O processor Internal Bus Address=(PCI_Address[31:0] & ~Limit_Register[31:0]) | ATU_Translate_Value_Register[31:0]. 2816 ** 2817 ** The incoming 32-bit PCI address (lower 32-bits in case of DACs) is first bitwise ANDed with the 2818 ** bitwise inverse of the limit register. This result is bitwise ORed with the ATU Translate Value and 2819 ** the result is the internal bus address. This translation mechanism is used for all inbound memory 2820 ** read and write commands excluding inbound configuration read and writes. 2821 ** In the PCI mode for inbound memory transactions, the only burst order supported is Linear 2822 ** Incrementing. For any other burst order, the ATU signals a Disconnect after the first data phase. 2823 ** The PCI-X supports linear incrementing only, and hence above situation is not encountered in the PCI-X mode. 2824 ** example: 2825 ** Register Values 2826 ** Base_Register=3A00 0000H 2827 ** Limit_Register=FF80 0000H (8 Mbyte limit value) 2828 ** Value_Register=B100 0000H 2829 ** Inbound Translation Window ranges from 3A00 0000H to 3A7F FFFFH (8 Mbytes) 2830 ** 2831 ** Address Detection (32-bit address) 2832 ** 2833 ** PCI_Address & Limit_Register == Base_Register 2834 ** 3A45 012CH & FF80 0000H == 3A00 0000H 2835 ** 2836 ** ANS: PCI_Address is in the Inbound Translation Window 2837 ** Address Translation (to get internal bus address) 2838 ** 2839 ** IB_Address=(PCI_Address & ~Limit_Register) | Value_Reg 2840 ** IB_Address=(3A45 012CH & 007F FFFFH) | B100 0000H 2841 ** 2842 ** ANS:IB_Address=B145 012CH 2843 *********************************************************************************** 2844 */ 2845 2846 2847 2848 /* 2849 *********************************************************************************** 2850 ** Inbound ATU Limit Register 0 - IALR0 2851 ** 2852 ** Inbound address translation for memory window 0 occurs for data transfers occurring from the PCI 2853 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 2854 ** PCI addresses to internal bus addresses. 2855 ** The 80331 translate value register��s programmed value must be naturally aligned with the base 2856 ** address register��s programmed value. The limit register is used as a mask; thus, the lower address 2857 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 2858 ** Specification, Revision 2.3 for additional information on programming base address registers. 2859 ** Bits 31 to 12 within the IALR0 have a direct effect on the IABAR0 register, bits 31 to 12, with a 2860 ** one to one correspondence. A value of 0 in a bit within the IALR0 makes the corresponding bit 2861 ** within the IABAR0 a read only bit which always returns 0. A value of 1 in a bit within the IALR0 2862 ** makes the corresponding bit within the IABAR0 read/write from PCI. Note that a consequence of 2863 ** this programming scheme is that unless a valid value exists within the IALR0, all writes to the 2864 ** IABAR0 has no effect since a value of all zeros within the IALR0 makes the IABAR0 a read only register. 2865 ** ----------------------------------------------------------------- 2866 ** Bit Default Description 2867 ** 31:12 FF000H Inbound Translation Limit 0 - This readback value determines the memory block size required for 2868 ** inbound memory window 0 of the address translation unit. This defaults to an inbound window of 16MB. 2869 ** 11:00 000H Reserved 2870 *********************************************************************************** 2871 */ 2872 #define ARCMSR_INBOUND_ATU_LIMIT0_REG 0x40 /*dword 0x43,0x42,0x41,0x40*/ 2873 /* 2874 *********************************************************************************** 2875 ** Inbound ATU Translate Value Register 0 - IATVR0 2876 ** 2877 ** The Inbound ATU Translate Value Register 0 (IATVR0) contains the internal bus address used to 2878 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 2879 ** inbound ATU address translation. 2880 ** ----------------------------------------------------------------- 2881 ** Bit Default Description 2882 ** 31:12 FF000H Inbound ATU Translation Value 0 - This value is used to convert the PCI address to internal bus addresses. 2883 ** This value must be 64-bit aligned on the internal bus. 2884 ** The default address allows the ATU to access the internal 80331 memory-mapped registers. 2885 ** 11:00 000H Reserved 2886 *********************************************************************************** 2887 */ 2888 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE0_REG 0x44 /*dword 0x47,0x46,0x45,0x44*/ 2889 /* 2890 *********************************************************************************** 2891 ** Expansion ROM Limit Register - ERLR 2892 ** 2893 ** The Expansion ROM Limit Register (ERLR) defines the block size of addresses the ATU defines 2894 ** as Expansion ROM address space. The block size is programmed by writing a value into the ERLR. 2895 ** Bits 31 to 12 within the ERLR have a direct effect on the ERBAR register, bits 31 to 12, with a one 2896 ** to one correspondence. A value of 0 in a bit within the ERLR makes the corresponding bit within 2897 ** the ERBAR a read only bit which always returns 0. A value of 1 in a bit within the ERLR makes 2898 ** the corresponding bit within the ERBAR read/write from PCI. 2899 ** ----------------------------------------------------------------- 2900 ** Bit Default Description 2901 ** 31:12 000000H Expansion ROM Limit - Block size of memory required for the Expansion ROM translation unit. Default 2902 ** value is 0, which indicates no Expansion ROM address space and all bits within the ERBAR are read only with a value of 0. 2903 ** 11:00 000H Reserved. 2904 *********************************************************************************** 2905 */ 2906 #define ARCMSR_EXPANSION_ROM_LIMIT_REG 0x48 /*dword 0x4B,0x4A,0x49,0x48*/ 2907 /* 2908 *********************************************************************************** 2909 ** Expansion ROM Translate Value Register - ERTVR 2910 ** 2911 ** The Expansion ROM Translate Value Register contains the 80331 internal bus address which the 2912 ** ATU converts the PCI bus access. This address is driven on the internal bus as a result of the 2913 ** Expansion ROM address translation. 2914 ** ----------------------------------------------------------------- 2915 ** Bit Default Description 2916 ** 31:12 00000H Expansion ROM Translation Value - Used to convert PCI addresses to 80331 internal bus addresses 2917 ** for Expansion ROM accesses. The Expansion ROM address translation value must be word aligned on the internal bus. 2918 ** 11:00 000H Reserved 2919 *********************************************************************************** 2920 */ 2921 #define ARCMSR_EXPANSION_ROM_TRANSLATE_VALUE_REG 0x4C /*dword 0x4F,0x4E,0x4D,0x4C*/ 2922 /* 2923 *********************************************************************************** 2924 ** Inbound ATU Limit Register 1 - IALR1 2925 ** 2926 ** Bits 31 to 12 within the IALR1 have a direct effect on the IABAR1 register, bits 31 to 12, with a 2927 ** one to one correspondence. A value of 0 in a bit within the IALR1 makes the corresponding bit 2928 ** within the IABAR1 a read only bit which always returns 0. A value of 1 in a bit within the IALR1 2929 ** makes the corresponding bit within the IABAR1 read/write from PCI. Note that a consequence of 2930 ** this programming scheme is that unless a valid value exists within the IALR1, all writes to the 2931 ** IABAR1 has no effect since a value of all zeros within the IALR1 makes the IABAR1 a read only 2932 ** register. 2933 ** The inbound memory window 1 is used merely to allocate memory on the PCI bus. The ATU does 2934 ** not process any PCI bus transactions to this memory range. 2935 ** Warning: The ATU does not claim any PCI accesses that fall within the range defined by IABAR1, 2936 ** IAUBAR1, and IALR1. 2937 ** ----------------------------------------------------------------- 2938 ** Bit Default Description 2939 ** 31:12 00000H Inbound Translation Limit 1 - This readback value determines the memory block size 2940 ** required for the ATUs memory window 1. 2941 ** 11:00 000H Reserved 2942 *********************************************************************************** 2943 */ 2944 #define ARCMSR_INBOUND_ATU_LIMIT1_REG 0x50 /*dword 0x53,0x52,0x51,0x50*/ 2945 /* 2946 *********************************************************************************** 2947 ** Inbound ATU Limit Register 2 - IALR2 2948 ** 2949 ** Inbound address translation for memory window 2 occurs for data transfers occurring from the PCI 2950 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 2951 ** PCI addresses to internal bus addresses. 2952 ** The inbound translation base address for inbound window 2 is specified in Section 3.10.15. When 2953 ** determining block size requirements �X as described in Section 3.10.21 �X the translation limit 2954 ** register provides the block size requirements for the base address register. The remaining registers 2955 ** used for performing address translation are discussed in Section 3.2.1.1. 2956 ** The 80331 translate value register��s programmed value must be naturally aligned with the base 2957 ** address register��s programmed value. The limit register is used as a mask; thus, the lower address 2958 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 2959 ** Specification, Revision 2.3 for additional information on programming base address registers. 2960 ** Bits 31 to 12 within the IALR2 have a direct effect on the IABAR2 register, bits 31 to 12, with a 2961 ** one to one correspondence. A value of 0 in a bit within the IALR2 makes the corresponding bit 2962 ** within the IABAR2 a read only bit which always returns 0. A value of 1 in a bit within the IALR2 2963 ** makes the corresponding bit within the IABAR2 read/write from PCI. Note that a consequence of 2964 ** this programming scheme is that unless a valid value exists within the IALR2, all writes to the 2965 ** IABAR2 has no effect since a value of all zeros within the IALR2 makes the IABAR2 a read only 2966 ** register. 2967 ** ----------------------------------------------------------------- 2968 ** Bit Default Description 2969 ** 31:12 00000H Inbound Translation Limit 2 - This readback value determines the memory block size 2970 ** required for the ATUs memory window 2. 2971 ** 11:00 000H Reserved 2972 *********************************************************************************** 2973 */ 2974 #define ARCMSR_INBOUND_ATU_LIMIT2_REG 0x54 /*dword 0x57,0x56,0x55,0x54*/ 2975 /* 2976 *********************************************************************************** 2977 ** Inbound ATU Translate Value Register 2 - IATVR2 2978 ** 2979 ** The Inbound ATU Translate Value Register 2 (IATVR2) contains the internal bus address used to 2980 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 2981 ** inbound ATU address translation. 2982 ** ----------------------------------------------------------------- 2983 ** Bit Default Description 2984 ** 31:12 00000H Inbound ATU Translation Value 2 - This value is used to convert the PCI address to internal bus addresses. 2985 ** This value must be 64-bit aligned on the internal bus. 2986 ** The default address allows the ATU to access the internal 80331 ** ** memory-mapped registers. 2987 ** 11:00 000H Reserved 2988 *********************************************************************************** 2989 */ 2990 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE2_REG 0x58 /*dword 0x5B,0x5A,0x59,0x58*/ 2991 /* 2992 *********************************************************************************** 2993 ** Outbound I/O Window Translate Value Register - OIOWTVR 2994 ** 2995 ** The Outbound I/O Window Translate Value Register (OIOWTVR) contains the PCI I/O address 2996 ** used to convert the internal bus access to a PCI address. This address is driven on the PCI bus as a 2997 ** result of the outbound ATU address translation. 2998 ** The I/O window is from 80331 internal bus address 9000 000H to 9000 FFFFH with the fixed 2999 ** length of 64 Kbytes. 3000 ** ----------------------------------------------------------------- 3001 ** Bit Default Description 3002 ** 31:16 0000H Outbound I/O Window Translate Value - Used to convert internal bus addresses to PCI addresses. 3003 ** 15:00 0000H Reserved 3004 *********************************************************************************** 3005 */ 3006 #define ARCMSR_OUTBOUND_IO_WINDOW_TRANSLATE_VALUE_REG 0x5C /*dword 0x5F,0x5E,0x5D,0x5C*/ 3007 /* 3008 *********************************************************************************** 3009 ** Outbound Memory Window Translate Value Register 0 -OMWTVR0 3010 ** 3011 ** The Outbound Memory Window Translate Value Register 0 (OMWTVR0) contains the PCI 3012 ** address used to convert 80331 internal bus addresses for outbound transactions. This address is 3013 ** driven on the PCI bus as a result of the outbound ATU address translation. 3014 ** The memory window is from internal bus address 8000 000H to 83FF FFFFH with the fixed length 3015 ** of 64 Mbytes. 3016 ** ----------------------------------------------------------------- 3017 ** Bit Default Description 3018 ** 31:26 00H Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses. 3019 ** 25:02 00 0000H Reserved 3020 ** 01:00 00 2 Burst Order - This bit field shows the address sequence during a memory burst. 3021 ** Only linear incrementing mode is supported. 3022 *********************************************************************************** 3023 */ 3024 #define ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x60 /*dword 0x63,0x62,0x61,0x60*/ 3025 /* 3026 *********************************************************************************** 3027 ** Outbound Upper 32-bit Memory Window Translate Value Register 0 - OUMWTVR0 3028 ** 3029 ** The Outbound Upper 32-bit Memory Window Translate Value Register 0 (OUMWTVR0) defines 3030 ** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to 3031 ** directly address anywhere within the 64-bit host address space. When this register is all-zero, then 3032 ** a SAC is generated on the PCI bus. 3033 ** The memory window is from internal bus address 8000 000H to 83FF FFFFH with the fixed 3034 ** length of 64 Mbytes. 3035 ** ----------------------------------------------------------------- 3036 ** Bit Default Description 3037 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 3038 *********************************************************************************** 3039 */ 3040 #define ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE0_REG 0x64 /*dword 0x67,0x66,0x65,0x64*/ 3041 /* 3042 *********************************************************************************** 3043 ** Outbound Memory Window Translate Value Register 1 -OMWTVR1 3044 ** 3045 ** The Outbound Memory Window Translate Value Register 1 (OMWTVR1) contains the PCI 3046 ** address used to convert 80331 internal bus addresses for outbound transactions. This address is 3047 ** driven on the PCI bus as a result of the outbound ATU address translation. 3048 ** The memory window is from internal bus address 8400 000H to 87FF FFFFH with the fixed length 3049 ** of 64 Mbytes. 3050 ** ----------------------------------------------------------------- 3051 ** Bit Default Description 3052 ** 31:26 00H Outbound MW Translate Value - Used to convert 80331 internal bus addresses to PCI addresses. 3053 ** 25:02 00 0000H Reserved 3054 ** 01:00 00 2 Burst Order - This bit field shows the address sequence during a memory burst. 3055 ** Only linear incrementing mode is supported. 3056 *********************************************************************************** 3057 */ 3058 #define ARCMSR_OUTBOUND_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x68 /*dword 0x6B,0x6A,0x69,0x68*/ 3059 /* 3060 *********************************************************************************** 3061 ** Outbound Upper 32-bit Memory Window Translate Value Register 1 - OUMWTVR1 3062 ** 3063 ** The Outbound Upper 32-bit Memory Window Translate Value Register 1 (OUMWTVR1) defines 3064 ** the upper 32-bits of address used during a dual address cycle. This enables the outbound ATU to 3065 ** directly address anywhere within the 64-bit host address space. When this register is all-zero, then 3066 ** a SAC is generated on the PCI bus. 3067 ** The memory window is from internal bus address 8400 000H to 87FF FFFFH with the fixed length 3068 ** of 64 Mbytes. 3069 ** ----------------------------------------------------------------- 3070 ** Bit Default Description 3071 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 3072 *********************************************************************************** 3073 */ 3074 #define ARCMSR_OUTBOUND_UPPER32_MEMORY_WINDOW_TRANSLATE_VALUE1_REG 0x6C /*dword 0x6F,0x6E,0x6D,0x6C*/ 3075 /* 3076 *********************************************************************************** 3077 ** Outbound Upper 32-bit Direct Window Translate Value Register - OUDWTVR 3078 ** 3079 ** The Outbound Upper 32-bit Direct Window Translate Value Register (OUDWTVR) defines the 3080 ** upper 32-bits of address used during a dual address cycle for the transactions via Direct Addressing 3081 ** Window. This enables the outbound ATU to directly address anywhere within the 64-bit host 3082 ** address space. When this register is all-zero, then a SAC is generated on the PCI bus. 3083 ** ----------------------------------------------------------------- 3084 ** Bit Default Description 3085 ** 31:00 0000 0000H These bits define the upper 32-bits of address driven during the dual address cycle (DAC). 3086 *********************************************************************************** 3087 */ 3088 #define ARCMSR_OUTBOUND_UPPER32_DIRECT_WINDOW_TRANSLATE_VALUE_REG 0x78 /*dword 0x7B,0x7A,0x79,0x78*/ 3089 /* 3090 *********************************************************************************** 3091 ** ATU Configuration Register - ATUCR 3092 ** 3093 ** The ATU Configuration Register controls the outbound address translation for address translation 3094 ** unit. It also contains bits for Conventional PCI Delayed Read Command (DRC) aliasing, discard 3095 ** timer status, SERR# manual assertion, SERR# detection interrupt masking, and ATU BIST 3096 ** interrupt enabling. 3097 ** ----------------------------------------------------------------- 3098 ** Bit Default Description 3099 ** 31:20 00H Reserved 3100 ** 19 0 2 ATU DRC Alias - when set, the ATU does not distinguish read commands when attempting to match a 3101 ** current PCI read transaction with read data enqueued within the DRC buffer. When clear, a current read 3102 ** transaction must have the exact same read command as the DRR for the ATU to deliver DRC data. Not 3103 ** applicable in the PCI-X mode. 3104 ** 18 0 2 Direct Addressing Upper 2Gbytes Translation Enable - When set, 3105 ** with Direct Addressing enabled (bit 7 of the ATUCR set), 3106 ** the ATU forwards internal bus cycles with an address between 0000.0040H and 3107 ** 7FFF.FFFFH to the PCI bus with bit 31 of the address set (8000.0000H - FFFF.FFFFH). 3108 ** When clear, no translation occurs. 3109 ** 17 0 2 Reserved 3110 ** 16 0 2 SERR# Manual Assertion - when set, the ATU asserts SERR# for one clock on the PCI interface. Until 3111 ** cleared, SERR# may not be manually asserted again. Once cleared, operation proceeds as specified. 3112 ** 15 0 2 ATU Discard Timer Status - when set, one of the 4 discard timers within the ATU has expired and 3113 ** discarded the delayed completion transaction within the queue. When clear, no timer has expired. 3114 ** 14:10 00000 2 Reserved 3115 ** 09 0 2 SERR# Detected Interrupt Enable - When set, the Intel XScale core is signalled an HPI# interrupt 3116 ** when the ATU detects that SERR# was asserted. When clear, 3117 ** the Intel XScale core is not interrupted when SERR# is detected. 3118 ** 08 0 2 Direct Addressing Enable - Setting this bit enables direct outbound addressing through the ATU. 3119 ** Internal bus cycles with an address between 0000.0040H and 7FFF.FFFFH automatically forwards to 3120 ** the PCI bus with or without translation of address bit 31 based on the setting of bit 18 of 3121 ** the ATUCR. 3122 ** 07:04 0000 2 Reserved 3123 ** 03 0 2 ATU BIST Interrupt Enable - When set, enables an interrupt to the Intel XScale core when the start 3124 ** BIST bit is set in the ATUBISTR register. This bit is also reflected as the BIST Capable bit 7 3125 ** in the ATUBISTR register. 3126 ** 02 0 2 Reserved 3127 ** 01 0 2 Outbound ATU Enable - When set, enables the outbound address translation unit. 3128 ** When cleared, disables the outbound ATU. 3129 ** 00 0 2 Reserved 3130 *********************************************************************************** 3131 */ 3132 #define ARCMSR_ATU_CONFIGURATION_REG 0x80 /*dword 0x83,0x82,0x81,0x80*/ 3133 /* 3134 *********************************************************************************** 3135 ** PCI Configuration and Status Register - PCSR 3136 ** 3137 ** The PCI Configuration and Status Register has additional bits for controlling and monitoring 3138 ** various features of the PCI bus interface. 3139 ** ----------------------------------------------------------------- 3140 ** Bit Default Description 3141 ** 31:19 0000H Reserved 3142 ** 18 0 2 Detected Address or Attribute Parity Error - set when a parity error is detected during either the address 3143 ** or attribute phase of a transaction on the PCI bus even when the ATUCMD register Parity Error 3144 ** Response bit is cleared. Set under the following conditions: 3145 ** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus (including one generated by the ATU). 3146 ** 17:16 Varies with 3147 ** external state 3148 ** of DEVSEL#, 3149 ** STOP#, and 3150 ** TRDY#, 3151 ** during 3152 ** P_RST# 3153 ** PCI-X capability - These two bits define the mode of 3154 ** the PCI bus (conventional or PCI-X) as well as the 3155 ** operating frequency in the case of PCI-X mode. 3156 ** 00 - Conventional PCI mode 3157 ** 01 - PCI-X 66 3158 ** 10 - PCI-X 100 3159 ** 11 - PCI-X 133 3160 ** As defined by the PCI-X Addendum to the PCI Local Bus Specification, 3161 ** Revision 1.0a, the operating 3162 ** mode is determined by an initialization pattern on the PCI bus during 3163 ** P_RST# assertion: 3164 ** DEVSEL# STOP# TRDY# Mode 3165 ** Deasserted Deasserted Deasserted Conventional 3166 ** Deasserted Deasserted Asserted PCI-X 66 3167 ** Deasserted Asserted Deasserted PCI-X 100 3168 ** Deasserted Asserted Asserted PCI-X 133 3169 ** All other patterns are reserved. 3170 ** 15 0 2 3171 ** Outbound Transaction Queue Busy: 3172 ** 0=Outbound Transaction Queue Empty 3173 ** 1=Outbound Transaction Queue Busy 3174 ** 14 0 2 3175 ** Inbound Transaction Queue Busy: 3176 ** 0=Inbound Transaction Queue Empty 3177 ** 1=Inbound Transaction Queue Busy 3178 ** 13 0 2 Reserved. 3179 ** 12 0 2 Discard Timer Value - This bit controls the time-out value 3180 ** for the four discard timers attached to the queues holding read data. 3181 ** A value of 0 indicates the time-out value is 2 15 clocks. 3182 ** A value of 1 indicates the time-out value is 2 10 clocks. 3183 ** 11 0 2 Reserved. 3184 ** 10 Varies with 3185 ** external state 3186 ** of M66EN 3187 ** during 3188 ** P_RST# 3189 ** Bus Operating at 66 MHz - When set, the interface has been initialized to function at 66 MHz in 3190 ** Conventional PCI mode by the assertion of M66EN during bus initialization. 3191 ** When clear, the interface 3192 ** has been initialized as a 33 MHz bus. 3193 ** NOTE: When PCSR bits 17:16 are not equal to zero, then this bit is meaningless since the 80331 is operating in PCI-X mode. 3194 ** 09 0 2 Reserved 3195 ** 08 Varies with 3196 ** external state 3197 ** of REQ64# 3198 ** during 3199 ** P_RST# 3200 ** PCI Bus 64-Bit Capable - When clear, the PCI bus interface has been 3201 ** configured as 64-bit capable by 3202 ** the assertion of REQ64# on the rising edge of P_RST#. When set, 3203 ** the PCI interface is configured as 3204 ** 32-bit only. 3205 ** 07:06 00 2 Reserved. 3206 ** 05 0 2 Reset Internal Bus - This bit controls the reset of the Intel XScale core 3207 ** and all units on the internal 3208 ** bus. In addition to the internal bus initialization, 3209 ** this bit triggers the assertion of the M_RST# pin for 3210 ** initialization of registered DIMMs. When set: 3211 ** When operating in the conventional PCI mode: 3212 ** �E All current PCI transactions being mastered by the ATU completes, 3213 ** and the ATU master interfaces 3214 ** proceeds to an idle state. No additional transactions is mastered by these units 3215 ** until the internal bus reset is complete. 3216 ** �E All current transactions being slaved by the ATU on either the PCI bus 3217 ** or the internal bus 3218 ** completes, and the ATU target interfaces proceeds to an idle state. 3219 ** All future slave transactions master aborts, 3220 ** with the exception of the completion cycle for the transaction that set the Reset 3221 ** Internal Bus bit in the PCSR. 3222 ** �E When the value of the Core Processor Reset bit in the PCSR (upon P_RST# assertion) 3223 ** is set, the Intel XScale core is held in reset when the internal bus reset is complete. 3224 ** �E The ATU ignores configuration cycles, and they appears as master aborts for: 32 3225 ** Internal Bus clocks. 3226 ** �E The 80331 hardware clears this bit after the reset operation completes. 3227 ** When operating in the PCI-X mode: 3228 ** The ATU hardware responds the same as in Conventional PCI-X mode. 3229 ** However, this may create a problem in PCI-X mode for split requests in 3230 ** that there may still be an outstanding split completion that the 3231 ** ATU is either waiting to receive (Outbound Request) or initiate 3232 ** (Inbound Read Request). For a cleaner 3233 ** internal bus reset, host software can take the following steps prior 3234 ** to asserting Reset Internal bus: 3235 ** 1. Clear the Bus Master (bit 2 of the ATUCMD) and the Memory Enable (bit 1 of the ATUCMD) bits in 3236 ** the ATUCMD. This ensures that no new transactions, either outbound or inbound are enqueued. 3237 ** 2. Wait for both the Outbound (bit 15 of the PCSR) and Inbound Read (bit 14 of the PCSR) Transaction 3238 ** queue busy bits to be clear. 3239 ** 3. Set the Reset Internal Bus bit 3240 ** As a result, the ATU hardware resets the internal bus using the same logic as in conventional mode, 3241 ** however the user is now assured that the ATU no longer has any pending inbound or outbound split 3242 ** completion transactions. 3243 ** NOTE: Since the Reset Internal Bus bit is set using an inbound configuration cycle, the user is 3244 ** guaranteed that any prior configuration cycles have properly completed since there is only a one 3245 ** deep transaction queue for configuration transaction requests. The ATU sends the appropriate 3246 ** Split Write Completion Message to the Requester prior to the onset of Internal Bus Reset. 3247 ** 04 0 2 Bus Master Indicator Enable: Provides software control for the 3248 ** Bus Master Indicator signal P_BMI used 3249 ** for external RAIDIOS logic control of private devices. Only valid when operating with the bridge and 3250 ** central resource/arbiter disabled (BRG_EN =low, ARB_EN=low). 3251 ** 03 Varies with external state of PRIVDEV during 3252 ** P_RST# 3253 ** Private Device Enable - This bit indicates the state of the reset strap which enables the private device 3254 ** control mechanism within the PCI-to-PCI Bridge SISR configuration register. 3255 ** 0=Private Device control Disabled - SISR register bits default to zero 3256 ** 1=Private Device control Enabled - SISR register bits default to one 3257 ** 02 Varies with external state of RETRY during P_RST# 3258 ** Configuration Cycle Retry - When this bit is set, the PCI interface of the 80331 responds to all 3259 ** configuration cycles with a Retry condition. When clear, the 80331 responds to the appropriate 3260 ** configuration cycles. 3261 ** The default condition for this bit is based on the external state of the RETRY pin at the rising edge of 3262 ** P_RST#. When the external state of the pin is high, the bit is set. When the external state of the pin is 3263 ** low, the bit is cleared. 3264 ** 01 Varies with external state of CORE_RST# during P_RST# 3265 ** Core Processor Reset - This bit is set to its default value by the hardware when either P_RST# is 3266 ** asserted or the Reset Internal Bus bit in PCSR is set. When this bit is set, the Intel XScale core is 3267 ** being held in reset. Software cannot set this bit. Software is required to clear this bit to deassert Intel 3268 ** XScale core reset. 3269 ** The default condition for this bit is based on the external state of the CORE_RST# pin at the rising edge 3270 ** of P_RST#. When the external state of the pin is low, the bit is set. When the external state of the pin is 3271 ** high, the bit is clear. 3272 ** 00 Varies with external state of PRIVMEM during P_RST# 3273 ** Private Memory Enable - This bit indicates the state of the reset strap which enables the private device 3274 ** control mechanism within the PCI-to-PCI Bridge SDER configuration register. 3275 ** 0=Private Memory control Disabled - SDER register bit 2 default to zero 3276 ** 1=Private Memory control Enabled - SDER register bits 2 default to one 3277 *********************************************************************************** 3278 */ 3279 #define ARCMSR_PCI_CONFIGURATION_STATUS_REG 0x84 /*dword 0x87,0x86,0x85,0x84*/ 3280 /* 3281 *********************************************************************************** 3282 ** ATU Interrupt Status Register - ATUISR 3283 ** 3284 ** The ATU Interrupt Status Register is used to notify the core processor of the source of an ATU 3285 ** interrupt. In addition, this register is written to clear the source of the interrupt to the interrupt unit 3286 ** of the 80331. All bits in this register are Read/Clear. 3287 ** Bits 4:0 are a direct reflection of bits 14:11 and bit 8 (respectively) of the ATU Status Register 3288 ** (these bits are set at the same time by hardware but need to be cleared independently). Bit 7 is set 3289 ** by an error associated with the internal bus of the 80331. Bit 8 is for software BIST. The 3290 ** conditions that result in an ATU interrupt are cleared by writing a 1 to the appropriate bits in this 3291 ** register. 3292 ** Note: Bits 4:0, and bits 15 and 13:7 can result in an interrupt being driven to the Intel XScale core. 3293 ** ----------------------------------------------------------------- 3294 ** Bit Default Description 3295 ** 31:18 0000H Reserved 3296 ** 17 0 2 VPD Address Register Updated - This bit is set when a PCI bus configuration write occurs to the VPDAR 3297 ** register. Configuration register writes to the VPDAR does NOT result in bit 15 also being set. When set, 3298 ** this bit results in the assertion of the ATU Configure Register Write Interrupt. 3299 ** 16 0 2 Reserved 3300 ** 15 0 2 ATU Configuration Write - This bit is set when a PCI bus configuration write occurs to any ATU register. 3301 ** When set, this bit results in the assertion of the ATU Configure Register Write Interrupt. 3302 ** 14 0 2 ATU Inbound Memory Window 1 Base Updated - This bit is set when a PCI bus configuration write 3303 ** occurs to either the IABAR1 register or the IAUBAR1 register. Configuration register writes to these 3304 ** registers deos NOT result in bit 15 also being set. When set, this bit results in the assertion of the ATU 3305 ** Configure Register Write Interrupt. 3306 ** 13 0 2 Initiated Split Completion Error Message - This bit is set when the device initiates a Split Completion 3307 ** Message on the PCI Bus with the Split Completion Error attribute bit set. 3308 ** 12 0 2 Received Split Completion Error Message - This bit is set when the device receives a Split Completion 3309 ** Message from the PCI Bus with the Split Completion Error attribute bit set. 3310 ** 11 0 2 Power State Transition - When the Power State Field of the ATU Power Management Control/Status 3311 ** Register is written to transition the ATU function Power State from D0 to D3, D0 to D1, or D3 to D0 and 3312 ** the ATU Power State Transition Interrupt mask bit is cleared, this bit is set. 3313 ** 10 0 2 P_SERR# Asserted - set when P_SERR# is asserted on the PCI bus by the ATU. 3314 ** 09 0 2 Detected Parity Error - set when a parity error is detected on the PCI bus even when the ATUCMD 3315 ** register��s Parity Error Response bit is cleared. Set under the following conditions: 3316 ** �E Write Data Parity Error when the ATU is a target (inbound write). 3317 ** �E Read Data Parity Error when the ATU is an initiator (outbound read). 3318 ** �E Any Address or Attribute (PCI-X Only) Parity Error on the Bus. 3319 ** 08 0 2 ATU BIST Interrupt - When set, generates the ATU BIST Start Interrupt and indicates the host processor 3320 ** has set the Start BIST bit (ATUBISTR register bit 6), when the ATU BIST interrupt is enabled (ATUCR 3321 ** register bit 3). The Intel XScale core can initiate the software BIST and store the result in ATUBISTR 3322 ** register bits 3:0. 3323 ** Configuration register writes to the ATUBISTR does NOT result in bit 15 also being set or the assertion 3324 ** of the ATU Configure Register Write Interrupt. 3325 ** 07 0 2 Internal Bus Master Abort - set when a transaction initiated by the ATU internal bus initiator interface ends in a Master-abort. 3326 ** 06:05 00 2 Reserved. 3327 ** 04 0 2 P_SERR# Detected - set when P_SERR# is detected on the PCI bus by the ATU. 3328 ** 03 0 2 PCI Master Abort - set when a transaction initiated by the ATU PCI initiator interface ends in a Master-abort. 3329 ** 02 0 2 PCI Target Abort (master) - set when a transaction initiated by the ATU PCI master interface ends in a Target-abort. 3330 ** 01 0 2 PCI Target Abort (target) - set when the ATU interface, acting as a target, terminates the transaction on the PCI bus with a target abort. 3331 ** 00 0 2 PCI Master Parity Error - Master Parity Error - The ATU interface sets this bit under the following 3332 ** conditions: 3333 ** �E The ATU asserted PERR# itself or the ATU observed PERR# asserted. 3334 ** �E And the ATU acted as the requester for the operation in which the error occurred. 3335 ** �E And the ATUCMD register��s Parity Error Response bit is set 3336 ** �E Or (PCI-X Mode Only) the ATU received a Write Data Parity Error Message 3337 ** �E And the ATUCMD register��s Parity Error Response bit is set 3338 *********************************************************************************** 3339 */ 3340 #define ARCMSR_ATU_INTERRUPT_STATUS_REG 0x88 /*dword 0x8B,0x8A,0x89,0x88*/ 3341 /* 3342 *********************************************************************************** 3343 ** ATU Interrupt Mask Register - ATUIMR 3344 ** 3345 ** The ATU Interrupt Mask Register contains the control bit to enable and disable interrupts 3346 ** generated by the ATU. 3347 ** ----------------------------------------------------------------- 3348 ** Bit Default Description 3349 ** 31:15 0 0000H Reserved 3350 ** 14 0 2 VPD Address Register Updated Mask - Controls the setting of bit 17 of the ATUISR and generation of the 3351 ** ATU Configuration Register Write interrupt when a PCI bus write occurs to the VPDAR register. 3352 ** 0=Not Masked 3353 ** 1=Masked 3354 ** 13 0 2 Reserved 3355 ** 12 0 2 Configuration Register Write Mask - Controls the setting of bit 15 of the ATUISR and generation of the 3356 ** ATU Configuration Register Write interrupt when a PCI bus write occurs to any ATU configuration register 3357 ** except those covered by mask bit 11 and bit 14 of this register, and ATU BIST enable bit 3 of the ATUCR. 3358 ** 0=Not Masked 3359 ** 1=Masked 3360 ** 11 1 2 ATU Inbound Memory Window 1 Base Updated Mask - Controls the setting of bit 14 of the ATUISR and 3361 ** generation of the ATU Configuration Register Write interrupt when a PCI bus write occurs to either the 3362 ** IABAR1 register or the IAUBAR1 register. 3363 ** 0=Not Masked 3364 ** 1=Masked 3365 ** 10 0 2 Initiated Split Completion Error Message Interrupt Mask - Controls the setting of bit 13 of the ATUISR and 3366 ** generation of the ATU Error interrupt when the ATU initiates a Split Completion Error Message. 3367 ** 0=Not Masked 3368 ** 1=Masked 3369 ** 09 0 2 Received Split Completion Error Message Interrupt Mask- Controls the setting of bit 12 of the ATUISR 3370 ** and generation of the ATU Error interrupt when a Split Completion Error Message results in bit 29 of the 3371 ** PCIXSR being set. 3372 ** 0=Not Masked 3373 ** 1=Masked 3374 ** 08 1 2 Power State Transition Interrupt Mask - Controls the setting of bit 12 of the ATUISR and generation of the 3375 ** ATU Error interrupt when ATU Power Management Control/Status Register is written to transition the 3376 ** ATU Function Power State from D0 to D3, D0 to D1, D1 to D3 or D3 to D0. 3377 ** 0=Not Masked 3378 ** 1=Masked 3379 ** 07 0 2 ATU Detected Parity Error Interrupt Mask - Controls the setting of bit 9 of the ATUISR and generation of 3380 ** the ATU Error interrupt when a parity error detected on the PCI bus that sets bit 15 of the ATUSR. 3381 ** 0=Not Masked 3382 ** 1=Masked 3383 ** 06 0 2 ATU SERR# Asserted Interrupt Mask - Controls the setting of bit 10 of the ATUISR and generation of the 3384 ** ATU Error interrupt when SERR# is asserted on the PCI interface resulting in bit 14 of the ATUSR being set. 3385 ** 0=Not Masked 3386 ** 1=Masked 3387 ** NOTE: This bit is specific to the ATU asserting SERR# and not detecting SERR# from another master. 3388 ** 05 0 2 ATU PCI Master Abort Interrupt Mask - Controls the setting of bit 3 of the ATUISR and generation of the 3389 ** ATU Error interrupt when a master abort error resulting in bit 13 of the ATUSR being set. 3390 ** 0=Not Masked 3391 ** 1=Masked 3392 ** 04 0 2 ATU PCI Target Abort (Master) Interrupt Mask- Controls the setting of bit 12 of the ATUISR and ATU Error 3393 ** generation of the interrupt when a target abort error resulting in bit 12 of the ATUSR being set 3394 ** 0=Not Masked 3395 ** 1=Masked 3396 ** 03 0 2 ATU PCI Target Abort (Target) Interrupt Mask- Controls the setting of bit 1 of the ATUISR and generation 3397 ** of the ATU Error interrupt when a target abort error resulting in bit 11 of the ATUSR being set. 3398 ** 0=Not Masked 3399 ** 1=Masked 3400 ** 02 0 2 ATU PCI Master Parity Error Interrupt Mask - Controls the setting of bit 0 of the ATUISR and generation 3401 ** of the ATU Error interrupt when a parity error resulting in bit 8 of the ATUSR being set. 3402 ** 0=Not Masked 3403 ** 1=Masked 3404 ** 01 0 2 ATU Inbound Error SERR# Enable - Controls when the ATU asserts (when enabled through the 3405 ** ATUCMD) SERR# on the PCI interface in response to a master abort on the internal bus during an 3406 ** inbound write transaction. 3407 ** 0=SERR# Not Asserted due to error 3408 ** 1=SERR# Asserted due to error 3409 ** 00 0 2 ATU ECC Target Abort Enable - Controls the ATU response on the PCI interface to a target abort (ECC 3410 ** error) from the memory controller on the internal bus. In conventional mode, this action only occurs 3411 ** during an inbound read transaction where the data phase that was target aborted on the internal bus is 3412 ** actually requested from the inbound read queue. 3413 ** 0=Disconnect with data 3414 ** (the data being up to 64 bits of 1��s) 3415 ** 1=Target Abort 3416 ** NOTE: In PCI-X Mode, The ATU initiates a Split Completion Error Message (with message class=2h - 3417 ** completer error and message index=81h - 80331 internal bus target abort) on the PCI bus, 3418 ** independent of the setting of this bit. 3419 *********************************************************************************** 3420 */ 3421 #define ARCMSR_ATU_INTERRUPT_MASK_REG 0x8C /*dword 0x8F,0x8E,0x8D,0x8C*/ 3422 /* 3423 *********************************************************************************** 3424 ** Inbound ATU Base Address Register 3 - IABAR3 3425 ** 3426 ** . The Inbound ATU Base Address Register 3 (IABAR3) together with the Inbound ATU Upper Base Address Register 3 (IAUBAR3) defines the block 3427 ** of memory addresses where the inbound translation window 3 begins. 3428 ** . The inbound ATU decodes and forwards the bus request to the 80331 internal bus with a translated address to map into 80331 local memory. 3429 ** . The IABAR3 and IAUBAR3 define the base address and describes the required memory block size. 3430 ** . Bits 31 through 12 of the IABAR3 is either read/write bits or read only with a value of 0 depending on the value located within the IALR3. 3431 ** The programmed value within the base address register must comply with the PCI programming requirements for address alignment. 3432 ** Note: 3433 ** Since IABAR3 does not appear in the standard PCI configuration header space (offsets 00H - 3CH), 3434 ** IABAR3 is not configured by the host during normal system initialization. 3435 ** Warning: 3436 ** When a non-zero value is not written to IALR3, 3437 ** the user should not set either the Prefetchable Indicator 3438 ** or the Type Indicator for 64 bit addressability. 3439 ** This is the default for IABAR3. 3440 ** Assuming a non-zero value is written to IALR3, 3441 ** the user may set the Prefetchable Indicator 3442 ** or the Type Indicator: 3443 ** a. Since non prefetchable memory windows can never be placed above the 4 Gbyte address boundary, 3444 ** when the Prefetchable Indicator is not set, 3445 ** the user should also leave the Type Indicator set for 32 bit addressability. 3446 ** This is the default for IABAR3. 3447 ** b. when the Prefetchable Indicator is set, 3448 ** the user should also set the Type Indicator for 64 bit addressability. 3449 ** ----------------------------------------------------------------- 3450 ** Bit Default Description 3451 ** 31:12 00000H Translation Base Address 3 - These bits define the actual location 3452 ** the translation function is to respond to when addressed from the PCI bus. 3453 ** 11:04 00H Reserved. 3454 ** 03 0 2 Prefetchable Indicator - When set, defines the memory space as prefetchable. 3455 ** 02:01 00 2 Type Indicator - Defines the width of the addressability for this memory window: 3456 ** 00 - Memory Window is locatable anywhere in 32 bit address space 3457 ** 10 - Memory Window is locatable anywhere in 64 bit address space 3458 ** 00 0 2 Memory Space Indicator - This bit field describes memory or I/O space base address. 3459 ** The ATU does not occupy I/O space, 3460 ** thus this bit must be zero. 3461 *********************************************************************************** 3462 */ 3463 #define ARCMSR_INBOUND_ATU_BASE_ADDRESS3_REG 0x90 /*dword 0x93,0x92,0x91,0x90*/ 3464 /* 3465 *********************************************************************************** 3466 ** Inbound ATU Upper Base Address Register 3 - IAUBAR3 3467 ** 3468 ** This register contains the upper base address when decoding PCI addresses beyond 4 GBytes. 3469 ** Together with the Translation Base Address this register defines the actual location 3470 ** the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes (for DACs). 3471 ** The programmed value within the base address register must comply with the PCI programming 3472 ** requirements for address alignment. 3473 ** Note: 3474 ** When the Type indicator of IABAR3 is set to indicate 32 bit addressability, 3475 ** the IAUBAR3 register attributes are read-only. 3476 ** This is the default for IABAR3. 3477 ** ----------------------------------------------------------------- 3478 ** Bit Default Description 3479 ** 31:0 00000H Translation Upper Base Address 3 - Together with the Translation Base Address 3 these bits define 3480 ** the actual location the translation function is to respond to when addressed from the PCI bus for addresses > 4GBytes. 3481 *********************************************************************************** 3482 */ 3483 #define ARCMSR_INBOUND_ATU_UPPER_BASE_ADDRESS3_REG 0x94 /*dword 0x97,0x96,0x95,0x94*/ 3484 /* 3485 *********************************************************************************** 3486 ** Inbound ATU Limit Register 3 - IALR3 3487 ** 3488 ** Inbound address translation for memory window 3 occurs for data transfers occurring from the PCI 3489 ** bus (originated from the PCI bus) to the 80331 internal bus. The address translation block converts 3490 ** PCI addresses to internal bus addresses. 3491 ** The inbound translation base address for inbound window 3 is specified in Section 3.10.15. When 3492 ** determining block size requirements �X as described in Section 3.10.21 �X the translation limit 3493 ** register provides the block size requirements for the base address register. The remaining registers 3494 ** used for performing address translation are discussed in Section 3.2.1.1. 3495 ** The 80331 translate value register��s programmed value must be naturally aligned with the base 3496 ** address register��s programmed value. The limit register is used as a mask; thus, the lower address 3497 ** bits programmed into the 80331 translate value register are invalid. Refer to the PCI Local Bus 3498 ** Specification, Revision 2.3 for additional information on programming base address registers. 3499 ** Bits 31 to 12 within the IALR3 have a direct effect on the IABAR3 register, bits 31 to 12, with a 3500 ** one to one correspondence. A value of 0 in a bit within the IALR3 makes the corresponding bit 3501 ** within the IABAR3 a read only bit which always returns 0. A value of 1 in a bit within the IALR3 3502 ** makes the corresponding bit within the IABAR3 read/write from PCI. Note that a consequence of 3503 ** this programming scheme is that unless a valid value exists within the IALR3, all writes to the 3504 ** IABAR3 has no effect since a value of all zeros within the IALR3 makes the IABAR3 a read only 3505 ** register. 3506 ** ----------------------------------------------------------------- 3507 ** Bit Default Description 3508 ** 31:12 00000H Inbound Translation Limit 3 - This readback value determines the memory block size required 3509 ** for the ATUs memory window 3. 3510 ** 11:00 000H Reserved 3511 *********************************************************************************** 3512 */ 3513 #define ARCMSR_INBOUND_ATU_LIMIT3_REG 0x98 /*dword 0x9B,0x9A,0x99,0x98*/ 3514 /* 3515 *********************************************************************************** 3516 ** Inbound ATU Translate Value Register 3 - IATVR3 3517 ** 3518 ** The Inbound ATU Translate Value Register 3 (IATVR3) contains the internal bus address used to 3519 ** convert PCI bus addresses. The converted address is driven on the internal bus as a result of the 3520 ** inbound ATU address translation. 3521 ** ----------------------------------------------------------------- 3522 ** Bit Default Description 3523 ** 31:12 00000H Inbound ATU Translation Value 3 - This value is used to convert the PCI address to internal bus addresses. 3524 ** This value must be 64-bit aligned on the internal bus. The default address allows the ATU to 3525 ** access the internal 80331 memory-mapped registers. 3526 ** 11:00 000H Reserved 3527 *********************************************************************************** 3528 */ 3529 #define ARCMSR_INBOUND_ATU_TRANSLATE_VALUE3_REG 0x9C /*dword 0x9F,0x9E,0x9D,0x9C*/ 3530 /* 3531 *********************************************************************************** 3532 ** Outbound Configuration Cycle Address Register - OCCAR 3533 ** 3534 ** The Outbound Configuration Cycle Address Register is used to hold the 32-bit PCI configuration 3535 ** cycle address. The Intel XScale core writes the PCI configuration cycles address which then 3536 ** enables the outbound configuration read or write. The Intel XScale core then performs a read or 3537 ** write to the Outbound Configuration Cycle Data Register to initiate the configuration cycle on the 3538 ** PCI bus. 3539 ** Note: Bits 15:11 of the configuration cycle address for Type 0 configuration cycles are defined differently 3540 ** for Conventional versus PCI-X modes. When 80331 software programs the OCCAR to initiate a 3541 ** Type 0 configuration cycle, the OCCAR should always be loaded based on the PCI-X definition for 3542 ** the Type 0 configuration cycle address. When operating in Conventional mode, the 80331 clears 3543 ** bits 15:11 of the OCCAR prior to initiating an outbound Type 0 configuration cycle. See the PCI-X 3544 ** Addendum to the PCI Local Bus Specification, Revision 1.0a for details on the two formats. 3545 ** ----------------------------------------------------------------- 3546 ** Bit Default Description 3547 ** 31:00 0000 0000H Configuration Cycle Address - These bits define the 32-bit PCI address used during an outbound 3548 ** configuration read or write cycle. 3549 *********************************************************************************** 3550 */ 3551 #define ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_ADDRESS_REG 0xA4 /*dword 0xA7,0xA6,0xA5,0xA4*/ 3552 /* 3553 *********************************************************************************** 3554 ** Outbound Configuration Cycle Data Register - OCCDR 3555 ** 3556 ** The Outbound Configuration Cycle Data Register is used to initiate a configuration read or write 3557 ** on the PCI bus. The register is logical rather than physical meaning that it is an address not a 3558 ** register. The Intel XScale core reads or writes the data registers memory-mapped address to 3559 ** initiate the configuration cycle on the PCI bus with the address found in the OCCAR. For a 3560 ** configuration write, the data is latched from the internal bus and forwarded directly to the OWQ. 3561 ** For a read, the data is returned directly from the ORQ to the Intel XScale core and is never 3562 ** actually entered into the data register (which does not physically exist). 3563 ** The OCCDR is only visible from 80331 internal bus address space and appears as a reserved value 3564 ** within the ATU configuration space. 3565 ** ----------------------------------------------------------------- 3566 ** Bit Default Description 3567 ** 31:00 0000 0000H Configuration Cycle Data - These bits define the data used during an outbound configuration read 3568 ** or write cycle. 3569 *********************************************************************************** 3570 */ 3571 #define ARCMSR_OUTBOUND_CONFIGURATION_CYCLE_DATA_REG 0xAC /*dword 0xAF,0xAE,0xAD,0xAC*/ 3572 /* 3573 *********************************************************************************** 3574 ** VPD Capability Identifier Register - VPD_CAPID 3575 ** 3576 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 3577 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 3578 ** Capability contained in that header. In the case of the 80331, this is the VPD extended capability 3579 ** with an ID of 03H as defined by the PCI Local Bus Specification, Revision 2.3. 3580 ** ----------------------------------------------------------------- 3581 ** Bit Default Description 3582 ** 07:00 03H Cap_Id - This field with its�� 03H value identifies this item in the linked list of Extended Capability 3583 ** Headers as being the VPD capability registers. 3584 *********************************************************************************** 3585 */ 3586 #define ARCMSR_VPD_CAPABILITY_IDENTIFIER_REG 0xB8 /*byte*/ 3587 /* 3588 *********************************************************************************** 3589 ** VPD Next Item Pointer Register - VPD_NXTP 3590 ** 3591 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 3592 ** Revision 2.3. This register describes the location of the next item in the function��s capability list. 3593 ** For the 80331, this the final capability list, and hence, this register is set to 00H. 3594 ** ----------------------------------------------------------------- 3595 ** Bit Default Description 3596 ** 07:00 00H Next_ Item_ Pointer - This field provides an offset into the function��s configuration space pointing to the 3597 ** next item in the function��s capability list. Since the VPD capabilities are the last in the linked list of 3598 ** extended capabilities in the 80331, the register is set to 00H. 3599 *********************************************************************************** 3600 */ 3601 #define ARCMSR_VPD_NEXT_ITEM_PTR_REG 0xB9 /*byte*/ 3602 /* 3603 *********************************************************************************** 3604 ** VPD Address Register - VPD_AR 3605 ** 3606 ** The VPD Address register (VPDAR) contains the DWORD-aligned byte address of the VPD to be 3607 ** accessed. The register is read/write and the initial value at power-up is indeterminate. 3608 ** A PCI Configuration Write to the VPDAR interrupts the Intel XScale core. Software can use 3609 ** the Flag setting to determine whether the configuration write was intended to initiate a read or 3610 ** write of the VPD through the VPD Data Register. 3611 ** ----------------------------------------------------------------- 3612 ** Bit Default Description 3613 ** 15 0 2 Flag - A flag is used to indicate when a transfer of data between the VPD Data Register and the storage 3614 ** component has completed. Please see Section 3.9, ��Vital Product Data�� on page 201 for more details on 3615 ** how the 80331 handles the data transfer. 3616 ** 14:0 0000H VPD Address - This register is written to set the DWORD-aligned byte address used to read or write 3617 ** Vital Product Data from the VPD storage component. 3618 *********************************************************************************** 3619 */ 3620 #define ARCMSR_VPD_ADDRESS_REG 0xBA /*word 0xBB,0xBA*/ 3621 /* 3622 *********************************************************************************** 3623 ** VPD Data Register - VPD_DR 3624 ** 3625 ** This register is used to transfer data between the 80331 and the VPD storage component. 3626 ** ----------------------------------------------------------------- 3627 ** Bit Default Description 3628 ** 31:00 0000H VPD Data - Four bytes are always read or written through this register to/from the VPD storage component. 3629 *********************************************************************************** 3630 */ 3631 #define ARCMSR_VPD_DATA_REG 0xBC /*dword 0xBF,0xBE,0xBD,0xBC*/ 3632 /* 3633 *********************************************************************************** 3634 ** Power Management Capability Identifier Register -PM_CAPID 3635 ** 3636 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 3637 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 3638 ** Capability contained in that header. In the case of the 80331, this is the PCI Bus Power 3639 ** Management extended capability with an ID of 01H as defined by the PCI Bus Power Management 3640 ** Interface Specification, Revision 1.1. 3641 ** ----------------------------------------------------------------- 3642 ** Bit Default Description 3643 ** 07:00 01H Cap_Id - This field with its�� 01H value identifies this item in the linked list of Extended Capability 3644 ** Headers as being the PCI Power Management Registers. 3645 *********************************************************************************** 3646 */ 3647 #define ARCMSR_POWER_MANAGEMENT_CAPABILITY_IDENTIFIER_REG 0xC0 /*byte*/ 3648 /* 3649 *********************************************************************************** 3650 ** Power Management Next Item Pointer Register - PM_NXTP 3651 ** 3652 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 3653 ** Revision 2.3. This register describes the location of the next item in the function��s capability list. 3654 ** For the 80331, the next capability (MSI capability list) is located at off-set D0H. 3655 ** ----------------------------------------------------------------- 3656 ** Bit Default Description 3657 ** 07:00 D0H Next_ Item_ Pointer - This field provides an offset into the function��s configuration space pointing to the 3658 ** next item in the function��s capability list which in the 80331 is the MSI extended capabilities header. 3659 *********************************************************************************** 3660 */ 3661 #define ARCMSR_POWER_NEXT_ITEM_PTR_REG 0xC1 /*byte*/ 3662 /* 3663 *********************************************************************************** 3664 ** Power Management Capabilities Register - PM_CAP 3665 ** 3666 ** Power Management Capabilities bits adhere to the definitions in the PCI Bus Power Management 3667 ** Interface Specification, Revision 1.1. This register is a 16-bit read-only register which provides 3668 ** information on the capabilities of the ATU function related to power management. 3669 ** ----------------------------------------------------------------- 3670 ** Bit Default Description 3671 ** 15:11 00000 2 PME_Support - This function is not capable of asserting the PME# signal in any state, since PME# 3672 ** is not supported by the 80331. 3673 ** 10 0 2 D2_Support - This bit is set to 0 2 indicating that the 80331 does not support the D2 Power Management State 3674 ** 9 1 2 D1_Support - This bit is set to 1 2 indicating that the 80331 supports the D1 Power Management State 3675 ** 8:6 000 2 Aux_Current - This field is set to 000 2 indicating that the 80331 has no current requirements for the 3676 ** 3.3Vaux signal as defined in the PCI Bus Power Management Interface Specification, Revision 1.1 3677 ** 5 0 2 DSI - This field is set to 0 2 meaning that this function requires a device specific initialization sequence 3678 ** following the transition to the D0 uninitialized state. 3679 ** 4 0 2 Reserved. 3680 ** 3 0 2 PME Clock - Since the 80331 does not support PME# signal generation this bit is cleared to 0 2 . 3681 ** 2:0 010 2 Version - Setting these bits to 010 2 means that this function complies with PCI Bus Power Management 3682 ** Interface Specification, Revision 1.1 3683 *********************************************************************************** 3684 */ 3685 #define ARCMSR_POWER_MANAGEMENT_CAPABILITY_REG 0xC2 /*word 0xC3,0xC2*/ 3686 /* 3687 *********************************************************************************** 3688 ** Power Management Control/Status Register - PM_CSR 3689 ** 3690 ** Power Management Control/Status bits adhere to the definitions in the PCI Bus Power 3691 ** Management Interface Specification, Revision 1.1. This 16-bit register is the control and status 3692 ** interface for the power management extended capability. 3693 ** ----------------------------------------------------------------- 3694 ** Bit Default Description 3695 ** 15 0 2 PME_Status - This function is not capable of asserting the PME# signal in any state, since PME## is not 3696 ** supported by the 80331. 3697 ** 14:9 00H Reserved 3698 ** 8 0 2 PME_En - This bit is hardwired to read-only 0 2 since this function does not support PME# 3699 ** generation from any power state. 3700 ** 7:2 000000 2 Reserved 3701 ** 1:0 00 2 Power State - This 2-bit field is used both to determine the current power state 3702 ** of a function and to set the function into a new power state. The definition of the values is: 3703 ** 00 2 - D0 3704 ** 01 2 - D1 3705 ** 10 2 - D2 (Unsupported) 3706 ** 11 2 - D3 hot 3707 ** The 80331 supports only the D0 and D3 hot states. 3708 ** 3709 *********************************************************************************** 3710 */ 3711 #define ARCMSR_POWER_MANAGEMENT_CONTROL_STATUS_REG 0xC4 /*word 0xC5,0xC4*/ 3712 /* 3713 *********************************************************************************** 3714 ** PCI-X Capability Identifier Register - PX_CAPID 3715 ** 3716 ** The Capability Identifier Register bits adhere to the definitions in the PCI Local Bus Specification, 3717 ** Revision 2.3. This register in the PCI Extended Capability header identifies the type of Extended 3718 ** Capability contained in that header. In the case of the 80331, this is the PCI-X extended capability with 3719 ** an ID of 07H as defined by the PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a. 3720 ** ----------------------------------------------------------------- 3721 ** Bit Default Description 3722 ** 07:00 07H Cap_Id - This field with its�� 07H value identifies this item in the linked list of Extended Capability 3723 ** Headers as being the PCI-X capability registers. 3724 *********************************************************************************** 3725 */ 3726 #define ARCMSR_PCIX_CAPABILITY_IDENTIFIER_REG 0xE0 /*byte*/ 3727 /* 3728 *********************************************************************************** 3729 ** PCI-X Next Item Pointer Register - PX_NXTP 3730 ** 3731 ** The Next Item Pointer Register bits adhere to the definitions in the PCI Local Bus Specification, 3732 ** Revision 2.3. This register describes the location of the next item in the function��s capability list. 3733 ** By default, the PCI-X capability is the last capabilities list for the 80331, thus this register defaults 3734 ** to 00H. 3735 ** However, this register may be written to B8H prior to host configuration to include the VPD 3736 ** capability located at off-set B8H. 3737 ** Warning: Writing this register to any value other than 00H (default) or B8H is not supported and may 3738 ** produce unpredictable system behavior. 3739 ** In order to guarantee that this register is written prior to host configuration, the 80331 must be 3740 ** initialized at P_RST# assertion to Retry Type 0 configuration cycles (bit 2 of PCSR). Typically, 3741 ** the Intel XScale core would be enabled to boot immediately following P_RST# assertion in 3742 ** this case (bit 1 of PCSR), as well. Please see Table 125, ��PCI Configuration and Status Register - 3743 ** PCSR�� on page 253 for more details on the 80331 initialization modes. 3744 ** ----------------------------------------------------------------- 3745 ** Bit Default Description 3746 ** 07:00 00H Next_ Item_ Pointer - This field provides an offset into the function��s configuration space pointing to the 3747 ** next item in the function��s capability list. Since the PCI-X capabilities are the last in the linked list of 3748 ** extended capabilities in the 80331, the register is set to 00H. 3749 ** However, this field may be written prior to host configuration with B8H to extend the list to include the 3750 ** VPD extended capabilities header. 3751 *********************************************************************************** 3752 */ 3753 #define ARCMSR_PCIX_NEXT_ITEM_PTR_REG 0xE1 /*byte*/ 3754 /* 3755 *********************************************************************************** 3756 ** PCI-X Command Register - PX_CMD 3757 ** 3758 ** This register controls various modes and features of ATU and Message Unit when operating in the 3759 ** PCI-X mode. 3760 ** ----------------------------------------------------------------- 3761 ** Bit Default Description 3762 ** 15:7 000000000 2 Reserved. 3763 ** 6:4 011 2 Maximum Outstanding Split Transactions - This register sets the maximum number of Split Transactions 3764 ** the device is permitted to have outstanding at one time. 3765 ** Register Maximum Outstanding 3766 ** 0 1 3767 ** 1 2 3768 ** 2 3 3769 ** 3 4 3770 ** 4 8 3771 ** 5 12 3772 ** 6 16 3773 ** 7 32 3774 ** 3:2 00 2 Maximum Memory Read Byte Count - This register sets the maximum byte count the device uses when 3775 ** initiating a Sequence with one of the burst memory read commands. 3776 ** Register Maximum Byte Count 3777 ** 0 512 3778 ** 1 1024 3779 ** 2 2048 3780 ** 3 4096 3781 ** 1 0 2 3782 ** Enable Relaxed Ordering - The 80331 does not set the relaxed ordering bit in the Requester Attributes 3783 ** of Transactions. 3784 ** 0 0 2 Data Parity Error Recovery Enable - The device driver sets this bit to enable the device to attempt to 3785 ** recover from data parity errors. When this bit is 0 and the device is in PCI-X mode, the device asserts 3786 ** SERR# (when enabled) whenever the Master Data Parity Error bit (Status register, bit 8) is set. 3787 *********************************************************************************** 3788 */ 3789 #define ARCMSR_PCIX_COMMAND_REG 0xE2 /*word 0xE3,0xE2*/ 3790 /* 3791 *********************************************************************************** 3792 ** PCI-X Status Register - PX_SR 3793 ** 3794 ** This register identifies the capabilities and current operating mode of ATU, DMAs and Message 3795 ** Unit when operating in the PCI-X mode. 3796 ** ----------------------------------------------------------------- 3797 ** Bit Default Description 3798 ** 31:30 00 2 Reserved 3799 ** 29 0 2 Received Split Completion Error Message - This bit is set when the device receives a Split Completion 3800 ** Message with the Split Completion Error attribute bit set. Once set, this bit remains set until software 3801 ** writes a 1 to this location. 3802 ** 0=no Split Completion error message received. 3803 ** 1=a Split Completion error message has been received. 3804 ** 28:26 001 2 Designed Maximum Cumulative Read Size (DMCRS) - The value of this register depends on the setting 3805 ** of the Maximum Memory Read Byte Count field of the PCIXCMD register: 3806 ** DMCRS Max ADQs Maximum Memory Read Byte Count Register Setting 3807 ** 1 16 512 (Default) 3808 ** 2 32 1024 3809 ** 2 32 2048 3810 ** 2 32 4096 3811 ** 25:23 011 2 Designed Maximum Outstanding Split Transactions - The 80331 can have up to four outstanding split transactions. 3812 ** 22:21 01 2 Designed Maximum Memory Read Byte Count - The 80331 can generate memory reads with byte counts up 3813 ** to 1024 bytes. 3814 ** 20 1 2 80331 is a complex device. 3815 ** 19 0 2 Unexpected Split Completion - This bit is set when an unexpected Split Completion with this device��s 3816 ** Requester ID is received. Once set, this bit remains set until software writes a 1 to this location. 3817 ** 0=no unexpected Split Completion has been received. 3818 ** 1=an unexpected Split Completion has been received. 3819 ** 18 0 2 Split Completion Discarded - This bit is set when the device discards a Split Completion because the 3820 ** requester would not accept it. See Section 5.4.4 of the PCI-X Addendum to the PCI Local Bus 3821 ** Specification, Revision 1.0a for details. Once set, this bit remains set until software writes a 1 to this 3822 ** location. 3823 ** 0=no Split Completion has been discarded. 3824 ** 1=a Split Completion has been discarded. 3825 ** NOTE: The 80331 does not set this bit since there is no Inbound address responding to Inbound Read 3826 ** Requests with Split Responses (Memory or Register) that has ��read side effects.�� 3827 ** 17 1 2 80331 is a 133 MHz capable device. 3828 ** 16 1 2 or P_32BITPCI# 80331 with bridge enabled (BRG_EN=1) implements the ATU with a 64-bit interface on the secondary PCI bus, 3829 ** therefore this bit is always set. 3830 ** 80331 with no bridge and central resource disabled (BRG_EN=0, ARB_EN=0), 3831 ** use this bit to identify the add-in card to the system as 64-bit or 32-bit wide via a user-configurable strap (P_32BITPCI#). 3832 ** This strap, by default, identifies the add in card based on 80331 with bridge disabled 3833 ** as 64-bit unless the user attaches the appropriate pull-down resistor to the strap. 3834 ** 0=The bus is 32 bits wide. 3835 ** 1=The bus is 64 bits wide. 3836 ** 15:8 FFH Bus Number - This register is read for diagnostic purposes only. It indicates the number of the bus 3837 ** segment for the device containing this function. The function uses this number as part of its Requester 3838 ** ID and Completer ID. For all devices other than the source bridge, each time the function is addressed 3839 ** by a Configuration Write transaction, the function must update this register with the contents of AD[7::0] 3840 ** of the attribute phase of the Configuration Write, regardless of which register in the function is 3841 ** addressed by the transaction. The function is addressed by a Configuration Write transaction when all of 3842 ** the following are true: 3843 ** 1. The transaction uses a Configuration Write command. 3844 ** 2. IDSEL is asserted during the address phase. 3845 ** 3. AD[1::0] are 00b (Type 0 configuration transaction). 3846 ** 4. AD[10::08] of the configuration address contain the appropriate function number. 3847 ** 7:3 1FH Device Number - This register is read for diagnostic purposes only. It indicates the number of the device 3848 ** containing this function, i.e., the number in the Device Number field (AD[15::11]) of the address of a 3849 ** Type 0 configuration transaction that is assigned to the device containing this function by the connection 3850 ** of the system hardware. The system must assign a device number other than 00h (00h is reserved for 3851 ** the source bridge). The function uses this number as part of its Requester ID and Completer ID. Each 3852 ** time the function is addressed by a Configuration Write transaction, the device must update this register 3853 ** with the contents of AD[15::11] of the address phase of the Configuration Write, regardless of which 3854 ** register in the function is addressed by the transaction. The function is addressed by a Configuration 3855 ** Write transaction when all of the following are true: 3856 ** 1. The transaction uses a Configuration Write command. 3857 ** 2. IDSEL is asserted during the address phase. 3858 ** 3. AD[1::0] are 00b (Type 0 configuration transaction). 3859 ** 4. AD[10::08] of the configuration address contain the appropriate function number. 3860 ** 2:0 000 2 Function Number - This register is read for diagnostic purposes only. It indicates the number of this 3861 ** function; i.e., the number in the Function Number field (AD[10::08]) of the address of a Type 0 3862 ** configuration transaction to which this function responds. The function uses this number as part of its 3863 ** Requester ID and Completer ID. 3864 ** 3865 ************************************************************************** 3866 */ 3867 #define ARCMSR_PCIX_STATUS_REG 0xE4 /*dword 0xE7,0xE6,0xE5,0xE4*/ 3868 3869 /* 3870 ************************************************************************** 3871 ** Inbound Read Transaction 3872 ** ======================================================================== 3873 ** An inbound read transaction is initiated by a PCI initiator and is targeted at either 80331 local 3874 ** memory or a 80331 memory-mapped register space. The read transaction is propagated through 3875 ** the inbound transaction queue (ITQ) and read data is returned through the inbound read queue 3876 ** (IRQ). 3877 ** When operating in the conventional PCI mode, all inbound read transactions are processed as 3878 ** delayed read transactions. When operating in the PCI-X mode, all inbound read transactions are 3879 ** processed as split transactions. The ATUs PCI interface claims the read transaction and forwards 3880 ** the read request through to the internal bus and returns the read data to the PCI bus. Data flow for 3881 ** an inbound read transaction on the PCI bus is summarized in the following statements: 3882 ** �E The ATU claims the PCI read transaction when the PCI address is within the inbound 3883 ** translation window defined by ATU Inbound Base Address Register (and Inbound Upper Base 3884 ** Address Register during DACs) and Inbound Limit Register. 3885 ** �E When operating in the conventional PCI mode, when the ITQ is currently holding transaction 3886 ** information from a previous delayed read, the current transaction information is compared to 3887 ** the previous transaction information (based on the setting of the DRC Alias bit in 3888 ** Section 3.10.39, ��ATU Configuration Register - ATUCR�� on page 252). When there is a 3889 ** match and the data is in the IRQ, return the data to the master on the PCI bus. When there is a 3890 ** match and the data is not available, a Retry is signaled with no other action taken. When there 3891 ** is not a match and when the ITQ has less than eight entries, capture the transaction 3892 ** information, signal a Retry and initiate a delayed transaction. When there is not a match and 3893 ** when the ITQ is full, then signal a Retry with no other action taken. 3894 ** �X When an address parity error is detected, the address parity response defined in 3895 ** Section 3.7 is used. 3896 ** �E When operating in the conventional PCI mode, once read data is driven onto the PCI bus from 3897 ** the IRQ, it continues until one of the following is true: 3898 ** �X The initiator completes the PCI transaction. When there is data left unread in the IRQ, the 3899 ** data is flushed. 3900 ** �X An internal bus Target Abort was detected. In this case, the QWORD associated with the 3901 ** Target Abort is never entered into the IRQ, and therefore is never returned. 3902 ** �X Target Abort or a Disconnect with Data is returned in response to the Internal Bus Error. 3903 ** �X The IRQ becomes empty. In this case, the PCI interface signals a Disconnect with data to 3904 ** the initiator on the last data word available. 3905 ** �E When operating in the PCI-X mode, when ITQ is not full, the PCI address, attribute and 3906 ** command are latched into the available ITQ and a Split Response Termination is signalled to 3907 ** the initiator. 3908 ** �E When operating in the PCI-X mode, when the transaction does not cross a 1024 byte aligned 3909 ** boundary, then the ATU waits until it receives the full byte count from the internal bus target 3910 ** before returning read data by generating the split completion transaction on the PCI-X bus. 3911 ** When the read requested crosses at least one 1024 byte boundary, then ATU completes the 3912 ** transfer by returning data in 1024 byte aligned chunks. 3913 ** �E When operating in the PCI-X mode, once a split completion transaction has started, it 3914 ** continues until one of the following is true: 3915 ** �X The requester (now the target) generates a Retry Termination, or a Disconnection at Next 3916 ** ADB (when the requester is a bridge) 3917 ** �X The byte count is satisfied. 3918 ** �X An internal bus Target Abort was detected. The ATU generates a Split Completion 3919 ** Message (message class=2h - completer error, and message index=81h - target abort) to 3920 ** inform the requester about the abnormal condition. The ITQ for this transaction is flushed. 3921 ** Refer to Section 3.7.1. 3922 ** �X An internal bus Master Abort was detected. The ATU generates a Split Completion 3923 ** Message (message class=2h - completer error, and message index=80h - Master abort) to 3924 ** inform the requester about the abnormal condition. The ITQ for this transaction is flushed. 3925 ** Refer to Section 3.7.1 3926 ** �E When operating in the conventional PCI mode, when the master inserts wait states on the PCI 3927 ** bus, the ATU PCI slave interface waits with no premature disconnects. 3928 ** �E When a data parity error occurs signified by PERR# asserted from the initiator, no action is 3929 ** taken by the target interface. Refer to Section 3.7.2.5. 3930 ** �E When operating in the conventional PCI mode, when the read on the internal bus is 3931 ** target-aborted, either a target-abort or a disconnect with data is signaled to the initiator. This is 3932 ** based on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). When set, a 3933 ** target abort is used, when clear, a disconnect is used. 3934 ** �E When operating in the PCI-X mode (with the exception of the MU queue ports at offsets 40h 3935 ** and 44h), when the transaction on the internal bus resulted in a target abort, the ATU generates 3936 ** a Split Completion Message (message class=2h - completer error, and message index=81h - 3937 ** internal bus target abort) to inform the requester about the abnormal condition. For the MU 3938 ** queue ports, the ATU returns either a target abort or a single data phase disconnect depending 3939 ** on the ATU ECC Target Abort Enable bit (bit 0 of the ATUIMR for ATU). The ITQ for this 3940 ** transaction is flushed. Refer to Section 3.7.1. 3941 ** �E When operating in the conventional PCI mode, when the transaction on the internal bus 3942 ** resulted in a master abort, the ATU returns a target abort to inform the requester about the 3943 ** abnormal condition. The ITQ for this transaction is flushed. Refer to Section 3.7.1 3944 ** �E When operating in the PCI-X mode, when the transaction on the internal bus resulted in a 3945 ** master abort, the ATU generates a Split Completion Message (message class=2h - completer 3946 ** error, and message index=80h - internal bus master abort) to inform the requester about the 3947 ** abnormal condition. The ITQ for this transaction is flushed. Refer to Section 3.7.1. 3948 ** �E When operating in the PCI-X mode, when the Split Completion transaction completes with 3949 ** either Master-Abort or Target-Abort, the requester is indicating a failure condition that 3950 ** prevents it from accepting the completion it requested. In this case, since the Split Request 3951 ** addresses a location that has no read side effects, the completer must discard the Split 3952 ** Completion and take no further action. 3953 ** The data flow for an inbound read transaction on the internal bus is summarized in the following 3954 ** statements: 3955 ** �E The ATU internal bus master interface requests the internal bus when a PCI address appears in 3956 ** an ITQ and transaction ordering has been satisfied. When operating in the PCI-X mode the 3957 ** ATU does not use the information provided by the Relax Ordering Attribute bit. That is, ATU 3958 ** always uses conventional PCI ordering rules. 3959 ** �E Once the internal bus is granted, the internal bus master interface drives the translated address 3960 ** onto the bus and wait for IB_DEVSEL#. When a Retry is signaled, the request is repeated. 3961 ** When a master abort occurs, the transaction is considered complete and a target abort is loaded 3962 ** into the associated IRQ for return to the PCI initiator (transaction is flushed once the PCI 3963 ** master has been delivered the target abort). 3964 ** �E Once the translated address is on the bus and the transaction has been accepted, the internal 3965 ** bus target starts returning data with the assertion of IB_TRDY#. Read data is continuously 3966 ** received by the IRQ until one of the following is true: 3967 ** �X The full byte count requested by the ATU read request is received. The ATU internal bus 3968 ** initiator interface performs a initiator completion in this case. 3969 ** �X When operating in the conventional PCI mode, a Target Abort is received on the internal 3970 ** bus from the internal bus target. In this case, the transaction is aborted and the PCI side is 3971 ** informed. 3972 ** �X When operating in the PCI-X mode, a Target Abort is received on the internal bus from 3973 ** the internal bus target. In this case, the transaction is aborted. The ATU generates a Split 3974 ** Completion Message (message class=2h - completer error, and message index=81h - 3975 ** target abort) on the PCI bus to inform the requester about the abnormal condition. The 3976 ** ITQ for this transaction is flushed. 3977 ** �X When operating in the conventional PCI mode, a single data phase disconnection is 3978 ** received from the internal bus target. When the data has not been received up to the next 3979 ** QWORD boundary, the ATU internal bus master interface attempts to reacquire the bus. 3980 ** When not, the bus returns to idle. 3981 ** �X When operating in the PCI-X mode, a single data phase disconnection is received from 3982 ** the internal bus target. The ATU IB initiator interface attempts to reacquire the bus to 3983 ** obtain remaining data. 3984 ** �X When operating in the conventional PCI mode, a disconnection at Next ADB is received 3985 ** from the internal bus target. The bus returns to idle. 3986 ** �X When operating in the PCI-X mode, a disconnection at Next ADB is received from the 3987 ** internal bus target. The ATU IB initiator interface attempts to reacquire the bus to obtain 3988 ** remaining data. 3989 ** To support PCI Local Bus Specification, Revision 2.0 devices, the ATU can be programmed to 3990 ** ignore the memory read command (Memory Read, Memory Read Line, and Memory Read 3991 ** Multiple) when trying to match the current inbound read transaction with data in a DRC queue 3992 ** which was read previously (DRC on target bus). When the Read Command Alias Bit in the 3993 ** ATUCR register is set, the ATU does not distinguish the read commands on transactions. For 3994 ** example, the ATU enqueues a DRR with a Memory Read Multiple command and performs the read 3995 ** on the internal bus. Some time later, a PCI master attempts a Memory Read with the same address 3996 ** as the previous Memory Read Multiple. When the Read Command Bit is set, the ATU would return 3997 ** the read data from the DRC queue and consider the Delayed Read transaction complete. When the 3998 ** Read Command bit in the ATUCR was clear, the ATU would not return data since the PCI read 3999 ** commands did not match, only the address. 4000 ************************************************************************** 4001 */ 4002 /* 4003 ************************************************************************** 4004 ** Inbound Write Transaction 4005 **======================================================================== 4006 ** An inbound write transaction is initiated by a PCI master and is targeted at either 80331 local 4007 ** memory or a 80331 memory-mapped register. 4008 ** Data flow for an inbound write transaction on the PCI bus is summarized as: 4009 ** �E The ATU claims the PCI write transaction when the PCI address is within the inbound 4010 ** translation window defined by the ATU Inbound Base Address Register (and Inbound Upper 4011 ** Base Address Register during DACs) and Inbound Limit Register. 4012 ** �E When the IWADQ has at least one address entry available and the IWQ has at least one buffer 4013 ** available, the address is captured and the first data phase is accepted. 4014 ** �E The PCI interface continues to accept write data until one of the following is true: 4015 ** �X The initiator performs a disconnect. 4016 ** �X The transaction crosses a buffer boundary. 4017 ** �E When an address parity error is detected during the address phase of the transaction, the 4018 ** address parity error mechanisms are used. Refer to Section 3.7.1 for details of the address 4019 ** parity error response. 4020 ** �E When operating in the PCI-X mode when an attribute parity error is detected, the attribute 4021 ** parity error mechanism described in Section 3.7.1 is used. 4022 ** �E When a data parity error is detected while accepting data, the slave interface sets the 4023 ** appropriate bits based on PCI specifications. No other action is taken. Refer to Section 3.7.2.6 4024 ** for details of the inbound write data parity error response. 4025 ** Once the PCI interface places a PCI address in the IWADQ, when IWQ has received data sufficient 4026 ** to cross a buffer boundary or the master disconnects on the PCI bus, the ATUs internal bus 4027 ** interface becomes aware of the inbound write. When there are additional write transactions ahead 4028 ** in the IWQ/IWADQ, the current transaction remains posted until ordering and priority have been 4029 ** satisfied (Refer to Section 3.5.3) and the transaction is attempted on the internal bus by the ATU 4030 ** internal master interface. The ATU does not insert target wait states nor do data merging on the PCI 4031 ** interface, when operating in the PCI mode. 4032 ** In the PCI-X mode memory writes are always executed as immediate transactions, while 4033 ** configuration write transactions are processed as split transactions. The ATU generates a Split 4034 ** Completion Message, (with Message class=0h - Write Completion Class and Message index = 4035 ** 00h - Write Completion Message) once a configuration write is successfully executed. 4036 ** Also, when operating in the PCI-X mode a write sequence may contain multiple write transactions. 4037 ** The ATU handles such transactions as independent transactions. 4038 ** Data flow for the inbound write transaction on the internal bus is summarized as: 4039 ** �E The ATU internal bus master requests the internal bus when IWADQ has at least one entry 4040 ** with associated data in the IWQ. 4041 ** �E When the internal bus is granted, the internal bus master interface initiates the write 4042 ** transaction by driving the translated address onto the internal bus. For details on inbound 4043 ** address translation. 4044 ** �E When IB_DEVSEL# is not returned, a master abort condition is signaled on the internal bus. 4045 ** The current transaction is flushed from the queue and SERR# may be asserted on the PCI 4046 ** interface. 4047 ** �E The ATU initiator interface asserts IB_REQ64# to attempt a 64-bit transfer. When 4048 ** IB_ACK64# is not returned, a 32-bit transfer is used. Transfers of less than 64-bits use the 4049 ** IB_C/BE[7:0]# to mask the bytes not written in the 64-bit data phase. Write data is transferred 4050 ** from the IWQ to the internal bus when data is available and the internal bus interface retains 4051 ** internal bus ownership. 4052 ** �E The internal bus interface stops transferring data from the current transaction to the internal 4053 ** bus when one of the following conditions becomes true: 4054 ** �X The internal bus initiator interface loses bus ownership. The ATU internal initiator 4055 ** terminates the transfer (initiator disconnection) at the next ADB (for the internal bus ADB 4056 ** is defined as a naturally aligned 128-byte boundary) and attempt to reacquire the bus to 4057 ** complete the delivery of remaining data using the same sequence ID but with the 4058 ** modified starting address and byte count. 4059 ** �X A Disconnect at Next ADB is signaled on the internal bus from the internal target. When 4060 ** the transaction in the IWQ completes at that ADB, the initiator returns to idle. When the 4061 ** transaction in the IWQ is not complete, the initiator attempts to reacquire the bus to 4062 ** complete the delivery of remaining data using the same sequence ID but with the 4063 ** modified starting address and byte count. 4064 ** �X A Single Data Phase Disconnect is signaled on the internal bus from the internal target. 4065 ** When the transaction in the IWQ needs only a single data phase, the master returns to idle. 4066 ** When the transaction in the IWQ is not complete, the initiator attempts to reacquire the 4067 ** bus to complete the delivery of remaining data using the same sequence ID but with the 4068 ** modified starting address and byte count. 4069 ** �X The data from the current transaction has completed (satisfaction of byte count). An 4070 ** initiator termination is performed and the bus returns to idle. 4071 ** �X A Master Abort is signaled on the internal bus. SERR# may be asserted on the PCI bus. 4072 ** Data is flushed from the IWQ. 4073 ***************************************************************** 4074 */ 4075 4076 4077 4078 /* 4079 ************************************************************************** 4080 ** Inbound Read Completions Data Parity Errors 4081 **======================================================================== 4082 ** As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode. 4083 ** When as the completer of a Split Read Request the ATU observes PERR# assertion during the split 4084 ** completion transaction, the ATU attempts to complete the transaction normally and no further 4085 ** action is taken. 4086 ************************************************************************** 4087 */ 4088 4089 /* 4090 ************************************************************************** 4091 ** Inbound Configuration Write Completion Message Data Parity Errors 4092 **======================================================================== 4093 ** As an initiator, the ATU may encounter this error condition when operating in the PCI-X mode. 4094 ** When as the completer of a Configuration (Split) Write Request the ATU observes PERR# 4095 ** assertion during the split completion transaction, the ATU attempts to complete the transaction 4096 ** normally and no further action is taken. 4097 ************************************************************************** 4098 */ 4099 4100 /* 4101 ************************************************************************** 4102 ** Inbound Read Request Data Parity Errors 4103 **===================== Immediate Data Transfer ========================== 4104 ** As a target, the ATU may encounter this error when operating in the Conventional PCI or PCI-X modes. 4105 ** Inbound read data parity errors occur when read data delivered from the IRQ is detected as having 4106 ** bad parity by the initiator of the transaction who is receiving the data. The initiator may optionally 4107 ** report the error to the system by asserting PERR#. As a target device in this scenario, no action is 4108 ** required and no error bits are set. 4109 **=====================Split Response Termination========================= 4110 ** As a target, the ATU may encounter this error when operating in the PCI-X mode. 4111 ** Inbound read data parity errors occur during the Split Response Termination. The initiator may 4112 ** optionally report the error to the system by asserting PERR#. As a target device in this scenario, no 4113 ** action is required and no error bits are set. 4114 ************************************************************************** 4115 */ 4116 4117 /* 4118 ************************************************************************** 4119 ** Inbound Write Request Data Parity Errors 4120 **======================================================================== 4121 ** As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes. 4122 ** Data parity errors occurring during write operations received by the ATU may assert PERR# on 4123 ** the PCI Bus. When an error occurs, the ATU continues accepting data until the initiator of the write 4124 ** transaction completes or a queue fill condition is reached. Specifically, the following actions with 4125 ** the given constraints are taken by the ATU: 4126 ** �E PERR# is asserted two clocks cycles (three clock cycles when operating in the PCI-X mode) 4127 ** following the data phase in which the data parity error is detected on the bus. This is only 4128 ** done when the Parity Error Response bit in the ATUCMD is set. 4129 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4130 ** actions is taken: 4131 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4132 ** Detected Parity Error bit in the ATUISR. When set, no action. 4133 *************************************************************************** 4134 */ 4135 4136 4137 /* 4138 *************************************************************************** 4139 ** Inbound Configuration Write Request 4140 ** ===================================================================== 4141 ** As a target, the ATU may encounter this error when operating in the Conventional or PCI-X modes. 4142 ** =============================================== 4143 ** Conventional PCI Mode 4144 ** =============================================== 4145 ** To allow for correct data parity calculations for delayed write transactions, the ATU delays the 4146 ** assertion of STOP# (signalling a Retry) until PAR is driven by the master. A parity error during a 4147 ** delayed write transaction (inbound configuration write cycle) can occur in any of the following 4148 ** parts of the transactions: 4149 ** �E During the initial Delayed Write Request cycle on the PCI bus when the ATU latches the 4150 ** address/command and data for delayed delivery to the internal configuration register. 4151 ** �E During the Delayed Write Completion cycle on the PCI bus when the ATU delivers the status 4152 ** of the operation back to the original master. 4153 ** The 80331 ATU PCI interface has the following responses to a delayed write parity error for 4154 ** inbound transactions during Delayed Write Request cycles with the given constraints: 4155 ** �E When the Parity Error Response bit in the ATUCMD is set, the ATU asserts TRDY# 4156 ** (disconnects with data) and two clock cycles later asserts PERR# notifying the initiator of the 4157 ** parity error. The delayed write cycle is not enqueued and forwarded to the internal bus. 4158 ** When the Parity Error Response bit in the ATUCMD is cleared, the ATU retries the 4159 ** transaction by asserting STOP# and enqueues the Delayed Write Request cycle to be 4160 ** forwarded to the internal bus. PERR# is not asserted. 4161 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4162 ** actions is taken: 4163 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4164 ** Detected Parity Error bit in the ATUISR. When set, no action. 4165 ** For the original write transaction to be completed, the initiator retries the transaction on the PCI 4166 ** bus and the ATU returns the status from the internal bus, completing the transaction. 4167 ** For the Delayed Write Completion transaction on the PCI bus where a data parity error occurs and 4168 ** therefore does not agree with the status being returned from the internal bus (i.e. status being 4169 ** returned is normal completion) the ATU performs the following actions with the given constraints: 4170 ** �E When the Parity Error Response Bit is set in the ATUCMD, the ATU asserts TRDY# 4171 ** (disconnects with data) and two clocks later asserts PERR#. The Delayed Completion cycle in 4172 ** the IDWQ remains since the data of retried command did not match the data within the queue. 4173 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4174 ** actions is taken: 4175 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4176 ** Detected Parity Error bit in the ATUISR. When set, no action. 4177 ** =================================================== 4178 ** PCI-X Mode 4179 ** =================================================== 4180 ** Data parity errors occurring during configuration write operations received by the ATU may cause 4181 ** PERR# assertion and delivery of a Split Completion Error Message on the PCI Bus. When an error 4182 ** occurs, the ATU accepts the write data and complete with a Split Response Termination. 4183 ** Specifically, the following actions with the given constraints are then taken by the ATU: 4184 ** �E When the Parity Error Response bit in the ATUCMD is set, PERR# is asserted three clocks 4185 ** cycles following the Split Response Termination in which the data parity error is detected on 4186 ** the bus. When the ATU asserts PERR#, additional actions is taken: 4187 ** �X A Split Write Data Parity Error message (with message class=2h - completer error and 4188 ** message index=01h - Split Write Data Parity Error) is initiated by the ATU on the PCI bus 4189 ** that addresses the requester of the configuration write. 4190 ** �X When the Initiated Split Completion Error Message Interrupt Mask in the ATUIMR is 4191 ** clear, set the Initiated Split Completion Error Message bit in the ATUISR. When set, no 4192 ** action. 4193 ** �X The Split Write Request is not enqueued and forwarded to the internal bus. 4194 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4195 ** actions is taken: 4196 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4197 ** Detected Parity Error bit in the ATUISR. When set, no action. 4198 ** 4199 *************************************************************************** 4200 */ 4201 4202 /* 4203 *************************************************************************** 4204 ** Split Completion Messages 4205 ** ======================================================================= 4206 ** As a target, the ATU may encounter this error when operating in the PCI-X mode. 4207 ** Data parity errors occurring during Split Completion Messages claimed by the ATU may assert 4208 ** PERR# (when enabled) or SERR# (when enabled) on the PCI Bus. When an error occurs, the 4209 ** ATU accepts the data and complete normally. Specifically, the following actions with the given 4210 ** constraints are taken by the ATU: 4211 ** �E PERR# is asserted three clocks cycles following the data phase in which the data parity error 4212 ** is detected on the bus. This is only done when the Parity Error Response bit in the ATUCMD 4213 ** is set. When the ATU asserts PERR#, additional actions is taken: 4214 ** �X The Master Parity Error bit in the ATUSR is set. 4215 ** �X When the ATU PCI Master Parity Error Interrupt Mask Bit in the ATUIMR is clear, set the 4216 ** PCI Master Parity Error bit in the ATUISR. When set, no action. 4217 ** �X When the SERR# Enable bit in the ATUCMD is set, and the Data Parity Error Recover 4218 ** Enable bit in the PCIXCMD register is clear, assert SERR#; otherwise no action is taken. 4219 ** When the ATU asserts SERR#, additional actions is taken: 4220 ** Set the SERR# Asserted bit in the ATUSR. 4221 ** When the ATU SERR# Asserted Interrupt Mask Bit in the ATUIMR is clear, set the 4222 ** SERR# Asserted bit in the ATUISR. When set, no action. 4223 ** When the ATU SERR# Detected Interrupt Enable Bit in the ATUCR is set, set the 4224 ** SERR# Detected bit in the ATUISR. When clear, no action. 4225 ** �E When the SCE bit (Split Completion Error -- bit 30 of the Completer Attributes) is set during 4226 ** the Attribute phase, the Received Split Completion Error Message bit in the PCIXSR is set. 4227 ** When the ATU sets this bit, additional actions is taken: 4228 ** �X When the ATU Received Split Completion Error Message Interrupt Mask bit in the 4229 ** ATUIMR is clear, set the Received Split Completion Error Message bit in the ATUISR. 4230 ** When set, no action. 4231 ** �E The Detected Parity Error bit in the ATUSR is set. When the ATU sets this bit, additional 4232 ** actions is taken: 4233 ** �X When the ATU Detected Parity Error Interrupt Mask bit in the ATUIMR is clear, set the 4234 ** Detected Parity Error bit in the ATUISR. When set, no action. 4235 ** �E The transaction associated with the Split Completion Message is discarded. 4236 ** �E When the discarded transaction was a read, a completion error message (with message 4237 ** class=2h - completer error and message index=82h - PCI bus read parity error) is generated on 4238 ** the internal bus of the 80331. 4239 ***************************************************************************** 4240 */ 4241 4242 4243 /* 4244 ****************************************************************************************************** 4245 ** Messaging Unit (MU) of the Intel R 80331 I/O processor (80331) 4246 ** ================================================================================================== 4247 ** The Messaging Unit (MU) transfers data between the PCI system and the 80331 4248 ** notifies the respective system when new data arrives. 4249 ** The PCI window for messaging transactions is always the first 4 Kbytes of the inbound translation. 4250 ** window defined by: 4251 ** 1.Inbound ATU Base Address Register 0 (IABAR0) 4252 ** 2.Inbound ATU Limit Register 0 (IALR0) 4253 ** All of the Messaging Unit errors are reported in the same manner as ATU errors. 4254 ** Error conditions and status can be found in : 4255 ** 1.ATUSR 4256 ** 2.ATUISR 4257 **==================================================================================================== 4258 ** Mechanism Quantity Assert PCI Interrupt Signals Generate I/O Processor Interrupt 4259 **---------------------------------------------------------------------------------------------------- 4260 ** Message Registers 2 Inbound Optional Optional 4261 ** 2 Outbound 4262 **---------------------------------------------------------------------------------------------------- 4263 ** Doorbell Registers 1 Inbound Optional Optional 4264 ** 1 Outbound 4265 **---------------------------------------------------------------------------------------------------- 4266 ** Circular Queues 4 Circular Queues Under certain conditions Under certain conditions 4267 **---------------------------------------------------------------------------------------------------- 4268 ** Index Registers 1004 32-bit Memory Locations No Optional 4269 **==================================================================================================== 4270 ** PCI Memory Map: First 4 Kbytes of the ATU Inbound PCI Address Space 4271 **==================================================================================================== 4272 ** 0000H Reserved 4273 ** 0004H Reserved 4274 ** 0008H Reserved 4275 ** 000CH Reserved 4276 **------------------------------------------------------------------------ 4277 ** 0010H Inbound Message Register 0 ] 4278 ** 0014H Inbound Message Register 1 ] 4279 ** 0018H Outbound Message Register 0 ] 4280 ** 001CH Outbound Message Register 1 ] 4 Message Registers 4281 **------------------------------------------------------------------------ 4282 ** 0020H Inbound Doorbell Register ] 4283 ** 0024H Inbound Interrupt Status Register ] 4284 ** 0028H Inbound Interrupt Mask Register ] 4285 ** 002CH Outbound Doorbell Register ] 4286 ** 0030H Outbound Interrupt Status Register ] 4287 ** 0034H Outbound Interrupt Mask Register ] 2 Doorbell Registers and 4 Interrupt Registers 4288 **------------------------------------------------------------------------ 4289 ** 0038H Reserved 4290 ** 003CH Reserved 4291 **------------------------------------------------------------------------ 4292 ** 0040H Inbound Queue Port ] 4293 ** 0044H Outbound Queue Port ] 2 Queue Ports 4294 **------------------------------------------------------------------------ 4295 ** 0048H Reserved 4296 ** 004CH Reserved 4297 **------------------------------------------------------------------------ 4298 ** 0050H ] 4299 ** : ] 4300 ** : Intel Xscale Microarchitecture Local Memory ] 4301 ** : ] 4302 ** 0FFCH ] 1004 Index Registers 4303 ******************************************************************************* 4304 */ 4305 /* 4306 ***************************************************************************** 4307 ** Theory of MU Operation 4308 ***************************************************************************** 4309 **-------------------- 4310 ** inbound_msgaddr0: 4311 ** inbound_msgaddr1: 4312 ** outbound_msgaddr0: 4313 ** outbound_msgaddr1: 4314 ** . The MU has four independent messaging mechanisms. 4315 ** There are four Message Registers that are similar to a combination of mailbox and doorbell registers. 4316 ** Each holds a 32-bit value and generates an interrupt when written. 4317 **-------------------- 4318 ** inbound_doorbell: 4319 ** outbound_doorbell: 4320 ** . The two Doorbell Registers support software interrupts. 4321 ** When a bit is set in a Doorbell Register, an interrupt is generated. 4322 **-------------------- 4323 ** inbound_queueport: 4324 ** outbound_queueport: 4325 ** 4326 ** 4327 ** . The Circular Queues support a message passing scheme that uses 4 circular queues. 4328 ** The 4 circular queues are implemented in 80331 local memory. 4329 ** Two queues are used for inbound messages and two are used for outbound messages. 4330 ** Interrupts may be generated when the queue is written. 4331 **-------------------- 4332 ** local_buffer 0x0050 ....0x0FFF 4333 ** . The Index Registers use a portion of the 80331 local memory to implement a large set of message registers. 4334 ** When one of the Index Registers is written, an interrupt is generated and the address of the register written is captured. 4335 ** Interrupt status for all interrupts is recorded in the Inbound Interrupt Status Register and the Outbound Interrupt Status Register. 4336 ** Each interrupt generated by the Messaging Unit can be masked. 4337 **-------------------- 4338 ** . Multi-DWORD PCI burst accesses are not supported by the Messaging Unit, 4339 ** with the exception of Multi-DWORD reads to the index registers. 4340 ** In Conventional mode: the MU terminates Multi-DWORD PCI transactions 4341 ** (other than index register reads) with a disconnect at the next Qword boundary, with the exception of queue ports. 4342 ** In PCI-X mode : the MU terminates a Multi-DWORD PCI read transaction with a Split Response 4343 ** and the data is returned through split completion transaction(s). 4344 ** however, when the burst request crosses into or through the range of offsets 40h to 4Ch 4345 ** (e.g., this includes the queue ports) the transaction is signaled target-abort immediately on the PCI bus. 4346 ** In PCI-X mode, Multi-DWORD PCI writes is signaled a Single-Data-Phase Disconnect 4347 ** which means that no data beyond the first Qword (Dword when the MU does not assert P_ACK64#) is written. 4348 **-------------------- 4349 ** . All registers needed to configure and control the Messaging Unit are memory-mapped registers. 4350 ** The MU uses the first 4 Kbytes of the inbound translation window in the Address Translation Unit (ATU). 4351 ** This PCI address window is used for PCI transactions that access the 80331 local memory. 4352 ** The PCI address of the inbound translation window is contained in the Inbound ATU Base Address Register. 4353 **-------------------- 4354 ** . From the PCI perspective, the Messaging Unit is part of the Address Translation Unit. 4355 ** The Messaging Unit uses the PCI configuration registers of the ATU for control and status information. 4356 ** The Messaging Unit must observe all PCI control bits in the ATU Command Register and ATU Configuration Register. 4357 ** The Messaging Unit reports all PCI errors in the ATU Status Register. 4358 **-------------------- 4359 ** . Parts of the Messaging Unit can be accessed as a 64-bit PCI device. 4360 ** The register interface, message registers, doorbell registers, 4361 ** and index registers returns a P_ACK64# in response to a P_REQ64# on the PCI interface. 4362 ** Up to 1 Qword of data can be read or written per transaction (except Index Register reads). 4363 ** The Inbound and Outbound Queue Ports are always 32-bit addresses and the MU does not assert P_ACK64# to offsets 40H and 44H. 4364 ************************************************************************** 4365 */ 4366 /* 4367 ************************************************************************** 4368 ** Message Registers 4369 ** ============================== 4370 ** . Messages can be sent and received by the 80331 through the use of the Message Registers. 4371 ** . When written, the message registers may cause an interrupt to be generated to either the Intel XScale core or the host processor. 4372 ** . Inbound messages are sent by the host processor and received by the 80331. 4373 ** Outbound messages are sent by the 80331 and received by the host processor. 4374 ** . The interrupt status for outbound messages is recorded in the Outbound Interrupt Status Register. 4375 ** Interrupt status for inbound messages is recorded in the Inbound Interrupt Status Register. 4376 ** 4377 ** Inbound Messages: 4378 ** ----------------- 4379 ** . When an inbound message register is written by an external PCI agent, an interrupt may be generated to the Intel XScale core. 4380 ** . The interrupt may be masked by the mask bits in the Inbound Interrupt Mask Register. 4381 ** . The Intel XScale core interrupt is recorded in the Inbound Interrupt Status Register. 4382 ** The interrupt causes the Inbound Message Interrupt bit to be set in the Inbound Interrupt Status Register. 4383 ** This is a Read/Clear bit that is set by the MU hardware and cleared by software. 4384 ** The interrupt is cleared when the Intel XScale core writes a value of 4385 ** 1 to the Inbound Message Interrupt bit in the Inbound Interrupt Status Register. 4386 ** ------------------------------------------------------------------------ 4387 ** Inbound Message Register - IMRx 4388 ** 4389 ** . There are two Inbound Message Registers: IMR0 and IMR1. 4390 ** . When the IMR register is written, an interrupt to the Intel XScale core may be generated. 4391 ** The interrupt is recorded in the Inbound Interrupt Status Register and may be masked 4392 ** by the Inbound Message Interrupt Mask bit in the Inbound Interrupt Mask Register. 4393 ** ----------------------------------------------------------------- 4394 ** Bit Default Description 4395 ** 31:00 0000 0000H Inbound Message - This is a 32-bit message written by an external PCI agent. 4396 ** When written, an interrupt to the Intel XScale core may be generated. 4397 ************************************************************************** 4398 */ 4399 #define ARCMSR_MU_INBOUND_MESSAGE_REG0 0x10 /*dword 0x13,0x12,0x11,0x10*/ 4400 #define ARCMSR_MU_INBOUND_MESSAGE_REG1 0x14 /*dword 0x17,0x16,0x15,0x14*/ 4401 /* 4402 ************************************************************************** 4403 ** Outbound Message Register - OMRx 4404 ** -------------------------------- 4405 ** There are two Outbound Message Registers: OMR0 and OMR1. When the OMR register is 4406 ** written, a PCI interrupt may be generated. The interrupt is recorded in the Outbound Interrupt 4407 ** Status Register and may be masked by the Outbound Message Interrupt Mask bit in the Outbound 4408 ** Interrupt Mask Register. 4409 ** 4410 ** Bit Default Description 4411 ** 31:00 00000000H Outbound Message - This is 32-bit message written by the Intel XScale core. When written, an 4412 ** interrupt may be generated on the PCI Interrupt pin determined by the ATU Interrupt Pin Register. 4413 ************************************************************************** 4414 */ 4415 #define ARCMSR_MU_OUTBOUND_MESSAGE_REG0 0x18 /*dword 0x1B,0x1A,0x19,0x18*/ 4416 #define ARCMSR_MU_OUTBOUND_MESSAGE_REG1 0x1C /*dword 0x1F,0x1E,0x1D,0x1C*/ 4417 /* 4418 ************************************************************************** 4419 ** Doorbell Registers 4420 ** ============================== 4421 ** There are two Doorbell Registers: 4422 ** Inbound Doorbell Register 4423 ** Outbound Doorbell Register 4424 ** The Inbound Doorbell Register allows external PCI agents to generate interrupts to the Intel R XScale core. 4425 ** The Outbound Doorbell Register allows the Intel R XScale core to generate a PCI interrupt. 4426 ** Both Doorbell Registers may generate interrupts whenever a bit in the register is set. 4427 ** 4428 ** Inbound Doorbells: 4429 ** ------------------ 4430 ** . When the Inbound Doorbell Register is written by an external PCI agent, an interrupt may be generated to the Intel R XScale core. 4431 ** An interrupt is generated when any of the bits in the doorbell register is written to a value of 1. 4432 ** Writing a value of 0 to any bit does not change the value of that bit and does not cause an interrupt to be generated. 4433 ** . Once a bit is set in the Inbound Doorbell Register, it cannot be cleared by any external PCI agent. 4434 ** The interrupt is recorded in the Inbound Interrupt Status Register. 4435 ** . The interrupt may be masked by the Inbound Doorbell Interrupt mask bit in the Inbound Interrupt Mask Register. 4436 ** When the mask bit is set for a particular bit, no interrupt is generated for that bit. 4437 ** The Inbound Interrupt Mask Register affects only the generation of the normal messaging unit interrupt 4438 ** and not the values written to the Inbound Doorbell Register. 4439 ** One bit in the Inbound Doorbell Register is reserved for an Error Doorbell interrupt. 4440 ** . The interrupt is cleared when the Intel R XScale core writes a value of 1 to the bits in the Inbound Doorbell Register that are set. 4441 ** Writing a value of 0 to any bit does not change the value of that bit and does not clear the interrupt. 4442 ** ------------------------------------------------------------------------ 4443 ** Inbound Doorbell Register - IDR 4444 ** 4445 ** . The Inbound Doorbell Register (IDR) is used to generate interrupts to the Intel XScale core. 4446 ** . Bit 31 is reserved for generating an Error Doorbell interrupt. 4447 ** When bit 31 is set, an Error interrupt may be generated to the Intel XScale core. 4448 ** All other bits, when set, cause the Normal Messaging Unit interrupt line of the Intel XScale core to be asserted, 4449 ** when the interrupt is not masked by the Inbound Doorbell Interrupt Mask bit in the Inbound Interrupt Mask Register. 4450 ** The bits in the IDR register can only be set by an external PCI agent and can only be cleared by the Intel XScale core. 4451 ** ------------------------------------------------------------------------ 4452 ** Bit Default Description 4453 ** 31 0 2 Error Interrupt - Generate an Error Interrupt to the Intel XScale core. 4454 ** 30:00 00000000H Normal Interrupt - When any bit is set, generate a Normal interrupt to the Intel XScale core. 4455 ** When all bits are clear, do not generate a Normal Interrupt. 4456 ************************************************************************** 4457 */ 4458 #define ARCMSR_MU_INBOUND_DOORBELL_REG 0x20 /*dword 0x23,0x22,0x21,0x20*/ 4459 /* 4460 ************************************************************************** 4461 ** Inbound Interrupt Status Register - IISR 4462 ** 4463 ** . The Inbound Interrupt Status Register (IISR) contains hardware interrupt status. 4464 ** It records the status of Intel XScale core interrupts generated by the Message Registers, Doorbell Registers, and the Circular Queues. 4465 ** All interrupts are routed to the Normal Messaging Unit interrupt input of the Intel XScale core, 4466 ** except for the Error Doorbell Interrupt and the Outbound Free Queue Full interrupt; 4467 ** these two are routed to the Messaging Unit Error interrupt input. 4468 ** The generation of interrupts recorded in the Inbound Interrupt Status Register 4469 ** may be masked by setting the corresponding bit in the Inbound Interrupt Mask Register. 4470 ** Some of the bits in this register are Read Only. 4471 ** For those bits, the interrupt must be cleared through another register. 4472 ** 4473 ** Bit Default Description 4474 ** 31:07 0000000H 0 2 Reserved 4475 ** 06 0 2 Index Register Interrupt - This bit is set by the MU hardware 4476 ** when an Index Register has been written after a PCI transaction. 4477 ** 05 0 2 Outbound Free Queue Full Interrupt - This bit is set 4478 ** when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full. 4479 ** An Error interrupt is generated for this condition. 4480 ** 04 0 2 Inbound Post Queue Interrupt - This bit is set by the MU hardware when the Inbound Post Queue has been written. 4481 ** Once cleared, an interrupt does NOT be generated 4482 ** when the head and tail pointers remain unequal (i.e. queue status is Not Empty). 4483 ** Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared, 4484 ** software must retain the information that the Inbound Post queue status is not empty. 4485 ** NOTE: This interrupt is provided with dedicated support in the 80331 Interrupt Controller. 4486 ** 03 0 2 Error Doorbell Interrupt - This bit is set when the Error Interrupt of the Inbound Doorbell Register is set. 4487 ** To clear this bit (and the interrupt), the Error Interrupt bit of the Inbound Doorbell Register must be clear. 4488 ** 02 0 2 Inbound Doorbell Interrupt - This bit is set when at least one 4489 ** Normal Interrupt bit in the Inbound Doorbell Register is set. 4490 ** To clear this bit (and the interrupt), the Normal Interrupt bits in the Inbound Doorbell Register must all be clear. 4491 ** 01 0 2 Inbound Message 1 Interrupt - This bit is set by the MU hardware when the Inbound Message 1 Register has been written. 4492 ** 00 0 2 Inbound Message 0 Interrupt - This bit is set by the MU hardware when the Inbound Message 0 Register has been written. 4493 ************************************************************************** 4494 */ 4495 #define ARCMSR_MU_INBOUND_INTERRUPT_STATUS_REG 0x24 /*dword 0x27,0x26,0x25,0x24*/ 4496 #define ARCMSR_MU_INBOUND_INDEX_INT 0x40 4497 #define ARCMSR_MU_INBOUND_QUEUEFULL_INT 0x20 4498 #define ARCMSR_MU_INBOUND_POSTQUEUE_INT 0x10 4499 #define ARCMSR_MU_INBOUND_ERROR_DOORBELL_INT 0x08 4500 #define ARCMSR_MU_INBOUND_DOORBELL_INT 0x04 4501 #define ARCMSR_MU_INBOUND_MESSAGE1_INT 0x02 4502 #define ARCMSR_MU_INBOUND_MESSAGE0_INT 0x01 4503 /* 4504 ************************************************************************** 4505 ** Inbound Interrupt Mask Register - IIMR 4506 ** 4507 ** . The Inbound Interrupt Mask Register (IIMR) provides the ability to mask Intel XScale core interrupts generated by the Messaging Unit. 4508 ** Each bit in the Mask register corresponds to an interrupt bit in the Inbound Interrupt Status Register. 4509 ** Setting or clearing bits in this register does not affect the Inbound Interrupt Status Register. 4510 ** They only affect the generation of the Intel XScale core interrupt. 4511 ** ------------------------------------------------------------------------ 4512 ** Bit Default Description 4513 ** 31:07 000000H 0 2 Reserved 4514 ** 06 0 2 Index Register Interrupt Mask - When set, this bit masks the interrupt generated by the MU hardware 4515 ** when an Index Register has been written after a PCI transaction. 4516 ** 05 0 2 Outbound Free Queue Full Interrupt Mask - When set, this bit masks the Error interrupt generated 4517 ** when the Outbound Free Head Pointer becomes equal to the Tail Pointer and the queue is full. 4518 ** 04 0 2 Inbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated 4519 ** by the MU hardware when the Inbound Post Queue has been written. 4520 ** 03 0 2 Error Doorbell Interrupt Mask - When set, this bit masks the Error Interrupt 4521 ** when the Error Interrupt bit of the Inbound Doorbell Register is set. 4522 ** 02 0 2 Inbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated 4523 ** when at least one Normal Interrupt bit in the Inbound Doorbell Register is set. 4524 ** 01 0 2 Inbound Message 1 Interrupt Mask - When set, this bit masks the Inbound Message 1 4525 ** Interrupt generated by a write to the Inbound Message 1 Register. 4526 ** 00 0 2 Inbound Message 0 Interrupt Mask - When set, 4527 ** this bit masks the Inbound Message 0 Interrupt generated by a write to the Inbound Message 0 Register. 4528 ************************************************************************** 4529 */ 4530 #define ARCMSR_MU_INBOUND_INTERRUPT_MASK_REG 0x28 /*dword 0x2B,0x2A,0x29,0x28*/ 4531 #define ARCMSR_MU_INBOUND_INDEX_INTMASKENABLE 0x40 4532 #define ARCMSR_MU_INBOUND_QUEUEFULL_INTMASKENABLE 0x20 4533 #define ARCMSR_MU_INBOUND_POSTQUEUE_INTMASKENABLE 0x10 4534 #define ARCMSR_MU_INBOUND_DOORBELL_ERROR_INTMASKENABLE 0x08 4535 #define ARCMSR_MU_INBOUND_DOORBELL_INTMASKENABLE 0x04 4536 #define ARCMSR_MU_INBOUND_MESSAGE1_INTMASKENABLE 0x02 4537 #define ARCMSR_MU_INBOUND_MESSAGE0_INTMASKENABLE 0x01 4538 /* 4539 ************************************************************************** 4540 ** Outbound Doorbell Register - ODR 4541 ** 4542 ** The Outbound Doorbell Register (ODR) allows software interrupt generation. It allows the Intel 4543 ** XScale core to generate PCI interrupts to the host processor by writing to this register. The 4544 ** generation of PCI interrupts through the Outbound Doorbell Register may be masked by setting the 4545 ** Outbound Doorbell Interrupt Mask bit in the Outbound Interrupt Mask Register. 4546 ** The Software Interrupt bits in this register can only be set by the Intel XScale core and can only 4547 ** be cleared by an external PCI agent. 4548 ** ---------------------------------------------------------------------- 4549 ** Bit Default Description 4550 ** 31 0 2 Reserved 4551 ** 30 0 2 Reserved. 4552 ** 29 0 2 Reserved 4553 ** 28 0000 0000H PCI Interrupt - When set, this bit causes the P_INTC# interrupt output 4554 ** (P_INTA# with BRG_EN and ARB_EN straps low) 4555 ** signal to be asserted or a Message-signaled Interrupt is generated (when enabled). 4556 ** When this bit is cleared, the P_INTC# interrupt output 4557 ** (P_INTA# with BRG_EN and ARB_EN straps low) 4558 ** signal is deasserted. 4559 ** 27:00 000 0000H Software Interrupts - When any bit is set the P_INTC# interrupt output 4560 ** (P_INTA# with BRG_EN and ARB_EN straps low) 4561 ** signal is asserted or a Message-signaled Interrupt is generated (when enabled). 4562 ** When all bits are cleared, the P_INTC# interrupt output (P_INTA# with BRG_EN and ARB_EN straps low) 4563 ** signal is deasserted. 4564 ************************************************************************** 4565 */ 4566 #define ARCMSR_MU_OUTBOUND_DOORBELL_REG 0x2C /*dword 0x2F,0x2E,0x2D,0x2C*/ 4567 /* 4568 ************************************************************************** 4569 ** Outbound Interrupt Status Register - OISR 4570 ** 4571 ** The Outbound Interrupt Status Register (OISR) contains hardware interrupt status. It records the 4572 ** status of PCI interrupts generated by the Message Registers, Doorbell Registers, and the Circular 4573 ** Queues. The generation of PCI interrupts recorded in the Outbound Interrupt Status Register may 4574 ** be masked by setting the corresponding bit in the Outbound Interrupt Mask Register. Some of the 4575 ** bits in this register are Read Only. For those bits, the interrupt must be cleared through another 4576 ** register. 4577 ** ---------------------------------------------------------------------- 4578 ** Bit Default Description 4579 ** 31:05 000000H 000 2 Reserved 4580 ** 04 0 2 PCI Interrupt - This bit is set when the PCI Interrupt bit (bit 28) is set in the Outbound Doorbell Register. 4581 ** To clear this bit (and the interrupt), the PCI Interrupt bit must be cleared. 4582 ** 03 0 2 Outbound Post Queue Interrupt - This bit is set when data in the prefetch buffer is valid. This bit is 4583 ** cleared when any prefetch data has been read from the Outbound Queue Port. 4584 ** 02 0 2 Outbound Doorbell Interrupt - This bit is set when at least one Software Interrupt bit in the Outbound 4585 ** Doorbell Register is set. To clear this bit (and the interrupt), the Software Interrupt bits in the Outbound 4586 ** Doorbell Register must all be clear. 4587 ** 01 0 2 Outbound Message 1 Interrupt - This bit is set by the MU when the Outbound Message 1 Register is 4588 ** written. Clearing this bit clears the interrupt. 4589 ** 00 0 2 Outbound Message 0 Interrupt - This bit is set by the MU when the Outbound Message 0 Register is 4590 ** written. Clearing this bit clears the interrupt. 4591 ************************************************************************** 4592 */ 4593 #define ARCMSR_MU_OUTBOUND_INTERRUPT_STATUS_REG 0x30 /*dword 0x33,0x32,0x31,0x30*/ 4594 #define ARCMSR_MU_OUTBOUND_PCI_INT 0x10 4595 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INT 0x08 4596 #define ARCMSR_MU_OUTBOUND_DOORBELL_INT 0x04 4597 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INT 0x02 4598 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INT 0x01 4599 /* 4600 ************************************************************************** 4601 ** Outbound Interrupt Mask Register - OIMR 4602 ** The Outbound Interrupt Mask Register (OIMR) provides the ability to mask outbound PCI 4603 ** interrupts generated by the Messaging Unit. Each bit in the mask register corresponds to a 4604 ** hardware interrupt bit in the Outbound Interrupt Status Register. When the bit is set, the PCI 4605 ** interrupt is not generated. When the bit is clear, the interrupt is allowed to be generated. 4606 ** Setting or clearing bits in this register does not affect the Outbound Interrupt Status Register. They 4607 ** only affect the generation of the PCI interrupt. 4608 ** ---------------------------------------------------------------------- 4609 ** Bit Default Description 4610 ** 31:05 000000H Reserved 4611 ** 04 0 2 PCI Interrupt Mask - When set, this bit masks the interrupt generation when the PCI Interrupt bit (bit 28) 4612 ** in the Outbound Doorbell Register is set. 4613 ** 03 0 2 Outbound Post Queue Interrupt Mask - When set, this bit masks the interrupt generated when data in 4614 ** the prefetch buffer is valid. 4615 ** 02 0 2 Outbound Doorbell Interrupt Mask - When set, this bit masks the interrupt generated by the Outbound 4616 ** Doorbell Register. 4617 ** 01 0 2 Outbound Message 1 Interrupt Mask - When set, this bit masks the Outbound Message 1 Interrupt 4618 ** generated by a write to the Outbound Message 1 Register. 4619 ** 00 0 2 Outbound Message 0 Interrupt Mask- When set, this bit masks the Outbound Message 0 Interrupt 4620 ** generated by a write to the Outbound Message 0 Register. 4621 ************************************************************************** 4622 */ 4623 #define ARCMSR_MU_OUTBOUND_INTERRUPT_MASK_REG 0x34 /*dword 0x37,0x36,0x35,0x34*/ 4624 #define ARCMSR_MU_OUTBOUND_PCI_INTMASKENABLE 0x10 4625 #define ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE 0x08 4626 #define ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE 0x04 4627 #define ARCMSR_MU_OUTBOUND_MESSAGE1_INTMASKENABLE 0x02 4628 #define ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE 0x01 4629 #define ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE 0x1F 4630 /* 4631 ************************************************************************** 4632 ** 4633 ************************************************************************** 4634 */ 4635 #define ARCMSR_MU_INBOUND_QUEUE_PORT_REG 0x40 /*dword 0x43,0x42,0x41,0x40*/ 4636 #define ARCMSR_MU_OUTBOUND_QUEUE_PORT_REG 0x44 /*dword 0x47,0x46,0x45,0x44*/ 4637 /* 4638 ************************************************************************** 4639 ** Circular Queues 4640 ** ====================================================================== 4641 ** The MU implements four circular queues. There are 2 inbound queues and 2 outbound queues. In 4642 ** this case, inbound and outbound refer to the direction of the flow of posted messages. 4643 ** Inbound messages are either: 4644 ** �E posted messages by other processors for the Intel XScale core to process or 4645 ** �E free (or empty) messages that can be reused by other processors. 4646 ** Outbound messages are either: 4647 ** �E posted messages by the Intel XScale core for other processors to process or 4648 ** �E free (or empty) messages that can be reused by the Intel XScale core. 4649 ** Therefore, free inbound messages flow away from the 80331 and free outbound messages flow toward the 80331. 4650 ** The four Circular Queues are used to pass messages in the following manner. 4651 ** . The two inbound queues are used to handle inbound messages 4652 ** and the two outbound queues are used to handle outbound messages. 4653 ** . One of the inbound queues is designated the Free queue and it contains inbound free messages. 4654 ** The other inbound queue is designated the Post queue and it contains inbound posted messages. 4655 ** Similarly, one of the outbound queues is designated the Free queue and the other outbound queue is designated the Post queue. 4656 ** 4657 ** ============================================================================================================= 4658 ** Circular Queue Summary 4659 ** _____________________________________________________________________________________________________________ 4660 ** | Queue Name | Purpose | Action on PCI Interface| 4661 ** |______________________|____________________________________________________________|_________________________| 4662 ** |Inbound Post Queue | Queue for inbound messages from other processors | Written | 4663 ** | | waiting to be processed by the 80331 | | 4664 ** |Inbound Free Queue | Queue for empty inbound messages from the 80331 | Read | 4665 ** | | available for use by other processors | | 4666 ** |Outbound Post Queue | Queue for outbound messages from the 80331 | Read | 4667 ** | | that are being posted to the other processors | | 4668 ** |Outbound Free Queue | Queue for empty outbound messages from other processors | Written | 4669 ** | | available for use by the 80331 | | 4670 ** |______________________|____________________________________________________________|_________________________| 4671 ** 4672 ** . The two inbound queues allow the host processor to post inbound messages for the 80331 in one 4673 ** queue and to receive free messages returning from the 80331. 4674 ** The host processor posts inbound messages, 4675 ** the Intel XScale core receives the posted message and when it is finished with the message, 4676 ** places it back on the inbound free queue for reuse by the host processor. 4677 ** 4678 ** The circular queues are accessed by external PCI agents through two port locations in the PCI 4679 ** address space: 4680 ** Inbound Queue Port 4681 ** and Outbound Queue Port. 4682 ** The Inbound Queue Port is used by external PCI agents to read the Inbound Free Queue and write the Inbound Post Queue. 4683 ** The Outbound Queue Port is used by external PCI agents to read the Outbound Post Queue and write the Outbound Free Queue. 4684 ** Note that a PCI transaction to the inbound or outbound queue ports with null byte enables (P_C/BE[3:0]#=1111 2 ) 4685 ** does not cause the MU hardware to increment the queue pointers. 4686 ** This is treated as when the PCI transaction did not occur. 4687 ** The Inbound and Outbound Queue Ports never respond with P_ACK64# on the PCI interface. 4688 ** ====================================================================================== 4689 ** Overview of Circular Queue Operation 4690 ** ====================================================================================== 4691 ** . The data storage for the circular queues must be provided by the 80331 local memory. 4692 ** . The base address of the circular queues is contained in the Queue Base Address Register. 4693 ** Each entry in the queue is a 32-bit data value. 4694 ** . Each read from or write to the queue may access only one queue entry. 4695 ** . Multi-DWORD accesses to the circular queues are not allowed. 4696 ** Sub-DWORD accesses are promoted to DWORD accesses. 4697 ** . Each circular queue has a head pointer and a tail pointer. 4698 ** The pointers are offsets from the Queue Base Address. 4699 ** . Writes to a queue occur at the head of the queue and reads occur from the tail. 4700 ** The head and tail pointers are incremented by either the Intel XScale core or the Messaging Unit hardware. 4701 ** Which unit maintains the pointer is determined by the writer of the queue. 4702 ** More details about the pointers are given in the queue descriptions below. 4703 ** The pointers are incremented after the queue access. 4704 ** Both pointers wrap around to the first address of the circular queue when they reach the circular queue size. 4705 ** 4706 ** Messaging Unit... 4707 ** 4708 ** The Messaging Unit generates an interrupt to the Intel XScale core or generate a PCI interrupt under certain conditions. 4709 ** . In general, when a Post queue is written, an interrupt is generated to notify the receiver that a message was posted. 4710 ** The size of each circular queue can range from 4K entries (16 Kbytes) to 64K entries (256 Kbytes). 4711 ** . All four queues must be the same size and may be contiguous. 4712 ** Therefore, the total amount of local memory needed by the circular queues ranges from 64 Kbytes to 1 Mbytes. 4713 ** The Queue size is determined by the Queue Size field in the MU Configuration Register. 4714 ** . There is one base address for all four queues. 4715 ** It is stored in the Queue Base Address Register (QBAR). 4716 ** The starting addresses of each queue is based on the Queue Base Address and the Queue Size field. 4717 ** here shows an example of how the circular queues should be set up based on the 4718 ** Intelligent I/O (I 2 O) Architecture Specification. 4719 ** Other ordering of the circular queues is possible. 4720 ** 4721 ** Queue Starting Address 4722 ** Inbound Free Queue QBAR 4723 ** Inbound Post Queue QBAR + Queue Size 4724 ** Outbound Post Queue QBAR + 2 * Queue Size 4725 ** Outbound Free Queue QBAR + 3 * Queue Size 4726 ** =================================================================================== 4727 ** Inbound Post Queue 4728 ** ------------------ 4729 ** The Inbound Post Queue holds posted messages placed there by other processors for the Intel XScale core to process. 4730 ** This queue is read from the queue tail by the Intel XScale core. It is written to the queue head by external PCI agents. 4731 ** The tail pointer is maintained by the Intel XScale core. The head pointer is maintained by the MU hardware. 4732 ** For a PCI write transaction that accesses the Inbound Queue Port, 4733 ** the MU writes the data to the local memory location address in the Inbound Post Head Pointer Register. 4734 ** When the data written to the Inbound Queue Port is written to local memory, the MU hardware increments the Inbound Post Head Pointer Register. 4735 ** An Intel XScale core interrupt may be generated when the Inbound Post Queue is written. 4736 ** The Inbound Post Queue Interrupt bit in the Inbound Interrupt Status Register indicates the interrupt status. 4737 ** The interrupt is cleared when the Inbound Post Queue Interrupt bit is cleared. 4738 ** The interrupt can be masked by the Inbound Interrupt Mask Register. 4739 ** Software must be aware of the state of the Inbound Post Queue Interrupt Mask bit to guarantee 4740 ** that the full condition is recognized by the core processor. 4741 ** In addition, to guarantee that the queue does not get overwritten, 4742 ** software must process messages from the tail of the queue before incrementing the tail pointer and clearing this interrupt. 4743 ** Once cleared, an interrupt is NOT generated when the head and tail pointers remain unequal (i.e. queue status is Not Empty). 4744 ** Only a new message posting the in the inbound queue generates a new interrupt. 4745 ** Therefore, when software leaves any unprocessed messages in the post queue when the interrupt is cleared, 4746 ** software must retain the information that the Inbound Post queue status. 4747 ** From the time that the PCI write transaction is received until the data is written 4748 ** in local memory and the Inbound Post Head Pointer Register is incremented, 4749 ** any PCI transaction that attempts to access the Inbound Post Queue Port is signalled a Retry. 4750 ** The Intel XScale core may read messages from the Inbound Post Queue 4751 ** by reading the data from the local memory location pointed to by the Inbound Post Tail Pointer Register. 4752 ** The Intel XScale core must then increment the Inbound Post Tail Pointer Register. 4753 ** When the Inbound Post Queue is full (head and tail pointers are equal and the head pointer was last updated by hardware), 4754 ** the hardware retries any PCI writes until a slot in the queue becomes available. 4755 ** A slot in the post queue becomes available by the Intel XScale core incrementing the tail pointer. 4756 ** =================================================================================== 4757 ** Inbound Free Queue 4758 ** ------------------ 4759 ** The Inbound Free Queue holds free inbound messages placed there by the Intel XScale core for other processors to use. 4760 ** This queue is read from the queue tail by external PCI agents. 4761 ** It is written to the queue head by the Intel XScale core. 4762 ** The tail pointer is maintained by the MU hardware. 4763 ** The head pointer is maintained by the Intel XScale core. 4764 ** For a PCI read transaction that accesses the Inbound Queue Port, 4765 ** the MU attempts to read the data at the local memory address in the Inbound Free Tail Pointer. 4766 ** When the queue is not empty (head and tail pointers are not equal) 4767 ** or full (head and tail pointers are equal but the head pointer was last written by software), the data is returned. 4768 ** When the queue is empty (head and tail pointers are equal and the head pointer was last updated by hardware), 4769 ** the value of -1 (FFFF.FFFFH) is returned. 4770 ** When the queue was not empty and the MU succeeded in returning the data at the tail, 4771 ** the MU hardware must increment the value in the Inbound Free Tail Pointer Register. 4772 ** To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate accesses to the Inbound Free Queue. 4773 ** The MU hardware prefetches the data at the tail of the Inbound Free Queue and load it into an internal prefetch register. 4774 ** When the PCI read access occurs, the data is read directly from the prefetch register. 4775 ** The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register 4776 ** when the head and tail pointers are equal and the queue is empty. 4777 ** In order to update the prefetch register when messages are added to the queue and it becomes non-empty, 4778 ** the prefetch mechanism automatically starts a prefetch when the prefetch register contains FFFF.FFFFH 4779 ** and the Inbound Free Head Pointer Register is written. 4780 ** The Intel XScale core needs to update the Inbound Free Head Pointer Register when it adds messages to the queue. 4781 ** A prefetch must appear atomic from the perspective of the external PCI agent. 4782 ** When a prefetch is started, any PCI transaction that attempts to access the Inbound Free Queue is signalled a Retry until the prefetch is completed. 4783 ** The Intel XScale core may place messages in the Inbound Free Queue by writing the data to the 4784 ** local memory location pointed to by the Inbound Free Head Pointer Register. 4785 ** The processor must then increment the Inbound Free Head Pointer Register. 4786 ** ================================================================================== 4787 ** Outbound Post Queue 4788 ** ------------------- 4789 ** The Outbound Post Queue holds outbound posted messages placed there by the Intel XScale 4790 ** core for other processors to process. This queue is read from the queue tail by external PCI agents. 4791 ** It is written to the queue head by the Intel XScale core. The tail pointer is maintained by the 4792 ** MU hardware. The head pointer is maintained by the Intel XScale core. 4793 ** For a PCI read transaction that accesses the Outbound Queue Port, the MU attempts to read the 4794 ** data at the local memory address in the Outbound Post Tail Pointer Register. When the queue is not 4795 ** empty (head and tail pointers are not equal) or full (head and tail pointers are equal but the head 4796 ** pointer was last written by software), the data is returned. When the queue is empty (head and tail 4797 ** pointers are equal and the head pointer was last updated by hardware), the value of -1 4798 ** (FFFF.FFFFH) is returned. When the queue was not empty and the MU succeeded in returning the 4799 ** data at the tail, the MU hardware must increment the value in the Outbound Post Tail Pointer 4800 ** Register. 4801 ** To reduce latency for the PCI read access, the MU implements a prefetch mechanism to anticipate 4802 ** accesses to the Outbound Post Queue. The MU hardware prefetches the data at the tail of the 4803 ** Outbound Post Queue and load it into an internal prefetch register. When the PCI read access 4804 ** occurs, the data is read directly from the prefetch register. 4805 ** The prefetch mechanism loads a value of -1 (FFFF.FFFFH) into the prefetch register when the head 4806 ** and tail pointers are equal and the queue is empty. In order to update the prefetch register when 4807 ** messages are added to the queue and it becomes non-empty, the prefetch mechanism automatically 4808 ** starts a prefetch when the prefetch register contains FFFF.FFFFH and the Outbound Post Head 4809 ** Pointer Register is written. The Intel XScale core needs to update the Outbound Post Head 4810 ** Pointer Register when it adds messages to the queue. 4811 ** A prefetch must appear atomic from the perspective of the external PCI agent. When a prefetch is 4812 ** started, any PCI transaction that attempts to access the Outbound Post Queue is signalled a Retry 4813 ** until the prefetch is completed. 4814 ** A PCI interrupt may be generated when data in the prefetch buffer is valid. When the prefetch 4815 ** queue is clear, no interrupt is generated. The Outbound Post Queue Interrupt bit in the Outbound 4816 ** Interrupt Status Register shall indicate the status of the prefetch buffer data and therefore the 4817 ** interrupt status. The interrupt is cleared when any prefetched data has been read from the Outbound 4818 ** Queue Port. The interrupt can be masked by the Outbound Interrupt Mask Register. 4819 ** The Intel XScale core may place messages in the Outbound Post Queue by writing the data to 4820 ** the local memory address in the Outbound Post Head Pointer Register. The processor must then 4821 ** increment the Outbound Post Head Pointer Register. 4822 ** ================================================== 4823 ** Outbound Free Queue 4824 ** ----------------------- 4825 ** The Outbound Free Queue holds free messages placed there by other processors for the Intel 4826 ** XScale core to use. This queue is read from the queue tail by the Intel XScale core. It is 4827 ** written to the queue head by external PCI agents. The tail pointer is maintained by the Intel 4828 ** XScale core. The head pointer is maintained by the MU hardware. 4829 ** For a PCI write transaction that accesses the Outbound Queue Port, the MU writes the data to the 4830 ** local memory address in the Outbound Free Head Pointer Register. When the data written to the 4831 ** Outbound Queue Port is written to local memory, the MU hardware increments the Outbound Free 4832 ** Head Pointer Register. 4833 ** When the head pointer and the tail pointer become equal and the queue is full, the MU may signal 4834 ** an interrupt to the Intel XScale core to register the queue full condition. This interrupt is 4835 ** recorded in the Inbound Interrupt Status Register. The interrupt is cleared when the Outbound Free 4836 ** Queue Full Interrupt bit is cleared and not by writing to the head or tail pointers. The interrupt can 4837 ** be masked by the Inbound Interrupt Mask Register. Software must be aware of the state of the 4838 ** Outbound Free Queue Interrupt Mask bit to guarantee that the full condition is recognized by the 4839 ** core processor. 4840 ** From the time that a PCI write transaction is received until the data is written in local memory and 4841 ** the Outbound Free Head Pointer Register is incremented, any PCI transaction that attempts to 4842 ** access the Outbound Free Queue Port is signalled a retry. 4843 ** The Intel XScale core may read messages from the Outbound Free Queue by reading the data 4844 ** from the local memory address in the Outbound Free Tail Pointer Register. The processor must 4845 ** then increment the Outbound Free Tail Pointer Register. When the Outbound Free Queue is full, 4846 ** the hardware must retry any PCI writes until a slot in the queue becomes available. 4847 ** 4848 ** ================================================================================== 4849 ** Circular Queue Summary 4850 ** ---------------------- 4851 ** ________________________________________________________________________________________________________________________________________________ 4852 ** | Queue Name | PCI Port |Generate PCI Interrupt |Generate Intel Xscale Core Interrupt|Head Pointer maintained by|Tail Pointer maintained by| 4853 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 4854 ** |Inbound Post | Inbound Queue | | | | | 4855 ** | Queue | Port | NO | Yes, when queue is written | MU hardware | Intel XScale | 4856 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 4857 ** |Inbound Free | Inbound Queue | | | | | 4858 ** | Queue | Port | NO | NO | Intel XScale | MU hardware | 4859 ** |_____________|_______________|_______________________|____________________________________|__________________________|__________________________| 4860 ** ================================================================================== 4861 ** Circular Queue Status Summary 4862 ** ---------------------- 4863 ** ____________________________________________________________________________________________________ 4864 ** | Queue Name | Queue Status | Head & Tail Pointer | Last Pointer Update | 4865 ** |_____________________|________________|_____________________|_______________________________________| 4866 ** | Inbound Post Queue | Empty | Equal | Tail pointer last updated by software | 4867 ** |_____________________|________________|_____________________|_______________________________________| 4868 ** | Inbound Free Queue | Empty | Equal | Head pointer last updated by hardware | 4869 ** |_____________________|________________|_____________________|_______________________________________| 4870 ************************************************************************** 4871 */ 4872 4873 /* 4874 ************************************************************************** 4875 ** Index Registers 4876 ** ======================== 4877 ** . The Index Registers are a set of 1004 registers that when written by an external PCI agent can generate an interrupt to the Intel XScale core. 4878 ** These registers are for inbound messages only. 4879 ** The interrupt is recorded in the Inbound Interrupt Status Register. 4880 ** The storage for the Index Registers is allocated from the 80331 local memory. 4881 ** PCI write accesses to the Index Registers write the data to local memory. 4882 ** PCI read accesses to the Index Registers read the data from local memory. 4883 ** . The local memory used for the Index Registers ranges from Inbound ATU Translate Value Register + 050H 4884 ** to Inbound ATU Translate Value Register + FFFH. 4885 ** . The address of the first write access is stored in the Index Address Register. 4886 ** This register is written during the earliest write access and provides a means to determine which Index Register was written. 4887 ** Once updated by the MU, the Index Address Register is not updated until the Index Register 4888 ** Interrupt bit in the Inbound Interrupt Status Register is cleared. 4889 ** . When the interrupt is cleared, the Index Address Register is re-enabled and stores the address of the next Index Register write access. 4890 ** Writes by the Intel XScale core to the local memory used by the Index Registers 4891 ** does not cause an interrupt and does not update the Index Address Register. 4892 ** . The index registers can be accessed with Multi-DWORD reads and single QWORD aligned writes. 4893 ************************************************************************** 4894 */ 4895 /* 4896 ************************************************************************** 4897 ** Messaging Unit Internal Bus Memory Map 4898 ** ======================================= 4899 ** Internal Bus Address___Register Description (Name)____________________|_PCI Configuration Space Register Number_ 4900 ** FFFF E300H reserved | 4901 ** .. .. | 4902 ** FFFF E30CH reserved | 4903 ** FFFF E310H Inbound Message Register 0 | Available through 4904 ** FFFF E314H Inbound Message Register 1 | ATU Inbound Translation Window 4905 ** FFFF E318H Outbound Message Register 0 | 4906 ** FFFF E31CH Outbound Message Register 1 | or 4907 ** FFFF E320H Inbound Doorbell Register | 4908 ** FFFF E324H Inbound Interrupt Status Register | must translate PCI address to 4909 ** FFFF E328H Inbound Interrupt Mask Register | the Intel Xscale Core 4910 ** FFFF E32CH Outbound Doorbell Register | Memory-Mapped Address 4911 ** FFFF E330H Outbound Interrupt Status Register | 4912 ** FFFF E334H Outbound Interrupt Mask Register | 4913 ** ______________________________________________________________________|________________________________________ 4914 ** FFFF E338H reserved | 4915 ** FFFF E33CH reserved | 4916 ** FFFF E340H reserved | 4917 ** FFFF E344H reserved | 4918 ** FFFF E348H reserved | 4919 ** FFFF E34CH reserved | 4920 ** FFFF E350H MU Configuration Register | 4921 ** FFFF E354H Queue Base Address Register | 4922 ** FFFF E358H reserved | 4923 ** FFFF E35CH reserved | must translate PCI address to 4924 ** FFFF E360H Inbound Free Head Pointer Register | the Intel Xscale Core 4925 ** FFFF E364H Inbound Free Tail Pointer Register | Memory-Mapped Address 4926 ** FFFF E368H Inbound Post Head pointer Register | 4927 ** FFFF E36CH Inbound Post Tail Pointer Register | 4928 ** FFFF E370H Outbound Free Head Pointer Register | 4929 ** FFFF E374H Outbound Free Tail Pointer Register | 4930 ** FFFF E378H Outbound Post Head pointer Register | 4931 ** FFFF E37CH Outbound Post Tail Pointer Register | 4932 ** FFFF E380H Index Address Register | 4933 ** FFFF E384H reserved | 4934 ** .. .. | 4935 ** FFFF E3FCH reserved | 4936 ** ______________________________________________________________________|_______________________________________ 4937 ************************************************************************** 4938 */ 4939 /* 4940 ************************************************************************** 4941 ** MU Configuration Register - MUCR FFFF.E350H 4942 ** 4943 ** . The MU Configuration Register (MUCR) contains the Circular Queue Enable bit and the size of one Circular Queue. 4944 ** . The Circular Queue Enable bit enables or disables the Circular Queues. 4945 ** The Circular Queues are disabled at reset to allow the software to initialize the head 4946 ** and tail pointer registers before any PCI accesses to the Queue Ports. 4947 ** . Each Circular Queue may range from 4 K entries (16 Kbytes) to 64 K entries (256 Kbytes) and there are four Circular Queues. 4948 ** ------------------------------------------------------------------------ 4949 ** Bit Default Description 4950 ** 31:06 000000H 00 2 Reserved 4951 ** 05:01 00001 2 Circular Queue Size - This field determines the size of each Circular Queue. 4952 ** All four queues are the same size. 4953 ** �E 00001 2 - 4K Entries (16 Kbytes) 4954 ** �E 00010 2 - 8K Entries (32 Kbytes) 4955 ** �E 00100 2 - 16K Entries (64 Kbytes) 4956 ** �E 01000 2 - 32K Entries (128 Kbytes) 4957 ** �E 10000 2 - 64K Entries (256 Kbytes) 4958 ** 00 0 2 Circular Queue Enable - This bit enables or disables the Circular Queues. When clear the Circular 4959 ** Queues are disabled, however the MU accepts PCI accesses to the Circular Queue Ports but ignores 4960 ** the data for Writes and return FFFF.FFFFH for Reads. Interrupts are not generated to the core when 4961 ** disabled. When set, the Circular Queues are fully enabled. 4962 ************************************************************************** 4963 */ 4964 #define ARCMSR_MU_CONFIGURATION_REG 0xFFFFE350 4965 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE64K 0x0020 4966 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE32K 0x0010 4967 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE16K 0x0008 4968 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE8K 0x0004 4969 #define ARCMSR_MU_CIRCULAR_QUEUE_SIZE4K 0x0002 4970 #define ARCMSR_MU_CIRCULAR_QUEUE_ENABLE 0x0001 /*0:disable 1:enable*/ 4971 /* 4972 ************************************************************************** 4973 ** Queue Base Address Register - QBAR 4974 ** 4975 ** . The Queue Base Address Register (QBAR) contains the local memory address of the Circular Queues. 4976 ** The base address is required to be located on a 1 Mbyte address boundary. 4977 ** . All Circular Queue head and tail pointers are based on the QBAR. 4978 ** When the head and tail pointer registers are read, the Queue Base Address is returned in the upper 12 bits. 4979 ** Writing to the upper 12 bits of the head and tail pointer registers does not affect the Queue Base Address or Queue Base Address Register. 4980 ** Warning: 4981 ** The QBAR must designate a range allocated to the 80331 DDR SDRAM interface 4982 ** ------------------------------------------------------------------------ 4983 ** Bit Default Description 4984 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 4985 ** 19:00 00000H Reserved 4986 ************************************************************************** 4987 */ 4988 #define ARCMSR_MU_QUEUE_BASE_ADDRESS_REG 0xFFFFE354 4989 /* 4990 ************************************************************************** 4991 ** Inbound Free Head Pointer Register - IFHPR 4992 ** 4993 ** . The Inbound Free Head Pointer Register (IFHPR) contains the local memory offset from 4994 ** the Queue Base Address of the head pointer for the Inbound Free Queue. 4995 ** The Head Pointer must be aligned on a DWORD address boundary. 4996 ** When read, the Queue Base Address is provided in the upper 12 bits of the register. 4997 ** Writes to the upper 12 bits of the register are ignored. 4998 ** This register is maintained by software. 4999 ** ------------------------------------------------------------------------ 5000 ** Bit Default Description 5001 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5002 ** 19:02 0000H 00 2 Inbound Free Head Pointer - Local memory offset of the head pointer for the Inbound Free Queue. 5003 ** 01:00 00 2 Reserved 5004 ************************************************************************** 5005 */ 5006 #define ARCMSR_MU_INBOUND_FREE_HEAD_PTR_REG 0xFFFFE360 5007 /* 5008 ************************************************************************** 5009 ** Inbound Free Tail Pointer Register - IFTPR 5010 ** 5011 ** . The Inbound Free Tail Pointer Register (IFTPR) contains the local memory offset from the Queue 5012 ** Base Address of the tail pointer for the Inbound Free Queue. The Tail Pointer must be aligned on a 5013 ** DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 5014 ** of the register. Writes to the upper 12 bits of the register are ignored. 5015 ** ------------------------------------------------------------------------ 5016 ** Bit Default Description 5017 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5018 ** 19:02 0000H 00 2 Inbound Free Tail Pointer - Local memory offset of the tail pointer for the Inbound Free Queue. 5019 ** 01:00 00 2 Reserved 5020 ************************************************************************** 5021 */ 5022 #define ARCMSR_MU_INBOUND_FREE_TAIL_PTR_REG 0xFFFFE364 5023 /* 5024 ************************************************************************** 5025 ** Inbound Post Head Pointer Register - IPHPR 5026 ** 5027 ** . The Inbound Post Head Pointer Register (IPHPR) contains the local memory offset from the Queue 5028 ** Base Address of the head pointer for the Inbound Post Queue. The Head Pointer must be aligned on 5029 ** a DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 5030 ** of the register. Writes to the upper 12 bits of the register are ignored. 5031 ** ------------------------------------------------------------------------ 5032 ** Bit Default Description 5033 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5034 ** 19:02 0000H 00 2 Inbound Post Head Pointer - Local memory offset of the head pointer for the Inbound Post Queue. 5035 ** 01:00 00 2 Reserved 5036 ************************************************************************** 5037 */ 5038 #define ARCMSR_MU_INBOUND_POST_HEAD_PTR_REG 0xFFFFE368 5039 /* 5040 ************************************************************************** 5041 ** Inbound Post Tail Pointer Register - IPTPR 5042 ** 5043 ** . The Inbound Post Tail Pointer Register (IPTPR) contains the local memory offset from the Queue 5044 ** Base Address of the tail pointer for the Inbound Post Queue. The Tail Pointer must be aligned on a 5045 ** DWORD address boundary. When read, the Queue Base Address is provided in the upper 12 bits 5046 ** of the register. Writes to the upper 12 bits of the register are ignored. 5047 ** ------------------------------------------------------------------------ 5048 ** Bit Default Description 5049 ** 31:20 000H Queue Base Address - Local memory address of the circular queues. 5050 ** 19:02 0000H 00 2 Inbound Post Tail Pointer - Local memory offset of the tail pointer for the Inbound Post Queue. 5051 ** 01:00 00 2 Reserved 5052 ************************************************************************** 5053 */ 5054 #define ARCMSR_MU_INBOUND_POST_TAIL_PTR_REG 0xFFFFE36C 5055 /* 5056 ************************************************************************** 5057 ** Index Address Register - IAR 5058 ** 5059 ** . The Index Address Register (IAR) contains the offset of the least recently accessed Index Register. 5060 ** It is written by the MU when the Index Registers are written by a PCI agent. 5061 ** The register is not updated until the Index Interrupt bit in the Inbound Interrupt Status Register is cleared. 5062 ** . The local memory address of the Index Register least recently accessed is computed 5063 ** by adding the Index Address Register to the Inbound ATU Translate Value Register. 5064 ** ------------------------------------------------------------------------ 5065 ** Bit Default Description 5066 ** 31:12 000000H Reserved 5067 ** 11:02 00H 00 2 Index Address - is the local memory offset of the Index Register written (050H to FFCH) 5068 ** 01:00 00 2 Reserved 5069 ************************************************************************** 5070 */ 5071 #define ARCMSR_MU_LOCAL_MEMORY_INDEX_REG 0xFFFFE380 /*1004 dwords 0x0050....0x0FFC, 4016 bytes 0x0050...0x0FFF*/ 5072 /* 5073 ********************************************************************************************************** 5074 ** RS-232 Interface for Areca Raid Controller 5075 ** The low level command interface is exclusive with VT100 terminal 5076 ** -------------------------------------------------------------------- 5077 ** 1. Sequence of command execution 5078 ** -------------------------------------------------------------------- 5079 ** (A) Header : 3 bytes sequence (0x5E, 0x01, 0x61) 5080 ** (B) Command block : variable length of data including length, command code, data and checksum byte 5081 ** (C) Return data : variable length of data 5082 ** -------------------------------------------------------------------- 5083 ** 2. Command block 5084 ** -------------------------------------------------------------------- 5085 ** (A) 1st byte : command block length (low byte) 5086 ** (B) 2nd byte : command block length (high byte) 5087 ** note ..command block length shouldn't > 2040 bytes, length excludes these two bytes 5088 ** (C) 3rd byte : command code 5089 ** (D) 4th and following bytes : variable length data bytes depends on command code 5090 ** (E) last byte : checksum byte (sum of 1st byte until last data byte) 5091 ** -------------------------------------------------------------------- 5092 ** 3. Command code and associated data 5093 ** -------------------------------------------------------------------- 5094 ** The following are command code defined in raid controller Command code 0x10--0x1? are used for system level management, 5095 ** no password checking is needed and should be implemented in separate well controlled utility and not for end user access. 5096 ** Command code 0x20--0x?? always check the password, password must be entered to enable these command. 5097 ** enum 5098 ** { 5099 ** GUI_SET_SERIAL=0x10, 5100 ** GUI_SET_VENDOR, 5101 ** GUI_SET_MODEL, 5102 ** GUI_IDENTIFY, 5103 ** GUI_CHECK_PASSWORD, 5104 ** GUI_LOGOUT, 5105 ** GUI_HTTP, 5106 ** GUI_SET_ETHERNET_ADDR, 5107 ** GUI_SET_LOGO, 5108 ** GUI_POLL_EVENT, 5109 ** GUI_GET_EVENT, 5110 ** GUI_GET_HW_MONITOR, 5111 ** 5112 ** // GUI_QUICK_CREATE=0x20, (function removed) 5113 ** GUI_GET_INFO_R=0x20, 5114 ** GUI_GET_INFO_V, 5115 ** GUI_GET_INFO_P, 5116 ** GUI_GET_INFO_S, 5117 ** GUI_CLEAR_EVENT, 5118 ** 5119 ** GUI_MUTE_BEEPER=0x30, 5120 ** GUI_BEEPER_SETTING, 5121 ** GUI_SET_PASSWORD, 5122 ** GUI_HOST_INTERFACE_MODE, 5123 ** GUI_REBUILD_PRIORITY, 5124 ** GUI_MAX_ATA_MODE, 5125 ** GUI_RESET_CONTROLLER, 5126 ** GUI_COM_PORT_SETTING, 5127 ** GUI_NO_OPERATION, 5128 ** GUI_DHCP_IP, 5129 ** 5130 ** GUI_CREATE_PASS_THROUGH=0x40, 5131 ** GUI_MODIFY_PASS_THROUGH, 5132 ** GUI_DELETE_PASS_THROUGH, 5133 ** GUI_IDENTIFY_DEVICE, 5134 ** 5135 ** GUI_CREATE_RAIDSET=0x50, 5136 ** GUI_DELETE_RAIDSET, 5137 ** GUI_EXPAND_RAIDSET, 5138 ** GUI_ACTIVATE_RAIDSET, 5139 ** GUI_CREATE_HOT_SPARE, 5140 ** GUI_DELETE_HOT_SPARE, 5141 ** 5142 ** GUI_CREATE_VOLUME=0x60, 5143 ** GUI_MODIFY_VOLUME, 5144 ** GUI_DELETE_VOLUME, 5145 ** GUI_START_CHECK_VOLUME, 5146 ** GUI_STOP_CHECK_VOLUME 5147 ** }; 5148 ** 5149 ** Command description : 5150 ** 5151 ** GUI_SET_SERIAL : Set the controller serial# 5152 ** byte 0,1 : length 5153 ** byte 2 : command code 0x10 5154 ** byte 3 : password length (should be 0x0f) 5155 ** byte 4-0x13 : should be "ArEcATecHnoLogY" 5156 ** byte 0x14--0x23 : Serial number string (must be 16 bytes) 5157 ** GUI_SET_VENDOR : Set vendor string for the controller 5158 ** byte 0,1 : length 5159 ** byte 2 : command code 0x11 5160 ** byte 3 : password length (should be 0x08) 5161 ** byte 4-0x13 : should be "ArEcAvAr" 5162 ** byte 0x14--0x3B : vendor string (must be 40 bytes) 5163 ** GUI_SET_MODEL : Set the model name of the controller 5164 ** byte 0,1 : length 5165 ** byte 2 : command code 0x12 5166 ** byte 3 : password length (should be 0x08) 5167 ** byte 4-0x13 : should be "ArEcAvAr" 5168 ** byte 0x14--0x1B : model string (must be 8 bytes) 5169 ** GUI_IDENTIFY : Identify device 5170 ** byte 0,1 : length 5171 ** byte 2 : command code 0x13 5172 ** return "Areca RAID Subsystem " 5173 ** GUI_CHECK_PASSWORD : Verify password 5174 ** byte 0,1 : length 5175 ** byte 2 : command code 0x14 5176 ** byte 3 : password length 5177 ** byte 4-0x?? : user password to be checked 5178 ** GUI_LOGOUT : Logout GUI (force password checking on next command) 5179 ** byte 0,1 : length 5180 ** byte 2 : command code 0x15 5181 ** GUI_HTTP : HTTP interface (reserved for Http proxy service)(0x16) 5182 ** 5183 ** GUI_SET_ETHERNET_ADDR : Set the ethernet MAC address 5184 ** byte 0,1 : length 5185 ** byte 2 : command code 0x17 5186 ** byte 3 : password length (should be 0x08) 5187 ** byte 4-0x13 : should be "ArEcAvAr" 5188 ** byte 0x14--0x19 : Ethernet MAC address (must be 6 bytes) 5189 ** GUI_SET_LOGO : Set logo in HTTP 5190 ** byte 0,1 : length 5191 ** byte 2 : command code 0x18 5192 ** byte 3 : Page# (0/1/2/3) (0xff --> clear OEM logo) 5193 ** byte 4/5/6/7 : 0x55/0xaa/0xa5/0x5a 5194 ** byte 8 : TITLE.JPG data (each page must be 2000 bytes) 5195 ** note .... page0 1st 2 byte must be actual length of the JPG file 5196 ** GUI_POLL_EVENT : Poll If Event Log Changed 5197 ** byte 0,1 : length 5198 ** byte 2 : command code 0x19 5199 ** GUI_GET_EVENT : Read Event 5200 ** byte 0,1 : length 5201 ** byte 2 : command code 0x1a 5202 ** byte 3 : Event Page (0:1st page/1/2/3:last page) 5203 ** GUI_GET_HW_MONITOR : Get HW monitor data 5204 ** byte 0,1 : length 5205 ** byte 2 : command code 0x1b 5206 ** byte 3 : # of FANs(example 2) 5207 ** byte 4 : # of Voltage sensor(example 3) 5208 ** byte 5 : # of temperature sensor(example 2) 5209 ** byte 6 : # of power 5210 ** byte 7/8 : Fan#0 (RPM) 5211 ** byte 9/10 : Fan#1 5212 ** byte 11/12 : Voltage#0 original value in *1000 5213 ** byte 13/14 : Voltage#0 value 5214 ** byte 15/16 : Voltage#1 org 5215 ** byte 17/18 : Voltage#1 5216 ** byte 19/20 : Voltage#2 org 5217 ** byte 21/22 : Voltage#2 5218 ** byte 23 : Temp#0 5219 ** byte 24 : Temp#1 5220 ** byte 25 : Power indicator (bit0 : power#0, bit1 : power#1) 5221 ** byte 26 : UPS indicator 5222 ** GUI_QUICK_CREATE : Quick create raid/volume set 5223 ** byte 0,1 : length 5224 ** byte 2 : command code 0x20 5225 ** byte 3/4/5/6 : raw capacity 5226 ** byte 7 : raid level 5227 ** byte 8 : stripe size 5228 ** byte 9 : spare 5229 ** byte 10/11/12/13: device mask (the devices to create raid/volume) 5230 ** This function is removed, application like to implement quick create function 5231 ** need to use GUI_CREATE_RAIDSET and GUI_CREATE_VOLUMESET function. 5232 ** GUI_GET_INFO_R : Get Raid Set Information 5233 ** byte 0,1 : length 5234 ** byte 2 : command code 0x20 5235 ** byte 3 : raidset# 5236 ** 5237 ** typedef struct sGUI_RAIDSET 5238 ** { 5239 ** BYTE grsRaidSetName[16]; 5240 ** DWORD grsCapacity; 5241 ** DWORD grsCapacityX; 5242 ** DWORD grsFailMask; 5243 ** BYTE grsDevArray[32]; 5244 ** BYTE grsMemberDevices; 5245 ** BYTE grsNewMemberDevices; 5246 ** BYTE grsRaidState; 5247 ** BYTE grsVolumes; 5248 ** BYTE grsVolumeList[16]; 5249 ** BYTE grsRes1; 5250 ** BYTE grsRes2; 5251 ** BYTE grsRes3; 5252 ** BYTE grsFreeSegments; 5253 ** DWORD grsRawStripes[8]; 5254 ** DWORD grsRes4; 5255 ** DWORD grsRes5; // Total to 128 bytes 5256 ** DWORD grsRes6; // Total to 128 bytes 5257 ** } sGUI_RAIDSET, *pGUI_RAIDSET; 5258 ** GUI_GET_INFO_V : Get Volume Set Information 5259 ** byte 0,1 : length 5260 ** byte 2 : command code 0x21 5261 ** byte 3 : volumeset# 5262 ** 5263 ** typedef struct sGUI_VOLUMESET 5264 ** { 5265 ** BYTE gvsVolumeName[16]; // 16 5266 ** DWORD gvsCapacity; 5267 ** DWORD gvsCapacityX; 5268 ** DWORD gvsFailMask; 5269 ** DWORD gvsStripeSize; 5270 ** DWORD gvsNewFailMask; 5271 ** DWORD gvsNewStripeSize; 5272 ** DWORD gvsVolumeStatus; 5273 ** DWORD gvsProgress; // 32 5274 ** sSCSI_ATTR gvsScsi; 5275 ** BYTE gvsMemberDisks; 5276 ** BYTE gvsRaidLevel; // 8 5277 ** 5278 ** BYTE gvsNewMemberDisks; 5279 ** BYTE gvsNewRaidLevel; 5280 ** BYTE gvsRaidSetNumber; 5281 ** BYTE gvsRes0; // 4 5282 ** BYTE gvsRes1[4]; // 64 bytes 5283 ** } sGUI_VOLUMESET, *pGUI_VOLUMESET; 5284 ** 5285 ** GUI_GET_INFO_P : Get Physical Drive Information 5286 ** byte 0,1 : length 5287 ** byte 2 : command code 0x22 5288 ** byte 3 : drive # (from 0 to max-channels - 1) 5289 ** 5290 ** typedef struct sGUI_PHY_DRV 5291 ** { 5292 ** BYTE gpdModelName[40]; 5293 ** BYTE gpdSerialNumber[20]; 5294 ** BYTE gpdFirmRev[8]; 5295 ** DWORD gpdCapacity; 5296 ** DWORD gpdCapacityX; // Reserved for expansion 5297 ** BYTE gpdDeviceState; 5298 ** BYTE gpdPioMode; 5299 ** BYTE gpdCurrentUdmaMode; 5300 ** BYTE gpdUdmaMode; 5301 ** BYTE gpdDriveSelect; 5302 ** BYTE gpdRaidNumber; // 0xff if not belongs to a raid set 5303 ** sSCSI_ATTR gpdScsi; 5304 ** BYTE gpdReserved[40]; // Total to 128 bytes 5305 ** } sGUI_PHY_DRV, *pGUI_PHY_DRV; 5306 ** 5307 ** GUI_GET_INFO_S : Get System Information 5308 ** byte 0,1 : length 5309 ** byte 2 : command code 0x23 5310 ** 5311 ** typedef struct sCOM_ATTR 5312 ** { 5313 ** BYTE comBaudRate; 5314 ** BYTE comDataBits; 5315 ** BYTE comStopBits; 5316 ** BYTE comParity; 5317 ** BYTE comFlowControl; 5318 ** } sCOM_ATTR, *pCOM_ATTR; 5319 ** 5320 ** typedef struct sSYSTEM_INFO 5321 ** { 5322 ** BYTE gsiVendorName[40]; 5323 ** BYTE gsiSerialNumber[16]; 5324 ** BYTE gsiFirmVersion[16]; 5325 ** BYTE gsiBootVersion[16]; 5326 ** BYTE gsiMbVersion[16]; 5327 ** BYTE gsiModelName[8]; 5328 ** BYTE gsiLocalIp[4]; 5329 ** BYTE gsiCurrentIp[4]; 5330 ** DWORD gsiTimeTick; 5331 ** DWORD gsiCpuSpeed; 5332 ** DWORD gsiICache; 5333 ** DWORD gsiDCache; 5334 ** DWORD gsiScache; 5335 ** DWORD gsiMemorySize; 5336 ** DWORD gsiMemorySpeed; 5337 ** DWORD gsiEvents; 5338 ** BYTE gsiMacAddress[6]; 5339 ** BYTE gsiDhcp; 5340 ** BYTE gsiBeeper; 5341 ** BYTE gsiChannelUsage; 5342 ** BYTE gsiMaxAtaMode; 5343 ** BYTE gsiSdramEcc; // 1:if ECC enabled 5344 ** BYTE gsiRebuildPriority; 5345 ** sCOM_ATTR gsiComA; // 5 bytes 5346 ** sCOM_ATTR gsiComB; // 5 bytes 5347 ** BYTE gsiIdeChannels; 5348 ** BYTE gsiScsiHostChannels; 5349 ** BYTE gsiIdeHostChannels; 5350 ** BYTE gsiMaxVolumeSet; 5351 ** BYTE gsiMaxRaidSet; 5352 ** BYTE gsiEtherPort; // 1:if ether net port supported 5353 ** BYTE gsiRaid6Engine; // 1:Raid6 engine supported 5354 ** BYTE gsiRes[75]; 5355 ** } sSYSTEM_INFO, *pSYSTEM_INFO; 5356 ** 5357 ** GUI_CLEAR_EVENT : Clear System Event 5358 ** byte 0,1 : length 5359 ** byte 2 : command code 0x24 5360 ** 5361 ** GUI_MUTE_BEEPER : Mute current beeper 5362 ** byte 0,1 : length 5363 ** byte 2 : command code 0x30 5364 ** 5365 ** GUI_BEEPER_SETTING : Disable beeper 5366 ** byte 0,1 : length 5367 ** byte 2 : command code 0x31 5368 ** byte 3 : 0->disable, 1->enable 5369 ** 5370 ** GUI_SET_PASSWORD : Change password 5371 ** byte 0,1 : length 5372 ** byte 2 : command code 0x32 5373 ** byte 3 : pass word length ( must <= 15 ) 5374 ** byte 4 : password (must be alpha-numerical) 5375 ** 5376 ** GUI_HOST_INTERFACE_MODE : Set host interface mode 5377 ** byte 0,1 : length 5378 ** byte 2 : command code 0x33 5379 ** byte 3 : 0->Independent, 1->cluster 5380 ** 5381 ** GUI_REBUILD_PRIORITY : Set rebuild priority 5382 ** byte 0,1 : length 5383 ** byte 2 : command code 0x34 5384 ** byte 3 : 0/1/2/3 (low->high) 5385 ** 5386 ** GUI_MAX_ATA_MODE : Set maximum ATA mode to be used 5387 ** byte 0,1 : length 5388 ** byte 2 : command code 0x35 5389 ** byte 3 : 0/1/2/3 (133/100/66/33) 5390 ** 5391 ** GUI_RESET_CONTROLLER : Reset Controller 5392 ** byte 0,1 : length 5393 ** byte 2 : command code 0x36 5394 ** *Response with VT100 screen (discard it) 5395 ** 5396 ** GUI_COM_PORT_SETTING : COM port setting 5397 ** byte 0,1 : length 5398 ** byte 2 : command code 0x37 5399 ** byte 3 : 0->COMA (term port), 1->COMB (debug port) 5400 ** byte 4 : 0/1/2/3/4/5/6/7 (1200/2400/4800/9600/19200/38400/57600/115200) 5401 ** byte 5 : data bit (0:7 bit, 1:8 bit : must be 8 bit) 5402 ** byte 6 : stop bit (0:1, 1:2 stop bits) 5403 ** byte 7 : parity (0:none, 1:off, 2:even) 5404 ** byte 8 : flow control (0:none, 1:xon/xoff, 2:hardware => must use none) 5405 ** 5406 ** GUI_NO_OPERATION : No operation 5407 ** byte 0,1 : length 5408 ** byte 2 : command code 0x38 5409 ** 5410 ** GUI_DHCP_IP : Set DHCP option and local IP address 5411 ** byte 0,1 : length 5412 ** byte 2 : command code 0x39 5413 ** byte 3 : 0:dhcp disabled, 1:dhcp enabled 5414 ** byte 4/5/6/7 : IP address 5415 ** 5416 ** GUI_CREATE_PASS_THROUGH : Create pass through disk 5417 ** byte 0,1 : length 5418 ** byte 2 : command code 0x40 5419 ** byte 3 : device # 5420 ** byte 4 : scsi channel (0/1) 5421 ** byte 5 : scsi id (0-->15) 5422 ** byte 6 : scsi lun (0-->7) 5423 ** byte 7 : tagged queue (1 : enabled) 5424 ** byte 8 : cache mode (1 : enabled) 5425 ** byte 9 : max speed (0/1/2/3/4, async/20/40/80/160 for scsi) 5426 ** (0/1/2/3/4, 33/66/100/133/150 for ide ) 5427 ** 5428 ** GUI_MODIFY_PASS_THROUGH : Modify pass through disk 5429 ** byte 0,1 : length 5430 ** byte 2 : command code 0x41 5431 ** byte 3 : device # 5432 ** byte 4 : scsi channel (0/1) 5433 ** byte 5 : scsi id (0-->15) 5434 ** byte 6 : scsi lun (0-->7) 5435 ** byte 7 : tagged queue (1 : enabled) 5436 ** byte 8 : cache mode (1 : enabled) 5437 ** byte 9 : max speed (0/1/2/3/4, async/20/40/80/160 for scsi) 5438 ** (0/1/2/3/4, 33/66/100/133/150 for ide ) 5439 ** 5440 ** GUI_DELETE_PASS_THROUGH : Delete pass through disk 5441 ** byte 0,1 : length 5442 ** byte 2 : command code 0x42 5443 ** byte 3 : device# to be deleted 5444 ** 5445 ** GUI_IDENTIFY_DEVICE : Identify Device 5446 ** byte 0,1 : length 5447 ** byte 2 : command code 0x43 5448 ** byte 3 : Flash Method(0:flash selected, 1:flash not selected) 5449 ** byte 4/5/6/7 : IDE device mask to be flashed 5450 ** note .... no response data available 5451 ** 5452 ** GUI_CREATE_RAIDSET : Create Raid Set 5453 ** byte 0,1 : length 5454 ** byte 2 : command code 0x50 5455 ** byte 3/4/5/6 : device mask 5456 ** byte 7-22 : raidset name (if byte 7 == 0:use default) 5457 ** 5458 ** GUI_DELETE_RAIDSET : Delete Raid Set 5459 ** byte 0,1 : length 5460 ** byte 2 : command code 0x51 5461 ** byte 3 : raidset# 5462 ** 5463 ** GUI_EXPAND_RAIDSET : Expand Raid Set 5464 ** byte 0,1 : length 5465 ** byte 2 : command code 0x52 5466 ** byte 3 : raidset# 5467 ** byte 4/5/6/7 : device mask for expansion 5468 ** byte 8/9/10 : (8:0 no change, 1 change, 0xff:terminate, 9:new raid level,10:new stripe size 0/1/2/3/4/5->4/8/16/32/64/128K ) 5469 ** byte 11/12/13 : repeat for each volume in the raidset .... 5470 ** 5471 ** GUI_ACTIVATE_RAIDSET : Activate incomplete raid set 5472 ** byte 0,1 : length 5473 ** byte 2 : command code 0x53 5474 ** byte 3 : raidset# 5475 ** 5476 ** GUI_CREATE_HOT_SPARE : Create hot spare disk 5477 ** byte 0,1 : length 5478 ** byte 2 : command code 0x54 5479 ** byte 3/4/5/6 : device mask for hot spare creation 5480 ** 5481 ** GUI_DELETE_HOT_SPARE : Delete hot spare disk 5482 ** byte 0,1 : length 5483 ** byte 2 : command code 0x55 5484 ** byte 3/4/5/6 : device mask for hot spare deletion 5485 ** 5486 ** GUI_CREATE_VOLUME : Create volume set 5487 ** byte 0,1 : length 5488 ** byte 2 : command code 0x60 5489 ** byte 3 : raidset# 5490 ** byte 4-19 : volume set name (if byte4 == 0, use default) 5491 ** byte 20-27 : volume capacity (blocks) 5492 ** byte 28 : raid level 5493 ** byte 29 : stripe size (0/1/2/3/4/5->4/8/16/32/64/128K) 5494 ** byte 30 : channel 5495 ** byte 31 : ID 5496 ** byte 32 : LUN 5497 ** byte 33 : 1 enable tag 5498 ** byte 34 : 1 enable cache 5499 ** byte 35 : speed (0/1/2/3/4->async/20/40/80/160 for scsi) 5500 ** (0/1/2/3/4->33/66/100/133/150 for IDE ) 5501 ** byte 36 : 1 to select quick init 5502 ** 5503 ** GUI_MODIFY_VOLUME : Modify volume Set 5504 ** byte 0,1 : length 5505 ** byte 2 : command code 0x61 5506 ** byte 3 : volumeset# 5507 ** byte 4-19 : new volume set name (if byte4 == 0, not change) 5508 ** byte 20-27 : new volume capacity (reserved) 5509 ** byte 28 : new raid level 5510 ** byte 29 : new stripe size (0/1/2/3/4/5->4/8/16/32/64/128K) 5511 ** byte 30 : new channel 5512 ** byte 31 : new ID 5513 ** byte 32 : new LUN 5514 ** byte 33 : 1 enable tag 5515 ** byte 34 : 1 enable cache 5516 ** byte 35 : speed (0/1/2/3/4->async/20/40/80/160 for scsi) 5517 ** (0/1/2/3/4->33/66/100/133/150 for IDE ) 5518 ** 5519 ** GUI_DELETE_VOLUME : Delete volume set 5520 ** byte 0,1 : length 5521 ** byte 2 : command code 0x62 5522 ** byte 3 : volumeset# 5523 ** 5524 ** GUI_START_CHECK_VOLUME : Start volume consistency check 5525 ** byte 0,1 : length 5526 ** byte 2 : command code 0x63 5527 ** byte 3 : volumeset# 5528 ** 5529 ** GUI_STOP_CHECK_VOLUME : Stop volume consistency check 5530 ** byte 0,1 : length 5531 ** byte 2 : command code 0x64 5532 ** --------------------------------------------------------------------- 5533 ** 4. Returned data 5534 ** --------------------------------------------------------------------- 5535 ** (A) Header : 3 bytes sequence (0x5E, 0x01, 0x61) 5536 ** (B) Length : 2 bytes (low byte 1st, excludes length and checksum byte) 5537 ** (C) status or data : 5538 ** <1> If length == 1 ==> 1 byte status code 5539 ** #define GUI_OK 0x41 5540 ** #define GUI_RAIDSET_NOT_NORMAL 0x42 5541 ** #define GUI_VOLUMESET_NOT_NORMAL 0x43 5542 ** #define GUI_NO_RAIDSET 0x44 5543 ** #define GUI_NO_VOLUMESET 0x45 5544 ** #define GUI_NO_PHYSICAL_DRIVE 0x46 5545 ** #define GUI_PARAMETER_ERROR 0x47 5546 ** #define GUI_UNSUPPORTED_COMMAND 0x48 5547 ** #define GUI_DISK_CONFIG_CHANGED 0x49 5548 ** #define GUI_INVALID_PASSWORD 0x4a 5549 ** #define GUI_NO_DISK_SPACE 0x4b 5550 ** #define GUI_CHECKSUM_ERROR 0x4c 5551 ** #define GUI_PASSWORD_REQUIRED 0x4d 5552 ** <2> If length > 1 ==> data block returned from controller and the contents depends on the command code 5553 ** (E) Checksum : checksum of length and status or data byte 5554 ************************************************************************** 5555 */ 5556