1 /* 2 ***************************************************************************************** 3 ** O.S : FreeBSD 4 ** FILE NAME : arcmsr.c 5 ** BY : Erich Chen, Ching Huang 6 ** Description: SCSI RAID Device Driver for 7 ** ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x) SATA/SAS RAID HOST Adapter 8 ** ARCMSR RAID Host adapter 9 ** [RAID controller:INTEL 331(PCI-X) 341(PCI-EXPRESS) chip set] 10 ****************************************************************************************** 11 ************************************************************************ 12 ** 13 ** Copyright (C) 2002 - 2010, Areca Technology Corporation All rights reserved. 14 ** 15 ** Redistribution and use in source and binary forms, with or without 16 ** modification, are permitted provided that the following conditions 17 ** are met: 18 ** 1. Redistributions of source code must retain the above copyright 19 ** notice, this list of conditions and the following disclaimer. 20 ** 2. Redistributions in binary form must reproduce the above copyright 21 ** notice, this list of conditions and the following disclaimer in the 22 ** documentation and/or other materials provided with the distribution. 23 ** 3. The name of the author may not be used to endorse or promote products 24 ** derived from this software without specific prior written permission. 25 ** 26 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 27 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 28 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 29 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 30 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT 31 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 32 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 33 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 34 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 35 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 36 ************************************************************************** 37 ** History 38 ** 39 ** REV# DATE NAME DESCRIPTION 40 ** 1.00.00.00 03/31/2004 Erich Chen First release 41 ** 1.20.00.02 11/29/2004 Erich Chen bug fix with arcmsr_bus_reset when PHY error 42 ** 1.20.00.03 04/19/2005 Erich Chen add SATA 24 Ports adapter type support 43 ** clean unused function 44 ** 1.20.00.12 09/12/2005 Erich Chen bug fix with abort command handling, 45 ** firmware version check 46 ** and firmware update notify for hardware bug fix 47 ** handling if none zero high part physical address 48 ** of srb resource 49 ** 1.20.00.13 08/18/2006 Erich Chen remove pending srb and report busy 50 ** add iop message xfer 51 ** with scsi pass-through command 52 ** add new device id of sas raid adapters 53 ** code fit for SPARC64 & PPC 54 ** 1.20.00.14 02/05/2007 Erich Chen bug fix for incorrect ccb_h.status report 55 ** and cause g_vfs_done() read write error 56 ** 1.20.00.15 10/10/2007 Erich Chen support new RAID adapter type ARC120x 57 ** 1.20.00.16 10/10/2009 Erich Chen Bug fix for RAID adapter type ARC120x 58 ** bus_dmamem_alloc() with BUS_DMA_ZERO 59 ** 1.20.00.17 07/15/2010 Ching Huang Added support ARC1880 60 ** report CAM_DEV_NOT_THERE instead of CAM_SEL_TIMEOUT when device failed, 61 ** prevent cam_periph_error removing all LUN devices of one Target id 62 ** for any one LUN device failed 63 ** 1.20.00.18 10/14/2010 Ching Huang Fixed "inquiry data fails comparion at DV1 step" 64 ** 10/25/2010 Ching Huang Fixed bad range input in bus_alloc_resource for ADAPTER_TYPE_B 65 ** 1.20.00.19 11/11/2010 Ching Huang Fixed arcmsr driver prevent arcsas support for Areca SAS HBA ARC13x0 66 ** 1.20.00.20 12/08/2010 Ching Huang Avoid calling atomic_set_int function 67 ** 1.20.00.21 02/08/2011 Ching Huang Implement I/O request timeout 68 ** 02/14/2011 Ching Huang Modified pktRequestCount 69 ** 1.20.00.21 03/03/2011 Ching Huang if a command timeout, then wait its ccb back before free it 70 ** 1.20.00.22 07/04/2011 Ching Huang Fixed multiple MTX panic 71 ** 1.20.00.23 10/28/2011 Ching Huang Added TIMEOUT_DELAY in case of too many HDDs need to start 72 ** 1.20.00.23 11/08/2011 Ching Huang Added report device transfer speed 73 ** 1.20.00.23 01/30/2012 Ching Huang Fixed Request requeued and Retrying command 74 ** 1.20.00.24 06/11/2012 Ching Huang Fixed return sense data condition 75 ** 1.20.00.25 08/17/2012 Ching Huang Fixed hotplug device no function on type A adapter 76 ** 1.20.00.26 12/14/2012 Ching Huang Added support ARC1214 77 ****************************************************************************************** 78 */ 79 80 #include <sys/cdefs.h> 81 __FBSDID("$FreeBSD$"); 82 83 #if 0 84 #define ARCMSR_DEBUG1 1 85 #endif 86 #include <sys/param.h> 87 #include <sys/systm.h> 88 #include <sys/malloc.h> 89 #include <sys/kernel.h> 90 #include <sys/bus.h> 91 #include <sys/queue.h> 92 #include <sys/stat.h> 93 #include <sys/devicestat.h> 94 #include <sys/kthread.h> 95 #include <sys/module.h> 96 #include <sys/proc.h> 97 #include <sys/lock.h> 98 #include <sys/sysctl.h> 99 #include <sys/poll.h> 100 #include <sys/ioccom.h> 101 #include <vm/vm.h> 102 #include <vm/vm_param.h> 103 #include <vm/pmap.h> 104 105 #include <isa/rtc.h> 106 107 #include <machine/bus.h> 108 #include <machine/resource.h> 109 #include <machine/atomic.h> 110 #include <sys/conf.h> 111 #include <sys/rman.h> 112 113 #include <cam/cam.h> 114 #include <cam/cam_ccb.h> 115 #include <cam/cam_sim.h> 116 #include <cam/cam_periph.h> 117 #include <cam/cam_xpt_periph.h> 118 #include <cam/cam_xpt_sim.h> 119 #include <cam/cam_debug.h> 120 #include <cam/scsi/scsi_all.h> 121 #include <cam/scsi/scsi_message.h> 122 /* 123 ************************************************************************** 124 ************************************************************************** 125 */ 126 #if __FreeBSD_version >= 500005 127 #include <sys/selinfo.h> 128 #include <sys/mutex.h> 129 #include <sys/endian.h> 130 #include <dev/pci/pcivar.h> 131 #include <dev/pci/pcireg.h> 132 #else 133 #include <sys/select.h> 134 #include <pci/pcivar.h> 135 #include <pci/pcireg.h> 136 #endif 137 138 #if !defined(CAM_NEW_TRAN_CODE) && __FreeBSD_version >= 700025 139 #define CAM_NEW_TRAN_CODE 1 140 #endif 141 142 #if __FreeBSD_version > 500000 143 #define arcmsr_callout_init(a) callout_init(a, /*mpsafe*/1); 144 #else 145 #define arcmsr_callout_init(a) callout_init(a); 146 #endif 147 148 #define ARCMSR_DRIVER_VERSION "Driver Version 1.20.00.26 2012-12-14" 149 #include <dev/arcmsr/arcmsr.h> 150 /* 151 ************************************************************************** 152 ************************************************************************** 153 */ 154 static void arcmsr_free_srb(struct CommandControlBlock *srb); 155 static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb); 156 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb); 157 static int arcmsr_probe(device_t dev); 158 static int arcmsr_attach(device_t dev); 159 static int arcmsr_detach(device_t dev); 160 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg); 161 static void arcmsr_iop_parking(struct AdapterControlBlock *acb); 162 static int arcmsr_shutdown(device_t dev); 163 static void arcmsr_interrupt(struct AdapterControlBlock *acb); 164 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb); 165 static void arcmsr_free_resource(struct AdapterControlBlock *acb); 166 static void arcmsr_bus_reset(struct AdapterControlBlock *acb); 167 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb); 168 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb); 169 static void arcmsr_iop_init(struct AdapterControlBlock *acb); 170 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb); 171 static void arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, struct QBUFFER *prbuffer); 172 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb); 173 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb); 174 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag); 175 static void arcmsr_iop_reset(struct AdapterControlBlock *acb); 176 static void arcmsr_report_sense_info(struct CommandControlBlock *srb); 177 static void arcmsr_build_srb(struct CommandControlBlock *srb, bus_dma_segment_t *dm_segs, u_int32_t nseg); 178 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb); 179 static int arcmsr_resume(device_t dev); 180 static int arcmsr_suspend(device_t dev); 181 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb); 182 static void arcmsr_polling_devmap(void *arg); 183 static void arcmsr_srb_timeout(void *arg); 184 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb); 185 #ifdef ARCMSR_DEBUG1 186 static void arcmsr_dump_data(struct AdapterControlBlock *acb); 187 #endif 188 /* 189 ************************************************************************** 190 ************************************************************************** 191 */ 192 static void UDELAY(u_int32_t us) { DELAY(us); } 193 /* 194 ************************************************************************** 195 ************************************************************************** 196 */ 197 static bus_dmamap_callback_t arcmsr_map_free_srb; 198 static bus_dmamap_callback_t arcmsr_execute_srb; 199 /* 200 ************************************************************************** 201 ************************************************************************** 202 */ 203 static d_open_t arcmsr_open; 204 static d_close_t arcmsr_close; 205 static d_ioctl_t arcmsr_ioctl; 206 207 static device_method_t arcmsr_methods[]={ 208 DEVMETHOD(device_probe, arcmsr_probe), 209 DEVMETHOD(device_attach, arcmsr_attach), 210 DEVMETHOD(device_detach, arcmsr_detach), 211 DEVMETHOD(device_shutdown, arcmsr_shutdown), 212 DEVMETHOD(device_suspend, arcmsr_suspend), 213 DEVMETHOD(device_resume, arcmsr_resume), 214 215 DEVMETHOD_END 216 }; 217 218 static driver_t arcmsr_driver={ 219 "arcmsr", arcmsr_methods, sizeof(struct AdapterControlBlock) 220 }; 221 222 static devclass_t arcmsr_devclass; 223 DRIVER_MODULE(arcmsr, pci, arcmsr_driver, arcmsr_devclass, 0, 0); 224 MODULE_DEPEND(arcmsr, pci, 1, 1, 1); 225 MODULE_DEPEND(arcmsr, cam, 1, 1, 1); 226 #ifndef BUS_DMA_COHERENT 227 #define BUS_DMA_COHERENT 0x04 /* hint: map memory in a coherent way */ 228 #endif 229 #if __FreeBSD_version >= 501000 230 static struct cdevsw arcmsr_cdevsw={ 231 #if __FreeBSD_version >= 503000 232 .d_version = D_VERSION, 233 #endif 234 #if (__FreeBSD_version>=503000 && __FreeBSD_version<600034) 235 .d_flags = D_NEEDGIANT, 236 #endif 237 .d_open = arcmsr_open, /* open */ 238 .d_close = arcmsr_close, /* close */ 239 .d_ioctl = arcmsr_ioctl, /* ioctl */ 240 .d_name = "arcmsr", /* name */ 241 }; 242 #else 243 #define ARCMSR_CDEV_MAJOR 180 244 245 static struct cdevsw arcmsr_cdevsw = { 246 arcmsr_open, /* open */ 247 arcmsr_close, /* close */ 248 noread, /* read */ 249 nowrite, /* write */ 250 arcmsr_ioctl, /* ioctl */ 251 nopoll, /* poll */ 252 nommap, /* mmap */ 253 nostrategy, /* strategy */ 254 "arcmsr", /* name */ 255 ARCMSR_CDEV_MAJOR, /* major */ 256 nodump, /* dump */ 257 nopsize, /* psize */ 258 0 /* flags */ 259 }; 260 #endif 261 /* 262 ************************************************************************** 263 ************************************************************************** 264 */ 265 #if __FreeBSD_version < 500005 266 static int arcmsr_open(dev_t dev, int flags, int fmt, struct proc *proc) 267 #else 268 #if __FreeBSD_version < 503000 269 static int arcmsr_open(dev_t dev, int flags, int fmt, struct thread *proc) 270 #else 271 static int arcmsr_open(struct cdev *dev, int flags, int fmt, struct thread *proc) 272 #endif 273 #endif 274 { 275 #if __FreeBSD_version < 503000 276 struct AdapterControlBlock *acb = dev->si_drv1; 277 #else 278 int unit = dev2unit(dev); 279 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit); 280 #endif 281 if(acb == NULL) { 282 return ENXIO; 283 } 284 return (0); 285 } 286 /* 287 ************************************************************************** 288 ************************************************************************** 289 */ 290 #if __FreeBSD_version < 500005 291 static int arcmsr_close(dev_t dev, int flags, int fmt, struct proc *proc) 292 #else 293 #if __FreeBSD_version < 503000 294 static int arcmsr_close(dev_t dev, int flags, int fmt, struct thread *proc) 295 #else 296 static int arcmsr_close(struct cdev *dev, int flags, int fmt, struct thread *proc) 297 #endif 298 #endif 299 { 300 #if __FreeBSD_version < 503000 301 struct AdapterControlBlock *acb = dev->si_drv1; 302 #else 303 int unit = dev2unit(dev); 304 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit); 305 #endif 306 if(acb == NULL) { 307 return ENXIO; 308 } 309 return 0; 310 } 311 /* 312 ************************************************************************** 313 ************************************************************************** 314 */ 315 #if __FreeBSD_version < 500005 316 static int arcmsr_ioctl(dev_t dev, u_long ioctl_cmd, caddr_t arg, int flags, struct proc *proc) 317 #else 318 #if __FreeBSD_version < 503000 319 static int arcmsr_ioctl(dev_t dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc) 320 #else 321 static int arcmsr_ioctl(struct cdev *dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc) 322 #endif 323 #endif 324 { 325 #if __FreeBSD_version < 503000 326 struct AdapterControlBlock *acb = dev->si_drv1; 327 #else 328 int unit = dev2unit(dev); 329 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit); 330 #endif 331 332 if(acb == NULL) { 333 return ENXIO; 334 } 335 return (arcmsr_iop_ioctlcmd(acb, ioctl_cmd, arg)); 336 } 337 /* 338 ********************************************************************** 339 ********************************************************************** 340 */ 341 static u_int32_t arcmsr_disable_allintr( struct AdapterControlBlock *acb) 342 { 343 u_int32_t intmask_org = 0; 344 345 switch (acb->adapter_type) { 346 case ACB_ADAPTER_TYPE_A: { 347 /* disable all outbound interrupt */ 348 intmask_org = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intmask); /* disable outbound message0 int */ 349 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE); 350 } 351 break; 352 case ACB_ADAPTER_TYPE_B: { 353 /* disable all outbound interrupt */ 354 intmask_org = CHIP_REG_READ32(HBB_DOORBELL, 355 0, iop2drv_doorbell_mask) & (~ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); /* disable outbound message0 int */ 356 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell_mask, 0); /* disable all interrupt */ 357 } 358 break; 359 case ACB_ADAPTER_TYPE_C: { 360 /* disable all outbound interrupt */ 361 intmask_org = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask) ; /* disable outbound message0 int */ 362 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE); 363 } 364 break; 365 case ACB_ADAPTER_TYPE_D: { 366 /* disable all outbound interrupt */ 367 intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable) ; /* disable outbound message0 int */ 368 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE); 369 } 370 break; 371 } 372 return (intmask_org); 373 } 374 /* 375 ********************************************************************** 376 ********************************************************************** 377 */ 378 static void arcmsr_enable_allintr( struct AdapterControlBlock *acb, u_int32_t intmask_org) 379 { 380 u_int32_t mask; 381 382 switch (acb->adapter_type) { 383 case ACB_ADAPTER_TYPE_A: { 384 /* enable outbound Post Queue, outbound doorbell Interrupt */ 385 mask = ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE|ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE); 386 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org & mask); 387 acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff; 388 } 389 break; 390 case ACB_ADAPTER_TYPE_B: { 391 /* enable ARCMSR_IOP2DRV_MESSAGE_CMD_DONE */ 392 mask = (ARCMSR_IOP2DRV_DATA_WRITE_OK|ARCMSR_IOP2DRV_DATA_READ_OK|ARCMSR_IOP2DRV_CDB_DONE|ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); 393 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell_mask, intmask_org | mask); /*1=interrupt enable, 0=interrupt disable*/ 394 acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f; 395 } 396 break; 397 case ACB_ADAPTER_TYPE_C: { 398 /* enable outbound Post Queue, outbound doorbell Interrupt */ 399 mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK); 400 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org & mask); 401 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f; 402 } 403 break; 404 case ACB_ADAPTER_TYPE_D: { 405 /* enable outbound Post Queue, outbound doorbell Interrupt */ 406 mask = ARCMSR_HBDMU_ALL_INT_ENABLE; 407 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | mask); 408 CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); 409 acb->outbound_int_enable = mask; 410 } 411 break; 412 } 413 } 414 /* 415 ********************************************************************** 416 ********************************************************************** 417 */ 418 static u_int8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb) 419 { 420 u_int32_t Index; 421 u_int8_t Retries = 0x00; 422 423 do { 424 for(Index=0; Index < 100; Index++) { 425 if(CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { 426 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);/*clear interrupt*/ 427 return TRUE; 428 } 429 UDELAY(10000); 430 }/*max 1 seconds*/ 431 }while(Retries++ < 20);/*max 20 sec*/ 432 return (FALSE); 433 } 434 /* 435 ********************************************************************** 436 ********************************************************************** 437 */ 438 static u_int8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb) 439 { 440 u_int32_t Index; 441 u_int8_t Retries = 0x00; 442 443 do { 444 for(Index=0; Index < 100; Index++) { 445 if(CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) { 446 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt*/ 447 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 448 return TRUE; 449 } 450 UDELAY(10000); 451 }/*max 1 seconds*/ 452 }while(Retries++ < 20);/*max 20 sec*/ 453 return (FALSE); 454 } 455 /* 456 ********************************************************************** 457 ********************************************************************** 458 */ 459 static u_int8_t arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock *acb) 460 { 461 u_int32_t Index; 462 u_int8_t Retries = 0x00; 463 464 do { 465 for(Index=0; Index < 100; Index++) { 466 if(CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 467 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);/*clear interrupt*/ 468 return TRUE; 469 } 470 UDELAY(10000); 471 }/*max 1 seconds*/ 472 }while(Retries++ < 20);/*max 20 sec*/ 473 return (FALSE); 474 } 475 /* 476 ********************************************************************** 477 ********************************************************************** 478 */ 479 static u_int8_t arcmsr_hbd_wait_msgint_ready(struct AdapterControlBlock *acb) 480 { 481 u_int32_t Index; 482 u_int8_t Retries = 0x00; 483 484 do { 485 for(Index=0; Index < 100; Index++) { 486 if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) { 487 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);/*clear interrupt*/ 488 return TRUE; 489 } 490 UDELAY(10000); 491 }/*max 1 seconds*/ 492 }while(Retries++ < 20);/*max 20 sec*/ 493 return (FALSE); 494 } 495 /* 496 ************************************************************************ 497 ************************************************************************ 498 */ 499 static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb) 500 { 501 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 502 503 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 504 do { 505 if(arcmsr_hba_wait_msgint_ready(acb)) { 506 break; 507 } else { 508 retry_count--; 509 } 510 }while(retry_count != 0); 511 } 512 /* 513 ************************************************************************ 514 ************************************************************************ 515 */ 516 static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb) 517 { 518 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 519 520 CHIP_REG_WRITE32(HBB_DOORBELL, 521 0, drv2iop_doorbell, ARCMSR_MESSAGE_FLUSH_CACHE); 522 do { 523 if(arcmsr_hbb_wait_msgint_ready(acb)) { 524 break; 525 } else { 526 retry_count--; 527 } 528 }while(retry_count != 0); 529 } 530 /* 531 ************************************************************************ 532 ************************************************************************ 533 */ 534 static void arcmsr_flush_hbc_cache(struct AdapterControlBlock *acb) 535 { 536 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 537 538 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 539 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 540 do { 541 if(arcmsr_hbc_wait_msgint_ready(acb)) { 542 break; 543 } else { 544 retry_count--; 545 } 546 }while(retry_count != 0); 547 } 548 /* 549 ************************************************************************ 550 ************************************************************************ 551 */ 552 static void arcmsr_flush_hbd_cache(struct AdapterControlBlock *acb) 553 { 554 int retry_count = 30; /* enlarge wait flush adapter cache time: 10 minute */ 555 556 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 557 do { 558 if(arcmsr_hbd_wait_msgint_ready(acb)) { 559 break; 560 } else { 561 retry_count--; 562 } 563 }while(retry_count != 0); 564 } 565 /* 566 ************************************************************************ 567 ************************************************************************ 568 */ 569 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb) 570 { 571 switch (acb->adapter_type) { 572 case ACB_ADAPTER_TYPE_A: { 573 arcmsr_flush_hba_cache(acb); 574 } 575 break; 576 case ACB_ADAPTER_TYPE_B: { 577 arcmsr_flush_hbb_cache(acb); 578 } 579 break; 580 case ACB_ADAPTER_TYPE_C: { 581 arcmsr_flush_hbc_cache(acb); 582 } 583 break; 584 case ACB_ADAPTER_TYPE_D: { 585 arcmsr_flush_hbd_cache(acb); 586 } 587 break; 588 } 589 } 590 /* 591 ******************************************************************************* 592 ******************************************************************************* 593 */ 594 static int arcmsr_suspend(device_t dev) 595 { 596 struct AdapterControlBlock *acb = device_get_softc(dev); 597 598 /* flush controller */ 599 arcmsr_iop_parking(acb); 600 /* disable all outbound interrupt */ 601 arcmsr_disable_allintr(acb); 602 return(0); 603 } 604 /* 605 ******************************************************************************* 606 ******************************************************************************* 607 */ 608 static int arcmsr_resume(device_t dev) 609 { 610 struct AdapterControlBlock *acb = device_get_softc(dev); 611 612 arcmsr_iop_init(acb); 613 return(0); 614 } 615 /* 616 ********************************************************************************* 617 ********************************************************************************* 618 */ 619 static void arcmsr_async(void *cb_arg, u_int32_t code, struct cam_path *path, void *arg) 620 { 621 struct AdapterControlBlock *acb; 622 u_int8_t target_id, target_lun; 623 struct cam_sim *sim; 624 625 sim = (struct cam_sim *) cb_arg; 626 acb =(struct AdapterControlBlock *) cam_sim_softc(sim); 627 switch (code) { 628 case AC_LOST_DEVICE: 629 target_id = xpt_path_target_id(path); 630 target_lun = xpt_path_lun_id(path); 631 if((target_id > ARCMSR_MAX_TARGETID) || (target_lun > ARCMSR_MAX_TARGETLUN)) { 632 break; 633 } 634 // printf("%s:scsi id=%d lun=%d device lost \n", device_get_name(acb->pci_dev), target_id, target_lun); 635 break; 636 default: 637 break; 638 } 639 } 640 /* 641 ********************************************************************** 642 ********************************************************************** 643 */ 644 static void arcmsr_report_sense_info(struct CommandControlBlock *srb) 645 { 646 union ccb *pccb = srb->pccb; 647 648 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 649 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 650 if(pccb->csio.sense_len) { 651 memset(&pccb->csio.sense_data, 0, sizeof(pccb->csio.sense_data)); 652 memcpy(&pccb->csio.sense_data, srb->arcmsr_cdb.SenseData, 653 get_min(sizeof(struct SENSE_DATA), sizeof(pccb->csio.sense_data))); 654 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); /* Valid,ErrorCode */ 655 pccb->ccb_h.status |= CAM_AUTOSNS_VALID; 656 } 657 } 658 /* 659 ********************************************************************* 660 ********************************************************************* 661 */ 662 static void arcmsr_abort_hba_allcmd(struct AdapterControlBlock *acb) 663 { 664 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 665 if(!arcmsr_hba_wait_msgint_ready(acb)) { 666 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 667 } 668 } 669 /* 670 ********************************************************************* 671 ********************************************************************* 672 */ 673 static void arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb) 674 { 675 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_ABORT_CMD); 676 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 677 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 678 } 679 } 680 /* 681 ********************************************************************* 682 ********************************************************************* 683 */ 684 static void arcmsr_abort_hbc_allcmd(struct AdapterControlBlock *acb) 685 { 686 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 687 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 688 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 689 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 690 } 691 } 692 /* 693 ********************************************************************* 694 ********************************************************************* 695 */ 696 static void arcmsr_abort_hbd_allcmd(struct AdapterControlBlock *acb) 697 { 698 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 699 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 700 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 701 } 702 } 703 /* 704 ********************************************************************* 705 ********************************************************************* 706 */ 707 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb) 708 { 709 switch (acb->adapter_type) { 710 case ACB_ADAPTER_TYPE_A: { 711 arcmsr_abort_hba_allcmd(acb); 712 } 713 break; 714 case ACB_ADAPTER_TYPE_B: { 715 arcmsr_abort_hbb_allcmd(acb); 716 } 717 break; 718 case ACB_ADAPTER_TYPE_C: { 719 arcmsr_abort_hbc_allcmd(acb); 720 } 721 break; 722 case ACB_ADAPTER_TYPE_D: { 723 arcmsr_abort_hbd_allcmd(acb); 724 } 725 break; 726 } 727 } 728 /* 729 ********************************************************************** 730 ********************************************************************** 731 */ 732 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag) 733 { 734 struct AdapterControlBlock *acb = srb->acb; 735 union ccb *pccb = srb->pccb; 736 737 if(srb->srb_flags & SRB_FLAG_TIMER_START) 738 callout_stop(&srb->ccb_callout); 739 if((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 740 bus_dmasync_op_t op; 741 742 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 743 op = BUS_DMASYNC_POSTREAD; 744 } else { 745 op = BUS_DMASYNC_POSTWRITE; 746 } 747 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op); 748 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap); 749 } 750 if(stand_flag == 1) { 751 atomic_subtract_int(&acb->srboutstandingcount, 1); 752 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) && ( 753 acb->srboutstandingcount < (acb->firm_numbers_queue -10))) { 754 acb->acb_flags &= ~ACB_F_CAM_DEV_QFRZN; 755 pccb->ccb_h.status |= CAM_RELEASE_SIMQ; 756 } 757 } 758 if(srb->srb_state != ARCMSR_SRB_TIMEOUT) 759 arcmsr_free_srb(srb); 760 acb->pktReturnCount++; 761 xpt_done(pccb); 762 } 763 /* 764 ************************************************************************** 765 ************************************************************************** 766 */ 767 static void arcmsr_report_srb_state(struct AdapterControlBlock *acb, struct CommandControlBlock *srb, u_int16_t error) 768 { 769 int target, lun; 770 771 target = srb->pccb->ccb_h.target_id; 772 lun = srb->pccb->ccb_h.target_lun; 773 if(error == FALSE) { 774 if(acb->devstate[target][lun] == ARECA_RAID_GONE) { 775 acb->devstate[target][lun] = ARECA_RAID_GOOD; 776 } 777 srb->pccb->ccb_h.status |= CAM_REQ_CMP; 778 arcmsr_srb_complete(srb, 1); 779 } else { 780 switch(srb->arcmsr_cdb.DeviceStatus) { 781 case ARCMSR_DEV_SELECT_TIMEOUT: { 782 if(acb->devstate[target][lun] == ARECA_RAID_GOOD) { 783 printf( "arcmsr%d: Target=%x, Lun=%x, selection timeout, raid volume was lost\n", acb->pci_unit, target, lun); 784 } 785 acb->devstate[target][lun] = ARECA_RAID_GONE; 786 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 787 arcmsr_srb_complete(srb, 1); 788 } 789 break; 790 case ARCMSR_DEV_ABORTED: 791 case ARCMSR_DEV_INIT_FAIL: { 792 acb->devstate[target][lun] = ARECA_RAID_GONE; 793 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 794 arcmsr_srb_complete(srb, 1); 795 } 796 break; 797 case SCSISTAT_CHECK_CONDITION: { 798 acb->devstate[target][lun] = ARECA_RAID_GOOD; 799 arcmsr_report_sense_info(srb); 800 arcmsr_srb_complete(srb, 1); 801 } 802 break; 803 default: 804 printf("arcmsr%d: scsi id=%d lun=%d isr got command error done,but got unknown DeviceStatus=0x%x \n" 805 , acb->pci_unit, target, lun ,srb->arcmsr_cdb.DeviceStatus); 806 acb->devstate[target][lun] = ARECA_RAID_GONE; 807 srb->pccb->ccb_h.status |= CAM_UNCOR_PARITY; 808 /*unknown error or crc error just for retry*/ 809 arcmsr_srb_complete(srb, 1); 810 break; 811 } 812 } 813 } 814 /* 815 ************************************************************************** 816 ************************************************************************** 817 */ 818 static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, u_int32_t flag_srb, u_int16_t error) 819 { 820 struct CommandControlBlock *srb; 821 822 /* check if command done with no error*/ 823 switch (acb->adapter_type) { 824 case ACB_ADAPTER_TYPE_C: 825 case ACB_ADAPTER_TYPE_D: 826 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0)); /*frame must be 32 bytes aligned*/ 827 break; 828 case ACB_ADAPTER_TYPE_A: 829 case ACB_ADAPTER_TYPE_B: 830 default: 831 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 832 break; 833 } 834 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 835 if(srb->srb_state == ARCMSR_SRB_TIMEOUT) { 836 arcmsr_free_srb(srb); 837 printf("arcmsr%d: srb='%p' return srb has been timeouted\n", acb->pci_unit, srb); 838 return; 839 } 840 printf("arcmsr%d: return srb has been completed\n" 841 "srb='%p' srb_state=0x%x outstanding srb count=%d \n", 842 acb->pci_unit, srb, srb->srb_state, acb->srboutstandingcount); 843 return; 844 } 845 arcmsr_report_srb_state(acb, srb, error); 846 } 847 /* 848 ************************************************************************** 849 ************************************************************************** 850 */ 851 static void arcmsr_srb_timeout(void *arg) 852 { 853 struct CommandControlBlock *srb = (struct CommandControlBlock *)arg; 854 struct AdapterControlBlock *acb; 855 int target, lun; 856 u_int8_t cmd; 857 858 target = srb->pccb->ccb_h.target_id; 859 lun = srb->pccb->ccb_h.target_lun; 860 acb = srb->acb; 861 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 862 if(srb->srb_state == ARCMSR_SRB_START) 863 { 864 cmd = srb->pccb->csio.cdb_io.cdb_bytes[0]; 865 srb->srb_state = ARCMSR_SRB_TIMEOUT; 866 srb->pccb->ccb_h.status |= CAM_CMD_TIMEOUT; 867 arcmsr_srb_complete(srb, 1); 868 printf("arcmsr%d: scsi id %d lun %d cmd=0x%x srb='%p' ccb command time out!\n", 869 acb->pci_unit, target, lun, cmd, srb); 870 } 871 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 872 #ifdef ARCMSR_DEBUG1 873 arcmsr_dump_data(acb); 874 #endif 875 } 876 877 /* 878 ********************************************************************** 879 ********************************************************************** 880 */ 881 static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb) 882 { 883 int i=0; 884 u_int32_t flag_srb; 885 u_int16_t error; 886 887 switch (acb->adapter_type) { 888 case ACB_ADAPTER_TYPE_A: { 889 u_int32_t outbound_intstatus; 890 891 /*clear and abort all outbound posted Q*/ 892 outbound_intstatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 893 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);/*clear interrupt*/ 894 while(((flag_srb=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_queueport)) != 0xFFFFFFFF) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) { 895 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 896 arcmsr_drain_donequeue(acb, flag_srb, error); 897 } 898 } 899 break; 900 case ACB_ADAPTER_TYPE_B: { 901 struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu; 902 903 /*clear all outbound posted Q*/ 904 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */ 905 for(i=0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) { 906 if((flag_srb = phbbmu->done_qbuffer[i]) != 0) { 907 phbbmu->done_qbuffer[i] = 0; 908 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 909 arcmsr_drain_donequeue(acb, flag_srb, error); 910 } 911 phbbmu->post_qbuffer[i] = 0; 912 }/*drain reply FIFO*/ 913 phbbmu->doneq_index = 0; 914 phbbmu->postq_index = 0; 915 } 916 break; 917 case ACB_ADAPTER_TYPE_C: { 918 919 while((CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) { 920 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 921 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 922 arcmsr_drain_donequeue(acb, flag_srb, error); 923 } 924 } 925 break; 926 case ACB_ADAPTER_TYPE_D: { 927 arcmsr_hbd_postqueue_isr(acb); 928 } 929 break; 930 } 931 } 932 /* 933 **************************************************************************** 934 **************************************************************************** 935 */ 936 static void arcmsr_iop_reset(struct AdapterControlBlock *acb) 937 { 938 struct CommandControlBlock *srb; 939 u_int32_t intmask_org; 940 u_int32_t i=0; 941 942 if(acb->srboutstandingcount>0) { 943 /* disable all outbound interrupt */ 944 intmask_org = arcmsr_disable_allintr(acb); 945 /*clear and abort all outbound posted Q*/ 946 arcmsr_done4abort_postqueue(acb); 947 /* talk to iop 331 outstanding command aborted*/ 948 arcmsr_abort_allcmd(acb); 949 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 950 srb = acb->psrb_pool[i]; 951 if(srb->srb_state == ARCMSR_SRB_START) { 952 srb->srb_state = ARCMSR_SRB_ABORTED; 953 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 954 arcmsr_srb_complete(srb, 1); 955 printf("arcmsr%d: scsi id=%d lun=%d srb='%p' aborted\n" 956 , acb->pci_unit, srb->pccb->ccb_h.target_id 957 , srb->pccb->ccb_h.target_lun, srb); 958 } 959 } 960 /* enable all outbound interrupt */ 961 arcmsr_enable_allintr(acb, intmask_org); 962 } 963 acb->srboutstandingcount = 0; 964 acb->workingsrb_doneindex = 0; 965 acb->workingsrb_startindex = 0; 966 acb->pktRequestCount = 0; 967 acb->pktReturnCount = 0; 968 } 969 /* 970 ********************************************************************** 971 ********************************************************************** 972 */ 973 static void arcmsr_build_srb(struct CommandControlBlock *srb, 974 bus_dma_segment_t *dm_segs, u_int32_t nseg) 975 { 976 struct ARCMSR_CDB *arcmsr_cdb = &srb->arcmsr_cdb; 977 u_int8_t *psge = (u_int8_t *)&arcmsr_cdb->u; 978 u_int32_t address_lo, address_hi; 979 union ccb *pccb = srb->pccb; 980 struct ccb_scsiio *pcsio = &pccb->csio; 981 u_int32_t arccdbsize = 0x30; 982 983 memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB)); 984 arcmsr_cdb->Bus = 0; 985 arcmsr_cdb->TargetID = pccb->ccb_h.target_id; 986 arcmsr_cdb->LUN = pccb->ccb_h.target_lun; 987 arcmsr_cdb->Function = 1; 988 arcmsr_cdb->CdbLength = (u_int8_t)pcsio->cdb_len; 989 bcopy(pcsio->cdb_io.cdb_bytes, arcmsr_cdb->Cdb, pcsio->cdb_len); 990 if(nseg != 0) { 991 struct AdapterControlBlock *acb = srb->acb; 992 bus_dmasync_op_t op; 993 u_int32_t length, i, cdb_sgcount = 0; 994 995 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 996 op = BUS_DMASYNC_PREREAD; 997 } else { 998 op = BUS_DMASYNC_PREWRITE; 999 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE; 1000 srb->srb_flags |= SRB_FLAG_WRITE; 1001 } 1002 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op); 1003 for(i=0; i < nseg; i++) { 1004 /* Get the physical address of the current data pointer */ 1005 length = arcmsr_htole32(dm_segs[i].ds_len); 1006 address_lo = arcmsr_htole32(dma_addr_lo32(dm_segs[i].ds_addr)); 1007 address_hi = arcmsr_htole32(dma_addr_hi32(dm_segs[i].ds_addr)); 1008 if(address_hi == 0) { 1009 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge; 1010 pdma_sg->address = address_lo; 1011 pdma_sg->length = length; 1012 psge += sizeof(struct SG32ENTRY); 1013 arccdbsize += sizeof(struct SG32ENTRY); 1014 } else { 1015 u_int32_t sg64s_size = 0, tmplength = length; 1016 1017 while(1) { 1018 u_int64_t span4G, length0; 1019 struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge; 1020 1021 span4G = (u_int64_t)address_lo + tmplength; 1022 pdma_sg->addresshigh = address_hi; 1023 pdma_sg->address = address_lo; 1024 if(span4G > 0x100000000) { 1025 /*see if cross 4G boundary*/ 1026 length0 = 0x100000000-address_lo; 1027 pdma_sg->length = (u_int32_t)length0 | IS_SG64_ADDR; 1028 address_hi = address_hi+1; 1029 address_lo = 0; 1030 tmplength = tmplength - (u_int32_t)length0; 1031 sg64s_size += sizeof(struct SG64ENTRY); 1032 psge += sizeof(struct SG64ENTRY); 1033 cdb_sgcount++; 1034 } else { 1035 pdma_sg->length = tmplength | IS_SG64_ADDR; 1036 sg64s_size += sizeof(struct SG64ENTRY); 1037 psge += sizeof(struct SG64ENTRY); 1038 break; 1039 } 1040 } 1041 arccdbsize += sg64s_size; 1042 } 1043 cdb_sgcount++; 1044 } 1045 arcmsr_cdb->sgcount = (u_int8_t)cdb_sgcount; 1046 arcmsr_cdb->DataLength = pcsio->dxfer_len; 1047 if( arccdbsize > 256) { 1048 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE; 1049 } 1050 } else { 1051 arcmsr_cdb->DataLength = 0; 1052 } 1053 srb->arc_cdb_size = arccdbsize; 1054 arcmsr_cdb->msgPages = (arccdbsize/256) + ((arccdbsize % 256) ? 1 : 0); 1055 } 1056 /* 1057 ************************************************************************** 1058 ************************************************************************** 1059 */ 1060 static void arcmsr_post_srb(struct AdapterControlBlock *acb, struct CommandControlBlock *srb) 1061 { 1062 u_int32_t cdb_phyaddr_low = (u_int32_t) srb->cdb_phyaddr_low; 1063 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&srb->arcmsr_cdb; 1064 1065 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, (srb->srb_flags & SRB_FLAG_WRITE) ? BUS_DMASYNC_POSTWRITE:BUS_DMASYNC_POSTREAD); 1066 atomic_add_int(&acb->srboutstandingcount, 1); 1067 srb->srb_state = ARCMSR_SRB_START; 1068 1069 switch (acb->adapter_type) { 1070 case ACB_ADAPTER_TYPE_A: { 1071 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { 1072 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low|ARCMSR_SRBPOST_FLAG_SGL_BSIZE); 1073 } else { 1074 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low); 1075 } 1076 } 1077 break; 1078 case ACB_ADAPTER_TYPE_B: { 1079 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1080 int ending_index, index; 1081 1082 index = phbbmu->postq_index; 1083 ending_index = ((index+1) % ARCMSR_MAX_HBB_POSTQUEUE); 1084 phbbmu->post_qbuffer[ending_index] = 0; 1085 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { 1086 phbbmu->post_qbuffer[index] = cdb_phyaddr_low | ARCMSR_SRBPOST_FLAG_SGL_BSIZE; 1087 } else { 1088 phbbmu->post_qbuffer[index] = cdb_phyaddr_low; 1089 } 1090 index++; 1091 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 1092 phbbmu->postq_index = index; 1093 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_CDB_POSTED); 1094 } 1095 break; 1096 case ACB_ADAPTER_TYPE_C: { 1097 u_int32_t ccb_post_stamp, arc_cdb_size, cdb_phyaddr_hi32; 1098 1099 arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size; 1100 ccb_post_stamp = (cdb_phyaddr_low | ((arc_cdb_size-1) >> 6) | 1); 1101 cdb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high; 1102 if(cdb_phyaddr_hi32) 1103 { 1104 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_high, cdb_phyaddr_hi32); 1105 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp); 1106 } 1107 else 1108 { 1109 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp); 1110 } 1111 } 1112 break; 1113 case ACB_ADAPTER_TYPE_D: { 1114 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1115 u_int16_t index_stripped; 1116 u_int16_t postq_index; 1117 struct InBound_SRB *pinbound_srb; 1118 1119 ARCMSR_LOCK_ACQUIRE(&acb->postDone_lock); 1120 postq_index = phbdmu->postq_index; 1121 pinbound_srb = (struct InBound_SRB *)&phbdmu->post_qbuffer[postq_index & 0xFF]; 1122 pinbound_srb->addressHigh = srb->cdb_phyaddr_high; 1123 pinbound_srb->addressLow = srb->cdb_phyaddr_low; 1124 pinbound_srb->length = srb->arc_cdb_size >> 2; 1125 arcmsr_cdb->Context = srb->cdb_phyaddr_low; 1126 if (postq_index & 0x4000) { 1127 index_stripped = postq_index & 0xFF; 1128 index_stripped += 1; 1129 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1130 phbdmu->postq_index = index_stripped ? (index_stripped | 0x4000) : index_stripped; 1131 } else { 1132 index_stripped = postq_index; 1133 index_stripped += 1; 1134 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1135 phbdmu->postq_index = index_stripped ? index_stripped : (index_stripped | 0x4000); 1136 } 1137 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inboundlist_write_pointer, postq_index); 1138 ARCMSR_LOCK_RELEASE(&acb->postDone_lock); 1139 } 1140 break; 1141 } 1142 } 1143 /* 1144 ************************************************************************ 1145 ************************************************************************ 1146 */ 1147 static struct QBUFFER *arcmsr_get_iop_rqbuffer( struct AdapterControlBlock *acb) 1148 { 1149 struct QBUFFER *qbuffer=NULL; 1150 1151 switch (acb->adapter_type) { 1152 case ACB_ADAPTER_TYPE_A: { 1153 struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu; 1154 1155 qbuffer = (struct QBUFFER *)&phbamu->message_rbuffer; 1156 } 1157 break; 1158 case ACB_ADAPTER_TYPE_B: { 1159 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1160 1161 qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_rbuffer; 1162 } 1163 break; 1164 case ACB_ADAPTER_TYPE_C: { 1165 struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu; 1166 1167 qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer; 1168 } 1169 break; 1170 case ACB_ADAPTER_TYPE_D: { 1171 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1172 1173 qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_rbuffer; 1174 } 1175 break; 1176 } 1177 return(qbuffer); 1178 } 1179 /* 1180 ************************************************************************ 1181 ************************************************************************ 1182 */ 1183 static struct QBUFFER *arcmsr_get_iop_wqbuffer( struct AdapterControlBlock *acb) 1184 { 1185 struct QBUFFER *qbuffer = NULL; 1186 1187 switch (acb->adapter_type) { 1188 case ACB_ADAPTER_TYPE_A: { 1189 struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu; 1190 1191 qbuffer = (struct QBUFFER *)&phbamu->message_wbuffer; 1192 } 1193 break; 1194 case ACB_ADAPTER_TYPE_B: { 1195 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1196 1197 qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_wbuffer; 1198 } 1199 break; 1200 case ACB_ADAPTER_TYPE_C: { 1201 struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu; 1202 1203 qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer; 1204 } 1205 break; 1206 case ACB_ADAPTER_TYPE_D: { 1207 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1208 1209 qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_wbuffer; 1210 } 1211 break; 1212 } 1213 return(qbuffer); 1214 } 1215 /* 1216 ************************************************************************** 1217 ************************************************************************** 1218 */ 1219 static void arcmsr_iop_message_read(struct AdapterControlBlock *acb) 1220 { 1221 switch (acb->adapter_type) { 1222 case ACB_ADAPTER_TYPE_A: { 1223 /* let IOP know data has been read */ 1224 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK); 1225 } 1226 break; 1227 case ACB_ADAPTER_TYPE_B: { 1228 /* let IOP know data has been read */ 1229 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK); 1230 } 1231 break; 1232 case ACB_ADAPTER_TYPE_C: { 1233 /* let IOP know data has been read */ 1234 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK); 1235 } 1236 break; 1237 case ACB_ADAPTER_TYPE_D: { 1238 /* let IOP know data has been read */ 1239 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ); 1240 } 1241 break; 1242 } 1243 } 1244 /* 1245 ************************************************************************** 1246 ************************************************************************** 1247 */ 1248 static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb) 1249 { 1250 switch (acb->adapter_type) { 1251 case ACB_ADAPTER_TYPE_A: { 1252 /* 1253 ** push inbound doorbell tell iop, driver data write ok 1254 ** and wait reply on next hwinterrupt for next Qbuffer post 1255 */ 1256 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK); 1257 } 1258 break; 1259 case ACB_ADAPTER_TYPE_B: { 1260 /* 1261 ** push inbound doorbell tell iop, driver data write ok 1262 ** and wait reply on next hwinterrupt for next Qbuffer post 1263 */ 1264 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_WRITE_OK); 1265 } 1266 break; 1267 case ACB_ADAPTER_TYPE_C: { 1268 /* 1269 ** push inbound doorbell tell iop, driver data write ok 1270 ** and wait reply on next hwinterrupt for next Qbuffer post 1271 */ 1272 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK); 1273 } 1274 break; 1275 case ACB_ADAPTER_TYPE_D: { 1276 /* 1277 ** push inbound doorbell tell iop, driver data write ok 1278 ** and wait reply on next hwinterrupt for next Qbuffer post 1279 */ 1280 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY); 1281 } 1282 break; 1283 } 1284 } 1285 /* 1286 ************************************************************************ 1287 ************************************************************************ 1288 */ 1289 static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb) 1290 { 1291 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1292 CHIP_REG_WRITE32(HBA_MessageUnit, 1293 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1294 if(!arcmsr_hba_wait_msgint_ready(acb)) { 1295 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n" 1296 , acb->pci_unit); 1297 } 1298 } 1299 /* 1300 ************************************************************************ 1301 ************************************************************************ 1302 */ 1303 static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb) 1304 { 1305 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1306 CHIP_REG_WRITE32(HBB_DOORBELL, 1307 0, drv2iop_doorbell, ARCMSR_MESSAGE_STOP_BGRB); 1308 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 1309 printf( "arcmsr%d: wait 'stop adapter background rebulid' timeout \n" 1310 , acb->pci_unit); 1311 } 1312 } 1313 /* 1314 ************************************************************************ 1315 ************************************************************************ 1316 */ 1317 static void arcmsr_stop_hbc_bgrb(struct AdapterControlBlock *acb) 1318 { 1319 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1320 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1321 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 1322 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 1323 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1324 } 1325 } 1326 /* 1327 ************************************************************************ 1328 ************************************************************************ 1329 */ 1330 static void arcmsr_stop_hbd_bgrb(struct AdapterControlBlock *acb) 1331 { 1332 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1333 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1334 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 1335 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1336 } 1337 } 1338 /* 1339 ************************************************************************ 1340 ************************************************************************ 1341 */ 1342 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb) 1343 { 1344 switch (acb->adapter_type) { 1345 case ACB_ADAPTER_TYPE_A: { 1346 arcmsr_stop_hba_bgrb(acb); 1347 } 1348 break; 1349 case ACB_ADAPTER_TYPE_B: { 1350 arcmsr_stop_hbb_bgrb(acb); 1351 } 1352 break; 1353 case ACB_ADAPTER_TYPE_C: { 1354 arcmsr_stop_hbc_bgrb(acb); 1355 } 1356 break; 1357 case ACB_ADAPTER_TYPE_D: { 1358 arcmsr_stop_hbd_bgrb(acb); 1359 } 1360 break; 1361 } 1362 } 1363 /* 1364 ************************************************************************ 1365 ************************************************************************ 1366 */ 1367 static void arcmsr_poll(struct cam_sim *psim) 1368 { 1369 struct AdapterControlBlock *acb; 1370 int mutex; 1371 1372 acb = (struct AdapterControlBlock *)cam_sim_softc(psim); 1373 mutex = mtx_owned(&acb->isr_lock); 1374 if( mutex == 0 ) 1375 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 1376 arcmsr_interrupt(acb); 1377 if( mutex == 0 ) 1378 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 1379 } 1380 /* 1381 ************************************************************************** 1382 ************************************************************************** 1383 */ 1384 static void arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, 1385 struct QBUFFER *prbuffer) { 1386 1387 u_int8_t *pQbuffer; 1388 u_int8_t *iop_data; 1389 u_int32_t iop_len; 1390 1391 iop_data = (u_int8_t *)prbuffer->data; 1392 iop_len = (u_int32_t)prbuffer->data_len; 1393 while (iop_len > 0) { 1394 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex]; 1395 *pQbuffer = *iop_data; 1396 acb->rqbuf_lastindex++; 1397 /* if last, index number set it to 0 */ 1398 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 1399 iop_data++; 1400 iop_len--; 1401 } 1402 /* let IOP know data has been read */ 1403 arcmsr_iop_message_read(acb); 1404 } 1405 /* 1406 ************************************************************************** 1407 ************************************************************************** 1408 */ 1409 static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb) 1410 { 1411 struct QBUFFER *prbuffer; 1412 int my_empty_len; 1413 1414 /*check this iop data if overflow my rqbuffer*/ 1415 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 1416 prbuffer = arcmsr_get_iop_rqbuffer(acb); 1417 my_empty_len = (acb->rqbuf_lastindex - acb->rqbuf_firstindex - 1) & 1418 (ARCMSR_MAX_QBUFFER-1); 1419 if(my_empty_len >= prbuffer->data_len) { 1420 arcmsr_Read_iop_rqbuffer_data(acb, prbuffer); 1421 } else { 1422 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 1423 } 1424 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 1425 } 1426 /* 1427 ********************************************************************** 1428 ********************************************************************** 1429 */ 1430 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb) 1431 { 1432 u_int8_t *pQbuffer; 1433 struct QBUFFER *pwbuffer; 1434 u_int8_t *iop_data; 1435 int32_t allxfer_len=0; 1436 1437 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) { 1438 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ); 1439 pwbuffer = arcmsr_get_iop_wqbuffer(acb); 1440 iop_data = (u_int8_t *)pwbuffer->data; 1441 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex) 1442 && (allxfer_len < 124)) { 1443 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex]; 1444 *iop_data = *pQbuffer; 1445 acb->wqbuf_firstindex++; 1446 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 1447 iop_data++; 1448 allxfer_len++; 1449 } 1450 pwbuffer->data_len = allxfer_len; 1451 arcmsr_iop_message_wrote(acb); 1452 } 1453 } 1454 /* 1455 ************************************************************************** 1456 ************************************************************************** 1457 */ 1458 static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb) 1459 { 1460 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 1461 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READ; 1462 /* 1463 ***************************************************************** 1464 ** check if there are any mail packages from user space program 1465 ** in my post bag, now is the time to send them into Areca's firmware 1466 ***************************************************************** 1467 */ 1468 if(acb->wqbuf_firstindex != acb->wqbuf_lastindex) { 1469 arcmsr_Write_data_2iop_wqbuffer(acb); 1470 } 1471 if(acb->wqbuf_firstindex == acb->wqbuf_lastindex) { 1472 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED; 1473 } 1474 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 1475 } 1476 /* 1477 ************************************************************************** 1478 ************************************************************************** 1479 */ 1480 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb) 1481 { 1482 /* 1483 if (ccb->ccb_h.status != CAM_REQ_CMP) 1484 printf("arcmsr_rescanLun_cb: Rescan Target=%x, lun=%x," 1485 "failure status=%x\n", ccb->ccb_h.target_id, 1486 ccb->ccb_h.target_lun, ccb->ccb_h.status); 1487 else 1488 printf("arcmsr_rescanLun_cb: Rescan lun successfully!\n"); 1489 */ 1490 xpt_free_path(ccb->ccb_h.path); 1491 xpt_free_ccb(ccb); 1492 } 1493 1494 static void arcmsr_rescan_lun(struct AdapterControlBlock *acb, int target, int lun) 1495 { 1496 struct cam_path *path; 1497 union ccb *ccb; 1498 1499 if ((ccb = (union ccb *)xpt_alloc_ccb_nowait()) == NULL) 1500 return; 1501 if (xpt_create_path(&path, xpt_periph, cam_sim_path(acb->psim), target, lun) != CAM_REQ_CMP) 1502 { 1503 xpt_free_ccb(ccb); 1504 return; 1505 } 1506 /* printf("arcmsr_rescan_lun: Rescan Target=%x, Lun=%x\n", target, lun); */ 1507 bzero(ccb, sizeof(union ccb)); 1508 xpt_setup_ccb(&ccb->ccb_h, path, 5); 1509 ccb->ccb_h.func_code = XPT_SCAN_LUN; 1510 ccb->ccb_h.cbfcnp = arcmsr_rescanLun_cb; 1511 ccb->crcn.flags = CAM_FLAG_NONE; 1512 xpt_action(ccb); 1513 } 1514 1515 1516 static void arcmsr_abort_dr_ccbs(struct AdapterControlBlock *acb, int target, int lun) 1517 { 1518 struct CommandControlBlock *srb; 1519 u_int32_t intmask_org; 1520 int i; 1521 1522 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 1523 /* disable all outbound interrupts */ 1524 intmask_org = arcmsr_disable_allintr(acb); 1525 for (i = 0; i < ARCMSR_MAX_FREESRB_NUM; i++) 1526 { 1527 srb = acb->psrb_pool[i]; 1528 if (srb->srb_state == ARCMSR_SRB_START) 1529 { 1530 if((target == srb->pccb->ccb_h.target_id) && (lun == srb->pccb->ccb_h.target_lun)) 1531 { 1532 srb->srb_state = ARCMSR_SRB_ABORTED; 1533 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 1534 arcmsr_srb_complete(srb, 1); 1535 printf("arcmsr%d: abort scsi id %d lun %d srb=%p \n", acb->pci_unit, target, lun, srb); 1536 } 1537 } 1538 } 1539 /* enable outbound Post Queue, outbound doorbell Interrupt */ 1540 arcmsr_enable_allintr(acb, intmask_org); 1541 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 1542 } 1543 /* 1544 ************************************************************************** 1545 ************************************************************************** 1546 */ 1547 static void arcmsr_dr_handle(struct AdapterControlBlock *acb) { 1548 u_int32_t devicemap; 1549 u_int32_t target, lun; 1550 u_int32_t deviceMapCurrent[4]={0}; 1551 u_int8_t *pDevMap; 1552 1553 switch (acb->adapter_type) { 1554 case ACB_ADAPTER_TYPE_A: 1555 devicemap = offsetof(struct HBA_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1556 for (target = 0; target < 4; target++) 1557 { 1558 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1559 devicemap += 4; 1560 } 1561 break; 1562 1563 case ACB_ADAPTER_TYPE_B: 1564 devicemap = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1565 for (target = 0; target < 4; target++) 1566 { 1567 deviceMapCurrent[target]=bus_space_read_4(acb->btag[1], acb->bhandle[1], devicemap); 1568 devicemap += 4; 1569 } 1570 break; 1571 1572 case ACB_ADAPTER_TYPE_C: 1573 devicemap = offsetof(struct HBC_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1574 for (target = 0; target < 4; target++) 1575 { 1576 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1577 devicemap += 4; 1578 } 1579 break; 1580 case ACB_ADAPTER_TYPE_D: 1581 devicemap = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1582 for (target = 0; target < 4; target++) 1583 { 1584 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1585 devicemap += 4; 1586 } 1587 break; 1588 } 1589 1590 if(acb->acb_flags & ACB_F_BUS_HANG_ON) 1591 { 1592 acb->acb_flags &= ~ACB_F_BUS_HANG_ON; 1593 } 1594 /* 1595 ** adapter posted CONFIG message 1596 ** copy the new map, note if there are differences with the current map 1597 */ 1598 pDevMap = (u_int8_t *)&deviceMapCurrent[0]; 1599 for (target = 0; target < ARCMSR_MAX_TARGETID - 1; target++) 1600 { 1601 if (*pDevMap != acb->device_map[target]) 1602 { 1603 u_int8_t difference, bit_check; 1604 1605 difference = *pDevMap ^ acb->device_map[target]; 1606 for(lun=0; lun < ARCMSR_MAX_TARGETLUN; lun++) 1607 { 1608 bit_check = (1 << lun); /*check bit from 0....31*/ 1609 if(difference & bit_check) 1610 { 1611 if(acb->device_map[target] & bit_check) 1612 {/* unit departed */ 1613 printf("arcmsr_dr_handle: Target=%x, lun=%x, GONE!!!\n",target,lun); 1614 arcmsr_abort_dr_ccbs(acb, target, lun); 1615 arcmsr_rescan_lun(acb, target, lun); 1616 acb->devstate[target][lun] = ARECA_RAID_GONE; 1617 } 1618 else 1619 {/* unit arrived */ 1620 printf("arcmsr_dr_handle: Target=%x, lun=%x, Plug-IN!!!\n",target,lun); 1621 arcmsr_rescan_lun(acb, target, lun); 1622 acb->devstate[target][lun] = ARECA_RAID_GOOD; 1623 } 1624 } 1625 } 1626 /* printf("arcmsr_dr_handle: acb->device_map[%x]=0x%x, deviceMapCurrent[%x]=%x\n",target,acb->device_map[target],target,*pDevMap); */ 1627 acb->device_map[target] = *pDevMap; 1628 } 1629 pDevMap++; 1630 } 1631 } 1632 /* 1633 ************************************************************************** 1634 ************************************************************************** 1635 */ 1636 static void arcmsr_hba_message_isr(struct AdapterControlBlock *acb) { 1637 u_int32_t outbound_message; 1638 1639 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT); 1640 outbound_message = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[0]); 1641 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1642 arcmsr_dr_handle( acb ); 1643 } 1644 /* 1645 ************************************************************************** 1646 ************************************************************************** 1647 */ 1648 static void arcmsr_hbb_message_isr(struct AdapterControlBlock *acb) { 1649 u_int32_t outbound_message; 1650 1651 /* clear interrupts */ 1652 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN); 1653 outbound_message = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0]); 1654 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1655 arcmsr_dr_handle( acb ); 1656 } 1657 /* 1658 ************************************************************************** 1659 ************************************************************************** 1660 */ 1661 static void arcmsr_hbc_message_isr(struct AdapterControlBlock *acb) { 1662 u_int32_t outbound_message; 1663 1664 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR); 1665 outbound_message = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[0]); 1666 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1667 arcmsr_dr_handle( acb ); 1668 } 1669 /* 1670 ************************************************************************** 1671 ************************************************************************** 1672 */ 1673 static void arcmsr_hbd_message_isr(struct AdapterControlBlock *acb) { 1674 u_int32_t outbound_message; 1675 1676 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR); 1677 outbound_message = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[0]); 1678 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1679 arcmsr_dr_handle( acb ); 1680 } 1681 /* 1682 ************************************************************************** 1683 ************************************************************************** 1684 */ 1685 static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb) 1686 { 1687 u_int32_t outbound_doorbell; 1688 1689 /* 1690 ******************************************************************* 1691 ** Maybe here we need to check wrqbuffer_lock is lock or not 1692 ** DOORBELL: din! don! 1693 ** check if there are any mail need to pack from firmware 1694 ******************************************************************* 1695 */ 1696 outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit, 1697 0, outbound_doorbell); 1698 CHIP_REG_WRITE32(HBA_MessageUnit, 1699 0, outbound_doorbell, outbound_doorbell); /* clear doorbell interrupt */ 1700 if(outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) { 1701 arcmsr_iop2drv_data_wrote_handle(acb); 1702 } 1703 if(outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) { 1704 arcmsr_iop2drv_data_read_handle(acb); 1705 } 1706 } 1707 /* 1708 ************************************************************************** 1709 ************************************************************************** 1710 */ 1711 static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *acb) 1712 { 1713 u_int32_t outbound_doorbell; 1714 1715 /* 1716 ******************************************************************* 1717 ** Maybe here we need to check wrqbuffer_lock is lock or not 1718 ** DOORBELL: din! don! 1719 ** check if there are any mail need to pack from firmware 1720 ******************************************************************* 1721 */ 1722 outbound_doorbell = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell); 1723 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell); /* clear doorbell interrupt */ 1724 if(outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) { 1725 arcmsr_iop2drv_data_wrote_handle(acb); 1726 } 1727 if(outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) { 1728 arcmsr_iop2drv_data_read_handle(acb); 1729 } 1730 if(outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 1731 arcmsr_hbc_message_isr(acb); /* messenger of "driver to iop commands" */ 1732 } 1733 } 1734 /* 1735 ************************************************************************** 1736 ************************************************************************** 1737 */ 1738 static void arcmsr_hbd_doorbell_isr(struct AdapterControlBlock *acb) 1739 { 1740 u_int32_t outbound_Doorbell; 1741 1742 /* 1743 ******************************************************************* 1744 ** Maybe here we need to check wrqbuffer_lock is lock or not 1745 ** DOORBELL: din! don! 1746 ** check if there are any mail need to pack from firmware 1747 ******************************************************************* 1748 */ 1749 outbound_Doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE; 1750 if(outbound_Doorbell) 1751 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_Doorbell); /* clear doorbell interrupt */ 1752 while( outbound_Doorbell & ARCMSR_HBDMU_F0_DOORBELL_CAUSE ) { 1753 if(outbound_Doorbell & ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK) { 1754 arcmsr_iop2drv_data_wrote_handle(acb); 1755 } 1756 if(outbound_Doorbell & ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK) { 1757 arcmsr_iop2drv_data_read_handle(acb); 1758 } 1759 if(outbound_Doorbell & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) { 1760 arcmsr_hbd_message_isr(acb); /* messenger of "driver to iop commands" */ 1761 } 1762 outbound_Doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE; 1763 if(outbound_Doorbell) 1764 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_Doorbell); /* clear doorbell interrupt */ 1765 } 1766 } 1767 /* 1768 ************************************************************************** 1769 ************************************************************************** 1770 */ 1771 static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb) 1772 { 1773 u_int32_t flag_srb; 1774 u_int16_t error; 1775 1776 /* 1777 ***************************************************************************** 1778 ** areca cdb command done 1779 ***************************************************************************** 1780 */ 1781 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 1782 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1783 while((flag_srb = CHIP_REG_READ32(HBA_MessageUnit, 1784 0, outbound_queueport)) != 0xFFFFFFFF) { 1785 /* check if command done with no error*/ 1786 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0) ? TRUE : FALSE; 1787 arcmsr_drain_donequeue(acb, flag_srb, error); 1788 } /*drain reply FIFO*/ 1789 } 1790 /* 1791 ************************************************************************** 1792 ************************************************************************** 1793 */ 1794 static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb) 1795 { 1796 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1797 u_int32_t flag_srb; 1798 int index; 1799 u_int16_t error; 1800 1801 /* 1802 ***************************************************************************** 1803 ** areca cdb command done 1804 ***************************************************************************** 1805 */ 1806 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 1807 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1808 index = phbbmu->doneq_index; 1809 while((flag_srb = phbbmu->done_qbuffer[index]) != 0) { 1810 phbbmu->done_qbuffer[index] = 0; 1811 index++; 1812 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 1813 phbbmu->doneq_index = index; 1814 /* check if command done with no error*/ 1815 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 1816 arcmsr_drain_donequeue(acb, flag_srb, error); 1817 } /*drain reply FIFO*/ 1818 } 1819 /* 1820 ************************************************************************** 1821 ************************************************************************** 1822 */ 1823 static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb) 1824 { 1825 u_int32_t flag_srb,throttling = 0; 1826 u_int16_t error; 1827 1828 /* 1829 ***************************************************************************** 1830 ** areca cdb command done 1831 ***************************************************************************** 1832 */ 1833 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1834 1835 while(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) { 1836 1837 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 1838 /* check if command done with no error*/ 1839 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE; 1840 arcmsr_drain_donequeue(acb, flag_srb, error); 1841 if(throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) { 1842 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING); 1843 break; 1844 } 1845 throttling++; 1846 } /*drain reply FIFO*/ 1847 } 1848 /* 1849 ********************************************************************** 1850 ** 1851 ********************************************************************** 1852 */ 1853 static uint16_t arcmsr_get_doneq_index(struct HBD_MessageUnit0 *phbdmu) 1854 { 1855 uint16_t doneq_index, index_stripped; 1856 1857 doneq_index = phbdmu->doneq_index; 1858 if (doneq_index & 0x4000) { 1859 index_stripped = doneq_index & 0xFF; 1860 index_stripped += 1; 1861 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1862 phbdmu->doneq_index = index_stripped ? 1863 (index_stripped | 0x4000) : index_stripped; 1864 } else { 1865 index_stripped = doneq_index; 1866 index_stripped += 1; 1867 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1868 phbdmu->doneq_index = index_stripped ? 1869 index_stripped : (index_stripped | 0x4000); 1870 } 1871 return (phbdmu->doneq_index); 1872 } 1873 /* 1874 ************************************************************************** 1875 ************************************************************************** 1876 */ 1877 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb) 1878 { 1879 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1880 u_int32_t outbound_write_pointer; 1881 u_int32_t addressLow; 1882 uint16_t doneq_index; 1883 u_int16_t error; 1884 /* 1885 ***************************************************************************** 1886 ** areca cdb command done 1887 ***************************************************************************** 1888 */ 1889 if((CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause) & 1890 ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT) == 0) 1891 return; 1892 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 1893 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1894 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 1895 doneq_index = phbdmu->doneq_index; 1896 while ((doneq_index & 0xFF) != (outbound_write_pointer & 0xFF)) { 1897 doneq_index = arcmsr_get_doneq_index(phbdmu); 1898 addressLow = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow; 1899 error = (addressLow & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 1900 arcmsr_drain_donequeue(acb, addressLow, error); /*Check if command done with no error */ 1901 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index); 1902 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 1903 } 1904 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_interrupt_cause, ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR); 1905 CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause); /*Dummy ioread32 to force pci flush */ 1906 } 1907 /* 1908 ********************************************************************** 1909 ********************************************************************** 1910 */ 1911 static void arcmsr_handle_hba_isr( struct AdapterControlBlock *acb) 1912 { 1913 u_int32_t outbound_intStatus; 1914 /* 1915 ********************************************* 1916 ** check outbound intstatus 1917 ********************************************* 1918 */ 1919 outbound_intStatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 1920 if(!outbound_intStatus) { 1921 /*it must be share irq*/ 1922 return; 1923 } 1924 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intStatus); /*clear interrupt*/ 1925 /* MU doorbell interrupts*/ 1926 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) { 1927 arcmsr_hba_doorbell_isr(acb); 1928 } 1929 /* MU post queue interrupts*/ 1930 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) { 1931 arcmsr_hba_postqueue_isr(acb); 1932 } 1933 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { 1934 arcmsr_hba_message_isr(acb); 1935 } 1936 } 1937 /* 1938 ********************************************************************** 1939 ********************************************************************** 1940 */ 1941 static void arcmsr_handle_hbb_isr( struct AdapterControlBlock *acb) 1942 { 1943 u_int32_t outbound_doorbell; 1944 /* 1945 ********************************************* 1946 ** check outbound intstatus 1947 ********************************************* 1948 */ 1949 outbound_doorbell = CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & acb->outbound_int_enable; 1950 if(!outbound_doorbell) { 1951 /*it must be share irq*/ 1952 return; 1953 } 1954 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ~outbound_doorbell); /* clear doorbell interrupt */ 1955 CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell); 1956 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 1957 /* MU ioctl transfer doorbell interrupts*/ 1958 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) { 1959 arcmsr_iop2drv_data_wrote_handle(acb); 1960 } 1961 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) { 1962 arcmsr_iop2drv_data_read_handle(acb); 1963 } 1964 /* MU post queue interrupts*/ 1965 if(outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) { 1966 arcmsr_hbb_postqueue_isr(acb); 1967 } 1968 if(outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) { 1969 arcmsr_hbb_message_isr(acb); 1970 } 1971 } 1972 /* 1973 ********************************************************************** 1974 ********************************************************************** 1975 */ 1976 static void arcmsr_handle_hbc_isr( struct AdapterControlBlock *acb) 1977 { 1978 u_int32_t host_interrupt_status; 1979 /* 1980 ********************************************* 1981 ** check outbound intstatus 1982 ********************************************* 1983 */ 1984 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status); 1985 if(!host_interrupt_status) { 1986 /*it must be share irq*/ 1987 return; 1988 } 1989 /* MU doorbell interrupts*/ 1990 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) { 1991 arcmsr_hbc_doorbell_isr(acb); 1992 } 1993 /* MU post queue interrupts*/ 1994 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) { 1995 arcmsr_hbc_postqueue_isr(acb); 1996 } 1997 } 1998 /* 1999 ********************************************************************** 2000 ********************************************************************** 2001 */ 2002 static void arcmsr_handle_hbd_isr( struct AdapterControlBlock *acb) 2003 { 2004 u_int32_t host_interrupt_status; 2005 u_int32_t intmask_org; 2006 /* 2007 ********************************************* 2008 ** check outbound intstatus 2009 ********************************************* 2010 */ 2011 host_interrupt_status = CHIP_REG_READ32(HBD_MessageUnit, 0, host_int_status) & acb->outbound_int_enable; 2012 if(!(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_INT)) { 2013 /*it must be share irq*/ 2014 return; 2015 } 2016 /* disable outbound interrupt */ 2017 intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable) ; /* disable outbound message0 int */ 2018 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE); 2019 /* MU doorbell interrupts*/ 2020 if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT) { 2021 arcmsr_hbd_doorbell_isr(acb); 2022 } 2023 /* MU post queue interrupts*/ 2024 if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT) { 2025 arcmsr_hbd_postqueue_isr(acb); 2026 } 2027 /* enable all outbound interrupt */ 2028 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | ARCMSR_HBDMU_ALL_INT_ENABLE); 2029 // CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); 2030 } 2031 /* 2032 ****************************************************************************** 2033 ****************************************************************************** 2034 */ 2035 static void arcmsr_interrupt(struct AdapterControlBlock *acb) 2036 { 2037 switch (acb->adapter_type) { 2038 case ACB_ADAPTER_TYPE_A: 2039 arcmsr_handle_hba_isr(acb); 2040 break; 2041 case ACB_ADAPTER_TYPE_B: 2042 arcmsr_handle_hbb_isr(acb); 2043 break; 2044 case ACB_ADAPTER_TYPE_C: 2045 arcmsr_handle_hbc_isr(acb); 2046 break; 2047 case ACB_ADAPTER_TYPE_D: 2048 arcmsr_handle_hbd_isr(acb); 2049 break; 2050 default: 2051 printf("arcmsr%d: interrupt service," 2052 " unknown adapter type =%d\n", acb->pci_unit, acb->adapter_type); 2053 break; 2054 } 2055 } 2056 /* 2057 ********************************************************************** 2058 ********************************************************************** 2059 */ 2060 static void arcmsr_intr_handler(void *arg) 2061 { 2062 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg; 2063 2064 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 2065 arcmsr_interrupt(acb); 2066 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 2067 } 2068 /* 2069 ****************************************************************************** 2070 ****************************************************************************** 2071 */ 2072 static void arcmsr_polling_devmap(void *arg) 2073 { 2074 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg; 2075 switch (acb->adapter_type) { 2076 case ACB_ADAPTER_TYPE_A: 2077 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2078 break; 2079 2080 case ACB_ADAPTER_TYPE_B: 2081 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG); 2082 break; 2083 2084 case ACB_ADAPTER_TYPE_C: 2085 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2086 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 2087 break; 2088 2089 case ACB_ADAPTER_TYPE_D: 2090 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2091 break; 2092 } 2093 2094 if((acb->acb_flags & ACB_F_SCSISTOPADAPTER) == 0) 2095 { 2096 callout_reset(&acb->devmap_callout, 5 * hz, arcmsr_polling_devmap, acb); /* polling per 5 seconds */ 2097 } 2098 } 2099 2100 /* 2101 ******************************************************************************* 2102 ** 2103 ******************************************************************************* 2104 */ 2105 static void arcmsr_iop_parking(struct AdapterControlBlock *acb) 2106 { 2107 u_int32_t intmask_org; 2108 2109 if(acb != NULL) { 2110 /* stop adapter background rebuild */ 2111 if(acb->acb_flags & ACB_F_MSG_START_BGRB) { 2112 intmask_org = arcmsr_disable_allintr(acb); 2113 arcmsr_stop_adapter_bgrb(acb); 2114 arcmsr_flush_adapter_cache(acb); 2115 arcmsr_enable_allintr(acb, intmask_org); 2116 } 2117 } 2118 } 2119 /* 2120 *********************************************************************** 2121 ** 2122 ************************************************************************ 2123 */ 2124 u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg) 2125 { 2126 struct CMD_MESSAGE_FIELD *pcmdmessagefld; 2127 u_int32_t retvalue = EINVAL; 2128 2129 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) arg; 2130 if(memcmp(pcmdmessagefld->cmdmessage.Signature, "ARCMSR", 6)!=0) { 2131 return retvalue; 2132 } 2133 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2134 switch(ioctl_cmd) { 2135 case ARCMSR_MESSAGE_READ_RQBUFFER: { 2136 u_int8_t *pQbuffer; 2137 u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer; 2138 u_int32_t allxfer_len=0; 2139 2140 while((acb->rqbuf_firstindex != acb->rqbuf_lastindex) 2141 && (allxfer_len < 1031)) { 2142 /*copy READ QBUFFER to srb*/ 2143 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex]; 2144 *ptmpQbuffer = *pQbuffer; 2145 acb->rqbuf_firstindex++; 2146 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 2147 /*if last index number set it to 0 */ 2148 ptmpQbuffer++; 2149 allxfer_len++; 2150 } 2151 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2152 struct QBUFFER *prbuffer; 2153 2154 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2155 prbuffer = arcmsr_get_iop_rqbuffer(acb); 2156 arcmsr_Read_iop_rqbuffer_data(acb, prbuffer); 2157 } 2158 pcmdmessagefld->cmdmessage.Length = allxfer_len; 2159 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2160 retvalue = ARCMSR_MESSAGE_SUCCESS; 2161 } 2162 break; 2163 case ARCMSR_MESSAGE_WRITE_WQBUFFER: { 2164 u_int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex; 2165 u_int8_t *pQbuffer; 2166 u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer; 2167 2168 user_len = pcmdmessagefld->cmdmessage.Length; 2169 /*check if data xfer length of this request will overflow my array qbuffer */ 2170 wqbuf_lastindex = acb->wqbuf_lastindex; 2171 wqbuf_firstindex = acb->wqbuf_firstindex; 2172 if(wqbuf_lastindex != wqbuf_firstindex) { 2173 arcmsr_Write_data_2iop_wqbuffer(acb); 2174 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2175 } else { 2176 my_empty_len = (wqbuf_firstindex - wqbuf_lastindex - 1) & 2177 (ARCMSR_MAX_QBUFFER - 1); 2178 if(my_empty_len >= user_len) { 2179 while(user_len > 0) { 2180 /*copy srb data to wqbuffer*/ 2181 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex]; 2182 *pQbuffer = *ptmpuserbuffer; 2183 acb->wqbuf_lastindex++; 2184 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 2185 /*if last index number set it to 0 */ 2186 ptmpuserbuffer++; 2187 user_len--; 2188 } 2189 /*post fist Qbuffer*/ 2190 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) { 2191 acb->acb_flags &= ~ACB_F_MESSAGE_WQBUFFER_CLEARED; 2192 arcmsr_Write_data_2iop_wqbuffer(acb); 2193 } 2194 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2195 } else { 2196 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2197 } 2198 } 2199 retvalue = ARCMSR_MESSAGE_SUCCESS; 2200 } 2201 break; 2202 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: { 2203 u_int8_t *pQbuffer = acb->rqbuffer; 2204 2205 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2206 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2207 arcmsr_iop_message_read(acb); 2208 /*signature, let IOP know data has been readed */ 2209 } 2210 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 2211 acb->rqbuf_firstindex = 0; 2212 acb->rqbuf_lastindex = 0; 2213 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2214 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2215 retvalue = ARCMSR_MESSAGE_SUCCESS; 2216 } 2217 break; 2218 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: 2219 { 2220 u_int8_t *pQbuffer = acb->wqbuffer; 2221 2222 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2223 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2224 arcmsr_iop_message_read(acb); 2225 /*signature, let IOP know data has been readed */ 2226 } 2227 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ); 2228 acb->wqbuf_firstindex = 0; 2229 acb->wqbuf_lastindex = 0; 2230 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2231 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2232 retvalue = ARCMSR_MESSAGE_SUCCESS; 2233 } 2234 break; 2235 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: { 2236 u_int8_t *pQbuffer; 2237 2238 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2239 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2240 arcmsr_iop_message_read(acb); 2241 /*signature, let IOP know data has been readed */ 2242 } 2243 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED 2244 |ACB_F_MESSAGE_RQBUFFER_CLEARED 2245 |ACB_F_MESSAGE_WQBUFFER_READ); 2246 acb->rqbuf_firstindex = 0; 2247 acb->rqbuf_lastindex = 0; 2248 acb->wqbuf_firstindex = 0; 2249 acb->wqbuf_lastindex = 0; 2250 pQbuffer = acb->rqbuffer; 2251 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 2252 pQbuffer = acb->wqbuffer; 2253 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 2254 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2255 retvalue = ARCMSR_MESSAGE_SUCCESS; 2256 } 2257 break; 2258 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: { 2259 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F; 2260 retvalue = ARCMSR_MESSAGE_SUCCESS; 2261 } 2262 break; 2263 case ARCMSR_MESSAGE_SAY_HELLO: { 2264 u_int8_t *hello_string = "Hello! I am ARCMSR"; 2265 u_int8_t *puserbuffer = (u_int8_t *)pcmdmessagefld->messagedatabuffer; 2266 2267 if(memcpy(puserbuffer, hello_string, (int16_t)strlen(hello_string))) { 2268 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2269 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2270 return ENOIOCTL; 2271 } 2272 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2273 retvalue = ARCMSR_MESSAGE_SUCCESS; 2274 } 2275 break; 2276 case ARCMSR_MESSAGE_SAY_GOODBYE: { 2277 arcmsr_iop_parking(acb); 2278 retvalue = ARCMSR_MESSAGE_SUCCESS; 2279 } 2280 break; 2281 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: { 2282 arcmsr_flush_adapter_cache(acb); 2283 retvalue = ARCMSR_MESSAGE_SUCCESS; 2284 } 2285 break; 2286 } 2287 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2288 return (retvalue); 2289 } 2290 /* 2291 ************************************************************************** 2292 ************************************************************************** 2293 */ 2294 static void arcmsr_free_srb(struct CommandControlBlock *srb) 2295 { 2296 struct AdapterControlBlock *acb; 2297 2298 acb = srb->acb; 2299 ARCMSR_LOCK_ACQUIRE(&acb->srb_lock); 2300 srb->srb_state = ARCMSR_SRB_DONE; 2301 srb->srb_flags = 0; 2302 acb->srbworkingQ[acb->workingsrb_doneindex] = srb; 2303 acb->workingsrb_doneindex++; 2304 acb->workingsrb_doneindex %= ARCMSR_MAX_FREESRB_NUM; 2305 ARCMSR_LOCK_RELEASE(&acb->srb_lock); 2306 } 2307 /* 2308 ************************************************************************** 2309 ************************************************************************** 2310 */ 2311 struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb) 2312 { 2313 struct CommandControlBlock *srb = NULL; 2314 u_int32_t workingsrb_startindex, workingsrb_doneindex; 2315 2316 ARCMSR_LOCK_ACQUIRE(&acb->srb_lock); 2317 workingsrb_doneindex = acb->workingsrb_doneindex; 2318 workingsrb_startindex = acb->workingsrb_startindex; 2319 srb = acb->srbworkingQ[workingsrb_startindex]; 2320 workingsrb_startindex++; 2321 workingsrb_startindex %= ARCMSR_MAX_FREESRB_NUM; 2322 if(workingsrb_doneindex != workingsrb_startindex) { 2323 acb->workingsrb_startindex = workingsrb_startindex; 2324 } else { 2325 srb = NULL; 2326 } 2327 ARCMSR_LOCK_RELEASE(&acb->srb_lock); 2328 return(srb); 2329 } 2330 /* 2331 ************************************************************************** 2332 ************************************************************************** 2333 */ 2334 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb) 2335 { 2336 struct CMD_MESSAGE_FIELD *pcmdmessagefld; 2337 int retvalue = 0, transfer_len = 0; 2338 char *buffer; 2339 u_int32_t controlcode = (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[5] << 24 | 2340 (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[6] << 16 | 2341 (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[7] << 8 | 2342 (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[8]; 2343 /* 4 bytes: Areca io control code */ 2344 if ((pccb->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_VADDR) { 2345 buffer = pccb->csio.data_ptr; 2346 transfer_len = pccb->csio.dxfer_len; 2347 } else { 2348 retvalue = ARCMSR_MESSAGE_FAIL; 2349 goto message_out; 2350 } 2351 if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) { 2352 retvalue = ARCMSR_MESSAGE_FAIL; 2353 goto message_out; 2354 } 2355 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) buffer; 2356 switch(controlcode) { 2357 case ARCMSR_MESSAGE_READ_RQBUFFER: { 2358 u_int8_t *pQbuffer; 2359 u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer; 2360 int32_t allxfer_len = 0; 2361 2362 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2363 while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex) 2364 && (allxfer_len < 1031)) { 2365 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex]; 2366 *ptmpQbuffer = *pQbuffer; 2367 acb->rqbuf_firstindex++; 2368 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 2369 ptmpQbuffer++; 2370 allxfer_len++; 2371 } 2372 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2373 struct QBUFFER *prbuffer; 2374 2375 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2376 prbuffer = arcmsr_get_iop_rqbuffer(acb); 2377 arcmsr_Read_iop_rqbuffer_data(acb, prbuffer); 2378 } 2379 pcmdmessagefld->cmdmessage.Length = allxfer_len; 2380 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2381 retvalue = ARCMSR_MESSAGE_SUCCESS; 2382 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2383 } 2384 break; 2385 case ARCMSR_MESSAGE_WRITE_WQBUFFER: { 2386 int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex; 2387 u_int8_t *pQbuffer; 2388 u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer; 2389 2390 user_len = pcmdmessagefld->cmdmessage.Length; 2391 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2392 wqbuf_lastindex = acb->wqbuf_lastindex; 2393 wqbuf_firstindex = acb->wqbuf_firstindex; 2394 if (wqbuf_lastindex != wqbuf_firstindex) { 2395 arcmsr_Write_data_2iop_wqbuffer(acb); 2396 /* has error report sensedata */ 2397 if(pccb->csio.sense_len) { 2398 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); 2399 /* Valid,ErrorCode */ 2400 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05; 2401 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */ 2402 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A; 2403 /* AdditionalSenseLength */ 2404 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20; 2405 /* AdditionalSenseCode */ 2406 } 2407 retvalue = ARCMSR_MESSAGE_FAIL; 2408 } else { 2409 my_empty_len = (wqbuf_firstindex-wqbuf_lastindex - 1) 2410 &(ARCMSR_MAX_QBUFFER - 1); 2411 if (my_empty_len >= user_len) { 2412 while (user_len > 0) { 2413 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex]; 2414 *pQbuffer = *ptmpuserbuffer; 2415 acb->wqbuf_lastindex++; 2416 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 2417 ptmpuserbuffer++; 2418 user_len--; 2419 } 2420 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) { 2421 acb->acb_flags &= 2422 ~ACB_F_MESSAGE_WQBUFFER_CLEARED; 2423 arcmsr_Write_data_2iop_wqbuffer(acb); 2424 } 2425 } else { 2426 /* has error report sensedata */ 2427 if(pccb->csio.sense_len) { 2428 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); 2429 /* Valid,ErrorCode */ 2430 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05; 2431 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */ 2432 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A; 2433 /* AdditionalSenseLength */ 2434 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20; 2435 /* AdditionalSenseCode */ 2436 } 2437 retvalue = ARCMSR_MESSAGE_FAIL; 2438 } 2439 } 2440 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2441 } 2442 break; 2443 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: { 2444 u_int8_t *pQbuffer = acb->rqbuffer; 2445 2446 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2447 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2448 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2449 arcmsr_iop_message_read(acb); 2450 } 2451 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 2452 acb->rqbuf_firstindex = 0; 2453 acb->rqbuf_lastindex = 0; 2454 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2455 pcmdmessagefld->cmdmessage.ReturnCode = 2456 ARCMSR_MESSAGE_RETURNCODE_OK; 2457 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2458 } 2459 break; 2460 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: { 2461 u_int8_t *pQbuffer = acb->wqbuffer; 2462 2463 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2464 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2465 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2466 arcmsr_iop_message_read(acb); 2467 } 2468 acb->acb_flags |= 2469 (ACB_F_MESSAGE_WQBUFFER_CLEARED | 2470 ACB_F_MESSAGE_WQBUFFER_READ); 2471 acb->wqbuf_firstindex = 0; 2472 acb->wqbuf_lastindex = 0; 2473 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2474 pcmdmessagefld->cmdmessage.ReturnCode = 2475 ARCMSR_MESSAGE_RETURNCODE_OK; 2476 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2477 } 2478 break; 2479 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: { 2480 u_int8_t *pQbuffer; 2481 2482 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2483 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2484 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2485 arcmsr_iop_message_read(acb); 2486 } 2487 acb->acb_flags |= 2488 (ACB_F_MESSAGE_WQBUFFER_CLEARED 2489 | ACB_F_MESSAGE_RQBUFFER_CLEARED 2490 | ACB_F_MESSAGE_WQBUFFER_READ); 2491 acb->rqbuf_firstindex = 0; 2492 acb->rqbuf_lastindex = 0; 2493 acb->wqbuf_firstindex = 0; 2494 acb->wqbuf_lastindex = 0; 2495 pQbuffer = acb->rqbuffer; 2496 memset(pQbuffer, 0, sizeof (struct QBUFFER)); 2497 pQbuffer = acb->wqbuffer; 2498 memset(pQbuffer, 0, sizeof (struct QBUFFER)); 2499 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2500 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2501 } 2502 break; 2503 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: { 2504 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F; 2505 } 2506 break; 2507 case ARCMSR_MESSAGE_SAY_HELLO: { 2508 int8_t *hello_string = "Hello! I am ARCMSR"; 2509 2510 memcpy(pcmdmessagefld->messagedatabuffer, hello_string 2511 , (int16_t)strlen(hello_string)); 2512 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2513 } 2514 break; 2515 case ARCMSR_MESSAGE_SAY_GOODBYE: 2516 arcmsr_iop_parking(acb); 2517 break; 2518 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: 2519 arcmsr_flush_adapter_cache(acb); 2520 break; 2521 default: 2522 retvalue = ARCMSR_MESSAGE_FAIL; 2523 } 2524 message_out: 2525 return (retvalue); 2526 } 2527 /* 2528 ********************************************************************* 2529 ********************************************************************* 2530 */ 2531 static void arcmsr_execute_srb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 2532 { 2533 struct CommandControlBlock *srb = (struct CommandControlBlock *)arg; 2534 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)srb->acb; 2535 union ccb *pccb; 2536 int target, lun; 2537 2538 pccb = srb->pccb; 2539 target = pccb->ccb_h.target_id; 2540 lun = pccb->ccb_h.target_lun; 2541 acb->pktRequestCount++; 2542 if(error != 0) { 2543 if(error != EFBIG) { 2544 printf("arcmsr%d: unexpected error %x" 2545 " returned from 'bus_dmamap_load' \n" 2546 , acb->pci_unit, error); 2547 } 2548 if((pccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_INPROG) { 2549 pccb->ccb_h.status |= CAM_REQ_TOO_BIG; 2550 } 2551 arcmsr_srb_complete(srb, 0); 2552 return; 2553 } 2554 if(nseg > ARCMSR_MAX_SG_ENTRIES) { 2555 pccb->ccb_h.status |= CAM_REQ_TOO_BIG; 2556 arcmsr_srb_complete(srb, 0); 2557 return; 2558 } 2559 if(acb->acb_flags & ACB_F_BUS_RESET) { 2560 printf("arcmsr%d: bus reset and return busy \n", acb->pci_unit); 2561 pccb->ccb_h.status |= CAM_SCSI_BUS_RESET; 2562 arcmsr_srb_complete(srb, 0); 2563 return; 2564 } 2565 if(acb->devstate[target][lun] == ARECA_RAID_GONE) { 2566 u_int8_t block_cmd, cmd; 2567 2568 cmd = pccb->csio.cdb_io.cdb_bytes[0]; 2569 block_cmd = cmd & 0x0f; 2570 if(block_cmd == 0x08 || block_cmd == 0x0a) { 2571 printf("arcmsr%d:block 'read/write' command " 2572 "with gone raid volume Cmd=0x%2x, TargetId=%d, Lun=%d \n" 2573 , acb->pci_unit, cmd, target, lun); 2574 pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 2575 arcmsr_srb_complete(srb, 0); 2576 return; 2577 } 2578 } 2579 if((pccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_INPROG) { 2580 if(nseg != 0) { 2581 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap); 2582 } 2583 arcmsr_srb_complete(srb, 0); 2584 return; 2585 } 2586 if(acb->srboutstandingcount >= acb->firm_numbers_queue) { 2587 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) == 0) 2588 { 2589 xpt_freeze_simq(acb->psim, 1); 2590 acb->acb_flags |= ACB_F_CAM_DEV_QFRZN; 2591 } 2592 pccb->ccb_h.status &= ~CAM_SIM_QUEUED; 2593 pccb->ccb_h.status |= CAM_REQUEUE_REQ; 2594 arcmsr_srb_complete(srb, 0); 2595 return; 2596 } 2597 pccb->ccb_h.status |= CAM_SIM_QUEUED; 2598 arcmsr_build_srb(srb, dm_segs, nseg); 2599 arcmsr_post_srb(acb, srb); 2600 if (pccb->ccb_h.timeout != CAM_TIME_INFINITY) 2601 { 2602 arcmsr_callout_init(&srb->ccb_callout); 2603 callout_reset(&srb->ccb_callout, ((pccb->ccb_h.timeout + (ARCMSR_TIMEOUT_DELAY * 1000)) * hz) / 1000, arcmsr_srb_timeout, srb); 2604 srb->srb_flags |= SRB_FLAG_TIMER_START; 2605 } 2606 } 2607 /* 2608 ***************************************************************************************** 2609 ***************************************************************************************** 2610 */ 2611 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb) 2612 { 2613 struct CommandControlBlock *srb; 2614 struct AdapterControlBlock *acb = (struct AdapterControlBlock *) abortccb->ccb_h.arcmsr_ccbacb_ptr; 2615 u_int32_t intmask_org; 2616 int i = 0; 2617 2618 acb->num_aborts++; 2619 /* 2620 *************************************************************************** 2621 ** It is the upper layer do abort command this lock just prior to calling us. 2622 ** First determine if we currently own this command. 2623 ** Start by searching the device queue. If not found 2624 ** at all, and the system wanted us to just abort the 2625 ** command return success. 2626 *************************************************************************** 2627 */ 2628 if(acb->srboutstandingcount != 0) { 2629 /* disable all outbound interrupt */ 2630 intmask_org = arcmsr_disable_allintr(acb); 2631 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 2632 srb = acb->psrb_pool[i]; 2633 if(srb->srb_state == ARCMSR_SRB_START) { 2634 if(srb->pccb == abortccb) { 2635 srb->srb_state = ARCMSR_SRB_ABORTED; 2636 printf("arcmsr%d:scsi id=%d lun=%d abort srb '%p'" 2637 "outstanding command \n" 2638 , acb->pci_unit, abortccb->ccb_h.target_id 2639 , abortccb->ccb_h.target_lun, srb); 2640 arcmsr_polling_srbdone(acb, srb); 2641 /* enable outbound Post Queue, outbound doorbell Interrupt */ 2642 arcmsr_enable_allintr(acb, intmask_org); 2643 return (TRUE); 2644 } 2645 } 2646 } 2647 /* enable outbound Post Queue, outbound doorbell Interrupt */ 2648 arcmsr_enable_allintr(acb, intmask_org); 2649 } 2650 return(FALSE); 2651 } 2652 /* 2653 **************************************************************************** 2654 **************************************************************************** 2655 */ 2656 static void arcmsr_bus_reset(struct AdapterControlBlock *acb) 2657 { 2658 int retry = 0; 2659 2660 acb->num_resets++; 2661 acb->acb_flags |= ACB_F_BUS_RESET; 2662 while(acb->srboutstandingcount != 0 && retry < 400) { 2663 arcmsr_interrupt(acb); 2664 UDELAY(25000); 2665 retry++; 2666 } 2667 arcmsr_iop_reset(acb); 2668 acb->acb_flags &= ~ACB_F_BUS_RESET; 2669 } 2670 /* 2671 ************************************************************************** 2672 ************************************************************************** 2673 */ 2674 static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb, 2675 union ccb *pccb) 2676 { 2677 if (pccb->ccb_h.target_lun) { 2678 pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 2679 xpt_done(pccb); 2680 return; 2681 } 2682 pccb->ccb_h.status |= CAM_REQ_CMP; 2683 switch (pccb->csio.cdb_io.cdb_bytes[0]) { 2684 case INQUIRY: { 2685 unsigned char inqdata[36]; 2686 char *buffer = pccb->csio.data_ptr; 2687 2688 inqdata[0] = T_PROCESSOR; /* Periph Qualifier & Periph Dev Type */ 2689 inqdata[1] = 0; /* rem media bit & Dev Type Modifier */ 2690 inqdata[2] = 0; /* ISO, ECMA, & ANSI versions */ 2691 inqdata[3] = 0; 2692 inqdata[4] = 31; /* length of additional data */ 2693 inqdata[5] = 0; 2694 inqdata[6] = 0; 2695 inqdata[7] = 0; 2696 strncpy(&inqdata[8], "Areca ", 8); /* Vendor Identification */ 2697 strncpy(&inqdata[16], "RAID controller ", 16); /* Product Identification */ 2698 strncpy(&inqdata[32], "R001", 4); /* Product Revision */ 2699 memcpy(buffer, inqdata, sizeof(inqdata)); 2700 xpt_done(pccb); 2701 } 2702 break; 2703 case WRITE_BUFFER: 2704 case READ_BUFFER: { 2705 if (arcmsr_iop_message_xfer(acb, pccb)) { 2706 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 2707 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 2708 } 2709 xpt_done(pccb); 2710 } 2711 break; 2712 default: 2713 xpt_done(pccb); 2714 } 2715 } 2716 /* 2717 ********************************************************************* 2718 ********************************************************************* 2719 */ 2720 static void arcmsr_action(struct cam_sim *psim, union ccb *pccb) 2721 { 2722 struct AdapterControlBlock *acb; 2723 2724 acb = (struct AdapterControlBlock *) cam_sim_softc(psim); 2725 if(acb == NULL) { 2726 pccb->ccb_h.status |= CAM_REQ_INVALID; 2727 xpt_done(pccb); 2728 return; 2729 } 2730 switch (pccb->ccb_h.func_code) { 2731 case XPT_SCSI_IO: { 2732 struct CommandControlBlock *srb; 2733 int target = pccb->ccb_h.target_id; 2734 int error; 2735 2736 if(target == 16) { 2737 /* virtual device for iop message transfer */ 2738 arcmsr_handle_virtual_command(acb, pccb); 2739 return; 2740 } 2741 if((srb = arcmsr_get_freesrb(acb)) == NULL) { 2742 pccb->ccb_h.status |= CAM_RESRC_UNAVAIL; 2743 xpt_done(pccb); 2744 return; 2745 } 2746 pccb->ccb_h.arcmsr_ccbsrb_ptr = srb; 2747 pccb->ccb_h.arcmsr_ccbacb_ptr = acb; 2748 srb->pccb = pccb; 2749 error = bus_dmamap_load_ccb(acb->dm_segs_dmat 2750 , srb->dm_segs_dmamap 2751 , pccb 2752 , arcmsr_execute_srb, srb, /*flags*/0); 2753 if(error == EINPROGRESS) { 2754 xpt_freeze_simq(acb->psim, 1); 2755 pccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2756 } 2757 break; 2758 } 2759 case XPT_TARGET_IO: { 2760 /* target mode not yet support vendor specific commands. */ 2761 pccb->ccb_h.status |= CAM_REQ_CMP; 2762 xpt_done(pccb); 2763 break; 2764 } 2765 case XPT_PATH_INQ: { 2766 struct ccb_pathinq *cpi = &pccb->cpi; 2767 2768 cpi->version_num = 1; 2769 cpi->hba_inquiry = PI_SDTR_ABLE | PI_TAG_ABLE; 2770 cpi->target_sprt = 0; 2771 cpi->hba_misc = 0; 2772 cpi->hba_eng_cnt = 0; 2773 cpi->max_target = ARCMSR_MAX_TARGETID; /* 0-16 */ 2774 cpi->max_lun = ARCMSR_MAX_TARGETLUN; /* 0-7 */ 2775 cpi->initiator_id = ARCMSR_SCSI_INITIATOR_ID; /* 255 */ 2776 cpi->bus_id = cam_sim_bus(psim); 2777 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2778 strncpy(cpi->hba_vid, "ARCMSR", HBA_IDLEN); 2779 strncpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN); 2780 cpi->unit_number = cam_sim_unit(psim); 2781 #ifdef CAM_NEW_TRAN_CODE 2782 if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G) 2783 cpi->base_transfer_speed = 600000; 2784 else 2785 cpi->base_transfer_speed = 300000; 2786 if((acb->vendor_device_id == PCIDevVenIDARC1880) || 2787 (acb->vendor_device_id == PCIDevVenIDARC1680) || 2788 (acb->vendor_device_id == PCIDevVenIDARC1214)) 2789 { 2790 cpi->transport = XPORT_SAS; 2791 cpi->transport_version = 0; 2792 cpi->protocol_version = SCSI_REV_SPC2; 2793 } 2794 else 2795 { 2796 cpi->transport = XPORT_SPI; 2797 cpi->transport_version = 2; 2798 cpi->protocol_version = SCSI_REV_2; 2799 } 2800 cpi->protocol = PROTO_SCSI; 2801 #endif 2802 cpi->ccb_h.status |= CAM_REQ_CMP; 2803 xpt_done(pccb); 2804 break; 2805 } 2806 case XPT_ABORT: { 2807 union ccb *pabort_ccb; 2808 2809 pabort_ccb = pccb->cab.abort_ccb; 2810 switch (pabort_ccb->ccb_h.func_code) { 2811 case XPT_ACCEPT_TARGET_IO: 2812 case XPT_IMMED_NOTIFY: 2813 case XPT_CONT_TARGET_IO: 2814 if(arcmsr_seek_cmd2abort(pabort_ccb)==TRUE) { 2815 pabort_ccb->ccb_h.status |= CAM_REQ_ABORTED; 2816 xpt_done(pabort_ccb); 2817 pccb->ccb_h.status |= CAM_REQ_CMP; 2818 } else { 2819 xpt_print_path(pabort_ccb->ccb_h.path); 2820 printf("Not found\n"); 2821 pccb->ccb_h.status |= CAM_PATH_INVALID; 2822 } 2823 break; 2824 case XPT_SCSI_IO: 2825 pccb->ccb_h.status |= CAM_UA_ABORT; 2826 break; 2827 default: 2828 pccb->ccb_h.status |= CAM_REQ_INVALID; 2829 break; 2830 } 2831 xpt_done(pccb); 2832 break; 2833 } 2834 case XPT_RESET_BUS: 2835 case XPT_RESET_DEV: { 2836 u_int32_t i; 2837 2838 arcmsr_bus_reset(acb); 2839 for (i=0; i < 500; i++) { 2840 DELAY(1000); 2841 } 2842 pccb->ccb_h.status |= CAM_REQ_CMP; 2843 xpt_done(pccb); 2844 break; 2845 } 2846 case XPT_TERM_IO: { 2847 pccb->ccb_h.status |= CAM_REQ_INVALID; 2848 xpt_done(pccb); 2849 break; 2850 } 2851 case XPT_GET_TRAN_SETTINGS: { 2852 struct ccb_trans_settings *cts; 2853 2854 if(pccb->ccb_h.target_id == 16) { 2855 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 2856 xpt_done(pccb); 2857 break; 2858 } 2859 cts = &pccb->cts; 2860 #ifdef CAM_NEW_TRAN_CODE 2861 { 2862 struct ccb_trans_settings_scsi *scsi; 2863 struct ccb_trans_settings_spi *spi; 2864 struct ccb_trans_settings_sas *sas; 2865 2866 scsi = &cts->proto_specific.scsi; 2867 scsi->flags = CTS_SCSI_FLAGS_TAG_ENB; 2868 scsi->valid = CTS_SCSI_VALID_TQ; 2869 cts->protocol = PROTO_SCSI; 2870 2871 if((acb->vendor_device_id == PCIDevVenIDARC1880) || 2872 (acb->vendor_device_id == PCIDevVenIDARC1680) || 2873 (acb->vendor_device_id == PCIDevVenIDARC1214)) 2874 { 2875 cts->protocol_version = SCSI_REV_SPC2; 2876 cts->transport_version = 0; 2877 cts->transport = XPORT_SAS; 2878 sas = &cts->xport_specific.sas; 2879 sas->valid = CTS_SAS_VALID_SPEED; 2880 if((acb->vendor_device_id == PCIDevVenIDARC1880) || 2881 (acb->vendor_device_id == PCIDevVenIDARC1214)) 2882 sas->bitrate = 600000; 2883 else if(acb->vendor_device_id == PCIDevVenIDARC1680) 2884 sas->bitrate = 300000; 2885 } 2886 else 2887 { 2888 cts->protocol_version = SCSI_REV_2; 2889 cts->transport_version = 2; 2890 cts->transport = XPORT_SPI; 2891 spi = &cts->xport_specific.spi; 2892 spi->flags = CTS_SPI_FLAGS_DISC_ENB; 2893 spi->sync_period = 2; 2894 spi->sync_offset = 32; 2895 spi->bus_width = MSG_EXT_WDTR_BUS_16_BIT; 2896 spi->valid = CTS_SPI_VALID_DISC 2897 | CTS_SPI_VALID_SYNC_RATE 2898 | CTS_SPI_VALID_SYNC_OFFSET 2899 | CTS_SPI_VALID_BUS_WIDTH; 2900 } 2901 } 2902 #else 2903 { 2904 cts->flags = (CCB_TRANS_DISC_ENB | CCB_TRANS_TAG_ENB); 2905 cts->sync_period = 2; 2906 cts->sync_offset = 32; 2907 cts->bus_width = MSG_EXT_WDTR_BUS_16_BIT; 2908 cts->valid = CCB_TRANS_SYNC_RATE_VALID | 2909 CCB_TRANS_SYNC_OFFSET_VALID | 2910 CCB_TRANS_BUS_WIDTH_VALID | 2911 CCB_TRANS_DISC_VALID | 2912 CCB_TRANS_TQ_VALID; 2913 } 2914 #endif 2915 pccb->ccb_h.status |= CAM_REQ_CMP; 2916 xpt_done(pccb); 2917 break; 2918 } 2919 case XPT_SET_TRAN_SETTINGS: { 2920 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 2921 xpt_done(pccb); 2922 break; 2923 } 2924 case XPT_CALC_GEOMETRY: 2925 if(pccb->ccb_h.target_id == 16) { 2926 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 2927 xpt_done(pccb); 2928 break; 2929 } 2930 #if __FreeBSD_version >= 500000 2931 cam_calc_geometry(&pccb->ccg, 1); 2932 #else 2933 { 2934 struct ccb_calc_geometry *ccg; 2935 u_int32_t size_mb; 2936 u_int32_t secs_per_cylinder; 2937 2938 ccg = &pccb->ccg; 2939 if (ccg->block_size == 0) { 2940 pccb->ccb_h.status = CAM_REQ_INVALID; 2941 xpt_done(pccb); 2942 break; 2943 } 2944 if(((1024L * 1024L)/ccg->block_size) < 0) { 2945 pccb->ccb_h.status = CAM_REQ_INVALID; 2946 xpt_done(pccb); 2947 break; 2948 } 2949 size_mb = ccg->volume_size/((1024L * 1024L)/ccg->block_size); 2950 if(size_mb > 1024 ) { 2951 ccg->heads = 255; 2952 ccg->secs_per_track = 63; 2953 } else { 2954 ccg->heads = 64; 2955 ccg->secs_per_track = 32; 2956 } 2957 secs_per_cylinder = ccg->heads * ccg->secs_per_track; 2958 ccg->cylinders = ccg->volume_size / secs_per_cylinder; 2959 pccb->ccb_h.status |= CAM_REQ_CMP; 2960 } 2961 #endif 2962 xpt_done(pccb); 2963 break; 2964 default: 2965 pccb->ccb_h.status |= CAM_REQ_INVALID; 2966 xpt_done(pccb); 2967 break; 2968 } 2969 } 2970 /* 2971 ********************************************************************** 2972 ********************************************************************** 2973 */ 2974 static void arcmsr_start_hba_bgrb(struct AdapterControlBlock *acb) 2975 { 2976 acb->acb_flags |= ACB_F_MSG_START_BGRB; 2977 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 2978 if(!arcmsr_hba_wait_msgint_ready(acb)) { 2979 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 2980 } 2981 } 2982 /* 2983 ********************************************************************** 2984 ********************************************************************** 2985 */ 2986 static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb) 2987 { 2988 acb->acb_flags |= ACB_F_MSG_START_BGRB; 2989 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_START_BGRB); 2990 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 2991 printf( "arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 2992 } 2993 } 2994 /* 2995 ********************************************************************** 2996 ********************************************************************** 2997 */ 2998 static void arcmsr_start_hbc_bgrb(struct AdapterControlBlock *acb) 2999 { 3000 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3001 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3002 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3003 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 3004 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3005 } 3006 } 3007 /* 3008 ********************************************************************** 3009 ********************************************************************** 3010 */ 3011 static void arcmsr_start_hbd_bgrb(struct AdapterControlBlock *acb) 3012 { 3013 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3014 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3015 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 3016 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3017 } 3018 } 3019 /* 3020 ********************************************************************** 3021 ********************************************************************** 3022 */ 3023 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb) 3024 { 3025 switch (acb->adapter_type) { 3026 case ACB_ADAPTER_TYPE_A: 3027 arcmsr_start_hba_bgrb(acb); 3028 break; 3029 case ACB_ADAPTER_TYPE_B: 3030 arcmsr_start_hbb_bgrb(acb); 3031 break; 3032 case ACB_ADAPTER_TYPE_C: 3033 arcmsr_start_hbc_bgrb(acb); 3034 break; 3035 case ACB_ADAPTER_TYPE_D: 3036 arcmsr_start_hbd_bgrb(acb); 3037 break; 3038 } 3039 } 3040 /* 3041 ********************************************************************** 3042 ** 3043 ********************************************************************** 3044 */ 3045 static void arcmsr_polling_hba_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3046 { 3047 struct CommandControlBlock *srb; 3048 u_int32_t flag_srb, outbound_intstatus, poll_srb_done=0, poll_count=0; 3049 u_int16_t error; 3050 3051 polling_ccb_retry: 3052 poll_count++; 3053 outbound_intstatus=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 3054 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus); /*clear interrupt*/ 3055 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3056 while(1) { 3057 if((flag_srb = CHIP_REG_READ32(HBA_MessageUnit, 3058 0, outbound_queueport)) == 0xFFFFFFFF) { 3059 if(poll_srb_done) { 3060 break;/*chip FIFO no ccb for completion already*/ 3061 } else { 3062 UDELAY(25000); 3063 if ((poll_count > 100) && (poll_srb != NULL)) { 3064 break; 3065 } 3066 goto polling_ccb_retry; 3067 } 3068 } 3069 /* check if command done with no error*/ 3070 srb = (struct CommandControlBlock *) 3071 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 3072 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 3073 poll_srb_done = (srb == poll_srb) ? 1:0; 3074 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3075 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3076 printf("arcmsr%d: scsi id=%d lun=%d srb='%p'" 3077 "poll command abort successfully \n" 3078 , acb->pci_unit 3079 , srb->pccb->ccb_h.target_id 3080 , srb->pccb->ccb_h.target_lun, srb); 3081 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3082 arcmsr_srb_complete(srb, 1); 3083 continue; 3084 } 3085 printf("arcmsr%d: polling get an illegal srb command done srb='%p'" 3086 "srboutstandingcount=%d \n" 3087 , acb->pci_unit 3088 , srb, acb->srboutstandingcount); 3089 continue; 3090 } 3091 arcmsr_report_srb_state(acb, srb, error); 3092 } /*drain reply FIFO*/ 3093 } 3094 /* 3095 ********************************************************************** 3096 ** 3097 ********************************************************************** 3098 */ 3099 static void arcmsr_polling_hbb_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3100 { 3101 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3102 struct CommandControlBlock *srb; 3103 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3104 int index; 3105 u_int16_t error; 3106 3107 polling_ccb_retry: 3108 poll_count++; 3109 CHIP_REG_WRITE32(HBB_DOORBELL, 3110 0, iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */ 3111 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3112 while(1) { 3113 index = phbbmu->doneq_index; 3114 if((flag_srb = phbbmu->done_qbuffer[index]) == 0) { 3115 if(poll_srb_done) { 3116 break;/*chip FIFO no ccb for completion already*/ 3117 } else { 3118 UDELAY(25000); 3119 if ((poll_count > 100) && (poll_srb != NULL)) { 3120 break; 3121 } 3122 goto polling_ccb_retry; 3123 } 3124 } 3125 phbbmu->done_qbuffer[index] = 0; 3126 index++; 3127 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 3128 phbbmu->doneq_index = index; 3129 /* check if command done with no error*/ 3130 srb = (struct CommandControlBlock *) 3131 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 3132 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 3133 poll_srb_done = (srb == poll_srb) ? 1:0; 3134 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3135 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3136 printf("arcmsr%d: scsi id=%d lun=%d srb='%p'" 3137 "poll command abort successfully \n" 3138 , acb->pci_unit 3139 , srb->pccb->ccb_h.target_id 3140 , srb->pccb->ccb_h.target_lun, srb); 3141 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3142 arcmsr_srb_complete(srb, 1); 3143 continue; 3144 } 3145 printf("arcmsr%d: polling get an illegal srb command done srb='%p'" 3146 "srboutstandingcount=%d \n" 3147 , acb->pci_unit 3148 , srb, acb->srboutstandingcount); 3149 continue; 3150 } 3151 arcmsr_report_srb_state(acb, srb, error); 3152 } /*drain reply FIFO*/ 3153 } 3154 /* 3155 ********************************************************************** 3156 ** 3157 ********************************************************************** 3158 */ 3159 static void arcmsr_polling_hbc_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3160 { 3161 struct CommandControlBlock *srb; 3162 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3163 u_int16_t error; 3164 3165 polling_ccb_retry: 3166 poll_count++; 3167 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3168 while(1) { 3169 if(!(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)) { 3170 if(poll_srb_done) { 3171 break;/*chip FIFO no ccb for completion already*/ 3172 } else { 3173 UDELAY(25000); 3174 if ((poll_count > 100) && (poll_srb != NULL)) { 3175 break; 3176 } 3177 if (acb->srboutstandingcount == 0) { 3178 break; 3179 } 3180 goto polling_ccb_retry; 3181 } 3182 } 3183 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 3184 /* check if command done with no error*/ 3185 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/ 3186 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE; 3187 if (poll_srb != NULL) 3188 poll_srb_done = (srb == poll_srb) ? 1:0; 3189 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3190 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3191 printf("arcmsr%d: scsi id=%d lun=%d srb='%p'poll command abort successfully \n" 3192 , acb->pci_unit, srb->pccb->ccb_h.target_id, srb->pccb->ccb_h.target_lun, srb); 3193 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3194 arcmsr_srb_complete(srb, 1); 3195 continue; 3196 } 3197 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 3198 , acb->pci_unit, srb, acb->srboutstandingcount); 3199 continue; 3200 } 3201 arcmsr_report_srb_state(acb, srb, error); 3202 } /*drain reply FIFO*/ 3203 } 3204 /* 3205 ********************************************************************** 3206 ** 3207 ********************************************************************** 3208 */ 3209 static void arcmsr_polling_hbd_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3210 { 3211 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 3212 struct CommandControlBlock *srb; 3213 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3214 u_int32_t outbound_write_pointer; 3215 u_int16_t error, doneq_index; 3216 3217 polling_ccb_retry: 3218 poll_count++; 3219 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3220 while(1) { 3221 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 3222 doneq_index = phbdmu->doneq_index; 3223 if ((outbound_write_pointer & 0xFF) == (doneq_index & 0xFF)) { 3224 if(poll_srb_done) { 3225 break;/*chip FIFO no ccb for completion already*/ 3226 } else { 3227 UDELAY(25000); 3228 if ((poll_count > 100) && (poll_srb != NULL)) { 3229 break; 3230 } 3231 if (acb->srboutstandingcount == 0) { 3232 break; 3233 } 3234 goto polling_ccb_retry; 3235 } 3236 } 3237 doneq_index = arcmsr_get_doneq_index(phbdmu); 3238 flag_srb = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow; 3239 /* check if command done with no error*/ 3240 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/ 3241 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 3242 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index); 3243 if (poll_srb != NULL) 3244 poll_srb_done = (srb == poll_srb) ? 1:0; 3245 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3246 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3247 printf("arcmsr%d: scsi id=%d lun=%d srb='%p'poll command abort successfully \n" 3248 , acb->pci_unit, srb->pccb->ccb_h.target_id, srb->pccb->ccb_h.target_lun, srb); 3249 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3250 arcmsr_srb_complete(srb, 1); 3251 continue; 3252 } 3253 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 3254 , acb->pci_unit, srb, acb->srboutstandingcount); 3255 continue; 3256 } 3257 arcmsr_report_srb_state(acb, srb, error); 3258 } /*drain reply FIFO*/ 3259 } 3260 /* 3261 ********************************************************************** 3262 ********************************************************************** 3263 */ 3264 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3265 { 3266 switch (acb->adapter_type) { 3267 case ACB_ADAPTER_TYPE_A: { 3268 arcmsr_polling_hba_srbdone(acb, poll_srb); 3269 } 3270 break; 3271 case ACB_ADAPTER_TYPE_B: { 3272 arcmsr_polling_hbb_srbdone(acb, poll_srb); 3273 } 3274 break; 3275 case ACB_ADAPTER_TYPE_C: { 3276 arcmsr_polling_hbc_srbdone(acb, poll_srb); 3277 } 3278 break; 3279 case ACB_ADAPTER_TYPE_D: { 3280 arcmsr_polling_hbd_srbdone(acb, poll_srb); 3281 } 3282 break; 3283 } 3284 } 3285 /* 3286 ********************************************************************** 3287 ********************************************************************** 3288 */ 3289 static void arcmsr_get_hba_config(struct AdapterControlBlock *acb) 3290 { 3291 char *acb_firm_model = acb->firm_model; 3292 char *acb_firm_version = acb->firm_version; 3293 char *acb_device_map = acb->device_map; 3294 size_t iop_firm_model = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3295 size_t iop_firm_version = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3296 size_t iop_device_map = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3297 int i; 3298 3299 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3300 if(!arcmsr_hba_wait_msgint_ready(acb)) { 3301 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3302 } 3303 i = 0; 3304 while(i < 8) { 3305 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3306 /* 8 bytes firm_model, 15, 60-67*/ 3307 acb_firm_model++; 3308 i++; 3309 } 3310 i=0; 3311 while(i < 16) { 3312 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3313 /* 16 bytes firm_version, 17, 68-83*/ 3314 acb_firm_version++; 3315 i++; 3316 } 3317 i=0; 3318 while(i < 16) { 3319 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3320 acb_device_map++; 3321 i++; 3322 } 3323 printf("ARECA RAID ADAPTER%d: %s \n", acb->pci_unit, ARCMSR_DRIVER_VERSION); 3324 printf("ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n", acb->pci_unit, acb->firm_version); 3325 acb->firm_request_len = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3326 acb->firm_numbers_queue = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3327 acb->firm_sdram_size = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3328 acb->firm_ide_channels = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3329 acb->firm_cfg_version = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3330 } 3331 /* 3332 ********************************************************************** 3333 ********************************************************************** 3334 */ 3335 static void arcmsr_get_hbb_config(struct AdapterControlBlock *acb) 3336 { 3337 char *acb_firm_model = acb->firm_model; 3338 char *acb_firm_version = acb->firm_version; 3339 char *acb_device_map = acb->device_map; 3340 size_t iop_firm_model = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3341 size_t iop_firm_version = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3342 size_t iop_device_map = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3343 int i; 3344 3345 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG); 3346 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3347 printf( "arcmsr%d: wait" "'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3348 } 3349 i = 0; 3350 while(i < 8) { 3351 *acb_firm_model = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_model+i); 3352 /* 8 bytes firm_model, 15, 60-67*/ 3353 acb_firm_model++; 3354 i++; 3355 } 3356 i = 0; 3357 while(i < 16) { 3358 *acb_firm_version = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_version+i); 3359 /* 16 bytes firm_version, 17, 68-83*/ 3360 acb_firm_version++; 3361 i++; 3362 } 3363 i = 0; 3364 while(i < 16) { 3365 *acb_device_map = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_device_map+i); 3366 acb_device_map++; 3367 i++; 3368 } 3369 printf("ARECA RAID ADAPTER%d: %s \n", acb->pci_unit, ARCMSR_DRIVER_VERSION); 3370 printf("ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n", acb->pci_unit, acb->firm_version); 3371 acb->firm_request_len = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3372 acb->firm_numbers_queue = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3373 acb->firm_sdram_size = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3374 acb->firm_ide_channels = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3375 acb->firm_cfg_version = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3376 } 3377 /* 3378 ********************************************************************** 3379 ********************************************************************** 3380 */ 3381 static void arcmsr_get_hbc_config(struct AdapterControlBlock *acb) 3382 { 3383 char *acb_firm_model = acb->firm_model; 3384 char *acb_firm_version = acb->firm_version; 3385 char *acb_device_map = acb->device_map; 3386 size_t iop_firm_model = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3387 size_t iop_firm_version = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3388 size_t iop_device_map = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3389 int i; 3390 3391 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3392 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3393 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 3394 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3395 } 3396 i = 0; 3397 while(i < 8) { 3398 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3399 /* 8 bytes firm_model, 15, 60-67*/ 3400 acb_firm_model++; 3401 i++; 3402 } 3403 i = 0; 3404 while(i < 16) { 3405 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3406 /* 16 bytes firm_version, 17, 68-83*/ 3407 acb_firm_version++; 3408 i++; 3409 } 3410 i = 0; 3411 while(i < 16) { 3412 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3413 acb_device_map++; 3414 i++; 3415 } 3416 printf("ARECA RAID ADAPTER%d: %s \n", acb->pci_unit, ARCMSR_DRIVER_VERSION); 3417 printf("ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n", acb->pci_unit, acb->firm_version); 3418 acb->firm_request_len = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3419 acb->firm_numbers_queue = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3420 acb->firm_sdram_size = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3421 acb->firm_ide_channels = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3422 acb->firm_cfg_version = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3423 } 3424 /* 3425 ********************************************************************** 3426 ********************************************************************** 3427 */ 3428 static void arcmsr_get_hbd_config(struct AdapterControlBlock *acb) 3429 { 3430 char *acb_firm_model = acb->firm_model; 3431 char *acb_firm_version = acb->firm_version; 3432 char *acb_device_map = acb->device_map; 3433 size_t iop_firm_model = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3434 size_t iop_firm_version = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3435 size_t iop_device_map = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3436 int i; 3437 3438 if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) 3439 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR); 3440 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3441 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 3442 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3443 } 3444 i = 0; 3445 while(i < 8) { 3446 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3447 /* 8 bytes firm_model, 15, 60-67*/ 3448 acb_firm_model++; 3449 i++; 3450 } 3451 i = 0; 3452 while(i < 16) { 3453 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3454 /* 16 bytes firm_version, 17, 68-83*/ 3455 acb_firm_version++; 3456 i++; 3457 } 3458 i = 0; 3459 while(i < 16) { 3460 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3461 acb_device_map++; 3462 i++; 3463 } 3464 printf("ARECA RAID ADAPTER%d: %s \n", acb->pci_unit, ARCMSR_DRIVER_VERSION); 3465 printf("ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n", acb->pci_unit, acb->firm_version); 3466 acb->firm_request_len = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_request_len, 1, 04-07*/ 3467 acb->firm_numbers_queue = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_numbers_queue, 2, 08-11*/ 3468 acb->firm_sdram_size = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_sdram_size, 3, 12-15*/ 3469 acb->firm_ide_channels = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[5]); /*firm_ide_channels, 4, 16-19*/ 3470 acb->firm_cfg_version = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3471 } 3472 /* 3473 ********************************************************************** 3474 ********************************************************************** 3475 */ 3476 static void arcmsr_get_firmware_spec(struct AdapterControlBlock *acb) 3477 { 3478 switch (acb->adapter_type) { 3479 case ACB_ADAPTER_TYPE_A: { 3480 arcmsr_get_hba_config(acb); 3481 } 3482 break; 3483 case ACB_ADAPTER_TYPE_B: { 3484 arcmsr_get_hbb_config(acb); 3485 } 3486 break; 3487 case ACB_ADAPTER_TYPE_C: { 3488 arcmsr_get_hbc_config(acb); 3489 } 3490 break; 3491 case ACB_ADAPTER_TYPE_D: { 3492 arcmsr_get_hbd_config(acb); 3493 } 3494 break; 3495 } 3496 } 3497 /* 3498 ********************************************************************** 3499 ********************************************************************** 3500 */ 3501 static void arcmsr_wait_firmware_ready( struct AdapterControlBlock *acb) 3502 { 3503 int timeout=0; 3504 3505 switch (acb->adapter_type) { 3506 case ACB_ADAPTER_TYPE_A: { 3507 while ((CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0) 3508 { 3509 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 3510 { 3511 printf( "arcmsr%d:timed out waiting for firmware \n", acb->pci_unit); 3512 return; 3513 } 3514 UDELAY(15000); /* wait 15 milli-seconds */ 3515 } 3516 } 3517 break; 3518 case ACB_ADAPTER_TYPE_B: { 3519 while ((CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & ARCMSR_MESSAGE_FIRMWARE_OK) == 0) 3520 { 3521 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 3522 { 3523 printf( "arcmsr%d: timed out waiting for firmware \n", acb->pci_unit); 3524 return; 3525 } 3526 UDELAY(15000); /* wait 15 milli-seconds */ 3527 } 3528 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 3529 } 3530 break; 3531 case ACB_ADAPTER_TYPE_C: { 3532 while ((CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0) 3533 { 3534 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 3535 { 3536 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 3537 return; 3538 } 3539 UDELAY(15000); /* wait 15 milli-seconds */ 3540 } 3541 } 3542 break; 3543 case ACB_ADAPTER_TYPE_D: { 3544 while ((CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK) == 0) 3545 { 3546 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 3547 { 3548 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 3549 return; 3550 } 3551 UDELAY(15000); /* wait 15 milli-seconds */ 3552 } 3553 } 3554 break; 3555 } 3556 } 3557 /* 3558 ********************************************************************** 3559 ********************************************************************** 3560 */ 3561 static void arcmsr_clear_doorbell_queue_buffer( struct AdapterControlBlock *acb) 3562 { 3563 u_int32_t outbound_doorbell; 3564 3565 switch (acb->adapter_type) { 3566 case ACB_ADAPTER_TYPE_A: { 3567 /* empty doorbell Qbuffer if door bell ringed */ 3568 outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell); 3569 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */ 3570 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK); 3571 3572 } 3573 break; 3574 case ACB_ADAPTER_TYPE_B: { 3575 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt and message state*/ 3576 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK); 3577 /* let IOP know data has been read */ 3578 } 3579 break; 3580 case ACB_ADAPTER_TYPE_C: { 3581 /* empty doorbell Qbuffer if door bell ringed */ 3582 outbound_doorbell = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell); 3583 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell); /*clear doorbell interrupt */ 3584 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK); 3585 CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell_clear); /* Dummy read to force pci flush */ 3586 CHIP_REG_READ32(HBC_MessageUnit, 0, inbound_doorbell); /* Dummy read to force pci flush */ 3587 } 3588 break; 3589 case ACB_ADAPTER_TYPE_D: { 3590 /* empty doorbell Qbuffer if door bell ringed */ 3591 outbound_doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell); 3592 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */ 3593 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ); 3594 3595 } 3596 break; 3597 } 3598 } 3599 /* 3600 ************************************************************************ 3601 ************************************************************************ 3602 */ 3603 static u_int32_t arcmsr_iop_confirm(struct AdapterControlBlock *acb) 3604 { 3605 unsigned long srb_phyaddr; 3606 u_int32_t srb_phyaddr_hi32; 3607 u_int32_t srb_phyaddr_lo32; 3608 3609 /* 3610 ******************************************************************** 3611 ** here we need to tell iop 331 our freesrb.HighPart 3612 ** if freesrb.HighPart is not zero 3613 ******************************************************************** 3614 */ 3615 srb_phyaddr = (unsigned long) acb->srb_phyaddr.phyaddr; 3616 srb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high; 3617 srb_phyaddr_lo32 = acb->srb_phyaddr.B.phyadd_low; 3618 switch (acb->adapter_type) { 3619 case ACB_ADAPTER_TYPE_A: { 3620 if(srb_phyaddr_hi32 != 0) { 3621 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 3622 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 3623 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 3624 if(!arcmsr_hba_wait_msgint_ready(acb)) { 3625 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 3626 return FALSE; 3627 } 3628 } 3629 } 3630 break; 3631 /* 3632 *********************************************************************** 3633 ** if adapter type B, set window of "post command Q" 3634 *********************************************************************** 3635 */ 3636 case ACB_ADAPTER_TYPE_B: { 3637 u_int32_t post_queue_phyaddr; 3638 struct HBB_MessageUnit *phbbmu; 3639 3640 phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3641 phbbmu->postq_index = 0; 3642 phbbmu->doneq_index = 0; 3643 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_SET_POST_WINDOW); 3644 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3645 printf( "arcmsr%d: 'set window of post command Q' timeout\n", acb->pci_unit); 3646 return FALSE; 3647 } 3648 post_queue_phyaddr = srb_phyaddr + ARCMSR_SRBS_POOL_SIZE 3649 + offsetof(struct HBB_MessageUnit, post_qbuffer); 3650 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */ 3651 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1], srb_phyaddr_hi32); /* normal should be zero */ 3652 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ size (256+8)*4 */ 3653 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3], post_queue_phyaddr+1056); /* doneQ size (256+8)*4 */ 3654 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4], 1056); /* srb maxQ size must be --> [(256+8)*4] */ 3655 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_SET_CONFIG); 3656 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3657 printf( "arcmsr%d: 'set command Q window' timeout \n", acb->pci_unit); 3658 return FALSE; 3659 } 3660 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_START_DRIVER_MODE); 3661 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3662 printf( "arcmsr%d: 'start diver mode' timeout \n", acb->pci_unit); 3663 return FALSE; 3664 } 3665 } 3666 break; 3667 case ACB_ADAPTER_TYPE_C: { 3668 if(srb_phyaddr_hi32 != 0) { 3669 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 3670 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 3671 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 3672 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3673 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 3674 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 3675 return FALSE; 3676 } 3677 } 3678 } 3679 break; 3680 case ACB_ADAPTER_TYPE_D: { 3681 u_int32_t post_queue_phyaddr, done_queue_phyaddr; 3682 struct HBD_MessageUnit0 *phbdmu; 3683 3684 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 3685 phbdmu->postq_index = 0; 3686 phbdmu->doneq_index = 0x40FF; 3687 post_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE 3688 + offsetof(struct HBD_MessageUnit0, post_qbuffer); 3689 done_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE 3690 + offsetof(struct HBD_MessageUnit0, done_qbuffer); 3691 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */ 3692 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 3693 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ base */ 3694 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[3], done_queue_phyaddr); /* doneQ base */ 3695 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[4], 0x100); 3696 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 3697 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 3698 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 3699 return FALSE; 3700 } 3701 } 3702 break; 3703 } 3704 return (TRUE); 3705 } 3706 /* 3707 ************************************************************************ 3708 ************************************************************************ 3709 */ 3710 static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb) 3711 { 3712 switch (acb->adapter_type) 3713 { 3714 case ACB_ADAPTER_TYPE_A: 3715 case ACB_ADAPTER_TYPE_C: 3716 case ACB_ADAPTER_TYPE_D: 3717 break; 3718 case ACB_ADAPTER_TYPE_B: { 3719 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell,ARCMSR_MESSAGE_ACTIVE_EOI_MODE); 3720 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3721 printf( "arcmsr%d: 'iop enable eoi mode' timeout \n", acb->pci_unit); 3722 return; 3723 } 3724 } 3725 break; 3726 } 3727 } 3728 /* 3729 ********************************************************************** 3730 ********************************************************************** 3731 */ 3732 static void arcmsr_iop_init(struct AdapterControlBlock *acb) 3733 { 3734 u_int32_t intmask_org; 3735 3736 /* disable all outbound interrupt */ 3737 intmask_org = arcmsr_disable_allintr(acb); 3738 arcmsr_wait_firmware_ready(acb); 3739 arcmsr_iop_confirm(acb); 3740 arcmsr_get_firmware_spec(acb); 3741 /*start background rebuild*/ 3742 arcmsr_start_adapter_bgrb(acb); 3743 /* empty doorbell Qbuffer if door bell ringed */ 3744 arcmsr_clear_doorbell_queue_buffer(acb); 3745 arcmsr_enable_eoi_mode(acb); 3746 /* enable outbound Post Queue, outbound doorbell Interrupt */ 3747 arcmsr_enable_allintr(acb, intmask_org); 3748 acb->acb_flags |= ACB_F_IOP_INITED; 3749 } 3750 /* 3751 ********************************************************************** 3752 ********************************************************************** 3753 */ 3754 static void arcmsr_map_free_srb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3755 { 3756 struct AdapterControlBlock *acb = arg; 3757 struct CommandControlBlock *srb_tmp; 3758 u_int32_t i; 3759 unsigned long srb_phyaddr = (unsigned long)segs->ds_addr; 3760 3761 acb->srb_phyaddr.phyaddr = srb_phyaddr; 3762 srb_tmp = (struct CommandControlBlock *)acb->uncacheptr; 3763 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 3764 if(bus_dmamap_create(acb->dm_segs_dmat, 3765 /*flags*/0, &srb_tmp->dm_segs_dmamap) != 0) { 3766 acb->acb_flags |= ACB_F_MAPFREESRB_FAILD; 3767 printf("arcmsr%d:" 3768 " srb dmamap bus_dmamap_create error\n", acb->pci_unit); 3769 return; 3770 } 3771 if((acb->adapter_type == ACB_ADAPTER_TYPE_C) || (acb->adapter_type == ACB_ADAPTER_TYPE_D)) 3772 { 3773 srb_tmp->cdb_phyaddr_low = srb_phyaddr; 3774 srb_tmp->cdb_phyaddr_high = (u_int32_t)((srb_phyaddr >> 16) >> 16); 3775 } 3776 else 3777 srb_tmp->cdb_phyaddr_low = srb_phyaddr >> 5; 3778 srb_tmp->acb = acb; 3779 acb->srbworkingQ[i] = acb->psrb_pool[i] = srb_tmp; 3780 srb_phyaddr = srb_phyaddr + SRB_SIZE; 3781 srb_tmp = (struct CommandControlBlock *)((unsigned long)srb_tmp + SRB_SIZE); 3782 } 3783 acb->vir2phy_offset = (unsigned long)srb_tmp - (unsigned long)srb_phyaddr; 3784 } 3785 /* 3786 ************************************************************************ 3787 ************************************************************************ 3788 */ 3789 static void arcmsr_free_resource(struct AdapterControlBlock *acb) 3790 { 3791 /* remove the control device */ 3792 if(acb->ioctl_dev != NULL) { 3793 destroy_dev(acb->ioctl_dev); 3794 } 3795 bus_dmamap_unload(acb->srb_dmat, acb->srb_dmamap); 3796 bus_dmamap_destroy(acb->srb_dmat, acb->srb_dmamap); 3797 bus_dma_tag_destroy(acb->srb_dmat); 3798 bus_dma_tag_destroy(acb->dm_segs_dmat); 3799 bus_dma_tag_destroy(acb->parent_dmat); 3800 } 3801 /* 3802 ************************************************************************ 3803 ************************************************************************ 3804 */ 3805 static void arcmsr_mutex_init(struct AdapterControlBlock *acb) 3806 { 3807 ARCMSR_LOCK_INIT(&acb->isr_lock, "arcmsr isr lock"); 3808 ARCMSR_LOCK_INIT(&acb->srb_lock, "arcmsr srb lock"); 3809 ARCMSR_LOCK_INIT(&acb->postDone_lock, "arcmsr postQ lock"); 3810 ARCMSR_LOCK_INIT(&acb->qbuffer_lock, "arcmsr RW buffer lock"); 3811 } 3812 /* 3813 ************************************************************************ 3814 ************************************************************************ 3815 */ 3816 static void arcmsr_mutex_destroy(struct AdapterControlBlock *acb) 3817 { 3818 ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock); 3819 ARCMSR_LOCK_DESTROY(&acb->postDone_lock); 3820 ARCMSR_LOCK_DESTROY(&acb->srb_lock); 3821 ARCMSR_LOCK_DESTROY(&acb->isr_lock); 3822 } 3823 /* 3824 ************************************************************************ 3825 ************************************************************************ 3826 */ 3827 static u_int32_t arcmsr_initialize(device_t dev) 3828 { 3829 struct AdapterControlBlock *acb = device_get_softc(dev); 3830 u_int16_t pci_command; 3831 int i, j,max_coherent_size; 3832 u_int32_t vendor_dev_id; 3833 3834 vendor_dev_id = pci_get_devid(dev); 3835 acb->vendor_device_id = vendor_dev_id; 3836 switch (vendor_dev_id) { 3837 case PCIDevVenIDARC1880: 3838 case PCIDevVenIDARC1882: 3839 case PCIDevVenIDARC1213: 3840 case PCIDevVenIDARC1223: { 3841 acb->adapter_type = ACB_ADAPTER_TYPE_C; 3842 acb->adapter_bus_speed = ACB_BUS_SPEED_6G; 3843 max_coherent_size = ARCMSR_SRBS_POOL_SIZE; 3844 } 3845 break; 3846 case PCIDevVenIDARC1214: { 3847 acb->adapter_type = ACB_ADAPTER_TYPE_D; 3848 acb->adapter_bus_speed = ACB_BUS_SPEED_6G; 3849 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBD_MessageUnit0)); 3850 } 3851 break; 3852 case PCIDevVenIDARC1200: 3853 case PCIDevVenIDARC1201: { 3854 acb->adapter_type = ACB_ADAPTER_TYPE_B; 3855 acb->adapter_bus_speed = ACB_BUS_SPEED_3G; 3856 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit)); 3857 } 3858 break; 3859 case PCIDevVenIDARC1110: 3860 case PCIDevVenIDARC1120: 3861 case PCIDevVenIDARC1130: 3862 case PCIDevVenIDARC1160: 3863 case PCIDevVenIDARC1170: 3864 case PCIDevVenIDARC1210: 3865 case PCIDevVenIDARC1220: 3866 case PCIDevVenIDARC1230: 3867 case PCIDevVenIDARC1231: 3868 case PCIDevVenIDARC1260: 3869 case PCIDevVenIDARC1261: 3870 case PCIDevVenIDARC1270: 3871 case PCIDevVenIDARC1280: 3872 case PCIDevVenIDARC1212: 3873 case PCIDevVenIDARC1222: 3874 case PCIDevVenIDARC1380: 3875 case PCIDevVenIDARC1381: 3876 case PCIDevVenIDARC1680: 3877 case PCIDevVenIDARC1681: { 3878 acb->adapter_type = ACB_ADAPTER_TYPE_A; 3879 acb->adapter_bus_speed = ACB_BUS_SPEED_3G; 3880 max_coherent_size = ARCMSR_SRBS_POOL_SIZE; 3881 } 3882 break; 3883 default: { 3884 printf("arcmsr%d:" 3885 " unknown RAID adapter type \n", device_get_unit(dev)); 3886 return ENOMEM; 3887 } 3888 } 3889 #if __FreeBSD_version >= 700000 3890 if(bus_dma_tag_create( /*PCI parent*/ bus_get_dma_tag(dev), 3891 #else 3892 if(bus_dma_tag_create( /*PCI parent*/ NULL, 3893 #endif 3894 /*alignemnt*/ 1, 3895 /*boundary*/ 0, 3896 /*lowaddr*/ BUS_SPACE_MAXADDR, 3897 /*highaddr*/ BUS_SPACE_MAXADDR, 3898 /*filter*/ NULL, 3899 /*filterarg*/ NULL, 3900 /*maxsize*/ BUS_SPACE_MAXSIZE_32BIT, 3901 /*nsegments*/ BUS_SPACE_UNRESTRICTED, 3902 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 3903 /*flags*/ 0, 3904 #if __FreeBSD_version >= 501102 3905 /*lockfunc*/ NULL, 3906 /*lockarg*/ NULL, 3907 #endif 3908 &acb->parent_dmat) != 0) 3909 { 3910 printf("arcmsr%d: parent_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 3911 return ENOMEM; 3912 } 3913 3914 /* Create a single tag describing a region large enough to hold all of the s/g lists we will need. */ 3915 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat, 3916 /*alignment*/ 1, 3917 /*boundary*/ 0, 3918 #ifdef PAE 3919 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 3920 #else 3921 /*lowaddr*/ BUS_SPACE_MAXADDR, 3922 #endif 3923 /*highaddr*/ BUS_SPACE_MAXADDR, 3924 /*filter*/ NULL, 3925 /*filterarg*/ NULL, 3926 /*maxsize*/ ARCMSR_MAX_SG_ENTRIES * PAGE_SIZE * ARCMSR_MAX_FREESRB_NUM, 3927 /*nsegments*/ ARCMSR_MAX_SG_ENTRIES, 3928 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 3929 /*flags*/ 0, 3930 #if __FreeBSD_version >= 501102 3931 /*lockfunc*/ busdma_lock_mutex, 3932 /*lockarg*/ &acb->isr_lock, 3933 #endif 3934 &acb->dm_segs_dmat) != 0) 3935 { 3936 bus_dma_tag_destroy(acb->parent_dmat); 3937 printf("arcmsr%d: dm_segs_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 3938 return ENOMEM; 3939 } 3940 3941 /* DMA tag for our srb structures.... Allocate the freesrb memory */ 3942 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat, 3943 /*alignment*/ 0x20, 3944 /*boundary*/ 0, 3945 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 3946 /*highaddr*/ BUS_SPACE_MAXADDR, 3947 /*filter*/ NULL, 3948 /*filterarg*/ NULL, 3949 /*maxsize*/ max_coherent_size, 3950 /*nsegments*/ 1, 3951 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 3952 /*flags*/ 0, 3953 #if __FreeBSD_version >= 501102 3954 /*lockfunc*/ NULL, 3955 /*lockarg*/ NULL, 3956 #endif 3957 &acb->srb_dmat) != 0) 3958 { 3959 bus_dma_tag_destroy(acb->dm_segs_dmat); 3960 bus_dma_tag_destroy(acb->parent_dmat); 3961 printf("arcmsr%d: srb_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 3962 return ENXIO; 3963 } 3964 /* Allocation for our srbs */ 3965 if(bus_dmamem_alloc(acb->srb_dmat, (void **)&acb->uncacheptr, BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, &acb->srb_dmamap) != 0) { 3966 bus_dma_tag_destroy(acb->srb_dmat); 3967 bus_dma_tag_destroy(acb->dm_segs_dmat); 3968 bus_dma_tag_destroy(acb->parent_dmat); 3969 printf("arcmsr%d: srb_dmat bus_dmamem_alloc failure!\n", device_get_unit(dev)); 3970 return ENXIO; 3971 } 3972 /* And permanently map them */ 3973 if(bus_dmamap_load(acb->srb_dmat, acb->srb_dmamap, acb->uncacheptr, max_coherent_size, arcmsr_map_free_srb, acb, /*flags*/0)) { 3974 bus_dma_tag_destroy(acb->srb_dmat); 3975 bus_dma_tag_destroy(acb->dm_segs_dmat); 3976 bus_dma_tag_destroy(acb->parent_dmat); 3977 printf("arcmsr%d: srb_dmat bus_dmamap_load failure!\n", device_get_unit(dev)); 3978 return ENXIO; 3979 } 3980 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 3981 pci_command |= PCIM_CMD_BUSMASTEREN; 3982 pci_command |= PCIM_CMD_PERRESPEN; 3983 pci_command |= PCIM_CMD_MWRICEN; 3984 /* Enable Busmaster/Mem */ 3985 pci_command |= PCIM_CMD_MEMEN; 3986 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 3987 switch(acb->adapter_type) { 3988 case ACB_ADAPTER_TYPE_A: { 3989 u_int32_t rid0 = PCIR_BAR(0); 3990 vm_offset_t mem_base0; 3991 3992 acb->sys_res_arcmsr[0] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, 0x1000, RF_ACTIVE); 3993 if(acb->sys_res_arcmsr[0] == NULL) { 3994 arcmsr_free_resource(acb); 3995 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 3996 return ENOMEM; 3997 } 3998 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 3999 arcmsr_free_resource(acb); 4000 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4001 return ENXIO; 4002 } 4003 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4004 if(mem_base0 == 0) { 4005 arcmsr_free_resource(acb); 4006 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4007 return ENXIO; 4008 } 4009 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4010 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4011 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4012 } 4013 break; 4014 case ACB_ADAPTER_TYPE_B: { 4015 struct HBB_MessageUnit *phbbmu; 4016 struct CommandControlBlock *freesrb; 4017 u_int32_t rid[]={ PCIR_BAR(0), PCIR_BAR(2) }; 4018 vm_offset_t mem_base[]={0,0}; 4019 for(i=0; i < 2; i++) { 4020 if(i == 0) { 4021 acb->sys_res_arcmsr[i] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid[i], 4022 0ul, ~0ul, sizeof(struct HBB_DOORBELL), RF_ACTIVE); 4023 } else { 4024 acb->sys_res_arcmsr[i] = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid[i], 4025 0ul, ~0ul, sizeof(struct HBB_RWBUFFER), RF_ACTIVE); 4026 } 4027 if(acb->sys_res_arcmsr[i] == NULL) { 4028 arcmsr_free_resource(acb); 4029 printf("arcmsr%d: bus_alloc_resource %d failure!\n", device_get_unit(dev), i); 4030 return ENOMEM; 4031 } 4032 if(rman_get_start(acb->sys_res_arcmsr[i]) <= 0) { 4033 arcmsr_free_resource(acb); 4034 printf("arcmsr%d: rman_get_start %d failure!\n", device_get_unit(dev), i); 4035 return ENXIO; 4036 } 4037 mem_base[i] = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[i]); 4038 if(mem_base[i] == 0) { 4039 arcmsr_free_resource(acb); 4040 printf("arcmsr%d: rman_get_virtual %d failure!\n", device_get_unit(dev), i); 4041 return ENXIO; 4042 } 4043 acb->btag[i] = rman_get_bustag(acb->sys_res_arcmsr[i]); 4044 acb->bhandle[i] = rman_get_bushandle(acb->sys_res_arcmsr[i]); 4045 } 4046 freesrb = (struct CommandControlBlock *)acb->uncacheptr; 4047 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)freesrb+ARCMSR_SRBS_POOL_SIZE); 4048 phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4049 phbbmu->hbb_doorbell = (struct HBB_DOORBELL *)mem_base[0]; 4050 phbbmu->hbb_rwbuffer = (struct HBB_RWBUFFER *)mem_base[1]; 4051 } 4052 break; 4053 case ACB_ADAPTER_TYPE_C: { 4054 u_int32_t rid0 = PCIR_BAR(1); 4055 vm_offset_t mem_base0; 4056 4057 acb->sys_res_arcmsr[0] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, sizeof(struct HBC_MessageUnit), RF_ACTIVE); 4058 if(acb->sys_res_arcmsr[0] == NULL) { 4059 arcmsr_free_resource(acb); 4060 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4061 return ENOMEM; 4062 } 4063 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4064 arcmsr_free_resource(acb); 4065 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4066 return ENXIO; 4067 } 4068 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4069 if(mem_base0 == 0) { 4070 arcmsr_free_resource(acb); 4071 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4072 return ENXIO; 4073 } 4074 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4075 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4076 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4077 } 4078 break; 4079 case ACB_ADAPTER_TYPE_D: { 4080 struct HBD_MessageUnit0 *phbdmu; 4081 u_int32_t rid0 = PCIR_BAR(0); 4082 vm_offset_t mem_base0; 4083 4084 acb->sys_res_arcmsr[0] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, sizeof(struct HBD_MessageUnit), RF_ACTIVE); 4085 if(acb->sys_res_arcmsr[0] == NULL) { 4086 arcmsr_free_resource(acb); 4087 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4088 return ENOMEM; 4089 } 4090 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4091 arcmsr_free_resource(acb); 4092 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4093 return ENXIO; 4094 } 4095 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4096 if(mem_base0 == 0) { 4097 arcmsr_free_resource(acb); 4098 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4099 return ENXIO; 4100 } 4101 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4102 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4103 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)acb->uncacheptr+ARCMSR_SRBS_POOL_SIZE); 4104 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 4105 phbdmu->phbdmu = (struct HBD_MessageUnit *)mem_base0; 4106 } 4107 break; 4108 } 4109 if(acb->acb_flags & ACB_F_MAPFREESRB_FAILD) { 4110 arcmsr_free_resource(acb); 4111 printf("arcmsr%d: map free srb failure!\n", device_get_unit(dev)); 4112 return ENXIO; 4113 } 4114 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_RQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ); 4115 acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER; 4116 /* 4117 ******************************************************************** 4118 ** init raid volume state 4119 ******************************************************************** 4120 */ 4121 for(i=0; i < ARCMSR_MAX_TARGETID; i++) { 4122 for(j=0; j < ARCMSR_MAX_TARGETLUN; j++) { 4123 acb->devstate[i][j] = ARECA_RAID_GONE; 4124 } 4125 } 4126 arcmsr_iop_init(acb); 4127 return(0); 4128 } 4129 /* 4130 ************************************************************************ 4131 ************************************************************************ 4132 */ 4133 static int arcmsr_attach(device_t dev) 4134 { 4135 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 4136 u_int32_t unit=device_get_unit(dev); 4137 struct ccb_setasync csa; 4138 struct cam_devq *devq; /* Device Queue to use for this SIM */ 4139 struct resource *irqres; 4140 int rid; 4141 4142 if(acb == NULL) { 4143 printf("arcmsr%d: cannot allocate softc\n", unit); 4144 return (ENOMEM); 4145 } 4146 arcmsr_mutex_init(acb); 4147 if(arcmsr_initialize(dev)) { 4148 printf("arcmsr%d: initialize failure!\n", unit); 4149 arcmsr_mutex_destroy(acb); 4150 return ENXIO; 4151 } 4152 /* After setting up the adapter, map our interrupt */ 4153 rid = 0; 4154 irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1, RF_SHAREABLE | RF_ACTIVE); 4155 if(irqres == NULL || 4156 #if __FreeBSD_version >= 700025 4157 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, NULL, arcmsr_intr_handler, acb, &acb->ih)) { 4158 #else 4159 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, arcmsr_intr_handler, acb, &acb->ih)) { 4160 #endif 4161 arcmsr_free_resource(acb); 4162 arcmsr_mutex_destroy(acb); 4163 printf("arcmsr%d: unable to register interrupt handler!\n", unit); 4164 return ENXIO; 4165 } 4166 acb->irqres = irqres; 4167 acb->pci_dev = dev; 4168 acb->pci_unit = unit; 4169 /* 4170 * Now let the CAM generic SCSI layer find the SCSI devices on 4171 * the bus * start queue to reset to the idle loop. * 4172 * Create device queue of SIM(s) * (MAX_START_JOB - 1) : 4173 * max_sim_transactions 4174 */ 4175 devq = cam_simq_alloc(ARCMSR_MAX_START_JOB); 4176 if(devq == NULL) { 4177 arcmsr_free_resource(acb); 4178 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres); 4179 arcmsr_mutex_destroy(acb); 4180 printf("arcmsr%d: cam_simq_alloc failure!\n", unit); 4181 return ENXIO; 4182 } 4183 #if __FreeBSD_version >= 700025 4184 acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, &acb->isr_lock, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq); 4185 #else 4186 acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq); 4187 #endif 4188 if(acb->psim == NULL) { 4189 arcmsr_free_resource(acb); 4190 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres); 4191 cam_simq_free(devq); 4192 arcmsr_mutex_destroy(acb); 4193 printf("arcmsr%d: cam_sim_alloc failure!\n", unit); 4194 return ENXIO; 4195 } 4196 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 4197 #if __FreeBSD_version >= 700044 4198 if(xpt_bus_register(acb->psim, dev, 0) != CAM_SUCCESS) { 4199 #else 4200 if(xpt_bus_register(acb->psim, 0) != CAM_SUCCESS) { 4201 #endif 4202 arcmsr_free_resource(acb); 4203 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres); 4204 cam_sim_free(acb->psim, /*free_devq*/TRUE); 4205 arcmsr_mutex_destroy(acb); 4206 printf("arcmsr%d: xpt_bus_register failure!\n", unit); 4207 return ENXIO; 4208 } 4209 if(xpt_create_path(&acb->ppath, /* periph */ NULL, cam_sim_path(acb->psim), CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 4210 arcmsr_free_resource(acb); 4211 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres); 4212 xpt_bus_deregister(cam_sim_path(acb->psim)); 4213 cam_sim_free(acb->psim, /* free_simq */ TRUE); 4214 arcmsr_mutex_destroy(acb); 4215 printf("arcmsr%d: xpt_create_path failure!\n", unit); 4216 return ENXIO; 4217 } 4218 /* 4219 **************************************************** 4220 */ 4221 xpt_setup_ccb(&csa.ccb_h, acb->ppath, /*priority*/5); 4222 csa.ccb_h.func_code = XPT_SASYNC_CB; 4223 csa.event_enable = AC_FOUND_DEVICE|AC_LOST_DEVICE; 4224 csa.callback = arcmsr_async; 4225 csa.callback_arg = acb->psim; 4226 xpt_action((union ccb *)&csa); 4227 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 4228 /* Create the control device. */ 4229 acb->ioctl_dev = make_dev(&arcmsr_cdevsw, unit, UID_ROOT, GID_WHEEL /* GID_OPERATOR */, S_IRUSR | S_IWUSR, "arcmsr%d", unit); 4230 4231 #if __FreeBSD_version < 503000 4232 acb->ioctl_dev->si_drv1 = acb; 4233 #endif 4234 #if __FreeBSD_version > 500005 4235 (void)make_dev_alias(acb->ioctl_dev, "arc%d", unit); 4236 #endif 4237 arcmsr_callout_init(&acb->devmap_callout); 4238 callout_reset(&acb->devmap_callout, 60 * hz, arcmsr_polling_devmap, acb); 4239 return (0); 4240 } 4241 4242 /* 4243 ************************************************************************ 4244 ************************************************************************ 4245 */ 4246 static int arcmsr_probe(device_t dev) 4247 { 4248 u_int32_t id; 4249 static char buf[256]; 4250 char x_type[]={"X-TYPE"}; 4251 char *type; 4252 int raid6 = 1; 4253 4254 if (pci_get_vendor(dev) != PCI_VENDOR_ID_ARECA) { 4255 return (ENXIO); 4256 } 4257 switch(id = pci_get_devid(dev)) { 4258 case PCIDevVenIDARC1110: 4259 case PCIDevVenIDARC1200: 4260 case PCIDevVenIDARC1201: 4261 case PCIDevVenIDARC1210: 4262 raid6 = 0; 4263 /*FALLTHRU*/ 4264 case PCIDevVenIDARC1120: 4265 case PCIDevVenIDARC1130: 4266 case PCIDevVenIDARC1160: 4267 case PCIDevVenIDARC1170: 4268 case PCIDevVenIDARC1220: 4269 case PCIDevVenIDARC1230: 4270 case PCIDevVenIDARC1231: 4271 case PCIDevVenIDARC1260: 4272 case PCIDevVenIDARC1261: 4273 case PCIDevVenIDARC1270: 4274 case PCIDevVenIDARC1280: 4275 type = "SATA 3G"; 4276 break; 4277 case PCIDevVenIDARC1212: 4278 case PCIDevVenIDARC1222: 4279 case PCIDevVenIDARC1380: 4280 case PCIDevVenIDARC1381: 4281 case PCIDevVenIDARC1680: 4282 case PCIDevVenIDARC1681: 4283 type = "SAS 3G"; 4284 break; 4285 case PCIDevVenIDARC1880: 4286 case PCIDevVenIDARC1882: 4287 case PCIDevVenIDARC1213: 4288 case PCIDevVenIDARC1223: 4289 type = "SAS 6G"; 4290 break; 4291 case PCIDevVenIDARC1214: 4292 type = "SATA 6G"; 4293 break; 4294 default: 4295 type = x_type; 4296 break; 4297 } 4298 if(type == x_type) 4299 return(ENXIO); 4300 sprintf(buf, "Areca %s Host Adapter RAID Controller %s\n", type, raid6 ? "(RAID6 capable)" : ""); 4301 device_set_desc_copy(dev, buf); 4302 return (BUS_PROBE_DEFAULT); 4303 } 4304 /* 4305 ************************************************************************ 4306 ************************************************************************ 4307 */ 4308 static int arcmsr_shutdown(device_t dev) 4309 { 4310 u_int32_t i; 4311 u_int32_t intmask_org; 4312 struct CommandControlBlock *srb; 4313 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 4314 4315 /* stop adapter background rebuild */ 4316 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 4317 /* disable all outbound interrupt */ 4318 intmask_org = arcmsr_disable_allintr(acb); 4319 arcmsr_stop_adapter_bgrb(acb); 4320 arcmsr_flush_adapter_cache(acb); 4321 /* abort all outstanding command */ 4322 acb->acb_flags |= ACB_F_SCSISTOPADAPTER; 4323 acb->acb_flags &= ~ACB_F_IOP_INITED; 4324 if(acb->srboutstandingcount != 0) { 4325 /*clear and abort all outbound posted Q*/ 4326 arcmsr_done4abort_postqueue(acb); 4327 /* talk to iop 331 outstanding command aborted*/ 4328 arcmsr_abort_allcmd(acb); 4329 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 4330 srb = acb->psrb_pool[i]; 4331 if(srb->srb_state == ARCMSR_SRB_START) { 4332 srb->srb_state = ARCMSR_SRB_ABORTED; 4333 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 4334 arcmsr_srb_complete(srb, 1); 4335 } 4336 } 4337 } 4338 acb->srboutstandingcount = 0; 4339 acb->workingsrb_doneindex = 0; 4340 acb->workingsrb_startindex = 0; 4341 acb->pktRequestCount = 0; 4342 acb->pktReturnCount = 0; 4343 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 4344 return (0); 4345 } 4346 /* 4347 ************************************************************************ 4348 ************************************************************************ 4349 */ 4350 static int arcmsr_detach(device_t dev) 4351 { 4352 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 4353 int i; 4354 4355 callout_stop(&acb->devmap_callout); 4356 bus_teardown_intr(dev, acb->irqres, acb->ih); 4357 arcmsr_shutdown(dev); 4358 arcmsr_free_resource(acb); 4359 for(i=0; (acb->sys_res_arcmsr[i]!=NULL) && (i<2); i++) { 4360 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(i), acb->sys_res_arcmsr[i]); 4361 } 4362 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres); 4363 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 4364 xpt_async(AC_LOST_DEVICE, acb->ppath, NULL); 4365 xpt_free_path(acb->ppath); 4366 xpt_bus_deregister(cam_sim_path(acb->psim)); 4367 cam_sim_free(acb->psim, TRUE); 4368 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 4369 arcmsr_mutex_destroy(acb); 4370 return (0); 4371 } 4372 4373 #ifdef ARCMSR_DEBUG1 4374 static void arcmsr_dump_data(struct AdapterControlBlock *acb) 4375 { 4376 if((acb->pktRequestCount - acb->pktReturnCount) == 0) 4377 return; 4378 printf("Command Request Count =0x%x\n",acb->pktRequestCount); 4379 printf("Command Return Count =0x%x\n",acb->pktReturnCount); 4380 printf("Command (Req-Rtn) Count =0x%x\n",(acb->pktRequestCount - acb->pktReturnCount)); 4381 printf("Queued Command Count =0x%x\n",acb->srboutstandingcount); 4382 } 4383 #endif 4384 4385