1 /* 2 ******************************************************************************** 3 ** OS : FreeBSD 4 ** FILE NAME : arcmsr.c 5 ** BY : Erich Chen, Ching Huang 6 ** Description: SCSI RAID Device Driver for 7 ** ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x) 8 ** SATA/SAS RAID HOST Adapter 9 ******************************************************************************** 10 ******************************************************************************** 11 ** 12 ** SPDX-License-Identifier: BSD-3-Clause 13 ** 14 ** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved. 15 ** 16 ** Redistribution and use in source and binary forms, with or without 17 ** modification, are permitted provided that the following conditions 18 ** are met: 19 ** 1. Redistributions of source code must retain the above copyright 20 ** notice, this list of conditions and the following disclaimer. 21 ** 2. Redistributions in binary form must reproduce the above copyright 22 ** notice, this list of conditions and the following disclaimer in the 23 ** documentation and/or other materials provided with the distribution. 24 ** 3. The name of the author may not be used to endorse or promote products 25 ** derived from this software without specific prior written permission. 26 ** 27 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 28 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 29 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 31 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT 32 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 34 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 36 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 ******************************************************************************** 38 ** History 39 ** 40 ** REV# DATE NAME DESCRIPTION 41 ** 1.00.00.00 03/31/2004 Erich Chen First release 42 ** 1.20.00.02 11/29/2004 Erich Chen bug fix with arcmsr_bus_reset when PHY error 43 ** 1.20.00.03 04/19/2005 Erich Chen add SATA 24 Ports adapter type support 44 ** clean unused function 45 ** 1.20.00.12 09/12/2005 Erich Chen bug fix with abort command handling, 46 ** firmware version check 47 ** and firmware update notify for hardware bug fix 48 ** handling if none zero high part physical address 49 ** of srb resource 50 ** 1.20.00.13 08/18/2006 Erich Chen remove pending srb and report busy 51 ** add iop message xfer 52 ** with scsi pass-through command 53 ** add new device id of sas raid adapters 54 ** code fit for SPARC64 & PPC 55 ** 1.20.00.14 02/05/2007 Erich Chen bug fix for incorrect ccb_h.status report 56 ** and cause g_vfs_done() read write error 57 ** 1.20.00.15 10/10/2007 Erich Chen support new RAID adapter type ARC120x 58 ** 1.20.00.16 10/10/2009 Erich Chen Bug fix for RAID adapter type ARC120x 59 ** bus_dmamem_alloc() with BUS_DMA_ZERO 60 ** 1.20.00.17 07/15/2010 Ching Huang Added support ARC1880 61 ** report CAM_DEV_NOT_THERE instead of CAM_SEL_TIMEOUT when device failed, 62 ** prevent cam_periph_error removing all LUN devices of one Target id 63 ** for any one LUN device failed 64 ** 1.20.00.18 10/14/2010 Ching Huang Fixed "inquiry data fails comparion at DV1 step" 65 ** 10/25/2010 Ching Huang Fixed bad range input in bus_alloc_resource for ADAPTER_TYPE_B 66 ** 1.20.00.19 11/11/2010 Ching Huang Fixed arcmsr driver prevent arcsas support for Areca SAS HBA ARC13x0 67 ** 1.20.00.20 12/08/2010 Ching Huang Avoid calling atomic_set_int function 68 ** 1.20.00.21 02/08/2011 Ching Huang Implement I/O request timeout 69 ** 02/14/2011 Ching Huang Modified pktRequestCount 70 ** 1.20.00.21 03/03/2011 Ching Huang if a command timeout, then wait its ccb back before free it 71 ** 1.20.00.22 07/04/2011 Ching Huang Fixed multiple MTX panic 72 ** 1.20.00.23 10/28/2011 Ching Huang Added TIMEOUT_DELAY in case of too many HDDs need to start 73 ** 1.20.00.23 11/08/2011 Ching Huang Added report device transfer speed 74 ** 1.20.00.23 01/30/2012 Ching Huang Fixed Request requeued and Retrying command 75 ** 1.20.00.24 06/11/2012 Ching Huang Fixed return sense data condition 76 ** 1.20.00.25 08/17/2012 Ching Huang Fixed hotplug device no function on type A adapter 77 ** 1.20.00.26 12/14/2012 Ching Huang Added support ARC1214,1224,1264,1284 78 ** 1.20.00.27 05/06/2013 Ching Huang Fixed out standing cmd full on ARC-12x4 79 ** 1.20.00.28 09/13/2013 Ching Huang Removed recursive mutex in arcmsr_abort_dr_ccbs 80 ** 1.20.00.29 12/18/2013 Ching Huang Change simq allocation number, support ARC1883 81 ** 1.30.00.00 11/30/2015 Ching Huang Added support ARC1203 82 ** 1.40.00.00 07/11/2017 Ching Huang Added support ARC1884 83 ** 1.40.00.01 10/30/2017 Ching Huang Fixed release memory resource 84 ** 1.50.00.00 09/30/2020 Ching Huang Added support ARC-1886, NVMe/SAS/SATA controller 85 ** 1.50.00.01 02/26/2021 Ching Huang Fixed no action of hot plugging device on type_F adapter 86 ** 1.50.00.02 04/16/2021 Ching Huang Fixed scsi command timeout on ARC-1886 when 87 ** scatter-gather count large than some number 88 ** 1.50.00.03 05/04/2021 Ching Huang Fixed doorbell status arrived late on ARC-1886 89 ** 1.50.00.04 12/08/2021 Ching Huang Fixed boot up hung under ARC-1886 with no volume created 90 ****************************************************************************************** 91 */ 92 93 #include <sys/cdefs.h> 94 __FBSDID("$FreeBSD$"); 95 96 #if 0 97 #define ARCMSR_DEBUG1 1 98 #endif 99 #include <sys/param.h> 100 #include <sys/systm.h> 101 #include <sys/malloc.h> 102 #include <sys/kernel.h> 103 #include <sys/bus.h> 104 #include <sys/queue.h> 105 #include <sys/stat.h> 106 #include <sys/devicestat.h> 107 #include <sys/kthread.h> 108 #include <sys/module.h> 109 #include <sys/proc.h> 110 #include <sys/lock.h> 111 #include <sys/sysctl.h> 112 #include <sys/poll.h> 113 #include <sys/ioccom.h> 114 #include <vm/vm.h> 115 #include <vm/vm_param.h> 116 #include <vm/pmap.h> 117 118 #include <isa/rtc.h> 119 120 #include <machine/bus.h> 121 #include <machine/resource.h> 122 #include <machine/atomic.h> 123 #include <sys/conf.h> 124 #include <sys/rman.h> 125 126 #include <cam/cam.h> 127 #include <cam/cam_ccb.h> 128 #include <cam/cam_sim.h> 129 #include <cam/cam_periph.h> 130 #include <cam/cam_xpt_periph.h> 131 #include <cam/cam_xpt_sim.h> 132 #include <cam/cam_debug.h> 133 #include <cam/scsi/scsi_all.h> 134 #include <cam/scsi/scsi_message.h> 135 /* 136 ************************************************************************** 137 ************************************************************************** 138 */ 139 #include <sys/selinfo.h> 140 #include <sys/mutex.h> 141 #include <sys/endian.h> 142 #include <dev/pci/pcivar.h> 143 #include <dev/pci/pcireg.h> 144 145 #define arcmsr_callout_init(a) callout_init(a, /*mpsafe*/1); 146 147 #define ARCMSR_DRIVER_VERSION "arcmsr version 1.50.00.04 2021-12-08" 148 #include <dev/arcmsr/arcmsr.h> 149 /* 150 ************************************************************************** 151 ************************************************************************** 152 */ 153 static void arcmsr_free_srb(struct CommandControlBlock *srb); 154 static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb); 155 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb); 156 static int arcmsr_probe(device_t dev); 157 static int arcmsr_attach(device_t dev); 158 static int arcmsr_detach(device_t dev); 159 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg); 160 static void arcmsr_iop_parking(struct AdapterControlBlock *acb); 161 static int arcmsr_shutdown(device_t dev); 162 static void arcmsr_interrupt(struct AdapterControlBlock *acb); 163 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb); 164 static void arcmsr_free_resource(struct AdapterControlBlock *acb); 165 static void arcmsr_bus_reset(struct AdapterControlBlock *acb); 166 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb); 167 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb); 168 static void arcmsr_iop_init(struct AdapterControlBlock *acb); 169 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb); 170 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, struct QBUFFER *prbuffer); 171 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb); 172 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb); 173 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag); 174 static void arcmsr_iop_reset(struct AdapterControlBlock *acb); 175 static void arcmsr_report_sense_info(struct CommandControlBlock *srb); 176 static void arcmsr_build_srb(struct CommandControlBlock *srb, bus_dma_segment_t *dm_segs, u_int32_t nseg); 177 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb); 178 static int arcmsr_resume(device_t dev); 179 static int arcmsr_suspend(device_t dev); 180 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb); 181 static void arcmsr_polling_devmap(void *arg); 182 static void arcmsr_srb_timeout(void *arg); 183 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb); 184 static void arcmsr_hbe_postqueue_isr(struct AdapterControlBlock *acb); 185 static void arcmsr_hbf_postqueue_isr(struct AdapterControlBlock *acb); 186 static void arcmsr_teardown_intr(device_t dev, struct AdapterControlBlock *acb); 187 #ifdef ARCMSR_DEBUG1 188 static void arcmsr_dump_data(struct AdapterControlBlock *acb); 189 #endif 190 /* 191 ************************************************************************** 192 ************************************************************************** 193 */ 194 static void UDELAY(u_int32_t us) { DELAY(us); } 195 /* 196 ************************************************************************** 197 ************************************************************************** 198 */ 199 static bus_dmamap_callback_t arcmsr_map_free_srb; 200 static bus_dmamap_callback_t arcmsr_execute_srb; 201 /* 202 ************************************************************************** 203 ************************************************************************** 204 */ 205 static d_open_t arcmsr_open; 206 static d_close_t arcmsr_close; 207 static d_ioctl_t arcmsr_ioctl; 208 209 static device_method_t arcmsr_methods[]={ 210 DEVMETHOD(device_probe, arcmsr_probe), 211 DEVMETHOD(device_attach, arcmsr_attach), 212 DEVMETHOD(device_detach, arcmsr_detach), 213 DEVMETHOD(device_shutdown, arcmsr_shutdown), 214 DEVMETHOD(device_suspend, arcmsr_suspend), 215 DEVMETHOD(device_resume, arcmsr_resume), 216 DEVMETHOD_END 217 }; 218 219 static driver_t arcmsr_driver={ 220 "arcmsr", arcmsr_methods, sizeof(struct AdapterControlBlock) 221 }; 222 223 static devclass_t arcmsr_devclass; 224 DRIVER_MODULE(arcmsr, pci, arcmsr_driver, arcmsr_devclass, 0, 0); 225 MODULE_DEPEND(arcmsr, pci, 1, 1, 1); 226 MODULE_DEPEND(arcmsr, cam, 1, 1, 1); 227 #ifndef BUS_DMA_COHERENT 228 #define BUS_DMA_COHERENT 0x04 /* hint: map memory in a coherent way */ 229 #endif 230 static struct cdevsw arcmsr_cdevsw={ 231 .d_version = D_VERSION, 232 .d_open = arcmsr_open, /* open */ 233 .d_close = arcmsr_close, /* close */ 234 .d_ioctl = arcmsr_ioctl, /* ioctl */ 235 .d_name = "arcmsr", /* name */ 236 }; 237 /* 238 ************************************************************************** 239 ************************************************************************** 240 */ 241 static int arcmsr_open(struct cdev *dev, int flags, int fmt, struct thread *proc) 242 { 243 int unit = dev2unit(dev); 244 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit); 245 246 if (acb == NULL) { 247 return ENXIO; 248 } 249 return (0); 250 } 251 /* 252 ************************************************************************** 253 ************************************************************************** 254 */ 255 static int arcmsr_close(struct cdev *dev, int flags, int fmt, struct thread *proc) 256 { 257 int unit = dev2unit(dev); 258 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit); 259 260 if (acb == NULL) { 261 return ENXIO; 262 } 263 return 0; 264 } 265 /* 266 ************************************************************************** 267 ************************************************************************** 268 */ 269 static int arcmsr_ioctl(struct cdev *dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc) 270 { 271 int unit = dev2unit(dev); 272 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit); 273 274 if (acb == NULL) { 275 return ENXIO; 276 } 277 return (arcmsr_iop_ioctlcmd(acb, ioctl_cmd, arg)); 278 } 279 /* 280 ********************************************************************** 281 ********************************************************************** 282 */ 283 static u_int32_t arcmsr_disable_allintr( struct AdapterControlBlock *acb) 284 { 285 u_int32_t intmask_org = 0; 286 287 switch (acb->adapter_type) { 288 case ACB_ADAPTER_TYPE_A: { 289 /* disable all outbound interrupt */ 290 intmask_org = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intmask); /* disable outbound message0 int */ 291 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE); 292 } 293 break; 294 case ACB_ADAPTER_TYPE_B: { 295 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 296 /* disable all outbound interrupt */ 297 intmask_org = READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask) 298 & (~ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); /* disable outbound message0 int */ 299 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask, 0); /* disable all interrupt */ 300 } 301 break; 302 case ACB_ADAPTER_TYPE_C: { 303 /* disable all outbound interrupt */ 304 intmask_org = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask); /* disable outbound message0 int */ 305 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE); 306 } 307 break; 308 case ACB_ADAPTER_TYPE_D: { 309 /* disable all outbound interrupt */ 310 intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); /* disable outbound message0 int */ 311 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE); 312 } 313 break; 314 case ACB_ADAPTER_TYPE_E: 315 case ACB_ADAPTER_TYPE_F: { 316 /* disable all outbound interrupt */ 317 intmask_org = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_mask); /* disable outbound message0 int */ 318 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_mask, intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE); 319 } 320 break; 321 } 322 return (intmask_org); 323 } 324 /* 325 ********************************************************************** 326 ********************************************************************** 327 */ 328 static void arcmsr_enable_allintr( struct AdapterControlBlock *acb, u_int32_t intmask_org) 329 { 330 u_int32_t mask; 331 332 switch (acb->adapter_type) { 333 case ACB_ADAPTER_TYPE_A: { 334 /* enable outbound Post Queue, outbound doorbell Interrupt */ 335 mask = ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE|ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE); 336 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org & mask); 337 acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff; 338 } 339 break; 340 case ACB_ADAPTER_TYPE_B: { 341 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 342 /* enable ARCMSR_IOP2DRV_MESSAGE_CMD_DONE */ 343 mask = (ARCMSR_IOP2DRV_DATA_WRITE_OK|ARCMSR_IOP2DRV_DATA_READ_OK|ARCMSR_IOP2DRV_CDB_DONE|ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); 344 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask, intmask_org | mask); /*1=interrupt enable, 0=interrupt disable*/ 345 acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f; 346 } 347 break; 348 case ACB_ADAPTER_TYPE_C: { 349 /* enable outbound Post Queue, outbound doorbell Interrupt */ 350 mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK); 351 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org & mask); 352 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f; 353 } 354 break; 355 case ACB_ADAPTER_TYPE_D: { 356 /* enable outbound Post Queue, outbound doorbell Interrupt */ 357 mask = ARCMSR_HBDMU_ALL_INT_ENABLE; 358 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | mask); 359 CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); 360 acb->outbound_int_enable = mask; 361 } 362 break; 363 case ACB_ADAPTER_TYPE_E: 364 case ACB_ADAPTER_TYPE_F: { 365 /* enable outbound Post Queue, outbound doorbell Interrupt */ 366 mask = ~(ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR); 367 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_mask, intmask_org & mask); 368 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f; 369 } 370 break; 371 } 372 } 373 /* 374 ********************************************************************** 375 ********************************************************************** 376 */ 377 static u_int8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb) 378 { 379 u_int32_t Index; 380 u_int8_t Retries = 0x00; 381 382 do { 383 for(Index=0; Index < 100; Index++) { 384 if(CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { 385 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);/*clear interrupt*/ 386 return TRUE; 387 } 388 UDELAY(10000); 389 }/*max 1 seconds*/ 390 }while(Retries++ < 20);/*max 20 sec*/ 391 return (FALSE); 392 } 393 /* 394 ********************************************************************** 395 ********************************************************************** 396 */ 397 static u_int8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb) 398 { 399 u_int32_t Index; 400 u_int8_t Retries = 0x00; 401 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 402 403 do { 404 for(Index=0; Index < 100; Index++) { 405 if(READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) { 406 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt*/ 407 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 408 return TRUE; 409 } 410 UDELAY(10000); 411 }/*max 1 seconds*/ 412 }while(Retries++ < 20);/*max 20 sec*/ 413 return (FALSE); 414 } 415 /* 416 ********************************************************************** 417 ********************************************************************** 418 */ 419 static u_int8_t arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock *acb) 420 { 421 u_int32_t Index; 422 u_int8_t Retries = 0x00; 423 424 do { 425 for(Index=0; Index < 100; Index++) { 426 if(CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 427 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);/*clear interrupt*/ 428 return TRUE; 429 } 430 UDELAY(10000); 431 }/*max 1 seconds*/ 432 }while(Retries++ < 20);/*max 20 sec*/ 433 return (FALSE); 434 } 435 /* 436 ********************************************************************** 437 ********************************************************************** 438 */ 439 static u_int8_t arcmsr_hbd_wait_msgint_ready(struct AdapterControlBlock *acb) 440 { 441 u_int32_t Index; 442 u_int8_t Retries = 0x00; 443 444 do { 445 for(Index=0; Index < 100; Index++) { 446 if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) { 447 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);/*clear interrupt*/ 448 return TRUE; 449 } 450 UDELAY(10000); 451 }/*max 1 seconds*/ 452 }while(Retries++ < 20);/*max 20 sec*/ 453 return (FALSE); 454 } 455 /* 456 ********************************************************************** 457 ********************************************************************** 458 */ 459 static u_int8_t arcmsr_hbe_wait_msgint_ready(struct AdapterControlBlock *acb) 460 { 461 u_int32_t Index, read_doorbell; 462 u_int8_t Retries = 0x00; 463 464 do { 465 for(Index=0; Index < 100; Index++) { 466 read_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell); 467 if((read_doorbell ^ acb->in_doorbell) & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) { 468 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0);/*clear interrupt*/ 469 acb->in_doorbell = read_doorbell; 470 return TRUE; 471 } 472 UDELAY(10000); 473 }/*max 1 seconds*/ 474 }while(Retries++ < 20);/*max 20 sec*/ 475 return (FALSE); 476 } 477 /* 478 ************************************************************************ 479 ************************************************************************ 480 */ 481 static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb) 482 { 483 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 484 485 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 486 do { 487 if(arcmsr_hba_wait_msgint_ready(acb)) { 488 break; 489 } else { 490 retry_count--; 491 } 492 }while(retry_count != 0); 493 } 494 /* 495 ************************************************************************ 496 ************************************************************************ 497 */ 498 static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb) 499 { 500 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 501 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 502 503 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_FLUSH_CACHE); 504 do { 505 if(arcmsr_hbb_wait_msgint_ready(acb)) { 506 break; 507 } else { 508 retry_count--; 509 } 510 }while(retry_count != 0); 511 } 512 /* 513 ************************************************************************ 514 ************************************************************************ 515 */ 516 static void arcmsr_flush_hbc_cache(struct AdapterControlBlock *acb) 517 { 518 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 519 520 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 521 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 522 do { 523 if(arcmsr_hbc_wait_msgint_ready(acb)) { 524 break; 525 } else { 526 retry_count--; 527 } 528 }while(retry_count != 0); 529 } 530 /* 531 ************************************************************************ 532 ************************************************************************ 533 */ 534 static void arcmsr_flush_hbd_cache(struct AdapterControlBlock *acb) 535 { 536 int retry_count = 30; /* enlarge wait flush adapter cache time: 10 minute */ 537 538 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 539 do { 540 if(arcmsr_hbd_wait_msgint_ready(acb)) { 541 break; 542 } else { 543 retry_count--; 544 } 545 }while(retry_count != 0); 546 } 547 /* 548 ************************************************************************ 549 ************************************************************************ 550 */ 551 static void arcmsr_flush_hbe_cache(struct AdapterControlBlock *acb) 552 { 553 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 554 555 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 556 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 557 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 558 do { 559 if(arcmsr_hbe_wait_msgint_ready(acb)) { 560 break; 561 } else { 562 retry_count--; 563 } 564 }while(retry_count != 0); 565 } 566 /* 567 ************************************************************************ 568 ************************************************************************ 569 */ 570 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb) 571 { 572 switch (acb->adapter_type) { 573 case ACB_ADAPTER_TYPE_A: { 574 arcmsr_flush_hba_cache(acb); 575 } 576 break; 577 case ACB_ADAPTER_TYPE_B: { 578 arcmsr_flush_hbb_cache(acb); 579 } 580 break; 581 case ACB_ADAPTER_TYPE_C: { 582 arcmsr_flush_hbc_cache(acb); 583 } 584 break; 585 case ACB_ADAPTER_TYPE_D: { 586 arcmsr_flush_hbd_cache(acb); 587 } 588 break; 589 case ACB_ADAPTER_TYPE_E: 590 case ACB_ADAPTER_TYPE_F: { 591 arcmsr_flush_hbe_cache(acb); 592 } 593 break; 594 } 595 } 596 /* 597 ******************************************************************************* 598 ******************************************************************************* 599 */ 600 static int arcmsr_suspend(device_t dev) 601 { 602 struct AdapterControlBlock *acb = device_get_softc(dev); 603 604 /* flush controller */ 605 arcmsr_iop_parking(acb); 606 /* disable all outbound interrupt */ 607 arcmsr_disable_allintr(acb); 608 return(0); 609 } 610 /* 611 ******************************************************************************* 612 ******************************************************************************* 613 */ 614 static int arcmsr_resume(device_t dev) 615 { 616 struct AdapterControlBlock *acb = device_get_softc(dev); 617 618 arcmsr_iop_init(acb); 619 return(0); 620 } 621 /* 622 ********************************************************************************* 623 ********************************************************************************* 624 */ 625 static void arcmsr_async(void *cb_arg, u_int32_t code, struct cam_path *path, void *arg) 626 { 627 u_int8_t target_id, target_lun; 628 629 switch (code) { 630 case AC_LOST_DEVICE: 631 target_id = xpt_path_target_id(path); 632 target_lun = xpt_path_lun_id(path); 633 if((target_id > ARCMSR_MAX_TARGETID) || (target_lun > ARCMSR_MAX_TARGETLUN)) { 634 break; 635 } 636 break; 637 default: 638 break; 639 } 640 } 641 /* 642 ********************************************************************** 643 ********************************************************************** 644 */ 645 static void arcmsr_report_sense_info(struct CommandControlBlock *srb) 646 { 647 union ccb *pccb = srb->pccb; 648 649 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 650 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 651 if(pccb->csio.sense_len) { 652 memset(&pccb->csio.sense_data, 0, sizeof(pccb->csio.sense_data)); 653 memcpy(&pccb->csio.sense_data, srb->arcmsr_cdb.SenseData, 654 get_min(sizeof(struct SENSE_DATA), sizeof(pccb->csio.sense_data))); 655 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); /* Valid,ErrorCode */ 656 pccb->ccb_h.status |= CAM_AUTOSNS_VALID; 657 } 658 } 659 /* 660 ********************************************************************* 661 ********************************************************************* 662 */ 663 static void arcmsr_abort_hba_allcmd(struct AdapterControlBlock *acb) 664 { 665 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 666 if(!arcmsr_hba_wait_msgint_ready(acb)) { 667 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 668 } 669 } 670 /* 671 ********************************************************************* 672 ********************************************************************* 673 */ 674 static void arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb) 675 { 676 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 677 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_ABORT_CMD); 678 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 679 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 680 } 681 } 682 /* 683 ********************************************************************* 684 ********************************************************************* 685 */ 686 static void arcmsr_abort_hbc_allcmd(struct AdapterControlBlock *acb) 687 { 688 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 689 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 690 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 691 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 692 } 693 } 694 /* 695 ********************************************************************* 696 ********************************************************************* 697 */ 698 static void arcmsr_abort_hbd_allcmd(struct AdapterControlBlock *acb) 699 { 700 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 701 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 702 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 703 } 704 } 705 /* 706 ********************************************************************* 707 ********************************************************************* 708 */ 709 static void arcmsr_abort_hbe_allcmd(struct AdapterControlBlock *acb) 710 { 711 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 712 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 713 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 714 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 715 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 716 } 717 } 718 /* 719 ********************************************************************* 720 ********************************************************************* 721 */ 722 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb) 723 { 724 switch (acb->adapter_type) { 725 case ACB_ADAPTER_TYPE_A: { 726 arcmsr_abort_hba_allcmd(acb); 727 } 728 break; 729 case ACB_ADAPTER_TYPE_B: { 730 arcmsr_abort_hbb_allcmd(acb); 731 } 732 break; 733 case ACB_ADAPTER_TYPE_C: { 734 arcmsr_abort_hbc_allcmd(acb); 735 } 736 break; 737 case ACB_ADAPTER_TYPE_D: { 738 arcmsr_abort_hbd_allcmd(acb); 739 } 740 break; 741 case ACB_ADAPTER_TYPE_E: 742 case ACB_ADAPTER_TYPE_F: { 743 arcmsr_abort_hbe_allcmd(acb); 744 } 745 break; 746 } 747 } 748 /* 749 ********************************************************************** 750 ********************************************************************** 751 */ 752 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag) 753 { 754 struct AdapterControlBlock *acb = srb->acb; 755 union ccb *pccb = srb->pccb; 756 757 if(srb->srb_flags & SRB_FLAG_TIMER_START) 758 callout_stop(&srb->ccb_callout); 759 if((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 760 bus_dmasync_op_t op; 761 762 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 763 op = BUS_DMASYNC_POSTREAD; 764 } else { 765 op = BUS_DMASYNC_POSTWRITE; 766 } 767 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op); 768 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap); 769 } 770 if(stand_flag == 1) { 771 atomic_subtract_int(&acb->srboutstandingcount, 1); 772 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) && ( 773 acb->srboutstandingcount < (acb->maxOutstanding -10))) { 774 acb->acb_flags &= ~ACB_F_CAM_DEV_QFRZN; 775 pccb->ccb_h.status |= CAM_RELEASE_SIMQ; 776 } 777 } 778 if(srb->srb_state != ARCMSR_SRB_TIMEOUT) 779 arcmsr_free_srb(srb); 780 acb->pktReturnCount++; 781 xpt_done(pccb); 782 } 783 /* 784 ************************************************************************** 785 ************************************************************************** 786 */ 787 static void arcmsr_report_srb_state(struct AdapterControlBlock *acb, struct CommandControlBlock *srb, u_int16_t error) 788 { 789 int target, lun; 790 791 target = srb->pccb->ccb_h.target_id; 792 lun = srb->pccb->ccb_h.target_lun; 793 if(error == FALSE) { 794 if(acb->devstate[target][lun] == ARECA_RAID_GONE) { 795 acb->devstate[target][lun] = ARECA_RAID_GOOD; 796 } 797 srb->pccb->ccb_h.status |= CAM_REQ_CMP; 798 arcmsr_srb_complete(srb, 1); 799 } else { 800 switch(srb->arcmsr_cdb.DeviceStatus) { 801 case ARCMSR_DEV_SELECT_TIMEOUT: { 802 if(acb->devstate[target][lun] == ARECA_RAID_GOOD) { 803 printf( "arcmsr%d: Target=%x, Lun=%x, selection timeout, raid volume was lost\n", acb->pci_unit, target, lun); 804 } 805 acb->devstate[target][lun] = ARECA_RAID_GONE; 806 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 807 arcmsr_srb_complete(srb, 1); 808 } 809 break; 810 case ARCMSR_DEV_ABORTED: 811 case ARCMSR_DEV_INIT_FAIL: { 812 acb->devstate[target][lun] = ARECA_RAID_GONE; 813 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 814 arcmsr_srb_complete(srb, 1); 815 } 816 break; 817 case SCSISTAT_CHECK_CONDITION: { 818 acb->devstate[target][lun] = ARECA_RAID_GOOD; 819 arcmsr_report_sense_info(srb); 820 arcmsr_srb_complete(srb, 1); 821 } 822 break; 823 default: 824 printf("arcmsr%d: scsi id=%d lun=%d isr got command error done,but got unknown DeviceStatus=0x%x \n" 825 , acb->pci_unit, target, lun ,srb->arcmsr_cdb.DeviceStatus); 826 acb->devstate[target][lun] = ARECA_RAID_GONE; 827 srb->pccb->ccb_h.status |= CAM_UNCOR_PARITY; 828 /*unknown error or crc error just for retry*/ 829 arcmsr_srb_complete(srb, 1); 830 break; 831 } 832 } 833 } 834 /* 835 ************************************************************************** 836 ************************************************************************** 837 */ 838 static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, u_int32_t flag_srb, u_int16_t error) 839 { 840 struct CommandControlBlock *srb; 841 842 /* check if command done with no error*/ 843 switch (acb->adapter_type) { 844 case ACB_ADAPTER_TYPE_A: 845 case ACB_ADAPTER_TYPE_B: 846 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 847 break; 848 case ACB_ADAPTER_TYPE_C: 849 case ACB_ADAPTER_TYPE_D: 850 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0)); /*frame must be 32 bytes aligned*/ 851 break; 852 case ACB_ADAPTER_TYPE_E: 853 case ACB_ADAPTER_TYPE_F: 854 srb = acb->psrb_pool[flag_srb]; 855 break; 856 default: 857 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 858 break; 859 } 860 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 861 if(srb->srb_state == ARCMSR_SRB_TIMEOUT) { 862 arcmsr_free_srb(srb); 863 printf("arcmsr%d: srb='%p' return srb has been timeouted\n", acb->pci_unit, srb); 864 return; 865 } 866 printf("arcmsr%d: return srb has been completed\n" 867 "srb='%p' srb_state=0x%x outstanding srb count=%d \n", 868 acb->pci_unit, srb, srb->srb_state, acb->srboutstandingcount); 869 return; 870 } 871 arcmsr_report_srb_state(acb, srb, error); 872 } 873 /* 874 ************************************************************************** 875 ************************************************************************** 876 */ 877 static void arcmsr_srb_timeout(void *arg) 878 { 879 struct CommandControlBlock *srb = (struct CommandControlBlock *)arg; 880 struct AdapterControlBlock *acb; 881 int target, lun; 882 u_int8_t cmd; 883 884 target = srb->pccb->ccb_h.target_id; 885 lun = srb->pccb->ccb_h.target_lun; 886 acb = srb->acb; 887 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 888 if(srb->srb_state == ARCMSR_SRB_START) 889 { 890 cmd = scsiio_cdb_ptr(&srb->pccb->csio)[0]; 891 srb->srb_state = ARCMSR_SRB_TIMEOUT; 892 srb->pccb->ccb_h.status |= CAM_CMD_TIMEOUT; 893 arcmsr_srb_complete(srb, 1); 894 printf("arcmsr%d: scsi id %d lun %d cmd=0x%x srb='%p' ccb command time out!\n", 895 acb->pci_unit, target, lun, cmd, srb); 896 } 897 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 898 #ifdef ARCMSR_DEBUG1 899 arcmsr_dump_data(acb); 900 #endif 901 } 902 903 /* 904 ********************************************************************** 905 ********************************************************************** 906 */ 907 static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb) 908 { 909 int i=0; 910 u_int32_t flag_srb; 911 u_int16_t error; 912 913 switch (acb->adapter_type) { 914 case ACB_ADAPTER_TYPE_A: { 915 u_int32_t outbound_intstatus; 916 917 /*clear and abort all outbound posted Q*/ 918 outbound_intstatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 919 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);/*clear interrupt*/ 920 while(((flag_srb=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_queueport)) != 0xFFFFFFFF) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) { 921 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 922 arcmsr_drain_donequeue(acb, flag_srb, error); 923 } 924 } 925 break; 926 case ACB_ADAPTER_TYPE_B: { 927 struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu; 928 929 /*clear all outbound posted Q*/ 930 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */ 931 for(i=0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) { 932 if((flag_srb = phbbmu->done_qbuffer[i]) != 0) { 933 phbbmu->done_qbuffer[i] = 0; 934 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 935 arcmsr_drain_donequeue(acb, flag_srb, error); 936 } 937 phbbmu->post_qbuffer[i] = 0; 938 }/*drain reply FIFO*/ 939 phbbmu->doneq_index = 0; 940 phbbmu->postq_index = 0; 941 } 942 break; 943 case ACB_ADAPTER_TYPE_C: { 944 while((CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) { 945 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 946 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 947 arcmsr_drain_donequeue(acb, flag_srb, error); 948 } 949 } 950 break; 951 case ACB_ADAPTER_TYPE_D: 952 arcmsr_hbd_postqueue_isr(acb); 953 break; 954 case ACB_ADAPTER_TYPE_E: 955 arcmsr_hbe_postqueue_isr(acb); 956 break; 957 case ACB_ADAPTER_TYPE_F: 958 arcmsr_hbf_postqueue_isr(acb); 959 break; 960 } 961 } 962 /* 963 **************************************************************************** 964 **************************************************************************** 965 */ 966 static void arcmsr_iop_reset(struct AdapterControlBlock *acb) 967 { 968 struct CommandControlBlock *srb; 969 u_int32_t intmask_org; 970 u_int32_t i=0; 971 972 if(acb->srboutstandingcount>0) { 973 /* disable all outbound interrupt */ 974 intmask_org = arcmsr_disable_allintr(acb); 975 /*clear and abort all outbound posted Q*/ 976 arcmsr_done4abort_postqueue(acb); 977 /* talk to iop 331 outstanding command aborted*/ 978 arcmsr_abort_allcmd(acb); 979 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 980 srb = acb->psrb_pool[i]; 981 if(srb->srb_state == ARCMSR_SRB_START) { 982 srb->srb_state = ARCMSR_SRB_ABORTED; 983 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 984 arcmsr_srb_complete(srb, 1); 985 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p' aborted\n" 986 , acb->pci_unit, srb->pccb->ccb_h.target_id 987 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 988 } 989 } 990 /* enable all outbound interrupt */ 991 arcmsr_enable_allintr(acb, intmask_org); 992 } 993 acb->srboutstandingcount = 0; 994 acb->workingsrb_doneindex = 0; 995 acb->workingsrb_startindex = 0; 996 acb->pktRequestCount = 0; 997 acb->pktReturnCount = 0; 998 } 999 /* 1000 ********************************************************************** 1001 ********************************************************************** 1002 */ 1003 static void arcmsr_build_srb(struct CommandControlBlock *srb, 1004 bus_dma_segment_t *dm_segs, u_int32_t nseg) 1005 { 1006 struct ARCMSR_CDB *arcmsr_cdb = &srb->arcmsr_cdb; 1007 u_int8_t *psge = (u_int8_t *)&arcmsr_cdb->u; 1008 u_int32_t address_lo, address_hi; 1009 union ccb *pccb = srb->pccb; 1010 struct ccb_scsiio *pcsio = &pccb->csio; 1011 u_int32_t arccdbsize = 0x30; 1012 1013 memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB)); 1014 arcmsr_cdb->Bus = 0; 1015 arcmsr_cdb->TargetID = pccb->ccb_h.target_id; 1016 arcmsr_cdb->LUN = pccb->ccb_h.target_lun; 1017 arcmsr_cdb->Function = 1; 1018 arcmsr_cdb->CdbLength = (u_int8_t)pcsio->cdb_len; 1019 bcopy(scsiio_cdb_ptr(pcsio), arcmsr_cdb->Cdb, pcsio->cdb_len); 1020 if(nseg != 0) { 1021 struct AdapterControlBlock *acb = srb->acb; 1022 bus_dmasync_op_t op; 1023 u_int32_t length, i, cdb_sgcount = 0; 1024 1025 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1026 op = BUS_DMASYNC_PREREAD; 1027 } else { 1028 op = BUS_DMASYNC_PREWRITE; 1029 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE; 1030 srb->srb_flags |= SRB_FLAG_WRITE; 1031 } 1032 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op); 1033 for(i=0; i < nseg; i++) { 1034 /* Get the physical address of the current data pointer */ 1035 length = arcmsr_htole32(dm_segs[i].ds_len); 1036 address_lo = arcmsr_htole32(dma_addr_lo32(dm_segs[i].ds_addr)); 1037 address_hi = arcmsr_htole32(dma_addr_hi32(dm_segs[i].ds_addr)); 1038 if(address_hi == 0) { 1039 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge; 1040 pdma_sg->address = address_lo; 1041 pdma_sg->length = length; 1042 psge += sizeof(struct SG32ENTRY); 1043 arccdbsize += sizeof(struct SG32ENTRY); 1044 } else { 1045 u_int32_t sg64s_size = 0, tmplength = length; 1046 1047 while(1) { 1048 u_int64_t span4G, length0; 1049 struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge; 1050 1051 span4G = (u_int64_t)address_lo + tmplength; 1052 pdma_sg->addresshigh = address_hi; 1053 pdma_sg->address = address_lo; 1054 if(span4G > 0x100000000) { 1055 /*see if cross 4G boundary*/ 1056 length0 = 0x100000000-address_lo; 1057 pdma_sg->length = (u_int32_t)length0 | IS_SG64_ADDR; 1058 address_hi = address_hi+1; 1059 address_lo = 0; 1060 tmplength = tmplength - (u_int32_t)length0; 1061 sg64s_size += sizeof(struct SG64ENTRY); 1062 psge += sizeof(struct SG64ENTRY); 1063 cdb_sgcount++; 1064 } else { 1065 pdma_sg->length = tmplength | IS_SG64_ADDR; 1066 sg64s_size += sizeof(struct SG64ENTRY); 1067 psge += sizeof(struct SG64ENTRY); 1068 break; 1069 } 1070 } 1071 arccdbsize += sg64s_size; 1072 } 1073 cdb_sgcount++; 1074 } 1075 arcmsr_cdb->sgcount = (u_int8_t)cdb_sgcount; 1076 arcmsr_cdb->DataLength = pcsio->dxfer_len; 1077 if( arccdbsize > 256) { 1078 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE; 1079 } 1080 } else { 1081 arcmsr_cdb->DataLength = 0; 1082 } 1083 srb->arc_cdb_size = arccdbsize; 1084 arcmsr_cdb->msgPages = (arccdbsize/256) + ((arccdbsize % 256) ? 1 : 0); 1085 } 1086 /* 1087 ************************************************************************** 1088 ************************************************************************** 1089 */ 1090 static void arcmsr_post_srb(struct AdapterControlBlock *acb, struct CommandControlBlock *srb) 1091 { 1092 u_int32_t cdb_phyaddr_low = (u_int32_t) srb->cdb_phyaddr_low; 1093 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&srb->arcmsr_cdb; 1094 1095 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, (srb->srb_flags & SRB_FLAG_WRITE) ? BUS_DMASYNC_POSTWRITE:BUS_DMASYNC_POSTREAD); 1096 atomic_add_int(&acb->srboutstandingcount, 1); 1097 srb->srb_state = ARCMSR_SRB_START; 1098 1099 switch (acb->adapter_type) { 1100 case ACB_ADAPTER_TYPE_A: { 1101 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { 1102 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low|ARCMSR_SRBPOST_FLAG_SGL_BSIZE); 1103 } else { 1104 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low); 1105 } 1106 } 1107 break; 1108 case ACB_ADAPTER_TYPE_B: { 1109 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1110 int ending_index, index; 1111 1112 index = phbbmu->postq_index; 1113 ending_index = ((index+1) % ARCMSR_MAX_HBB_POSTQUEUE); 1114 phbbmu->post_qbuffer[ending_index] = 0; 1115 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { 1116 phbbmu->post_qbuffer[index] = cdb_phyaddr_low | ARCMSR_SRBPOST_FLAG_SGL_BSIZE; 1117 } else { 1118 phbbmu->post_qbuffer[index] = cdb_phyaddr_low; 1119 } 1120 index++; 1121 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 1122 phbbmu->postq_index = index; 1123 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_CDB_POSTED); 1124 } 1125 break; 1126 case ACB_ADAPTER_TYPE_C: { 1127 u_int32_t ccb_post_stamp, arc_cdb_size, cdb_phyaddr_hi32; 1128 1129 arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size; 1130 ccb_post_stamp = (cdb_phyaddr_low | ((arc_cdb_size-1) >> 6) | 1); 1131 cdb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high; 1132 if(cdb_phyaddr_hi32) 1133 { 1134 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_high, cdb_phyaddr_hi32); 1135 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp); 1136 } 1137 else 1138 { 1139 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp); 1140 } 1141 } 1142 break; 1143 case ACB_ADAPTER_TYPE_D: { 1144 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1145 u_int16_t index_stripped; 1146 u_int16_t postq_index; 1147 struct InBound_SRB *pinbound_srb; 1148 1149 ARCMSR_LOCK_ACQUIRE(&acb->postDone_lock); 1150 postq_index = phbdmu->postq_index; 1151 pinbound_srb = (struct InBound_SRB *)&phbdmu->post_qbuffer[postq_index & 0xFF]; 1152 pinbound_srb->addressHigh = srb->cdb_phyaddr_high; 1153 pinbound_srb->addressLow = srb->cdb_phyaddr_low; 1154 pinbound_srb->length = srb->arc_cdb_size >> 2; 1155 arcmsr_cdb->Context = srb->cdb_phyaddr_low; 1156 if (postq_index & 0x4000) { 1157 index_stripped = postq_index & 0xFF; 1158 index_stripped += 1; 1159 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1160 phbdmu->postq_index = index_stripped ? (index_stripped | 0x4000) : index_stripped; 1161 } else { 1162 index_stripped = postq_index; 1163 index_stripped += 1; 1164 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1165 phbdmu->postq_index = index_stripped ? index_stripped : (index_stripped | 0x4000); 1166 } 1167 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inboundlist_write_pointer, postq_index); 1168 ARCMSR_LOCK_RELEASE(&acb->postDone_lock); 1169 } 1170 break; 1171 case ACB_ADAPTER_TYPE_E: { 1172 u_int32_t ccb_post_stamp, arc_cdb_size; 1173 1174 arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size; 1175 ccb_post_stamp = (srb->smid | ((arc_cdb_size-1) >> 6)); 1176 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_queueport_high, 0); 1177 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_queueport_low, ccb_post_stamp); 1178 } 1179 break; 1180 case ACB_ADAPTER_TYPE_F: { 1181 u_int32_t ccb_post_stamp, arc_cdb_size; 1182 1183 if (srb->arc_cdb_size <= 0x300) 1184 arc_cdb_size = (srb->arc_cdb_size - 1) >> 6 | 1; 1185 else { 1186 arc_cdb_size = ((srb->arc_cdb_size + 0xff) >> 8) + 2; 1187 if (arc_cdb_size > 0xF) 1188 arc_cdb_size = 0xF; 1189 arc_cdb_size = (arc_cdb_size << 1) | 1; 1190 } 1191 ccb_post_stamp = (srb->smid | arc_cdb_size); 1192 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_queueport_high, 0); 1193 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_queueport_low, ccb_post_stamp); 1194 } 1195 break; 1196 } 1197 } 1198 /* 1199 ************************************************************************ 1200 ************************************************************************ 1201 */ 1202 static struct QBUFFER *arcmsr_get_iop_rqbuffer( struct AdapterControlBlock *acb) 1203 { 1204 struct QBUFFER *qbuffer=NULL; 1205 1206 switch (acb->adapter_type) { 1207 case ACB_ADAPTER_TYPE_A: { 1208 struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu; 1209 1210 qbuffer = (struct QBUFFER *)&phbamu->message_rbuffer; 1211 } 1212 break; 1213 case ACB_ADAPTER_TYPE_B: { 1214 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1215 1216 qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_rbuffer; 1217 } 1218 break; 1219 case ACB_ADAPTER_TYPE_C: { 1220 struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu; 1221 1222 qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer; 1223 } 1224 break; 1225 case ACB_ADAPTER_TYPE_D: { 1226 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1227 1228 qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_rbuffer; 1229 } 1230 break; 1231 case ACB_ADAPTER_TYPE_E: { 1232 struct HBE_MessageUnit *phbcmu = (struct HBE_MessageUnit *)acb->pmu; 1233 1234 qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer; 1235 } 1236 break; 1237 case ACB_ADAPTER_TYPE_F: 1238 qbuffer = (struct QBUFFER *)acb->message_rbuffer; 1239 break; 1240 } 1241 return(qbuffer); 1242 } 1243 /* 1244 ************************************************************************ 1245 ************************************************************************ 1246 */ 1247 static struct QBUFFER *arcmsr_get_iop_wqbuffer( struct AdapterControlBlock *acb) 1248 { 1249 struct QBUFFER *qbuffer = NULL; 1250 1251 switch (acb->adapter_type) { 1252 case ACB_ADAPTER_TYPE_A: { 1253 struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu; 1254 1255 qbuffer = (struct QBUFFER *)&phbamu->message_wbuffer; 1256 } 1257 break; 1258 case ACB_ADAPTER_TYPE_B: { 1259 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1260 1261 qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_wbuffer; 1262 } 1263 break; 1264 case ACB_ADAPTER_TYPE_C: { 1265 struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu; 1266 1267 qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer; 1268 } 1269 break; 1270 case ACB_ADAPTER_TYPE_D: { 1271 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1272 1273 qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_wbuffer; 1274 } 1275 break; 1276 case ACB_ADAPTER_TYPE_E: { 1277 struct HBE_MessageUnit *phbcmu = (struct HBE_MessageUnit *)acb->pmu; 1278 1279 qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer; 1280 } 1281 break; 1282 case ACB_ADAPTER_TYPE_F: 1283 qbuffer = (struct QBUFFER *)acb->message_wbuffer; 1284 break; 1285 } 1286 return(qbuffer); 1287 } 1288 /* 1289 ************************************************************************** 1290 ************************************************************************** 1291 */ 1292 static void arcmsr_iop_message_read(struct AdapterControlBlock *acb) 1293 { 1294 switch (acb->adapter_type) { 1295 case ACB_ADAPTER_TYPE_A: { 1296 /* let IOP know data has been read */ 1297 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK); 1298 } 1299 break; 1300 case ACB_ADAPTER_TYPE_B: { 1301 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1302 /* let IOP know data has been read */ 1303 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK); 1304 } 1305 break; 1306 case ACB_ADAPTER_TYPE_C: { 1307 /* let IOP know data has been read */ 1308 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK); 1309 } 1310 break; 1311 case ACB_ADAPTER_TYPE_D: { 1312 /* let IOP know data has been read */ 1313 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ); 1314 } 1315 break; 1316 case ACB_ADAPTER_TYPE_E: 1317 case ACB_ADAPTER_TYPE_F: { 1318 /* let IOP know data has been read */ 1319 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK; 1320 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 1321 } 1322 break; 1323 } 1324 } 1325 /* 1326 ************************************************************************** 1327 ************************************************************************** 1328 */ 1329 static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb) 1330 { 1331 switch (acb->adapter_type) { 1332 case ACB_ADAPTER_TYPE_A: { 1333 /* 1334 ** push inbound doorbell tell iop, driver data write ok 1335 ** and wait reply on next hwinterrupt for next Qbuffer post 1336 */ 1337 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK); 1338 } 1339 break; 1340 case ACB_ADAPTER_TYPE_B: { 1341 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1342 /* 1343 ** push inbound doorbell tell iop, driver data write ok 1344 ** and wait reply on next hwinterrupt for next Qbuffer post 1345 */ 1346 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_WRITE_OK); 1347 } 1348 break; 1349 case ACB_ADAPTER_TYPE_C: { 1350 /* 1351 ** push inbound doorbell tell iop, driver data write ok 1352 ** and wait reply on next hwinterrupt for next Qbuffer post 1353 */ 1354 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK); 1355 } 1356 break; 1357 case ACB_ADAPTER_TYPE_D: { 1358 /* 1359 ** push inbound doorbell tell iop, driver data write ok 1360 ** and wait reply on next hwinterrupt for next Qbuffer post 1361 */ 1362 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY); 1363 } 1364 break; 1365 case ACB_ADAPTER_TYPE_E: 1366 case ACB_ADAPTER_TYPE_F: { 1367 /* 1368 ** push inbound doorbell tell iop, driver data write ok 1369 ** and wait reply on next hwinterrupt for next Qbuffer post 1370 */ 1371 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK; 1372 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 1373 } 1374 break; 1375 } 1376 } 1377 /* 1378 ************************************************************************ 1379 ************************************************************************ 1380 */ 1381 static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb) 1382 { 1383 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1384 CHIP_REG_WRITE32(HBA_MessageUnit, 1385 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1386 if(!arcmsr_hba_wait_msgint_ready(acb)) { 1387 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n" 1388 , acb->pci_unit); 1389 } 1390 } 1391 /* 1392 ************************************************************************ 1393 ************************************************************************ 1394 */ 1395 static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb) 1396 { 1397 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1398 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1399 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_STOP_BGRB); 1400 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 1401 printf( "arcmsr%d: wait 'stop adapter background rebulid' timeout \n" 1402 , acb->pci_unit); 1403 } 1404 } 1405 /* 1406 ************************************************************************ 1407 ************************************************************************ 1408 */ 1409 static void arcmsr_stop_hbc_bgrb(struct AdapterControlBlock *acb) 1410 { 1411 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1412 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1413 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 1414 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 1415 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1416 } 1417 } 1418 /* 1419 ************************************************************************ 1420 ************************************************************************ 1421 */ 1422 static void arcmsr_stop_hbd_bgrb(struct AdapterControlBlock *acb) 1423 { 1424 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1425 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1426 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 1427 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1428 } 1429 } 1430 /* 1431 ************************************************************************ 1432 ************************************************************************ 1433 */ 1434 static void arcmsr_stop_hbe_bgrb(struct AdapterControlBlock *acb) 1435 { 1436 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1437 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1438 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 1439 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 1440 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 1441 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1442 } 1443 } 1444 /* 1445 ************************************************************************ 1446 ************************************************************************ 1447 */ 1448 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb) 1449 { 1450 switch (acb->adapter_type) { 1451 case ACB_ADAPTER_TYPE_A: { 1452 arcmsr_stop_hba_bgrb(acb); 1453 } 1454 break; 1455 case ACB_ADAPTER_TYPE_B: { 1456 arcmsr_stop_hbb_bgrb(acb); 1457 } 1458 break; 1459 case ACB_ADAPTER_TYPE_C: { 1460 arcmsr_stop_hbc_bgrb(acb); 1461 } 1462 break; 1463 case ACB_ADAPTER_TYPE_D: { 1464 arcmsr_stop_hbd_bgrb(acb); 1465 } 1466 break; 1467 case ACB_ADAPTER_TYPE_E: 1468 case ACB_ADAPTER_TYPE_F: { 1469 arcmsr_stop_hbe_bgrb(acb); 1470 } 1471 break; 1472 } 1473 } 1474 /* 1475 ************************************************************************ 1476 ************************************************************************ 1477 */ 1478 static void arcmsr_poll(struct cam_sim *psim) 1479 { 1480 struct AdapterControlBlock *acb; 1481 int mutex; 1482 1483 acb = (struct AdapterControlBlock *)cam_sim_softc(psim); 1484 mutex = mtx_owned(&acb->isr_lock); 1485 if( mutex == 0 ) 1486 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 1487 arcmsr_interrupt(acb); 1488 if( mutex == 0 ) 1489 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 1490 } 1491 /* 1492 ************************************************************************** 1493 ************************************************************************** 1494 */ 1495 static u_int32_t arcmsr_Read_iop_rqbuffer_data_D(struct AdapterControlBlock *acb, 1496 struct QBUFFER *prbuffer) { 1497 u_int8_t *pQbuffer; 1498 u_int8_t *buf1 = NULL; 1499 u_int32_t *iop_data, *buf2 = NULL; 1500 u_int32_t iop_len, data_len; 1501 1502 iop_data = (u_int32_t *)prbuffer->data; 1503 iop_len = (u_int32_t)prbuffer->data_len; 1504 if ( iop_len > 0 ) 1505 { 1506 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO); 1507 buf2 = (u_int32_t *)buf1; 1508 if( buf1 == NULL) 1509 return (0); 1510 data_len = iop_len; 1511 while(data_len >= 4) 1512 { 1513 *buf2++ = *iop_data++; 1514 data_len -= 4; 1515 } 1516 if(data_len) 1517 *buf2 = *iop_data; 1518 buf2 = (u_int32_t *)buf1; 1519 } 1520 while (iop_len > 0) { 1521 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex]; 1522 *pQbuffer = *buf1; 1523 acb->rqbuf_lastindex++; 1524 /* if last, index number set it to 0 */ 1525 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 1526 buf1++; 1527 iop_len--; 1528 } 1529 if(buf2) 1530 free( (u_int8_t *)buf2, M_DEVBUF); 1531 /* let IOP know data has been read */ 1532 arcmsr_iop_message_read(acb); 1533 return (1); 1534 } 1535 /* 1536 ************************************************************************** 1537 ************************************************************************** 1538 */ 1539 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, 1540 struct QBUFFER *prbuffer) { 1541 u_int8_t *pQbuffer; 1542 u_int8_t *iop_data; 1543 u_int32_t iop_len; 1544 1545 if(acb->adapter_type >= ACB_ADAPTER_TYPE_B) { 1546 return(arcmsr_Read_iop_rqbuffer_data_D(acb, prbuffer)); 1547 } 1548 iop_data = (u_int8_t *)prbuffer->data; 1549 iop_len = (u_int32_t)prbuffer->data_len; 1550 while (iop_len > 0) { 1551 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex]; 1552 *pQbuffer = *iop_data; 1553 acb->rqbuf_lastindex++; 1554 /* if last, index number set it to 0 */ 1555 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 1556 iop_data++; 1557 iop_len--; 1558 } 1559 /* let IOP know data has been read */ 1560 arcmsr_iop_message_read(acb); 1561 return (1); 1562 } 1563 /* 1564 ************************************************************************** 1565 ************************************************************************** 1566 */ 1567 static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb) 1568 { 1569 struct QBUFFER *prbuffer; 1570 int my_empty_len; 1571 1572 /*check this iop data if overflow my rqbuffer*/ 1573 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 1574 prbuffer = arcmsr_get_iop_rqbuffer(acb); 1575 my_empty_len = (acb->rqbuf_lastindex - acb->rqbuf_firstindex - 1) & 1576 (ARCMSR_MAX_QBUFFER-1); 1577 if(my_empty_len >= prbuffer->data_len) { 1578 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 1579 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 1580 } else { 1581 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 1582 } 1583 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 1584 } 1585 /* 1586 ********************************************************************** 1587 ********************************************************************** 1588 */ 1589 static void arcmsr_Write_data_2iop_wqbuffer_D(struct AdapterControlBlock *acb) 1590 { 1591 u_int8_t *pQbuffer; 1592 struct QBUFFER *pwbuffer; 1593 u_int8_t *buf1 = NULL; 1594 u_int32_t *iop_data, *buf2 = NULL; 1595 u_int32_t allxfer_len = 0, data_len; 1596 1597 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) { 1598 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO); 1599 buf2 = (u_int32_t *)buf1; 1600 if( buf1 == NULL) 1601 return; 1602 1603 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ); 1604 pwbuffer = arcmsr_get_iop_wqbuffer(acb); 1605 iop_data = (u_int32_t *)pwbuffer->data; 1606 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex) 1607 && (allxfer_len < 124)) { 1608 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex]; 1609 *buf1 = *pQbuffer; 1610 acb->wqbuf_firstindex++; 1611 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 1612 buf1++; 1613 allxfer_len++; 1614 } 1615 pwbuffer->data_len = allxfer_len; 1616 data_len = allxfer_len; 1617 buf1 = (u_int8_t *)buf2; 1618 while(data_len >= 4) 1619 { 1620 *iop_data++ = *buf2++; 1621 data_len -= 4; 1622 } 1623 if(data_len) 1624 *iop_data = *buf2; 1625 free( buf1, M_DEVBUF); 1626 arcmsr_iop_message_wrote(acb); 1627 } 1628 } 1629 /* 1630 ********************************************************************** 1631 ********************************************************************** 1632 */ 1633 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb) 1634 { 1635 u_int8_t *pQbuffer; 1636 struct QBUFFER *pwbuffer; 1637 u_int8_t *iop_data; 1638 int32_t allxfer_len=0; 1639 1640 if(acb->adapter_type >= ACB_ADAPTER_TYPE_B) { 1641 arcmsr_Write_data_2iop_wqbuffer_D(acb); 1642 return; 1643 } 1644 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) { 1645 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ); 1646 pwbuffer = arcmsr_get_iop_wqbuffer(acb); 1647 iop_data = (u_int8_t *)pwbuffer->data; 1648 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex) 1649 && (allxfer_len < 124)) { 1650 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex]; 1651 *iop_data = *pQbuffer; 1652 acb->wqbuf_firstindex++; 1653 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 1654 iop_data++; 1655 allxfer_len++; 1656 } 1657 pwbuffer->data_len = allxfer_len; 1658 arcmsr_iop_message_wrote(acb); 1659 } 1660 } 1661 /* 1662 ************************************************************************** 1663 ************************************************************************** 1664 */ 1665 static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb) 1666 { 1667 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 1668 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READ; 1669 /* 1670 ***************************************************************** 1671 ** check if there are any mail packages from user space program 1672 ** in my post bag, now is the time to send them into Areca's firmware 1673 ***************************************************************** 1674 */ 1675 if(acb->wqbuf_firstindex != acb->wqbuf_lastindex) { 1676 arcmsr_Write_data_2iop_wqbuffer(acb); 1677 } 1678 if(acb->wqbuf_firstindex == acb->wqbuf_lastindex) { 1679 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED; 1680 } 1681 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 1682 } 1683 /* 1684 ************************************************************************** 1685 ************************************************************************** 1686 */ 1687 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb) 1688 { 1689 /* 1690 if (ccb->ccb_h.status != CAM_REQ_CMP) 1691 printf("arcmsr_rescanLun_cb: Rescan Target=%x, lun=%x," 1692 "failure status=%x\n", ccb->ccb_h.target_id, 1693 ccb->ccb_h.target_lun, ccb->ccb_h.status); 1694 else 1695 printf("arcmsr_rescanLun_cb: Rescan lun successfully!\n"); 1696 */ 1697 xpt_free_path(ccb->ccb_h.path); 1698 xpt_free_ccb(ccb); 1699 } 1700 1701 static void arcmsr_rescan_lun(struct AdapterControlBlock *acb, int target, int lun) 1702 { 1703 struct cam_path *path; 1704 union ccb *ccb; 1705 1706 if ((ccb = (union ccb *)xpt_alloc_ccb_nowait()) == NULL) 1707 return; 1708 if (xpt_create_path(&path, NULL, cam_sim_path(acb->psim), target, lun) != CAM_REQ_CMP) 1709 { 1710 xpt_free_ccb(ccb); 1711 return; 1712 } 1713 /* printf("arcmsr_rescan_lun: Rescan Target=%x, Lun=%x\n", target, lun); */ 1714 xpt_setup_ccb(&ccb->ccb_h, path, 5); 1715 ccb->ccb_h.func_code = XPT_SCAN_LUN; 1716 ccb->ccb_h.cbfcnp = arcmsr_rescanLun_cb; 1717 ccb->crcn.flags = CAM_FLAG_NONE; 1718 xpt_action(ccb); 1719 } 1720 1721 static void arcmsr_abort_dr_ccbs(struct AdapterControlBlock *acb, int target, int lun) 1722 { 1723 struct CommandControlBlock *srb; 1724 u_int32_t intmask_org; 1725 int i; 1726 1727 /* disable all outbound interrupts */ 1728 intmask_org = arcmsr_disable_allintr(acb); 1729 for (i = 0; i < ARCMSR_MAX_FREESRB_NUM; i++) 1730 { 1731 srb = acb->psrb_pool[i]; 1732 if (srb->srb_state == ARCMSR_SRB_START) 1733 { 1734 if((target == srb->pccb->ccb_h.target_id) && (lun == srb->pccb->ccb_h.target_lun)) 1735 { 1736 srb->srb_state = ARCMSR_SRB_ABORTED; 1737 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 1738 arcmsr_srb_complete(srb, 1); 1739 printf("arcmsr%d: abort scsi id %d lun %d srb=%p \n", acb->pci_unit, target, lun, srb); 1740 } 1741 } 1742 } 1743 /* enable outbound Post Queue, outbound doorbell Interrupt */ 1744 arcmsr_enable_allintr(acb, intmask_org); 1745 } 1746 /* 1747 ************************************************************************** 1748 ************************************************************************** 1749 */ 1750 static void arcmsr_dr_handle(struct AdapterControlBlock *acb) { 1751 u_int32_t devicemap; 1752 u_int32_t target, lun; 1753 u_int32_t deviceMapCurrent[4]={0}; 1754 u_int8_t *pDevMap; 1755 1756 switch (acb->adapter_type) { 1757 case ACB_ADAPTER_TYPE_A: 1758 devicemap = offsetof(struct HBA_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1759 for (target = 0; target < 4; target++) 1760 { 1761 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1762 devicemap += 4; 1763 } 1764 break; 1765 1766 case ACB_ADAPTER_TYPE_B: 1767 devicemap = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1768 for (target = 0; target < 4; target++) 1769 { 1770 deviceMapCurrent[target]=bus_space_read_4(acb->btag[1], acb->bhandle[1], devicemap); 1771 devicemap += 4; 1772 } 1773 break; 1774 1775 case ACB_ADAPTER_TYPE_C: 1776 devicemap = offsetof(struct HBC_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1777 for (target = 0; target < 4; target++) 1778 { 1779 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1780 devicemap += 4; 1781 } 1782 break; 1783 case ACB_ADAPTER_TYPE_D: 1784 devicemap = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1785 for (target = 0; target < 4; target++) 1786 { 1787 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1788 devicemap += 4; 1789 } 1790 break; 1791 case ACB_ADAPTER_TYPE_E: 1792 devicemap = offsetof(struct HBE_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1793 for (target = 0; target < 4; target++) 1794 { 1795 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1796 devicemap += 4; 1797 } 1798 break; 1799 case ACB_ADAPTER_TYPE_F: 1800 devicemap = ARCMSR_FW_DEVMAP_OFFSET; 1801 for (target = 0; target < 4; target++) 1802 { 1803 deviceMapCurrent[target] = acb->msgcode_rwbuffer[devicemap]; 1804 devicemap += 1; 1805 } 1806 break; 1807 } 1808 1809 if(acb->acb_flags & ACB_F_BUS_HANG_ON) 1810 { 1811 acb->acb_flags &= ~ACB_F_BUS_HANG_ON; 1812 } 1813 /* 1814 ** adapter posted CONFIG message 1815 ** copy the new map, note if there are differences with the current map 1816 */ 1817 pDevMap = (u_int8_t *)&deviceMapCurrent[0]; 1818 for (target = 0; target < ARCMSR_MAX_TARGETID - 1; target++) 1819 { 1820 if (*pDevMap != acb->device_map[target]) 1821 { 1822 u_int8_t difference, bit_check; 1823 1824 difference = *pDevMap ^ acb->device_map[target]; 1825 for(lun=0; lun < ARCMSR_MAX_TARGETLUN; lun++) 1826 { 1827 bit_check = (1 << lun); /*check bit from 0....31*/ 1828 if(difference & bit_check) 1829 { 1830 if(acb->device_map[target] & bit_check) 1831 {/* unit departed */ 1832 printf("arcmsr_dr_handle: Target=%x, lun=%x, GONE!!!\n",target,lun); 1833 arcmsr_abort_dr_ccbs(acb, target, lun); 1834 arcmsr_rescan_lun(acb, target, lun); 1835 acb->devstate[target][lun] = ARECA_RAID_GONE; 1836 } 1837 else 1838 {/* unit arrived */ 1839 printf("arcmsr_dr_handle: Target=%x, lun=%x, Plug-IN!!!\n",target,lun); 1840 arcmsr_rescan_lun(acb, target, lun); 1841 acb->devstate[target][lun] = ARECA_RAID_GOOD; 1842 } 1843 } 1844 } 1845 /* printf("arcmsr_dr_handle: acb->device_map[%x]=0x%x, deviceMapCurrent[%x]=%x\n",target,acb->device_map[target],target,*pDevMap); */ 1846 acb->device_map[target] = *pDevMap; 1847 } 1848 pDevMap++; 1849 } 1850 } 1851 /* 1852 ************************************************************************** 1853 ************************************************************************** 1854 */ 1855 static void arcmsr_hba_message_isr(struct AdapterControlBlock *acb) { 1856 u_int32_t outbound_message; 1857 1858 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT); 1859 outbound_message = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[0]); 1860 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1861 arcmsr_dr_handle( acb ); 1862 } 1863 /* 1864 ************************************************************************** 1865 ************************************************************************** 1866 */ 1867 static void arcmsr_hbb_message_isr(struct AdapterControlBlock *acb) { 1868 u_int32_t outbound_message; 1869 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1870 1871 /* clear interrupts */ 1872 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN); 1873 outbound_message = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0]); 1874 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1875 arcmsr_dr_handle( acb ); 1876 } 1877 /* 1878 ************************************************************************** 1879 ************************************************************************** 1880 */ 1881 static void arcmsr_hbc_message_isr(struct AdapterControlBlock *acb) { 1882 u_int32_t outbound_message; 1883 1884 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR); 1885 outbound_message = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[0]); 1886 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1887 arcmsr_dr_handle( acb ); 1888 } 1889 /* 1890 ************************************************************************** 1891 ************************************************************************** 1892 */ 1893 static void arcmsr_hbd_message_isr(struct AdapterControlBlock *acb) { 1894 u_int32_t outbound_message; 1895 1896 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR); 1897 outbound_message = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[0]); 1898 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1899 arcmsr_dr_handle( acb ); 1900 } 1901 /* 1902 ************************************************************************** 1903 ************************************************************************** 1904 */ 1905 static void arcmsr_hbe_message_isr(struct AdapterControlBlock *acb) { 1906 u_int32_t outbound_message; 1907 1908 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); 1909 if (acb->adapter_type == ACB_ADAPTER_TYPE_E) 1910 outbound_message = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[0]); 1911 else 1912 outbound_message = acb->msgcode_rwbuffer[0]; 1913 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1914 arcmsr_dr_handle( acb ); 1915 } 1916 /* 1917 ************************************************************************** 1918 ************************************************************************** 1919 */ 1920 static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb) 1921 { 1922 u_int32_t doorbell_status; 1923 1924 /* 1925 ******************************************************************* 1926 ** Maybe here we need to check wrqbuffer_lock is lock or not 1927 ** DOORBELL: din! don! 1928 ** check if there are any mail need to pack from firmware 1929 ******************************************************************* 1930 */ 1931 doorbell_status = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell); 1932 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */ 1933 if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) { 1934 arcmsr_iop2drv_data_wrote_handle(acb); 1935 } 1936 if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) { 1937 arcmsr_iop2drv_data_read_handle(acb); 1938 } 1939 } 1940 /* 1941 ************************************************************************** 1942 ************************************************************************** 1943 */ 1944 static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *acb) 1945 { 1946 u_int32_t doorbell_status; 1947 1948 /* 1949 ******************************************************************* 1950 ** Maybe here we need to check wrqbuffer_lock is lock or not 1951 ** DOORBELL: din! don! 1952 ** check if there are any mail need to pack from firmware 1953 ******************************************************************* 1954 */ 1955 doorbell_status = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell); 1956 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, doorbell_status); /* clear doorbell interrupt */ 1957 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) { 1958 arcmsr_iop2drv_data_wrote_handle(acb); 1959 } 1960 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) { 1961 arcmsr_iop2drv_data_read_handle(acb); 1962 } 1963 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 1964 arcmsr_hbc_message_isr(acb); /* messenger of "driver to iop commands" */ 1965 } 1966 } 1967 /* 1968 ************************************************************************** 1969 ************************************************************************** 1970 */ 1971 static void arcmsr_hbd_doorbell_isr(struct AdapterControlBlock *acb) 1972 { 1973 u_int32_t doorbell_status; 1974 1975 /* 1976 ******************************************************************* 1977 ** Maybe here we need to check wrqbuffer_lock is lock or not 1978 ** DOORBELL: din! don! 1979 ** check if there are any mail need to pack from firmware 1980 ******************************************************************* 1981 */ 1982 doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE; 1983 if(doorbell_status) 1984 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */ 1985 while( doorbell_status & ARCMSR_HBDMU_F0_DOORBELL_CAUSE ) { 1986 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK) { 1987 arcmsr_iop2drv_data_wrote_handle(acb); 1988 } 1989 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK) { 1990 arcmsr_iop2drv_data_read_handle(acb); 1991 } 1992 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) { 1993 arcmsr_hbd_message_isr(acb); /* messenger of "driver to iop commands" */ 1994 } 1995 doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE; 1996 if(doorbell_status) 1997 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */ 1998 } 1999 } 2000 /* 2001 ************************************************************************** 2002 ************************************************************************** 2003 */ 2004 static void arcmsr_hbe_doorbell_isr(struct AdapterControlBlock *acb) 2005 { 2006 u_int32_t doorbell_status, in_doorbell; 2007 2008 /* 2009 ******************************************************************* 2010 ** Maybe here we need to check wrqbuffer_lock is lock or not 2011 ** DOORBELL: din! don! 2012 ** check if there are any mail need to pack from firmware 2013 ******************************************************************* 2014 */ 2015 in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell); 2016 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /* clear doorbell interrupt */ 2017 doorbell_status = in_doorbell ^ acb->in_doorbell; 2018 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) { 2019 arcmsr_iop2drv_data_wrote_handle(acb); 2020 } 2021 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK) { 2022 arcmsr_iop2drv_data_read_handle(acb); 2023 } 2024 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) { 2025 arcmsr_hbe_message_isr(acb); /* messenger of "driver to iop commands" */ 2026 } 2027 acb->in_doorbell = in_doorbell; 2028 } 2029 /* 2030 ************************************************************************** 2031 ************************************************************************** 2032 */ 2033 static void arcmsr_hbf_doorbell_isr(struct AdapterControlBlock *acb) 2034 { 2035 u_int32_t doorbell_status, in_doorbell; 2036 2037 /* 2038 ******************************************************************* 2039 ** Maybe here we need to check wrqbuffer_lock is lock or not 2040 ** DOORBELL: din! don! 2041 ** check if there are any mail need to pack from firmware 2042 ******************************************************************* 2043 */ 2044 while(1) { 2045 in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell); 2046 if ((in_doorbell != 0) && (in_doorbell != 0xFFFFFFFF)) 2047 break; 2048 } 2049 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /* clear doorbell interrupt */ 2050 doorbell_status = in_doorbell ^ acb->in_doorbell; 2051 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) { 2052 arcmsr_iop2drv_data_wrote_handle(acb); 2053 } 2054 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK) { 2055 arcmsr_iop2drv_data_read_handle(acb); 2056 } 2057 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) { 2058 arcmsr_hbe_message_isr(acb); /* messenger of "driver to iop commands" */ 2059 } 2060 acb->in_doorbell = in_doorbell; 2061 } 2062 /* 2063 ************************************************************************** 2064 ************************************************************************** 2065 */ 2066 static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb) 2067 { 2068 u_int32_t flag_srb; 2069 u_int16_t error; 2070 2071 /* 2072 ***************************************************************************** 2073 ** areca cdb command done 2074 ***************************************************************************** 2075 */ 2076 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 2077 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2078 while((flag_srb = CHIP_REG_READ32(HBA_MessageUnit, 2079 0, outbound_queueport)) != 0xFFFFFFFF) { 2080 /* check if command done with no error*/ 2081 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0) ? TRUE : FALSE; 2082 arcmsr_drain_donequeue(acb, flag_srb, error); 2083 } /*drain reply FIFO*/ 2084 } 2085 /* 2086 ************************************************************************** 2087 ************************************************************************** 2088 */ 2089 static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb) 2090 { 2091 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 2092 u_int32_t flag_srb; 2093 int index; 2094 u_int16_t error; 2095 2096 /* 2097 ***************************************************************************** 2098 ** areca cdb command done 2099 ***************************************************************************** 2100 */ 2101 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 2102 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2103 index = phbbmu->doneq_index; 2104 while((flag_srb = phbbmu->done_qbuffer[index]) != 0) { 2105 phbbmu->done_qbuffer[index] = 0; 2106 index++; 2107 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 2108 phbbmu->doneq_index = index; 2109 /* check if command done with no error*/ 2110 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 2111 arcmsr_drain_donequeue(acb, flag_srb, error); 2112 } /*drain reply FIFO*/ 2113 } 2114 /* 2115 ************************************************************************** 2116 ************************************************************************** 2117 */ 2118 static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb) 2119 { 2120 u_int32_t flag_srb,throttling = 0; 2121 u_int16_t error; 2122 2123 /* 2124 ***************************************************************************** 2125 ** areca cdb command done 2126 ***************************************************************************** 2127 */ 2128 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2129 do { 2130 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 2131 if (flag_srb == 0xFFFFFFFF) 2132 break; 2133 /* check if command done with no error*/ 2134 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE; 2135 arcmsr_drain_donequeue(acb, flag_srb, error); 2136 throttling++; 2137 if(throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) { 2138 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING); 2139 throttling = 0; 2140 } 2141 } while(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR); 2142 } 2143 /* 2144 ********************************************************************** 2145 ** 2146 ********************************************************************** 2147 */ 2148 static uint16_t arcmsr_get_doneq_index(struct HBD_MessageUnit0 *phbdmu) 2149 { 2150 uint16_t doneq_index, index_stripped; 2151 2152 doneq_index = phbdmu->doneq_index; 2153 if (doneq_index & 0x4000) { 2154 index_stripped = doneq_index & 0xFF; 2155 index_stripped += 1; 2156 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 2157 phbdmu->doneq_index = index_stripped ? 2158 (index_stripped | 0x4000) : index_stripped; 2159 } else { 2160 index_stripped = doneq_index; 2161 index_stripped += 1; 2162 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 2163 phbdmu->doneq_index = index_stripped ? 2164 index_stripped : (index_stripped | 0x4000); 2165 } 2166 return (phbdmu->doneq_index); 2167 } 2168 /* 2169 ************************************************************************** 2170 ************************************************************************** 2171 */ 2172 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb) 2173 { 2174 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 2175 u_int32_t outbound_write_pointer; 2176 u_int32_t addressLow; 2177 uint16_t doneq_index; 2178 u_int16_t error; 2179 /* 2180 ***************************************************************************** 2181 ** areca cdb command done 2182 ***************************************************************************** 2183 */ 2184 if((CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause) & 2185 ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT) == 0) 2186 return; 2187 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 2188 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2189 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 2190 doneq_index = phbdmu->doneq_index; 2191 while ((doneq_index & 0xFF) != (outbound_write_pointer & 0xFF)) { 2192 doneq_index = arcmsr_get_doneq_index(phbdmu); 2193 addressLow = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow; 2194 error = (addressLow & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 2195 arcmsr_drain_donequeue(acb, addressLow, error); /*Check if command done with no error */ 2196 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index); 2197 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 2198 } 2199 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_interrupt_cause, ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR); 2200 CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause); /*Dummy ioread32 to force pci flush */ 2201 } 2202 /* 2203 ************************************************************************** 2204 ************************************************************************** 2205 */ 2206 static void arcmsr_hbe_postqueue_isr(struct AdapterControlBlock *acb) 2207 { 2208 u_int16_t error; 2209 uint32_t doneq_index; 2210 uint16_t cmdSMID; 2211 2212 /* 2213 ***************************************************************************** 2214 ** areca cdb command done 2215 ***************************************************************************** 2216 */ 2217 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2218 doneq_index = acb->doneq_index; 2219 while ((CHIP_REG_READ32(HBE_MessageUnit, 0, reply_post_producer_index) & 0xFFFF) != doneq_index) { 2220 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID; 2221 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 2222 arcmsr_drain_donequeue(acb, (u_int32_t)cmdSMID, error); 2223 doneq_index++; 2224 if (doneq_index >= acb->completionQ_entry) 2225 doneq_index = 0; 2226 } 2227 acb->doneq_index = doneq_index; 2228 CHIP_REG_WRITE32(HBE_MessageUnit, 0, reply_post_consumer_index, doneq_index); 2229 } 2230 2231 static void arcmsr_hbf_postqueue_isr(struct AdapterControlBlock *acb) 2232 { 2233 uint16_t error; 2234 uint32_t doneq_index; 2235 uint16_t cmdSMID; 2236 2237 /* 2238 ***************************************************************************** 2239 ** areca cdb command done 2240 ***************************************************************************** 2241 */ 2242 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2243 doneq_index = acb->doneq_index; 2244 while (1) { 2245 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID; 2246 if (cmdSMID == 0xffff) 2247 break; 2248 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 2249 arcmsr_drain_donequeue(acb, (u_int32_t)cmdSMID, error); 2250 acb->pCompletionQ[doneq_index].cmdSMID = 0xffff; 2251 doneq_index++; 2252 if (doneq_index >= acb->completionQ_entry) 2253 doneq_index = 0; 2254 } 2255 acb->doneq_index = doneq_index; 2256 CHIP_REG_WRITE32(HBF_MessageUnit, 0, reply_post_consumer_index, doneq_index); 2257 } 2258 2259 /* 2260 ********************************************************************** 2261 ********************************************************************** 2262 */ 2263 static void arcmsr_handle_hba_isr( struct AdapterControlBlock *acb) 2264 { 2265 u_int32_t outbound_intStatus; 2266 /* 2267 ********************************************* 2268 ** check outbound intstatus 2269 ********************************************* 2270 */ 2271 outbound_intStatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 2272 if(!outbound_intStatus) { 2273 /*it must be share irq*/ 2274 return; 2275 } 2276 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intStatus); /*clear interrupt*/ 2277 /* MU doorbell interrupts*/ 2278 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) { 2279 arcmsr_hba_doorbell_isr(acb); 2280 } 2281 /* MU post queue interrupts*/ 2282 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) { 2283 arcmsr_hba_postqueue_isr(acb); 2284 } 2285 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { 2286 arcmsr_hba_message_isr(acb); 2287 } 2288 } 2289 /* 2290 ********************************************************************** 2291 ********************************************************************** 2292 */ 2293 static void arcmsr_handle_hbb_isr( struct AdapterControlBlock *acb) 2294 { 2295 u_int32_t outbound_doorbell; 2296 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 2297 /* 2298 ********************************************* 2299 ** check outbound intstatus 2300 ********************************************* 2301 */ 2302 outbound_doorbell = READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & acb->outbound_int_enable; 2303 if(!outbound_doorbell) { 2304 /*it must be share irq*/ 2305 return; 2306 } 2307 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ~outbound_doorbell); /* clear doorbell interrupt */ 2308 READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell); 2309 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 2310 /* MU ioctl transfer doorbell interrupts*/ 2311 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) { 2312 arcmsr_iop2drv_data_wrote_handle(acb); 2313 } 2314 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) { 2315 arcmsr_iop2drv_data_read_handle(acb); 2316 } 2317 /* MU post queue interrupts*/ 2318 if(outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) { 2319 arcmsr_hbb_postqueue_isr(acb); 2320 } 2321 if(outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) { 2322 arcmsr_hbb_message_isr(acb); 2323 } 2324 } 2325 /* 2326 ********************************************************************** 2327 ********************************************************************** 2328 */ 2329 static void arcmsr_handle_hbc_isr( struct AdapterControlBlock *acb) 2330 { 2331 u_int32_t host_interrupt_status; 2332 /* 2333 ********************************************* 2334 ** check outbound intstatus 2335 ********************************************* 2336 */ 2337 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & 2338 (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | 2339 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR); 2340 if(!host_interrupt_status) { 2341 /*it must be share irq*/ 2342 return; 2343 } 2344 do { 2345 /* MU doorbell interrupts*/ 2346 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) { 2347 arcmsr_hbc_doorbell_isr(acb); 2348 } 2349 /* MU post queue interrupts*/ 2350 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) { 2351 arcmsr_hbc_postqueue_isr(acb); 2352 } 2353 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status); 2354 } while (host_interrupt_status & (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR)); 2355 } 2356 /* 2357 ********************************************************************** 2358 ********************************************************************** 2359 */ 2360 static void arcmsr_handle_hbd_isr( struct AdapterControlBlock *acb) 2361 { 2362 u_int32_t host_interrupt_status; 2363 u_int32_t intmask_org; 2364 /* 2365 ********************************************* 2366 ** check outbound intstatus 2367 ********************************************* 2368 */ 2369 host_interrupt_status = CHIP_REG_READ32(HBD_MessageUnit, 0, host_int_status) & acb->outbound_int_enable; 2370 if(!(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_INT)) { 2371 /*it must be share irq*/ 2372 return; 2373 } 2374 /* disable outbound interrupt */ 2375 intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable) ; /* disable outbound message0 int */ 2376 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE); 2377 /* MU doorbell interrupts*/ 2378 if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT) { 2379 arcmsr_hbd_doorbell_isr(acb); 2380 } 2381 /* MU post queue interrupts*/ 2382 if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT) { 2383 arcmsr_hbd_postqueue_isr(acb); 2384 } 2385 /* enable all outbound interrupt */ 2386 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | ARCMSR_HBDMU_ALL_INT_ENABLE); 2387 // CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); 2388 } 2389 /* 2390 ********************************************************************** 2391 ********************************************************************** 2392 */ 2393 static void arcmsr_handle_hbe_isr( struct AdapterControlBlock *acb) 2394 { 2395 u_int32_t host_interrupt_status; 2396 /* 2397 ********************************************* 2398 ** check outbound intstatus 2399 ********************************************* 2400 */ 2401 host_interrupt_status = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_status) & 2402 (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | 2403 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR); 2404 if(!host_interrupt_status) { 2405 /*it must be share irq*/ 2406 return; 2407 } 2408 do { 2409 /* MU doorbell interrupts*/ 2410 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) { 2411 arcmsr_hbe_doorbell_isr(acb); 2412 } 2413 /* MU post queue interrupts*/ 2414 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) { 2415 arcmsr_hbe_postqueue_isr(acb); 2416 } 2417 host_interrupt_status = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_status); 2418 } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR)); 2419 } 2420 2421 static void arcmsr_handle_hbf_isr( struct AdapterControlBlock *acb) 2422 { 2423 u_int32_t host_interrupt_status; 2424 /* 2425 ********************************************* 2426 ** check outbound intstatus 2427 ********************************************* 2428 */ 2429 host_interrupt_status = CHIP_REG_READ32(HBF_MessageUnit, 0, host_int_status) & 2430 (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | 2431 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR); 2432 if(!host_interrupt_status) { 2433 /*it must be share irq*/ 2434 return; 2435 } 2436 do { 2437 /* MU doorbell interrupts*/ 2438 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) { 2439 arcmsr_hbf_doorbell_isr(acb); 2440 } 2441 /* MU post queue interrupts*/ 2442 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) { 2443 arcmsr_hbf_postqueue_isr(acb); 2444 } 2445 host_interrupt_status = CHIP_REG_READ32(HBF_MessageUnit, 0, host_int_status); 2446 } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR)); 2447 } 2448 /* 2449 ****************************************************************************** 2450 ****************************************************************************** 2451 */ 2452 static void arcmsr_interrupt(struct AdapterControlBlock *acb) 2453 { 2454 switch (acb->adapter_type) { 2455 case ACB_ADAPTER_TYPE_A: 2456 arcmsr_handle_hba_isr(acb); 2457 break; 2458 case ACB_ADAPTER_TYPE_B: 2459 arcmsr_handle_hbb_isr(acb); 2460 break; 2461 case ACB_ADAPTER_TYPE_C: 2462 arcmsr_handle_hbc_isr(acb); 2463 break; 2464 case ACB_ADAPTER_TYPE_D: 2465 arcmsr_handle_hbd_isr(acb); 2466 break; 2467 case ACB_ADAPTER_TYPE_E: 2468 arcmsr_handle_hbe_isr(acb); 2469 break; 2470 case ACB_ADAPTER_TYPE_F: 2471 arcmsr_handle_hbf_isr(acb); 2472 break; 2473 default: 2474 printf("arcmsr%d: interrupt service," 2475 " unknown adapter type =%d\n", acb->pci_unit, acb->adapter_type); 2476 break; 2477 } 2478 } 2479 /* 2480 ********************************************************************** 2481 ********************************************************************** 2482 */ 2483 static void arcmsr_intr_handler(void *arg) 2484 { 2485 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg; 2486 2487 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 2488 arcmsr_interrupt(acb); 2489 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 2490 } 2491 /* 2492 ****************************************************************************** 2493 ****************************************************************************** 2494 */ 2495 static void arcmsr_polling_devmap(void *arg) 2496 { 2497 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg; 2498 switch (acb->adapter_type) { 2499 case ACB_ADAPTER_TYPE_A: 2500 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2501 break; 2502 2503 case ACB_ADAPTER_TYPE_B: { 2504 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 2505 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG); 2506 } 2507 break; 2508 2509 case ACB_ADAPTER_TYPE_C: 2510 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2511 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 2512 break; 2513 2514 case ACB_ADAPTER_TYPE_D: 2515 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2516 break; 2517 2518 case ACB_ADAPTER_TYPE_E: 2519 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2520 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 2521 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 2522 break; 2523 2524 case ACB_ADAPTER_TYPE_F: { 2525 u_int32_t outMsg1 = CHIP_REG_READ32(HBF_MessageUnit, 0, outbound_msgaddr1); 2526 if (!(outMsg1 & ARCMSR_HBFMU_MESSAGE_FIRMWARE_OK) || 2527 (outMsg1 & ARCMSR_HBFMU_MESSAGE_NO_VOLUME_CHANGE)) 2528 goto nxt6s; 2529 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2530 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 2531 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 2532 break; 2533 } 2534 } 2535 nxt6s: 2536 if((acb->acb_flags & ACB_F_SCSISTOPADAPTER) == 0) 2537 { 2538 callout_reset(&acb->devmap_callout, 5 * hz, arcmsr_polling_devmap, acb); /* polling per 5 seconds */ 2539 } 2540 } 2541 2542 /* 2543 ******************************************************************************* 2544 ** 2545 ******************************************************************************* 2546 */ 2547 static void arcmsr_iop_parking(struct AdapterControlBlock *acb) 2548 { 2549 u_int32_t intmask_org; 2550 2551 if(acb != NULL) { 2552 /* stop adapter background rebuild */ 2553 if(acb->acb_flags & ACB_F_MSG_START_BGRB) { 2554 intmask_org = arcmsr_disable_allintr(acb); 2555 arcmsr_stop_adapter_bgrb(acb); 2556 arcmsr_flush_adapter_cache(acb); 2557 arcmsr_enable_allintr(acb, intmask_org); 2558 } 2559 } 2560 } 2561 /* 2562 *********************************************************************** 2563 ** 2564 ************************************************************************ 2565 */ 2566 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg) 2567 { 2568 struct CMD_MESSAGE_FIELD *pcmdmessagefld; 2569 u_int32_t retvalue = EINVAL; 2570 2571 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) arg; 2572 if(memcmp(pcmdmessagefld->cmdmessage.Signature, "ARCMSR", 6)!=0) { 2573 return retvalue; 2574 } 2575 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2576 switch(ioctl_cmd) { 2577 case ARCMSR_MESSAGE_READ_RQBUFFER: { 2578 u_int8_t *pQbuffer; 2579 u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer; 2580 u_int32_t allxfer_len=0; 2581 2582 while((acb->rqbuf_firstindex != acb->rqbuf_lastindex) 2583 && (allxfer_len < 1031)) { 2584 /*copy READ QBUFFER to srb*/ 2585 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex]; 2586 *ptmpQbuffer = *pQbuffer; 2587 acb->rqbuf_firstindex++; 2588 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 2589 /*if last index number set it to 0 */ 2590 ptmpQbuffer++; 2591 allxfer_len++; 2592 } 2593 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2594 struct QBUFFER *prbuffer; 2595 2596 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2597 prbuffer = arcmsr_get_iop_rqbuffer(acb); 2598 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 2599 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 2600 } 2601 pcmdmessagefld->cmdmessage.Length = allxfer_len; 2602 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2603 retvalue = ARCMSR_MESSAGE_SUCCESS; 2604 } 2605 break; 2606 case ARCMSR_MESSAGE_WRITE_WQBUFFER: { 2607 u_int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex; 2608 u_int8_t *pQbuffer; 2609 u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer; 2610 2611 user_len = pcmdmessagefld->cmdmessage.Length; 2612 /*check if data xfer length of this request will overflow my array qbuffer */ 2613 wqbuf_lastindex = acb->wqbuf_lastindex; 2614 wqbuf_firstindex = acb->wqbuf_firstindex; 2615 if(wqbuf_lastindex != wqbuf_firstindex) { 2616 arcmsr_Write_data_2iop_wqbuffer(acb); 2617 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2618 } else { 2619 my_empty_len = (wqbuf_firstindex - wqbuf_lastindex - 1) & 2620 (ARCMSR_MAX_QBUFFER - 1); 2621 if(my_empty_len >= user_len) { 2622 while(user_len > 0) { 2623 /*copy srb data to wqbuffer*/ 2624 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex]; 2625 *pQbuffer = *ptmpuserbuffer; 2626 acb->wqbuf_lastindex++; 2627 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 2628 /*if last index number set it to 0 */ 2629 ptmpuserbuffer++; 2630 user_len--; 2631 } 2632 /*post fist Qbuffer*/ 2633 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) { 2634 acb->acb_flags &= ~ACB_F_MESSAGE_WQBUFFER_CLEARED; 2635 arcmsr_Write_data_2iop_wqbuffer(acb); 2636 } 2637 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2638 } else { 2639 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2640 } 2641 } 2642 retvalue = ARCMSR_MESSAGE_SUCCESS; 2643 } 2644 break; 2645 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: { 2646 u_int8_t *pQbuffer = acb->rqbuffer; 2647 2648 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2649 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2650 arcmsr_iop_message_read(acb); 2651 /*signature, let IOP know data has been readed */ 2652 } 2653 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 2654 acb->rqbuf_firstindex = 0; 2655 acb->rqbuf_lastindex = 0; 2656 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2657 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2658 retvalue = ARCMSR_MESSAGE_SUCCESS; 2659 } 2660 break; 2661 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: 2662 { 2663 u_int8_t *pQbuffer = acb->wqbuffer; 2664 2665 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2666 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2667 arcmsr_iop_message_read(acb); 2668 /*signature, let IOP know data has been readed */ 2669 } 2670 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ); 2671 acb->wqbuf_firstindex = 0; 2672 acb->wqbuf_lastindex = 0; 2673 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2674 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2675 retvalue = ARCMSR_MESSAGE_SUCCESS; 2676 } 2677 break; 2678 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: { 2679 u_int8_t *pQbuffer; 2680 2681 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2682 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2683 arcmsr_iop_message_read(acb); 2684 /*signature, let IOP know data has been readed */ 2685 } 2686 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED 2687 |ACB_F_MESSAGE_RQBUFFER_CLEARED 2688 |ACB_F_MESSAGE_WQBUFFER_READ); 2689 acb->rqbuf_firstindex = 0; 2690 acb->rqbuf_lastindex = 0; 2691 acb->wqbuf_firstindex = 0; 2692 acb->wqbuf_lastindex = 0; 2693 pQbuffer = acb->rqbuffer; 2694 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 2695 pQbuffer = acb->wqbuffer; 2696 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 2697 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2698 retvalue = ARCMSR_MESSAGE_SUCCESS; 2699 } 2700 break; 2701 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: { 2702 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F; 2703 retvalue = ARCMSR_MESSAGE_SUCCESS; 2704 } 2705 break; 2706 case ARCMSR_MESSAGE_SAY_HELLO: { 2707 u_int8_t *hello_string = "Hello! I am ARCMSR"; 2708 u_int8_t *puserbuffer = (u_int8_t *)pcmdmessagefld->messagedatabuffer; 2709 2710 if(memcpy(puserbuffer, hello_string, (int16_t)strlen(hello_string))) { 2711 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2712 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2713 return ENOIOCTL; 2714 } 2715 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2716 retvalue = ARCMSR_MESSAGE_SUCCESS; 2717 } 2718 break; 2719 case ARCMSR_MESSAGE_SAY_GOODBYE: { 2720 arcmsr_iop_parking(acb); 2721 retvalue = ARCMSR_MESSAGE_SUCCESS; 2722 } 2723 break; 2724 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: { 2725 arcmsr_flush_adapter_cache(acb); 2726 retvalue = ARCMSR_MESSAGE_SUCCESS; 2727 } 2728 break; 2729 } 2730 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2731 return (retvalue); 2732 } 2733 /* 2734 ************************************************************************** 2735 ************************************************************************** 2736 */ 2737 static void arcmsr_free_srb(struct CommandControlBlock *srb) 2738 { 2739 struct AdapterControlBlock *acb; 2740 2741 acb = srb->acb; 2742 ARCMSR_LOCK_ACQUIRE(&acb->srb_lock); 2743 srb->srb_state = ARCMSR_SRB_DONE; 2744 srb->srb_flags = 0; 2745 acb->srbworkingQ[acb->workingsrb_doneindex] = srb; 2746 acb->workingsrb_doneindex++; 2747 acb->workingsrb_doneindex %= ARCMSR_MAX_FREESRB_NUM; 2748 ARCMSR_LOCK_RELEASE(&acb->srb_lock); 2749 } 2750 /* 2751 ************************************************************************** 2752 ************************************************************************** 2753 */ 2754 static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb) 2755 { 2756 struct CommandControlBlock *srb = NULL; 2757 u_int32_t workingsrb_startindex, workingsrb_doneindex; 2758 2759 ARCMSR_LOCK_ACQUIRE(&acb->srb_lock); 2760 workingsrb_doneindex = acb->workingsrb_doneindex; 2761 workingsrb_startindex = acb->workingsrb_startindex; 2762 srb = acb->srbworkingQ[workingsrb_startindex]; 2763 workingsrb_startindex++; 2764 workingsrb_startindex %= ARCMSR_MAX_FREESRB_NUM; 2765 if(workingsrb_doneindex != workingsrb_startindex) { 2766 acb->workingsrb_startindex = workingsrb_startindex; 2767 } else { 2768 srb = NULL; 2769 } 2770 ARCMSR_LOCK_RELEASE(&acb->srb_lock); 2771 return(srb); 2772 } 2773 /* 2774 ************************************************************************** 2775 ************************************************************************** 2776 */ 2777 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb) 2778 { 2779 struct CMD_MESSAGE_FIELD *pcmdmessagefld; 2780 int retvalue = 0, transfer_len = 0; 2781 char *buffer; 2782 uint8_t *ptr = scsiio_cdb_ptr(&pccb->csio); 2783 u_int32_t controlcode = (u_int32_t ) ptr[5] << 24 | 2784 (u_int32_t ) ptr[6] << 16 | 2785 (u_int32_t ) ptr[7] << 8 | 2786 (u_int32_t ) ptr[8]; 2787 /* 4 bytes: Areca io control code */ 2788 if ((pccb->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_VADDR) { 2789 buffer = pccb->csio.data_ptr; 2790 transfer_len = pccb->csio.dxfer_len; 2791 } else { 2792 retvalue = ARCMSR_MESSAGE_FAIL; 2793 goto message_out; 2794 } 2795 if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) { 2796 retvalue = ARCMSR_MESSAGE_FAIL; 2797 goto message_out; 2798 } 2799 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) buffer; 2800 switch(controlcode) { 2801 case ARCMSR_MESSAGE_READ_RQBUFFER: { 2802 u_int8_t *pQbuffer; 2803 u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer; 2804 int32_t allxfer_len = 0; 2805 2806 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2807 while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex) 2808 && (allxfer_len < 1031)) { 2809 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex]; 2810 *ptmpQbuffer = *pQbuffer; 2811 acb->rqbuf_firstindex++; 2812 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 2813 ptmpQbuffer++; 2814 allxfer_len++; 2815 } 2816 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2817 struct QBUFFER *prbuffer; 2818 2819 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2820 prbuffer = arcmsr_get_iop_rqbuffer(acb); 2821 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 2822 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 2823 } 2824 pcmdmessagefld->cmdmessage.Length = allxfer_len; 2825 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2826 retvalue = ARCMSR_MESSAGE_SUCCESS; 2827 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2828 } 2829 break; 2830 case ARCMSR_MESSAGE_WRITE_WQBUFFER: { 2831 int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex; 2832 u_int8_t *pQbuffer; 2833 u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer; 2834 2835 user_len = pcmdmessagefld->cmdmessage.Length; 2836 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2837 wqbuf_lastindex = acb->wqbuf_lastindex; 2838 wqbuf_firstindex = acb->wqbuf_firstindex; 2839 if (wqbuf_lastindex != wqbuf_firstindex) { 2840 arcmsr_Write_data_2iop_wqbuffer(acb); 2841 /* has error report sensedata */ 2842 if(pccb->csio.sense_len) { 2843 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); 2844 /* Valid,ErrorCode */ 2845 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05; 2846 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */ 2847 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A; 2848 /* AdditionalSenseLength */ 2849 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20; 2850 /* AdditionalSenseCode */ 2851 } 2852 retvalue = ARCMSR_MESSAGE_FAIL; 2853 } else { 2854 my_empty_len = (wqbuf_firstindex-wqbuf_lastindex - 1) 2855 &(ARCMSR_MAX_QBUFFER - 1); 2856 if (my_empty_len >= user_len) { 2857 while (user_len > 0) { 2858 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex]; 2859 *pQbuffer = *ptmpuserbuffer; 2860 acb->wqbuf_lastindex++; 2861 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 2862 ptmpuserbuffer++; 2863 user_len--; 2864 } 2865 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) { 2866 acb->acb_flags &= 2867 ~ACB_F_MESSAGE_WQBUFFER_CLEARED; 2868 arcmsr_Write_data_2iop_wqbuffer(acb); 2869 } 2870 } else { 2871 /* has error report sensedata */ 2872 if(pccb->csio.sense_len) { 2873 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); 2874 /* Valid,ErrorCode */ 2875 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05; 2876 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */ 2877 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A; 2878 /* AdditionalSenseLength */ 2879 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20; 2880 /* AdditionalSenseCode */ 2881 } 2882 retvalue = ARCMSR_MESSAGE_FAIL; 2883 } 2884 } 2885 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2886 } 2887 break; 2888 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: { 2889 u_int8_t *pQbuffer = acb->rqbuffer; 2890 2891 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2892 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2893 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2894 arcmsr_iop_message_read(acb); 2895 } 2896 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 2897 acb->rqbuf_firstindex = 0; 2898 acb->rqbuf_lastindex = 0; 2899 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2900 pcmdmessagefld->cmdmessage.ReturnCode = 2901 ARCMSR_MESSAGE_RETURNCODE_OK; 2902 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2903 } 2904 break; 2905 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: { 2906 u_int8_t *pQbuffer = acb->wqbuffer; 2907 2908 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2909 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2910 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2911 arcmsr_iop_message_read(acb); 2912 } 2913 acb->acb_flags |= 2914 (ACB_F_MESSAGE_WQBUFFER_CLEARED | 2915 ACB_F_MESSAGE_WQBUFFER_READ); 2916 acb->wqbuf_firstindex = 0; 2917 acb->wqbuf_lastindex = 0; 2918 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2919 pcmdmessagefld->cmdmessage.ReturnCode = 2920 ARCMSR_MESSAGE_RETURNCODE_OK; 2921 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2922 } 2923 break; 2924 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: { 2925 u_int8_t *pQbuffer; 2926 2927 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2928 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2929 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2930 arcmsr_iop_message_read(acb); 2931 } 2932 acb->acb_flags |= 2933 (ACB_F_MESSAGE_WQBUFFER_CLEARED 2934 | ACB_F_MESSAGE_RQBUFFER_CLEARED 2935 | ACB_F_MESSAGE_WQBUFFER_READ); 2936 acb->rqbuf_firstindex = 0; 2937 acb->rqbuf_lastindex = 0; 2938 acb->wqbuf_firstindex = 0; 2939 acb->wqbuf_lastindex = 0; 2940 pQbuffer = acb->rqbuffer; 2941 memset(pQbuffer, 0, sizeof (struct QBUFFER)); 2942 pQbuffer = acb->wqbuffer; 2943 memset(pQbuffer, 0, sizeof (struct QBUFFER)); 2944 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2945 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2946 } 2947 break; 2948 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: { 2949 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F; 2950 } 2951 break; 2952 case ARCMSR_MESSAGE_SAY_HELLO: { 2953 int8_t *hello_string = "Hello! I am ARCMSR"; 2954 2955 memcpy(pcmdmessagefld->messagedatabuffer, hello_string 2956 , (int16_t)strlen(hello_string)); 2957 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2958 } 2959 break; 2960 case ARCMSR_MESSAGE_SAY_GOODBYE: 2961 arcmsr_iop_parking(acb); 2962 break; 2963 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: 2964 arcmsr_flush_adapter_cache(acb); 2965 break; 2966 default: 2967 retvalue = ARCMSR_MESSAGE_FAIL; 2968 } 2969 message_out: 2970 return (retvalue); 2971 } 2972 /* 2973 ********************************************************************* 2974 ********************************************************************* 2975 */ 2976 static void arcmsr_execute_srb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 2977 { 2978 struct CommandControlBlock *srb = (struct CommandControlBlock *)arg; 2979 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)srb->acb; 2980 union ccb *pccb; 2981 int target, lun; 2982 2983 pccb = srb->pccb; 2984 target = pccb->ccb_h.target_id; 2985 lun = pccb->ccb_h.target_lun; 2986 acb->pktRequestCount++; 2987 if(error != 0) { 2988 if(error != EFBIG) { 2989 printf("arcmsr%d: unexpected error %x" 2990 " returned from 'bus_dmamap_load' \n" 2991 , acb->pci_unit, error); 2992 } 2993 if((pccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_INPROG) { 2994 pccb->ccb_h.status |= CAM_REQ_TOO_BIG; 2995 } 2996 arcmsr_srb_complete(srb, 0); 2997 return; 2998 } 2999 if(nseg > ARCMSR_MAX_SG_ENTRIES) { 3000 pccb->ccb_h.status |= CAM_REQ_TOO_BIG; 3001 arcmsr_srb_complete(srb, 0); 3002 return; 3003 } 3004 if(acb->acb_flags & ACB_F_BUS_RESET) { 3005 printf("arcmsr%d: bus reset and return busy \n", acb->pci_unit); 3006 pccb->ccb_h.status |= CAM_SCSI_BUS_RESET; 3007 arcmsr_srb_complete(srb, 0); 3008 return; 3009 } 3010 if(acb->devstate[target][lun] == ARECA_RAID_GONE) { 3011 u_int8_t block_cmd, cmd; 3012 3013 cmd = scsiio_cdb_ptr(&pccb->csio)[0]; 3014 block_cmd = cmd & 0x0f; 3015 if(block_cmd == 0x08 || block_cmd == 0x0a) { 3016 printf("arcmsr%d:block 'read/write' command " 3017 "with gone raid volume Cmd=0x%2x, TargetId=%d, Lun=%d \n" 3018 , acb->pci_unit, cmd, target, lun); 3019 pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 3020 arcmsr_srb_complete(srb, 0); 3021 return; 3022 } 3023 } 3024 if((pccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_INPROG) { 3025 if(nseg != 0) { 3026 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap); 3027 } 3028 arcmsr_srb_complete(srb, 0); 3029 return; 3030 } 3031 if(acb->srboutstandingcount >= acb->maxOutstanding) { 3032 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) == 0) 3033 { 3034 xpt_freeze_simq(acb->psim, 1); 3035 acb->acb_flags |= ACB_F_CAM_DEV_QFRZN; 3036 } 3037 pccb->ccb_h.status &= ~CAM_SIM_QUEUED; 3038 pccb->ccb_h.status |= CAM_REQUEUE_REQ; 3039 arcmsr_srb_complete(srb, 0); 3040 return; 3041 } 3042 pccb->ccb_h.status |= CAM_SIM_QUEUED; 3043 arcmsr_build_srb(srb, dm_segs, nseg); 3044 arcmsr_post_srb(acb, srb); 3045 if (pccb->ccb_h.timeout != CAM_TIME_INFINITY) 3046 { 3047 arcmsr_callout_init(&srb->ccb_callout); 3048 callout_reset_sbt(&srb->ccb_callout, SBT_1MS * 3049 (pccb->ccb_h.timeout + (ARCMSR_TIMEOUT_DELAY * 1000)), 0, 3050 arcmsr_srb_timeout, srb, 0); 3051 srb->srb_flags |= SRB_FLAG_TIMER_START; 3052 } 3053 } 3054 /* 3055 ***************************************************************************************** 3056 ***************************************************************************************** 3057 */ 3058 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb) 3059 { 3060 struct CommandControlBlock *srb; 3061 struct AdapterControlBlock *acb = (struct AdapterControlBlock *) abortccb->ccb_h.arcmsr_ccbacb_ptr; 3062 u_int32_t intmask_org; 3063 int i = 0; 3064 3065 acb->num_aborts++; 3066 /* 3067 *************************************************************************** 3068 ** It is the upper layer do abort command this lock just prior to calling us. 3069 ** First determine if we currently own this command. 3070 ** Start by searching the device queue. If not found 3071 ** at all, and the system wanted us to just abort the 3072 ** command return success. 3073 *************************************************************************** 3074 */ 3075 if(acb->srboutstandingcount != 0) { 3076 /* disable all outbound interrupt */ 3077 intmask_org = arcmsr_disable_allintr(acb); 3078 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 3079 srb = acb->psrb_pool[i]; 3080 if(srb->srb_state == ARCMSR_SRB_START) { 3081 if(srb->pccb == abortccb) { 3082 srb->srb_state = ARCMSR_SRB_ABORTED; 3083 printf("arcmsr%d:scsi id=%d lun=%jx abort srb '%p'" 3084 "outstanding command \n" 3085 , acb->pci_unit, abortccb->ccb_h.target_id 3086 , (uintmax_t)abortccb->ccb_h.target_lun, srb); 3087 arcmsr_polling_srbdone(acb, srb); 3088 /* enable outbound Post Queue, outbound doorbell Interrupt */ 3089 arcmsr_enable_allintr(acb, intmask_org); 3090 return (TRUE); 3091 } 3092 } 3093 } 3094 /* enable outbound Post Queue, outbound doorbell Interrupt */ 3095 arcmsr_enable_allintr(acb, intmask_org); 3096 } 3097 return(FALSE); 3098 } 3099 /* 3100 **************************************************************************** 3101 **************************************************************************** 3102 */ 3103 static void arcmsr_bus_reset(struct AdapterControlBlock *acb) 3104 { 3105 int retry = 0; 3106 3107 acb->num_resets++; 3108 acb->acb_flags |= ACB_F_BUS_RESET; 3109 while(acb->srboutstandingcount != 0 && retry < 400) { 3110 arcmsr_interrupt(acb); 3111 UDELAY(25000); 3112 retry++; 3113 } 3114 arcmsr_iop_reset(acb); 3115 acb->acb_flags &= ~ACB_F_BUS_RESET; 3116 } 3117 /* 3118 ************************************************************************** 3119 ************************************************************************** 3120 */ 3121 static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb, 3122 union ccb *pccb) 3123 { 3124 if (pccb->ccb_h.target_lun) { 3125 pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 3126 xpt_done(pccb); 3127 return; 3128 } 3129 pccb->ccb_h.status |= CAM_REQ_CMP; 3130 switch (scsiio_cdb_ptr(&pccb->csio)[0]) { 3131 case INQUIRY: { 3132 unsigned char inqdata[36]; 3133 char *buffer = pccb->csio.data_ptr; 3134 3135 inqdata[0] = T_PROCESSOR; /* Periph Qualifier & Periph Dev Type */ 3136 inqdata[1] = 0; /* rem media bit & Dev Type Modifier */ 3137 inqdata[2] = 0; /* ISO, ECMA, & ANSI versions */ 3138 inqdata[3] = 0; 3139 inqdata[4] = 31; /* length of additional data */ 3140 inqdata[5] = 0; 3141 inqdata[6] = 0; 3142 inqdata[7] = 0; 3143 strncpy(&inqdata[8], "Areca ", 8); /* Vendor Identification */ 3144 strncpy(&inqdata[16], "RAID controller ", 16); /* Product Identification */ 3145 strncpy(&inqdata[32], "R001", 4); /* Product Revision */ 3146 memcpy(buffer, inqdata, sizeof(inqdata)); 3147 xpt_done(pccb); 3148 } 3149 break; 3150 case WRITE_BUFFER: 3151 case READ_BUFFER: { 3152 if (arcmsr_iop_message_xfer(acb, pccb)) { 3153 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 3154 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 3155 } 3156 xpt_done(pccb); 3157 } 3158 break; 3159 default: 3160 xpt_done(pccb); 3161 } 3162 } 3163 /* 3164 ********************************************************************* 3165 ********************************************************************* 3166 */ 3167 static void arcmsr_action(struct cam_sim *psim, union ccb *pccb) 3168 { 3169 struct AdapterControlBlock *acb; 3170 3171 acb = (struct AdapterControlBlock *) cam_sim_softc(psim); 3172 if(acb == NULL) { 3173 pccb->ccb_h.status |= CAM_REQ_INVALID; 3174 xpt_done(pccb); 3175 return; 3176 } 3177 switch (pccb->ccb_h.func_code) { 3178 case XPT_SCSI_IO: { 3179 struct CommandControlBlock *srb; 3180 int target = pccb->ccb_h.target_id; 3181 int error; 3182 3183 if (pccb->ccb_h.flags & CAM_CDB_PHYS) { 3184 pccb->ccb_h.status = CAM_REQ_INVALID; 3185 xpt_done(pccb); 3186 return; 3187 } 3188 3189 if(target == 16) { 3190 /* virtual device for iop message transfer */ 3191 arcmsr_handle_virtual_command(acb, pccb); 3192 return; 3193 } 3194 if((srb = arcmsr_get_freesrb(acb)) == NULL) { 3195 pccb->ccb_h.status |= CAM_RESRC_UNAVAIL; 3196 xpt_done(pccb); 3197 return; 3198 } 3199 pccb->ccb_h.arcmsr_ccbsrb_ptr = srb; 3200 pccb->ccb_h.arcmsr_ccbacb_ptr = acb; 3201 srb->pccb = pccb; 3202 error = bus_dmamap_load_ccb(acb->dm_segs_dmat 3203 , srb->dm_segs_dmamap 3204 , pccb 3205 , arcmsr_execute_srb, srb, /*flags*/0); 3206 if(error == EINPROGRESS) { 3207 xpt_freeze_simq(acb->psim, 1); 3208 pccb->ccb_h.status |= CAM_RELEASE_SIMQ; 3209 } 3210 break; 3211 } 3212 case XPT_PATH_INQ: { 3213 struct ccb_pathinq *cpi = &pccb->cpi; 3214 3215 cpi->version_num = 1; 3216 cpi->hba_inquiry = PI_SDTR_ABLE | PI_TAG_ABLE; 3217 cpi->target_sprt = 0; 3218 cpi->hba_misc = 0; 3219 cpi->hba_eng_cnt = 0; 3220 cpi->max_target = ARCMSR_MAX_TARGETID; /* 0-16 */ 3221 cpi->max_lun = ARCMSR_MAX_TARGETLUN; /* 0-7 */ 3222 cpi->initiator_id = ARCMSR_SCSI_INITIATOR_ID; /* 255 */ 3223 cpi->bus_id = cam_sim_bus(psim); 3224 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 3225 strlcpy(cpi->hba_vid, "ARCMSR", HBA_IDLEN); 3226 strlcpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN); 3227 cpi->unit_number = cam_sim_unit(psim); 3228 if(acb->adapter_bus_speed == ACB_BUS_SPEED_12G) 3229 cpi->base_transfer_speed = 1200000; 3230 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G) 3231 cpi->base_transfer_speed = 600000; 3232 else 3233 cpi->base_transfer_speed = 300000; 3234 if((acb->vendor_device_id == PCIDevVenIDARC1880) || 3235 (acb->vendor_device_id == PCIDevVenIDARC1884) || 3236 (acb->vendor_device_id == PCIDevVenIDARC1680) || 3237 (acb->vendor_device_id == PCIDevVenIDARC1214)) 3238 { 3239 cpi->transport = XPORT_SAS; 3240 cpi->transport_version = 0; 3241 cpi->protocol_version = SCSI_REV_SPC2; 3242 } 3243 else 3244 { 3245 cpi->transport = XPORT_SPI; 3246 cpi->transport_version = 2; 3247 cpi->protocol_version = SCSI_REV_2; 3248 } 3249 cpi->protocol = PROTO_SCSI; 3250 cpi->ccb_h.status |= CAM_REQ_CMP; 3251 xpt_done(pccb); 3252 break; 3253 } 3254 case XPT_ABORT: { 3255 union ccb *pabort_ccb; 3256 3257 pabort_ccb = pccb->cab.abort_ccb; 3258 switch (pabort_ccb->ccb_h.func_code) { 3259 case XPT_ACCEPT_TARGET_IO: 3260 case XPT_CONT_TARGET_IO: 3261 if(arcmsr_seek_cmd2abort(pabort_ccb)==TRUE) { 3262 pabort_ccb->ccb_h.status |= CAM_REQ_ABORTED; 3263 xpt_done(pabort_ccb); 3264 pccb->ccb_h.status |= CAM_REQ_CMP; 3265 } else { 3266 xpt_print_path(pabort_ccb->ccb_h.path); 3267 printf("Not found\n"); 3268 pccb->ccb_h.status |= CAM_PATH_INVALID; 3269 } 3270 break; 3271 case XPT_SCSI_IO: 3272 pccb->ccb_h.status |= CAM_UA_ABORT; 3273 break; 3274 default: 3275 pccb->ccb_h.status |= CAM_REQ_INVALID; 3276 break; 3277 } 3278 xpt_done(pccb); 3279 break; 3280 } 3281 case XPT_RESET_BUS: 3282 case XPT_RESET_DEV: { 3283 u_int32_t i; 3284 3285 arcmsr_bus_reset(acb); 3286 for (i=0; i < 500; i++) { 3287 DELAY(1000); 3288 } 3289 pccb->ccb_h.status |= CAM_REQ_CMP; 3290 xpt_done(pccb); 3291 break; 3292 } 3293 case XPT_TERM_IO: { 3294 pccb->ccb_h.status |= CAM_REQ_INVALID; 3295 xpt_done(pccb); 3296 break; 3297 } 3298 case XPT_GET_TRAN_SETTINGS: { 3299 struct ccb_trans_settings *cts; 3300 3301 if(pccb->ccb_h.target_id == 16) { 3302 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 3303 xpt_done(pccb); 3304 break; 3305 } 3306 cts = &pccb->cts; 3307 { 3308 struct ccb_trans_settings_scsi *scsi; 3309 struct ccb_trans_settings_spi *spi; 3310 struct ccb_trans_settings_sas *sas; 3311 3312 scsi = &cts->proto_specific.scsi; 3313 scsi->flags = CTS_SCSI_FLAGS_TAG_ENB; 3314 scsi->valid = CTS_SCSI_VALID_TQ; 3315 cts->protocol = PROTO_SCSI; 3316 3317 if((acb->vendor_device_id == PCIDevVenIDARC1880) || 3318 (acb->vendor_device_id == PCIDevVenIDARC1884) || 3319 (acb->vendor_device_id == PCIDevVenIDARC1680) || 3320 (acb->vendor_device_id == PCIDevVenIDARC1214)) 3321 { 3322 cts->protocol_version = SCSI_REV_SPC2; 3323 cts->transport_version = 0; 3324 cts->transport = XPORT_SAS; 3325 sas = &cts->xport_specific.sas; 3326 sas->valid = CTS_SAS_VALID_SPEED; 3327 if (acb->adapter_bus_speed == ACB_BUS_SPEED_12G) 3328 sas->bitrate = 1200000; 3329 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G) 3330 sas->bitrate = 600000; 3331 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_3G) 3332 sas->bitrate = 300000; 3333 } 3334 else 3335 { 3336 cts->protocol_version = SCSI_REV_2; 3337 cts->transport_version = 2; 3338 cts->transport = XPORT_SPI; 3339 spi = &cts->xport_specific.spi; 3340 spi->flags = CTS_SPI_FLAGS_DISC_ENB; 3341 if (acb->adapter_bus_speed == ACB_BUS_SPEED_6G) 3342 spi->sync_period = 1; 3343 else 3344 spi->sync_period = 2; 3345 spi->sync_offset = 32; 3346 spi->bus_width = MSG_EXT_WDTR_BUS_16_BIT; 3347 spi->valid = CTS_SPI_VALID_DISC 3348 | CTS_SPI_VALID_SYNC_RATE 3349 | CTS_SPI_VALID_SYNC_OFFSET 3350 | CTS_SPI_VALID_BUS_WIDTH; 3351 } 3352 } 3353 pccb->ccb_h.status |= CAM_REQ_CMP; 3354 xpt_done(pccb); 3355 break; 3356 } 3357 case XPT_SET_TRAN_SETTINGS: { 3358 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 3359 xpt_done(pccb); 3360 break; 3361 } 3362 case XPT_CALC_GEOMETRY: 3363 if(pccb->ccb_h.target_id == 16) { 3364 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 3365 xpt_done(pccb); 3366 break; 3367 } 3368 cam_calc_geometry(&pccb->ccg, 1); 3369 xpt_done(pccb); 3370 break; 3371 default: 3372 pccb->ccb_h.status |= CAM_REQ_INVALID; 3373 xpt_done(pccb); 3374 break; 3375 } 3376 } 3377 /* 3378 ********************************************************************** 3379 ********************************************************************** 3380 */ 3381 static void arcmsr_start_hba_bgrb(struct AdapterControlBlock *acb) 3382 { 3383 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3384 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3385 if(!arcmsr_hba_wait_msgint_ready(acb)) { 3386 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3387 } 3388 } 3389 /* 3390 ********************************************************************** 3391 ********************************************************************** 3392 */ 3393 static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb) 3394 { 3395 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3396 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3397 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_START_BGRB); 3398 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3399 printf( "arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3400 } 3401 } 3402 /* 3403 ********************************************************************** 3404 ********************************************************************** 3405 */ 3406 static void arcmsr_start_hbc_bgrb(struct AdapterControlBlock *acb) 3407 { 3408 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3409 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3410 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3411 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 3412 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3413 } 3414 } 3415 /* 3416 ********************************************************************** 3417 ********************************************************************** 3418 */ 3419 static void arcmsr_start_hbd_bgrb(struct AdapterControlBlock *acb) 3420 { 3421 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3422 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3423 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 3424 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3425 } 3426 } 3427 /* 3428 ********************************************************************** 3429 ********************************************************************** 3430 */ 3431 static void arcmsr_start_hbe_bgrb(struct AdapterControlBlock *acb) 3432 { 3433 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3434 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3435 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 3436 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 3437 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 3438 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3439 } 3440 } 3441 /* 3442 ********************************************************************** 3443 ********************************************************************** 3444 */ 3445 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb) 3446 { 3447 switch (acb->adapter_type) { 3448 case ACB_ADAPTER_TYPE_A: 3449 arcmsr_start_hba_bgrb(acb); 3450 break; 3451 case ACB_ADAPTER_TYPE_B: 3452 arcmsr_start_hbb_bgrb(acb); 3453 break; 3454 case ACB_ADAPTER_TYPE_C: 3455 arcmsr_start_hbc_bgrb(acb); 3456 break; 3457 case ACB_ADAPTER_TYPE_D: 3458 arcmsr_start_hbd_bgrb(acb); 3459 break; 3460 case ACB_ADAPTER_TYPE_E: 3461 case ACB_ADAPTER_TYPE_F: 3462 arcmsr_start_hbe_bgrb(acb); 3463 break; 3464 } 3465 } 3466 /* 3467 ********************************************************************** 3468 ** 3469 ********************************************************************** 3470 */ 3471 static void arcmsr_polling_hba_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3472 { 3473 struct CommandControlBlock *srb; 3474 u_int32_t flag_srb, outbound_intstatus, poll_srb_done=0, poll_count=0; 3475 u_int16_t error; 3476 3477 polling_ccb_retry: 3478 poll_count++; 3479 outbound_intstatus=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 3480 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus); /*clear interrupt*/ 3481 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3482 while(1) { 3483 if((flag_srb = CHIP_REG_READ32(HBA_MessageUnit, 3484 0, outbound_queueport)) == 0xFFFFFFFF) { 3485 if(poll_srb_done) { 3486 break;/*chip FIFO no ccb for completion already*/ 3487 } else { 3488 UDELAY(25000); 3489 if ((poll_count > 100) && (poll_srb != NULL)) { 3490 break; 3491 } 3492 goto polling_ccb_retry; 3493 } 3494 } 3495 /* check if command done with no error*/ 3496 srb = (struct CommandControlBlock *) 3497 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 3498 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 3499 poll_srb_done = (srb == poll_srb) ? 1:0; 3500 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3501 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3502 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'" 3503 "poll command abort successfully \n" 3504 , acb->pci_unit 3505 , srb->pccb->ccb_h.target_id 3506 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3507 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3508 arcmsr_srb_complete(srb, 1); 3509 continue; 3510 } 3511 printf("arcmsr%d: polling get an illegal srb command done srb='%p'" 3512 "srboutstandingcount=%d \n" 3513 , acb->pci_unit 3514 , srb, acb->srboutstandingcount); 3515 continue; 3516 } 3517 arcmsr_report_srb_state(acb, srb, error); 3518 } /*drain reply FIFO*/ 3519 } 3520 /* 3521 ********************************************************************** 3522 ** 3523 ********************************************************************** 3524 */ 3525 static void arcmsr_polling_hbb_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3526 { 3527 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3528 struct CommandControlBlock *srb; 3529 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3530 int index; 3531 u_int16_t error; 3532 3533 polling_ccb_retry: 3534 poll_count++; 3535 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */ 3536 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3537 while(1) { 3538 index = phbbmu->doneq_index; 3539 if((flag_srb = phbbmu->done_qbuffer[index]) == 0) { 3540 if(poll_srb_done) { 3541 break;/*chip FIFO no ccb for completion already*/ 3542 } else { 3543 UDELAY(25000); 3544 if ((poll_count > 100) && (poll_srb != NULL)) { 3545 break; 3546 } 3547 goto polling_ccb_retry; 3548 } 3549 } 3550 phbbmu->done_qbuffer[index] = 0; 3551 index++; 3552 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 3553 phbbmu->doneq_index = index; 3554 /* check if command done with no error*/ 3555 srb = (struct CommandControlBlock *) 3556 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 3557 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 3558 poll_srb_done = (srb == poll_srb) ? 1:0; 3559 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3560 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3561 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'" 3562 "poll command abort successfully \n" 3563 , acb->pci_unit 3564 , srb->pccb->ccb_h.target_id 3565 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3566 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3567 arcmsr_srb_complete(srb, 1); 3568 continue; 3569 } 3570 printf("arcmsr%d: polling get an illegal srb command done srb='%p'" 3571 "srboutstandingcount=%d \n" 3572 , acb->pci_unit 3573 , srb, acb->srboutstandingcount); 3574 continue; 3575 } 3576 arcmsr_report_srb_state(acb, srb, error); 3577 } /*drain reply FIFO*/ 3578 } 3579 /* 3580 ********************************************************************** 3581 ** 3582 ********************************************************************** 3583 */ 3584 static void arcmsr_polling_hbc_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3585 { 3586 struct CommandControlBlock *srb; 3587 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3588 u_int16_t error; 3589 3590 polling_ccb_retry: 3591 poll_count++; 3592 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3593 while(1) { 3594 if(!(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)) { 3595 if(poll_srb_done) { 3596 break;/*chip FIFO no ccb for completion already*/ 3597 } else { 3598 UDELAY(25000); 3599 if ((poll_count > 100) && (poll_srb != NULL)) { 3600 break; 3601 } 3602 if (acb->srboutstandingcount == 0) { 3603 break; 3604 } 3605 goto polling_ccb_retry; 3606 } 3607 } 3608 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 3609 /* check if command done with no error*/ 3610 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/ 3611 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE; 3612 if (poll_srb != NULL) 3613 poll_srb_done = (srb == poll_srb) ? 1:0; 3614 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3615 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3616 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n" 3617 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3618 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3619 arcmsr_srb_complete(srb, 1); 3620 continue; 3621 } 3622 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 3623 , acb->pci_unit, srb, acb->srboutstandingcount); 3624 continue; 3625 } 3626 arcmsr_report_srb_state(acb, srb, error); 3627 } /*drain reply FIFO*/ 3628 } 3629 /* 3630 ********************************************************************** 3631 ** 3632 ********************************************************************** 3633 */ 3634 static void arcmsr_polling_hbd_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3635 { 3636 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 3637 struct CommandControlBlock *srb; 3638 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3639 u_int32_t outbound_write_pointer; 3640 u_int16_t error, doneq_index; 3641 3642 polling_ccb_retry: 3643 poll_count++; 3644 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3645 while(1) { 3646 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 3647 doneq_index = phbdmu->doneq_index; 3648 if ((outbound_write_pointer & 0xFF) == (doneq_index & 0xFF)) { 3649 if(poll_srb_done) { 3650 break;/*chip FIFO no ccb for completion already*/ 3651 } else { 3652 UDELAY(25000); 3653 if ((poll_count > 100) && (poll_srb != NULL)) { 3654 break; 3655 } 3656 if (acb->srboutstandingcount == 0) { 3657 break; 3658 } 3659 goto polling_ccb_retry; 3660 } 3661 } 3662 doneq_index = arcmsr_get_doneq_index(phbdmu); 3663 flag_srb = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow; 3664 /* check if command done with no error*/ 3665 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/ 3666 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 3667 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index); 3668 if (poll_srb != NULL) 3669 poll_srb_done = (srb == poll_srb) ? 1:0; 3670 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3671 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3672 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n" 3673 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3674 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3675 arcmsr_srb_complete(srb, 1); 3676 continue; 3677 } 3678 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 3679 , acb->pci_unit, srb, acb->srboutstandingcount); 3680 continue; 3681 } 3682 arcmsr_report_srb_state(acb, srb, error); 3683 } /*drain reply FIFO*/ 3684 } 3685 /* 3686 ********************************************************************** 3687 ** 3688 ********************************************************************** 3689 */ 3690 static void arcmsr_polling_hbe_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3691 { 3692 struct CommandControlBlock *srb; 3693 u_int32_t poll_srb_done=0, poll_count=0, doneq_index; 3694 u_int16_t error, cmdSMID; 3695 3696 polling_ccb_retry: 3697 poll_count++; 3698 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3699 while(1) { 3700 doneq_index = acb->doneq_index; 3701 if((CHIP_REG_READ32(HBE_MessageUnit, 0, reply_post_producer_index) & 0xFFFF) == doneq_index) { 3702 if(poll_srb_done) { 3703 break;/*chip FIFO no ccb for completion already*/ 3704 } else { 3705 UDELAY(25000); 3706 if ((poll_count > 100) && (poll_srb != NULL)) { 3707 break; 3708 } 3709 if (acb->srboutstandingcount == 0) { 3710 break; 3711 } 3712 goto polling_ccb_retry; 3713 } 3714 } 3715 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID; 3716 doneq_index++; 3717 if (doneq_index >= acb->completionQ_entry) 3718 doneq_index = 0; 3719 acb->doneq_index = doneq_index; 3720 srb = acb->psrb_pool[cmdSMID]; 3721 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 3722 if (poll_srb != NULL) 3723 poll_srb_done = (srb == poll_srb) ? 1:0; 3724 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3725 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3726 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n" 3727 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3728 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3729 arcmsr_srb_complete(srb, 1); 3730 continue; 3731 } 3732 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 3733 , acb->pci_unit, srb, acb->srboutstandingcount); 3734 continue; 3735 } 3736 arcmsr_report_srb_state(acb, srb, error); 3737 } /*drain reply FIFO*/ 3738 CHIP_REG_WRITE32(HBE_MessageUnit, 0, reply_post_producer_index, doneq_index); 3739 } 3740 /* 3741 ********************************************************************** 3742 ********************************************************************** 3743 */ 3744 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3745 { 3746 switch (acb->adapter_type) { 3747 case ACB_ADAPTER_TYPE_A: 3748 arcmsr_polling_hba_srbdone(acb, poll_srb); 3749 break; 3750 case ACB_ADAPTER_TYPE_B: 3751 arcmsr_polling_hbb_srbdone(acb, poll_srb); 3752 break; 3753 case ACB_ADAPTER_TYPE_C: 3754 arcmsr_polling_hbc_srbdone(acb, poll_srb); 3755 break; 3756 case ACB_ADAPTER_TYPE_D: 3757 arcmsr_polling_hbd_srbdone(acb, poll_srb); 3758 break; 3759 case ACB_ADAPTER_TYPE_E: 3760 case ACB_ADAPTER_TYPE_F: 3761 arcmsr_polling_hbe_srbdone(acb, poll_srb); 3762 break; 3763 } 3764 } 3765 /* 3766 ********************************************************************** 3767 ********************************************************************** 3768 */ 3769 static void arcmsr_get_hba_config(struct AdapterControlBlock *acb) 3770 { 3771 char *acb_firm_model = acb->firm_model; 3772 char *acb_firm_version = acb->firm_version; 3773 char *acb_device_map = acb->device_map; 3774 size_t iop_firm_model = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3775 size_t iop_firm_version = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3776 size_t iop_device_map = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3777 int i; 3778 3779 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3780 if(!arcmsr_hba_wait_msgint_ready(acb)) { 3781 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3782 } 3783 i = 0; 3784 while(i < 8) { 3785 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3786 /* 8 bytes firm_model, 15, 60-67*/ 3787 acb_firm_model++; 3788 i++; 3789 } 3790 i=0; 3791 while(i < 16) { 3792 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3793 /* 16 bytes firm_version, 17, 68-83*/ 3794 acb_firm_version++; 3795 i++; 3796 } 3797 i=0; 3798 while(i < 16) { 3799 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3800 acb_device_map++; 3801 i++; 3802 } 3803 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3804 acb->firm_request_len = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3805 acb->firm_numbers_queue = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3806 acb->firm_sdram_size = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3807 acb->firm_ide_channels = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3808 acb->firm_cfg_version = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3809 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 3810 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 3811 else 3812 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3813 } 3814 /* 3815 ********************************************************************** 3816 ********************************************************************** 3817 */ 3818 static void arcmsr_get_hbb_config(struct AdapterControlBlock *acb) 3819 { 3820 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3821 char *acb_firm_model = acb->firm_model; 3822 char *acb_firm_version = acb->firm_version; 3823 char *acb_device_map = acb->device_map; 3824 size_t iop_firm_model = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3825 size_t iop_firm_version = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3826 size_t iop_device_map = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3827 int i; 3828 3829 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG); 3830 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3831 printf( "arcmsr%d: wait" "'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3832 } 3833 i = 0; 3834 while(i < 8) { 3835 *acb_firm_model = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_model+i); 3836 /* 8 bytes firm_model, 15, 60-67*/ 3837 acb_firm_model++; 3838 i++; 3839 } 3840 i = 0; 3841 while(i < 16) { 3842 *acb_firm_version = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_version+i); 3843 /* 16 bytes firm_version, 17, 68-83*/ 3844 acb_firm_version++; 3845 i++; 3846 } 3847 i = 0; 3848 while(i < 16) { 3849 *acb_device_map = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_device_map+i); 3850 acb_device_map++; 3851 i++; 3852 } 3853 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3854 acb->firm_request_len = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3855 acb->firm_numbers_queue = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3856 acb->firm_sdram_size = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3857 acb->firm_ide_channels = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3858 acb->firm_cfg_version = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3859 if(acb->firm_numbers_queue > ARCMSR_MAX_HBB_POSTQUEUE) 3860 acb->maxOutstanding = ARCMSR_MAX_HBB_POSTQUEUE - 1; 3861 else 3862 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3863 } 3864 /* 3865 ********************************************************************** 3866 ********************************************************************** 3867 */ 3868 static void arcmsr_get_hbc_config(struct AdapterControlBlock *acb) 3869 { 3870 char *acb_firm_model = acb->firm_model; 3871 char *acb_firm_version = acb->firm_version; 3872 char *acb_device_map = acb->device_map; 3873 size_t iop_firm_model = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3874 size_t iop_firm_version = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3875 size_t iop_device_map = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3876 int i; 3877 3878 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3879 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3880 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 3881 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3882 } 3883 i = 0; 3884 while(i < 8) { 3885 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3886 /* 8 bytes firm_model, 15, 60-67*/ 3887 acb_firm_model++; 3888 i++; 3889 } 3890 i = 0; 3891 while(i < 16) { 3892 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3893 /* 16 bytes firm_version, 17, 68-83*/ 3894 acb_firm_version++; 3895 i++; 3896 } 3897 i = 0; 3898 while(i < 16) { 3899 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3900 acb_device_map++; 3901 i++; 3902 } 3903 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3904 acb->firm_request_len = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3905 acb->firm_numbers_queue = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3906 acb->firm_sdram_size = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3907 acb->firm_ide_channels = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3908 acb->firm_cfg_version = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3909 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 3910 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 3911 else 3912 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3913 } 3914 /* 3915 ********************************************************************** 3916 ********************************************************************** 3917 */ 3918 static void arcmsr_get_hbd_config(struct AdapterControlBlock *acb) 3919 { 3920 char *acb_firm_model = acb->firm_model; 3921 char *acb_firm_version = acb->firm_version; 3922 char *acb_device_map = acb->device_map; 3923 size_t iop_firm_model = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3924 size_t iop_firm_version = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3925 size_t iop_device_map = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3926 int i; 3927 3928 if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) 3929 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR); 3930 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3931 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 3932 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3933 } 3934 i = 0; 3935 while(i < 8) { 3936 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3937 /* 8 bytes firm_model, 15, 60-67*/ 3938 acb_firm_model++; 3939 i++; 3940 } 3941 i = 0; 3942 while(i < 16) { 3943 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3944 /* 16 bytes firm_version, 17, 68-83*/ 3945 acb_firm_version++; 3946 i++; 3947 } 3948 i = 0; 3949 while(i < 16) { 3950 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3951 acb_device_map++; 3952 i++; 3953 } 3954 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3955 acb->firm_request_len = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3956 acb->firm_numbers_queue = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3957 acb->firm_sdram_size = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3958 acb->firm_ide_channels = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3959 acb->firm_cfg_version = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3960 if(acb->firm_numbers_queue > ARCMSR_MAX_HBD_POSTQUEUE) 3961 acb->maxOutstanding = ARCMSR_MAX_HBD_POSTQUEUE - 1; 3962 else 3963 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3964 } 3965 /* 3966 ********************************************************************** 3967 ********************************************************************** 3968 */ 3969 static void arcmsr_get_hbe_config(struct AdapterControlBlock *acb) 3970 { 3971 char *acb_firm_model = acb->firm_model; 3972 char *acb_firm_version = acb->firm_version; 3973 char *acb_device_map = acb->device_map; 3974 size_t iop_firm_model = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3975 size_t iop_firm_version = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3976 size_t iop_device_map = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3977 int i; 3978 3979 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3980 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 3981 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 3982 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 3983 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3984 } 3985 3986 i = 0; 3987 while(i < 8) { 3988 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3989 /* 8 bytes firm_model, 15, 60-67*/ 3990 acb_firm_model++; 3991 i++; 3992 } 3993 i = 0; 3994 while(i < 16) { 3995 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3996 /* 16 bytes firm_version, 17, 68-83*/ 3997 acb_firm_version++; 3998 i++; 3999 } 4000 i = 0; 4001 while(i < 16) { 4002 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 4003 acb_device_map++; 4004 i++; 4005 } 4006 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 4007 acb->firm_request_len = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 4008 acb->firm_numbers_queue = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 4009 acb->firm_sdram_size = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 4010 acb->firm_ide_channels = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 4011 acb->firm_cfg_version = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 4012 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 4013 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 4014 else 4015 acb->maxOutstanding = acb->firm_numbers_queue - 1; 4016 } 4017 /* 4018 ********************************************************************** 4019 ********************************************************************** 4020 */ 4021 static void arcmsr_get_hbf_config(struct AdapterControlBlock *acb) 4022 { 4023 u_int32_t *acb_firm_model = (u_int32_t *)acb->firm_model; 4024 u_int32_t *acb_firm_version = (u_int32_t *)acb->firm_version; 4025 u_int32_t *acb_device_map = (u_int32_t *)acb->device_map; 4026 size_t iop_firm_model = ARCMSR_FW_MODEL_OFFSET; /*firm_model,15,60-67*/ 4027 size_t iop_firm_version = ARCMSR_FW_VERS_OFFSET; /*firm_version,17,68-83*/ 4028 size_t iop_device_map = ARCMSR_FW_DEVMAP_OFFSET; 4029 int i; 4030 4031 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 4032 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 4033 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 4034 if(!arcmsr_hbe_wait_msgint_ready(acb)) 4035 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 4036 4037 i = 0; 4038 while(i < 2) { 4039 *acb_firm_model = acb->msgcode_rwbuffer[iop_firm_model]; 4040 /* 8 bytes firm_model, 15, 60-67*/ 4041 acb_firm_model++; 4042 iop_firm_model++; 4043 i++; 4044 } 4045 i = 0; 4046 while(i < 4) { 4047 *acb_firm_version = acb->msgcode_rwbuffer[iop_firm_version]; 4048 /* 16 bytes firm_version, 17, 68-83*/ 4049 acb_firm_version++; 4050 iop_firm_version++; 4051 i++; 4052 } 4053 i = 0; 4054 while(i < 4) { 4055 *acb_device_map = acb->msgcode_rwbuffer[iop_device_map]; 4056 acb_device_map++; 4057 iop_device_map++; 4058 i++; 4059 } 4060 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 4061 acb->firm_request_len = acb->msgcode_rwbuffer[1]; /*firm_request_len, 1, 04-07*/ 4062 acb->firm_numbers_queue = acb->msgcode_rwbuffer[2]; /*firm_numbers_queue, 2, 08-11*/ 4063 acb->firm_sdram_size = acb->msgcode_rwbuffer[3]; /*firm_sdram_size, 3, 12-15*/ 4064 acb->firm_ide_channels = acb->msgcode_rwbuffer[4]; /*firm_ide_channels, 4, 16-19*/ 4065 acb->firm_cfg_version = acb->msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]; /*firm_cfg_version, 25*/ 4066 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 4067 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 4068 else 4069 acb->maxOutstanding = acb->firm_numbers_queue - 1; 4070 } 4071 /* 4072 ********************************************************************** 4073 ********************************************************************** 4074 */ 4075 static void arcmsr_get_firmware_spec(struct AdapterControlBlock *acb) 4076 { 4077 switch (acb->adapter_type) { 4078 case ACB_ADAPTER_TYPE_A: 4079 arcmsr_get_hba_config(acb); 4080 break; 4081 case ACB_ADAPTER_TYPE_B: 4082 arcmsr_get_hbb_config(acb); 4083 break; 4084 case ACB_ADAPTER_TYPE_C: 4085 arcmsr_get_hbc_config(acb); 4086 break; 4087 case ACB_ADAPTER_TYPE_D: 4088 arcmsr_get_hbd_config(acb); 4089 break; 4090 case ACB_ADAPTER_TYPE_E: 4091 arcmsr_get_hbe_config(acb); 4092 break; 4093 case ACB_ADAPTER_TYPE_F: 4094 arcmsr_get_hbf_config(acb); 4095 break; 4096 } 4097 } 4098 /* 4099 ********************************************************************** 4100 ********************************************************************** 4101 */ 4102 static void arcmsr_wait_firmware_ready( struct AdapterControlBlock *acb) 4103 { 4104 int timeout=0; 4105 4106 switch (acb->adapter_type) { 4107 case ACB_ADAPTER_TYPE_A: { 4108 while ((CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0) 4109 { 4110 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 4111 { 4112 printf( "arcmsr%d:timed out waiting for firmware \n", acb->pci_unit); 4113 return; 4114 } 4115 UDELAY(15000); /* wait 15 milli-seconds */ 4116 } 4117 } 4118 break; 4119 case ACB_ADAPTER_TYPE_B: { 4120 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4121 while ((READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & ARCMSR_MESSAGE_FIRMWARE_OK) == 0) 4122 { 4123 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 4124 { 4125 printf( "arcmsr%d: timed out waiting for firmware \n", acb->pci_unit); 4126 return; 4127 } 4128 UDELAY(15000); /* wait 15 milli-seconds */ 4129 } 4130 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 4131 } 4132 break; 4133 case ACB_ADAPTER_TYPE_C: { 4134 while ((CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0) 4135 { 4136 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 4137 { 4138 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 4139 return; 4140 } 4141 UDELAY(15000); /* wait 15 milli-seconds */ 4142 } 4143 } 4144 break; 4145 case ACB_ADAPTER_TYPE_D: { 4146 while ((CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK) == 0) 4147 { 4148 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 4149 { 4150 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 4151 return; 4152 } 4153 UDELAY(15000); /* wait 15 milli-seconds */ 4154 } 4155 } 4156 break; 4157 case ACB_ADAPTER_TYPE_E: 4158 case ACB_ADAPTER_TYPE_F: { 4159 while ((CHIP_REG_READ32(HBE_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK) == 0) 4160 { 4161 if (timeout++ > 4000) /* (4000*15)/1000 = 60 sec */ 4162 { 4163 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 4164 return; 4165 } 4166 UDELAY(15000); /* wait 15 milli-seconds */ 4167 } 4168 } 4169 break; 4170 } 4171 } 4172 /* 4173 ********************************************************************** 4174 ********************************************************************** 4175 */ 4176 static void arcmsr_clear_doorbell_queue_buffer( struct AdapterControlBlock *acb) 4177 { 4178 u_int32_t outbound_doorbell; 4179 4180 switch (acb->adapter_type) { 4181 case ACB_ADAPTER_TYPE_A: { 4182 /* empty doorbell Qbuffer if door bell ringed */ 4183 outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell); 4184 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */ 4185 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK); 4186 } 4187 break; 4188 case ACB_ADAPTER_TYPE_B: { 4189 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4190 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN);/*clear interrupt and message state*/ 4191 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK); 4192 /* let IOP know data has been read */ 4193 } 4194 break; 4195 case ACB_ADAPTER_TYPE_C: { 4196 /* empty doorbell Qbuffer if door bell ringed */ 4197 outbound_doorbell = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell); 4198 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell); /*clear doorbell interrupt */ 4199 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK); 4200 CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell_clear); /* Dummy read to force pci flush */ 4201 CHIP_REG_READ32(HBC_MessageUnit, 0, inbound_doorbell); /* Dummy read to force pci flush */ 4202 } 4203 break; 4204 case ACB_ADAPTER_TYPE_D: { 4205 /* empty doorbell Qbuffer if door bell ringed */ 4206 outbound_doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell); 4207 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */ 4208 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ); 4209 } 4210 break; 4211 case ACB_ADAPTER_TYPE_E: 4212 case ACB_ADAPTER_TYPE_F: { 4213 /* empty doorbell Qbuffer if door bell ringed */ 4214 acb->in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell); 4215 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /*clear doorbell interrupt */ 4216 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK; 4217 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 4218 } 4219 break; 4220 } 4221 } 4222 /* 4223 ************************************************************************ 4224 ************************************************************************ 4225 */ 4226 static u_int32_t arcmsr_iop_confirm(struct AdapterControlBlock *acb) 4227 { 4228 unsigned long srb_phyaddr; 4229 u_int32_t srb_phyaddr_hi32; 4230 u_int32_t srb_phyaddr_lo32; 4231 4232 /* 4233 ******************************************************************** 4234 ** here we need to tell iop 331 our freesrb.HighPart 4235 ** if freesrb.HighPart is not zero 4236 ******************************************************************** 4237 */ 4238 srb_phyaddr = (unsigned long) acb->srb_phyaddr.phyaddr; 4239 srb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high; 4240 srb_phyaddr_lo32 = acb->srb_phyaddr.B.phyadd_low; 4241 switch (acb->adapter_type) { 4242 case ACB_ADAPTER_TYPE_A: { 4243 if(srb_phyaddr_hi32 != 0) { 4244 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 4245 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 4246 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4247 if(!arcmsr_hba_wait_msgint_ready(acb)) { 4248 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4249 return FALSE; 4250 } 4251 } 4252 } 4253 break; 4254 /* 4255 *********************************************************************** 4256 ** if adapter type B, set window of "post command Q" 4257 *********************************************************************** 4258 */ 4259 case ACB_ADAPTER_TYPE_B: { 4260 u_int32_t post_queue_phyaddr; 4261 struct HBB_MessageUnit *phbbmu; 4262 4263 phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4264 phbbmu->postq_index = 0; 4265 phbbmu->doneq_index = 0; 4266 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_SET_POST_WINDOW); 4267 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 4268 printf( "arcmsr%d: 'set window of post command Q' timeout\n", acb->pci_unit); 4269 return FALSE; 4270 } 4271 post_queue_phyaddr = srb_phyaddr + ARCMSR_SRBS_POOL_SIZE 4272 + offsetof(struct HBB_MessageUnit, post_qbuffer); 4273 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */ 4274 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1], srb_phyaddr_hi32); /* normal should be zero */ 4275 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ size (256+8)*4 */ 4276 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3], post_queue_phyaddr+1056); /* doneQ size (256+8)*4 */ 4277 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4], 1056); /* srb maxQ size must be --> [(256+8)*4] */ 4278 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_SET_CONFIG); 4279 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 4280 printf( "arcmsr%d: 'set command Q window' timeout \n", acb->pci_unit); 4281 return FALSE; 4282 } 4283 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_START_DRIVER_MODE); 4284 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 4285 printf( "arcmsr%d: 'start diver mode' timeout \n", acb->pci_unit); 4286 return FALSE; 4287 } 4288 } 4289 break; 4290 case ACB_ADAPTER_TYPE_C: { 4291 if(srb_phyaddr_hi32 != 0) { 4292 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 4293 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 4294 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4295 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 4296 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 4297 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4298 return FALSE; 4299 } 4300 } 4301 } 4302 break; 4303 case ACB_ADAPTER_TYPE_D: { 4304 u_int32_t post_queue_phyaddr, done_queue_phyaddr; 4305 struct HBD_MessageUnit0 *phbdmu; 4306 4307 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 4308 phbdmu->postq_index = 0; 4309 phbdmu->doneq_index = 0x40FF; 4310 post_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE 4311 + offsetof(struct HBD_MessageUnit0, post_qbuffer); 4312 done_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE 4313 + offsetof(struct HBD_MessageUnit0, done_qbuffer); 4314 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */ 4315 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 4316 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ base */ 4317 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[3], done_queue_phyaddr); /* doneQ base */ 4318 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[4], 0x100); 4319 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4320 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 4321 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4322 return FALSE; 4323 } 4324 } 4325 break; 4326 case ACB_ADAPTER_TYPE_E: { 4327 u_int32_t cdb_phyaddr_lo32; 4328 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + offsetof(struct CommandControlBlock, arcmsr_cdb); 4329 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 4330 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[1], ARCMSR_SIGNATURE_1884); 4331 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[2], cdb_phyaddr_lo32); 4332 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[3], srb_phyaddr_hi32); 4333 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[4], SRB_SIZE); 4334 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE; 4335 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[5], cdb_phyaddr_lo32); 4336 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[6], srb_phyaddr_hi32); 4337 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[7], COMPLETION_Q_POOL_SIZE); 4338 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4339 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 4340 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 4341 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 4342 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4343 return FALSE; 4344 } 4345 } 4346 break; 4347 case ACB_ADAPTER_TYPE_F: { 4348 u_int32_t cdb_phyaddr_lo32; 4349 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + offsetof(struct CommandControlBlock, arcmsr_cdb); 4350 acb->msgcode_rwbuffer[0] = ARCMSR_SIGNATURE_SET_CONFIG; 4351 acb->msgcode_rwbuffer[1] = ARCMSR_SIGNATURE_1886; 4352 acb->msgcode_rwbuffer[2] = cdb_phyaddr_lo32; 4353 acb->msgcode_rwbuffer[3] = srb_phyaddr_hi32; 4354 acb->msgcode_rwbuffer[4] = SRB_SIZE; 4355 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE; 4356 acb->msgcode_rwbuffer[5] = cdb_phyaddr_lo32; 4357 acb->msgcode_rwbuffer[6] = srb_phyaddr_hi32; 4358 acb->msgcode_rwbuffer[7] = COMPLETION_Q_POOL_SIZE; 4359 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4360 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 4361 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 4362 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 4363 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4364 return FALSE; 4365 } 4366 } 4367 break; 4368 } 4369 return (TRUE); 4370 } 4371 /* 4372 ************************************************************************ 4373 ************************************************************************ 4374 */ 4375 static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb) 4376 { 4377 if (acb->adapter_type == ACB_ADAPTER_TYPE_B) 4378 { 4379 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4380 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_ACTIVE_EOI_MODE); 4381 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 4382 printf( "arcmsr%d: 'iop enable eoi mode' timeout \n", acb->pci_unit); 4383 return; 4384 } 4385 } 4386 } 4387 /* 4388 ********************************************************************** 4389 ********************************************************************** 4390 */ 4391 static void arcmsr_iop_init(struct AdapterControlBlock *acb) 4392 { 4393 u_int32_t intmask_org; 4394 4395 /* disable all outbound interrupt */ 4396 intmask_org = arcmsr_disable_allintr(acb); 4397 arcmsr_wait_firmware_ready(acb); 4398 arcmsr_iop_confirm(acb); 4399 arcmsr_get_firmware_spec(acb); 4400 /*start background rebuild*/ 4401 arcmsr_start_adapter_bgrb(acb); 4402 /* empty doorbell Qbuffer if door bell ringed */ 4403 arcmsr_clear_doorbell_queue_buffer(acb); 4404 arcmsr_enable_eoi_mode(acb); 4405 /* enable outbound Post Queue, outbound doorbell Interrupt */ 4406 arcmsr_enable_allintr(acb, intmask_org); 4407 acb->acb_flags |= ACB_F_IOP_INITED; 4408 } 4409 /* 4410 ********************************************************************** 4411 ********************************************************************** 4412 */ 4413 static void arcmsr_map_free_srb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4414 { 4415 struct AdapterControlBlock *acb = arg; 4416 struct CommandControlBlock *srb_tmp; 4417 u_int32_t i; 4418 unsigned long srb_phyaddr = (unsigned long)segs->ds_addr; 4419 4420 acb->srb_phyaddr.phyaddr = srb_phyaddr; 4421 srb_tmp = (struct CommandControlBlock *)acb->uncacheptr; 4422 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 4423 if(bus_dmamap_create(acb->dm_segs_dmat, 4424 /*flags*/0, &srb_tmp->dm_segs_dmamap) != 0) { 4425 acb->acb_flags |= ACB_F_MAPFREESRB_FAILD; 4426 printf("arcmsr%d:" 4427 " srb dmamap bus_dmamap_create error\n", acb->pci_unit); 4428 return; 4429 } 4430 if((acb->adapter_type == ACB_ADAPTER_TYPE_C) || (acb->adapter_type == ACB_ADAPTER_TYPE_D) 4431 || (acb->adapter_type == ACB_ADAPTER_TYPE_E) || (acb->adapter_type == ACB_ADAPTER_TYPE_F)) 4432 { 4433 srb_tmp->cdb_phyaddr_low = srb_phyaddr; 4434 srb_tmp->cdb_phyaddr_high = (u_int32_t)((srb_phyaddr >> 16) >> 16); 4435 } 4436 else 4437 srb_tmp->cdb_phyaddr_low = srb_phyaddr >> 5; 4438 srb_tmp->acb = acb; 4439 srb_tmp->smid = i << 16; 4440 acb->srbworkingQ[i] = acb->psrb_pool[i] = srb_tmp; 4441 srb_phyaddr = srb_phyaddr + SRB_SIZE; 4442 srb_tmp = (struct CommandControlBlock *)((unsigned long)srb_tmp + SRB_SIZE); 4443 } 4444 if (acb->adapter_type == ACB_ADAPTER_TYPE_E) 4445 acb->pCompletionQ = (pCompletion_Q)srb_tmp; 4446 else if (acb->adapter_type == ACB_ADAPTER_TYPE_F) { 4447 acb->pCompletionQ = (pCompletion_Q)srb_tmp; 4448 acb->completeQ_phys = srb_phyaddr; 4449 memset(acb->pCompletionQ, 0xff, COMPLETION_Q_POOL_SIZE); 4450 acb->message_wbuffer = (u_int32_t *)((unsigned long)acb->pCompletionQ + COMPLETION_Q_POOL_SIZE); 4451 acb->message_rbuffer = (u_int32_t *)((unsigned long)acb->message_wbuffer + 0x100); 4452 acb->msgcode_rwbuffer = (u_int32_t *)((unsigned long)acb->message_wbuffer + 0x200); 4453 memset((void *)acb->message_wbuffer, 0, MESG_RW_BUFFER_SIZE); 4454 } 4455 acb->vir2phy_offset = (unsigned long)srb_tmp - (unsigned long)srb_phyaddr; 4456 } 4457 /* 4458 ************************************************************************ 4459 ************************************************************************ 4460 */ 4461 static void arcmsr_free_resource(struct AdapterControlBlock *acb) 4462 { 4463 /* remove the control device */ 4464 if(acb->ioctl_dev != NULL) { 4465 destroy_dev(acb->ioctl_dev); 4466 } 4467 bus_dmamap_unload(acb->srb_dmat, acb->srb_dmamap); 4468 bus_dmamap_destroy(acb->srb_dmat, acb->srb_dmamap); 4469 bus_dma_tag_destroy(acb->srb_dmat); 4470 bus_dma_tag_destroy(acb->dm_segs_dmat); 4471 bus_dma_tag_destroy(acb->parent_dmat); 4472 } 4473 /* 4474 ************************************************************************ 4475 ************************************************************************ 4476 */ 4477 static void arcmsr_mutex_init(struct AdapterControlBlock *acb) 4478 { 4479 ARCMSR_LOCK_INIT(&acb->isr_lock, "arcmsr isr lock"); 4480 ARCMSR_LOCK_INIT(&acb->srb_lock, "arcmsr srb lock"); 4481 ARCMSR_LOCK_INIT(&acb->postDone_lock, "arcmsr postQ lock"); 4482 ARCMSR_LOCK_INIT(&acb->qbuffer_lock, "arcmsr RW buffer lock"); 4483 } 4484 /* 4485 ************************************************************************ 4486 ************************************************************************ 4487 */ 4488 static void arcmsr_mutex_destroy(struct AdapterControlBlock *acb) 4489 { 4490 ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock); 4491 ARCMSR_LOCK_DESTROY(&acb->postDone_lock); 4492 ARCMSR_LOCK_DESTROY(&acb->srb_lock); 4493 ARCMSR_LOCK_DESTROY(&acb->isr_lock); 4494 } 4495 /* 4496 ************************************************************************ 4497 ************************************************************************ 4498 */ 4499 static u_int32_t arcmsr_initialize(device_t dev) 4500 { 4501 struct AdapterControlBlock *acb = device_get_softc(dev); 4502 u_int16_t pci_command; 4503 int i, j,max_coherent_size; 4504 u_int32_t vendor_dev_id; 4505 4506 vendor_dev_id = pci_get_devid(dev); 4507 acb->vendor_device_id = vendor_dev_id; 4508 acb->sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); 4509 switch (vendor_dev_id) { 4510 case PCIDevVenIDARC1880: 4511 case PCIDevVenIDARC1882: 4512 case PCIDevVenIDARC1213: 4513 case PCIDevVenIDARC1223: { 4514 acb->adapter_type = ACB_ADAPTER_TYPE_C; 4515 if ((acb->sub_device_id == ARECA_SUB_DEV_ID_1883) || 4516 (acb->sub_device_id == ARECA_SUB_DEV_ID_1216) || 4517 (acb->sub_device_id == ARECA_SUB_DEV_ID_1226)) 4518 acb->adapter_bus_speed = ACB_BUS_SPEED_12G; 4519 else 4520 acb->adapter_bus_speed = ACB_BUS_SPEED_6G; 4521 max_coherent_size = ARCMSR_SRBS_POOL_SIZE; 4522 } 4523 break; 4524 case PCIDevVenIDARC1884: 4525 acb->adapter_type = ACB_ADAPTER_TYPE_E; 4526 acb->adapter_bus_speed = ACB_BUS_SPEED_12G; 4527 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + COMPLETION_Q_POOL_SIZE; 4528 acb->completionQ_entry = COMPLETION_Q_POOL_SIZE / sizeof(struct deliver_completeQ); 4529 break; 4530 case PCIDevVenIDARC1886_: 4531 case PCIDevVenIDARC1886: 4532 acb->adapter_type = ACB_ADAPTER_TYPE_F; 4533 acb->adapter_bus_speed = ACB_BUS_SPEED_12G; 4534 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + COMPLETION_Q_POOL_SIZE + MESG_RW_BUFFER_SIZE; 4535 acb->completionQ_entry = COMPLETION_Q_POOL_SIZE / sizeof(struct deliver_completeQ); 4536 break; 4537 case PCIDevVenIDARC1214: { 4538 acb->adapter_type = ACB_ADAPTER_TYPE_D; 4539 acb->adapter_bus_speed = ACB_BUS_SPEED_6G; 4540 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBD_MessageUnit0)); 4541 } 4542 break; 4543 case PCIDevVenIDARC1200: 4544 case PCIDevVenIDARC1201: { 4545 acb->adapter_type = ACB_ADAPTER_TYPE_B; 4546 acb->adapter_bus_speed = ACB_BUS_SPEED_3G; 4547 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit)); 4548 } 4549 break; 4550 case PCIDevVenIDARC1203: { 4551 acb->adapter_type = ACB_ADAPTER_TYPE_B; 4552 acb->adapter_bus_speed = ACB_BUS_SPEED_6G; 4553 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit)); 4554 } 4555 break; 4556 case PCIDevVenIDARC1110: 4557 case PCIDevVenIDARC1120: 4558 case PCIDevVenIDARC1130: 4559 case PCIDevVenIDARC1160: 4560 case PCIDevVenIDARC1170: 4561 case PCIDevVenIDARC1210: 4562 case PCIDevVenIDARC1220: 4563 case PCIDevVenIDARC1230: 4564 case PCIDevVenIDARC1231: 4565 case PCIDevVenIDARC1260: 4566 case PCIDevVenIDARC1261: 4567 case PCIDevVenIDARC1270: 4568 case PCIDevVenIDARC1280: 4569 case PCIDevVenIDARC1212: 4570 case PCIDevVenIDARC1222: 4571 case PCIDevVenIDARC1380: 4572 case PCIDevVenIDARC1381: 4573 case PCIDevVenIDARC1680: 4574 case PCIDevVenIDARC1681: { 4575 acb->adapter_type = ACB_ADAPTER_TYPE_A; 4576 acb->adapter_bus_speed = ACB_BUS_SPEED_3G; 4577 max_coherent_size = ARCMSR_SRBS_POOL_SIZE; 4578 } 4579 break; 4580 default: { 4581 printf("arcmsr%d:" 4582 " unknown RAID adapter type \n", device_get_unit(dev)); 4583 return ENOMEM; 4584 } 4585 } 4586 if(bus_dma_tag_create( /*PCI parent*/ bus_get_dma_tag(dev), 4587 /*alignemnt*/ 1, 4588 /*boundary*/ 0, 4589 /*lowaddr*/ BUS_SPACE_MAXADDR, 4590 /*highaddr*/ BUS_SPACE_MAXADDR, 4591 /*filter*/ NULL, 4592 /*filterarg*/ NULL, 4593 /*maxsize*/ BUS_SPACE_MAXSIZE_32BIT, 4594 /*nsegments*/ BUS_SPACE_UNRESTRICTED, 4595 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4596 /*flags*/ 0, 4597 /*lockfunc*/ NULL, 4598 /*lockarg*/ NULL, 4599 &acb->parent_dmat) != 0) 4600 { 4601 printf("arcmsr%d: parent_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4602 return ENOMEM; 4603 } 4604 4605 /* Create a single tag describing a region large enough to hold all of the s/g lists we will need. */ 4606 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat, 4607 /*alignment*/ 1, 4608 /*boundary*/ 0, 4609 #ifdef PAE 4610 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 4611 #else 4612 /*lowaddr*/ BUS_SPACE_MAXADDR, 4613 #endif 4614 /*highaddr*/ BUS_SPACE_MAXADDR, 4615 /*filter*/ NULL, 4616 /*filterarg*/ NULL, 4617 /*maxsize*/ ARCMSR_MAX_SG_ENTRIES * PAGE_SIZE * ARCMSR_MAX_FREESRB_NUM, 4618 /*nsegments*/ ARCMSR_MAX_SG_ENTRIES, 4619 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4620 /*flags*/ 0, 4621 /*lockfunc*/ busdma_lock_mutex, 4622 /*lockarg*/ &acb->isr_lock, 4623 &acb->dm_segs_dmat) != 0) 4624 { 4625 bus_dma_tag_destroy(acb->parent_dmat); 4626 printf("arcmsr%d: dm_segs_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4627 return ENOMEM; 4628 } 4629 4630 /* DMA tag for our srb structures.... Allocate the freesrb memory */ 4631 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat, 4632 /*alignment*/ 0x20, 4633 /*boundary*/ 0, 4634 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 4635 /*highaddr*/ BUS_SPACE_MAXADDR, 4636 /*filter*/ NULL, 4637 /*filterarg*/ NULL, 4638 /*maxsize*/ max_coherent_size, 4639 /*nsegments*/ 1, 4640 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4641 /*flags*/ 0, 4642 /*lockfunc*/ NULL, 4643 /*lockarg*/ NULL, 4644 &acb->srb_dmat) != 0) 4645 { 4646 bus_dma_tag_destroy(acb->dm_segs_dmat); 4647 bus_dma_tag_destroy(acb->parent_dmat); 4648 printf("arcmsr%d: srb_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4649 return ENXIO; 4650 } 4651 /* Allocation for our srbs */ 4652 if(bus_dmamem_alloc(acb->srb_dmat, (void **)&acb->uncacheptr, BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, &acb->srb_dmamap) != 0) { 4653 bus_dma_tag_destroy(acb->srb_dmat); 4654 bus_dma_tag_destroy(acb->dm_segs_dmat); 4655 bus_dma_tag_destroy(acb->parent_dmat); 4656 printf("arcmsr%d: srb_dmat bus_dmamem_alloc failure!\n", device_get_unit(dev)); 4657 return ENXIO; 4658 } 4659 /* And permanently map them */ 4660 if(bus_dmamap_load(acb->srb_dmat, acb->srb_dmamap, acb->uncacheptr, max_coherent_size, arcmsr_map_free_srb, acb, /*flags*/0)) { 4661 bus_dma_tag_destroy(acb->srb_dmat); 4662 bus_dma_tag_destroy(acb->dm_segs_dmat); 4663 bus_dma_tag_destroy(acb->parent_dmat); 4664 printf("arcmsr%d: srb_dmat bus_dmamap_load failure!\n", device_get_unit(dev)); 4665 return ENXIO; 4666 } 4667 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 4668 pci_command |= PCIM_CMD_BUSMASTEREN; 4669 pci_command |= PCIM_CMD_PERRESPEN; 4670 pci_command |= PCIM_CMD_MWRICEN; 4671 /* Enable Busmaster */ 4672 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 4673 switch(acb->adapter_type) { 4674 case ACB_ADAPTER_TYPE_A: { 4675 u_int32_t rid0 = PCIR_BAR(0); 4676 vm_offset_t mem_base0; 4677 4678 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev,SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4679 if(acb->sys_res_arcmsr[0] == NULL) { 4680 arcmsr_free_resource(acb); 4681 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4682 return ENOMEM; 4683 } 4684 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4685 arcmsr_free_resource(acb); 4686 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4687 return ENXIO; 4688 } 4689 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4690 if(mem_base0 == 0) { 4691 arcmsr_free_resource(acb); 4692 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4693 return ENXIO; 4694 } 4695 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4696 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4697 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4698 acb->rid[0] = rid0; 4699 } 4700 break; 4701 case ACB_ADAPTER_TYPE_B: { 4702 struct HBB_MessageUnit *phbbmu; 4703 struct CommandControlBlock *freesrb; 4704 u_int32_t rid[]={ PCIR_BAR(0), PCIR_BAR(2) }; 4705 vm_offset_t mem_base[]={0,0}; 4706 for(i=0; i < 2; i++) { 4707 acb->sys_res_arcmsr[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid[i], RF_ACTIVE); 4708 if(acb->sys_res_arcmsr[i] == NULL) { 4709 arcmsr_free_resource(acb); 4710 printf("arcmsr%d: bus_alloc_resource %d failure!\n", device_get_unit(dev), i); 4711 return ENOMEM; 4712 } 4713 if(rman_get_start(acb->sys_res_arcmsr[i]) <= 0) { 4714 arcmsr_free_resource(acb); 4715 printf("arcmsr%d: rman_get_start %d failure!\n", device_get_unit(dev), i); 4716 return ENXIO; 4717 } 4718 mem_base[i] = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[i]); 4719 if(mem_base[i] == 0) { 4720 arcmsr_free_resource(acb); 4721 printf("arcmsr%d: rman_get_virtual %d failure!\n", device_get_unit(dev), i); 4722 return ENXIO; 4723 } 4724 acb->btag[i] = rman_get_bustag(acb->sys_res_arcmsr[i]); 4725 acb->bhandle[i] = rman_get_bushandle(acb->sys_res_arcmsr[i]); 4726 } 4727 freesrb = (struct CommandControlBlock *)acb->uncacheptr; 4728 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)freesrb+ARCMSR_SRBS_POOL_SIZE); 4729 phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4730 phbbmu->hbb_doorbell = (struct HBB_DOORBELL *)mem_base[0]; 4731 phbbmu->hbb_rwbuffer = (struct HBB_RWBUFFER *)mem_base[1]; 4732 if (vendor_dev_id == PCIDevVenIDARC1203) { 4733 phbbmu->drv2iop_doorbell = offsetof(struct HBB_DOORBELL_1203, drv2iop_doorbell); 4734 phbbmu->drv2iop_doorbell_mask = offsetof(struct HBB_DOORBELL_1203, drv2iop_doorbell_mask); 4735 phbbmu->iop2drv_doorbell = offsetof(struct HBB_DOORBELL_1203, iop2drv_doorbell); 4736 phbbmu->iop2drv_doorbell_mask = offsetof(struct HBB_DOORBELL_1203, iop2drv_doorbell_mask); 4737 } else { 4738 phbbmu->drv2iop_doorbell = offsetof(struct HBB_DOORBELL, drv2iop_doorbell); 4739 phbbmu->drv2iop_doorbell_mask = offsetof(struct HBB_DOORBELL, drv2iop_doorbell_mask); 4740 phbbmu->iop2drv_doorbell = offsetof(struct HBB_DOORBELL, iop2drv_doorbell); 4741 phbbmu->iop2drv_doorbell_mask = offsetof(struct HBB_DOORBELL, iop2drv_doorbell_mask); 4742 } 4743 acb->rid[0] = rid[0]; 4744 acb->rid[1] = rid[1]; 4745 } 4746 break; 4747 case ACB_ADAPTER_TYPE_C: { 4748 u_int32_t rid0 = PCIR_BAR(1); 4749 vm_offset_t mem_base0; 4750 4751 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4752 if(acb->sys_res_arcmsr[0] == NULL) { 4753 arcmsr_free_resource(acb); 4754 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4755 return ENOMEM; 4756 } 4757 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4758 arcmsr_free_resource(acb); 4759 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4760 return ENXIO; 4761 } 4762 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4763 if(mem_base0 == 0) { 4764 arcmsr_free_resource(acb); 4765 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4766 return ENXIO; 4767 } 4768 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4769 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4770 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4771 acb->rid[0] = rid0; 4772 } 4773 break; 4774 case ACB_ADAPTER_TYPE_D: { 4775 struct HBD_MessageUnit0 *phbdmu; 4776 u_int32_t rid0 = PCIR_BAR(0); 4777 vm_offset_t mem_base0; 4778 4779 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4780 if(acb->sys_res_arcmsr[0] == NULL) { 4781 arcmsr_free_resource(acb); 4782 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4783 return ENOMEM; 4784 } 4785 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4786 arcmsr_free_resource(acb); 4787 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4788 return ENXIO; 4789 } 4790 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4791 if(mem_base0 == 0) { 4792 arcmsr_free_resource(acb); 4793 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4794 return ENXIO; 4795 } 4796 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4797 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4798 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)acb->uncacheptr+ARCMSR_SRBS_POOL_SIZE); 4799 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 4800 phbdmu->phbdmu = (struct HBD_MessageUnit *)mem_base0; 4801 acb->rid[0] = rid0; 4802 } 4803 break; 4804 case ACB_ADAPTER_TYPE_E: { 4805 u_int32_t rid0 = PCIR_BAR(1); 4806 vm_offset_t mem_base0; 4807 4808 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4809 if(acb->sys_res_arcmsr[0] == NULL) { 4810 arcmsr_free_resource(acb); 4811 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4812 return ENOMEM; 4813 } 4814 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4815 arcmsr_free_resource(acb); 4816 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4817 return ENXIO; 4818 } 4819 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4820 if(mem_base0 == 0) { 4821 arcmsr_free_resource(acb); 4822 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4823 return ENXIO; 4824 } 4825 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4826 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4827 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4828 acb->doneq_index = 0; 4829 acb->in_doorbell = 0; 4830 acb->out_doorbell = 0; 4831 acb->rid[0] = rid0; 4832 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /*clear interrupt*/ 4833 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, ARCMSR_HBEMU_DOORBELL_SYNC); /* synchronize doorbell to 0 */ 4834 } 4835 break; 4836 case ACB_ADAPTER_TYPE_F: { 4837 u_int32_t rid0 = PCIR_BAR(0); 4838 vm_offset_t mem_base0; 4839 unsigned long host_buffer_dma; 4840 4841 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4842 if(acb->sys_res_arcmsr[0] == NULL) { 4843 arcmsr_free_resource(acb); 4844 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4845 return ENOMEM; 4846 } 4847 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4848 arcmsr_free_resource(acb); 4849 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4850 return ENXIO; 4851 } 4852 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4853 if(mem_base0 == 0) { 4854 arcmsr_free_resource(acb); 4855 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4856 return ENXIO; 4857 } 4858 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4859 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4860 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4861 acb->doneq_index = 0; 4862 acb->in_doorbell = 0; 4863 acb->out_doorbell = 0; 4864 acb->rid[0] = rid0; 4865 CHIP_REG_WRITE32(HBF_MessageUnit, 0, host_int_status, 0); /*clear interrupt*/ 4866 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, ARCMSR_HBEMU_DOORBELL_SYNC); /* synchronize doorbell to 0 */ 4867 arcmsr_wait_firmware_ready(acb); 4868 host_buffer_dma = acb->completeQ_phys + COMPLETION_Q_POOL_SIZE; 4869 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, (u_int32_t)(host_buffer_dma | 1)); /* host buffer low addr, bit0:1 all buffer active */ 4870 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr1, (u_int32_t)((host_buffer_dma >> 16) >> 16));/* host buffer high addr */ 4871 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, ARCMSR_HBFMU_DOORBELL_SYNC1); /* set host buffer physical address */ 4872 } 4873 break; 4874 } 4875 if(acb->acb_flags & ACB_F_MAPFREESRB_FAILD) { 4876 arcmsr_free_resource(acb); 4877 printf("arcmsr%d: map free srb failure!\n", device_get_unit(dev)); 4878 return ENXIO; 4879 } 4880 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_RQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ); 4881 acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER; 4882 /* 4883 ******************************************************************** 4884 ** init raid volume state 4885 ******************************************************************** 4886 */ 4887 for(i=0; i < ARCMSR_MAX_TARGETID; i++) { 4888 for(j=0; j < ARCMSR_MAX_TARGETLUN; j++) { 4889 acb->devstate[i][j] = ARECA_RAID_GONE; 4890 } 4891 } 4892 arcmsr_iop_init(acb); 4893 return(0); 4894 } 4895 4896 static int arcmsr_setup_msix(struct AdapterControlBlock *acb) 4897 { 4898 int i; 4899 4900 for (i = 0; i < acb->msix_vectors; i++) { 4901 acb->irq_id[i] = 1 + i; 4902 acb->irqres[i] = bus_alloc_resource_any(acb->pci_dev, 4903 SYS_RES_IRQ, &acb->irq_id[i], RF_ACTIVE); 4904 if (acb->irqres[i] == NULL) { 4905 printf("arcmsr: Can't allocate MSI-X resource\n"); 4906 goto irq_alloc_failed; 4907 } 4908 if (bus_setup_intr(acb->pci_dev, acb->irqres[i], 4909 INTR_MPSAFE | INTR_TYPE_CAM, NULL, arcmsr_intr_handler, 4910 acb, &acb->ih[i])) { 4911 printf("arcmsr: Cannot set up MSI-X interrupt handler\n"); 4912 goto irq_alloc_failed; 4913 } 4914 } 4915 printf("arcmsr: MSI-X INT enabled\n"); 4916 acb->acb_flags |= ACB_F_MSIX_ENABLED; 4917 return TRUE; 4918 4919 irq_alloc_failed: 4920 arcmsr_teardown_intr(acb->pci_dev, acb); 4921 return FALSE; 4922 } 4923 4924 /* 4925 ************************************************************************ 4926 ************************************************************************ 4927 */ 4928 static int arcmsr_attach(device_t dev) 4929 { 4930 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 4931 u_int32_t unit=device_get_unit(dev); 4932 struct ccb_setasync csa; 4933 struct cam_devq *devq; /* Device Queue to use for this SIM */ 4934 struct resource *irqres; 4935 4936 if(acb == NULL) { 4937 printf("arcmsr%d: cannot allocate softc\n", unit); 4938 return (ENOMEM); 4939 } 4940 arcmsr_mutex_init(acb); 4941 acb->pci_dev = dev; 4942 acb->pci_unit = unit; 4943 if(arcmsr_initialize(dev)) { 4944 printf("arcmsr%d: initialize failure!\n", unit); 4945 goto initialize_failed; 4946 } 4947 /* After setting up the adapter, map our interrupt */ 4948 acb->msix_vectors = ARCMSR_NUM_MSIX_VECTORS; 4949 if (pci_alloc_msix(dev, &acb->msix_vectors) == 0) { 4950 if (arcmsr_setup_msix(acb) == TRUE) 4951 goto irqx; 4952 } 4953 acb->irq_id[0] = 0; 4954 irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &acb->irq_id[0], RF_SHAREABLE | RF_ACTIVE); 4955 if(irqres == NULL || 4956 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, NULL, arcmsr_intr_handler, acb, &acb->ih[0])) { 4957 printf("arcmsr%d: unable to register interrupt handler!\n", unit); 4958 goto setup_intr_failed; 4959 } 4960 acb->irqres[0] = irqres; 4961 irqx: 4962 /* 4963 * Now let the CAM generic SCSI layer find the SCSI devices on 4964 * the bus * start queue to reset to the idle loop. * 4965 * Create device queue of SIM(s) * (MAX_START_JOB - 1) : 4966 * max_sim_transactions 4967 */ 4968 devq = cam_simq_alloc(acb->maxOutstanding); 4969 if(devq == NULL) { 4970 printf("arcmsr%d: cam_simq_alloc failure!\n", unit); 4971 goto simq_alloc_failed; 4972 } 4973 acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, &acb->isr_lock, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq); 4974 if(acb->psim == NULL) { 4975 printf("arcmsr%d: cam_sim_alloc failure!\n", unit); 4976 goto sim_alloc_failed; 4977 } 4978 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 4979 if(xpt_bus_register(acb->psim, dev, 0) != CAM_SUCCESS) { 4980 printf("arcmsr%d: xpt_bus_register failure!\n", unit); 4981 goto xpt_bus_failed; 4982 } 4983 if(xpt_create_path(&acb->ppath, /* periph */ NULL, cam_sim_path(acb->psim), CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 4984 printf("arcmsr%d: xpt_create_path failure!\n", unit); 4985 goto xpt_path_failed; 4986 } 4987 /* 4988 **************************************************** 4989 */ 4990 memset(&csa, 0, sizeof(csa)); 4991 xpt_setup_ccb(&csa.ccb_h, acb->ppath, /*priority*/5); 4992 csa.ccb_h.func_code = XPT_SASYNC_CB; 4993 csa.event_enable = AC_FOUND_DEVICE|AC_LOST_DEVICE; 4994 csa.callback = arcmsr_async; 4995 csa.callback_arg = acb->psim; 4996 xpt_action((union ccb *)&csa); 4997 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 4998 /* Create the control device. */ 4999 acb->ioctl_dev = make_dev(&arcmsr_cdevsw, unit, UID_ROOT, GID_WHEEL /* GID_OPERATOR */, S_IRUSR | S_IWUSR, "arcmsr%d", unit); 5000 5001 (void)make_dev_alias(acb->ioctl_dev, "arc%d", unit); 5002 arcmsr_callout_init(&acb->devmap_callout); 5003 callout_reset(&acb->devmap_callout, 60 * hz, arcmsr_polling_devmap, acb); 5004 return (0); 5005 xpt_path_failed: 5006 xpt_bus_deregister(cam_sim_path(acb->psim)); 5007 xpt_bus_failed: 5008 cam_sim_free(acb->psim, /* free_simq */ TRUE); 5009 sim_alloc_failed: 5010 cam_simq_free(devq); 5011 simq_alloc_failed: 5012 arcmsr_teardown_intr(dev, acb); 5013 setup_intr_failed: 5014 arcmsr_free_resource(acb); 5015 initialize_failed: 5016 arcmsr_mutex_destroy(acb); 5017 return ENXIO; 5018 } 5019 5020 /* 5021 ************************************************************************ 5022 ************************************************************************ 5023 */ 5024 static int arcmsr_probe(device_t dev) 5025 { 5026 u_int32_t id; 5027 u_int16_t sub_device_id; 5028 static char buf[256]; 5029 char x_type[]={"unknown"}; 5030 char *type; 5031 int raid6 = 1; 5032 5033 if (pci_get_vendor(dev) != PCI_VENDOR_ID_ARECA) { 5034 return (ENXIO); 5035 } 5036 sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); 5037 switch(id = pci_get_devid(dev)) { 5038 case PCIDevVenIDARC1110: 5039 case PCIDevVenIDARC1200: 5040 case PCIDevVenIDARC1201: 5041 case PCIDevVenIDARC1210: 5042 raid6 = 0; 5043 /*FALLTHRU*/ 5044 case PCIDevVenIDARC1120: 5045 case PCIDevVenIDARC1130: 5046 case PCIDevVenIDARC1160: 5047 case PCIDevVenIDARC1170: 5048 case PCIDevVenIDARC1220: 5049 case PCIDevVenIDARC1230: 5050 case PCIDevVenIDARC1231: 5051 case PCIDevVenIDARC1260: 5052 case PCIDevVenIDARC1261: 5053 case PCIDevVenIDARC1270: 5054 case PCIDevVenIDARC1280: 5055 type = "SATA 3G"; 5056 break; 5057 case PCIDevVenIDARC1212: 5058 case PCIDevVenIDARC1222: 5059 case PCIDevVenIDARC1380: 5060 case PCIDevVenIDARC1381: 5061 case PCIDevVenIDARC1680: 5062 case PCIDevVenIDARC1681: 5063 type = "SAS 3G"; 5064 break; 5065 case PCIDevVenIDARC1880: 5066 case PCIDevVenIDARC1882: 5067 case PCIDevVenIDARC1213: 5068 case PCIDevVenIDARC1223: 5069 if ((sub_device_id == ARECA_SUB_DEV_ID_1883) || 5070 (sub_device_id == ARECA_SUB_DEV_ID_1216) || 5071 (sub_device_id == ARECA_SUB_DEV_ID_1226)) 5072 type = "SAS 12G"; 5073 else 5074 type = "SAS 6G"; 5075 break; 5076 case PCIDevVenIDARC1884: 5077 type = "SAS 12G"; 5078 break; 5079 case PCIDevVenIDARC1886_: 5080 case PCIDevVenIDARC1886: 5081 type = "NVME,SAS-12G,SATA-6G"; 5082 break; 5083 case PCIDevVenIDARC1214: 5084 case PCIDevVenIDARC1203: 5085 type = "SATA 6G"; 5086 break; 5087 default: 5088 type = x_type; 5089 raid6 = 0; 5090 break; 5091 } 5092 if(type == x_type) 5093 return(ENXIO); 5094 sprintf(buf, "Areca %s Host Adapter RAID Controller %s\n%s\n", 5095 type, raid6 ? "(RAID6 capable)" : "", ARCMSR_DRIVER_VERSION); 5096 device_set_desc_copy(dev, buf); 5097 return (BUS_PROBE_DEFAULT); 5098 } 5099 /* 5100 ************************************************************************ 5101 ************************************************************************ 5102 */ 5103 static int arcmsr_shutdown(device_t dev) 5104 { 5105 u_int32_t i; 5106 struct CommandControlBlock *srb; 5107 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 5108 5109 /* stop adapter background rebuild */ 5110 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 5111 /* disable all outbound interrupt */ 5112 arcmsr_disable_allintr(acb); 5113 arcmsr_stop_adapter_bgrb(acb); 5114 arcmsr_flush_adapter_cache(acb); 5115 /* abort all outstanding command */ 5116 acb->acb_flags |= ACB_F_SCSISTOPADAPTER; 5117 acb->acb_flags &= ~ACB_F_IOP_INITED; 5118 if(acb->srboutstandingcount != 0) { 5119 /*clear and abort all outbound posted Q*/ 5120 arcmsr_done4abort_postqueue(acb); 5121 /* talk to iop 331 outstanding command aborted*/ 5122 arcmsr_abort_allcmd(acb); 5123 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 5124 srb = acb->psrb_pool[i]; 5125 if(srb->srb_state == ARCMSR_SRB_START) { 5126 srb->srb_state = ARCMSR_SRB_ABORTED; 5127 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 5128 arcmsr_srb_complete(srb, 1); 5129 } 5130 } 5131 } 5132 acb->srboutstandingcount = 0; 5133 acb->workingsrb_doneindex = 0; 5134 acb->workingsrb_startindex = 0; 5135 acb->pktRequestCount = 0; 5136 acb->pktReturnCount = 0; 5137 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 5138 return (0); 5139 } 5140 /* 5141 ************************************************************************ 5142 ************************************************************************ 5143 */ 5144 static void arcmsr_teardown_intr(device_t dev, struct AdapterControlBlock *acb) 5145 { 5146 int i; 5147 5148 if (acb->acb_flags & ACB_F_MSIX_ENABLED) { 5149 for (i = 0; i < acb->msix_vectors; i++) { 5150 if (acb->ih[i]) 5151 bus_teardown_intr(dev, acb->irqres[i], acb->ih[i]); 5152 if (acb->irqres[i] != NULL) 5153 bus_release_resource(dev, SYS_RES_IRQ, 5154 acb->irq_id[i], acb->irqres[i]); 5155 5156 acb->ih[i] = NULL; 5157 } 5158 pci_release_msi(dev); 5159 } else { 5160 if (acb->ih[0]) 5161 bus_teardown_intr(dev, acb->irqres[0], acb->ih[0]); 5162 if (acb->irqres[0] != NULL) 5163 bus_release_resource(dev, SYS_RES_IRQ, 5164 acb->irq_id[0], acb->irqres[0]); 5165 acb->ih[0] = NULL; 5166 } 5167 5168 } 5169 /* 5170 ************************************************************************ 5171 ************************************************************************ 5172 */ 5173 static int arcmsr_detach(device_t dev) 5174 { 5175 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 5176 int i; 5177 5178 callout_stop(&acb->devmap_callout); 5179 arcmsr_teardown_intr(dev, acb); 5180 arcmsr_shutdown(dev); 5181 arcmsr_free_resource(acb); 5182 for(i=0; (acb->sys_res_arcmsr[i]!=NULL) && (i<2); i++) { 5183 bus_release_resource(dev, SYS_RES_MEMORY, acb->rid[i], acb->sys_res_arcmsr[i]); 5184 } 5185 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 5186 xpt_async(AC_LOST_DEVICE, acb->ppath, NULL); 5187 xpt_free_path(acb->ppath); 5188 xpt_bus_deregister(cam_sim_path(acb->psim)); 5189 cam_sim_free(acb->psim, TRUE); 5190 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 5191 arcmsr_mutex_destroy(acb); 5192 return (0); 5193 } 5194 5195 #ifdef ARCMSR_DEBUG1 5196 static void arcmsr_dump_data(struct AdapterControlBlock *acb) 5197 { 5198 if((acb->pktRequestCount - acb->pktReturnCount) == 0) 5199 return; 5200 printf("Command Request Count =0x%x\n",acb->pktRequestCount); 5201 printf("Command Return Count =0x%x\n",acb->pktReturnCount); 5202 printf("Command (Req-Rtn) Count =0x%x\n",(acb->pktRequestCount - acb->pktReturnCount)); 5203 printf("Queued Command Count =0x%x\n",acb->srboutstandingcount); 5204 } 5205 #endif 5206