1 /* 2 ******************************************************************************** 3 ** OS : FreeBSD 4 ** FILE NAME : arcmsr.c 5 ** BY : Erich Chen, Ching Huang 6 ** Description: SCSI RAID Device Driver for 7 ** ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x) 8 ** SATA/SAS RAID HOST Adapter 9 ******************************************************************************** 10 ******************************************************************************** 11 ** 12 ** SPDX-License-Identifier: BSD-3-Clause 13 ** 14 ** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved. 15 ** 16 ** Redistribution and use in source and binary forms, with or without 17 ** modification, are permitted provided that the following conditions 18 ** are met: 19 ** 1. Redistributions of source code must retain the above copyright 20 ** notice, this list of conditions and the following disclaimer. 21 ** 2. Redistributions in binary form must reproduce the above copyright 22 ** notice, this list of conditions and the following disclaimer in the 23 ** documentation and/or other materials provided with the distribution. 24 ** 3. The name of the author may not be used to endorse or promote products 25 ** derived from this software without specific prior written permission. 26 ** 27 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 28 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 29 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 31 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT 32 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 34 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 36 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 ******************************************************************************** 38 ** History 39 ** 40 ** REV# DATE NAME DESCRIPTION 41 ** 1.00.00.00 03/31/2004 Erich Chen First release 42 ** 1.20.00.02 11/29/2004 Erich Chen bug fix with arcmsr_bus_reset when PHY error 43 ** 1.20.00.03 04/19/2005 Erich Chen add SATA 24 Ports adapter type support 44 ** clean unused function 45 ** 1.20.00.12 09/12/2005 Erich Chen bug fix with abort command handling, 46 ** firmware version check 47 ** and firmware update notify for hardware bug fix 48 ** handling if none zero high part physical address 49 ** of srb resource 50 ** 1.20.00.13 08/18/2006 Erich Chen remove pending srb and report busy 51 ** add iop message xfer 52 ** with scsi pass-through command 53 ** add new device id of sas raid adapters 54 ** code fit for SPARC64 & PPC 55 ** 1.20.00.14 02/05/2007 Erich Chen bug fix for incorrect ccb_h.status report 56 ** and cause g_vfs_done() read write error 57 ** 1.20.00.15 10/10/2007 Erich Chen support new RAID adapter type ARC120x 58 ** 1.20.00.16 10/10/2009 Erich Chen Bug fix for RAID adapter type ARC120x 59 ** bus_dmamem_alloc() with BUS_DMA_ZERO 60 ** 1.20.00.17 07/15/2010 Ching Huang Added support ARC1880 61 ** report CAM_DEV_NOT_THERE instead of CAM_SEL_TIMEOUT when device failed, 62 ** prevent cam_periph_error removing all LUN devices of one Target id 63 ** for any one LUN device failed 64 ** 1.20.00.18 10/14/2010 Ching Huang Fixed "inquiry data fails comparion at DV1 step" 65 ** 10/25/2010 Ching Huang Fixed bad range input in bus_alloc_resource for ADAPTER_TYPE_B 66 ** 1.20.00.19 11/11/2010 Ching Huang Fixed arcmsr driver prevent arcsas support for Areca SAS HBA ARC13x0 67 ** 1.20.00.20 12/08/2010 Ching Huang Avoid calling atomic_set_int function 68 ** 1.20.00.21 02/08/2011 Ching Huang Implement I/O request timeout 69 ** 02/14/2011 Ching Huang Modified pktRequestCount 70 ** 1.20.00.21 03/03/2011 Ching Huang if a command timeout, then wait its ccb back before free it 71 ** 1.20.00.22 07/04/2011 Ching Huang Fixed multiple MTX panic 72 ** 1.20.00.23 10/28/2011 Ching Huang Added TIMEOUT_DELAY in case of too many HDDs need to start 73 ** 1.20.00.23 11/08/2011 Ching Huang Added report device transfer speed 74 ** 1.20.00.23 01/30/2012 Ching Huang Fixed Request requeued and Retrying command 75 ** 1.20.00.24 06/11/2012 Ching Huang Fixed return sense data condition 76 ** 1.20.00.25 08/17/2012 Ching Huang Fixed hotplug device no function on type A adapter 77 ** 1.20.00.26 12/14/2012 Ching Huang Added support ARC1214,1224,1264,1284 78 ** 1.20.00.27 05/06/2013 Ching Huang Fixed out standing cmd full on ARC-12x4 79 ** 1.20.00.28 09/13/2013 Ching Huang Removed recursive mutex in arcmsr_abort_dr_ccbs 80 ** 1.20.00.29 12/18/2013 Ching Huang Change simq allocation number, support ARC1883 81 ** 1.30.00.00 11/30/2015 Ching Huang Added support ARC1203 82 ** 1.40.00.00 07/11/2017 Ching Huang Added support ARC1884 83 ** 1.40.00.01 10/30/2017 Ching Huang Fixed release memory resource 84 ** 1.50.00.00 09/30/2020 Ching Huang Added support ARC-1886, NVMe/SAS/SATA controller 85 ** 1.50.00.01 02/26/2021 Ching Huang Fixed no action of hot plugging device on type_F adapter 86 ** 1.50.00.02 04/16/2021 Ching Huang Fixed scsi command timeout on ARC-1886 when 87 ** scatter-gather count large than some number 88 ****************************************************************************************** 89 */ 90 91 #include <sys/cdefs.h> 92 __FBSDID("$FreeBSD$"); 93 94 #if 0 95 #define ARCMSR_DEBUG1 1 96 #endif 97 #include <sys/param.h> 98 #include <sys/systm.h> 99 #include <sys/malloc.h> 100 #include <sys/kernel.h> 101 #include <sys/bus.h> 102 #include <sys/queue.h> 103 #include <sys/stat.h> 104 #include <sys/devicestat.h> 105 #include <sys/kthread.h> 106 #include <sys/module.h> 107 #include <sys/proc.h> 108 #include <sys/lock.h> 109 #include <sys/sysctl.h> 110 #include <sys/poll.h> 111 #include <sys/ioccom.h> 112 #include <vm/vm.h> 113 #include <vm/vm_param.h> 114 #include <vm/pmap.h> 115 116 #include <isa/rtc.h> 117 118 #include <machine/bus.h> 119 #include <machine/resource.h> 120 #include <machine/atomic.h> 121 #include <sys/conf.h> 122 #include <sys/rman.h> 123 124 #include <cam/cam.h> 125 #include <cam/cam_ccb.h> 126 #include <cam/cam_sim.h> 127 #include <cam/cam_periph.h> 128 #include <cam/cam_xpt_periph.h> 129 #include <cam/cam_xpt_sim.h> 130 #include <cam/cam_debug.h> 131 #include <cam/scsi/scsi_all.h> 132 #include <cam/scsi/scsi_message.h> 133 /* 134 ************************************************************************** 135 ************************************************************************** 136 */ 137 #include <sys/selinfo.h> 138 #include <sys/mutex.h> 139 #include <sys/endian.h> 140 #include <dev/pci/pcivar.h> 141 #include <dev/pci/pcireg.h> 142 143 #define arcmsr_callout_init(a) callout_init(a, /*mpsafe*/1); 144 145 #define ARCMSR_DRIVER_VERSION "arcmsr version 1.50.00.02 2021-04-16" 146 #include <dev/arcmsr/arcmsr.h> 147 /* 148 ************************************************************************** 149 ************************************************************************** 150 */ 151 static void arcmsr_free_srb(struct CommandControlBlock *srb); 152 static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb); 153 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb); 154 static int arcmsr_probe(device_t dev); 155 static int arcmsr_attach(device_t dev); 156 static int arcmsr_detach(device_t dev); 157 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg); 158 static void arcmsr_iop_parking(struct AdapterControlBlock *acb); 159 static int arcmsr_shutdown(device_t dev); 160 static void arcmsr_interrupt(struct AdapterControlBlock *acb); 161 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb); 162 static void arcmsr_free_resource(struct AdapterControlBlock *acb); 163 static void arcmsr_bus_reset(struct AdapterControlBlock *acb); 164 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb); 165 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb); 166 static void arcmsr_iop_init(struct AdapterControlBlock *acb); 167 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb); 168 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, struct QBUFFER *prbuffer); 169 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb); 170 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb); 171 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag); 172 static void arcmsr_iop_reset(struct AdapterControlBlock *acb); 173 static void arcmsr_report_sense_info(struct CommandControlBlock *srb); 174 static void arcmsr_build_srb(struct CommandControlBlock *srb, bus_dma_segment_t *dm_segs, u_int32_t nseg); 175 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb); 176 static int arcmsr_resume(device_t dev); 177 static int arcmsr_suspend(device_t dev); 178 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb); 179 static void arcmsr_polling_devmap(void *arg); 180 static void arcmsr_srb_timeout(void *arg); 181 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb); 182 static void arcmsr_hbe_postqueue_isr(struct AdapterControlBlock *acb); 183 static void arcmsr_hbf_postqueue_isr(struct AdapterControlBlock *acb); 184 static void arcmsr_teardown_intr(device_t dev, struct AdapterControlBlock *acb); 185 #ifdef ARCMSR_DEBUG1 186 static void arcmsr_dump_data(struct AdapterControlBlock *acb); 187 #endif 188 /* 189 ************************************************************************** 190 ************************************************************************** 191 */ 192 static void UDELAY(u_int32_t us) { DELAY(us); } 193 /* 194 ************************************************************************** 195 ************************************************************************** 196 */ 197 static bus_dmamap_callback_t arcmsr_map_free_srb; 198 static bus_dmamap_callback_t arcmsr_execute_srb; 199 /* 200 ************************************************************************** 201 ************************************************************************** 202 */ 203 static d_open_t arcmsr_open; 204 static d_close_t arcmsr_close; 205 static d_ioctl_t arcmsr_ioctl; 206 207 static device_method_t arcmsr_methods[]={ 208 DEVMETHOD(device_probe, arcmsr_probe), 209 DEVMETHOD(device_attach, arcmsr_attach), 210 DEVMETHOD(device_detach, arcmsr_detach), 211 DEVMETHOD(device_shutdown, arcmsr_shutdown), 212 DEVMETHOD(device_suspend, arcmsr_suspend), 213 DEVMETHOD(device_resume, arcmsr_resume), 214 DEVMETHOD_END 215 }; 216 217 static driver_t arcmsr_driver={ 218 "arcmsr", arcmsr_methods, sizeof(struct AdapterControlBlock) 219 }; 220 221 static devclass_t arcmsr_devclass; 222 DRIVER_MODULE(arcmsr, pci, arcmsr_driver, arcmsr_devclass, 0, 0); 223 MODULE_DEPEND(arcmsr, pci, 1, 1, 1); 224 MODULE_DEPEND(arcmsr, cam, 1, 1, 1); 225 #ifndef BUS_DMA_COHERENT 226 #define BUS_DMA_COHERENT 0x04 /* hint: map memory in a coherent way */ 227 #endif 228 static struct cdevsw arcmsr_cdevsw={ 229 .d_version = D_VERSION, 230 .d_open = arcmsr_open, /* open */ 231 .d_close = arcmsr_close, /* close */ 232 .d_ioctl = arcmsr_ioctl, /* ioctl */ 233 .d_name = "arcmsr", /* name */ 234 }; 235 /* 236 ************************************************************************** 237 ************************************************************************** 238 */ 239 static int arcmsr_open(struct cdev *dev, int flags, int fmt, struct thread *proc) 240 { 241 int unit = dev2unit(dev); 242 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit); 243 244 if (acb == NULL) { 245 return ENXIO; 246 } 247 return (0); 248 } 249 /* 250 ************************************************************************** 251 ************************************************************************** 252 */ 253 static int arcmsr_close(struct cdev *dev, int flags, int fmt, struct thread *proc) 254 { 255 int unit = dev2unit(dev); 256 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit); 257 258 if (acb == NULL) { 259 return ENXIO; 260 } 261 return 0; 262 } 263 /* 264 ************************************************************************** 265 ************************************************************************** 266 */ 267 static int arcmsr_ioctl(struct cdev *dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc) 268 { 269 int unit = dev2unit(dev); 270 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit); 271 272 if (acb == NULL) { 273 return ENXIO; 274 } 275 return (arcmsr_iop_ioctlcmd(acb, ioctl_cmd, arg)); 276 } 277 /* 278 ********************************************************************** 279 ********************************************************************** 280 */ 281 static u_int32_t arcmsr_disable_allintr( struct AdapterControlBlock *acb) 282 { 283 u_int32_t intmask_org = 0; 284 285 switch (acb->adapter_type) { 286 case ACB_ADAPTER_TYPE_A: { 287 /* disable all outbound interrupt */ 288 intmask_org = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intmask); /* disable outbound message0 int */ 289 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE); 290 } 291 break; 292 case ACB_ADAPTER_TYPE_B: { 293 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 294 /* disable all outbound interrupt */ 295 intmask_org = READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask) 296 & (~ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); /* disable outbound message0 int */ 297 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask, 0); /* disable all interrupt */ 298 } 299 break; 300 case ACB_ADAPTER_TYPE_C: { 301 /* disable all outbound interrupt */ 302 intmask_org = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask); /* disable outbound message0 int */ 303 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE); 304 } 305 break; 306 case ACB_ADAPTER_TYPE_D: { 307 /* disable all outbound interrupt */ 308 intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); /* disable outbound message0 int */ 309 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE); 310 } 311 break; 312 case ACB_ADAPTER_TYPE_E: 313 case ACB_ADAPTER_TYPE_F: { 314 /* disable all outbound interrupt */ 315 intmask_org = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_mask); /* disable outbound message0 int */ 316 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_mask, intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE); 317 } 318 break; 319 } 320 return (intmask_org); 321 } 322 /* 323 ********************************************************************** 324 ********************************************************************** 325 */ 326 static void arcmsr_enable_allintr( struct AdapterControlBlock *acb, u_int32_t intmask_org) 327 { 328 u_int32_t mask; 329 330 switch (acb->adapter_type) { 331 case ACB_ADAPTER_TYPE_A: { 332 /* enable outbound Post Queue, outbound doorbell Interrupt */ 333 mask = ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE|ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE); 334 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org & mask); 335 acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff; 336 } 337 break; 338 case ACB_ADAPTER_TYPE_B: { 339 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 340 /* enable ARCMSR_IOP2DRV_MESSAGE_CMD_DONE */ 341 mask = (ARCMSR_IOP2DRV_DATA_WRITE_OK|ARCMSR_IOP2DRV_DATA_READ_OK|ARCMSR_IOP2DRV_CDB_DONE|ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); 342 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask, intmask_org | mask); /*1=interrupt enable, 0=interrupt disable*/ 343 acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f; 344 } 345 break; 346 case ACB_ADAPTER_TYPE_C: { 347 /* enable outbound Post Queue, outbound doorbell Interrupt */ 348 mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK); 349 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org & mask); 350 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f; 351 } 352 break; 353 case ACB_ADAPTER_TYPE_D: { 354 /* enable outbound Post Queue, outbound doorbell Interrupt */ 355 mask = ARCMSR_HBDMU_ALL_INT_ENABLE; 356 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | mask); 357 CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); 358 acb->outbound_int_enable = mask; 359 } 360 break; 361 case ACB_ADAPTER_TYPE_E: 362 case ACB_ADAPTER_TYPE_F: { 363 /* enable outbound Post Queue, outbound doorbell Interrupt */ 364 mask = ~(ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR); 365 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_mask, intmask_org & mask); 366 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f; 367 } 368 break; 369 } 370 } 371 /* 372 ********************************************************************** 373 ********************************************************************** 374 */ 375 static u_int8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb) 376 { 377 u_int32_t Index; 378 u_int8_t Retries = 0x00; 379 380 do { 381 for(Index=0; Index < 100; Index++) { 382 if(CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { 383 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);/*clear interrupt*/ 384 return TRUE; 385 } 386 UDELAY(10000); 387 }/*max 1 seconds*/ 388 }while(Retries++ < 20);/*max 20 sec*/ 389 return (FALSE); 390 } 391 /* 392 ********************************************************************** 393 ********************************************************************** 394 */ 395 static u_int8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb) 396 { 397 u_int32_t Index; 398 u_int8_t Retries = 0x00; 399 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 400 401 do { 402 for(Index=0; Index < 100; Index++) { 403 if(READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) { 404 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt*/ 405 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 406 return TRUE; 407 } 408 UDELAY(10000); 409 }/*max 1 seconds*/ 410 }while(Retries++ < 20);/*max 20 sec*/ 411 return (FALSE); 412 } 413 /* 414 ********************************************************************** 415 ********************************************************************** 416 */ 417 static u_int8_t arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock *acb) 418 { 419 u_int32_t Index; 420 u_int8_t Retries = 0x00; 421 422 do { 423 for(Index=0; Index < 100; Index++) { 424 if(CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 425 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);/*clear interrupt*/ 426 return TRUE; 427 } 428 UDELAY(10000); 429 }/*max 1 seconds*/ 430 }while(Retries++ < 20);/*max 20 sec*/ 431 return (FALSE); 432 } 433 /* 434 ********************************************************************** 435 ********************************************************************** 436 */ 437 static u_int8_t arcmsr_hbd_wait_msgint_ready(struct AdapterControlBlock *acb) 438 { 439 u_int32_t Index; 440 u_int8_t Retries = 0x00; 441 442 do { 443 for(Index=0; Index < 100; Index++) { 444 if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) { 445 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);/*clear interrupt*/ 446 return TRUE; 447 } 448 UDELAY(10000); 449 }/*max 1 seconds*/ 450 }while(Retries++ < 20);/*max 20 sec*/ 451 return (FALSE); 452 } 453 /* 454 ********************************************************************** 455 ********************************************************************** 456 */ 457 static u_int8_t arcmsr_hbe_wait_msgint_ready(struct AdapterControlBlock *acb) 458 { 459 u_int32_t Index, read_doorbell; 460 u_int8_t Retries = 0x00; 461 462 do { 463 for(Index=0; Index < 100; Index++) { 464 read_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell); 465 if((read_doorbell ^ acb->in_doorbell) & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) { 466 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0);/*clear interrupt*/ 467 acb->in_doorbell = read_doorbell; 468 return TRUE; 469 } 470 UDELAY(10000); 471 }/*max 1 seconds*/ 472 }while(Retries++ < 20);/*max 20 sec*/ 473 return (FALSE); 474 } 475 /* 476 ************************************************************************ 477 ************************************************************************ 478 */ 479 static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb) 480 { 481 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 482 483 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 484 do { 485 if(arcmsr_hba_wait_msgint_ready(acb)) { 486 break; 487 } else { 488 retry_count--; 489 } 490 }while(retry_count != 0); 491 } 492 /* 493 ************************************************************************ 494 ************************************************************************ 495 */ 496 static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb) 497 { 498 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 499 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 500 501 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_FLUSH_CACHE); 502 do { 503 if(arcmsr_hbb_wait_msgint_ready(acb)) { 504 break; 505 } else { 506 retry_count--; 507 } 508 }while(retry_count != 0); 509 } 510 /* 511 ************************************************************************ 512 ************************************************************************ 513 */ 514 static void arcmsr_flush_hbc_cache(struct AdapterControlBlock *acb) 515 { 516 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 517 518 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 519 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 520 do { 521 if(arcmsr_hbc_wait_msgint_ready(acb)) { 522 break; 523 } else { 524 retry_count--; 525 } 526 }while(retry_count != 0); 527 } 528 /* 529 ************************************************************************ 530 ************************************************************************ 531 */ 532 static void arcmsr_flush_hbd_cache(struct AdapterControlBlock *acb) 533 { 534 int retry_count = 30; /* enlarge wait flush adapter cache time: 10 minute */ 535 536 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 537 do { 538 if(arcmsr_hbd_wait_msgint_ready(acb)) { 539 break; 540 } else { 541 retry_count--; 542 } 543 }while(retry_count != 0); 544 } 545 /* 546 ************************************************************************ 547 ************************************************************************ 548 */ 549 static void arcmsr_flush_hbe_cache(struct AdapterControlBlock *acb) 550 { 551 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 552 553 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 554 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 555 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 556 do { 557 if(arcmsr_hbe_wait_msgint_ready(acb)) { 558 break; 559 } else { 560 retry_count--; 561 } 562 }while(retry_count != 0); 563 } 564 /* 565 ************************************************************************ 566 ************************************************************************ 567 */ 568 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb) 569 { 570 switch (acb->adapter_type) { 571 case ACB_ADAPTER_TYPE_A: { 572 arcmsr_flush_hba_cache(acb); 573 } 574 break; 575 case ACB_ADAPTER_TYPE_B: { 576 arcmsr_flush_hbb_cache(acb); 577 } 578 break; 579 case ACB_ADAPTER_TYPE_C: { 580 arcmsr_flush_hbc_cache(acb); 581 } 582 break; 583 case ACB_ADAPTER_TYPE_D: { 584 arcmsr_flush_hbd_cache(acb); 585 } 586 break; 587 case ACB_ADAPTER_TYPE_E: 588 case ACB_ADAPTER_TYPE_F: { 589 arcmsr_flush_hbe_cache(acb); 590 } 591 break; 592 } 593 } 594 /* 595 ******************************************************************************* 596 ******************************************************************************* 597 */ 598 static int arcmsr_suspend(device_t dev) 599 { 600 struct AdapterControlBlock *acb = device_get_softc(dev); 601 602 /* flush controller */ 603 arcmsr_iop_parking(acb); 604 /* disable all outbound interrupt */ 605 arcmsr_disable_allintr(acb); 606 return(0); 607 } 608 /* 609 ******************************************************************************* 610 ******************************************************************************* 611 */ 612 static int arcmsr_resume(device_t dev) 613 { 614 struct AdapterControlBlock *acb = device_get_softc(dev); 615 616 arcmsr_iop_init(acb); 617 return(0); 618 } 619 /* 620 ********************************************************************************* 621 ********************************************************************************* 622 */ 623 static void arcmsr_async(void *cb_arg, u_int32_t code, struct cam_path *path, void *arg) 624 { 625 struct AdapterControlBlock *acb; 626 u_int8_t target_id, target_lun; 627 struct cam_sim *sim; 628 629 sim = (struct cam_sim *) cb_arg; 630 acb =(struct AdapterControlBlock *) cam_sim_softc(sim); 631 switch (code) { 632 case AC_LOST_DEVICE: 633 target_id = xpt_path_target_id(path); 634 target_lun = xpt_path_lun_id(path); 635 if((target_id > ARCMSR_MAX_TARGETID) || (target_lun > ARCMSR_MAX_TARGETLUN)) { 636 break; 637 } 638 // printf("%s:scsi id=%d lun=%d device lost \n", device_get_name(acb->pci_dev), target_id, target_lun); 639 break; 640 default: 641 break; 642 } 643 } 644 /* 645 ********************************************************************** 646 ********************************************************************** 647 */ 648 static void arcmsr_report_sense_info(struct CommandControlBlock *srb) 649 { 650 union ccb *pccb = srb->pccb; 651 652 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 653 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 654 if(pccb->csio.sense_len) { 655 memset(&pccb->csio.sense_data, 0, sizeof(pccb->csio.sense_data)); 656 memcpy(&pccb->csio.sense_data, srb->arcmsr_cdb.SenseData, 657 get_min(sizeof(struct SENSE_DATA), sizeof(pccb->csio.sense_data))); 658 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); /* Valid,ErrorCode */ 659 pccb->ccb_h.status |= CAM_AUTOSNS_VALID; 660 } 661 } 662 /* 663 ********************************************************************* 664 ********************************************************************* 665 */ 666 static void arcmsr_abort_hba_allcmd(struct AdapterControlBlock *acb) 667 { 668 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 669 if(!arcmsr_hba_wait_msgint_ready(acb)) { 670 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 671 } 672 } 673 /* 674 ********************************************************************* 675 ********************************************************************* 676 */ 677 static void arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb) 678 { 679 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 680 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_ABORT_CMD); 681 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 682 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 683 } 684 } 685 /* 686 ********************************************************************* 687 ********************************************************************* 688 */ 689 static void arcmsr_abort_hbc_allcmd(struct AdapterControlBlock *acb) 690 { 691 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 692 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 693 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 694 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 695 } 696 } 697 /* 698 ********************************************************************* 699 ********************************************************************* 700 */ 701 static void arcmsr_abort_hbd_allcmd(struct AdapterControlBlock *acb) 702 { 703 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 704 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 705 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 706 } 707 } 708 /* 709 ********************************************************************* 710 ********************************************************************* 711 */ 712 static void arcmsr_abort_hbe_allcmd(struct AdapterControlBlock *acb) 713 { 714 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 715 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 716 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 717 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 718 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 719 } 720 } 721 /* 722 ********************************************************************* 723 ********************************************************************* 724 */ 725 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb) 726 { 727 switch (acb->adapter_type) { 728 case ACB_ADAPTER_TYPE_A: { 729 arcmsr_abort_hba_allcmd(acb); 730 } 731 break; 732 case ACB_ADAPTER_TYPE_B: { 733 arcmsr_abort_hbb_allcmd(acb); 734 } 735 break; 736 case ACB_ADAPTER_TYPE_C: { 737 arcmsr_abort_hbc_allcmd(acb); 738 } 739 break; 740 case ACB_ADAPTER_TYPE_D: { 741 arcmsr_abort_hbd_allcmd(acb); 742 } 743 break; 744 case ACB_ADAPTER_TYPE_E: 745 case ACB_ADAPTER_TYPE_F: { 746 arcmsr_abort_hbe_allcmd(acb); 747 } 748 break; 749 } 750 } 751 /* 752 ********************************************************************** 753 ********************************************************************** 754 */ 755 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag) 756 { 757 struct AdapterControlBlock *acb = srb->acb; 758 union ccb *pccb = srb->pccb; 759 760 if(srb->srb_flags & SRB_FLAG_TIMER_START) 761 callout_stop(&srb->ccb_callout); 762 if((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 763 bus_dmasync_op_t op; 764 765 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 766 op = BUS_DMASYNC_POSTREAD; 767 } else { 768 op = BUS_DMASYNC_POSTWRITE; 769 } 770 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op); 771 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap); 772 } 773 if(stand_flag == 1) { 774 atomic_subtract_int(&acb->srboutstandingcount, 1); 775 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) && ( 776 acb->srboutstandingcount < (acb->maxOutstanding -10))) { 777 acb->acb_flags &= ~ACB_F_CAM_DEV_QFRZN; 778 pccb->ccb_h.status |= CAM_RELEASE_SIMQ; 779 } 780 } 781 if(srb->srb_state != ARCMSR_SRB_TIMEOUT) 782 arcmsr_free_srb(srb); 783 acb->pktReturnCount++; 784 xpt_done(pccb); 785 } 786 /* 787 ************************************************************************** 788 ************************************************************************** 789 */ 790 static void arcmsr_report_srb_state(struct AdapterControlBlock *acb, struct CommandControlBlock *srb, u_int16_t error) 791 { 792 int target, lun; 793 794 target = srb->pccb->ccb_h.target_id; 795 lun = srb->pccb->ccb_h.target_lun; 796 if(error == FALSE) { 797 if(acb->devstate[target][lun] == ARECA_RAID_GONE) { 798 acb->devstate[target][lun] = ARECA_RAID_GOOD; 799 } 800 srb->pccb->ccb_h.status |= CAM_REQ_CMP; 801 arcmsr_srb_complete(srb, 1); 802 } else { 803 switch(srb->arcmsr_cdb.DeviceStatus) { 804 case ARCMSR_DEV_SELECT_TIMEOUT: { 805 if(acb->devstate[target][lun] == ARECA_RAID_GOOD) { 806 printf( "arcmsr%d: Target=%x, Lun=%x, selection timeout, raid volume was lost\n", acb->pci_unit, target, lun); 807 } 808 acb->devstate[target][lun] = ARECA_RAID_GONE; 809 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 810 arcmsr_srb_complete(srb, 1); 811 } 812 break; 813 case ARCMSR_DEV_ABORTED: 814 case ARCMSR_DEV_INIT_FAIL: { 815 acb->devstate[target][lun] = ARECA_RAID_GONE; 816 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 817 arcmsr_srb_complete(srb, 1); 818 } 819 break; 820 case SCSISTAT_CHECK_CONDITION: { 821 acb->devstate[target][lun] = ARECA_RAID_GOOD; 822 arcmsr_report_sense_info(srb); 823 arcmsr_srb_complete(srb, 1); 824 } 825 break; 826 default: 827 printf("arcmsr%d: scsi id=%d lun=%d isr got command error done,but got unknown DeviceStatus=0x%x \n" 828 , acb->pci_unit, target, lun ,srb->arcmsr_cdb.DeviceStatus); 829 acb->devstate[target][lun] = ARECA_RAID_GONE; 830 srb->pccb->ccb_h.status |= CAM_UNCOR_PARITY; 831 /*unknown error or crc error just for retry*/ 832 arcmsr_srb_complete(srb, 1); 833 break; 834 } 835 } 836 } 837 /* 838 ************************************************************************** 839 ************************************************************************** 840 */ 841 static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, u_int32_t flag_srb, u_int16_t error) 842 { 843 struct CommandControlBlock *srb; 844 845 /* check if command done with no error*/ 846 switch (acb->adapter_type) { 847 case ACB_ADAPTER_TYPE_A: 848 case ACB_ADAPTER_TYPE_B: 849 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 850 break; 851 case ACB_ADAPTER_TYPE_C: 852 case ACB_ADAPTER_TYPE_D: 853 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0)); /*frame must be 32 bytes aligned*/ 854 break; 855 case ACB_ADAPTER_TYPE_E: 856 case ACB_ADAPTER_TYPE_F: 857 srb = acb->psrb_pool[flag_srb]; 858 break; 859 default: 860 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 861 break; 862 } 863 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 864 if(srb->srb_state == ARCMSR_SRB_TIMEOUT) { 865 arcmsr_free_srb(srb); 866 printf("arcmsr%d: srb='%p' return srb has been timeouted\n", acb->pci_unit, srb); 867 return; 868 } 869 printf("arcmsr%d: return srb has been completed\n" 870 "srb='%p' srb_state=0x%x outstanding srb count=%d \n", 871 acb->pci_unit, srb, srb->srb_state, acb->srboutstandingcount); 872 return; 873 } 874 arcmsr_report_srb_state(acb, srb, error); 875 } 876 /* 877 ************************************************************************** 878 ************************************************************************** 879 */ 880 static void arcmsr_srb_timeout(void *arg) 881 { 882 struct CommandControlBlock *srb = (struct CommandControlBlock *)arg; 883 struct AdapterControlBlock *acb; 884 int target, lun; 885 u_int8_t cmd; 886 887 target = srb->pccb->ccb_h.target_id; 888 lun = srb->pccb->ccb_h.target_lun; 889 acb = srb->acb; 890 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 891 if(srb->srb_state == ARCMSR_SRB_START) 892 { 893 cmd = scsiio_cdb_ptr(&srb->pccb->csio)[0]; 894 srb->srb_state = ARCMSR_SRB_TIMEOUT; 895 srb->pccb->ccb_h.status |= CAM_CMD_TIMEOUT; 896 arcmsr_srb_complete(srb, 1); 897 printf("arcmsr%d: scsi id %d lun %d cmd=0x%x srb='%p' ccb command time out!\n", 898 acb->pci_unit, target, lun, cmd, srb); 899 } 900 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 901 #ifdef ARCMSR_DEBUG1 902 arcmsr_dump_data(acb); 903 #endif 904 } 905 906 /* 907 ********************************************************************** 908 ********************************************************************** 909 */ 910 static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb) 911 { 912 int i=0; 913 u_int32_t flag_srb; 914 u_int16_t error; 915 916 switch (acb->adapter_type) { 917 case ACB_ADAPTER_TYPE_A: { 918 u_int32_t outbound_intstatus; 919 920 /*clear and abort all outbound posted Q*/ 921 outbound_intstatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 922 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);/*clear interrupt*/ 923 while(((flag_srb=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_queueport)) != 0xFFFFFFFF) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) { 924 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 925 arcmsr_drain_donequeue(acb, flag_srb, error); 926 } 927 } 928 break; 929 case ACB_ADAPTER_TYPE_B: { 930 struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu; 931 932 /*clear all outbound posted Q*/ 933 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */ 934 for(i=0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) { 935 if((flag_srb = phbbmu->done_qbuffer[i]) != 0) { 936 phbbmu->done_qbuffer[i] = 0; 937 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 938 arcmsr_drain_donequeue(acb, flag_srb, error); 939 } 940 phbbmu->post_qbuffer[i] = 0; 941 }/*drain reply FIFO*/ 942 phbbmu->doneq_index = 0; 943 phbbmu->postq_index = 0; 944 } 945 break; 946 case ACB_ADAPTER_TYPE_C: { 947 while((CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) { 948 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 949 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 950 arcmsr_drain_donequeue(acb, flag_srb, error); 951 } 952 } 953 break; 954 case ACB_ADAPTER_TYPE_D: 955 arcmsr_hbd_postqueue_isr(acb); 956 break; 957 case ACB_ADAPTER_TYPE_E: 958 arcmsr_hbe_postqueue_isr(acb); 959 break; 960 case ACB_ADAPTER_TYPE_F: 961 arcmsr_hbf_postqueue_isr(acb); 962 break; 963 } 964 } 965 /* 966 **************************************************************************** 967 **************************************************************************** 968 */ 969 static void arcmsr_iop_reset(struct AdapterControlBlock *acb) 970 { 971 struct CommandControlBlock *srb; 972 u_int32_t intmask_org; 973 u_int32_t i=0; 974 975 if(acb->srboutstandingcount>0) { 976 /* disable all outbound interrupt */ 977 intmask_org = arcmsr_disable_allintr(acb); 978 /*clear and abort all outbound posted Q*/ 979 arcmsr_done4abort_postqueue(acb); 980 /* talk to iop 331 outstanding command aborted*/ 981 arcmsr_abort_allcmd(acb); 982 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 983 srb = acb->psrb_pool[i]; 984 if(srb->srb_state == ARCMSR_SRB_START) { 985 srb->srb_state = ARCMSR_SRB_ABORTED; 986 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 987 arcmsr_srb_complete(srb, 1); 988 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p' aborted\n" 989 , acb->pci_unit, srb->pccb->ccb_h.target_id 990 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 991 } 992 } 993 /* enable all outbound interrupt */ 994 arcmsr_enable_allintr(acb, intmask_org); 995 } 996 acb->srboutstandingcount = 0; 997 acb->workingsrb_doneindex = 0; 998 acb->workingsrb_startindex = 0; 999 acb->pktRequestCount = 0; 1000 acb->pktReturnCount = 0; 1001 } 1002 /* 1003 ********************************************************************** 1004 ********************************************************************** 1005 */ 1006 static void arcmsr_build_srb(struct CommandControlBlock *srb, 1007 bus_dma_segment_t *dm_segs, u_int32_t nseg) 1008 { 1009 struct ARCMSR_CDB *arcmsr_cdb = &srb->arcmsr_cdb; 1010 u_int8_t *psge = (u_int8_t *)&arcmsr_cdb->u; 1011 u_int32_t address_lo, address_hi; 1012 union ccb *pccb = srb->pccb; 1013 struct ccb_scsiio *pcsio = &pccb->csio; 1014 u_int32_t arccdbsize = 0x30; 1015 1016 memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB)); 1017 arcmsr_cdb->Bus = 0; 1018 arcmsr_cdb->TargetID = pccb->ccb_h.target_id; 1019 arcmsr_cdb->LUN = pccb->ccb_h.target_lun; 1020 arcmsr_cdb->Function = 1; 1021 arcmsr_cdb->CdbLength = (u_int8_t)pcsio->cdb_len; 1022 bcopy(scsiio_cdb_ptr(pcsio), arcmsr_cdb->Cdb, pcsio->cdb_len); 1023 if(nseg != 0) { 1024 struct AdapterControlBlock *acb = srb->acb; 1025 bus_dmasync_op_t op; 1026 u_int32_t length, i, cdb_sgcount = 0; 1027 1028 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1029 op = BUS_DMASYNC_PREREAD; 1030 } else { 1031 op = BUS_DMASYNC_PREWRITE; 1032 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE; 1033 srb->srb_flags |= SRB_FLAG_WRITE; 1034 } 1035 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op); 1036 for(i=0; i < nseg; i++) { 1037 /* Get the physical address of the current data pointer */ 1038 length = arcmsr_htole32(dm_segs[i].ds_len); 1039 address_lo = arcmsr_htole32(dma_addr_lo32(dm_segs[i].ds_addr)); 1040 address_hi = arcmsr_htole32(dma_addr_hi32(dm_segs[i].ds_addr)); 1041 if(address_hi == 0) { 1042 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge; 1043 pdma_sg->address = address_lo; 1044 pdma_sg->length = length; 1045 psge += sizeof(struct SG32ENTRY); 1046 arccdbsize += sizeof(struct SG32ENTRY); 1047 } else { 1048 u_int32_t sg64s_size = 0, tmplength = length; 1049 1050 while(1) { 1051 u_int64_t span4G, length0; 1052 struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge; 1053 1054 span4G = (u_int64_t)address_lo + tmplength; 1055 pdma_sg->addresshigh = address_hi; 1056 pdma_sg->address = address_lo; 1057 if(span4G > 0x100000000) { 1058 /*see if cross 4G boundary*/ 1059 length0 = 0x100000000-address_lo; 1060 pdma_sg->length = (u_int32_t)length0 | IS_SG64_ADDR; 1061 address_hi = address_hi+1; 1062 address_lo = 0; 1063 tmplength = tmplength - (u_int32_t)length0; 1064 sg64s_size += sizeof(struct SG64ENTRY); 1065 psge += sizeof(struct SG64ENTRY); 1066 cdb_sgcount++; 1067 } else { 1068 pdma_sg->length = tmplength | IS_SG64_ADDR; 1069 sg64s_size += sizeof(struct SG64ENTRY); 1070 psge += sizeof(struct SG64ENTRY); 1071 break; 1072 } 1073 } 1074 arccdbsize += sg64s_size; 1075 } 1076 cdb_sgcount++; 1077 } 1078 arcmsr_cdb->sgcount = (u_int8_t)cdb_sgcount; 1079 arcmsr_cdb->DataLength = pcsio->dxfer_len; 1080 if( arccdbsize > 256) { 1081 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE; 1082 } 1083 } else { 1084 arcmsr_cdb->DataLength = 0; 1085 } 1086 srb->arc_cdb_size = arccdbsize; 1087 arcmsr_cdb->msgPages = (arccdbsize/256) + ((arccdbsize % 256) ? 1 : 0); 1088 } 1089 /* 1090 ************************************************************************** 1091 ************************************************************************** 1092 */ 1093 static void arcmsr_post_srb(struct AdapterControlBlock *acb, struct CommandControlBlock *srb) 1094 { 1095 u_int32_t cdb_phyaddr_low = (u_int32_t) srb->cdb_phyaddr_low; 1096 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&srb->arcmsr_cdb; 1097 1098 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, (srb->srb_flags & SRB_FLAG_WRITE) ? BUS_DMASYNC_POSTWRITE:BUS_DMASYNC_POSTREAD); 1099 atomic_add_int(&acb->srboutstandingcount, 1); 1100 srb->srb_state = ARCMSR_SRB_START; 1101 1102 switch (acb->adapter_type) { 1103 case ACB_ADAPTER_TYPE_A: { 1104 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { 1105 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low|ARCMSR_SRBPOST_FLAG_SGL_BSIZE); 1106 } else { 1107 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low); 1108 } 1109 } 1110 break; 1111 case ACB_ADAPTER_TYPE_B: { 1112 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1113 int ending_index, index; 1114 1115 index = phbbmu->postq_index; 1116 ending_index = ((index+1) % ARCMSR_MAX_HBB_POSTQUEUE); 1117 phbbmu->post_qbuffer[ending_index] = 0; 1118 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { 1119 phbbmu->post_qbuffer[index] = cdb_phyaddr_low | ARCMSR_SRBPOST_FLAG_SGL_BSIZE; 1120 } else { 1121 phbbmu->post_qbuffer[index] = cdb_phyaddr_low; 1122 } 1123 index++; 1124 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 1125 phbbmu->postq_index = index; 1126 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_CDB_POSTED); 1127 } 1128 break; 1129 case ACB_ADAPTER_TYPE_C: { 1130 u_int32_t ccb_post_stamp, arc_cdb_size, cdb_phyaddr_hi32; 1131 1132 arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size; 1133 ccb_post_stamp = (cdb_phyaddr_low | ((arc_cdb_size-1) >> 6) | 1); 1134 cdb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high; 1135 if(cdb_phyaddr_hi32) 1136 { 1137 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_high, cdb_phyaddr_hi32); 1138 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp); 1139 } 1140 else 1141 { 1142 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp); 1143 } 1144 } 1145 break; 1146 case ACB_ADAPTER_TYPE_D: { 1147 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1148 u_int16_t index_stripped; 1149 u_int16_t postq_index; 1150 struct InBound_SRB *pinbound_srb; 1151 1152 ARCMSR_LOCK_ACQUIRE(&acb->postDone_lock); 1153 postq_index = phbdmu->postq_index; 1154 pinbound_srb = (struct InBound_SRB *)&phbdmu->post_qbuffer[postq_index & 0xFF]; 1155 pinbound_srb->addressHigh = srb->cdb_phyaddr_high; 1156 pinbound_srb->addressLow = srb->cdb_phyaddr_low; 1157 pinbound_srb->length = srb->arc_cdb_size >> 2; 1158 arcmsr_cdb->Context = srb->cdb_phyaddr_low; 1159 if (postq_index & 0x4000) { 1160 index_stripped = postq_index & 0xFF; 1161 index_stripped += 1; 1162 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1163 phbdmu->postq_index = index_stripped ? (index_stripped | 0x4000) : index_stripped; 1164 } else { 1165 index_stripped = postq_index; 1166 index_stripped += 1; 1167 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1168 phbdmu->postq_index = index_stripped ? index_stripped : (index_stripped | 0x4000); 1169 } 1170 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inboundlist_write_pointer, postq_index); 1171 ARCMSR_LOCK_RELEASE(&acb->postDone_lock); 1172 } 1173 break; 1174 case ACB_ADAPTER_TYPE_E: { 1175 u_int32_t ccb_post_stamp, arc_cdb_size; 1176 1177 arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size; 1178 ccb_post_stamp = (srb->smid | ((arc_cdb_size-1) >> 6)); 1179 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_queueport_high, 0); 1180 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_queueport_low, ccb_post_stamp); 1181 } 1182 break; 1183 case ACB_ADAPTER_TYPE_F: { 1184 u_int32_t ccb_post_stamp, arc_cdb_size; 1185 1186 if (srb->arc_cdb_size <= 0x300) 1187 arc_cdb_size = (srb->arc_cdb_size - 1) >> 6 | 1; 1188 else { 1189 arc_cdb_size = ((srb->arc_cdb_size + 0xff) >> 8) + 2; 1190 if (arc_cdb_size > 0xF) 1191 arc_cdb_size = 0xF; 1192 arc_cdb_size = (arc_cdb_size << 1) | 1; 1193 } 1194 ccb_post_stamp = (srb->smid | arc_cdb_size); 1195 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_queueport_high, 0); 1196 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_queueport_low, ccb_post_stamp); 1197 } 1198 break; 1199 } 1200 } 1201 /* 1202 ************************************************************************ 1203 ************************************************************************ 1204 */ 1205 static struct QBUFFER *arcmsr_get_iop_rqbuffer( struct AdapterControlBlock *acb) 1206 { 1207 struct QBUFFER *qbuffer=NULL; 1208 1209 switch (acb->adapter_type) { 1210 case ACB_ADAPTER_TYPE_A: { 1211 struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu; 1212 1213 qbuffer = (struct QBUFFER *)&phbamu->message_rbuffer; 1214 } 1215 break; 1216 case ACB_ADAPTER_TYPE_B: { 1217 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1218 1219 qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_rbuffer; 1220 } 1221 break; 1222 case ACB_ADAPTER_TYPE_C: { 1223 struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu; 1224 1225 qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer; 1226 } 1227 break; 1228 case ACB_ADAPTER_TYPE_D: { 1229 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1230 1231 qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_rbuffer; 1232 } 1233 break; 1234 case ACB_ADAPTER_TYPE_E: { 1235 struct HBE_MessageUnit *phbcmu = (struct HBE_MessageUnit *)acb->pmu; 1236 1237 qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer; 1238 } 1239 break; 1240 case ACB_ADAPTER_TYPE_F: 1241 qbuffer = (struct QBUFFER *)acb->message_rbuffer; 1242 break; 1243 } 1244 return(qbuffer); 1245 } 1246 /* 1247 ************************************************************************ 1248 ************************************************************************ 1249 */ 1250 static struct QBUFFER *arcmsr_get_iop_wqbuffer( struct AdapterControlBlock *acb) 1251 { 1252 struct QBUFFER *qbuffer = NULL; 1253 1254 switch (acb->adapter_type) { 1255 case ACB_ADAPTER_TYPE_A: { 1256 struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu; 1257 1258 qbuffer = (struct QBUFFER *)&phbamu->message_wbuffer; 1259 } 1260 break; 1261 case ACB_ADAPTER_TYPE_B: { 1262 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1263 1264 qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_wbuffer; 1265 } 1266 break; 1267 case ACB_ADAPTER_TYPE_C: { 1268 struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu; 1269 1270 qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer; 1271 } 1272 break; 1273 case ACB_ADAPTER_TYPE_D: { 1274 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1275 1276 qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_wbuffer; 1277 } 1278 break; 1279 case ACB_ADAPTER_TYPE_E: { 1280 struct HBE_MessageUnit *phbcmu = (struct HBE_MessageUnit *)acb->pmu; 1281 1282 qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer; 1283 } 1284 break; 1285 case ACB_ADAPTER_TYPE_F: 1286 qbuffer = (struct QBUFFER *)acb->message_wbuffer; 1287 break; 1288 } 1289 return(qbuffer); 1290 } 1291 /* 1292 ************************************************************************** 1293 ************************************************************************** 1294 */ 1295 static void arcmsr_iop_message_read(struct AdapterControlBlock *acb) 1296 { 1297 switch (acb->adapter_type) { 1298 case ACB_ADAPTER_TYPE_A: { 1299 /* let IOP know data has been read */ 1300 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK); 1301 } 1302 break; 1303 case ACB_ADAPTER_TYPE_B: { 1304 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1305 /* let IOP know data has been read */ 1306 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK); 1307 } 1308 break; 1309 case ACB_ADAPTER_TYPE_C: { 1310 /* let IOP know data has been read */ 1311 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK); 1312 } 1313 break; 1314 case ACB_ADAPTER_TYPE_D: { 1315 /* let IOP know data has been read */ 1316 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ); 1317 } 1318 break; 1319 case ACB_ADAPTER_TYPE_E: 1320 case ACB_ADAPTER_TYPE_F: { 1321 /* let IOP know data has been read */ 1322 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK; 1323 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 1324 } 1325 break; 1326 } 1327 } 1328 /* 1329 ************************************************************************** 1330 ************************************************************************** 1331 */ 1332 static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb) 1333 { 1334 switch (acb->adapter_type) { 1335 case ACB_ADAPTER_TYPE_A: { 1336 /* 1337 ** push inbound doorbell tell iop, driver data write ok 1338 ** and wait reply on next hwinterrupt for next Qbuffer post 1339 */ 1340 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK); 1341 } 1342 break; 1343 case ACB_ADAPTER_TYPE_B: { 1344 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1345 /* 1346 ** push inbound doorbell tell iop, driver data write ok 1347 ** and wait reply on next hwinterrupt for next Qbuffer post 1348 */ 1349 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_WRITE_OK); 1350 } 1351 break; 1352 case ACB_ADAPTER_TYPE_C: { 1353 /* 1354 ** push inbound doorbell tell iop, driver data write ok 1355 ** and wait reply on next hwinterrupt for next Qbuffer post 1356 */ 1357 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK); 1358 } 1359 break; 1360 case ACB_ADAPTER_TYPE_D: { 1361 /* 1362 ** push inbound doorbell tell iop, driver data write ok 1363 ** and wait reply on next hwinterrupt for next Qbuffer post 1364 */ 1365 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY); 1366 } 1367 break; 1368 case ACB_ADAPTER_TYPE_E: 1369 case ACB_ADAPTER_TYPE_F: { 1370 /* 1371 ** push inbound doorbell tell iop, driver data write ok 1372 ** and wait reply on next hwinterrupt for next Qbuffer post 1373 */ 1374 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK; 1375 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 1376 } 1377 break; 1378 } 1379 } 1380 /* 1381 ************************************************************************ 1382 ************************************************************************ 1383 */ 1384 static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb) 1385 { 1386 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1387 CHIP_REG_WRITE32(HBA_MessageUnit, 1388 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1389 if(!arcmsr_hba_wait_msgint_ready(acb)) { 1390 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n" 1391 , acb->pci_unit); 1392 } 1393 } 1394 /* 1395 ************************************************************************ 1396 ************************************************************************ 1397 */ 1398 static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb) 1399 { 1400 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1401 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1402 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_STOP_BGRB); 1403 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 1404 printf( "arcmsr%d: wait 'stop adapter background rebulid' timeout \n" 1405 , acb->pci_unit); 1406 } 1407 } 1408 /* 1409 ************************************************************************ 1410 ************************************************************************ 1411 */ 1412 static void arcmsr_stop_hbc_bgrb(struct AdapterControlBlock *acb) 1413 { 1414 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1415 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1416 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 1417 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 1418 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1419 } 1420 } 1421 /* 1422 ************************************************************************ 1423 ************************************************************************ 1424 */ 1425 static void arcmsr_stop_hbd_bgrb(struct AdapterControlBlock *acb) 1426 { 1427 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1428 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1429 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 1430 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1431 } 1432 } 1433 /* 1434 ************************************************************************ 1435 ************************************************************************ 1436 */ 1437 static void arcmsr_stop_hbe_bgrb(struct AdapterControlBlock *acb) 1438 { 1439 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1440 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1441 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 1442 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 1443 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 1444 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1445 } 1446 } 1447 /* 1448 ************************************************************************ 1449 ************************************************************************ 1450 */ 1451 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb) 1452 { 1453 switch (acb->adapter_type) { 1454 case ACB_ADAPTER_TYPE_A: { 1455 arcmsr_stop_hba_bgrb(acb); 1456 } 1457 break; 1458 case ACB_ADAPTER_TYPE_B: { 1459 arcmsr_stop_hbb_bgrb(acb); 1460 } 1461 break; 1462 case ACB_ADAPTER_TYPE_C: { 1463 arcmsr_stop_hbc_bgrb(acb); 1464 } 1465 break; 1466 case ACB_ADAPTER_TYPE_D: { 1467 arcmsr_stop_hbd_bgrb(acb); 1468 } 1469 break; 1470 case ACB_ADAPTER_TYPE_E: 1471 case ACB_ADAPTER_TYPE_F: { 1472 arcmsr_stop_hbe_bgrb(acb); 1473 } 1474 break; 1475 } 1476 } 1477 /* 1478 ************************************************************************ 1479 ************************************************************************ 1480 */ 1481 static void arcmsr_poll(struct cam_sim *psim) 1482 { 1483 struct AdapterControlBlock *acb; 1484 int mutex; 1485 1486 acb = (struct AdapterControlBlock *)cam_sim_softc(psim); 1487 mutex = mtx_owned(&acb->isr_lock); 1488 if( mutex == 0 ) 1489 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 1490 arcmsr_interrupt(acb); 1491 if( mutex == 0 ) 1492 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 1493 } 1494 /* 1495 ************************************************************************** 1496 ************************************************************************** 1497 */ 1498 static u_int32_t arcmsr_Read_iop_rqbuffer_data_D(struct AdapterControlBlock *acb, 1499 struct QBUFFER *prbuffer) { 1500 u_int8_t *pQbuffer; 1501 u_int8_t *buf1 = NULL; 1502 u_int32_t *iop_data, *buf2 = NULL; 1503 u_int32_t iop_len, data_len; 1504 1505 iop_data = (u_int32_t *)prbuffer->data; 1506 iop_len = (u_int32_t)prbuffer->data_len; 1507 if ( iop_len > 0 ) 1508 { 1509 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO); 1510 buf2 = (u_int32_t *)buf1; 1511 if( buf1 == NULL) 1512 return (0); 1513 data_len = iop_len; 1514 while(data_len >= 4) 1515 { 1516 *buf2++ = *iop_data++; 1517 data_len -= 4; 1518 } 1519 if(data_len) 1520 *buf2 = *iop_data; 1521 buf2 = (u_int32_t *)buf1; 1522 } 1523 while (iop_len > 0) { 1524 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex]; 1525 *pQbuffer = *buf1; 1526 acb->rqbuf_lastindex++; 1527 /* if last, index number set it to 0 */ 1528 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 1529 buf1++; 1530 iop_len--; 1531 } 1532 if(buf2) 1533 free( (u_int8_t *)buf2, M_DEVBUF); 1534 /* let IOP know data has been read */ 1535 arcmsr_iop_message_read(acb); 1536 return (1); 1537 } 1538 /* 1539 ************************************************************************** 1540 ************************************************************************** 1541 */ 1542 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, 1543 struct QBUFFER *prbuffer) { 1544 u_int8_t *pQbuffer; 1545 u_int8_t *iop_data; 1546 u_int32_t iop_len; 1547 1548 if(acb->adapter_type >= ACB_ADAPTER_TYPE_B) { 1549 return(arcmsr_Read_iop_rqbuffer_data_D(acb, prbuffer)); 1550 } 1551 iop_data = (u_int8_t *)prbuffer->data; 1552 iop_len = (u_int32_t)prbuffer->data_len; 1553 while (iop_len > 0) { 1554 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex]; 1555 *pQbuffer = *iop_data; 1556 acb->rqbuf_lastindex++; 1557 /* if last, index number set it to 0 */ 1558 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 1559 iop_data++; 1560 iop_len--; 1561 } 1562 /* let IOP know data has been read */ 1563 arcmsr_iop_message_read(acb); 1564 return (1); 1565 } 1566 /* 1567 ************************************************************************** 1568 ************************************************************************** 1569 */ 1570 static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb) 1571 { 1572 struct QBUFFER *prbuffer; 1573 int my_empty_len; 1574 1575 /*check this iop data if overflow my rqbuffer*/ 1576 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 1577 prbuffer = arcmsr_get_iop_rqbuffer(acb); 1578 my_empty_len = (acb->rqbuf_lastindex - acb->rqbuf_firstindex - 1) & 1579 (ARCMSR_MAX_QBUFFER-1); 1580 if(my_empty_len >= prbuffer->data_len) { 1581 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 1582 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 1583 } else { 1584 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 1585 } 1586 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 1587 } 1588 /* 1589 ********************************************************************** 1590 ********************************************************************** 1591 */ 1592 static void arcmsr_Write_data_2iop_wqbuffer_D(struct AdapterControlBlock *acb) 1593 { 1594 u_int8_t *pQbuffer; 1595 struct QBUFFER *pwbuffer; 1596 u_int8_t *buf1 = NULL; 1597 u_int32_t *iop_data, *buf2 = NULL; 1598 u_int32_t allxfer_len = 0, data_len; 1599 1600 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) { 1601 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO); 1602 buf2 = (u_int32_t *)buf1; 1603 if( buf1 == NULL) 1604 return; 1605 1606 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ); 1607 pwbuffer = arcmsr_get_iop_wqbuffer(acb); 1608 iop_data = (u_int32_t *)pwbuffer->data; 1609 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex) 1610 && (allxfer_len < 124)) { 1611 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex]; 1612 *buf1 = *pQbuffer; 1613 acb->wqbuf_firstindex++; 1614 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 1615 buf1++; 1616 allxfer_len++; 1617 } 1618 pwbuffer->data_len = allxfer_len; 1619 data_len = allxfer_len; 1620 buf1 = (u_int8_t *)buf2; 1621 while(data_len >= 4) 1622 { 1623 *iop_data++ = *buf2++; 1624 data_len -= 4; 1625 } 1626 if(data_len) 1627 *iop_data = *buf2; 1628 free( buf1, M_DEVBUF); 1629 arcmsr_iop_message_wrote(acb); 1630 } 1631 } 1632 /* 1633 ********************************************************************** 1634 ********************************************************************** 1635 */ 1636 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb) 1637 { 1638 u_int8_t *pQbuffer; 1639 struct QBUFFER *pwbuffer; 1640 u_int8_t *iop_data; 1641 int32_t allxfer_len=0; 1642 1643 if(acb->adapter_type >= ACB_ADAPTER_TYPE_B) { 1644 arcmsr_Write_data_2iop_wqbuffer_D(acb); 1645 return; 1646 } 1647 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) { 1648 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ); 1649 pwbuffer = arcmsr_get_iop_wqbuffer(acb); 1650 iop_data = (u_int8_t *)pwbuffer->data; 1651 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex) 1652 && (allxfer_len < 124)) { 1653 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex]; 1654 *iop_data = *pQbuffer; 1655 acb->wqbuf_firstindex++; 1656 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 1657 iop_data++; 1658 allxfer_len++; 1659 } 1660 pwbuffer->data_len = allxfer_len; 1661 arcmsr_iop_message_wrote(acb); 1662 } 1663 } 1664 /* 1665 ************************************************************************** 1666 ************************************************************************** 1667 */ 1668 static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb) 1669 { 1670 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 1671 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READ; 1672 /* 1673 ***************************************************************** 1674 ** check if there are any mail packages from user space program 1675 ** in my post bag, now is the time to send them into Areca's firmware 1676 ***************************************************************** 1677 */ 1678 if(acb->wqbuf_firstindex != acb->wqbuf_lastindex) { 1679 arcmsr_Write_data_2iop_wqbuffer(acb); 1680 } 1681 if(acb->wqbuf_firstindex == acb->wqbuf_lastindex) { 1682 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED; 1683 } 1684 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 1685 } 1686 /* 1687 ************************************************************************** 1688 ************************************************************************** 1689 */ 1690 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb) 1691 { 1692 /* 1693 if (ccb->ccb_h.status != CAM_REQ_CMP) 1694 printf("arcmsr_rescanLun_cb: Rescan Target=%x, lun=%x," 1695 "failure status=%x\n", ccb->ccb_h.target_id, 1696 ccb->ccb_h.target_lun, ccb->ccb_h.status); 1697 else 1698 printf("arcmsr_rescanLun_cb: Rescan lun successfully!\n"); 1699 */ 1700 xpt_free_path(ccb->ccb_h.path); 1701 xpt_free_ccb(ccb); 1702 } 1703 1704 static void arcmsr_rescan_lun(struct AdapterControlBlock *acb, int target, int lun) 1705 { 1706 struct cam_path *path; 1707 union ccb *ccb; 1708 1709 if ((ccb = (union ccb *)xpt_alloc_ccb_nowait()) == NULL) 1710 return; 1711 if (xpt_create_path(&path, NULL, cam_sim_path(acb->psim), target, lun) != CAM_REQ_CMP) 1712 { 1713 xpt_free_ccb(ccb); 1714 return; 1715 } 1716 /* printf("arcmsr_rescan_lun: Rescan Target=%x, Lun=%x\n", target, lun); */ 1717 xpt_setup_ccb(&ccb->ccb_h, path, 5); 1718 ccb->ccb_h.func_code = XPT_SCAN_LUN; 1719 ccb->ccb_h.cbfcnp = arcmsr_rescanLun_cb; 1720 ccb->crcn.flags = CAM_FLAG_NONE; 1721 xpt_action(ccb); 1722 } 1723 1724 static void arcmsr_abort_dr_ccbs(struct AdapterControlBlock *acb, int target, int lun) 1725 { 1726 struct CommandControlBlock *srb; 1727 u_int32_t intmask_org; 1728 int i; 1729 1730 /* disable all outbound interrupts */ 1731 intmask_org = arcmsr_disable_allintr(acb); 1732 for (i = 0; i < ARCMSR_MAX_FREESRB_NUM; i++) 1733 { 1734 srb = acb->psrb_pool[i]; 1735 if (srb->srb_state == ARCMSR_SRB_START) 1736 { 1737 if((target == srb->pccb->ccb_h.target_id) && (lun == srb->pccb->ccb_h.target_lun)) 1738 { 1739 srb->srb_state = ARCMSR_SRB_ABORTED; 1740 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 1741 arcmsr_srb_complete(srb, 1); 1742 printf("arcmsr%d: abort scsi id %d lun %d srb=%p \n", acb->pci_unit, target, lun, srb); 1743 } 1744 } 1745 } 1746 /* enable outbound Post Queue, outbound doorbell Interrupt */ 1747 arcmsr_enable_allintr(acb, intmask_org); 1748 } 1749 /* 1750 ************************************************************************** 1751 ************************************************************************** 1752 */ 1753 static void arcmsr_dr_handle(struct AdapterControlBlock *acb) { 1754 u_int32_t devicemap; 1755 u_int32_t target, lun; 1756 u_int32_t deviceMapCurrent[4]={0}; 1757 u_int8_t *pDevMap; 1758 1759 switch (acb->adapter_type) { 1760 case ACB_ADAPTER_TYPE_A: 1761 devicemap = offsetof(struct HBA_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1762 for (target = 0; target < 4; target++) 1763 { 1764 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1765 devicemap += 4; 1766 } 1767 break; 1768 1769 case ACB_ADAPTER_TYPE_B: 1770 devicemap = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1771 for (target = 0; target < 4; target++) 1772 { 1773 deviceMapCurrent[target]=bus_space_read_4(acb->btag[1], acb->bhandle[1], devicemap); 1774 devicemap += 4; 1775 } 1776 break; 1777 1778 case ACB_ADAPTER_TYPE_C: 1779 devicemap = offsetof(struct HBC_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1780 for (target = 0; target < 4; target++) 1781 { 1782 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1783 devicemap += 4; 1784 } 1785 break; 1786 case ACB_ADAPTER_TYPE_D: 1787 devicemap = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1788 for (target = 0; target < 4; target++) 1789 { 1790 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1791 devicemap += 4; 1792 } 1793 break; 1794 case ACB_ADAPTER_TYPE_E: 1795 devicemap = offsetof(struct HBE_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1796 for (target = 0; target < 4; target++) 1797 { 1798 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1799 devicemap += 4; 1800 } 1801 break; 1802 case ACB_ADAPTER_TYPE_F: 1803 devicemap = ARCMSR_FW_DEVMAP_OFFSET; 1804 for (target = 0; target < 4; target++) 1805 { 1806 deviceMapCurrent[target] = acb->msgcode_rwbuffer[devicemap]; 1807 devicemap += 1; 1808 } 1809 break; 1810 } 1811 1812 if(acb->acb_flags & ACB_F_BUS_HANG_ON) 1813 { 1814 acb->acb_flags &= ~ACB_F_BUS_HANG_ON; 1815 } 1816 /* 1817 ** adapter posted CONFIG message 1818 ** copy the new map, note if there are differences with the current map 1819 */ 1820 pDevMap = (u_int8_t *)&deviceMapCurrent[0]; 1821 for (target = 0; target < ARCMSR_MAX_TARGETID - 1; target++) 1822 { 1823 if (*pDevMap != acb->device_map[target]) 1824 { 1825 u_int8_t difference, bit_check; 1826 1827 difference = *pDevMap ^ acb->device_map[target]; 1828 for(lun=0; lun < ARCMSR_MAX_TARGETLUN; lun++) 1829 { 1830 bit_check = (1 << lun); /*check bit from 0....31*/ 1831 if(difference & bit_check) 1832 { 1833 if(acb->device_map[target] & bit_check) 1834 {/* unit departed */ 1835 printf("arcmsr_dr_handle: Target=%x, lun=%x, GONE!!!\n",target,lun); 1836 arcmsr_abort_dr_ccbs(acb, target, lun); 1837 arcmsr_rescan_lun(acb, target, lun); 1838 acb->devstate[target][lun] = ARECA_RAID_GONE; 1839 } 1840 else 1841 {/* unit arrived */ 1842 printf("arcmsr_dr_handle: Target=%x, lun=%x, Plug-IN!!!\n",target,lun); 1843 arcmsr_rescan_lun(acb, target, lun); 1844 acb->devstate[target][lun] = ARECA_RAID_GOOD; 1845 } 1846 } 1847 } 1848 /* printf("arcmsr_dr_handle: acb->device_map[%x]=0x%x, deviceMapCurrent[%x]=%x\n",target,acb->device_map[target],target,*pDevMap); */ 1849 acb->device_map[target] = *pDevMap; 1850 } 1851 pDevMap++; 1852 } 1853 } 1854 /* 1855 ************************************************************************** 1856 ************************************************************************** 1857 */ 1858 static void arcmsr_hba_message_isr(struct AdapterControlBlock *acb) { 1859 u_int32_t outbound_message; 1860 1861 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT); 1862 outbound_message = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[0]); 1863 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1864 arcmsr_dr_handle( acb ); 1865 } 1866 /* 1867 ************************************************************************** 1868 ************************************************************************** 1869 */ 1870 static void arcmsr_hbb_message_isr(struct AdapterControlBlock *acb) { 1871 u_int32_t outbound_message; 1872 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1873 1874 /* clear interrupts */ 1875 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN); 1876 outbound_message = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0]); 1877 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1878 arcmsr_dr_handle( acb ); 1879 } 1880 /* 1881 ************************************************************************** 1882 ************************************************************************** 1883 */ 1884 static void arcmsr_hbc_message_isr(struct AdapterControlBlock *acb) { 1885 u_int32_t outbound_message; 1886 1887 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR); 1888 outbound_message = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[0]); 1889 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1890 arcmsr_dr_handle( acb ); 1891 } 1892 /* 1893 ************************************************************************** 1894 ************************************************************************** 1895 */ 1896 static void arcmsr_hbd_message_isr(struct AdapterControlBlock *acb) { 1897 u_int32_t outbound_message; 1898 1899 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR); 1900 outbound_message = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[0]); 1901 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1902 arcmsr_dr_handle( acb ); 1903 } 1904 /* 1905 ************************************************************************** 1906 ************************************************************************** 1907 */ 1908 static void arcmsr_hbe_message_isr(struct AdapterControlBlock *acb) { 1909 u_int32_t outbound_message; 1910 1911 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); 1912 if (acb->adapter_type == ACB_ADAPTER_TYPE_E) 1913 outbound_message = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[0]); 1914 else 1915 outbound_message = acb->msgcode_rwbuffer[0]; 1916 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1917 arcmsr_dr_handle( acb ); 1918 } 1919 /* 1920 ************************************************************************** 1921 ************************************************************************** 1922 */ 1923 static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb) 1924 { 1925 u_int32_t doorbell_status; 1926 1927 /* 1928 ******************************************************************* 1929 ** Maybe here we need to check wrqbuffer_lock is lock or not 1930 ** DOORBELL: din! don! 1931 ** check if there are any mail need to pack from firmware 1932 ******************************************************************* 1933 */ 1934 doorbell_status = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell); 1935 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */ 1936 if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) { 1937 arcmsr_iop2drv_data_wrote_handle(acb); 1938 } 1939 if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) { 1940 arcmsr_iop2drv_data_read_handle(acb); 1941 } 1942 } 1943 /* 1944 ************************************************************************** 1945 ************************************************************************** 1946 */ 1947 static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *acb) 1948 { 1949 u_int32_t doorbell_status; 1950 1951 /* 1952 ******************************************************************* 1953 ** Maybe here we need to check wrqbuffer_lock is lock or not 1954 ** DOORBELL: din! don! 1955 ** check if there are any mail need to pack from firmware 1956 ******************************************************************* 1957 */ 1958 doorbell_status = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell); 1959 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, doorbell_status); /* clear doorbell interrupt */ 1960 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) { 1961 arcmsr_iop2drv_data_wrote_handle(acb); 1962 } 1963 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) { 1964 arcmsr_iop2drv_data_read_handle(acb); 1965 } 1966 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 1967 arcmsr_hbc_message_isr(acb); /* messenger of "driver to iop commands" */ 1968 } 1969 } 1970 /* 1971 ************************************************************************** 1972 ************************************************************************** 1973 */ 1974 static void arcmsr_hbd_doorbell_isr(struct AdapterControlBlock *acb) 1975 { 1976 u_int32_t doorbell_status; 1977 1978 /* 1979 ******************************************************************* 1980 ** Maybe here we need to check wrqbuffer_lock is lock or not 1981 ** DOORBELL: din! don! 1982 ** check if there are any mail need to pack from firmware 1983 ******************************************************************* 1984 */ 1985 doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE; 1986 if(doorbell_status) 1987 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */ 1988 while( doorbell_status & ARCMSR_HBDMU_F0_DOORBELL_CAUSE ) { 1989 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK) { 1990 arcmsr_iop2drv_data_wrote_handle(acb); 1991 } 1992 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK) { 1993 arcmsr_iop2drv_data_read_handle(acb); 1994 } 1995 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) { 1996 arcmsr_hbd_message_isr(acb); /* messenger of "driver to iop commands" */ 1997 } 1998 doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE; 1999 if(doorbell_status) 2000 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */ 2001 } 2002 } 2003 /* 2004 ************************************************************************** 2005 ************************************************************************** 2006 */ 2007 static void arcmsr_hbe_doorbell_isr(struct AdapterControlBlock *acb) 2008 { 2009 u_int32_t doorbell_status, in_doorbell; 2010 2011 /* 2012 ******************************************************************* 2013 ** Maybe here we need to check wrqbuffer_lock is lock or not 2014 ** DOORBELL: din! don! 2015 ** check if there are any mail need to pack from firmware 2016 ******************************************************************* 2017 */ 2018 in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell); 2019 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /* clear doorbell interrupt */ 2020 doorbell_status = in_doorbell ^ acb->in_doorbell; 2021 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) { 2022 arcmsr_iop2drv_data_wrote_handle(acb); 2023 } 2024 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK) { 2025 arcmsr_iop2drv_data_read_handle(acb); 2026 } 2027 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) { 2028 arcmsr_hbe_message_isr(acb); /* messenger of "driver to iop commands" */ 2029 } 2030 acb->in_doorbell = in_doorbell; 2031 } 2032 /* 2033 ************************************************************************** 2034 ************************************************************************** 2035 */ 2036 static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb) 2037 { 2038 u_int32_t flag_srb; 2039 u_int16_t error; 2040 2041 /* 2042 ***************************************************************************** 2043 ** areca cdb command done 2044 ***************************************************************************** 2045 */ 2046 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 2047 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2048 while((flag_srb = CHIP_REG_READ32(HBA_MessageUnit, 2049 0, outbound_queueport)) != 0xFFFFFFFF) { 2050 /* check if command done with no error*/ 2051 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0) ? TRUE : FALSE; 2052 arcmsr_drain_donequeue(acb, flag_srb, error); 2053 } /*drain reply FIFO*/ 2054 } 2055 /* 2056 ************************************************************************** 2057 ************************************************************************** 2058 */ 2059 static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb) 2060 { 2061 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 2062 u_int32_t flag_srb; 2063 int index; 2064 u_int16_t error; 2065 2066 /* 2067 ***************************************************************************** 2068 ** areca cdb command done 2069 ***************************************************************************** 2070 */ 2071 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 2072 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2073 index = phbbmu->doneq_index; 2074 while((flag_srb = phbbmu->done_qbuffer[index]) != 0) { 2075 phbbmu->done_qbuffer[index] = 0; 2076 index++; 2077 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 2078 phbbmu->doneq_index = index; 2079 /* check if command done with no error*/ 2080 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 2081 arcmsr_drain_donequeue(acb, flag_srb, error); 2082 } /*drain reply FIFO*/ 2083 } 2084 /* 2085 ************************************************************************** 2086 ************************************************************************** 2087 */ 2088 static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb) 2089 { 2090 u_int32_t flag_srb,throttling = 0; 2091 u_int16_t error; 2092 2093 /* 2094 ***************************************************************************** 2095 ** areca cdb command done 2096 ***************************************************************************** 2097 */ 2098 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2099 do { 2100 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 2101 if (flag_srb == 0xFFFFFFFF) 2102 break; 2103 /* check if command done with no error*/ 2104 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE; 2105 arcmsr_drain_donequeue(acb, flag_srb, error); 2106 throttling++; 2107 if(throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) { 2108 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING); 2109 throttling = 0; 2110 } 2111 } while(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR); 2112 } 2113 /* 2114 ********************************************************************** 2115 ** 2116 ********************************************************************** 2117 */ 2118 static uint16_t arcmsr_get_doneq_index(struct HBD_MessageUnit0 *phbdmu) 2119 { 2120 uint16_t doneq_index, index_stripped; 2121 2122 doneq_index = phbdmu->doneq_index; 2123 if (doneq_index & 0x4000) { 2124 index_stripped = doneq_index & 0xFF; 2125 index_stripped += 1; 2126 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 2127 phbdmu->doneq_index = index_stripped ? 2128 (index_stripped | 0x4000) : index_stripped; 2129 } else { 2130 index_stripped = doneq_index; 2131 index_stripped += 1; 2132 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 2133 phbdmu->doneq_index = index_stripped ? 2134 index_stripped : (index_stripped | 0x4000); 2135 } 2136 return (phbdmu->doneq_index); 2137 } 2138 /* 2139 ************************************************************************** 2140 ************************************************************************** 2141 */ 2142 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb) 2143 { 2144 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 2145 u_int32_t outbound_write_pointer; 2146 u_int32_t addressLow; 2147 uint16_t doneq_index; 2148 u_int16_t error; 2149 /* 2150 ***************************************************************************** 2151 ** areca cdb command done 2152 ***************************************************************************** 2153 */ 2154 if((CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause) & 2155 ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT) == 0) 2156 return; 2157 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 2158 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2159 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 2160 doneq_index = phbdmu->doneq_index; 2161 while ((doneq_index & 0xFF) != (outbound_write_pointer & 0xFF)) { 2162 doneq_index = arcmsr_get_doneq_index(phbdmu); 2163 addressLow = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow; 2164 error = (addressLow & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 2165 arcmsr_drain_donequeue(acb, addressLow, error); /*Check if command done with no error */ 2166 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index); 2167 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 2168 } 2169 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_interrupt_cause, ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR); 2170 CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause); /*Dummy ioread32 to force pci flush */ 2171 } 2172 /* 2173 ************************************************************************** 2174 ************************************************************************** 2175 */ 2176 static void arcmsr_hbe_postqueue_isr(struct AdapterControlBlock *acb) 2177 { 2178 u_int16_t error; 2179 uint32_t doneq_index; 2180 uint16_t cmdSMID; 2181 2182 /* 2183 ***************************************************************************** 2184 ** areca cdb command done 2185 ***************************************************************************** 2186 */ 2187 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2188 doneq_index = acb->doneq_index; 2189 while ((CHIP_REG_READ32(HBE_MessageUnit, 0, reply_post_producer_index) & 0xFFFF) != doneq_index) { 2190 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID; 2191 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 2192 arcmsr_drain_donequeue(acb, (u_int32_t)cmdSMID, error); 2193 doneq_index++; 2194 if (doneq_index >= acb->completionQ_entry) 2195 doneq_index = 0; 2196 } 2197 acb->doneq_index = doneq_index; 2198 CHIP_REG_WRITE32(HBE_MessageUnit, 0, reply_post_consumer_index, doneq_index); 2199 } 2200 2201 static void arcmsr_hbf_postqueue_isr(struct AdapterControlBlock *acb) 2202 { 2203 uint16_t error; 2204 uint32_t doneq_index; 2205 uint16_t cmdSMID; 2206 2207 /* 2208 ***************************************************************************** 2209 ** areca cdb command done 2210 ***************************************************************************** 2211 */ 2212 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2213 doneq_index = acb->doneq_index; 2214 while (1) { 2215 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID; 2216 if (cmdSMID == 0xffff) 2217 break; 2218 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 2219 arcmsr_drain_donequeue(acb, (u_int32_t)cmdSMID, error); 2220 acb->pCompletionQ[doneq_index].cmdSMID = 0xffff; 2221 doneq_index++; 2222 if (doneq_index >= acb->completionQ_entry) 2223 doneq_index = 0; 2224 } 2225 acb->doneq_index = doneq_index; 2226 CHIP_REG_WRITE32(HBF_MessageUnit, 0, reply_post_consumer_index, doneq_index); 2227 } 2228 2229 /* 2230 ********************************************************************** 2231 ********************************************************************** 2232 */ 2233 static void arcmsr_handle_hba_isr( struct AdapterControlBlock *acb) 2234 { 2235 u_int32_t outbound_intStatus; 2236 /* 2237 ********************************************* 2238 ** check outbound intstatus 2239 ********************************************* 2240 */ 2241 outbound_intStatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 2242 if(!outbound_intStatus) { 2243 /*it must be share irq*/ 2244 return; 2245 } 2246 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intStatus); /*clear interrupt*/ 2247 /* MU doorbell interrupts*/ 2248 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) { 2249 arcmsr_hba_doorbell_isr(acb); 2250 } 2251 /* MU post queue interrupts*/ 2252 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) { 2253 arcmsr_hba_postqueue_isr(acb); 2254 } 2255 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { 2256 arcmsr_hba_message_isr(acb); 2257 } 2258 } 2259 /* 2260 ********************************************************************** 2261 ********************************************************************** 2262 */ 2263 static void arcmsr_handle_hbb_isr( struct AdapterControlBlock *acb) 2264 { 2265 u_int32_t outbound_doorbell; 2266 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 2267 /* 2268 ********************************************* 2269 ** check outbound intstatus 2270 ********************************************* 2271 */ 2272 outbound_doorbell = READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & acb->outbound_int_enable; 2273 if(!outbound_doorbell) { 2274 /*it must be share irq*/ 2275 return; 2276 } 2277 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ~outbound_doorbell); /* clear doorbell interrupt */ 2278 READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell); 2279 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 2280 /* MU ioctl transfer doorbell interrupts*/ 2281 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) { 2282 arcmsr_iop2drv_data_wrote_handle(acb); 2283 } 2284 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) { 2285 arcmsr_iop2drv_data_read_handle(acb); 2286 } 2287 /* MU post queue interrupts*/ 2288 if(outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) { 2289 arcmsr_hbb_postqueue_isr(acb); 2290 } 2291 if(outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) { 2292 arcmsr_hbb_message_isr(acb); 2293 } 2294 } 2295 /* 2296 ********************************************************************** 2297 ********************************************************************** 2298 */ 2299 static void arcmsr_handle_hbc_isr( struct AdapterControlBlock *acb) 2300 { 2301 u_int32_t host_interrupt_status; 2302 /* 2303 ********************************************* 2304 ** check outbound intstatus 2305 ********************************************* 2306 */ 2307 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & 2308 (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | 2309 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR); 2310 if(!host_interrupt_status) { 2311 /*it must be share irq*/ 2312 return; 2313 } 2314 do { 2315 /* MU doorbell interrupts*/ 2316 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) { 2317 arcmsr_hbc_doorbell_isr(acb); 2318 } 2319 /* MU post queue interrupts*/ 2320 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) { 2321 arcmsr_hbc_postqueue_isr(acb); 2322 } 2323 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status); 2324 } while (host_interrupt_status & (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR)); 2325 } 2326 /* 2327 ********************************************************************** 2328 ********************************************************************** 2329 */ 2330 static void arcmsr_handle_hbd_isr( struct AdapterControlBlock *acb) 2331 { 2332 u_int32_t host_interrupt_status; 2333 u_int32_t intmask_org; 2334 /* 2335 ********************************************* 2336 ** check outbound intstatus 2337 ********************************************* 2338 */ 2339 host_interrupt_status = CHIP_REG_READ32(HBD_MessageUnit, 0, host_int_status) & acb->outbound_int_enable; 2340 if(!(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_INT)) { 2341 /*it must be share irq*/ 2342 return; 2343 } 2344 /* disable outbound interrupt */ 2345 intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable) ; /* disable outbound message0 int */ 2346 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE); 2347 /* MU doorbell interrupts*/ 2348 if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT) { 2349 arcmsr_hbd_doorbell_isr(acb); 2350 } 2351 /* MU post queue interrupts*/ 2352 if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT) { 2353 arcmsr_hbd_postqueue_isr(acb); 2354 } 2355 /* enable all outbound interrupt */ 2356 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | ARCMSR_HBDMU_ALL_INT_ENABLE); 2357 // CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); 2358 } 2359 /* 2360 ********************************************************************** 2361 ********************************************************************** 2362 */ 2363 static void arcmsr_handle_hbe_isr( struct AdapterControlBlock *acb) 2364 { 2365 u_int32_t host_interrupt_status; 2366 /* 2367 ********************************************* 2368 ** check outbound intstatus 2369 ********************************************* 2370 */ 2371 host_interrupt_status = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_status) & 2372 (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | 2373 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR); 2374 if(!host_interrupt_status) { 2375 /*it must be share irq*/ 2376 return; 2377 } 2378 do { 2379 /* MU doorbell interrupts*/ 2380 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) { 2381 arcmsr_hbe_doorbell_isr(acb); 2382 } 2383 /* MU post queue interrupts*/ 2384 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) { 2385 arcmsr_hbe_postqueue_isr(acb); 2386 } 2387 host_interrupt_status = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_status); 2388 } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR)); 2389 } 2390 2391 static void arcmsr_handle_hbf_isr( struct AdapterControlBlock *acb) 2392 { 2393 u_int32_t host_interrupt_status; 2394 /* 2395 ********************************************* 2396 ** check outbound intstatus 2397 ********************************************* 2398 */ 2399 host_interrupt_status = CHIP_REG_READ32(HBF_MessageUnit, 0, host_int_status) & 2400 (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | 2401 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR); 2402 if(!host_interrupt_status) { 2403 /*it must be share irq*/ 2404 return; 2405 } 2406 do { 2407 /* MU doorbell interrupts*/ 2408 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) { 2409 arcmsr_hbe_doorbell_isr(acb); 2410 } 2411 /* MU post queue interrupts*/ 2412 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) { 2413 arcmsr_hbf_postqueue_isr(acb); 2414 } 2415 host_interrupt_status = CHIP_REG_READ32(HBF_MessageUnit, 0, host_int_status); 2416 } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR)); 2417 } 2418 /* 2419 ****************************************************************************** 2420 ****************************************************************************** 2421 */ 2422 static void arcmsr_interrupt(struct AdapterControlBlock *acb) 2423 { 2424 switch (acb->adapter_type) { 2425 case ACB_ADAPTER_TYPE_A: 2426 arcmsr_handle_hba_isr(acb); 2427 break; 2428 case ACB_ADAPTER_TYPE_B: 2429 arcmsr_handle_hbb_isr(acb); 2430 break; 2431 case ACB_ADAPTER_TYPE_C: 2432 arcmsr_handle_hbc_isr(acb); 2433 break; 2434 case ACB_ADAPTER_TYPE_D: 2435 arcmsr_handle_hbd_isr(acb); 2436 break; 2437 case ACB_ADAPTER_TYPE_E: 2438 arcmsr_handle_hbe_isr(acb); 2439 break; 2440 case ACB_ADAPTER_TYPE_F: 2441 arcmsr_handle_hbf_isr(acb); 2442 break; 2443 default: 2444 printf("arcmsr%d: interrupt service," 2445 " unknown adapter type =%d\n", acb->pci_unit, acb->adapter_type); 2446 break; 2447 } 2448 } 2449 /* 2450 ********************************************************************** 2451 ********************************************************************** 2452 */ 2453 static void arcmsr_intr_handler(void *arg) 2454 { 2455 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg; 2456 2457 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 2458 arcmsr_interrupt(acb); 2459 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 2460 } 2461 /* 2462 ****************************************************************************** 2463 ****************************************************************************** 2464 */ 2465 static void arcmsr_polling_devmap(void *arg) 2466 { 2467 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg; 2468 switch (acb->adapter_type) { 2469 case ACB_ADAPTER_TYPE_A: 2470 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2471 break; 2472 2473 case ACB_ADAPTER_TYPE_B: { 2474 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 2475 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG); 2476 } 2477 break; 2478 2479 case ACB_ADAPTER_TYPE_C: 2480 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2481 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 2482 break; 2483 2484 case ACB_ADAPTER_TYPE_D: 2485 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2486 break; 2487 2488 case ACB_ADAPTER_TYPE_E: 2489 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2490 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 2491 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 2492 break; 2493 2494 case ACB_ADAPTER_TYPE_F: { 2495 u_int32_t outMsg1 = CHIP_REG_READ32(HBF_MessageUnit, 0, outbound_msgaddr1); 2496 if (!(outMsg1 & ARCMSR_HBFMU_MESSAGE_FIRMWARE_OK) || 2497 (outMsg1 & ARCMSR_HBFMU_MESSAGE_NO_VOLUME_CHANGE)) 2498 goto nxt6s; 2499 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2500 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 2501 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 2502 break; 2503 } 2504 } 2505 nxt6s: 2506 if((acb->acb_flags & ACB_F_SCSISTOPADAPTER) == 0) 2507 { 2508 callout_reset(&acb->devmap_callout, 5 * hz, arcmsr_polling_devmap, acb); /* polling per 5 seconds */ 2509 } 2510 } 2511 2512 /* 2513 ******************************************************************************* 2514 ** 2515 ******************************************************************************* 2516 */ 2517 static void arcmsr_iop_parking(struct AdapterControlBlock *acb) 2518 { 2519 u_int32_t intmask_org; 2520 2521 if(acb != NULL) { 2522 /* stop adapter background rebuild */ 2523 if(acb->acb_flags & ACB_F_MSG_START_BGRB) { 2524 intmask_org = arcmsr_disable_allintr(acb); 2525 arcmsr_stop_adapter_bgrb(acb); 2526 arcmsr_flush_adapter_cache(acb); 2527 arcmsr_enable_allintr(acb, intmask_org); 2528 } 2529 } 2530 } 2531 /* 2532 *********************************************************************** 2533 ** 2534 ************************************************************************ 2535 */ 2536 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg) 2537 { 2538 struct CMD_MESSAGE_FIELD *pcmdmessagefld; 2539 u_int32_t retvalue = EINVAL; 2540 2541 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) arg; 2542 if(memcmp(pcmdmessagefld->cmdmessage.Signature, "ARCMSR", 6)!=0) { 2543 return retvalue; 2544 } 2545 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2546 switch(ioctl_cmd) { 2547 case ARCMSR_MESSAGE_READ_RQBUFFER: { 2548 u_int8_t *pQbuffer; 2549 u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer; 2550 u_int32_t allxfer_len=0; 2551 2552 while((acb->rqbuf_firstindex != acb->rqbuf_lastindex) 2553 && (allxfer_len < 1031)) { 2554 /*copy READ QBUFFER to srb*/ 2555 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex]; 2556 *ptmpQbuffer = *pQbuffer; 2557 acb->rqbuf_firstindex++; 2558 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 2559 /*if last index number set it to 0 */ 2560 ptmpQbuffer++; 2561 allxfer_len++; 2562 } 2563 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2564 struct QBUFFER *prbuffer; 2565 2566 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2567 prbuffer = arcmsr_get_iop_rqbuffer(acb); 2568 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 2569 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 2570 } 2571 pcmdmessagefld->cmdmessage.Length = allxfer_len; 2572 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2573 retvalue = ARCMSR_MESSAGE_SUCCESS; 2574 } 2575 break; 2576 case ARCMSR_MESSAGE_WRITE_WQBUFFER: { 2577 u_int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex; 2578 u_int8_t *pQbuffer; 2579 u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer; 2580 2581 user_len = pcmdmessagefld->cmdmessage.Length; 2582 /*check if data xfer length of this request will overflow my array qbuffer */ 2583 wqbuf_lastindex = acb->wqbuf_lastindex; 2584 wqbuf_firstindex = acb->wqbuf_firstindex; 2585 if(wqbuf_lastindex != wqbuf_firstindex) { 2586 arcmsr_Write_data_2iop_wqbuffer(acb); 2587 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2588 } else { 2589 my_empty_len = (wqbuf_firstindex - wqbuf_lastindex - 1) & 2590 (ARCMSR_MAX_QBUFFER - 1); 2591 if(my_empty_len >= user_len) { 2592 while(user_len > 0) { 2593 /*copy srb data to wqbuffer*/ 2594 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex]; 2595 *pQbuffer = *ptmpuserbuffer; 2596 acb->wqbuf_lastindex++; 2597 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 2598 /*if last index number set it to 0 */ 2599 ptmpuserbuffer++; 2600 user_len--; 2601 } 2602 /*post fist Qbuffer*/ 2603 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) { 2604 acb->acb_flags &= ~ACB_F_MESSAGE_WQBUFFER_CLEARED; 2605 arcmsr_Write_data_2iop_wqbuffer(acb); 2606 } 2607 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2608 } else { 2609 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2610 } 2611 } 2612 retvalue = ARCMSR_MESSAGE_SUCCESS; 2613 } 2614 break; 2615 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: { 2616 u_int8_t *pQbuffer = acb->rqbuffer; 2617 2618 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2619 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2620 arcmsr_iop_message_read(acb); 2621 /*signature, let IOP know data has been readed */ 2622 } 2623 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 2624 acb->rqbuf_firstindex = 0; 2625 acb->rqbuf_lastindex = 0; 2626 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2627 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2628 retvalue = ARCMSR_MESSAGE_SUCCESS; 2629 } 2630 break; 2631 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: 2632 { 2633 u_int8_t *pQbuffer = acb->wqbuffer; 2634 2635 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2636 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2637 arcmsr_iop_message_read(acb); 2638 /*signature, let IOP know data has been readed */ 2639 } 2640 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ); 2641 acb->wqbuf_firstindex = 0; 2642 acb->wqbuf_lastindex = 0; 2643 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2644 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2645 retvalue = ARCMSR_MESSAGE_SUCCESS; 2646 } 2647 break; 2648 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: { 2649 u_int8_t *pQbuffer; 2650 2651 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2652 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2653 arcmsr_iop_message_read(acb); 2654 /*signature, let IOP know data has been readed */ 2655 } 2656 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED 2657 |ACB_F_MESSAGE_RQBUFFER_CLEARED 2658 |ACB_F_MESSAGE_WQBUFFER_READ); 2659 acb->rqbuf_firstindex = 0; 2660 acb->rqbuf_lastindex = 0; 2661 acb->wqbuf_firstindex = 0; 2662 acb->wqbuf_lastindex = 0; 2663 pQbuffer = acb->rqbuffer; 2664 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 2665 pQbuffer = acb->wqbuffer; 2666 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 2667 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2668 retvalue = ARCMSR_MESSAGE_SUCCESS; 2669 } 2670 break; 2671 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: { 2672 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F; 2673 retvalue = ARCMSR_MESSAGE_SUCCESS; 2674 } 2675 break; 2676 case ARCMSR_MESSAGE_SAY_HELLO: { 2677 u_int8_t *hello_string = "Hello! I am ARCMSR"; 2678 u_int8_t *puserbuffer = (u_int8_t *)pcmdmessagefld->messagedatabuffer; 2679 2680 if(memcpy(puserbuffer, hello_string, (int16_t)strlen(hello_string))) { 2681 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2682 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2683 return ENOIOCTL; 2684 } 2685 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2686 retvalue = ARCMSR_MESSAGE_SUCCESS; 2687 } 2688 break; 2689 case ARCMSR_MESSAGE_SAY_GOODBYE: { 2690 arcmsr_iop_parking(acb); 2691 retvalue = ARCMSR_MESSAGE_SUCCESS; 2692 } 2693 break; 2694 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: { 2695 arcmsr_flush_adapter_cache(acb); 2696 retvalue = ARCMSR_MESSAGE_SUCCESS; 2697 } 2698 break; 2699 } 2700 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2701 return (retvalue); 2702 } 2703 /* 2704 ************************************************************************** 2705 ************************************************************************** 2706 */ 2707 static void arcmsr_free_srb(struct CommandControlBlock *srb) 2708 { 2709 struct AdapterControlBlock *acb; 2710 2711 acb = srb->acb; 2712 ARCMSR_LOCK_ACQUIRE(&acb->srb_lock); 2713 srb->srb_state = ARCMSR_SRB_DONE; 2714 srb->srb_flags = 0; 2715 acb->srbworkingQ[acb->workingsrb_doneindex] = srb; 2716 acb->workingsrb_doneindex++; 2717 acb->workingsrb_doneindex %= ARCMSR_MAX_FREESRB_NUM; 2718 ARCMSR_LOCK_RELEASE(&acb->srb_lock); 2719 } 2720 /* 2721 ************************************************************************** 2722 ************************************************************************** 2723 */ 2724 static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb) 2725 { 2726 struct CommandControlBlock *srb = NULL; 2727 u_int32_t workingsrb_startindex, workingsrb_doneindex; 2728 2729 ARCMSR_LOCK_ACQUIRE(&acb->srb_lock); 2730 workingsrb_doneindex = acb->workingsrb_doneindex; 2731 workingsrb_startindex = acb->workingsrb_startindex; 2732 srb = acb->srbworkingQ[workingsrb_startindex]; 2733 workingsrb_startindex++; 2734 workingsrb_startindex %= ARCMSR_MAX_FREESRB_NUM; 2735 if(workingsrb_doneindex != workingsrb_startindex) { 2736 acb->workingsrb_startindex = workingsrb_startindex; 2737 } else { 2738 srb = NULL; 2739 } 2740 ARCMSR_LOCK_RELEASE(&acb->srb_lock); 2741 return(srb); 2742 } 2743 /* 2744 ************************************************************************** 2745 ************************************************************************** 2746 */ 2747 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb) 2748 { 2749 struct CMD_MESSAGE_FIELD *pcmdmessagefld; 2750 int retvalue = 0, transfer_len = 0; 2751 char *buffer; 2752 uint8_t *ptr = scsiio_cdb_ptr(&pccb->csio); 2753 u_int32_t controlcode = (u_int32_t ) ptr[5] << 24 | 2754 (u_int32_t ) ptr[6] << 16 | 2755 (u_int32_t ) ptr[7] << 8 | 2756 (u_int32_t ) ptr[8]; 2757 /* 4 bytes: Areca io control code */ 2758 if ((pccb->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_VADDR) { 2759 buffer = pccb->csio.data_ptr; 2760 transfer_len = pccb->csio.dxfer_len; 2761 } else { 2762 retvalue = ARCMSR_MESSAGE_FAIL; 2763 goto message_out; 2764 } 2765 if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) { 2766 retvalue = ARCMSR_MESSAGE_FAIL; 2767 goto message_out; 2768 } 2769 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) buffer; 2770 switch(controlcode) { 2771 case ARCMSR_MESSAGE_READ_RQBUFFER: { 2772 u_int8_t *pQbuffer; 2773 u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer; 2774 int32_t allxfer_len = 0; 2775 2776 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2777 while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex) 2778 && (allxfer_len < 1031)) { 2779 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex]; 2780 *ptmpQbuffer = *pQbuffer; 2781 acb->rqbuf_firstindex++; 2782 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 2783 ptmpQbuffer++; 2784 allxfer_len++; 2785 } 2786 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2787 struct QBUFFER *prbuffer; 2788 2789 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2790 prbuffer = arcmsr_get_iop_rqbuffer(acb); 2791 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 2792 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 2793 } 2794 pcmdmessagefld->cmdmessage.Length = allxfer_len; 2795 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2796 retvalue = ARCMSR_MESSAGE_SUCCESS; 2797 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2798 } 2799 break; 2800 case ARCMSR_MESSAGE_WRITE_WQBUFFER: { 2801 int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex; 2802 u_int8_t *pQbuffer; 2803 u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer; 2804 2805 user_len = pcmdmessagefld->cmdmessage.Length; 2806 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2807 wqbuf_lastindex = acb->wqbuf_lastindex; 2808 wqbuf_firstindex = acb->wqbuf_firstindex; 2809 if (wqbuf_lastindex != wqbuf_firstindex) { 2810 arcmsr_Write_data_2iop_wqbuffer(acb); 2811 /* has error report sensedata */ 2812 if(pccb->csio.sense_len) { 2813 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); 2814 /* Valid,ErrorCode */ 2815 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05; 2816 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */ 2817 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A; 2818 /* AdditionalSenseLength */ 2819 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20; 2820 /* AdditionalSenseCode */ 2821 } 2822 retvalue = ARCMSR_MESSAGE_FAIL; 2823 } else { 2824 my_empty_len = (wqbuf_firstindex-wqbuf_lastindex - 1) 2825 &(ARCMSR_MAX_QBUFFER - 1); 2826 if (my_empty_len >= user_len) { 2827 while (user_len > 0) { 2828 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex]; 2829 *pQbuffer = *ptmpuserbuffer; 2830 acb->wqbuf_lastindex++; 2831 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 2832 ptmpuserbuffer++; 2833 user_len--; 2834 } 2835 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) { 2836 acb->acb_flags &= 2837 ~ACB_F_MESSAGE_WQBUFFER_CLEARED; 2838 arcmsr_Write_data_2iop_wqbuffer(acb); 2839 } 2840 } else { 2841 /* has error report sensedata */ 2842 if(pccb->csio.sense_len) { 2843 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); 2844 /* Valid,ErrorCode */ 2845 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05; 2846 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */ 2847 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A; 2848 /* AdditionalSenseLength */ 2849 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20; 2850 /* AdditionalSenseCode */ 2851 } 2852 retvalue = ARCMSR_MESSAGE_FAIL; 2853 } 2854 } 2855 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2856 } 2857 break; 2858 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: { 2859 u_int8_t *pQbuffer = acb->rqbuffer; 2860 2861 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2862 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2863 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2864 arcmsr_iop_message_read(acb); 2865 } 2866 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 2867 acb->rqbuf_firstindex = 0; 2868 acb->rqbuf_lastindex = 0; 2869 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2870 pcmdmessagefld->cmdmessage.ReturnCode = 2871 ARCMSR_MESSAGE_RETURNCODE_OK; 2872 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2873 } 2874 break; 2875 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: { 2876 u_int8_t *pQbuffer = acb->wqbuffer; 2877 2878 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2879 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2880 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2881 arcmsr_iop_message_read(acb); 2882 } 2883 acb->acb_flags |= 2884 (ACB_F_MESSAGE_WQBUFFER_CLEARED | 2885 ACB_F_MESSAGE_WQBUFFER_READ); 2886 acb->wqbuf_firstindex = 0; 2887 acb->wqbuf_lastindex = 0; 2888 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2889 pcmdmessagefld->cmdmessage.ReturnCode = 2890 ARCMSR_MESSAGE_RETURNCODE_OK; 2891 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2892 } 2893 break; 2894 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: { 2895 u_int8_t *pQbuffer; 2896 2897 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2898 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2899 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2900 arcmsr_iop_message_read(acb); 2901 } 2902 acb->acb_flags |= 2903 (ACB_F_MESSAGE_WQBUFFER_CLEARED 2904 | ACB_F_MESSAGE_RQBUFFER_CLEARED 2905 | ACB_F_MESSAGE_WQBUFFER_READ); 2906 acb->rqbuf_firstindex = 0; 2907 acb->rqbuf_lastindex = 0; 2908 acb->wqbuf_firstindex = 0; 2909 acb->wqbuf_lastindex = 0; 2910 pQbuffer = acb->rqbuffer; 2911 memset(pQbuffer, 0, sizeof (struct QBUFFER)); 2912 pQbuffer = acb->wqbuffer; 2913 memset(pQbuffer, 0, sizeof (struct QBUFFER)); 2914 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2915 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2916 } 2917 break; 2918 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: { 2919 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F; 2920 } 2921 break; 2922 case ARCMSR_MESSAGE_SAY_HELLO: { 2923 int8_t *hello_string = "Hello! I am ARCMSR"; 2924 2925 memcpy(pcmdmessagefld->messagedatabuffer, hello_string 2926 , (int16_t)strlen(hello_string)); 2927 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2928 } 2929 break; 2930 case ARCMSR_MESSAGE_SAY_GOODBYE: 2931 arcmsr_iop_parking(acb); 2932 break; 2933 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: 2934 arcmsr_flush_adapter_cache(acb); 2935 break; 2936 default: 2937 retvalue = ARCMSR_MESSAGE_FAIL; 2938 } 2939 message_out: 2940 return (retvalue); 2941 } 2942 /* 2943 ********************************************************************* 2944 ********************************************************************* 2945 */ 2946 static void arcmsr_execute_srb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 2947 { 2948 struct CommandControlBlock *srb = (struct CommandControlBlock *)arg; 2949 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)srb->acb; 2950 union ccb *pccb; 2951 int target, lun; 2952 2953 pccb = srb->pccb; 2954 target = pccb->ccb_h.target_id; 2955 lun = pccb->ccb_h.target_lun; 2956 acb->pktRequestCount++; 2957 if(error != 0) { 2958 if(error != EFBIG) { 2959 printf("arcmsr%d: unexpected error %x" 2960 " returned from 'bus_dmamap_load' \n" 2961 , acb->pci_unit, error); 2962 } 2963 if((pccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_INPROG) { 2964 pccb->ccb_h.status |= CAM_REQ_TOO_BIG; 2965 } 2966 arcmsr_srb_complete(srb, 0); 2967 return; 2968 } 2969 if(nseg > ARCMSR_MAX_SG_ENTRIES) { 2970 pccb->ccb_h.status |= CAM_REQ_TOO_BIG; 2971 arcmsr_srb_complete(srb, 0); 2972 return; 2973 } 2974 if(acb->acb_flags & ACB_F_BUS_RESET) { 2975 printf("arcmsr%d: bus reset and return busy \n", acb->pci_unit); 2976 pccb->ccb_h.status |= CAM_SCSI_BUS_RESET; 2977 arcmsr_srb_complete(srb, 0); 2978 return; 2979 } 2980 if(acb->devstate[target][lun] == ARECA_RAID_GONE) { 2981 u_int8_t block_cmd, cmd; 2982 2983 cmd = scsiio_cdb_ptr(&pccb->csio)[0]; 2984 block_cmd = cmd & 0x0f; 2985 if(block_cmd == 0x08 || block_cmd == 0x0a) { 2986 printf("arcmsr%d:block 'read/write' command " 2987 "with gone raid volume Cmd=0x%2x, TargetId=%d, Lun=%d \n" 2988 , acb->pci_unit, cmd, target, lun); 2989 pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 2990 arcmsr_srb_complete(srb, 0); 2991 return; 2992 } 2993 } 2994 if((pccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_INPROG) { 2995 if(nseg != 0) { 2996 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap); 2997 } 2998 arcmsr_srb_complete(srb, 0); 2999 return; 3000 } 3001 if(acb->srboutstandingcount >= acb->maxOutstanding) { 3002 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) == 0) 3003 { 3004 xpt_freeze_simq(acb->psim, 1); 3005 acb->acb_flags |= ACB_F_CAM_DEV_QFRZN; 3006 } 3007 pccb->ccb_h.status &= ~CAM_SIM_QUEUED; 3008 pccb->ccb_h.status |= CAM_REQUEUE_REQ; 3009 arcmsr_srb_complete(srb, 0); 3010 return; 3011 } 3012 pccb->ccb_h.status |= CAM_SIM_QUEUED; 3013 arcmsr_build_srb(srb, dm_segs, nseg); 3014 arcmsr_post_srb(acb, srb); 3015 if (pccb->ccb_h.timeout != CAM_TIME_INFINITY) 3016 { 3017 arcmsr_callout_init(&srb->ccb_callout); 3018 callout_reset_sbt(&srb->ccb_callout, SBT_1MS * 3019 (pccb->ccb_h.timeout + (ARCMSR_TIMEOUT_DELAY * 1000)), 0, 3020 arcmsr_srb_timeout, srb, 0); 3021 srb->srb_flags |= SRB_FLAG_TIMER_START; 3022 } 3023 } 3024 /* 3025 ***************************************************************************************** 3026 ***************************************************************************************** 3027 */ 3028 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb) 3029 { 3030 struct CommandControlBlock *srb; 3031 struct AdapterControlBlock *acb = (struct AdapterControlBlock *) abortccb->ccb_h.arcmsr_ccbacb_ptr; 3032 u_int32_t intmask_org; 3033 int i = 0; 3034 3035 acb->num_aborts++; 3036 /* 3037 *************************************************************************** 3038 ** It is the upper layer do abort command this lock just prior to calling us. 3039 ** First determine if we currently own this command. 3040 ** Start by searching the device queue. If not found 3041 ** at all, and the system wanted us to just abort the 3042 ** command return success. 3043 *************************************************************************** 3044 */ 3045 if(acb->srboutstandingcount != 0) { 3046 /* disable all outbound interrupt */ 3047 intmask_org = arcmsr_disable_allintr(acb); 3048 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 3049 srb = acb->psrb_pool[i]; 3050 if(srb->srb_state == ARCMSR_SRB_START) { 3051 if(srb->pccb == abortccb) { 3052 srb->srb_state = ARCMSR_SRB_ABORTED; 3053 printf("arcmsr%d:scsi id=%d lun=%jx abort srb '%p'" 3054 "outstanding command \n" 3055 , acb->pci_unit, abortccb->ccb_h.target_id 3056 , (uintmax_t)abortccb->ccb_h.target_lun, srb); 3057 arcmsr_polling_srbdone(acb, srb); 3058 /* enable outbound Post Queue, outbound doorbell Interrupt */ 3059 arcmsr_enable_allintr(acb, intmask_org); 3060 return (TRUE); 3061 } 3062 } 3063 } 3064 /* enable outbound Post Queue, outbound doorbell Interrupt */ 3065 arcmsr_enable_allintr(acb, intmask_org); 3066 } 3067 return(FALSE); 3068 } 3069 /* 3070 **************************************************************************** 3071 **************************************************************************** 3072 */ 3073 static void arcmsr_bus_reset(struct AdapterControlBlock *acb) 3074 { 3075 int retry = 0; 3076 3077 acb->num_resets++; 3078 acb->acb_flags |= ACB_F_BUS_RESET; 3079 while(acb->srboutstandingcount != 0 && retry < 400) { 3080 arcmsr_interrupt(acb); 3081 UDELAY(25000); 3082 retry++; 3083 } 3084 arcmsr_iop_reset(acb); 3085 acb->acb_flags &= ~ACB_F_BUS_RESET; 3086 } 3087 /* 3088 ************************************************************************** 3089 ************************************************************************** 3090 */ 3091 static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb, 3092 union ccb *pccb) 3093 { 3094 if (pccb->ccb_h.target_lun) { 3095 pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 3096 xpt_done(pccb); 3097 return; 3098 } 3099 pccb->ccb_h.status |= CAM_REQ_CMP; 3100 switch (scsiio_cdb_ptr(&pccb->csio)[0]) { 3101 case INQUIRY: { 3102 unsigned char inqdata[36]; 3103 char *buffer = pccb->csio.data_ptr; 3104 3105 inqdata[0] = T_PROCESSOR; /* Periph Qualifier & Periph Dev Type */ 3106 inqdata[1] = 0; /* rem media bit & Dev Type Modifier */ 3107 inqdata[2] = 0; /* ISO, ECMA, & ANSI versions */ 3108 inqdata[3] = 0; 3109 inqdata[4] = 31; /* length of additional data */ 3110 inqdata[5] = 0; 3111 inqdata[6] = 0; 3112 inqdata[7] = 0; 3113 strncpy(&inqdata[8], "Areca ", 8); /* Vendor Identification */ 3114 strncpy(&inqdata[16], "RAID controller ", 16); /* Product Identification */ 3115 strncpy(&inqdata[32], "R001", 4); /* Product Revision */ 3116 memcpy(buffer, inqdata, sizeof(inqdata)); 3117 xpt_done(pccb); 3118 } 3119 break; 3120 case WRITE_BUFFER: 3121 case READ_BUFFER: { 3122 if (arcmsr_iop_message_xfer(acb, pccb)) { 3123 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 3124 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 3125 } 3126 xpt_done(pccb); 3127 } 3128 break; 3129 default: 3130 xpt_done(pccb); 3131 } 3132 } 3133 /* 3134 ********************************************************************* 3135 ********************************************************************* 3136 */ 3137 static void arcmsr_action(struct cam_sim *psim, union ccb *pccb) 3138 { 3139 struct AdapterControlBlock *acb; 3140 3141 acb = (struct AdapterControlBlock *) cam_sim_softc(psim); 3142 if(acb == NULL) { 3143 pccb->ccb_h.status |= CAM_REQ_INVALID; 3144 xpt_done(pccb); 3145 return; 3146 } 3147 switch (pccb->ccb_h.func_code) { 3148 case XPT_SCSI_IO: { 3149 struct CommandControlBlock *srb; 3150 int target = pccb->ccb_h.target_id; 3151 int error; 3152 3153 if (pccb->ccb_h.flags & CAM_CDB_PHYS) { 3154 pccb->ccb_h.status = CAM_REQ_INVALID; 3155 xpt_done(pccb); 3156 return; 3157 } 3158 3159 if(target == 16) { 3160 /* virtual device for iop message transfer */ 3161 arcmsr_handle_virtual_command(acb, pccb); 3162 return; 3163 } 3164 if((srb = arcmsr_get_freesrb(acb)) == NULL) { 3165 pccb->ccb_h.status |= CAM_RESRC_UNAVAIL; 3166 xpt_done(pccb); 3167 return; 3168 } 3169 pccb->ccb_h.arcmsr_ccbsrb_ptr = srb; 3170 pccb->ccb_h.arcmsr_ccbacb_ptr = acb; 3171 srb->pccb = pccb; 3172 error = bus_dmamap_load_ccb(acb->dm_segs_dmat 3173 , srb->dm_segs_dmamap 3174 , pccb 3175 , arcmsr_execute_srb, srb, /*flags*/0); 3176 if(error == EINPROGRESS) { 3177 xpt_freeze_simq(acb->psim, 1); 3178 pccb->ccb_h.status |= CAM_RELEASE_SIMQ; 3179 } 3180 break; 3181 } 3182 case XPT_PATH_INQ: { 3183 struct ccb_pathinq *cpi = &pccb->cpi; 3184 3185 cpi->version_num = 1; 3186 cpi->hba_inquiry = PI_SDTR_ABLE | PI_TAG_ABLE; 3187 cpi->target_sprt = 0; 3188 cpi->hba_misc = 0; 3189 cpi->hba_eng_cnt = 0; 3190 cpi->max_target = ARCMSR_MAX_TARGETID; /* 0-16 */ 3191 cpi->max_lun = ARCMSR_MAX_TARGETLUN; /* 0-7 */ 3192 cpi->initiator_id = ARCMSR_SCSI_INITIATOR_ID; /* 255 */ 3193 cpi->bus_id = cam_sim_bus(psim); 3194 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 3195 strlcpy(cpi->hba_vid, "ARCMSR", HBA_IDLEN); 3196 strlcpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN); 3197 cpi->unit_number = cam_sim_unit(psim); 3198 if(acb->adapter_bus_speed == ACB_BUS_SPEED_12G) 3199 cpi->base_transfer_speed = 1200000; 3200 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G) 3201 cpi->base_transfer_speed = 600000; 3202 else 3203 cpi->base_transfer_speed = 300000; 3204 if((acb->vendor_device_id == PCIDevVenIDARC1880) || 3205 (acb->vendor_device_id == PCIDevVenIDARC1884) || 3206 (acb->vendor_device_id == PCIDevVenIDARC1680) || 3207 (acb->vendor_device_id == PCIDevVenIDARC1214)) 3208 { 3209 cpi->transport = XPORT_SAS; 3210 cpi->transport_version = 0; 3211 cpi->protocol_version = SCSI_REV_SPC2; 3212 } 3213 else 3214 { 3215 cpi->transport = XPORT_SPI; 3216 cpi->transport_version = 2; 3217 cpi->protocol_version = SCSI_REV_2; 3218 } 3219 cpi->protocol = PROTO_SCSI; 3220 cpi->ccb_h.status |= CAM_REQ_CMP; 3221 xpt_done(pccb); 3222 break; 3223 } 3224 case XPT_ABORT: { 3225 union ccb *pabort_ccb; 3226 3227 pabort_ccb = pccb->cab.abort_ccb; 3228 switch (pabort_ccb->ccb_h.func_code) { 3229 case XPT_ACCEPT_TARGET_IO: 3230 case XPT_CONT_TARGET_IO: 3231 if(arcmsr_seek_cmd2abort(pabort_ccb)==TRUE) { 3232 pabort_ccb->ccb_h.status |= CAM_REQ_ABORTED; 3233 xpt_done(pabort_ccb); 3234 pccb->ccb_h.status |= CAM_REQ_CMP; 3235 } else { 3236 xpt_print_path(pabort_ccb->ccb_h.path); 3237 printf("Not found\n"); 3238 pccb->ccb_h.status |= CAM_PATH_INVALID; 3239 } 3240 break; 3241 case XPT_SCSI_IO: 3242 pccb->ccb_h.status |= CAM_UA_ABORT; 3243 break; 3244 default: 3245 pccb->ccb_h.status |= CAM_REQ_INVALID; 3246 break; 3247 } 3248 xpt_done(pccb); 3249 break; 3250 } 3251 case XPT_RESET_BUS: 3252 case XPT_RESET_DEV: { 3253 u_int32_t i; 3254 3255 arcmsr_bus_reset(acb); 3256 for (i=0; i < 500; i++) { 3257 DELAY(1000); 3258 } 3259 pccb->ccb_h.status |= CAM_REQ_CMP; 3260 xpt_done(pccb); 3261 break; 3262 } 3263 case XPT_TERM_IO: { 3264 pccb->ccb_h.status |= CAM_REQ_INVALID; 3265 xpt_done(pccb); 3266 break; 3267 } 3268 case XPT_GET_TRAN_SETTINGS: { 3269 struct ccb_trans_settings *cts; 3270 3271 if(pccb->ccb_h.target_id == 16) { 3272 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 3273 xpt_done(pccb); 3274 break; 3275 } 3276 cts = &pccb->cts; 3277 { 3278 struct ccb_trans_settings_scsi *scsi; 3279 struct ccb_trans_settings_spi *spi; 3280 struct ccb_trans_settings_sas *sas; 3281 3282 scsi = &cts->proto_specific.scsi; 3283 scsi->flags = CTS_SCSI_FLAGS_TAG_ENB; 3284 scsi->valid = CTS_SCSI_VALID_TQ; 3285 cts->protocol = PROTO_SCSI; 3286 3287 if((acb->vendor_device_id == PCIDevVenIDARC1880) || 3288 (acb->vendor_device_id == PCIDevVenIDARC1884) || 3289 (acb->vendor_device_id == PCIDevVenIDARC1680) || 3290 (acb->vendor_device_id == PCIDevVenIDARC1214)) 3291 { 3292 cts->protocol_version = SCSI_REV_SPC2; 3293 cts->transport_version = 0; 3294 cts->transport = XPORT_SAS; 3295 sas = &cts->xport_specific.sas; 3296 sas->valid = CTS_SAS_VALID_SPEED; 3297 if (acb->adapter_bus_speed == ACB_BUS_SPEED_12G) 3298 sas->bitrate = 1200000; 3299 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G) 3300 sas->bitrate = 600000; 3301 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_3G) 3302 sas->bitrate = 300000; 3303 } 3304 else 3305 { 3306 cts->protocol_version = SCSI_REV_2; 3307 cts->transport_version = 2; 3308 cts->transport = XPORT_SPI; 3309 spi = &cts->xport_specific.spi; 3310 spi->flags = CTS_SPI_FLAGS_DISC_ENB; 3311 if (acb->adapter_bus_speed == ACB_BUS_SPEED_6G) 3312 spi->sync_period = 1; 3313 else 3314 spi->sync_period = 2; 3315 spi->sync_offset = 32; 3316 spi->bus_width = MSG_EXT_WDTR_BUS_16_BIT; 3317 spi->valid = CTS_SPI_VALID_DISC 3318 | CTS_SPI_VALID_SYNC_RATE 3319 | CTS_SPI_VALID_SYNC_OFFSET 3320 | CTS_SPI_VALID_BUS_WIDTH; 3321 } 3322 } 3323 pccb->ccb_h.status |= CAM_REQ_CMP; 3324 xpt_done(pccb); 3325 break; 3326 } 3327 case XPT_SET_TRAN_SETTINGS: { 3328 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 3329 xpt_done(pccb); 3330 break; 3331 } 3332 case XPT_CALC_GEOMETRY: 3333 if(pccb->ccb_h.target_id == 16) { 3334 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 3335 xpt_done(pccb); 3336 break; 3337 } 3338 cam_calc_geometry(&pccb->ccg, 1); 3339 xpt_done(pccb); 3340 break; 3341 default: 3342 pccb->ccb_h.status |= CAM_REQ_INVALID; 3343 xpt_done(pccb); 3344 break; 3345 } 3346 } 3347 /* 3348 ********************************************************************** 3349 ********************************************************************** 3350 */ 3351 static void arcmsr_start_hba_bgrb(struct AdapterControlBlock *acb) 3352 { 3353 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3354 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3355 if(!arcmsr_hba_wait_msgint_ready(acb)) { 3356 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3357 } 3358 } 3359 /* 3360 ********************************************************************** 3361 ********************************************************************** 3362 */ 3363 static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb) 3364 { 3365 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3366 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3367 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_START_BGRB); 3368 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3369 printf( "arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3370 } 3371 } 3372 /* 3373 ********************************************************************** 3374 ********************************************************************** 3375 */ 3376 static void arcmsr_start_hbc_bgrb(struct AdapterControlBlock *acb) 3377 { 3378 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3379 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3380 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3381 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 3382 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3383 } 3384 } 3385 /* 3386 ********************************************************************** 3387 ********************************************************************** 3388 */ 3389 static void arcmsr_start_hbd_bgrb(struct AdapterControlBlock *acb) 3390 { 3391 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3392 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3393 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 3394 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3395 } 3396 } 3397 /* 3398 ********************************************************************** 3399 ********************************************************************** 3400 */ 3401 static void arcmsr_start_hbe_bgrb(struct AdapterControlBlock *acb) 3402 { 3403 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3404 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3405 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 3406 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 3407 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 3408 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3409 } 3410 } 3411 /* 3412 ********************************************************************** 3413 ********************************************************************** 3414 */ 3415 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb) 3416 { 3417 switch (acb->adapter_type) { 3418 case ACB_ADAPTER_TYPE_A: 3419 arcmsr_start_hba_bgrb(acb); 3420 break; 3421 case ACB_ADAPTER_TYPE_B: 3422 arcmsr_start_hbb_bgrb(acb); 3423 break; 3424 case ACB_ADAPTER_TYPE_C: 3425 arcmsr_start_hbc_bgrb(acb); 3426 break; 3427 case ACB_ADAPTER_TYPE_D: 3428 arcmsr_start_hbd_bgrb(acb); 3429 break; 3430 case ACB_ADAPTER_TYPE_E: 3431 case ACB_ADAPTER_TYPE_F: 3432 arcmsr_start_hbe_bgrb(acb); 3433 break; 3434 } 3435 } 3436 /* 3437 ********************************************************************** 3438 ** 3439 ********************************************************************** 3440 */ 3441 static void arcmsr_polling_hba_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3442 { 3443 struct CommandControlBlock *srb; 3444 u_int32_t flag_srb, outbound_intstatus, poll_srb_done=0, poll_count=0; 3445 u_int16_t error; 3446 3447 polling_ccb_retry: 3448 poll_count++; 3449 outbound_intstatus=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 3450 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus); /*clear interrupt*/ 3451 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3452 while(1) { 3453 if((flag_srb = CHIP_REG_READ32(HBA_MessageUnit, 3454 0, outbound_queueport)) == 0xFFFFFFFF) { 3455 if(poll_srb_done) { 3456 break;/*chip FIFO no ccb for completion already*/ 3457 } else { 3458 UDELAY(25000); 3459 if ((poll_count > 100) && (poll_srb != NULL)) { 3460 break; 3461 } 3462 goto polling_ccb_retry; 3463 } 3464 } 3465 /* check if command done with no error*/ 3466 srb = (struct CommandControlBlock *) 3467 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 3468 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 3469 poll_srb_done = (srb == poll_srb) ? 1:0; 3470 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3471 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3472 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'" 3473 "poll command abort successfully \n" 3474 , acb->pci_unit 3475 , srb->pccb->ccb_h.target_id 3476 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3477 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3478 arcmsr_srb_complete(srb, 1); 3479 continue; 3480 } 3481 printf("arcmsr%d: polling get an illegal srb command done srb='%p'" 3482 "srboutstandingcount=%d \n" 3483 , acb->pci_unit 3484 , srb, acb->srboutstandingcount); 3485 continue; 3486 } 3487 arcmsr_report_srb_state(acb, srb, error); 3488 } /*drain reply FIFO*/ 3489 } 3490 /* 3491 ********************************************************************** 3492 ** 3493 ********************************************************************** 3494 */ 3495 static void arcmsr_polling_hbb_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3496 { 3497 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3498 struct CommandControlBlock *srb; 3499 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3500 int index; 3501 u_int16_t error; 3502 3503 polling_ccb_retry: 3504 poll_count++; 3505 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */ 3506 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3507 while(1) { 3508 index = phbbmu->doneq_index; 3509 if((flag_srb = phbbmu->done_qbuffer[index]) == 0) { 3510 if(poll_srb_done) { 3511 break;/*chip FIFO no ccb for completion already*/ 3512 } else { 3513 UDELAY(25000); 3514 if ((poll_count > 100) && (poll_srb != NULL)) { 3515 break; 3516 } 3517 goto polling_ccb_retry; 3518 } 3519 } 3520 phbbmu->done_qbuffer[index] = 0; 3521 index++; 3522 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 3523 phbbmu->doneq_index = index; 3524 /* check if command done with no error*/ 3525 srb = (struct CommandControlBlock *) 3526 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 3527 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 3528 poll_srb_done = (srb == poll_srb) ? 1:0; 3529 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3530 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3531 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'" 3532 "poll command abort successfully \n" 3533 , acb->pci_unit 3534 , srb->pccb->ccb_h.target_id 3535 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3536 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3537 arcmsr_srb_complete(srb, 1); 3538 continue; 3539 } 3540 printf("arcmsr%d: polling get an illegal srb command done srb='%p'" 3541 "srboutstandingcount=%d \n" 3542 , acb->pci_unit 3543 , srb, acb->srboutstandingcount); 3544 continue; 3545 } 3546 arcmsr_report_srb_state(acb, srb, error); 3547 } /*drain reply FIFO*/ 3548 } 3549 /* 3550 ********************************************************************** 3551 ** 3552 ********************************************************************** 3553 */ 3554 static void arcmsr_polling_hbc_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3555 { 3556 struct CommandControlBlock *srb; 3557 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3558 u_int16_t error; 3559 3560 polling_ccb_retry: 3561 poll_count++; 3562 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3563 while(1) { 3564 if(!(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)) { 3565 if(poll_srb_done) { 3566 break;/*chip FIFO no ccb for completion already*/ 3567 } else { 3568 UDELAY(25000); 3569 if ((poll_count > 100) && (poll_srb != NULL)) { 3570 break; 3571 } 3572 if (acb->srboutstandingcount == 0) { 3573 break; 3574 } 3575 goto polling_ccb_retry; 3576 } 3577 } 3578 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 3579 /* check if command done with no error*/ 3580 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/ 3581 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE; 3582 if (poll_srb != NULL) 3583 poll_srb_done = (srb == poll_srb) ? 1:0; 3584 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3585 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3586 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n" 3587 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3588 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3589 arcmsr_srb_complete(srb, 1); 3590 continue; 3591 } 3592 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 3593 , acb->pci_unit, srb, acb->srboutstandingcount); 3594 continue; 3595 } 3596 arcmsr_report_srb_state(acb, srb, error); 3597 } /*drain reply FIFO*/ 3598 } 3599 /* 3600 ********************************************************************** 3601 ** 3602 ********************************************************************** 3603 */ 3604 static void arcmsr_polling_hbd_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3605 { 3606 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 3607 struct CommandControlBlock *srb; 3608 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3609 u_int32_t outbound_write_pointer; 3610 u_int16_t error, doneq_index; 3611 3612 polling_ccb_retry: 3613 poll_count++; 3614 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3615 while(1) { 3616 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 3617 doneq_index = phbdmu->doneq_index; 3618 if ((outbound_write_pointer & 0xFF) == (doneq_index & 0xFF)) { 3619 if(poll_srb_done) { 3620 break;/*chip FIFO no ccb for completion already*/ 3621 } else { 3622 UDELAY(25000); 3623 if ((poll_count > 100) && (poll_srb != NULL)) { 3624 break; 3625 } 3626 if (acb->srboutstandingcount == 0) { 3627 break; 3628 } 3629 goto polling_ccb_retry; 3630 } 3631 } 3632 doneq_index = arcmsr_get_doneq_index(phbdmu); 3633 flag_srb = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow; 3634 /* check if command done with no error*/ 3635 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/ 3636 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 3637 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index); 3638 if (poll_srb != NULL) 3639 poll_srb_done = (srb == poll_srb) ? 1:0; 3640 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3641 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3642 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n" 3643 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3644 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3645 arcmsr_srb_complete(srb, 1); 3646 continue; 3647 } 3648 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 3649 , acb->pci_unit, srb, acb->srboutstandingcount); 3650 continue; 3651 } 3652 arcmsr_report_srb_state(acb, srb, error); 3653 } /*drain reply FIFO*/ 3654 } 3655 /* 3656 ********************************************************************** 3657 ** 3658 ********************************************************************** 3659 */ 3660 static void arcmsr_polling_hbe_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3661 { 3662 struct CommandControlBlock *srb; 3663 u_int32_t poll_srb_done=0, poll_count=0, doneq_index; 3664 u_int16_t error, cmdSMID; 3665 3666 polling_ccb_retry: 3667 poll_count++; 3668 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3669 while(1) { 3670 doneq_index = acb->doneq_index; 3671 if((CHIP_REG_READ32(HBE_MessageUnit, 0, reply_post_producer_index) & 0xFFFF) == doneq_index) { 3672 if(poll_srb_done) { 3673 break;/*chip FIFO no ccb for completion already*/ 3674 } else { 3675 UDELAY(25000); 3676 if ((poll_count > 100) && (poll_srb != NULL)) { 3677 break; 3678 } 3679 if (acb->srboutstandingcount == 0) { 3680 break; 3681 } 3682 goto polling_ccb_retry; 3683 } 3684 } 3685 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID; 3686 doneq_index++; 3687 if (doneq_index >= acb->completionQ_entry) 3688 doneq_index = 0; 3689 acb->doneq_index = doneq_index; 3690 srb = acb->psrb_pool[cmdSMID]; 3691 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 3692 if (poll_srb != NULL) 3693 poll_srb_done = (srb == poll_srb) ? 1:0; 3694 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3695 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3696 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n" 3697 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3698 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3699 arcmsr_srb_complete(srb, 1); 3700 continue; 3701 } 3702 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 3703 , acb->pci_unit, srb, acb->srboutstandingcount); 3704 continue; 3705 } 3706 arcmsr_report_srb_state(acb, srb, error); 3707 } /*drain reply FIFO*/ 3708 CHIP_REG_WRITE32(HBE_MessageUnit, 0, reply_post_producer_index, doneq_index); 3709 } 3710 /* 3711 ********************************************************************** 3712 ********************************************************************** 3713 */ 3714 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3715 { 3716 switch (acb->adapter_type) { 3717 case ACB_ADAPTER_TYPE_A: 3718 arcmsr_polling_hba_srbdone(acb, poll_srb); 3719 break; 3720 case ACB_ADAPTER_TYPE_B: 3721 arcmsr_polling_hbb_srbdone(acb, poll_srb); 3722 break; 3723 case ACB_ADAPTER_TYPE_C: 3724 arcmsr_polling_hbc_srbdone(acb, poll_srb); 3725 break; 3726 case ACB_ADAPTER_TYPE_D: 3727 arcmsr_polling_hbd_srbdone(acb, poll_srb); 3728 break; 3729 case ACB_ADAPTER_TYPE_E: 3730 case ACB_ADAPTER_TYPE_F: 3731 arcmsr_polling_hbe_srbdone(acb, poll_srb); 3732 break; 3733 } 3734 } 3735 /* 3736 ********************************************************************** 3737 ********************************************************************** 3738 */ 3739 static void arcmsr_get_hba_config(struct AdapterControlBlock *acb) 3740 { 3741 char *acb_firm_model = acb->firm_model; 3742 char *acb_firm_version = acb->firm_version; 3743 char *acb_device_map = acb->device_map; 3744 size_t iop_firm_model = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3745 size_t iop_firm_version = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3746 size_t iop_device_map = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3747 int i; 3748 3749 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3750 if(!arcmsr_hba_wait_msgint_ready(acb)) { 3751 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3752 } 3753 i = 0; 3754 while(i < 8) { 3755 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3756 /* 8 bytes firm_model, 15, 60-67*/ 3757 acb_firm_model++; 3758 i++; 3759 } 3760 i=0; 3761 while(i < 16) { 3762 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3763 /* 16 bytes firm_version, 17, 68-83*/ 3764 acb_firm_version++; 3765 i++; 3766 } 3767 i=0; 3768 while(i < 16) { 3769 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3770 acb_device_map++; 3771 i++; 3772 } 3773 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3774 acb->firm_request_len = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3775 acb->firm_numbers_queue = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3776 acb->firm_sdram_size = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3777 acb->firm_ide_channels = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3778 acb->firm_cfg_version = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3779 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 3780 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 3781 else 3782 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3783 } 3784 /* 3785 ********************************************************************** 3786 ********************************************************************** 3787 */ 3788 static void arcmsr_get_hbb_config(struct AdapterControlBlock *acb) 3789 { 3790 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3791 char *acb_firm_model = acb->firm_model; 3792 char *acb_firm_version = acb->firm_version; 3793 char *acb_device_map = acb->device_map; 3794 size_t iop_firm_model = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3795 size_t iop_firm_version = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3796 size_t iop_device_map = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3797 int i; 3798 3799 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG); 3800 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3801 printf( "arcmsr%d: wait" "'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3802 } 3803 i = 0; 3804 while(i < 8) { 3805 *acb_firm_model = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_model+i); 3806 /* 8 bytes firm_model, 15, 60-67*/ 3807 acb_firm_model++; 3808 i++; 3809 } 3810 i = 0; 3811 while(i < 16) { 3812 *acb_firm_version = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_version+i); 3813 /* 16 bytes firm_version, 17, 68-83*/ 3814 acb_firm_version++; 3815 i++; 3816 } 3817 i = 0; 3818 while(i < 16) { 3819 *acb_device_map = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_device_map+i); 3820 acb_device_map++; 3821 i++; 3822 } 3823 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3824 acb->firm_request_len = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3825 acb->firm_numbers_queue = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3826 acb->firm_sdram_size = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3827 acb->firm_ide_channels = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3828 acb->firm_cfg_version = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3829 if(acb->firm_numbers_queue > ARCMSR_MAX_HBB_POSTQUEUE) 3830 acb->maxOutstanding = ARCMSR_MAX_HBB_POSTQUEUE - 1; 3831 else 3832 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3833 } 3834 /* 3835 ********************************************************************** 3836 ********************************************************************** 3837 */ 3838 static void arcmsr_get_hbc_config(struct AdapterControlBlock *acb) 3839 { 3840 char *acb_firm_model = acb->firm_model; 3841 char *acb_firm_version = acb->firm_version; 3842 char *acb_device_map = acb->device_map; 3843 size_t iop_firm_model = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3844 size_t iop_firm_version = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3845 size_t iop_device_map = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3846 int i; 3847 3848 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3849 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3850 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 3851 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3852 } 3853 i = 0; 3854 while(i < 8) { 3855 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3856 /* 8 bytes firm_model, 15, 60-67*/ 3857 acb_firm_model++; 3858 i++; 3859 } 3860 i = 0; 3861 while(i < 16) { 3862 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3863 /* 16 bytes firm_version, 17, 68-83*/ 3864 acb_firm_version++; 3865 i++; 3866 } 3867 i = 0; 3868 while(i < 16) { 3869 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3870 acb_device_map++; 3871 i++; 3872 } 3873 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3874 acb->firm_request_len = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3875 acb->firm_numbers_queue = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3876 acb->firm_sdram_size = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3877 acb->firm_ide_channels = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3878 acb->firm_cfg_version = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3879 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 3880 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 3881 else 3882 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3883 } 3884 /* 3885 ********************************************************************** 3886 ********************************************************************** 3887 */ 3888 static void arcmsr_get_hbd_config(struct AdapterControlBlock *acb) 3889 { 3890 char *acb_firm_model = acb->firm_model; 3891 char *acb_firm_version = acb->firm_version; 3892 char *acb_device_map = acb->device_map; 3893 size_t iop_firm_model = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3894 size_t iop_firm_version = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3895 size_t iop_device_map = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3896 int i; 3897 3898 if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) 3899 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR); 3900 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3901 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 3902 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3903 } 3904 i = 0; 3905 while(i < 8) { 3906 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3907 /* 8 bytes firm_model, 15, 60-67*/ 3908 acb_firm_model++; 3909 i++; 3910 } 3911 i = 0; 3912 while(i < 16) { 3913 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3914 /* 16 bytes firm_version, 17, 68-83*/ 3915 acb_firm_version++; 3916 i++; 3917 } 3918 i = 0; 3919 while(i < 16) { 3920 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3921 acb_device_map++; 3922 i++; 3923 } 3924 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3925 acb->firm_request_len = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3926 acb->firm_numbers_queue = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3927 acb->firm_sdram_size = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3928 acb->firm_ide_channels = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3929 acb->firm_cfg_version = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3930 if(acb->firm_numbers_queue > ARCMSR_MAX_HBD_POSTQUEUE) 3931 acb->maxOutstanding = ARCMSR_MAX_HBD_POSTQUEUE - 1; 3932 else 3933 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3934 } 3935 /* 3936 ********************************************************************** 3937 ********************************************************************** 3938 */ 3939 static void arcmsr_get_hbe_config(struct AdapterControlBlock *acb) 3940 { 3941 char *acb_firm_model = acb->firm_model; 3942 char *acb_firm_version = acb->firm_version; 3943 char *acb_device_map = acb->device_map; 3944 size_t iop_firm_model = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3945 size_t iop_firm_version = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3946 size_t iop_device_map = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3947 int i; 3948 3949 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3950 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 3951 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 3952 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 3953 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3954 } 3955 3956 i = 0; 3957 while(i < 8) { 3958 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3959 /* 8 bytes firm_model, 15, 60-67*/ 3960 acb_firm_model++; 3961 i++; 3962 } 3963 i = 0; 3964 while(i < 16) { 3965 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3966 /* 16 bytes firm_version, 17, 68-83*/ 3967 acb_firm_version++; 3968 i++; 3969 } 3970 i = 0; 3971 while(i < 16) { 3972 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3973 acb_device_map++; 3974 i++; 3975 } 3976 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3977 acb->firm_request_len = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3978 acb->firm_numbers_queue = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3979 acb->firm_sdram_size = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3980 acb->firm_ide_channels = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3981 acb->firm_cfg_version = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3982 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 3983 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 3984 else 3985 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3986 } 3987 /* 3988 ********************************************************************** 3989 ********************************************************************** 3990 */ 3991 static void arcmsr_get_hbf_config(struct AdapterControlBlock *acb) 3992 { 3993 u_int32_t *acb_firm_model = (u_int32_t *)acb->firm_model; 3994 u_int32_t *acb_firm_version = (u_int32_t *)acb->firm_version; 3995 u_int32_t *acb_device_map = (u_int32_t *)acb->device_map; 3996 size_t iop_firm_model = ARCMSR_FW_MODEL_OFFSET; /*firm_model,15,60-67*/ 3997 size_t iop_firm_version = ARCMSR_FW_VERS_OFFSET; /*firm_version,17,68-83*/ 3998 size_t iop_device_map = ARCMSR_FW_DEVMAP_OFFSET; 3999 int i; 4000 4001 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 4002 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 4003 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 4004 if(!arcmsr_hbe_wait_msgint_ready(acb)) 4005 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 4006 4007 i = 0; 4008 while(i < 2) { 4009 *acb_firm_model = acb->msgcode_rwbuffer[iop_firm_model]; 4010 /* 8 bytes firm_model, 15, 60-67*/ 4011 acb_firm_model++; 4012 iop_firm_model++; 4013 i++; 4014 } 4015 i = 0; 4016 while(i < 4) { 4017 *acb_firm_version = acb->msgcode_rwbuffer[iop_firm_version]; 4018 /* 16 bytes firm_version, 17, 68-83*/ 4019 acb_firm_version++; 4020 iop_firm_version++; 4021 i++; 4022 } 4023 i = 0; 4024 while(i < 4) { 4025 *acb_device_map = acb->msgcode_rwbuffer[iop_device_map]; 4026 acb_device_map++; 4027 iop_device_map++; 4028 i++; 4029 } 4030 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 4031 acb->firm_request_len = acb->msgcode_rwbuffer[1]; /*firm_request_len, 1, 04-07*/ 4032 acb->firm_numbers_queue = acb->msgcode_rwbuffer[2]; /*firm_numbers_queue, 2, 08-11*/ 4033 acb->firm_sdram_size = acb->msgcode_rwbuffer[3]; /*firm_sdram_size, 3, 12-15*/ 4034 acb->firm_ide_channels = acb->msgcode_rwbuffer[4]; /*firm_ide_channels, 4, 16-19*/ 4035 acb->firm_cfg_version = acb->msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]; /*firm_cfg_version, 25*/ 4036 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 4037 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 4038 else 4039 acb->maxOutstanding = acb->firm_numbers_queue - 1; 4040 } 4041 /* 4042 ********************************************************************** 4043 ********************************************************************** 4044 */ 4045 static void arcmsr_get_firmware_spec(struct AdapterControlBlock *acb) 4046 { 4047 switch (acb->adapter_type) { 4048 case ACB_ADAPTER_TYPE_A: 4049 arcmsr_get_hba_config(acb); 4050 break; 4051 case ACB_ADAPTER_TYPE_B: 4052 arcmsr_get_hbb_config(acb); 4053 break; 4054 case ACB_ADAPTER_TYPE_C: 4055 arcmsr_get_hbc_config(acb); 4056 break; 4057 case ACB_ADAPTER_TYPE_D: 4058 arcmsr_get_hbd_config(acb); 4059 break; 4060 case ACB_ADAPTER_TYPE_E: 4061 arcmsr_get_hbe_config(acb); 4062 break; 4063 case ACB_ADAPTER_TYPE_F: 4064 arcmsr_get_hbf_config(acb); 4065 break; 4066 } 4067 } 4068 /* 4069 ********************************************************************** 4070 ********************************************************************** 4071 */ 4072 static void arcmsr_wait_firmware_ready( struct AdapterControlBlock *acb) 4073 { 4074 int timeout=0; 4075 4076 switch (acb->adapter_type) { 4077 case ACB_ADAPTER_TYPE_A: { 4078 while ((CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0) 4079 { 4080 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 4081 { 4082 printf( "arcmsr%d:timed out waiting for firmware \n", acb->pci_unit); 4083 return; 4084 } 4085 UDELAY(15000); /* wait 15 milli-seconds */ 4086 } 4087 } 4088 break; 4089 case ACB_ADAPTER_TYPE_B: { 4090 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4091 while ((READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & ARCMSR_MESSAGE_FIRMWARE_OK) == 0) 4092 { 4093 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 4094 { 4095 printf( "arcmsr%d: timed out waiting for firmware \n", acb->pci_unit); 4096 return; 4097 } 4098 UDELAY(15000); /* wait 15 milli-seconds */ 4099 } 4100 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 4101 } 4102 break; 4103 case ACB_ADAPTER_TYPE_C: { 4104 while ((CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0) 4105 { 4106 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 4107 { 4108 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 4109 return; 4110 } 4111 UDELAY(15000); /* wait 15 milli-seconds */ 4112 } 4113 } 4114 break; 4115 case ACB_ADAPTER_TYPE_D: { 4116 while ((CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK) == 0) 4117 { 4118 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 4119 { 4120 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 4121 return; 4122 } 4123 UDELAY(15000); /* wait 15 milli-seconds */ 4124 } 4125 } 4126 break; 4127 case ACB_ADAPTER_TYPE_E: 4128 case ACB_ADAPTER_TYPE_F: { 4129 while ((CHIP_REG_READ32(HBE_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK) == 0) 4130 { 4131 if (timeout++ > 4000) /* (4000*15)/1000 = 60 sec */ 4132 { 4133 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 4134 return; 4135 } 4136 UDELAY(15000); /* wait 15 milli-seconds */ 4137 } 4138 } 4139 break; 4140 } 4141 } 4142 /* 4143 ********************************************************************** 4144 ********************************************************************** 4145 */ 4146 static void arcmsr_clear_doorbell_queue_buffer( struct AdapterControlBlock *acb) 4147 { 4148 u_int32_t outbound_doorbell; 4149 4150 switch (acb->adapter_type) { 4151 case ACB_ADAPTER_TYPE_A: { 4152 /* empty doorbell Qbuffer if door bell ringed */ 4153 outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell); 4154 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */ 4155 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK); 4156 } 4157 break; 4158 case ACB_ADAPTER_TYPE_B: { 4159 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4160 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN);/*clear interrupt and message state*/ 4161 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK); 4162 /* let IOP know data has been read */ 4163 } 4164 break; 4165 case ACB_ADAPTER_TYPE_C: { 4166 /* empty doorbell Qbuffer if door bell ringed */ 4167 outbound_doorbell = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell); 4168 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell); /*clear doorbell interrupt */ 4169 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK); 4170 CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell_clear); /* Dummy read to force pci flush */ 4171 CHIP_REG_READ32(HBC_MessageUnit, 0, inbound_doorbell); /* Dummy read to force pci flush */ 4172 } 4173 break; 4174 case ACB_ADAPTER_TYPE_D: { 4175 /* empty doorbell Qbuffer if door bell ringed */ 4176 outbound_doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell); 4177 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */ 4178 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ); 4179 } 4180 break; 4181 case ACB_ADAPTER_TYPE_E: 4182 case ACB_ADAPTER_TYPE_F: { 4183 /* empty doorbell Qbuffer if door bell ringed */ 4184 acb->in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell); 4185 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /*clear doorbell interrupt */ 4186 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK; 4187 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 4188 } 4189 break; 4190 } 4191 } 4192 /* 4193 ************************************************************************ 4194 ************************************************************************ 4195 */ 4196 static u_int32_t arcmsr_iop_confirm(struct AdapterControlBlock *acb) 4197 { 4198 unsigned long srb_phyaddr; 4199 u_int32_t srb_phyaddr_hi32; 4200 u_int32_t srb_phyaddr_lo32; 4201 4202 /* 4203 ******************************************************************** 4204 ** here we need to tell iop 331 our freesrb.HighPart 4205 ** if freesrb.HighPart is not zero 4206 ******************************************************************** 4207 */ 4208 srb_phyaddr = (unsigned long) acb->srb_phyaddr.phyaddr; 4209 srb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high; 4210 srb_phyaddr_lo32 = acb->srb_phyaddr.B.phyadd_low; 4211 switch (acb->adapter_type) { 4212 case ACB_ADAPTER_TYPE_A: { 4213 if(srb_phyaddr_hi32 != 0) { 4214 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 4215 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 4216 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4217 if(!arcmsr_hba_wait_msgint_ready(acb)) { 4218 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4219 return FALSE; 4220 } 4221 } 4222 } 4223 break; 4224 /* 4225 *********************************************************************** 4226 ** if adapter type B, set window of "post command Q" 4227 *********************************************************************** 4228 */ 4229 case ACB_ADAPTER_TYPE_B: { 4230 u_int32_t post_queue_phyaddr; 4231 struct HBB_MessageUnit *phbbmu; 4232 4233 phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4234 phbbmu->postq_index = 0; 4235 phbbmu->doneq_index = 0; 4236 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_SET_POST_WINDOW); 4237 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 4238 printf( "arcmsr%d: 'set window of post command Q' timeout\n", acb->pci_unit); 4239 return FALSE; 4240 } 4241 post_queue_phyaddr = srb_phyaddr + ARCMSR_SRBS_POOL_SIZE 4242 + offsetof(struct HBB_MessageUnit, post_qbuffer); 4243 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */ 4244 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1], srb_phyaddr_hi32); /* normal should be zero */ 4245 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ size (256+8)*4 */ 4246 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3], post_queue_phyaddr+1056); /* doneQ size (256+8)*4 */ 4247 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4], 1056); /* srb maxQ size must be --> [(256+8)*4] */ 4248 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_SET_CONFIG); 4249 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 4250 printf( "arcmsr%d: 'set command Q window' timeout \n", acb->pci_unit); 4251 return FALSE; 4252 } 4253 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_START_DRIVER_MODE); 4254 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 4255 printf( "arcmsr%d: 'start diver mode' timeout \n", acb->pci_unit); 4256 return FALSE; 4257 } 4258 } 4259 break; 4260 case ACB_ADAPTER_TYPE_C: { 4261 if(srb_phyaddr_hi32 != 0) { 4262 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 4263 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 4264 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4265 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 4266 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 4267 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4268 return FALSE; 4269 } 4270 } 4271 } 4272 break; 4273 case ACB_ADAPTER_TYPE_D: { 4274 u_int32_t post_queue_phyaddr, done_queue_phyaddr; 4275 struct HBD_MessageUnit0 *phbdmu; 4276 4277 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 4278 phbdmu->postq_index = 0; 4279 phbdmu->doneq_index = 0x40FF; 4280 post_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE 4281 + offsetof(struct HBD_MessageUnit0, post_qbuffer); 4282 done_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE 4283 + offsetof(struct HBD_MessageUnit0, done_qbuffer); 4284 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */ 4285 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 4286 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ base */ 4287 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[3], done_queue_phyaddr); /* doneQ base */ 4288 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[4], 0x100); 4289 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4290 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 4291 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4292 return FALSE; 4293 } 4294 } 4295 break; 4296 case ACB_ADAPTER_TYPE_E: { 4297 u_int32_t cdb_phyaddr_lo32; 4298 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + offsetof(struct CommandControlBlock, arcmsr_cdb); 4299 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 4300 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[1], ARCMSR_SIGNATURE_1884); 4301 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[2], cdb_phyaddr_lo32); 4302 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[3], srb_phyaddr_hi32); 4303 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[4], SRB_SIZE); 4304 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE; 4305 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[5], cdb_phyaddr_lo32); 4306 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[6], srb_phyaddr_hi32); 4307 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[7], COMPLETION_Q_POOL_SIZE); 4308 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4309 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 4310 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 4311 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 4312 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4313 return FALSE; 4314 } 4315 } 4316 break; 4317 case ACB_ADAPTER_TYPE_F: { 4318 u_int32_t cdb_phyaddr_lo32; 4319 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + offsetof(struct CommandControlBlock, arcmsr_cdb); 4320 acb->msgcode_rwbuffer[0] = ARCMSR_SIGNATURE_SET_CONFIG; 4321 acb->msgcode_rwbuffer[1] = ARCMSR_SIGNATURE_1886; 4322 acb->msgcode_rwbuffer[2] = cdb_phyaddr_lo32; 4323 acb->msgcode_rwbuffer[3] = srb_phyaddr_hi32; 4324 acb->msgcode_rwbuffer[4] = SRB_SIZE; 4325 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE; 4326 acb->msgcode_rwbuffer[5] = cdb_phyaddr_lo32; 4327 acb->msgcode_rwbuffer[6] = srb_phyaddr_hi32; 4328 acb->msgcode_rwbuffer[7] = COMPLETION_Q_POOL_SIZE; 4329 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4330 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 4331 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 4332 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 4333 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4334 return FALSE; 4335 } 4336 } 4337 break; 4338 } 4339 return (TRUE); 4340 } 4341 /* 4342 ************************************************************************ 4343 ************************************************************************ 4344 */ 4345 static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb) 4346 { 4347 if (acb->adapter_type == ACB_ADAPTER_TYPE_B) 4348 { 4349 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4350 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_ACTIVE_EOI_MODE); 4351 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 4352 printf( "arcmsr%d: 'iop enable eoi mode' timeout \n", acb->pci_unit); 4353 return; 4354 } 4355 } 4356 } 4357 /* 4358 ********************************************************************** 4359 ********************************************************************** 4360 */ 4361 static void arcmsr_iop_init(struct AdapterControlBlock *acb) 4362 { 4363 u_int32_t intmask_org; 4364 4365 /* disable all outbound interrupt */ 4366 intmask_org = arcmsr_disable_allintr(acb); 4367 arcmsr_wait_firmware_ready(acb); 4368 arcmsr_iop_confirm(acb); 4369 arcmsr_get_firmware_spec(acb); 4370 /*start background rebuild*/ 4371 arcmsr_start_adapter_bgrb(acb); 4372 /* empty doorbell Qbuffer if door bell ringed */ 4373 arcmsr_clear_doorbell_queue_buffer(acb); 4374 arcmsr_enable_eoi_mode(acb); 4375 /* enable outbound Post Queue, outbound doorbell Interrupt */ 4376 arcmsr_enable_allintr(acb, intmask_org); 4377 acb->acb_flags |= ACB_F_IOP_INITED; 4378 } 4379 /* 4380 ********************************************************************** 4381 ********************************************************************** 4382 */ 4383 static void arcmsr_map_free_srb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4384 { 4385 struct AdapterControlBlock *acb = arg; 4386 struct CommandControlBlock *srb_tmp; 4387 u_int32_t i; 4388 unsigned long srb_phyaddr = (unsigned long)segs->ds_addr; 4389 4390 acb->srb_phyaddr.phyaddr = srb_phyaddr; 4391 srb_tmp = (struct CommandControlBlock *)acb->uncacheptr; 4392 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 4393 if(bus_dmamap_create(acb->dm_segs_dmat, 4394 /*flags*/0, &srb_tmp->dm_segs_dmamap) != 0) { 4395 acb->acb_flags |= ACB_F_MAPFREESRB_FAILD; 4396 printf("arcmsr%d:" 4397 " srb dmamap bus_dmamap_create error\n", acb->pci_unit); 4398 return; 4399 } 4400 if((acb->adapter_type == ACB_ADAPTER_TYPE_C) || (acb->adapter_type == ACB_ADAPTER_TYPE_D) 4401 || (acb->adapter_type == ACB_ADAPTER_TYPE_E) || (acb->adapter_type == ACB_ADAPTER_TYPE_F)) 4402 { 4403 srb_tmp->cdb_phyaddr_low = srb_phyaddr; 4404 srb_tmp->cdb_phyaddr_high = (u_int32_t)((srb_phyaddr >> 16) >> 16); 4405 } 4406 else 4407 srb_tmp->cdb_phyaddr_low = srb_phyaddr >> 5; 4408 srb_tmp->acb = acb; 4409 srb_tmp->smid = i << 16; 4410 acb->srbworkingQ[i] = acb->psrb_pool[i] = srb_tmp; 4411 srb_phyaddr = srb_phyaddr + SRB_SIZE; 4412 srb_tmp = (struct CommandControlBlock *)((unsigned long)srb_tmp + SRB_SIZE); 4413 } 4414 if (acb->adapter_type == ACB_ADAPTER_TYPE_E) 4415 acb->pCompletionQ = (pCompletion_Q)srb_tmp; 4416 else if (acb->adapter_type == ACB_ADAPTER_TYPE_F) { 4417 acb->pCompletionQ = (pCompletion_Q)srb_tmp; 4418 acb->completeQ_phys = srb_phyaddr; 4419 memset(acb->pCompletionQ, 0xff, COMPLETION_Q_POOL_SIZE); 4420 acb->message_wbuffer = (u_int32_t *)((unsigned long)acb->pCompletionQ + COMPLETION_Q_POOL_SIZE); 4421 acb->message_rbuffer = (u_int32_t *)((unsigned long)acb->message_wbuffer + 0x100); 4422 acb->msgcode_rwbuffer = (u_int32_t *)((unsigned long)acb->message_wbuffer + 0x200); 4423 memset((void *)acb->message_wbuffer, 0, MESG_RW_BUFFER_SIZE); 4424 } 4425 acb->vir2phy_offset = (unsigned long)srb_tmp - (unsigned long)srb_phyaddr; 4426 } 4427 /* 4428 ************************************************************************ 4429 ************************************************************************ 4430 */ 4431 static void arcmsr_free_resource(struct AdapterControlBlock *acb) 4432 { 4433 /* remove the control device */ 4434 if(acb->ioctl_dev != NULL) { 4435 destroy_dev(acb->ioctl_dev); 4436 } 4437 bus_dmamap_unload(acb->srb_dmat, acb->srb_dmamap); 4438 bus_dmamap_destroy(acb->srb_dmat, acb->srb_dmamap); 4439 bus_dma_tag_destroy(acb->srb_dmat); 4440 bus_dma_tag_destroy(acb->dm_segs_dmat); 4441 bus_dma_tag_destroy(acb->parent_dmat); 4442 } 4443 /* 4444 ************************************************************************ 4445 ************************************************************************ 4446 */ 4447 static void arcmsr_mutex_init(struct AdapterControlBlock *acb) 4448 { 4449 ARCMSR_LOCK_INIT(&acb->isr_lock, "arcmsr isr lock"); 4450 ARCMSR_LOCK_INIT(&acb->srb_lock, "arcmsr srb lock"); 4451 ARCMSR_LOCK_INIT(&acb->postDone_lock, "arcmsr postQ lock"); 4452 ARCMSR_LOCK_INIT(&acb->qbuffer_lock, "arcmsr RW buffer lock"); 4453 } 4454 /* 4455 ************************************************************************ 4456 ************************************************************************ 4457 */ 4458 static void arcmsr_mutex_destroy(struct AdapterControlBlock *acb) 4459 { 4460 ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock); 4461 ARCMSR_LOCK_DESTROY(&acb->postDone_lock); 4462 ARCMSR_LOCK_DESTROY(&acb->srb_lock); 4463 ARCMSR_LOCK_DESTROY(&acb->isr_lock); 4464 } 4465 /* 4466 ************************************************************************ 4467 ************************************************************************ 4468 */ 4469 static u_int32_t arcmsr_initialize(device_t dev) 4470 { 4471 struct AdapterControlBlock *acb = device_get_softc(dev); 4472 u_int16_t pci_command; 4473 int i, j,max_coherent_size; 4474 u_int32_t vendor_dev_id; 4475 4476 vendor_dev_id = pci_get_devid(dev); 4477 acb->vendor_device_id = vendor_dev_id; 4478 acb->sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); 4479 switch (vendor_dev_id) { 4480 case PCIDevVenIDARC1880: 4481 case PCIDevVenIDARC1882: 4482 case PCIDevVenIDARC1213: 4483 case PCIDevVenIDARC1223: { 4484 acb->adapter_type = ACB_ADAPTER_TYPE_C; 4485 if ((acb->sub_device_id == ARECA_SUB_DEV_ID_1883) || 4486 (acb->sub_device_id == ARECA_SUB_DEV_ID_1216) || 4487 (acb->sub_device_id == ARECA_SUB_DEV_ID_1226)) 4488 acb->adapter_bus_speed = ACB_BUS_SPEED_12G; 4489 else 4490 acb->adapter_bus_speed = ACB_BUS_SPEED_6G; 4491 max_coherent_size = ARCMSR_SRBS_POOL_SIZE; 4492 } 4493 break; 4494 case PCIDevVenIDARC1884: 4495 acb->adapter_type = ACB_ADAPTER_TYPE_E; 4496 acb->adapter_bus_speed = ACB_BUS_SPEED_12G; 4497 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + COMPLETION_Q_POOL_SIZE; 4498 acb->completionQ_entry = COMPLETION_Q_POOL_SIZE / sizeof(struct deliver_completeQ); 4499 break; 4500 case PCIDevVenIDARC1886_: 4501 case PCIDevVenIDARC1886: 4502 acb->adapter_type = ACB_ADAPTER_TYPE_F; 4503 acb->adapter_bus_speed = ACB_BUS_SPEED_12G; 4504 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + COMPLETION_Q_POOL_SIZE + MESG_RW_BUFFER_SIZE; 4505 acb->completionQ_entry = COMPLETION_Q_POOL_SIZE / sizeof(struct deliver_completeQ); 4506 break; 4507 case PCIDevVenIDARC1214: { 4508 acb->adapter_type = ACB_ADAPTER_TYPE_D; 4509 acb->adapter_bus_speed = ACB_BUS_SPEED_6G; 4510 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBD_MessageUnit0)); 4511 } 4512 break; 4513 case PCIDevVenIDARC1200: 4514 case PCIDevVenIDARC1201: { 4515 acb->adapter_type = ACB_ADAPTER_TYPE_B; 4516 acb->adapter_bus_speed = ACB_BUS_SPEED_3G; 4517 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit)); 4518 } 4519 break; 4520 case PCIDevVenIDARC1203: { 4521 acb->adapter_type = ACB_ADAPTER_TYPE_B; 4522 acb->adapter_bus_speed = ACB_BUS_SPEED_6G; 4523 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit)); 4524 } 4525 break; 4526 case PCIDevVenIDARC1110: 4527 case PCIDevVenIDARC1120: 4528 case PCIDevVenIDARC1130: 4529 case PCIDevVenIDARC1160: 4530 case PCIDevVenIDARC1170: 4531 case PCIDevVenIDARC1210: 4532 case PCIDevVenIDARC1220: 4533 case PCIDevVenIDARC1230: 4534 case PCIDevVenIDARC1231: 4535 case PCIDevVenIDARC1260: 4536 case PCIDevVenIDARC1261: 4537 case PCIDevVenIDARC1270: 4538 case PCIDevVenIDARC1280: 4539 case PCIDevVenIDARC1212: 4540 case PCIDevVenIDARC1222: 4541 case PCIDevVenIDARC1380: 4542 case PCIDevVenIDARC1381: 4543 case PCIDevVenIDARC1680: 4544 case PCIDevVenIDARC1681: { 4545 acb->adapter_type = ACB_ADAPTER_TYPE_A; 4546 acb->adapter_bus_speed = ACB_BUS_SPEED_3G; 4547 max_coherent_size = ARCMSR_SRBS_POOL_SIZE; 4548 } 4549 break; 4550 default: { 4551 printf("arcmsr%d:" 4552 " unknown RAID adapter type \n", device_get_unit(dev)); 4553 return ENOMEM; 4554 } 4555 } 4556 if(bus_dma_tag_create( /*PCI parent*/ bus_get_dma_tag(dev), 4557 /*alignemnt*/ 1, 4558 /*boundary*/ 0, 4559 /*lowaddr*/ BUS_SPACE_MAXADDR, 4560 /*highaddr*/ BUS_SPACE_MAXADDR, 4561 /*filter*/ NULL, 4562 /*filterarg*/ NULL, 4563 /*maxsize*/ BUS_SPACE_MAXSIZE_32BIT, 4564 /*nsegments*/ BUS_SPACE_UNRESTRICTED, 4565 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4566 /*flags*/ 0, 4567 /*lockfunc*/ NULL, 4568 /*lockarg*/ NULL, 4569 &acb->parent_dmat) != 0) 4570 { 4571 printf("arcmsr%d: parent_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4572 return ENOMEM; 4573 } 4574 4575 /* Create a single tag describing a region large enough to hold all of the s/g lists we will need. */ 4576 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat, 4577 /*alignment*/ 1, 4578 /*boundary*/ 0, 4579 #ifdef PAE 4580 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 4581 #else 4582 /*lowaddr*/ BUS_SPACE_MAXADDR, 4583 #endif 4584 /*highaddr*/ BUS_SPACE_MAXADDR, 4585 /*filter*/ NULL, 4586 /*filterarg*/ NULL, 4587 /*maxsize*/ ARCMSR_MAX_SG_ENTRIES * PAGE_SIZE * ARCMSR_MAX_FREESRB_NUM, 4588 /*nsegments*/ ARCMSR_MAX_SG_ENTRIES, 4589 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4590 /*flags*/ 0, 4591 /*lockfunc*/ busdma_lock_mutex, 4592 /*lockarg*/ &acb->isr_lock, 4593 &acb->dm_segs_dmat) != 0) 4594 { 4595 bus_dma_tag_destroy(acb->parent_dmat); 4596 printf("arcmsr%d: dm_segs_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4597 return ENOMEM; 4598 } 4599 4600 /* DMA tag for our srb structures.... Allocate the freesrb memory */ 4601 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat, 4602 /*alignment*/ 0x20, 4603 /*boundary*/ 0, 4604 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 4605 /*highaddr*/ BUS_SPACE_MAXADDR, 4606 /*filter*/ NULL, 4607 /*filterarg*/ NULL, 4608 /*maxsize*/ max_coherent_size, 4609 /*nsegments*/ 1, 4610 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4611 /*flags*/ 0, 4612 /*lockfunc*/ NULL, 4613 /*lockarg*/ NULL, 4614 &acb->srb_dmat) != 0) 4615 { 4616 bus_dma_tag_destroy(acb->dm_segs_dmat); 4617 bus_dma_tag_destroy(acb->parent_dmat); 4618 printf("arcmsr%d: srb_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4619 return ENXIO; 4620 } 4621 /* Allocation for our srbs */ 4622 if(bus_dmamem_alloc(acb->srb_dmat, (void **)&acb->uncacheptr, BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, &acb->srb_dmamap) != 0) { 4623 bus_dma_tag_destroy(acb->srb_dmat); 4624 bus_dma_tag_destroy(acb->dm_segs_dmat); 4625 bus_dma_tag_destroy(acb->parent_dmat); 4626 printf("arcmsr%d: srb_dmat bus_dmamem_alloc failure!\n", device_get_unit(dev)); 4627 return ENXIO; 4628 } 4629 /* And permanently map them */ 4630 if(bus_dmamap_load(acb->srb_dmat, acb->srb_dmamap, acb->uncacheptr, max_coherent_size, arcmsr_map_free_srb, acb, /*flags*/0)) { 4631 bus_dma_tag_destroy(acb->srb_dmat); 4632 bus_dma_tag_destroy(acb->dm_segs_dmat); 4633 bus_dma_tag_destroy(acb->parent_dmat); 4634 printf("arcmsr%d: srb_dmat bus_dmamap_load failure!\n", device_get_unit(dev)); 4635 return ENXIO; 4636 } 4637 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 4638 pci_command |= PCIM_CMD_BUSMASTEREN; 4639 pci_command |= PCIM_CMD_PERRESPEN; 4640 pci_command |= PCIM_CMD_MWRICEN; 4641 /* Enable Busmaster */ 4642 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 4643 switch(acb->adapter_type) { 4644 case ACB_ADAPTER_TYPE_A: { 4645 u_int32_t rid0 = PCIR_BAR(0); 4646 vm_offset_t mem_base0; 4647 4648 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev,SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4649 if(acb->sys_res_arcmsr[0] == NULL) { 4650 arcmsr_free_resource(acb); 4651 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4652 return ENOMEM; 4653 } 4654 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4655 arcmsr_free_resource(acb); 4656 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4657 return ENXIO; 4658 } 4659 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4660 if(mem_base0 == 0) { 4661 arcmsr_free_resource(acb); 4662 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4663 return ENXIO; 4664 } 4665 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4666 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4667 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4668 acb->rid[0] = rid0; 4669 } 4670 break; 4671 case ACB_ADAPTER_TYPE_B: { 4672 struct HBB_MessageUnit *phbbmu; 4673 struct CommandControlBlock *freesrb; 4674 u_int32_t rid[]={ PCIR_BAR(0), PCIR_BAR(2) }; 4675 vm_offset_t mem_base[]={0,0}; 4676 for(i=0; i < 2; i++) { 4677 acb->sys_res_arcmsr[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid[i], RF_ACTIVE); 4678 if(acb->sys_res_arcmsr[i] == NULL) { 4679 arcmsr_free_resource(acb); 4680 printf("arcmsr%d: bus_alloc_resource %d failure!\n", device_get_unit(dev), i); 4681 return ENOMEM; 4682 } 4683 if(rman_get_start(acb->sys_res_arcmsr[i]) <= 0) { 4684 arcmsr_free_resource(acb); 4685 printf("arcmsr%d: rman_get_start %d failure!\n", device_get_unit(dev), i); 4686 return ENXIO; 4687 } 4688 mem_base[i] = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[i]); 4689 if(mem_base[i] == 0) { 4690 arcmsr_free_resource(acb); 4691 printf("arcmsr%d: rman_get_virtual %d failure!\n", device_get_unit(dev), i); 4692 return ENXIO; 4693 } 4694 acb->btag[i] = rman_get_bustag(acb->sys_res_arcmsr[i]); 4695 acb->bhandle[i] = rman_get_bushandle(acb->sys_res_arcmsr[i]); 4696 } 4697 freesrb = (struct CommandControlBlock *)acb->uncacheptr; 4698 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)freesrb+ARCMSR_SRBS_POOL_SIZE); 4699 phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4700 phbbmu->hbb_doorbell = (struct HBB_DOORBELL *)mem_base[0]; 4701 phbbmu->hbb_rwbuffer = (struct HBB_RWBUFFER *)mem_base[1]; 4702 if (vendor_dev_id == PCIDevVenIDARC1203) { 4703 phbbmu->drv2iop_doorbell = offsetof(struct HBB_DOORBELL_1203, drv2iop_doorbell); 4704 phbbmu->drv2iop_doorbell_mask = offsetof(struct HBB_DOORBELL_1203, drv2iop_doorbell_mask); 4705 phbbmu->iop2drv_doorbell = offsetof(struct HBB_DOORBELL_1203, iop2drv_doorbell); 4706 phbbmu->iop2drv_doorbell_mask = offsetof(struct HBB_DOORBELL_1203, iop2drv_doorbell_mask); 4707 } else { 4708 phbbmu->drv2iop_doorbell = offsetof(struct HBB_DOORBELL, drv2iop_doorbell); 4709 phbbmu->drv2iop_doorbell_mask = offsetof(struct HBB_DOORBELL, drv2iop_doorbell_mask); 4710 phbbmu->iop2drv_doorbell = offsetof(struct HBB_DOORBELL, iop2drv_doorbell); 4711 phbbmu->iop2drv_doorbell_mask = offsetof(struct HBB_DOORBELL, iop2drv_doorbell_mask); 4712 } 4713 acb->rid[0] = rid[0]; 4714 acb->rid[1] = rid[1]; 4715 } 4716 break; 4717 case ACB_ADAPTER_TYPE_C: { 4718 u_int32_t rid0 = PCIR_BAR(1); 4719 vm_offset_t mem_base0; 4720 4721 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4722 if(acb->sys_res_arcmsr[0] == NULL) { 4723 arcmsr_free_resource(acb); 4724 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4725 return ENOMEM; 4726 } 4727 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4728 arcmsr_free_resource(acb); 4729 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4730 return ENXIO; 4731 } 4732 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4733 if(mem_base0 == 0) { 4734 arcmsr_free_resource(acb); 4735 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4736 return ENXIO; 4737 } 4738 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4739 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4740 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4741 acb->rid[0] = rid0; 4742 } 4743 break; 4744 case ACB_ADAPTER_TYPE_D: { 4745 struct HBD_MessageUnit0 *phbdmu; 4746 u_int32_t rid0 = PCIR_BAR(0); 4747 vm_offset_t mem_base0; 4748 4749 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4750 if(acb->sys_res_arcmsr[0] == NULL) { 4751 arcmsr_free_resource(acb); 4752 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4753 return ENOMEM; 4754 } 4755 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4756 arcmsr_free_resource(acb); 4757 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4758 return ENXIO; 4759 } 4760 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4761 if(mem_base0 == 0) { 4762 arcmsr_free_resource(acb); 4763 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4764 return ENXIO; 4765 } 4766 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4767 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4768 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)acb->uncacheptr+ARCMSR_SRBS_POOL_SIZE); 4769 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 4770 phbdmu->phbdmu = (struct HBD_MessageUnit *)mem_base0; 4771 acb->rid[0] = rid0; 4772 } 4773 break; 4774 case ACB_ADAPTER_TYPE_E: { 4775 u_int32_t rid0 = PCIR_BAR(1); 4776 vm_offset_t mem_base0; 4777 4778 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4779 if(acb->sys_res_arcmsr[0] == NULL) { 4780 arcmsr_free_resource(acb); 4781 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4782 return ENOMEM; 4783 } 4784 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4785 arcmsr_free_resource(acb); 4786 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4787 return ENXIO; 4788 } 4789 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4790 if(mem_base0 == 0) { 4791 arcmsr_free_resource(acb); 4792 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4793 return ENXIO; 4794 } 4795 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4796 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4797 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4798 acb->doneq_index = 0; 4799 acb->in_doorbell = 0; 4800 acb->out_doorbell = 0; 4801 acb->rid[0] = rid0; 4802 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /*clear interrupt*/ 4803 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, ARCMSR_HBEMU_DOORBELL_SYNC); /* synchronize doorbell to 0 */ 4804 } 4805 break; 4806 case ACB_ADAPTER_TYPE_F: { 4807 u_int32_t rid0 = PCIR_BAR(0); 4808 vm_offset_t mem_base0; 4809 unsigned long host_buffer_dma; 4810 4811 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4812 if(acb->sys_res_arcmsr[0] == NULL) { 4813 arcmsr_free_resource(acb); 4814 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4815 return ENOMEM; 4816 } 4817 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4818 arcmsr_free_resource(acb); 4819 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4820 return ENXIO; 4821 } 4822 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4823 if(mem_base0 == 0) { 4824 arcmsr_free_resource(acb); 4825 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4826 return ENXIO; 4827 } 4828 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4829 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4830 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4831 acb->doneq_index = 0; 4832 acb->in_doorbell = 0; 4833 acb->out_doorbell = 0; 4834 acb->rid[0] = rid0; 4835 arcmsr_wait_firmware_ready(acb); 4836 CHIP_REG_WRITE32(HBF_MessageUnit, 0, host_int_status, 0); /*clear interrupt*/ 4837 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, ARCMSR_HBEMU_DOORBELL_SYNC); /* synchronize doorbell to 0 */ 4838 host_buffer_dma = acb->completeQ_phys + COMPLETION_Q_POOL_SIZE; 4839 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, (u_int32_t)(host_buffer_dma | 1)); /* host buffer low addr, bit0:1 all buffer active */ 4840 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr1, (u_int32_t)((host_buffer_dma >> 16) >> 16));/* host buffer high addr */ 4841 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, ARCMSR_HBFMU_DOORBELL_SYNC1); /* set host buffer physical address */ 4842 } 4843 break; 4844 } 4845 if(acb->acb_flags & ACB_F_MAPFREESRB_FAILD) { 4846 arcmsr_free_resource(acb); 4847 printf("arcmsr%d: map free srb failure!\n", device_get_unit(dev)); 4848 return ENXIO; 4849 } 4850 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_RQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ); 4851 acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER; 4852 /* 4853 ******************************************************************** 4854 ** init raid volume state 4855 ******************************************************************** 4856 */ 4857 for(i=0; i < ARCMSR_MAX_TARGETID; i++) { 4858 for(j=0; j < ARCMSR_MAX_TARGETLUN; j++) { 4859 acb->devstate[i][j] = ARECA_RAID_GONE; 4860 } 4861 } 4862 arcmsr_iop_init(acb); 4863 return(0); 4864 } 4865 4866 static int arcmsr_setup_msix(struct AdapterControlBlock *acb) 4867 { 4868 int i; 4869 4870 for (i = 0; i < acb->msix_vectors; i++) { 4871 acb->irq_id[i] = 1 + i; 4872 acb->irqres[i] = bus_alloc_resource_any(acb->pci_dev, 4873 SYS_RES_IRQ, &acb->irq_id[i], RF_ACTIVE); 4874 if (acb->irqres[i] == NULL) { 4875 printf("arcmsr: Can't allocate MSI-X resource\n"); 4876 goto irq_alloc_failed; 4877 } 4878 if (bus_setup_intr(acb->pci_dev, acb->irqres[i], 4879 INTR_MPSAFE | INTR_TYPE_CAM, NULL, arcmsr_intr_handler, 4880 acb, &acb->ih[i])) { 4881 printf("arcmsr: Cannot set up MSI-X interrupt handler\n"); 4882 goto irq_alloc_failed; 4883 } 4884 } 4885 printf("arcmsr: MSI-X INT enabled\n"); 4886 acb->acb_flags |= ACB_F_MSIX_ENABLED; 4887 return TRUE; 4888 4889 irq_alloc_failed: 4890 arcmsr_teardown_intr(acb->pci_dev, acb); 4891 return FALSE; 4892 } 4893 4894 /* 4895 ************************************************************************ 4896 ************************************************************************ 4897 */ 4898 static int arcmsr_attach(device_t dev) 4899 { 4900 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 4901 u_int32_t unit=device_get_unit(dev); 4902 struct ccb_setasync csa; 4903 struct cam_devq *devq; /* Device Queue to use for this SIM */ 4904 struct resource *irqres; 4905 4906 if(acb == NULL) { 4907 printf("arcmsr%d: cannot allocate softc\n", unit); 4908 return (ENOMEM); 4909 } 4910 arcmsr_mutex_init(acb); 4911 acb->pci_dev = dev; 4912 acb->pci_unit = unit; 4913 if(arcmsr_initialize(dev)) { 4914 printf("arcmsr%d: initialize failure!\n", unit); 4915 goto initialize_failed; 4916 } 4917 /* After setting up the adapter, map our interrupt */ 4918 acb->msix_vectors = ARCMSR_NUM_MSIX_VECTORS; 4919 if (pci_alloc_msix(dev, &acb->msix_vectors) == 0) { 4920 if (arcmsr_setup_msix(acb) == TRUE) 4921 goto irqx; 4922 } 4923 acb->irq_id[0] = 0; 4924 irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &acb->irq_id[0], RF_SHAREABLE | RF_ACTIVE); 4925 if(irqres == NULL || 4926 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, NULL, arcmsr_intr_handler, acb, &acb->ih[0])) { 4927 printf("arcmsr%d: unable to register interrupt handler!\n", unit); 4928 goto setup_intr_failed; 4929 } 4930 acb->irqres[0] = irqres; 4931 irqx: 4932 /* 4933 * Now let the CAM generic SCSI layer find the SCSI devices on 4934 * the bus * start queue to reset to the idle loop. * 4935 * Create device queue of SIM(s) * (MAX_START_JOB - 1) : 4936 * max_sim_transactions 4937 */ 4938 devq = cam_simq_alloc(acb->maxOutstanding); 4939 if(devq == NULL) { 4940 printf("arcmsr%d: cam_simq_alloc failure!\n", unit); 4941 goto simq_alloc_failed; 4942 } 4943 acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, &acb->isr_lock, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq); 4944 if(acb->psim == NULL) { 4945 printf("arcmsr%d: cam_sim_alloc failure!\n", unit); 4946 goto sim_alloc_failed; 4947 } 4948 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 4949 if(xpt_bus_register(acb->psim, dev, 0) != CAM_SUCCESS) { 4950 printf("arcmsr%d: xpt_bus_register failure!\n", unit); 4951 goto xpt_bus_failed; 4952 } 4953 if(xpt_create_path(&acb->ppath, /* periph */ NULL, cam_sim_path(acb->psim), CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 4954 printf("arcmsr%d: xpt_create_path failure!\n", unit); 4955 goto xpt_path_failed; 4956 } 4957 /* 4958 **************************************************** 4959 */ 4960 memset(&csa, 0, sizeof(csa)); 4961 xpt_setup_ccb(&csa.ccb_h, acb->ppath, /*priority*/5); 4962 csa.ccb_h.func_code = XPT_SASYNC_CB; 4963 csa.event_enable = AC_FOUND_DEVICE|AC_LOST_DEVICE; 4964 csa.callback = arcmsr_async; 4965 csa.callback_arg = acb->psim; 4966 xpt_action((union ccb *)&csa); 4967 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 4968 /* Create the control device. */ 4969 acb->ioctl_dev = make_dev(&arcmsr_cdevsw, unit, UID_ROOT, GID_WHEEL /* GID_OPERATOR */, S_IRUSR | S_IWUSR, "arcmsr%d", unit); 4970 4971 (void)make_dev_alias(acb->ioctl_dev, "arc%d", unit); 4972 arcmsr_callout_init(&acb->devmap_callout); 4973 callout_reset(&acb->devmap_callout, 60 * hz, arcmsr_polling_devmap, acb); 4974 return (0); 4975 xpt_path_failed: 4976 xpt_bus_deregister(cam_sim_path(acb->psim)); 4977 xpt_bus_failed: 4978 cam_sim_free(acb->psim, /* free_simq */ TRUE); 4979 sim_alloc_failed: 4980 cam_simq_free(devq); 4981 simq_alloc_failed: 4982 arcmsr_teardown_intr(dev, acb); 4983 setup_intr_failed: 4984 arcmsr_free_resource(acb); 4985 initialize_failed: 4986 arcmsr_mutex_destroy(acb); 4987 return ENXIO; 4988 } 4989 4990 /* 4991 ************************************************************************ 4992 ************************************************************************ 4993 */ 4994 static int arcmsr_probe(device_t dev) 4995 { 4996 u_int32_t id; 4997 u_int16_t sub_device_id; 4998 static char buf[256]; 4999 char x_type[]={"unknown"}; 5000 char *type; 5001 int raid6 = 1; 5002 5003 if (pci_get_vendor(dev) != PCI_VENDOR_ID_ARECA) { 5004 return (ENXIO); 5005 } 5006 sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); 5007 switch(id = pci_get_devid(dev)) { 5008 case PCIDevVenIDARC1110: 5009 case PCIDevVenIDARC1200: 5010 case PCIDevVenIDARC1201: 5011 case PCIDevVenIDARC1210: 5012 raid6 = 0; 5013 /*FALLTHRU*/ 5014 case PCIDevVenIDARC1120: 5015 case PCIDevVenIDARC1130: 5016 case PCIDevVenIDARC1160: 5017 case PCIDevVenIDARC1170: 5018 case PCIDevVenIDARC1220: 5019 case PCIDevVenIDARC1230: 5020 case PCIDevVenIDARC1231: 5021 case PCIDevVenIDARC1260: 5022 case PCIDevVenIDARC1261: 5023 case PCIDevVenIDARC1270: 5024 case PCIDevVenIDARC1280: 5025 type = "SATA 3G"; 5026 break; 5027 case PCIDevVenIDARC1212: 5028 case PCIDevVenIDARC1222: 5029 case PCIDevVenIDARC1380: 5030 case PCIDevVenIDARC1381: 5031 case PCIDevVenIDARC1680: 5032 case PCIDevVenIDARC1681: 5033 type = "SAS 3G"; 5034 break; 5035 case PCIDevVenIDARC1880: 5036 case PCIDevVenIDARC1882: 5037 case PCIDevVenIDARC1213: 5038 case PCIDevVenIDARC1223: 5039 if ((sub_device_id == ARECA_SUB_DEV_ID_1883) || 5040 (sub_device_id == ARECA_SUB_DEV_ID_1216) || 5041 (sub_device_id == ARECA_SUB_DEV_ID_1226)) 5042 type = "SAS 12G"; 5043 else 5044 type = "SAS 6G"; 5045 break; 5046 case PCIDevVenIDARC1884: 5047 type = "SAS 12G"; 5048 break; 5049 case PCIDevVenIDARC1886_: 5050 case PCIDevVenIDARC1886: 5051 type = "NVME,SAS-12G,SATA-6G"; 5052 break; 5053 case PCIDevVenIDARC1214: 5054 case PCIDevVenIDARC1203: 5055 type = "SATA 6G"; 5056 break; 5057 default: 5058 type = x_type; 5059 raid6 = 0; 5060 break; 5061 } 5062 if(type == x_type) 5063 return(ENXIO); 5064 sprintf(buf, "Areca %s Host Adapter RAID Controller %s\n%s\n", 5065 type, raid6 ? "(RAID6 capable)" : "", ARCMSR_DRIVER_VERSION); 5066 device_set_desc_copy(dev, buf); 5067 return (BUS_PROBE_DEFAULT); 5068 } 5069 /* 5070 ************************************************************************ 5071 ************************************************************************ 5072 */ 5073 static int arcmsr_shutdown(device_t dev) 5074 { 5075 u_int32_t i; 5076 u_int32_t intmask_org; 5077 struct CommandControlBlock *srb; 5078 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 5079 5080 /* stop adapter background rebuild */ 5081 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 5082 /* disable all outbound interrupt */ 5083 intmask_org = arcmsr_disable_allintr(acb); 5084 arcmsr_stop_adapter_bgrb(acb); 5085 arcmsr_flush_adapter_cache(acb); 5086 /* abort all outstanding command */ 5087 acb->acb_flags |= ACB_F_SCSISTOPADAPTER; 5088 acb->acb_flags &= ~ACB_F_IOP_INITED; 5089 if(acb->srboutstandingcount != 0) { 5090 /*clear and abort all outbound posted Q*/ 5091 arcmsr_done4abort_postqueue(acb); 5092 /* talk to iop 331 outstanding command aborted*/ 5093 arcmsr_abort_allcmd(acb); 5094 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 5095 srb = acb->psrb_pool[i]; 5096 if(srb->srb_state == ARCMSR_SRB_START) { 5097 srb->srb_state = ARCMSR_SRB_ABORTED; 5098 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 5099 arcmsr_srb_complete(srb, 1); 5100 } 5101 } 5102 } 5103 acb->srboutstandingcount = 0; 5104 acb->workingsrb_doneindex = 0; 5105 acb->workingsrb_startindex = 0; 5106 acb->pktRequestCount = 0; 5107 acb->pktReturnCount = 0; 5108 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 5109 return (0); 5110 } 5111 /* 5112 ************************************************************************ 5113 ************************************************************************ 5114 */ 5115 static void arcmsr_teardown_intr(device_t dev, struct AdapterControlBlock *acb) 5116 { 5117 int i; 5118 5119 if (acb->acb_flags & ACB_F_MSIX_ENABLED) { 5120 for (i = 0; i < acb->msix_vectors; i++) { 5121 if (acb->ih[i]) 5122 bus_teardown_intr(dev, acb->irqres[i], acb->ih[i]); 5123 if (acb->irqres[i] != NULL) 5124 bus_release_resource(dev, SYS_RES_IRQ, 5125 acb->irq_id[i], acb->irqres[i]); 5126 5127 acb->ih[i] = NULL; 5128 } 5129 pci_release_msi(dev); 5130 } else { 5131 if (acb->ih[0]) 5132 bus_teardown_intr(dev, acb->irqres[0], acb->ih[0]); 5133 if (acb->irqres[0] != NULL) 5134 bus_release_resource(dev, SYS_RES_IRQ, 5135 acb->irq_id[0], acb->irqres[0]); 5136 acb->ih[0] = NULL; 5137 } 5138 5139 } 5140 /* 5141 ************************************************************************ 5142 ************************************************************************ 5143 */ 5144 static int arcmsr_detach(device_t dev) 5145 { 5146 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 5147 int i; 5148 5149 callout_stop(&acb->devmap_callout); 5150 arcmsr_teardown_intr(dev, acb); 5151 arcmsr_shutdown(dev); 5152 arcmsr_free_resource(acb); 5153 for(i=0; (acb->sys_res_arcmsr[i]!=NULL) && (i<2); i++) { 5154 bus_release_resource(dev, SYS_RES_MEMORY, acb->rid[i], acb->sys_res_arcmsr[i]); 5155 } 5156 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 5157 xpt_async(AC_LOST_DEVICE, acb->ppath, NULL); 5158 xpt_free_path(acb->ppath); 5159 xpt_bus_deregister(cam_sim_path(acb->psim)); 5160 cam_sim_free(acb->psim, TRUE); 5161 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 5162 arcmsr_mutex_destroy(acb); 5163 return (0); 5164 } 5165 5166 #ifdef ARCMSR_DEBUG1 5167 static void arcmsr_dump_data(struct AdapterControlBlock *acb) 5168 { 5169 if((acb->pktRequestCount - acb->pktReturnCount) == 0) 5170 return; 5171 printf("Command Request Count =0x%x\n",acb->pktRequestCount); 5172 printf("Command Return Count =0x%x\n",acb->pktReturnCount); 5173 printf("Command (Req-Rtn) Count =0x%x\n",(acb->pktRequestCount - acb->pktReturnCount)); 5174 printf("Queued Command Count =0x%x\n",acb->srboutstandingcount); 5175 } 5176 #endif 5177