1 /* 2 ******************************************************************************** 3 ** OS : FreeBSD 4 ** FILE NAME : arcmsr.c 5 ** BY : Erich Chen, Ching Huang 6 ** Description: SCSI RAID Device Driver for 7 ** ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x) 8 ** SATA/SAS RAID HOST Adapter 9 ******************************************************************************** 10 ******************************************************************************** 11 ** 12 ** SPDX-License-Identifier: BSD-3-Clause 13 ** 14 ** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved. 15 ** 16 ** Redistribution and use in source and binary forms, with or without 17 ** modification, are permitted provided that the following conditions 18 ** are met: 19 ** 1. Redistributions of source code must retain the above copyright 20 ** notice, this list of conditions and the following disclaimer. 21 ** 2. Redistributions in binary form must reproduce the above copyright 22 ** notice, this list of conditions and the following disclaimer in the 23 ** documentation and/or other materials provided with the distribution. 24 ** 3. The name of the author may not be used to endorse or promote products 25 ** derived from this software without specific prior written permission. 26 ** 27 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 28 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 29 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 31 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT 32 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 34 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 36 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 ******************************************************************************** 38 ** History 39 ** 40 ** REV# DATE NAME DESCRIPTION 41 ** 1.00.00.00 03/31/2004 Erich Chen First release 42 ** 1.20.00.02 11/29/2004 Erich Chen bug fix with arcmsr_bus_reset when PHY error 43 ** 1.20.00.03 04/19/2005 Erich Chen add SATA 24 Ports adapter type support 44 ** clean unused function 45 ** 1.20.00.12 09/12/2005 Erich Chen bug fix with abort command handling, 46 ** firmware version check 47 ** and firmware update notify for hardware bug fix 48 ** handling if none zero high part physical address 49 ** of srb resource 50 ** 1.20.00.13 08/18/2006 Erich Chen remove pending srb and report busy 51 ** add iop message xfer 52 ** with scsi pass-through command 53 ** add new device id of sas raid adapters 54 ** code fit for SPARC64 & PPC 55 ** 1.20.00.14 02/05/2007 Erich Chen bug fix for incorrect ccb_h.status report 56 ** and cause g_vfs_done() read write error 57 ** 1.20.00.15 10/10/2007 Erich Chen support new RAID adapter type ARC120x 58 ** 1.20.00.16 10/10/2009 Erich Chen Bug fix for RAID adapter type ARC120x 59 ** bus_dmamem_alloc() with BUS_DMA_ZERO 60 ** 1.20.00.17 07/15/2010 Ching Huang Added support ARC1880 61 ** report CAM_DEV_NOT_THERE instead of CAM_SEL_TIMEOUT when device failed, 62 ** prevent cam_periph_error removing all LUN devices of one Target id 63 ** for any one LUN device failed 64 ** 1.20.00.18 10/14/2010 Ching Huang Fixed "inquiry data fails comparion at DV1 step" 65 ** 10/25/2010 Ching Huang Fixed bad range input in bus_alloc_resource for ADAPTER_TYPE_B 66 ** 1.20.00.19 11/11/2010 Ching Huang Fixed arcmsr driver prevent arcsas support for Areca SAS HBA ARC13x0 67 ** 1.20.00.20 12/08/2010 Ching Huang Avoid calling atomic_set_int function 68 ** 1.20.00.21 02/08/2011 Ching Huang Implement I/O request timeout 69 ** 02/14/2011 Ching Huang Modified pktRequestCount 70 ** 1.20.00.21 03/03/2011 Ching Huang if a command timeout, then wait its ccb back before free it 71 ** 1.20.00.22 07/04/2011 Ching Huang Fixed multiple MTX panic 72 ** 1.20.00.23 10/28/2011 Ching Huang Added TIMEOUT_DELAY in case of too many HDDs need to start 73 ** 1.20.00.23 11/08/2011 Ching Huang Added report device transfer speed 74 ** 1.20.00.23 01/30/2012 Ching Huang Fixed Request requeued and Retrying command 75 ** 1.20.00.24 06/11/2012 Ching Huang Fixed return sense data condition 76 ** 1.20.00.25 08/17/2012 Ching Huang Fixed hotplug device no function on type A adapter 77 ** 1.20.00.26 12/14/2012 Ching Huang Added support ARC1214,1224,1264,1284 78 ** 1.20.00.27 05/06/2013 Ching Huang Fixed out standing cmd full on ARC-12x4 79 ** 1.20.00.28 09/13/2013 Ching Huang Removed recursive mutex in arcmsr_abort_dr_ccbs 80 ** 1.20.00.29 12/18/2013 Ching Huang Change simq allocation number, support ARC1883 81 ** 1.30.00.00 11/30/2015 Ching Huang Added support ARC1203 82 ** 1.40.00.00 07/11/2017 Ching Huang Added support ARC1884 83 ** 1.40.00.01 10/30/2017 Ching Huang Fixed release memory resource 84 ** 1.50.00.00 09/30/2020 Ching Huang Added support ARC-1886, NVMe/SAS/SATA controller 85 ** 1.50.00.01 02/26/2021 Ching Huang Fixed no action of hot plugging device on type_F adapter 86 ** 1.50.00.02 04/16/2021 Ching Huang Fixed scsi command timeout on ARC-1886 when 87 ** scatter-gather count large than some number 88 ** 1.50.00.03 05/04/2021 Ching Huang Fixed doorbell status arrived late on ARC-1886 89 ** 1.50.00.04 12/08/2021 Ching Huang Fixed boot up hung under ARC-1886 with no volume created 90 ****************************************************************************************** 91 */ 92 93 #include <sys/cdefs.h> 94 __FBSDID("$FreeBSD$"); 95 96 #if 0 97 #define ARCMSR_DEBUG1 1 98 #endif 99 #include <sys/param.h> 100 #include <sys/systm.h> 101 #include <sys/malloc.h> 102 #include <sys/kernel.h> 103 #include <sys/bus.h> 104 #include <sys/queue.h> 105 #include <sys/stat.h> 106 #include <sys/devicestat.h> 107 #include <sys/kthread.h> 108 #include <sys/module.h> 109 #include <sys/proc.h> 110 #include <sys/lock.h> 111 #include <sys/sysctl.h> 112 #include <sys/poll.h> 113 #include <sys/ioccom.h> 114 #include <vm/vm.h> 115 #include <vm/vm_param.h> 116 #include <vm/pmap.h> 117 118 #include <isa/rtc.h> 119 120 #include <machine/bus.h> 121 #include <machine/resource.h> 122 #include <machine/atomic.h> 123 #include <sys/conf.h> 124 #include <sys/rman.h> 125 126 #include <cam/cam.h> 127 #include <cam/cam_ccb.h> 128 #include <cam/cam_sim.h> 129 #include <cam/cam_periph.h> 130 #include <cam/cam_xpt_periph.h> 131 #include <cam/cam_xpt_sim.h> 132 #include <cam/cam_debug.h> 133 #include <cam/scsi/scsi_all.h> 134 #include <cam/scsi/scsi_message.h> 135 /* 136 ************************************************************************** 137 ************************************************************************** 138 */ 139 #include <sys/selinfo.h> 140 #include <sys/mutex.h> 141 #include <sys/endian.h> 142 #include <dev/pci/pcivar.h> 143 #include <dev/pci/pcireg.h> 144 145 #define arcmsr_callout_init(a) callout_init(a, /*mpsafe*/1); 146 147 #define ARCMSR_DRIVER_VERSION "arcmsr version 1.50.00.04 2021-12-08" 148 #include <dev/arcmsr/arcmsr.h> 149 /* 150 ************************************************************************** 151 ************************************************************************** 152 */ 153 static void arcmsr_free_srb(struct CommandControlBlock *srb); 154 static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb); 155 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb); 156 static int arcmsr_probe(device_t dev); 157 static int arcmsr_attach(device_t dev); 158 static int arcmsr_detach(device_t dev); 159 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg); 160 static void arcmsr_iop_parking(struct AdapterControlBlock *acb); 161 static int arcmsr_shutdown(device_t dev); 162 static void arcmsr_interrupt(struct AdapterControlBlock *acb); 163 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb); 164 static void arcmsr_free_resource(struct AdapterControlBlock *acb); 165 static void arcmsr_bus_reset(struct AdapterControlBlock *acb); 166 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb); 167 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb); 168 static void arcmsr_iop_init(struct AdapterControlBlock *acb); 169 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb); 170 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, struct QBUFFER *prbuffer); 171 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb); 172 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb); 173 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag); 174 static void arcmsr_iop_reset(struct AdapterControlBlock *acb); 175 static void arcmsr_report_sense_info(struct CommandControlBlock *srb); 176 static void arcmsr_build_srb(struct CommandControlBlock *srb, bus_dma_segment_t *dm_segs, u_int32_t nseg); 177 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb); 178 static int arcmsr_resume(device_t dev); 179 static int arcmsr_suspend(device_t dev); 180 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb); 181 static void arcmsr_polling_devmap(void *arg); 182 static void arcmsr_srb_timeout(void *arg); 183 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb); 184 static void arcmsr_hbe_postqueue_isr(struct AdapterControlBlock *acb); 185 static void arcmsr_hbf_postqueue_isr(struct AdapterControlBlock *acb); 186 static void arcmsr_teardown_intr(device_t dev, struct AdapterControlBlock *acb); 187 #ifdef ARCMSR_DEBUG1 188 static void arcmsr_dump_data(struct AdapterControlBlock *acb); 189 #endif 190 /* 191 ************************************************************************** 192 ************************************************************************** 193 */ 194 static void UDELAY(u_int32_t us) { DELAY(us); } 195 /* 196 ************************************************************************** 197 ************************************************************************** 198 */ 199 static bus_dmamap_callback_t arcmsr_map_free_srb; 200 static bus_dmamap_callback_t arcmsr_execute_srb; 201 /* 202 ************************************************************************** 203 ************************************************************************** 204 */ 205 static d_open_t arcmsr_open; 206 static d_close_t arcmsr_close; 207 static d_ioctl_t arcmsr_ioctl; 208 209 static device_method_t arcmsr_methods[]={ 210 DEVMETHOD(device_probe, arcmsr_probe), 211 DEVMETHOD(device_attach, arcmsr_attach), 212 DEVMETHOD(device_detach, arcmsr_detach), 213 DEVMETHOD(device_shutdown, arcmsr_shutdown), 214 DEVMETHOD(device_suspend, arcmsr_suspend), 215 DEVMETHOD(device_resume, arcmsr_resume), 216 DEVMETHOD_END 217 }; 218 219 static driver_t arcmsr_driver={ 220 "arcmsr", arcmsr_methods, sizeof(struct AdapterControlBlock) 221 }; 222 223 static devclass_t arcmsr_devclass; 224 DRIVER_MODULE(arcmsr, pci, arcmsr_driver, arcmsr_devclass, 0, 0); 225 MODULE_DEPEND(arcmsr, pci, 1, 1, 1); 226 MODULE_DEPEND(arcmsr, cam, 1, 1, 1); 227 #ifndef BUS_DMA_COHERENT 228 #define BUS_DMA_COHERENT 0x04 /* hint: map memory in a coherent way */ 229 #endif 230 static struct cdevsw arcmsr_cdevsw={ 231 .d_version = D_VERSION, 232 .d_open = arcmsr_open, /* open */ 233 .d_close = arcmsr_close, /* close */ 234 .d_ioctl = arcmsr_ioctl, /* ioctl */ 235 .d_name = "arcmsr", /* name */ 236 }; 237 /* 238 ************************************************************************** 239 ************************************************************************** 240 */ 241 static int arcmsr_open(struct cdev *dev, int flags, int fmt, struct thread *proc) 242 { 243 struct AdapterControlBlock *acb = dev->si_drv1; 244 245 if (acb == NULL) { 246 return ENXIO; 247 } 248 return (0); 249 } 250 /* 251 ************************************************************************** 252 ************************************************************************** 253 */ 254 static int arcmsr_close(struct cdev *dev, int flags, int fmt, struct thread *proc) 255 { 256 struct AdapterControlBlock *acb = dev->si_drv1; 257 258 if (acb == NULL) { 259 return ENXIO; 260 } 261 return 0; 262 } 263 /* 264 ************************************************************************** 265 ************************************************************************** 266 */ 267 static int arcmsr_ioctl(struct cdev *dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc) 268 { 269 struct AdapterControlBlock *acb = dev->si_drv1; 270 271 if (acb == NULL) { 272 return ENXIO; 273 } 274 return (arcmsr_iop_ioctlcmd(acb, ioctl_cmd, arg)); 275 } 276 /* 277 ********************************************************************** 278 ********************************************************************** 279 */ 280 static u_int32_t arcmsr_disable_allintr( struct AdapterControlBlock *acb) 281 { 282 u_int32_t intmask_org = 0; 283 284 switch (acb->adapter_type) { 285 case ACB_ADAPTER_TYPE_A: { 286 /* disable all outbound interrupt */ 287 intmask_org = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intmask); /* disable outbound message0 int */ 288 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE); 289 } 290 break; 291 case ACB_ADAPTER_TYPE_B: { 292 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 293 /* disable all outbound interrupt */ 294 intmask_org = READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask) 295 & (~ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); /* disable outbound message0 int */ 296 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask, 0); /* disable all interrupt */ 297 } 298 break; 299 case ACB_ADAPTER_TYPE_C: { 300 /* disable all outbound interrupt */ 301 intmask_org = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask); /* disable outbound message0 int */ 302 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE); 303 } 304 break; 305 case ACB_ADAPTER_TYPE_D: { 306 /* disable all outbound interrupt */ 307 intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); /* disable outbound message0 int */ 308 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE); 309 } 310 break; 311 case ACB_ADAPTER_TYPE_E: 312 case ACB_ADAPTER_TYPE_F: { 313 /* disable all outbound interrupt */ 314 intmask_org = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_mask); /* disable outbound message0 int */ 315 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_mask, intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE); 316 } 317 break; 318 } 319 return (intmask_org); 320 } 321 /* 322 ********************************************************************** 323 ********************************************************************** 324 */ 325 static void arcmsr_enable_allintr( struct AdapterControlBlock *acb, u_int32_t intmask_org) 326 { 327 u_int32_t mask; 328 329 switch (acb->adapter_type) { 330 case ACB_ADAPTER_TYPE_A: { 331 /* enable outbound Post Queue, outbound doorbell Interrupt */ 332 mask = ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE|ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE); 333 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org & mask); 334 acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff; 335 } 336 break; 337 case ACB_ADAPTER_TYPE_B: { 338 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 339 /* enable ARCMSR_IOP2DRV_MESSAGE_CMD_DONE */ 340 mask = (ARCMSR_IOP2DRV_DATA_WRITE_OK|ARCMSR_IOP2DRV_DATA_READ_OK|ARCMSR_IOP2DRV_CDB_DONE|ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); 341 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask, intmask_org | mask); /*1=interrupt enable, 0=interrupt disable*/ 342 acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f; 343 } 344 break; 345 case ACB_ADAPTER_TYPE_C: { 346 /* enable outbound Post Queue, outbound doorbell Interrupt */ 347 mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK); 348 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org & mask); 349 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f; 350 } 351 break; 352 case ACB_ADAPTER_TYPE_D: { 353 /* enable outbound Post Queue, outbound doorbell Interrupt */ 354 mask = ARCMSR_HBDMU_ALL_INT_ENABLE; 355 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | mask); 356 CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); 357 acb->outbound_int_enable = mask; 358 } 359 break; 360 case ACB_ADAPTER_TYPE_E: 361 case ACB_ADAPTER_TYPE_F: { 362 /* enable outbound Post Queue, outbound doorbell Interrupt */ 363 mask = ~(ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR); 364 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_mask, intmask_org & mask); 365 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f; 366 } 367 break; 368 } 369 } 370 /* 371 ********************************************************************** 372 ********************************************************************** 373 */ 374 static u_int8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb) 375 { 376 u_int32_t Index; 377 u_int8_t Retries = 0x00; 378 379 do { 380 for(Index=0; Index < 100; Index++) { 381 if(CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { 382 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);/*clear interrupt*/ 383 return TRUE; 384 } 385 UDELAY(10000); 386 }/*max 1 seconds*/ 387 }while(Retries++ < 20);/*max 20 sec*/ 388 return (FALSE); 389 } 390 /* 391 ********************************************************************** 392 ********************************************************************** 393 */ 394 static u_int8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb) 395 { 396 u_int32_t Index; 397 u_int8_t Retries = 0x00; 398 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 399 400 do { 401 for(Index=0; Index < 100; Index++) { 402 if(READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) { 403 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt*/ 404 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 405 return TRUE; 406 } 407 UDELAY(10000); 408 }/*max 1 seconds*/ 409 }while(Retries++ < 20);/*max 20 sec*/ 410 return (FALSE); 411 } 412 /* 413 ********************************************************************** 414 ********************************************************************** 415 */ 416 static u_int8_t arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock *acb) 417 { 418 u_int32_t Index; 419 u_int8_t Retries = 0x00; 420 421 do { 422 for(Index=0; Index < 100; Index++) { 423 if(CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 424 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);/*clear interrupt*/ 425 return TRUE; 426 } 427 UDELAY(10000); 428 }/*max 1 seconds*/ 429 }while(Retries++ < 20);/*max 20 sec*/ 430 return (FALSE); 431 } 432 /* 433 ********************************************************************** 434 ********************************************************************** 435 */ 436 static u_int8_t arcmsr_hbd_wait_msgint_ready(struct AdapterControlBlock *acb) 437 { 438 u_int32_t Index; 439 u_int8_t Retries = 0x00; 440 441 do { 442 for(Index=0; Index < 100; Index++) { 443 if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) { 444 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);/*clear interrupt*/ 445 return TRUE; 446 } 447 UDELAY(10000); 448 }/*max 1 seconds*/ 449 }while(Retries++ < 20);/*max 20 sec*/ 450 return (FALSE); 451 } 452 /* 453 ********************************************************************** 454 ********************************************************************** 455 */ 456 static u_int8_t arcmsr_hbe_wait_msgint_ready(struct AdapterControlBlock *acb) 457 { 458 u_int32_t Index, read_doorbell; 459 u_int8_t Retries = 0x00; 460 461 do { 462 for(Index=0; Index < 100; Index++) { 463 read_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell); 464 if((read_doorbell ^ acb->in_doorbell) & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) { 465 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0);/*clear interrupt*/ 466 acb->in_doorbell = read_doorbell; 467 return TRUE; 468 } 469 UDELAY(10000); 470 }/*max 1 seconds*/ 471 }while(Retries++ < 20);/*max 20 sec*/ 472 return (FALSE); 473 } 474 /* 475 ************************************************************************ 476 ************************************************************************ 477 */ 478 static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb) 479 { 480 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 481 482 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 483 do { 484 if(arcmsr_hba_wait_msgint_ready(acb)) { 485 break; 486 } else { 487 retry_count--; 488 } 489 }while(retry_count != 0); 490 } 491 /* 492 ************************************************************************ 493 ************************************************************************ 494 */ 495 static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb) 496 { 497 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 498 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 499 500 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_FLUSH_CACHE); 501 do { 502 if(arcmsr_hbb_wait_msgint_ready(acb)) { 503 break; 504 } else { 505 retry_count--; 506 } 507 }while(retry_count != 0); 508 } 509 /* 510 ************************************************************************ 511 ************************************************************************ 512 */ 513 static void arcmsr_flush_hbc_cache(struct AdapterControlBlock *acb) 514 { 515 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 516 517 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 518 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 519 do { 520 if(arcmsr_hbc_wait_msgint_ready(acb)) { 521 break; 522 } else { 523 retry_count--; 524 } 525 }while(retry_count != 0); 526 } 527 /* 528 ************************************************************************ 529 ************************************************************************ 530 */ 531 static void arcmsr_flush_hbd_cache(struct AdapterControlBlock *acb) 532 { 533 int retry_count = 30; /* enlarge wait flush adapter cache time: 10 minute */ 534 535 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 536 do { 537 if(arcmsr_hbd_wait_msgint_ready(acb)) { 538 break; 539 } else { 540 retry_count--; 541 } 542 }while(retry_count != 0); 543 } 544 /* 545 ************************************************************************ 546 ************************************************************************ 547 */ 548 static void arcmsr_flush_hbe_cache(struct AdapterControlBlock *acb) 549 { 550 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 551 552 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 553 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 554 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 555 do { 556 if(arcmsr_hbe_wait_msgint_ready(acb)) { 557 break; 558 } else { 559 retry_count--; 560 } 561 }while(retry_count != 0); 562 } 563 /* 564 ************************************************************************ 565 ************************************************************************ 566 */ 567 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb) 568 { 569 switch (acb->adapter_type) { 570 case ACB_ADAPTER_TYPE_A: { 571 arcmsr_flush_hba_cache(acb); 572 } 573 break; 574 case ACB_ADAPTER_TYPE_B: { 575 arcmsr_flush_hbb_cache(acb); 576 } 577 break; 578 case ACB_ADAPTER_TYPE_C: { 579 arcmsr_flush_hbc_cache(acb); 580 } 581 break; 582 case ACB_ADAPTER_TYPE_D: { 583 arcmsr_flush_hbd_cache(acb); 584 } 585 break; 586 case ACB_ADAPTER_TYPE_E: 587 case ACB_ADAPTER_TYPE_F: { 588 arcmsr_flush_hbe_cache(acb); 589 } 590 break; 591 } 592 } 593 /* 594 ******************************************************************************* 595 ******************************************************************************* 596 */ 597 static int arcmsr_suspend(device_t dev) 598 { 599 struct AdapterControlBlock *acb = device_get_softc(dev); 600 601 /* flush controller */ 602 arcmsr_iop_parking(acb); 603 /* disable all outbound interrupt */ 604 arcmsr_disable_allintr(acb); 605 return(0); 606 } 607 /* 608 ******************************************************************************* 609 ******************************************************************************* 610 */ 611 static int arcmsr_resume(device_t dev) 612 { 613 struct AdapterControlBlock *acb = device_get_softc(dev); 614 615 arcmsr_iop_init(acb); 616 return(0); 617 } 618 /* 619 ********************************************************************************* 620 ********************************************************************************* 621 */ 622 static void arcmsr_async(void *cb_arg, u_int32_t code, struct cam_path *path, void *arg) 623 { 624 u_int8_t target_id, target_lun; 625 626 switch (code) { 627 case AC_LOST_DEVICE: 628 target_id = xpt_path_target_id(path); 629 target_lun = xpt_path_lun_id(path); 630 if((target_id > ARCMSR_MAX_TARGETID) || (target_lun > ARCMSR_MAX_TARGETLUN)) { 631 break; 632 } 633 break; 634 default: 635 break; 636 } 637 } 638 /* 639 ********************************************************************** 640 ********************************************************************** 641 */ 642 static void arcmsr_report_sense_info(struct CommandControlBlock *srb) 643 { 644 union ccb *pccb = srb->pccb; 645 646 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 647 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 648 if(pccb->csio.sense_len) { 649 memset(&pccb->csio.sense_data, 0, sizeof(pccb->csio.sense_data)); 650 memcpy(&pccb->csio.sense_data, srb->arcmsr_cdb.SenseData, 651 get_min(sizeof(struct SENSE_DATA), sizeof(pccb->csio.sense_data))); 652 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); /* Valid,ErrorCode */ 653 pccb->ccb_h.status |= CAM_AUTOSNS_VALID; 654 } 655 } 656 /* 657 ********************************************************************* 658 ********************************************************************* 659 */ 660 static void arcmsr_abort_hba_allcmd(struct AdapterControlBlock *acb) 661 { 662 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 663 if(!arcmsr_hba_wait_msgint_ready(acb)) { 664 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 665 } 666 } 667 /* 668 ********************************************************************* 669 ********************************************************************* 670 */ 671 static void arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb) 672 { 673 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 674 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_ABORT_CMD); 675 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 676 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 677 } 678 } 679 /* 680 ********************************************************************* 681 ********************************************************************* 682 */ 683 static void arcmsr_abort_hbc_allcmd(struct AdapterControlBlock *acb) 684 { 685 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 686 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 687 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 688 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 689 } 690 } 691 /* 692 ********************************************************************* 693 ********************************************************************* 694 */ 695 static void arcmsr_abort_hbd_allcmd(struct AdapterControlBlock *acb) 696 { 697 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 698 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 699 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 700 } 701 } 702 /* 703 ********************************************************************* 704 ********************************************************************* 705 */ 706 static void arcmsr_abort_hbe_allcmd(struct AdapterControlBlock *acb) 707 { 708 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 709 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 710 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 711 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 712 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 713 } 714 } 715 /* 716 ********************************************************************* 717 ********************************************************************* 718 */ 719 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb) 720 { 721 switch (acb->adapter_type) { 722 case ACB_ADAPTER_TYPE_A: { 723 arcmsr_abort_hba_allcmd(acb); 724 } 725 break; 726 case ACB_ADAPTER_TYPE_B: { 727 arcmsr_abort_hbb_allcmd(acb); 728 } 729 break; 730 case ACB_ADAPTER_TYPE_C: { 731 arcmsr_abort_hbc_allcmd(acb); 732 } 733 break; 734 case ACB_ADAPTER_TYPE_D: { 735 arcmsr_abort_hbd_allcmd(acb); 736 } 737 break; 738 case ACB_ADAPTER_TYPE_E: 739 case ACB_ADAPTER_TYPE_F: { 740 arcmsr_abort_hbe_allcmd(acb); 741 } 742 break; 743 } 744 } 745 /* 746 ********************************************************************** 747 ********************************************************************** 748 */ 749 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag) 750 { 751 struct AdapterControlBlock *acb = srb->acb; 752 union ccb *pccb = srb->pccb; 753 754 if(srb->srb_flags & SRB_FLAG_TIMER_START) 755 callout_stop(&srb->ccb_callout); 756 if((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 757 bus_dmasync_op_t op; 758 759 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 760 op = BUS_DMASYNC_POSTREAD; 761 } else { 762 op = BUS_DMASYNC_POSTWRITE; 763 } 764 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op); 765 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap); 766 } 767 if(stand_flag == 1) { 768 atomic_subtract_int(&acb->srboutstandingcount, 1); 769 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) && ( 770 acb->srboutstandingcount < (acb->maxOutstanding -10))) { 771 acb->acb_flags &= ~ACB_F_CAM_DEV_QFRZN; 772 pccb->ccb_h.status |= CAM_RELEASE_SIMQ; 773 } 774 } 775 if(srb->srb_state != ARCMSR_SRB_TIMEOUT) 776 arcmsr_free_srb(srb); 777 acb->pktReturnCount++; 778 xpt_done(pccb); 779 } 780 /* 781 ************************************************************************** 782 ************************************************************************** 783 */ 784 static void arcmsr_report_srb_state(struct AdapterControlBlock *acb, struct CommandControlBlock *srb, u_int16_t error) 785 { 786 int target, lun; 787 788 target = srb->pccb->ccb_h.target_id; 789 lun = srb->pccb->ccb_h.target_lun; 790 if(error == FALSE) { 791 if(acb->devstate[target][lun] == ARECA_RAID_GONE) { 792 acb->devstate[target][lun] = ARECA_RAID_GOOD; 793 } 794 srb->pccb->ccb_h.status |= CAM_REQ_CMP; 795 arcmsr_srb_complete(srb, 1); 796 } else { 797 switch(srb->arcmsr_cdb.DeviceStatus) { 798 case ARCMSR_DEV_SELECT_TIMEOUT: { 799 if(acb->devstate[target][lun] == ARECA_RAID_GOOD) { 800 printf( "arcmsr%d: Target=%x, Lun=%x, selection timeout, raid volume was lost\n", acb->pci_unit, target, lun); 801 } 802 acb->devstate[target][lun] = ARECA_RAID_GONE; 803 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 804 arcmsr_srb_complete(srb, 1); 805 } 806 break; 807 case ARCMSR_DEV_ABORTED: 808 case ARCMSR_DEV_INIT_FAIL: { 809 acb->devstate[target][lun] = ARECA_RAID_GONE; 810 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 811 arcmsr_srb_complete(srb, 1); 812 } 813 break; 814 case SCSISTAT_CHECK_CONDITION: { 815 acb->devstate[target][lun] = ARECA_RAID_GOOD; 816 arcmsr_report_sense_info(srb); 817 arcmsr_srb_complete(srb, 1); 818 } 819 break; 820 default: 821 printf("arcmsr%d: scsi id=%d lun=%d isr got command error done,but got unknown DeviceStatus=0x%x \n" 822 , acb->pci_unit, target, lun ,srb->arcmsr_cdb.DeviceStatus); 823 acb->devstate[target][lun] = ARECA_RAID_GONE; 824 srb->pccb->ccb_h.status |= CAM_UNCOR_PARITY; 825 /*unknown error or crc error just for retry*/ 826 arcmsr_srb_complete(srb, 1); 827 break; 828 } 829 } 830 } 831 /* 832 ************************************************************************** 833 ************************************************************************** 834 */ 835 static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, u_int32_t flag_srb, u_int16_t error) 836 { 837 struct CommandControlBlock *srb; 838 839 /* check if command done with no error*/ 840 switch (acb->adapter_type) { 841 case ACB_ADAPTER_TYPE_A: 842 case ACB_ADAPTER_TYPE_B: 843 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 844 break; 845 case ACB_ADAPTER_TYPE_C: 846 case ACB_ADAPTER_TYPE_D: 847 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0)); /*frame must be 32 bytes aligned*/ 848 break; 849 case ACB_ADAPTER_TYPE_E: 850 case ACB_ADAPTER_TYPE_F: 851 srb = acb->psrb_pool[flag_srb]; 852 break; 853 default: 854 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 855 break; 856 } 857 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 858 if(srb->srb_state == ARCMSR_SRB_TIMEOUT) { 859 arcmsr_free_srb(srb); 860 printf("arcmsr%d: srb='%p' return srb has been timeouted\n", acb->pci_unit, srb); 861 return; 862 } 863 printf("arcmsr%d: return srb has been completed\n" 864 "srb='%p' srb_state=0x%x outstanding srb count=%d \n", 865 acb->pci_unit, srb, srb->srb_state, acb->srboutstandingcount); 866 return; 867 } 868 arcmsr_report_srb_state(acb, srb, error); 869 } 870 /* 871 ************************************************************************** 872 ************************************************************************** 873 */ 874 static void arcmsr_srb_timeout(void *arg) 875 { 876 struct CommandControlBlock *srb = (struct CommandControlBlock *)arg; 877 struct AdapterControlBlock *acb; 878 int target, lun; 879 u_int8_t cmd; 880 881 target = srb->pccb->ccb_h.target_id; 882 lun = srb->pccb->ccb_h.target_lun; 883 acb = srb->acb; 884 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 885 if(srb->srb_state == ARCMSR_SRB_START) 886 { 887 cmd = scsiio_cdb_ptr(&srb->pccb->csio)[0]; 888 srb->srb_state = ARCMSR_SRB_TIMEOUT; 889 srb->pccb->ccb_h.status |= CAM_CMD_TIMEOUT; 890 arcmsr_srb_complete(srb, 1); 891 printf("arcmsr%d: scsi id %d lun %d cmd=0x%x srb='%p' ccb command time out!\n", 892 acb->pci_unit, target, lun, cmd, srb); 893 } 894 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 895 #ifdef ARCMSR_DEBUG1 896 arcmsr_dump_data(acb); 897 #endif 898 } 899 900 /* 901 ********************************************************************** 902 ********************************************************************** 903 */ 904 static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb) 905 { 906 int i=0; 907 u_int32_t flag_srb; 908 u_int16_t error; 909 910 switch (acb->adapter_type) { 911 case ACB_ADAPTER_TYPE_A: { 912 u_int32_t outbound_intstatus; 913 914 /*clear and abort all outbound posted Q*/ 915 outbound_intstatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 916 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);/*clear interrupt*/ 917 while(((flag_srb=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_queueport)) != 0xFFFFFFFF) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) { 918 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 919 arcmsr_drain_donequeue(acb, flag_srb, error); 920 } 921 } 922 break; 923 case ACB_ADAPTER_TYPE_B: { 924 struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu; 925 926 /*clear all outbound posted Q*/ 927 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */ 928 for(i=0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) { 929 if((flag_srb = phbbmu->done_qbuffer[i]) != 0) { 930 phbbmu->done_qbuffer[i] = 0; 931 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 932 arcmsr_drain_donequeue(acb, flag_srb, error); 933 } 934 phbbmu->post_qbuffer[i] = 0; 935 }/*drain reply FIFO*/ 936 phbbmu->doneq_index = 0; 937 phbbmu->postq_index = 0; 938 } 939 break; 940 case ACB_ADAPTER_TYPE_C: { 941 while((CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) { 942 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 943 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 944 arcmsr_drain_donequeue(acb, flag_srb, error); 945 } 946 } 947 break; 948 case ACB_ADAPTER_TYPE_D: 949 arcmsr_hbd_postqueue_isr(acb); 950 break; 951 case ACB_ADAPTER_TYPE_E: 952 arcmsr_hbe_postqueue_isr(acb); 953 break; 954 case ACB_ADAPTER_TYPE_F: 955 arcmsr_hbf_postqueue_isr(acb); 956 break; 957 } 958 } 959 /* 960 **************************************************************************** 961 **************************************************************************** 962 */ 963 static void arcmsr_iop_reset(struct AdapterControlBlock *acb) 964 { 965 struct CommandControlBlock *srb; 966 u_int32_t intmask_org; 967 u_int32_t i=0; 968 969 if(acb->srboutstandingcount>0) { 970 /* disable all outbound interrupt */ 971 intmask_org = arcmsr_disable_allintr(acb); 972 /*clear and abort all outbound posted Q*/ 973 arcmsr_done4abort_postqueue(acb); 974 /* talk to iop 331 outstanding command aborted*/ 975 arcmsr_abort_allcmd(acb); 976 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 977 srb = acb->psrb_pool[i]; 978 if(srb->srb_state == ARCMSR_SRB_START) { 979 srb->srb_state = ARCMSR_SRB_ABORTED; 980 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 981 arcmsr_srb_complete(srb, 1); 982 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p' aborted\n" 983 , acb->pci_unit, srb->pccb->ccb_h.target_id 984 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 985 } 986 } 987 /* enable all outbound interrupt */ 988 arcmsr_enable_allintr(acb, intmask_org); 989 } 990 acb->srboutstandingcount = 0; 991 acb->workingsrb_doneindex = 0; 992 acb->workingsrb_startindex = 0; 993 acb->pktRequestCount = 0; 994 acb->pktReturnCount = 0; 995 } 996 /* 997 ********************************************************************** 998 ********************************************************************** 999 */ 1000 static void arcmsr_build_srb(struct CommandControlBlock *srb, 1001 bus_dma_segment_t *dm_segs, u_int32_t nseg) 1002 { 1003 struct ARCMSR_CDB *arcmsr_cdb = &srb->arcmsr_cdb; 1004 u_int8_t *psge = (u_int8_t *)&arcmsr_cdb->u; 1005 u_int32_t address_lo, address_hi; 1006 union ccb *pccb = srb->pccb; 1007 struct ccb_scsiio *pcsio = &pccb->csio; 1008 u_int32_t arccdbsize = 0x30; 1009 1010 memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB)); 1011 arcmsr_cdb->Bus = 0; 1012 arcmsr_cdb->TargetID = pccb->ccb_h.target_id; 1013 arcmsr_cdb->LUN = pccb->ccb_h.target_lun; 1014 arcmsr_cdb->Function = 1; 1015 arcmsr_cdb->CdbLength = (u_int8_t)pcsio->cdb_len; 1016 bcopy(scsiio_cdb_ptr(pcsio), arcmsr_cdb->Cdb, pcsio->cdb_len); 1017 if(nseg != 0) { 1018 struct AdapterControlBlock *acb = srb->acb; 1019 bus_dmasync_op_t op; 1020 u_int32_t length, i, cdb_sgcount = 0; 1021 1022 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1023 op = BUS_DMASYNC_PREREAD; 1024 } else { 1025 op = BUS_DMASYNC_PREWRITE; 1026 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE; 1027 srb->srb_flags |= SRB_FLAG_WRITE; 1028 } 1029 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op); 1030 for(i=0; i < nseg; i++) { 1031 /* Get the physical address of the current data pointer */ 1032 length = arcmsr_htole32(dm_segs[i].ds_len); 1033 address_lo = arcmsr_htole32(dma_addr_lo32(dm_segs[i].ds_addr)); 1034 address_hi = arcmsr_htole32(dma_addr_hi32(dm_segs[i].ds_addr)); 1035 if(address_hi == 0) { 1036 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge; 1037 pdma_sg->address = address_lo; 1038 pdma_sg->length = length; 1039 psge += sizeof(struct SG32ENTRY); 1040 arccdbsize += sizeof(struct SG32ENTRY); 1041 } else { 1042 u_int32_t sg64s_size = 0, tmplength = length; 1043 1044 while(1) { 1045 u_int64_t span4G, length0; 1046 struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge; 1047 1048 span4G = (u_int64_t)address_lo + tmplength; 1049 pdma_sg->addresshigh = address_hi; 1050 pdma_sg->address = address_lo; 1051 if(span4G > 0x100000000) { 1052 /*see if cross 4G boundary*/ 1053 length0 = 0x100000000-address_lo; 1054 pdma_sg->length = (u_int32_t)length0 | IS_SG64_ADDR; 1055 address_hi = address_hi+1; 1056 address_lo = 0; 1057 tmplength = tmplength - (u_int32_t)length0; 1058 sg64s_size += sizeof(struct SG64ENTRY); 1059 psge += sizeof(struct SG64ENTRY); 1060 cdb_sgcount++; 1061 } else { 1062 pdma_sg->length = tmplength | IS_SG64_ADDR; 1063 sg64s_size += sizeof(struct SG64ENTRY); 1064 psge += sizeof(struct SG64ENTRY); 1065 break; 1066 } 1067 } 1068 arccdbsize += sg64s_size; 1069 } 1070 cdb_sgcount++; 1071 } 1072 arcmsr_cdb->sgcount = (u_int8_t)cdb_sgcount; 1073 arcmsr_cdb->DataLength = pcsio->dxfer_len; 1074 if( arccdbsize > 256) { 1075 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE; 1076 } 1077 } else { 1078 arcmsr_cdb->DataLength = 0; 1079 } 1080 srb->arc_cdb_size = arccdbsize; 1081 arcmsr_cdb->msgPages = (arccdbsize/256) + ((arccdbsize % 256) ? 1 : 0); 1082 } 1083 /* 1084 ************************************************************************** 1085 ************************************************************************** 1086 */ 1087 static void arcmsr_post_srb(struct AdapterControlBlock *acb, struct CommandControlBlock *srb) 1088 { 1089 u_int32_t cdb_phyaddr_low = (u_int32_t) srb->cdb_phyaddr_low; 1090 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&srb->arcmsr_cdb; 1091 1092 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, (srb->srb_flags & SRB_FLAG_WRITE) ? BUS_DMASYNC_POSTWRITE:BUS_DMASYNC_POSTREAD); 1093 atomic_add_int(&acb->srboutstandingcount, 1); 1094 srb->srb_state = ARCMSR_SRB_START; 1095 1096 switch (acb->adapter_type) { 1097 case ACB_ADAPTER_TYPE_A: { 1098 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { 1099 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low|ARCMSR_SRBPOST_FLAG_SGL_BSIZE); 1100 } else { 1101 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low); 1102 } 1103 } 1104 break; 1105 case ACB_ADAPTER_TYPE_B: { 1106 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1107 int ending_index, index; 1108 1109 index = phbbmu->postq_index; 1110 ending_index = ((index+1) % ARCMSR_MAX_HBB_POSTQUEUE); 1111 phbbmu->post_qbuffer[ending_index] = 0; 1112 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { 1113 phbbmu->post_qbuffer[index] = cdb_phyaddr_low | ARCMSR_SRBPOST_FLAG_SGL_BSIZE; 1114 } else { 1115 phbbmu->post_qbuffer[index] = cdb_phyaddr_low; 1116 } 1117 index++; 1118 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 1119 phbbmu->postq_index = index; 1120 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_CDB_POSTED); 1121 } 1122 break; 1123 case ACB_ADAPTER_TYPE_C: { 1124 u_int32_t ccb_post_stamp, arc_cdb_size, cdb_phyaddr_hi32; 1125 1126 arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size; 1127 ccb_post_stamp = (cdb_phyaddr_low | ((arc_cdb_size-1) >> 6) | 1); 1128 cdb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high; 1129 if(cdb_phyaddr_hi32) 1130 { 1131 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_high, cdb_phyaddr_hi32); 1132 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp); 1133 } 1134 else 1135 { 1136 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp); 1137 } 1138 } 1139 break; 1140 case ACB_ADAPTER_TYPE_D: { 1141 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1142 u_int16_t index_stripped; 1143 u_int16_t postq_index; 1144 struct InBound_SRB *pinbound_srb; 1145 1146 ARCMSR_LOCK_ACQUIRE(&acb->postDone_lock); 1147 postq_index = phbdmu->postq_index; 1148 pinbound_srb = (struct InBound_SRB *)&phbdmu->post_qbuffer[postq_index & 0xFF]; 1149 pinbound_srb->addressHigh = srb->cdb_phyaddr_high; 1150 pinbound_srb->addressLow = srb->cdb_phyaddr_low; 1151 pinbound_srb->length = srb->arc_cdb_size >> 2; 1152 arcmsr_cdb->Context = srb->cdb_phyaddr_low; 1153 if (postq_index & 0x4000) { 1154 index_stripped = postq_index & 0xFF; 1155 index_stripped += 1; 1156 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1157 phbdmu->postq_index = index_stripped ? (index_stripped | 0x4000) : index_stripped; 1158 } else { 1159 index_stripped = postq_index; 1160 index_stripped += 1; 1161 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1162 phbdmu->postq_index = index_stripped ? index_stripped : (index_stripped | 0x4000); 1163 } 1164 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inboundlist_write_pointer, postq_index); 1165 ARCMSR_LOCK_RELEASE(&acb->postDone_lock); 1166 } 1167 break; 1168 case ACB_ADAPTER_TYPE_E: { 1169 u_int32_t ccb_post_stamp, arc_cdb_size; 1170 1171 arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size; 1172 ccb_post_stamp = (srb->smid | ((arc_cdb_size-1) >> 6)); 1173 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_queueport_high, 0); 1174 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_queueport_low, ccb_post_stamp); 1175 } 1176 break; 1177 case ACB_ADAPTER_TYPE_F: { 1178 u_int32_t ccb_post_stamp, arc_cdb_size; 1179 1180 if (srb->arc_cdb_size <= 0x300) 1181 arc_cdb_size = (srb->arc_cdb_size - 1) >> 6 | 1; 1182 else { 1183 arc_cdb_size = ((srb->arc_cdb_size + 0xff) >> 8) + 2; 1184 if (arc_cdb_size > 0xF) 1185 arc_cdb_size = 0xF; 1186 arc_cdb_size = (arc_cdb_size << 1) | 1; 1187 } 1188 ccb_post_stamp = (srb->smid | arc_cdb_size); 1189 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_queueport_high, 0); 1190 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_queueport_low, ccb_post_stamp); 1191 } 1192 break; 1193 } 1194 } 1195 /* 1196 ************************************************************************ 1197 ************************************************************************ 1198 */ 1199 static struct QBUFFER *arcmsr_get_iop_rqbuffer( struct AdapterControlBlock *acb) 1200 { 1201 struct QBUFFER *qbuffer=NULL; 1202 1203 switch (acb->adapter_type) { 1204 case ACB_ADAPTER_TYPE_A: { 1205 struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu; 1206 1207 qbuffer = (struct QBUFFER *)&phbamu->message_rbuffer; 1208 } 1209 break; 1210 case ACB_ADAPTER_TYPE_B: { 1211 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1212 1213 qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_rbuffer; 1214 } 1215 break; 1216 case ACB_ADAPTER_TYPE_C: { 1217 struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu; 1218 1219 qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer; 1220 } 1221 break; 1222 case ACB_ADAPTER_TYPE_D: { 1223 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1224 1225 qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_rbuffer; 1226 } 1227 break; 1228 case ACB_ADAPTER_TYPE_E: { 1229 struct HBE_MessageUnit *phbcmu = (struct HBE_MessageUnit *)acb->pmu; 1230 1231 qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer; 1232 } 1233 break; 1234 case ACB_ADAPTER_TYPE_F: 1235 qbuffer = (struct QBUFFER *)acb->message_rbuffer; 1236 break; 1237 } 1238 return(qbuffer); 1239 } 1240 /* 1241 ************************************************************************ 1242 ************************************************************************ 1243 */ 1244 static struct QBUFFER *arcmsr_get_iop_wqbuffer( struct AdapterControlBlock *acb) 1245 { 1246 struct QBUFFER *qbuffer = NULL; 1247 1248 switch (acb->adapter_type) { 1249 case ACB_ADAPTER_TYPE_A: { 1250 struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu; 1251 1252 qbuffer = (struct QBUFFER *)&phbamu->message_wbuffer; 1253 } 1254 break; 1255 case ACB_ADAPTER_TYPE_B: { 1256 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1257 1258 qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_wbuffer; 1259 } 1260 break; 1261 case ACB_ADAPTER_TYPE_C: { 1262 struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu; 1263 1264 qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer; 1265 } 1266 break; 1267 case ACB_ADAPTER_TYPE_D: { 1268 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1269 1270 qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_wbuffer; 1271 } 1272 break; 1273 case ACB_ADAPTER_TYPE_E: { 1274 struct HBE_MessageUnit *phbcmu = (struct HBE_MessageUnit *)acb->pmu; 1275 1276 qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer; 1277 } 1278 break; 1279 case ACB_ADAPTER_TYPE_F: 1280 qbuffer = (struct QBUFFER *)acb->message_wbuffer; 1281 break; 1282 } 1283 return(qbuffer); 1284 } 1285 /* 1286 ************************************************************************** 1287 ************************************************************************** 1288 */ 1289 static void arcmsr_iop_message_read(struct AdapterControlBlock *acb) 1290 { 1291 switch (acb->adapter_type) { 1292 case ACB_ADAPTER_TYPE_A: { 1293 /* let IOP know data has been read */ 1294 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK); 1295 } 1296 break; 1297 case ACB_ADAPTER_TYPE_B: { 1298 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1299 /* let IOP know data has been read */ 1300 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK); 1301 } 1302 break; 1303 case ACB_ADAPTER_TYPE_C: { 1304 /* let IOP know data has been read */ 1305 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK); 1306 } 1307 break; 1308 case ACB_ADAPTER_TYPE_D: { 1309 /* let IOP know data has been read */ 1310 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ); 1311 } 1312 break; 1313 case ACB_ADAPTER_TYPE_E: 1314 case ACB_ADAPTER_TYPE_F: { 1315 /* let IOP know data has been read */ 1316 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK; 1317 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 1318 } 1319 break; 1320 } 1321 } 1322 /* 1323 ************************************************************************** 1324 ************************************************************************** 1325 */ 1326 static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb) 1327 { 1328 switch (acb->adapter_type) { 1329 case ACB_ADAPTER_TYPE_A: { 1330 /* 1331 ** push inbound doorbell tell iop, driver data write ok 1332 ** and wait reply on next hwinterrupt for next Qbuffer post 1333 */ 1334 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK); 1335 } 1336 break; 1337 case ACB_ADAPTER_TYPE_B: { 1338 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1339 /* 1340 ** push inbound doorbell tell iop, driver data write ok 1341 ** and wait reply on next hwinterrupt for next Qbuffer post 1342 */ 1343 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_WRITE_OK); 1344 } 1345 break; 1346 case ACB_ADAPTER_TYPE_C: { 1347 /* 1348 ** push inbound doorbell tell iop, driver data write ok 1349 ** and wait reply on next hwinterrupt for next Qbuffer post 1350 */ 1351 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK); 1352 } 1353 break; 1354 case ACB_ADAPTER_TYPE_D: { 1355 /* 1356 ** push inbound doorbell tell iop, driver data write ok 1357 ** and wait reply on next hwinterrupt for next Qbuffer post 1358 */ 1359 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY); 1360 } 1361 break; 1362 case ACB_ADAPTER_TYPE_E: 1363 case ACB_ADAPTER_TYPE_F: { 1364 /* 1365 ** push inbound doorbell tell iop, driver data write ok 1366 ** and wait reply on next hwinterrupt for next Qbuffer post 1367 */ 1368 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK; 1369 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 1370 } 1371 break; 1372 } 1373 } 1374 /* 1375 ************************************************************************ 1376 ************************************************************************ 1377 */ 1378 static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb) 1379 { 1380 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1381 CHIP_REG_WRITE32(HBA_MessageUnit, 1382 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1383 if(!arcmsr_hba_wait_msgint_ready(acb)) { 1384 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n" 1385 , acb->pci_unit); 1386 } 1387 } 1388 /* 1389 ************************************************************************ 1390 ************************************************************************ 1391 */ 1392 static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb) 1393 { 1394 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1395 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1396 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_STOP_BGRB); 1397 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 1398 printf( "arcmsr%d: wait 'stop adapter background rebulid' timeout \n" 1399 , acb->pci_unit); 1400 } 1401 } 1402 /* 1403 ************************************************************************ 1404 ************************************************************************ 1405 */ 1406 static void arcmsr_stop_hbc_bgrb(struct AdapterControlBlock *acb) 1407 { 1408 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1409 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1410 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 1411 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 1412 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1413 } 1414 } 1415 /* 1416 ************************************************************************ 1417 ************************************************************************ 1418 */ 1419 static void arcmsr_stop_hbd_bgrb(struct AdapterControlBlock *acb) 1420 { 1421 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1422 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1423 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 1424 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1425 } 1426 } 1427 /* 1428 ************************************************************************ 1429 ************************************************************************ 1430 */ 1431 static void arcmsr_stop_hbe_bgrb(struct AdapterControlBlock *acb) 1432 { 1433 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1434 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1435 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 1436 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 1437 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 1438 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1439 } 1440 } 1441 /* 1442 ************************************************************************ 1443 ************************************************************************ 1444 */ 1445 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb) 1446 { 1447 switch (acb->adapter_type) { 1448 case ACB_ADAPTER_TYPE_A: { 1449 arcmsr_stop_hba_bgrb(acb); 1450 } 1451 break; 1452 case ACB_ADAPTER_TYPE_B: { 1453 arcmsr_stop_hbb_bgrb(acb); 1454 } 1455 break; 1456 case ACB_ADAPTER_TYPE_C: { 1457 arcmsr_stop_hbc_bgrb(acb); 1458 } 1459 break; 1460 case ACB_ADAPTER_TYPE_D: { 1461 arcmsr_stop_hbd_bgrb(acb); 1462 } 1463 break; 1464 case ACB_ADAPTER_TYPE_E: 1465 case ACB_ADAPTER_TYPE_F: { 1466 arcmsr_stop_hbe_bgrb(acb); 1467 } 1468 break; 1469 } 1470 } 1471 /* 1472 ************************************************************************ 1473 ************************************************************************ 1474 */ 1475 static void arcmsr_poll(struct cam_sim *psim) 1476 { 1477 struct AdapterControlBlock *acb; 1478 int mutex; 1479 1480 acb = (struct AdapterControlBlock *)cam_sim_softc(psim); 1481 mutex = mtx_owned(&acb->isr_lock); 1482 if( mutex == 0 ) 1483 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 1484 arcmsr_interrupt(acb); 1485 if( mutex == 0 ) 1486 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 1487 } 1488 /* 1489 ************************************************************************** 1490 ************************************************************************** 1491 */ 1492 static u_int32_t arcmsr_Read_iop_rqbuffer_data_D(struct AdapterControlBlock *acb, 1493 struct QBUFFER *prbuffer) { 1494 u_int8_t *pQbuffer; 1495 u_int8_t *buf1 = NULL; 1496 u_int32_t *iop_data, *buf2 = NULL; 1497 u_int32_t iop_len, data_len; 1498 1499 iop_data = (u_int32_t *)prbuffer->data; 1500 iop_len = (u_int32_t)prbuffer->data_len; 1501 if ( iop_len > 0 ) 1502 { 1503 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO); 1504 buf2 = (u_int32_t *)buf1; 1505 if( buf1 == NULL) 1506 return (0); 1507 data_len = iop_len; 1508 while(data_len >= 4) 1509 { 1510 *buf2++ = *iop_data++; 1511 data_len -= 4; 1512 } 1513 if(data_len) 1514 *buf2 = *iop_data; 1515 buf2 = (u_int32_t *)buf1; 1516 } 1517 while (iop_len > 0) { 1518 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex]; 1519 *pQbuffer = *buf1; 1520 acb->rqbuf_lastindex++; 1521 /* if last, index number set it to 0 */ 1522 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 1523 buf1++; 1524 iop_len--; 1525 } 1526 if(buf2) 1527 free( (u_int8_t *)buf2, M_DEVBUF); 1528 /* let IOP know data has been read */ 1529 arcmsr_iop_message_read(acb); 1530 return (1); 1531 } 1532 /* 1533 ************************************************************************** 1534 ************************************************************************** 1535 */ 1536 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, 1537 struct QBUFFER *prbuffer) { 1538 u_int8_t *pQbuffer; 1539 u_int8_t *iop_data; 1540 u_int32_t iop_len; 1541 1542 if(acb->adapter_type >= ACB_ADAPTER_TYPE_B) { 1543 return(arcmsr_Read_iop_rqbuffer_data_D(acb, prbuffer)); 1544 } 1545 iop_data = (u_int8_t *)prbuffer->data; 1546 iop_len = (u_int32_t)prbuffer->data_len; 1547 while (iop_len > 0) { 1548 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex]; 1549 *pQbuffer = *iop_data; 1550 acb->rqbuf_lastindex++; 1551 /* if last, index number set it to 0 */ 1552 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 1553 iop_data++; 1554 iop_len--; 1555 } 1556 /* let IOP know data has been read */ 1557 arcmsr_iop_message_read(acb); 1558 return (1); 1559 } 1560 /* 1561 ************************************************************************** 1562 ************************************************************************** 1563 */ 1564 static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb) 1565 { 1566 struct QBUFFER *prbuffer; 1567 int my_empty_len; 1568 1569 /*check this iop data if overflow my rqbuffer*/ 1570 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 1571 prbuffer = arcmsr_get_iop_rqbuffer(acb); 1572 my_empty_len = (acb->rqbuf_lastindex - acb->rqbuf_firstindex - 1) & 1573 (ARCMSR_MAX_QBUFFER-1); 1574 if(my_empty_len >= prbuffer->data_len) { 1575 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 1576 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 1577 } else { 1578 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 1579 } 1580 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 1581 } 1582 /* 1583 ********************************************************************** 1584 ********************************************************************** 1585 */ 1586 static void arcmsr_Write_data_2iop_wqbuffer_D(struct AdapterControlBlock *acb) 1587 { 1588 u_int8_t *pQbuffer; 1589 struct QBUFFER *pwbuffer; 1590 u_int8_t *buf1 = NULL; 1591 u_int32_t *iop_data, *buf2 = NULL; 1592 u_int32_t allxfer_len = 0, data_len; 1593 1594 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) { 1595 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO); 1596 buf2 = (u_int32_t *)buf1; 1597 if( buf1 == NULL) 1598 return; 1599 1600 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ); 1601 pwbuffer = arcmsr_get_iop_wqbuffer(acb); 1602 iop_data = (u_int32_t *)pwbuffer->data; 1603 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex) 1604 && (allxfer_len < 124)) { 1605 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex]; 1606 *buf1 = *pQbuffer; 1607 acb->wqbuf_firstindex++; 1608 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 1609 buf1++; 1610 allxfer_len++; 1611 } 1612 pwbuffer->data_len = allxfer_len; 1613 data_len = allxfer_len; 1614 buf1 = (u_int8_t *)buf2; 1615 while(data_len >= 4) 1616 { 1617 *iop_data++ = *buf2++; 1618 data_len -= 4; 1619 } 1620 if(data_len) 1621 *iop_data = *buf2; 1622 free( buf1, M_DEVBUF); 1623 arcmsr_iop_message_wrote(acb); 1624 } 1625 } 1626 /* 1627 ********************************************************************** 1628 ********************************************************************** 1629 */ 1630 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb) 1631 { 1632 u_int8_t *pQbuffer; 1633 struct QBUFFER *pwbuffer; 1634 u_int8_t *iop_data; 1635 int32_t allxfer_len=0; 1636 1637 if(acb->adapter_type >= ACB_ADAPTER_TYPE_B) { 1638 arcmsr_Write_data_2iop_wqbuffer_D(acb); 1639 return; 1640 } 1641 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) { 1642 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ); 1643 pwbuffer = arcmsr_get_iop_wqbuffer(acb); 1644 iop_data = (u_int8_t *)pwbuffer->data; 1645 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex) 1646 && (allxfer_len < 124)) { 1647 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex]; 1648 *iop_data = *pQbuffer; 1649 acb->wqbuf_firstindex++; 1650 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 1651 iop_data++; 1652 allxfer_len++; 1653 } 1654 pwbuffer->data_len = allxfer_len; 1655 arcmsr_iop_message_wrote(acb); 1656 } 1657 } 1658 /* 1659 ************************************************************************** 1660 ************************************************************************** 1661 */ 1662 static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb) 1663 { 1664 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 1665 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READ; 1666 /* 1667 ***************************************************************** 1668 ** check if there are any mail packages from user space program 1669 ** in my post bag, now is the time to send them into Areca's firmware 1670 ***************************************************************** 1671 */ 1672 if(acb->wqbuf_firstindex != acb->wqbuf_lastindex) { 1673 arcmsr_Write_data_2iop_wqbuffer(acb); 1674 } 1675 if(acb->wqbuf_firstindex == acb->wqbuf_lastindex) { 1676 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED; 1677 } 1678 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 1679 } 1680 /* 1681 ************************************************************************** 1682 ************************************************************************** 1683 */ 1684 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb) 1685 { 1686 /* 1687 if (ccb->ccb_h.status != CAM_REQ_CMP) 1688 printf("arcmsr_rescanLun_cb: Rescan Target=%x, lun=%x," 1689 "failure status=%x\n", ccb->ccb_h.target_id, 1690 ccb->ccb_h.target_lun, ccb->ccb_h.status); 1691 else 1692 printf("arcmsr_rescanLun_cb: Rescan lun successfully!\n"); 1693 */ 1694 xpt_free_path(ccb->ccb_h.path); 1695 xpt_free_ccb(ccb); 1696 } 1697 1698 static void arcmsr_rescan_lun(struct AdapterControlBlock *acb, int target, int lun) 1699 { 1700 struct cam_path *path; 1701 union ccb *ccb; 1702 1703 if ((ccb = (union ccb *)xpt_alloc_ccb_nowait()) == NULL) 1704 return; 1705 if (xpt_create_path(&path, NULL, cam_sim_path(acb->psim), target, lun) != CAM_REQ_CMP) 1706 { 1707 xpt_free_ccb(ccb); 1708 return; 1709 } 1710 /* printf("arcmsr_rescan_lun: Rescan Target=%x, Lun=%x\n", target, lun); */ 1711 xpt_setup_ccb(&ccb->ccb_h, path, 5); 1712 ccb->ccb_h.func_code = XPT_SCAN_LUN; 1713 ccb->ccb_h.cbfcnp = arcmsr_rescanLun_cb; 1714 ccb->crcn.flags = CAM_FLAG_NONE; 1715 xpt_action(ccb); 1716 } 1717 1718 static void arcmsr_abort_dr_ccbs(struct AdapterControlBlock *acb, int target, int lun) 1719 { 1720 struct CommandControlBlock *srb; 1721 u_int32_t intmask_org; 1722 int i; 1723 1724 /* disable all outbound interrupts */ 1725 intmask_org = arcmsr_disable_allintr(acb); 1726 for (i = 0; i < ARCMSR_MAX_FREESRB_NUM; i++) 1727 { 1728 srb = acb->psrb_pool[i]; 1729 if (srb->srb_state == ARCMSR_SRB_START) 1730 { 1731 if((target == srb->pccb->ccb_h.target_id) && (lun == srb->pccb->ccb_h.target_lun)) 1732 { 1733 srb->srb_state = ARCMSR_SRB_ABORTED; 1734 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 1735 arcmsr_srb_complete(srb, 1); 1736 printf("arcmsr%d: abort scsi id %d lun %d srb=%p \n", acb->pci_unit, target, lun, srb); 1737 } 1738 } 1739 } 1740 /* enable outbound Post Queue, outbound doorbell Interrupt */ 1741 arcmsr_enable_allintr(acb, intmask_org); 1742 } 1743 /* 1744 ************************************************************************** 1745 ************************************************************************** 1746 */ 1747 static void arcmsr_dr_handle(struct AdapterControlBlock *acb) { 1748 u_int32_t devicemap; 1749 u_int32_t target, lun; 1750 u_int32_t deviceMapCurrent[4]={0}; 1751 u_int8_t *pDevMap; 1752 1753 switch (acb->adapter_type) { 1754 case ACB_ADAPTER_TYPE_A: 1755 devicemap = offsetof(struct HBA_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1756 for (target = 0; target < 4; target++) 1757 { 1758 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1759 devicemap += 4; 1760 } 1761 break; 1762 1763 case ACB_ADAPTER_TYPE_B: 1764 devicemap = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1765 for (target = 0; target < 4; target++) 1766 { 1767 deviceMapCurrent[target]=bus_space_read_4(acb->btag[1], acb->bhandle[1], devicemap); 1768 devicemap += 4; 1769 } 1770 break; 1771 1772 case ACB_ADAPTER_TYPE_C: 1773 devicemap = offsetof(struct HBC_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1774 for (target = 0; target < 4; target++) 1775 { 1776 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1777 devicemap += 4; 1778 } 1779 break; 1780 case ACB_ADAPTER_TYPE_D: 1781 devicemap = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1782 for (target = 0; target < 4; target++) 1783 { 1784 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1785 devicemap += 4; 1786 } 1787 break; 1788 case ACB_ADAPTER_TYPE_E: 1789 devicemap = offsetof(struct HBE_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1790 for (target = 0; target < 4; target++) 1791 { 1792 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1793 devicemap += 4; 1794 } 1795 break; 1796 case ACB_ADAPTER_TYPE_F: 1797 devicemap = ARCMSR_FW_DEVMAP_OFFSET; 1798 for (target = 0; target < 4; target++) 1799 { 1800 deviceMapCurrent[target] = acb->msgcode_rwbuffer[devicemap]; 1801 devicemap += 1; 1802 } 1803 break; 1804 } 1805 1806 if(acb->acb_flags & ACB_F_BUS_HANG_ON) 1807 { 1808 acb->acb_flags &= ~ACB_F_BUS_HANG_ON; 1809 } 1810 /* 1811 ** adapter posted CONFIG message 1812 ** copy the new map, note if there are differences with the current map 1813 */ 1814 pDevMap = (u_int8_t *)&deviceMapCurrent[0]; 1815 for (target = 0; target < ARCMSR_MAX_TARGETID - 1; target++) 1816 { 1817 if (*pDevMap != acb->device_map[target]) 1818 { 1819 u_int8_t difference, bit_check; 1820 1821 difference = *pDevMap ^ acb->device_map[target]; 1822 for(lun=0; lun < ARCMSR_MAX_TARGETLUN; lun++) 1823 { 1824 bit_check = (1 << lun); /*check bit from 0....31*/ 1825 if(difference & bit_check) 1826 { 1827 if(acb->device_map[target] & bit_check) 1828 {/* unit departed */ 1829 printf("arcmsr_dr_handle: Target=%x, lun=%x, GONE!!!\n",target,lun); 1830 arcmsr_abort_dr_ccbs(acb, target, lun); 1831 arcmsr_rescan_lun(acb, target, lun); 1832 acb->devstate[target][lun] = ARECA_RAID_GONE; 1833 } 1834 else 1835 {/* unit arrived */ 1836 printf("arcmsr_dr_handle: Target=%x, lun=%x, Plug-IN!!!\n",target,lun); 1837 arcmsr_rescan_lun(acb, target, lun); 1838 acb->devstate[target][lun] = ARECA_RAID_GOOD; 1839 } 1840 } 1841 } 1842 /* printf("arcmsr_dr_handle: acb->device_map[%x]=0x%x, deviceMapCurrent[%x]=%x\n",target,acb->device_map[target],target,*pDevMap); */ 1843 acb->device_map[target] = *pDevMap; 1844 } 1845 pDevMap++; 1846 } 1847 } 1848 /* 1849 ************************************************************************** 1850 ************************************************************************** 1851 */ 1852 static void arcmsr_hba_message_isr(struct AdapterControlBlock *acb) { 1853 u_int32_t outbound_message; 1854 1855 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT); 1856 outbound_message = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[0]); 1857 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1858 arcmsr_dr_handle( acb ); 1859 } 1860 /* 1861 ************************************************************************** 1862 ************************************************************************** 1863 */ 1864 static void arcmsr_hbb_message_isr(struct AdapterControlBlock *acb) { 1865 u_int32_t outbound_message; 1866 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1867 1868 /* clear interrupts */ 1869 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN); 1870 outbound_message = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0]); 1871 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1872 arcmsr_dr_handle( acb ); 1873 } 1874 /* 1875 ************************************************************************** 1876 ************************************************************************** 1877 */ 1878 static void arcmsr_hbc_message_isr(struct AdapterControlBlock *acb) { 1879 u_int32_t outbound_message; 1880 1881 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR); 1882 outbound_message = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[0]); 1883 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1884 arcmsr_dr_handle( acb ); 1885 } 1886 /* 1887 ************************************************************************** 1888 ************************************************************************** 1889 */ 1890 static void arcmsr_hbd_message_isr(struct AdapterControlBlock *acb) { 1891 u_int32_t outbound_message; 1892 1893 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR); 1894 outbound_message = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[0]); 1895 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1896 arcmsr_dr_handle( acb ); 1897 } 1898 /* 1899 ************************************************************************** 1900 ************************************************************************** 1901 */ 1902 static void arcmsr_hbe_message_isr(struct AdapterControlBlock *acb) { 1903 u_int32_t outbound_message; 1904 1905 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); 1906 if (acb->adapter_type == ACB_ADAPTER_TYPE_E) 1907 outbound_message = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[0]); 1908 else 1909 outbound_message = acb->msgcode_rwbuffer[0]; 1910 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1911 arcmsr_dr_handle( acb ); 1912 } 1913 /* 1914 ************************************************************************** 1915 ************************************************************************** 1916 */ 1917 static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb) 1918 { 1919 u_int32_t doorbell_status; 1920 1921 /* 1922 ******************************************************************* 1923 ** Maybe here we need to check wrqbuffer_lock is lock or not 1924 ** DOORBELL: din! don! 1925 ** check if there are any mail need to pack from firmware 1926 ******************************************************************* 1927 */ 1928 doorbell_status = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell); 1929 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */ 1930 if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) { 1931 arcmsr_iop2drv_data_wrote_handle(acb); 1932 } 1933 if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) { 1934 arcmsr_iop2drv_data_read_handle(acb); 1935 } 1936 } 1937 /* 1938 ************************************************************************** 1939 ************************************************************************** 1940 */ 1941 static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *acb) 1942 { 1943 u_int32_t doorbell_status; 1944 1945 /* 1946 ******************************************************************* 1947 ** Maybe here we need to check wrqbuffer_lock is lock or not 1948 ** DOORBELL: din! don! 1949 ** check if there are any mail need to pack from firmware 1950 ******************************************************************* 1951 */ 1952 doorbell_status = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell); 1953 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, doorbell_status); /* clear doorbell interrupt */ 1954 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) { 1955 arcmsr_iop2drv_data_wrote_handle(acb); 1956 } 1957 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) { 1958 arcmsr_iop2drv_data_read_handle(acb); 1959 } 1960 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 1961 arcmsr_hbc_message_isr(acb); /* messenger of "driver to iop commands" */ 1962 } 1963 } 1964 /* 1965 ************************************************************************** 1966 ************************************************************************** 1967 */ 1968 static void arcmsr_hbd_doorbell_isr(struct AdapterControlBlock *acb) 1969 { 1970 u_int32_t doorbell_status; 1971 1972 /* 1973 ******************************************************************* 1974 ** Maybe here we need to check wrqbuffer_lock is lock or not 1975 ** DOORBELL: din! don! 1976 ** check if there are any mail need to pack from firmware 1977 ******************************************************************* 1978 */ 1979 doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE; 1980 if(doorbell_status) 1981 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */ 1982 while( doorbell_status & ARCMSR_HBDMU_F0_DOORBELL_CAUSE ) { 1983 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK) { 1984 arcmsr_iop2drv_data_wrote_handle(acb); 1985 } 1986 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK) { 1987 arcmsr_iop2drv_data_read_handle(acb); 1988 } 1989 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) { 1990 arcmsr_hbd_message_isr(acb); /* messenger of "driver to iop commands" */ 1991 } 1992 doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE; 1993 if(doorbell_status) 1994 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */ 1995 } 1996 } 1997 /* 1998 ************************************************************************** 1999 ************************************************************************** 2000 */ 2001 static void arcmsr_hbe_doorbell_isr(struct AdapterControlBlock *acb) 2002 { 2003 u_int32_t doorbell_status, in_doorbell; 2004 2005 /* 2006 ******************************************************************* 2007 ** Maybe here we need to check wrqbuffer_lock is lock or not 2008 ** DOORBELL: din! don! 2009 ** check if there are any mail need to pack from firmware 2010 ******************************************************************* 2011 */ 2012 in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell); 2013 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /* clear doorbell interrupt */ 2014 doorbell_status = in_doorbell ^ acb->in_doorbell; 2015 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) { 2016 arcmsr_iop2drv_data_wrote_handle(acb); 2017 } 2018 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK) { 2019 arcmsr_iop2drv_data_read_handle(acb); 2020 } 2021 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) { 2022 arcmsr_hbe_message_isr(acb); /* messenger of "driver to iop commands" */ 2023 } 2024 acb->in_doorbell = in_doorbell; 2025 } 2026 /* 2027 ************************************************************************** 2028 ************************************************************************** 2029 */ 2030 static void arcmsr_hbf_doorbell_isr(struct AdapterControlBlock *acb) 2031 { 2032 u_int32_t doorbell_status, in_doorbell; 2033 2034 /* 2035 ******************************************************************* 2036 ** Maybe here we need to check wrqbuffer_lock is lock or not 2037 ** DOORBELL: din! don! 2038 ** check if there are any mail need to pack from firmware 2039 ******************************************************************* 2040 */ 2041 while(1) { 2042 in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell); 2043 if ((in_doorbell != 0) && (in_doorbell != 0xFFFFFFFF)) 2044 break; 2045 } 2046 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /* clear doorbell interrupt */ 2047 doorbell_status = in_doorbell ^ acb->in_doorbell; 2048 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) { 2049 arcmsr_iop2drv_data_wrote_handle(acb); 2050 } 2051 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK) { 2052 arcmsr_iop2drv_data_read_handle(acb); 2053 } 2054 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) { 2055 arcmsr_hbe_message_isr(acb); /* messenger of "driver to iop commands" */ 2056 } 2057 acb->in_doorbell = in_doorbell; 2058 } 2059 /* 2060 ************************************************************************** 2061 ************************************************************************** 2062 */ 2063 static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb) 2064 { 2065 u_int32_t flag_srb; 2066 u_int16_t error; 2067 2068 /* 2069 ***************************************************************************** 2070 ** areca cdb command done 2071 ***************************************************************************** 2072 */ 2073 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 2074 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2075 while((flag_srb = CHIP_REG_READ32(HBA_MessageUnit, 2076 0, outbound_queueport)) != 0xFFFFFFFF) { 2077 /* check if command done with no error*/ 2078 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0) ? TRUE : FALSE; 2079 arcmsr_drain_donequeue(acb, flag_srb, error); 2080 } /*drain reply FIFO*/ 2081 } 2082 /* 2083 ************************************************************************** 2084 ************************************************************************** 2085 */ 2086 static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb) 2087 { 2088 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 2089 u_int32_t flag_srb; 2090 int index; 2091 u_int16_t error; 2092 2093 /* 2094 ***************************************************************************** 2095 ** areca cdb command done 2096 ***************************************************************************** 2097 */ 2098 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 2099 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2100 index = phbbmu->doneq_index; 2101 while((flag_srb = phbbmu->done_qbuffer[index]) != 0) { 2102 phbbmu->done_qbuffer[index] = 0; 2103 index++; 2104 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 2105 phbbmu->doneq_index = index; 2106 /* check if command done with no error*/ 2107 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 2108 arcmsr_drain_donequeue(acb, flag_srb, error); 2109 } /*drain reply FIFO*/ 2110 } 2111 /* 2112 ************************************************************************** 2113 ************************************************************************** 2114 */ 2115 static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb) 2116 { 2117 u_int32_t flag_srb,throttling = 0; 2118 u_int16_t error; 2119 2120 /* 2121 ***************************************************************************** 2122 ** areca cdb command done 2123 ***************************************************************************** 2124 */ 2125 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2126 do { 2127 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 2128 if (flag_srb == 0xFFFFFFFF) 2129 break; 2130 /* check if command done with no error*/ 2131 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE; 2132 arcmsr_drain_donequeue(acb, flag_srb, error); 2133 throttling++; 2134 if(throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) { 2135 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING); 2136 throttling = 0; 2137 } 2138 } while(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR); 2139 } 2140 /* 2141 ********************************************************************** 2142 ** 2143 ********************************************************************** 2144 */ 2145 static uint16_t arcmsr_get_doneq_index(struct HBD_MessageUnit0 *phbdmu) 2146 { 2147 uint16_t doneq_index, index_stripped; 2148 2149 doneq_index = phbdmu->doneq_index; 2150 if (doneq_index & 0x4000) { 2151 index_stripped = doneq_index & 0xFF; 2152 index_stripped += 1; 2153 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 2154 phbdmu->doneq_index = index_stripped ? 2155 (index_stripped | 0x4000) : index_stripped; 2156 } else { 2157 index_stripped = doneq_index; 2158 index_stripped += 1; 2159 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 2160 phbdmu->doneq_index = index_stripped ? 2161 index_stripped : (index_stripped | 0x4000); 2162 } 2163 return (phbdmu->doneq_index); 2164 } 2165 /* 2166 ************************************************************************** 2167 ************************************************************************** 2168 */ 2169 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb) 2170 { 2171 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 2172 u_int32_t outbound_write_pointer; 2173 u_int32_t addressLow; 2174 uint16_t doneq_index; 2175 u_int16_t error; 2176 /* 2177 ***************************************************************************** 2178 ** areca cdb command done 2179 ***************************************************************************** 2180 */ 2181 if((CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause) & 2182 ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT) == 0) 2183 return; 2184 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 2185 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2186 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 2187 doneq_index = phbdmu->doneq_index; 2188 while ((doneq_index & 0xFF) != (outbound_write_pointer & 0xFF)) { 2189 doneq_index = arcmsr_get_doneq_index(phbdmu); 2190 addressLow = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow; 2191 error = (addressLow & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 2192 arcmsr_drain_donequeue(acb, addressLow, error); /*Check if command done with no error */ 2193 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index); 2194 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 2195 } 2196 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_interrupt_cause, ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR); 2197 CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause); /*Dummy ioread32 to force pci flush */ 2198 } 2199 /* 2200 ************************************************************************** 2201 ************************************************************************** 2202 */ 2203 static void arcmsr_hbe_postqueue_isr(struct AdapterControlBlock *acb) 2204 { 2205 u_int16_t error; 2206 uint32_t doneq_index; 2207 uint16_t cmdSMID; 2208 2209 /* 2210 ***************************************************************************** 2211 ** areca cdb command done 2212 ***************************************************************************** 2213 */ 2214 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2215 doneq_index = acb->doneq_index; 2216 while ((CHIP_REG_READ32(HBE_MessageUnit, 0, reply_post_producer_index) & 0xFFFF) != doneq_index) { 2217 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID; 2218 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 2219 arcmsr_drain_donequeue(acb, (u_int32_t)cmdSMID, error); 2220 doneq_index++; 2221 if (doneq_index >= acb->completionQ_entry) 2222 doneq_index = 0; 2223 } 2224 acb->doneq_index = doneq_index; 2225 CHIP_REG_WRITE32(HBE_MessageUnit, 0, reply_post_consumer_index, doneq_index); 2226 } 2227 2228 static void arcmsr_hbf_postqueue_isr(struct AdapterControlBlock *acb) 2229 { 2230 uint16_t error; 2231 uint32_t doneq_index; 2232 uint16_t cmdSMID; 2233 2234 /* 2235 ***************************************************************************** 2236 ** areca cdb command done 2237 ***************************************************************************** 2238 */ 2239 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2240 doneq_index = acb->doneq_index; 2241 while (1) { 2242 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID; 2243 if (cmdSMID == 0xffff) 2244 break; 2245 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 2246 arcmsr_drain_donequeue(acb, (u_int32_t)cmdSMID, error); 2247 acb->pCompletionQ[doneq_index].cmdSMID = 0xffff; 2248 doneq_index++; 2249 if (doneq_index >= acb->completionQ_entry) 2250 doneq_index = 0; 2251 } 2252 acb->doneq_index = doneq_index; 2253 CHIP_REG_WRITE32(HBF_MessageUnit, 0, reply_post_consumer_index, doneq_index); 2254 } 2255 2256 /* 2257 ********************************************************************** 2258 ********************************************************************** 2259 */ 2260 static void arcmsr_handle_hba_isr( struct AdapterControlBlock *acb) 2261 { 2262 u_int32_t outbound_intStatus; 2263 /* 2264 ********************************************* 2265 ** check outbound intstatus 2266 ********************************************* 2267 */ 2268 outbound_intStatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 2269 if(!outbound_intStatus) { 2270 /*it must be share irq*/ 2271 return; 2272 } 2273 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intStatus); /*clear interrupt*/ 2274 /* MU doorbell interrupts*/ 2275 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) { 2276 arcmsr_hba_doorbell_isr(acb); 2277 } 2278 /* MU post queue interrupts*/ 2279 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) { 2280 arcmsr_hba_postqueue_isr(acb); 2281 } 2282 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { 2283 arcmsr_hba_message_isr(acb); 2284 } 2285 } 2286 /* 2287 ********************************************************************** 2288 ********************************************************************** 2289 */ 2290 static void arcmsr_handle_hbb_isr( struct AdapterControlBlock *acb) 2291 { 2292 u_int32_t outbound_doorbell; 2293 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 2294 /* 2295 ********************************************* 2296 ** check outbound intstatus 2297 ********************************************* 2298 */ 2299 outbound_doorbell = READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & acb->outbound_int_enable; 2300 if(!outbound_doorbell) { 2301 /*it must be share irq*/ 2302 return; 2303 } 2304 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ~outbound_doorbell); /* clear doorbell interrupt */ 2305 READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell); 2306 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 2307 /* MU ioctl transfer doorbell interrupts*/ 2308 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) { 2309 arcmsr_iop2drv_data_wrote_handle(acb); 2310 } 2311 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) { 2312 arcmsr_iop2drv_data_read_handle(acb); 2313 } 2314 /* MU post queue interrupts*/ 2315 if(outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) { 2316 arcmsr_hbb_postqueue_isr(acb); 2317 } 2318 if(outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) { 2319 arcmsr_hbb_message_isr(acb); 2320 } 2321 } 2322 /* 2323 ********************************************************************** 2324 ********************************************************************** 2325 */ 2326 static void arcmsr_handle_hbc_isr( struct AdapterControlBlock *acb) 2327 { 2328 u_int32_t host_interrupt_status; 2329 /* 2330 ********************************************* 2331 ** check outbound intstatus 2332 ********************************************* 2333 */ 2334 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & 2335 (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | 2336 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR); 2337 if(!host_interrupt_status) { 2338 /*it must be share irq*/ 2339 return; 2340 } 2341 do { 2342 /* MU doorbell interrupts*/ 2343 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) { 2344 arcmsr_hbc_doorbell_isr(acb); 2345 } 2346 /* MU post queue interrupts*/ 2347 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) { 2348 arcmsr_hbc_postqueue_isr(acb); 2349 } 2350 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status); 2351 } while (host_interrupt_status & (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR)); 2352 } 2353 /* 2354 ********************************************************************** 2355 ********************************************************************** 2356 */ 2357 static void arcmsr_handle_hbd_isr( struct AdapterControlBlock *acb) 2358 { 2359 u_int32_t host_interrupt_status; 2360 u_int32_t intmask_org; 2361 /* 2362 ********************************************* 2363 ** check outbound intstatus 2364 ********************************************* 2365 */ 2366 host_interrupt_status = CHIP_REG_READ32(HBD_MessageUnit, 0, host_int_status) & acb->outbound_int_enable; 2367 if(!(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_INT)) { 2368 /*it must be share irq*/ 2369 return; 2370 } 2371 /* disable outbound interrupt */ 2372 intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable) ; /* disable outbound message0 int */ 2373 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE); 2374 /* MU doorbell interrupts*/ 2375 if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT) { 2376 arcmsr_hbd_doorbell_isr(acb); 2377 } 2378 /* MU post queue interrupts*/ 2379 if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT) { 2380 arcmsr_hbd_postqueue_isr(acb); 2381 } 2382 /* enable all outbound interrupt */ 2383 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | ARCMSR_HBDMU_ALL_INT_ENABLE); 2384 // CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); 2385 } 2386 /* 2387 ********************************************************************** 2388 ********************************************************************** 2389 */ 2390 static void arcmsr_handle_hbe_isr( struct AdapterControlBlock *acb) 2391 { 2392 u_int32_t host_interrupt_status; 2393 /* 2394 ********************************************* 2395 ** check outbound intstatus 2396 ********************************************* 2397 */ 2398 host_interrupt_status = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_status) & 2399 (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | 2400 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR); 2401 if(!host_interrupt_status) { 2402 /*it must be share irq*/ 2403 return; 2404 } 2405 do { 2406 /* MU doorbell interrupts*/ 2407 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) { 2408 arcmsr_hbe_doorbell_isr(acb); 2409 } 2410 /* MU post queue interrupts*/ 2411 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) { 2412 arcmsr_hbe_postqueue_isr(acb); 2413 } 2414 host_interrupt_status = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_status); 2415 } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR)); 2416 } 2417 2418 static void arcmsr_handle_hbf_isr( struct AdapterControlBlock *acb) 2419 { 2420 u_int32_t host_interrupt_status; 2421 /* 2422 ********************************************* 2423 ** check outbound intstatus 2424 ********************************************* 2425 */ 2426 host_interrupt_status = CHIP_REG_READ32(HBF_MessageUnit, 0, host_int_status) & 2427 (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | 2428 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR); 2429 if(!host_interrupt_status) { 2430 /*it must be share irq*/ 2431 return; 2432 } 2433 do { 2434 /* MU doorbell interrupts*/ 2435 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) { 2436 arcmsr_hbf_doorbell_isr(acb); 2437 } 2438 /* MU post queue interrupts*/ 2439 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) { 2440 arcmsr_hbf_postqueue_isr(acb); 2441 } 2442 host_interrupt_status = CHIP_REG_READ32(HBF_MessageUnit, 0, host_int_status); 2443 } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR)); 2444 } 2445 /* 2446 ****************************************************************************** 2447 ****************************************************************************** 2448 */ 2449 static void arcmsr_interrupt(struct AdapterControlBlock *acb) 2450 { 2451 switch (acb->adapter_type) { 2452 case ACB_ADAPTER_TYPE_A: 2453 arcmsr_handle_hba_isr(acb); 2454 break; 2455 case ACB_ADAPTER_TYPE_B: 2456 arcmsr_handle_hbb_isr(acb); 2457 break; 2458 case ACB_ADAPTER_TYPE_C: 2459 arcmsr_handle_hbc_isr(acb); 2460 break; 2461 case ACB_ADAPTER_TYPE_D: 2462 arcmsr_handle_hbd_isr(acb); 2463 break; 2464 case ACB_ADAPTER_TYPE_E: 2465 arcmsr_handle_hbe_isr(acb); 2466 break; 2467 case ACB_ADAPTER_TYPE_F: 2468 arcmsr_handle_hbf_isr(acb); 2469 break; 2470 default: 2471 printf("arcmsr%d: interrupt service," 2472 " unknown adapter type =%d\n", acb->pci_unit, acb->adapter_type); 2473 break; 2474 } 2475 } 2476 /* 2477 ********************************************************************** 2478 ********************************************************************** 2479 */ 2480 static void arcmsr_intr_handler(void *arg) 2481 { 2482 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg; 2483 2484 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 2485 arcmsr_interrupt(acb); 2486 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 2487 } 2488 /* 2489 ****************************************************************************** 2490 ****************************************************************************** 2491 */ 2492 static void arcmsr_polling_devmap(void *arg) 2493 { 2494 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg; 2495 switch (acb->adapter_type) { 2496 case ACB_ADAPTER_TYPE_A: 2497 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2498 break; 2499 2500 case ACB_ADAPTER_TYPE_B: { 2501 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 2502 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG); 2503 } 2504 break; 2505 2506 case ACB_ADAPTER_TYPE_C: 2507 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2508 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 2509 break; 2510 2511 case ACB_ADAPTER_TYPE_D: 2512 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2513 break; 2514 2515 case ACB_ADAPTER_TYPE_E: 2516 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2517 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 2518 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 2519 break; 2520 2521 case ACB_ADAPTER_TYPE_F: { 2522 u_int32_t outMsg1 = CHIP_REG_READ32(HBF_MessageUnit, 0, outbound_msgaddr1); 2523 if (!(outMsg1 & ARCMSR_HBFMU_MESSAGE_FIRMWARE_OK) || 2524 (outMsg1 & ARCMSR_HBFMU_MESSAGE_NO_VOLUME_CHANGE)) 2525 goto nxt6s; 2526 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2527 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 2528 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 2529 break; 2530 } 2531 } 2532 nxt6s: 2533 if((acb->acb_flags & ACB_F_SCSISTOPADAPTER) == 0) 2534 { 2535 callout_reset(&acb->devmap_callout, 5 * hz, arcmsr_polling_devmap, acb); /* polling per 5 seconds */ 2536 } 2537 } 2538 2539 /* 2540 ******************************************************************************* 2541 ** 2542 ******************************************************************************* 2543 */ 2544 static void arcmsr_iop_parking(struct AdapterControlBlock *acb) 2545 { 2546 u_int32_t intmask_org; 2547 2548 if(acb != NULL) { 2549 /* stop adapter background rebuild */ 2550 if(acb->acb_flags & ACB_F_MSG_START_BGRB) { 2551 intmask_org = arcmsr_disable_allintr(acb); 2552 arcmsr_stop_adapter_bgrb(acb); 2553 arcmsr_flush_adapter_cache(acb); 2554 arcmsr_enable_allintr(acb, intmask_org); 2555 } 2556 } 2557 } 2558 /* 2559 *********************************************************************** 2560 ** 2561 ************************************************************************ 2562 */ 2563 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg) 2564 { 2565 struct CMD_MESSAGE_FIELD *pcmdmessagefld; 2566 u_int32_t retvalue = EINVAL; 2567 2568 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) arg; 2569 if(memcmp(pcmdmessagefld->cmdmessage.Signature, "ARCMSR", 6)!=0) { 2570 return retvalue; 2571 } 2572 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2573 switch(ioctl_cmd) { 2574 case ARCMSR_MESSAGE_READ_RQBUFFER: { 2575 u_int8_t *pQbuffer; 2576 u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer; 2577 u_int32_t allxfer_len=0; 2578 2579 while((acb->rqbuf_firstindex != acb->rqbuf_lastindex) 2580 && (allxfer_len < 1031)) { 2581 /*copy READ QBUFFER to srb*/ 2582 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex]; 2583 *ptmpQbuffer = *pQbuffer; 2584 acb->rqbuf_firstindex++; 2585 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 2586 /*if last index number set it to 0 */ 2587 ptmpQbuffer++; 2588 allxfer_len++; 2589 } 2590 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2591 struct QBUFFER *prbuffer; 2592 2593 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2594 prbuffer = arcmsr_get_iop_rqbuffer(acb); 2595 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 2596 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 2597 } 2598 pcmdmessagefld->cmdmessage.Length = allxfer_len; 2599 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2600 retvalue = ARCMSR_MESSAGE_SUCCESS; 2601 } 2602 break; 2603 case ARCMSR_MESSAGE_WRITE_WQBUFFER: { 2604 u_int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex; 2605 u_int8_t *pQbuffer; 2606 u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer; 2607 2608 user_len = pcmdmessagefld->cmdmessage.Length; 2609 /*check if data xfer length of this request will overflow my array qbuffer */ 2610 wqbuf_lastindex = acb->wqbuf_lastindex; 2611 wqbuf_firstindex = acb->wqbuf_firstindex; 2612 if(wqbuf_lastindex != wqbuf_firstindex) { 2613 arcmsr_Write_data_2iop_wqbuffer(acb); 2614 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2615 } else { 2616 my_empty_len = (wqbuf_firstindex - wqbuf_lastindex - 1) & 2617 (ARCMSR_MAX_QBUFFER - 1); 2618 if(my_empty_len >= user_len) { 2619 while(user_len > 0) { 2620 /*copy srb data to wqbuffer*/ 2621 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex]; 2622 *pQbuffer = *ptmpuserbuffer; 2623 acb->wqbuf_lastindex++; 2624 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 2625 /*if last index number set it to 0 */ 2626 ptmpuserbuffer++; 2627 user_len--; 2628 } 2629 /*post fist Qbuffer*/ 2630 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) { 2631 acb->acb_flags &= ~ACB_F_MESSAGE_WQBUFFER_CLEARED; 2632 arcmsr_Write_data_2iop_wqbuffer(acb); 2633 } 2634 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2635 } else { 2636 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2637 } 2638 } 2639 retvalue = ARCMSR_MESSAGE_SUCCESS; 2640 } 2641 break; 2642 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: { 2643 u_int8_t *pQbuffer = acb->rqbuffer; 2644 2645 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2646 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2647 arcmsr_iop_message_read(acb); 2648 /*signature, let IOP know data has been readed */ 2649 } 2650 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 2651 acb->rqbuf_firstindex = 0; 2652 acb->rqbuf_lastindex = 0; 2653 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2654 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2655 retvalue = ARCMSR_MESSAGE_SUCCESS; 2656 } 2657 break; 2658 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: 2659 { 2660 u_int8_t *pQbuffer = acb->wqbuffer; 2661 2662 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2663 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2664 arcmsr_iop_message_read(acb); 2665 /*signature, let IOP know data has been readed */ 2666 } 2667 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ); 2668 acb->wqbuf_firstindex = 0; 2669 acb->wqbuf_lastindex = 0; 2670 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2671 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2672 retvalue = ARCMSR_MESSAGE_SUCCESS; 2673 } 2674 break; 2675 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: { 2676 u_int8_t *pQbuffer; 2677 2678 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2679 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2680 arcmsr_iop_message_read(acb); 2681 /*signature, let IOP know data has been readed */ 2682 } 2683 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED 2684 |ACB_F_MESSAGE_RQBUFFER_CLEARED 2685 |ACB_F_MESSAGE_WQBUFFER_READ); 2686 acb->rqbuf_firstindex = 0; 2687 acb->rqbuf_lastindex = 0; 2688 acb->wqbuf_firstindex = 0; 2689 acb->wqbuf_lastindex = 0; 2690 pQbuffer = acb->rqbuffer; 2691 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 2692 pQbuffer = acb->wqbuffer; 2693 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 2694 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2695 retvalue = ARCMSR_MESSAGE_SUCCESS; 2696 } 2697 break; 2698 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: { 2699 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F; 2700 retvalue = ARCMSR_MESSAGE_SUCCESS; 2701 } 2702 break; 2703 case ARCMSR_MESSAGE_SAY_HELLO: { 2704 u_int8_t *hello_string = "Hello! I am ARCMSR"; 2705 u_int8_t *puserbuffer = (u_int8_t *)pcmdmessagefld->messagedatabuffer; 2706 2707 if(memcpy(puserbuffer, hello_string, (int16_t)strlen(hello_string))) { 2708 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2709 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2710 return ENOIOCTL; 2711 } 2712 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2713 retvalue = ARCMSR_MESSAGE_SUCCESS; 2714 } 2715 break; 2716 case ARCMSR_MESSAGE_SAY_GOODBYE: { 2717 arcmsr_iop_parking(acb); 2718 retvalue = ARCMSR_MESSAGE_SUCCESS; 2719 } 2720 break; 2721 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: { 2722 arcmsr_flush_adapter_cache(acb); 2723 retvalue = ARCMSR_MESSAGE_SUCCESS; 2724 } 2725 break; 2726 } 2727 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2728 return (retvalue); 2729 } 2730 /* 2731 ************************************************************************** 2732 ************************************************************************** 2733 */ 2734 static void arcmsr_free_srb(struct CommandControlBlock *srb) 2735 { 2736 struct AdapterControlBlock *acb; 2737 2738 acb = srb->acb; 2739 ARCMSR_LOCK_ACQUIRE(&acb->srb_lock); 2740 srb->srb_state = ARCMSR_SRB_DONE; 2741 srb->srb_flags = 0; 2742 acb->srbworkingQ[acb->workingsrb_doneindex] = srb; 2743 acb->workingsrb_doneindex++; 2744 acb->workingsrb_doneindex %= ARCMSR_MAX_FREESRB_NUM; 2745 ARCMSR_LOCK_RELEASE(&acb->srb_lock); 2746 } 2747 /* 2748 ************************************************************************** 2749 ************************************************************************** 2750 */ 2751 static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb) 2752 { 2753 struct CommandControlBlock *srb = NULL; 2754 u_int32_t workingsrb_startindex, workingsrb_doneindex; 2755 2756 ARCMSR_LOCK_ACQUIRE(&acb->srb_lock); 2757 workingsrb_doneindex = acb->workingsrb_doneindex; 2758 workingsrb_startindex = acb->workingsrb_startindex; 2759 srb = acb->srbworkingQ[workingsrb_startindex]; 2760 workingsrb_startindex++; 2761 workingsrb_startindex %= ARCMSR_MAX_FREESRB_NUM; 2762 if(workingsrb_doneindex != workingsrb_startindex) { 2763 acb->workingsrb_startindex = workingsrb_startindex; 2764 } else { 2765 srb = NULL; 2766 } 2767 ARCMSR_LOCK_RELEASE(&acb->srb_lock); 2768 return(srb); 2769 } 2770 /* 2771 ************************************************************************** 2772 ************************************************************************** 2773 */ 2774 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb) 2775 { 2776 struct CMD_MESSAGE_FIELD *pcmdmessagefld; 2777 int retvalue = 0, transfer_len = 0; 2778 char *buffer; 2779 uint8_t *ptr = scsiio_cdb_ptr(&pccb->csio); 2780 u_int32_t controlcode = (u_int32_t ) ptr[5] << 24 | 2781 (u_int32_t ) ptr[6] << 16 | 2782 (u_int32_t ) ptr[7] << 8 | 2783 (u_int32_t ) ptr[8]; 2784 /* 4 bytes: Areca io control code */ 2785 if ((pccb->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_VADDR) { 2786 buffer = pccb->csio.data_ptr; 2787 transfer_len = pccb->csio.dxfer_len; 2788 } else { 2789 retvalue = ARCMSR_MESSAGE_FAIL; 2790 goto message_out; 2791 } 2792 if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) { 2793 retvalue = ARCMSR_MESSAGE_FAIL; 2794 goto message_out; 2795 } 2796 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) buffer; 2797 switch(controlcode) { 2798 case ARCMSR_MESSAGE_READ_RQBUFFER: { 2799 u_int8_t *pQbuffer; 2800 u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer; 2801 int32_t allxfer_len = 0; 2802 2803 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2804 while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex) 2805 && (allxfer_len < 1031)) { 2806 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex]; 2807 *ptmpQbuffer = *pQbuffer; 2808 acb->rqbuf_firstindex++; 2809 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 2810 ptmpQbuffer++; 2811 allxfer_len++; 2812 } 2813 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2814 struct QBUFFER *prbuffer; 2815 2816 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2817 prbuffer = arcmsr_get_iop_rqbuffer(acb); 2818 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 2819 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 2820 } 2821 pcmdmessagefld->cmdmessage.Length = allxfer_len; 2822 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2823 retvalue = ARCMSR_MESSAGE_SUCCESS; 2824 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2825 } 2826 break; 2827 case ARCMSR_MESSAGE_WRITE_WQBUFFER: { 2828 int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex; 2829 u_int8_t *pQbuffer; 2830 u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer; 2831 2832 user_len = pcmdmessagefld->cmdmessage.Length; 2833 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2834 wqbuf_lastindex = acb->wqbuf_lastindex; 2835 wqbuf_firstindex = acb->wqbuf_firstindex; 2836 if (wqbuf_lastindex != wqbuf_firstindex) { 2837 arcmsr_Write_data_2iop_wqbuffer(acb); 2838 /* has error report sensedata */ 2839 if(pccb->csio.sense_len) { 2840 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); 2841 /* Valid,ErrorCode */ 2842 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05; 2843 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */ 2844 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A; 2845 /* AdditionalSenseLength */ 2846 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20; 2847 /* AdditionalSenseCode */ 2848 } 2849 retvalue = ARCMSR_MESSAGE_FAIL; 2850 } else { 2851 my_empty_len = (wqbuf_firstindex-wqbuf_lastindex - 1) 2852 &(ARCMSR_MAX_QBUFFER - 1); 2853 if (my_empty_len >= user_len) { 2854 while (user_len > 0) { 2855 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex]; 2856 *pQbuffer = *ptmpuserbuffer; 2857 acb->wqbuf_lastindex++; 2858 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 2859 ptmpuserbuffer++; 2860 user_len--; 2861 } 2862 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) { 2863 acb->acb_flags &= 2864 ~ACB_F_MESSAGE_WQBUFFER_CLEARED; 2865 arcmsr_Write_data_2iop_wqbuffer(acb); 2866 } 2867 } else { 2868 /* has error report sensedata */ 2869 if(pccb->csio.sense_len) { 2870 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); 2871 /* Valid,ErrorCode */ 2872 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05; 2873 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */ 2874 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A; 2875 /* AdditionalSenseLength */ 2876 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20; 2877 /* AdditionalSenseCode */ 2878 } 2879 retvalue = ARCMSR_MESSAGE_FAIL; 2880 } 2881 } 2882 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2883 } 2884 break; 2885 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: { 2886 u_int8_t *pQbuffer = acb->rqbuffer; 2887 2888 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2889 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2890 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2891 arcmsr_iop_message_read(acb); 2892 } 2893 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 2894 acb->rqbuf_firstindex = 0; 2895 acb->rqbuf_lastindex = 0; 2896 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2897 pcmdmessagefld->cmdmessage.ReturnCode = 2898 ARCMSR_MESSAGE_RETURNCODE_OK; 2899 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2900 } 2901 break; 2902 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: { 2903 u_int8_t *pQbuffer = acb->wqbuffer; 2904 2905 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2906 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2907 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2908 arcmsr_iop_message_read(acb); 2909 } 2910 acb->acb_flags |= 2911 (ACB_F_MESSAGE_WQBUFFER_CLEARED | 2912 ACB_F_MESSAGE_WQBUFFER_READ); 2913 acb->wqbuf_firstindex = 0; 2914 acb->wqbuf_lastindex = 0; 2915 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2916 pcmdmessagefld->cmdmessage.ReturnCode = 2917 ARCMSR_MESSAGE_RETURNCODE_OK; 2918 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2919 } 2920 break; 2921 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: { 2922 u_int8_t *pQbuffer; 2923 2924 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2925 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2926 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2927 arcmsr_iop_message_read(acb); 2928 } 2929 acb->acb_flags |= 2930 (ACB_F_MESSAGE_WQBUFFER_CLEARED 2931 | ACB_F_MESSAGE_RQBUFFER_CLEARED 2932 | ACB_F_MESSAGE_WQBUFFER_READ); 2933 acb->rqbuf_firstindex = 0; 2934 acb->rqbuf_lastindex = 0; 2935 acb->wqbuf_firstindex = 0; 2936 acb->wqbuf_lastindex = 0; 2937 pQbuffer = acb->rqbuffer; 2938 memset(pQbuffer, 0, sizeof (struct QBUFFER)); 2939 pQbuffer = acb->wqbuffer; 2940 memset(pQbuffer, 0, sizeof (struct QBUFFER)); 2941 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2942 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2943 } 2944 break; 2945 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: { 2946 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F; 2947 } 2948 break; 2949 case ARCMSR_MESSAGE_SAY_HELLO: { 2950 int8_t *hello_string = "Hello! I am ARCMSR"; 2951 2952 memcpy(pcmdmessagefld->messagedatabuffer, hello_string 2953 , (int16_t)strlen(hello_string)); 2954 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2955 } 2956 break; 2957 case ARCMSR_MESSAGE_SAY_GOODBYE: 2958 arcmsr_iop_parking(acb); 2959 break; 2960 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: 2961 arcmsr_flush_adapter_cache(acb); 2962 break; 2963 default: 2964 retvalue = ARCMSR_MESSAGE_FAIL; 2965 } 2966 message_out: 2967 return (retvalue); 2968 } 2969 /* 2970 ********************************************************************* 2971 ********************************************************************* 2972 */ 2973 static void arcmsr_execute_srb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 2974 { 2975 struct CommandControlBlock *srb = (struct CommandControlBlock *)arg; 2976 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)srb->acb; 2977 union ccb *pccb; 2978 int target, lun; 2979 2980 pccb = srb->pccb; 2981 target = pccb->ccb_h.target_id; 2982 lun = pccb->ccb_h.target_lun; 2983 acb->pktRequestCount++; 2984 if(error != 0) { 2985 if(error != EFBIG) { 2986 printf("arcmsr%d: unexpected error %x" 2987 " returned from 'bus_dmamap_load' \n" 2988 , acb->pci_unit, error); 2989 } 2990 if((pccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_INPROG) { 2991 pccb->ccb_h.status |= CAM_REQ_TOO_BIG; 2992 } 2993 arcmsr_srb_complete(srb, 0); 2994 return; 2995 } 2996 if(nseg > ARCMSR_MAX_SG_ENTRIES) { 2997 pccb->ccb_h.status |= CAM_REQ_TOO_BIG; 2998 arcmsr_srb_complete(srb, 0); 2999 return; 3000 } 3001 if(acb->acb_flags & ACB_F_BUS_RESET) { 3002 printf("arcmsr%d: bus reset and return busy \n", acb->pci_unit); 3003 pccb->ccb_h.status |= CAM_SCSI_BUS_RESET; 3004 arcmsr_srb_complete(srb, 0); 3005 return; 3006 } 3007 if(acb->devstate[target][lun] == ARECA_RAID_GONE) { 3008 u_int8_t block_cmd, cmd; 3009 3010 cmd = scsiio_cdb_ptr(&pccb->csio)[0]; 3011 block_cmd = cmd & 0x0f; 3012 if(block_cmd == 0x08 || block_cmd == 0x0a) { 3013 printf("arcmsr%d:block 'read/write' command " 3014 "with gone raid volume Cmd=0x%2x, TargetId=%d, Lun=%d \n" 3015 , acb->pci_unit, cmd, target, lun); 3016 pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 3017 arcmsr_srb_complete(srb, 0); 3018 return; 3019 } 3020 } 3021 if((pccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_INPROG) { 3022 if(nseg != 0) { 3023 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap); 3024 } 3025 arcmsr_srb_complete(srb, 0); 3026 return; 3027 } 3028 if(acb->srboutstandingcount >= acb->maxOutstanding) { 3029 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) == 0) 3030 { 3031 xpt_freeze_simq(acb->psim, 1); 3032 acb->acb_flags |= ACB_F_CAM_DEV_QFRZN; 3033 } 3034 pccb->ccb_h.status &= ~CAM_SIM_QUEUED; 3035 pccb->ccb_h.status |= CAM_REQUEUE_REQ; 3036 arcmsr_srb_complete(srb, 0); 3037 return; 3038 } 3039 pccb->ccb_h.status |= CAM_SIM_QUEUED; 3040 arcmsr_build_srb(srb, dm_segs, nseg); 3041 arcmsr_post_srb(acb, srb); 3042 if (pccb->ccb_h.timeout != CAM_TIME_INFINITY) 3043 { 3044 arcmsr_callout_init(&srb->ccb_callout); 3045 callout_reset_sbt(&srb->ccb_callout, SBT_1MS * 3046 (pccb->ccb_h.timeout + (ARCMSR_TIMEOUT_DELAY * 1000)), 0, 3047 arcmsr_srb_timeout, srb, 0); 3048 srb->srb_flags |= SRB_FLAG_TIMER_START; 3049 } 3050 } 3051 /* 3052 ***************************************************************************************** 3053 ***************************************************************************************** 3054 */ 3055 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb) 3056 { 3057 struct CommandControlBlock *srb; 3058 struct AdapterControlBlock *acb = (struct AdapterControlBlock *) abortccb->ccb_h.arcmsr_ccbacb_ptr; 3059 u_int32_t intmask_org; 3060 int i = 0; 3061 3062 acb->num_aborts++; 3063 /* 3064 *************************************************************************** 3065 ** It is the upper layer do abort command this lock just prior to calling us. 3066 ** First determine if we currently own this command. 3067 ** Start by searching the device queue. If not found 3068 ** at all, and the system wanted us to just abort the 3069 ** command return success. 3070 *************************************************************************** 3071 */ 3072 if(acb->srboutstandingcount != 0) { 3073 /* disable all outbound interrupt */ 3074 intmask_org = arcmsr_disable_allintr(acb); 3075 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 3076 srb = acb->psrb_pool[i]; 3077 if(srb->srb_state == ARCMSR_SRB_START) { 3078 if(srb->pccb == abortccb) { 3079 srb->srb_state = ARCMSR_SRB_ABORTED; 3080 printf("arcmsr%d:scsi id=%d lun=%jx abort srb '%p'" 3081 "outstanding command \n" 3082 , acb->pci_unit, abortccb->ccb_h.target_id 3083 , (uintmax_t)abortccb->ccb_h.target_lun, srb); 3084 arcmsr_polling_srbdone(acb, srb); 3085 /* enable outbound Post Queue, outbound doorbell Interrupt */ 3086 arcmsr_enable_allintr(acb, intmask_org); 3087 return (TRUE); 3088 } 3089 } 3090 } 3091 /* enable outbound Post Queue, outbound doorbell Interrupt */ 3092 arcmsr_enable_allintr(acb, intmask_org); 3093 } 3094 return(FALSE); 3095 } 3096 /* 3097 **************************************************************************** 3098 **************************************************************************** 3099 */ 3100 static void arcmsr_bus_reset(struct AdapterControlBlock *acb) 3101 { 3102 int retry = 0; 3103 3104 acb->num_resets++; 3105 acb->acb_flags |= ACB_F_BUS_RESET; 3106 while(acb->srboutstandingcount != 0 && retry < 400) { 3107 arcmsr_interrupt(acb); 3108 UDELAY(25000); 3109 retry++; 3110 } 3111 arcmsr_iop_reset(acb); 3112 acb->acb_flags &= ~ACB_F_BUS_RESET; 3113 } 3114 /* 3115 ************************************************************************** 3116 ************************************************************************** 3117 */ 3118 static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb, 3119 union ccb *pccb) 3120 { 3121 if (pccb->ccb_h.target_lun) { 3122 pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 3123 xpt_done(pccb); 3124 return; 3125 } 3126 pccb->ccb_h.status |= CAM_REQ_CMP; 3127 switch (scsiio_cdb_ptr(&pccb->csio)[0]) { 3128 case INQUIRY: { 3129 unsigned char inqdata[36]; 3130 char *buffer = pccb->csio.data_ptr; 3131 3132 inqdata[0] = T_PROCESSOR; /* Periph Qualifier & Periph Dev Type */ 3133 inqdata[1] = 0; /* rem media bit & Dev Type Modifier */ 3134 inqdata[2] = 0; /* ISO, ECMA, & ANSI versions */ 3135 inqdata[3] = 0; 3136 inqdata[4] = 31; /* length of additional data */ 3137 inqdata[5] = 0; 3138 inqdata[6] = 0; 3139 inqdata[7] = 0; 3140 strncpy(&inqdata[8], "Areca ", 8); /* Vendor Identification */ 3141 strncpy(&inqdata[16], "RAID controller ", 16); /* Product Identification */ 3142 strncpy(&inqdata[32], "R001", 4); /* Product Revision */ 3143 memcpy(buffer, inqdata, sizeof(inqdata)); 3144 xpt_done(pccb); 3145 } 3146 break; 3147 case WRITE_BUFFER: 3148 case READ_BUFFER: { 3149 if (arcmsr_iop_message_xfer(acb, pccb)) { 3150 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 3151 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 3152 } 3153 xpt_done(pccb); 3154 } 3155 break; 3156 default: 3157 xpt_done(pccb); 3158 } 3159 } 3160 /* 3161 ********************************************************************* 3162 ********************************************************************* 3163 */ 3164 static void arcmsr_action(struct cam_sim *psim, union ccb *pccb) 3165 { 3166 struct AdapterControlBlock *acb; 3167 3168 acb = (struct AdapterControlBlock *) cam_sim_softc(psim); 3169 if(acb == NULL) { 3170 pccb->ccb_h.status |= CAM_REQ_INVALID; 3171 xpt_done(pccb); 3172 return; 3173 } 3174 switch (pccb->ccb_h.func_code) { 3175 case XPT_SCSI_IO: { 3176 struct CommandControlBlock *srb; 3177 int target = pccb->ccb_h.target_id; 3178 int error; 3179 3180 if (pccb->ccb_h.flags & CAM_CDB_PHYS) { 3181 pccb->ccb_h.status = CAM_REQ_INVALID; 3182 xpt_done(pccb); 3183 return; 3184 } 3185 3186 if(target == 16) { 3187 /* virtual device for iop message transfer */ 3188 arcmsr_handle_virtual_command(acb, pccb); 3189 return; 3190 } 3191 if((srb = arcmsr_get_freesrb(acb)) == NULL) { 3192 pccb->ccb_h.status |= CAM_RESRC_UNAVAIL; 3193 xpt_done(pccb); 3194 return; 3195 } 3196 pccb->ccb_h.arcmsr_ccbsrb_ptr = srb; 3197 pccb->ccb_h.arcmsr_ccbacb_ptr = acb; 3198 srb->pccb = pccb; 3199 error = bus_dmamap_load_ccb(acb->dm_segs_dmat 3200 , srb->dm_segs_dmamap 3201 , pccb 3202 , arcmsr_execute_srb, srb, /*flags*/0); 3203 if(error == EINPROGRESS) { 3204 xpt_freeze_simq(acb->psim, 1); 3205 pccb->ccb_h.status |= CAM_RELEASE_SIMQ; 3206 } 3207 break; 3208 } 3209 case XPT_PATH_INQ: { 3210 struct ccb_pathinq *cpi = &pccb->cpi; 3211 3212 cpi->version_num = 1; 3213 cpi->hba_inquiry = PI_SDTR_ABLE | PI_TAG_ABLE; 3214 cpi->target_sprt = 0; 3215 cpi->hba_misc = 0; 3216 cpi->hba_eng_cnt = 0; 3217 cpi->max_target = ARCMSR_MAX_TARGETID; /* 0-16 */ 3218 cpi->max_lun = ARCMSR_MAX_TARGETLUN; /* 0-7 */ 3219 cpi->initiator_id = ARCMSR_SCSI_INITIATOR_ID; /* 255 */ 3220 cpi->bus_id = cam_sim_bus(psim); 3221 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 3222 strlcpy(cpi->hba_vid, "ARCMSR", HBA_IDLEN); 3223 strlcpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN); 3224 cpi->unit_number = cam_sim_unit(psim); 3225 if(acb->adapter_bus_speed == ACB_BUS_SPEED_12G) 3226 cpi->base_transfer_speed = 1200000; 3227 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G) 3228 cpi->base_transfer_speed = 600000; 3229 else 3230 cpi->base_transfer_speed = 300000; 3231 if((acb->vendor_device_id == PCIDevVenIDARC1880) || 3232 (acb->vendor_device_id == PCIDevVenIDARC1884) || 3233 (acb->vendor_device_id == PCIDevVenIDARC1680) || 3234 (acb->vendor_device_id == PCIDevVenIDARC1214)) 3235 { 3236 cpi->transport = XPORT_SAS; 3237 cpi->transport_version = 0; 3238 cpi->protocol_version = SCSI_REV_SPC2; 3239 } 3240 else 3241 { 3242 cpi->transport = XPORT_SPI; 3243 cpi->transport_version = 2; 3244 cpi->protocol_version = SCSI_REV_2; 3245 } 3246 cpi->protocol = PROTO_SCSI; 3247 cpi->ccb_h.status |= CAM_REQ_CMP; 3248 xpt_done(pccb); 3249 break; 3250 } 3251 case XPT_ABORT: { 3252 union ccb *pabort_ccb; 3253 3254 pabort_ccb = pccb->cab.abort_ccb; 3255 switch (pabort_ccb->ccb_h.func_code) { 3256 case XPT_ACCEPT_TARGET_IO: 3257 case XPT_CONT_TARGET_IO: 3258 if(arcmsr_seek_cmd2abort(pabort_ccb)==TRUE) { 3259 pabort_ccb->ccb_h.status |= CAM_REQ_ABORTED; 3260 xpt_done(pabort_ccb); 3261 pccb->ccb_h.status |= CAM_REQ_CMP; 3262 } else { 3263 xpt_print_path(pabort_ccb->ccb_h.path); 3264 printf("Not found\n"); 3265 pccb->ccb_h.status |= CAM_PATH_INVALID; 3266 } 3267 break; 3268 case XPT_SCSI_IO: 3269 pccb->ccb_h.status |= CAM_UA_ABORT; 3270 break; 3271 default: 3272 pccb->ccb_h.status |= CAM_REQ_INVALID; 3273 break; 3274 } 3275 xpt_done(pccb); 3276 break; 3277 } 3278 case XPT_RESET_BUS: 3279 case XPT_RESET_DEV: { 3280 u_int32_t i; 3281 3282 arcmsr_bus_reset(acb); 3283 for (i=0; i < 500; i++) { 3284 DELAY(1000); 3285 } 3286 pccb->ccb_h.status |= CAM_REQ_CMP; 3287 xpt_done(pccb); 3288 break; 3289 } 3290 case XPT_TERM_IO: { 3291 pccb->ccb_h.status |= CAM_REQ_INVALID; 3292 xpt_done(pccb); 3293 break; 3294 } 3295 case XPT_GET_TRAN_SETTINGS: { 3296 struct ccb_trans_settings *cts; 3297 3298 if(pccb->ccb_h.target_id == 16) { 3299 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 3300 xpt_done(pccb); 3301 break; 3302 } 3303 cts = &pccb->cts; 3304 { 3305 struct ccb_trans_settings_scsi *scsi; 3306 struct ccb_trans_settings_spi *spi; 3307 struct ccb_trans_settings_sas *sas; 3308 3309 scsi = &cts->proto_specific.scsi; 3310 scsi->flags = CTS_SCSI_FLAGS_TAG_ENB; 3311 scsi->valid = CTS_SCSI_VALID_TQ; 3312 cts->protocol = PROTO_SCSI; 3313 3314 if((acb->vendor_device_id == PCIDevVenIDARC1880) || 3315 (acb->vendor_device_id == PCIDevVenIDARC1884) || 3316 (acb->vendor_device_id == PCIDevVenIDARC1680) || 3317 (acb->vendor_device_id == PCIDevVenIDARC1214)) 3318 { 3319 cts->protocol_version = SCSI_REV_SPC2; 3320 cts->transport_version = 0; 3321 cts->transport = XPORT_SAS; 3322 sas = &cts->xport_specific.sas; 3323 sas->valid = CTS_SAS_VALID_SPEED; 3324 if (acb->adapter_bus_speed == ACB_BUS_SPEED_12G) 3325 sas->bitrate = 1200000; 3326 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G) 3327 sas->bitrate = 600000; 3328 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_3G) 3329 sas->bitrate = 300000; 3330 } 3331 else 3332 { 3333 cts->protocol_version = SCSI_REV_2; 3334 cts->transport_version = 2; 3335 cts->transport = XPORT_SPI; 3336 spi = &cts->xport_specific.spi; 3337 spi->flags = CTS_SPI_FLAGS_DISC_ENB; 3338 if (acb->adapter_bus_speed == ACB_BUS_SPEED_6G) 3339 spi->sync_period = 1; 3340 else 3341 spi->sync_period = 2; 3342 spi->sync_offset = 32; 3343 spi->bus_width = MSG_EXT_WDTR_BUS_16_BIT; 3344 spi->valid = CTS_SPI_VALID_DISC 3345 | CTS_SPI_VALID_SYNC_RATE 3346 | CTS_SPI_VALID_SYNC_OFFSET 3347 | CTS_SPI_VALID_BUS_WIDTH; 3348 } 3349 } 3350 pccb->ccb_h.status |= CAM_REQ_CMP; 3351 xpt_done(pccb); 3352 break; 3353 } 3354 case XPT_SET_TRAN_SETTINGS: { 3355 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 3356 xpt_done(pccb); 3357 break; 3358 } 3359 case XPT_CALC_GEOMETRY: 3360 if(pccb->ccb_h.target_id == 16) { 3361 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 3362 xpt_done(pccb); 3363 break; 3364 } 3365 cam_calc_geometry(&pccb->ccg, 1); 3366 xpt_done(pccb); 3367 break; 3368 default: 3369 pccb->ccb_h.status |= CAM_REQ_INVALID; 3370 xpt_done(pccb); 3371 break; 3372 } 3373 } 3374 /* 3375 ********************************************************************** 3376 ********************************************************************** 3377 */ 3378 static void arcmsr_start_hba_bgrb(struct AdapterControlBlock *acb) 3379 { 3380 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3381 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3382 if(!arcmsr_hba_wait_msgint_ready(acb)) { 3383 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3384 } 3385 } 3386 /* 3387 ********************************************************************** 3388 ********************************************************************** 3389 */ 3390 static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb) 3391 { 3392 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3393 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3394 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_START_BGRB); 3395 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3396 printf( "arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3397 } 3398 } 3399 /* 3400 ********************************************************************** 3401 ********************************************************************** 3402 */ 3403 static void arcmsr_start_hbc_bgrb(struct AdapterControlBlock *acb) 3404 { 3405 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3406 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3407 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3408 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 3409 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3410 } 3411 } 3412 /* 3413 ********************************************************************** 3414 ********************************************************************** 3415 */ 3416 static void arcmsr_start_hbd_bgrb(struct AdapterControlBlock *acb) 3417 { 3418 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3419 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3420 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 3421 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3422 } 3423 } 3424 /* 3425 ********************************************************************** 3426 ********************************************************************** 3427 */ 3428 static void arcmsr_start_hbe_bgrb(struct AdapterControlBlock *acb) 3429 { 3430 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3431 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3432 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 3433 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 3434 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 3435 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3436 } 3437 } 3438 /* 3439 ********************************************************************** 3440 ********************************************************************** 3441 */ 3442 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb) 3443 { 3444 switch (acb->adapter_type) { 3445 case ACB_ADAPTER_TYPE_A: 3446 arcmsr_start_hba_bgrb(acb); 3447 break; 3448 case ACB_ADAPTER_TYPE_B: 3449 arcmsr_start_hbb_bgrb(acb); 3450 break; 3451 case ACB_ADAPTER_TYPE_C: 3452 arcmsr_start_hbc_bgrb(acb); 3453 break; 3454 case ACB_ADAPTER_TYPE_D: 3455 arcmsr_start_hbd_bgrb(acb); 3456 break; 3457 case ACB_ADAPTER_TYPE_E: 3458 case ACB_ADAPTER_TYPE_F: 3459 arcmsr_start_hbe_bgrb(acb); 3460 break; 3461 } 3462 } 3463 /* 3464 ********************************************************************** 3465 ** 3466 ********************************************************************** 3467 */ 3468 static void arcmsr_polling_hba_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3469 { 3470 struct CommandControlBlock *srb; 3471 u_int32_t flag_srb, outbound_intstatus, poll_srb_done=0, poll_count=0; 3472 u_int16_t error; 3473 3474 polling_ccb_retry: 3475 poll_count++; 3476 outbound_intstatus=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 3477 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus); /*clear interrupt*/ 3478 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3479 while(1) { 3480 if((flag_srb = CHIP_REG_READ32(HBA_MessageUnit, 3481 0, outbound_queueport)) == 0xFFFFFFFF) { 3482 if(poll_srb_done) { 3483 break;/*chip FIFO no ccb for completion already*/ 3484 } else { 3485 UDELAY(25000); 3486 if ((poll_count > 100) && (poll_srb != NULL)) { 3487 break; 3488 } 3489 goto polling_ccb_retry; 3490 } 3491 } 3492 /* check if command done with no error*/ 3493 srb = (struct CommandControlBlock *) 3494 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 3495 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 3496 poll_srb_done = (srb == poll_srb) ? 1:0; 3497 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3498 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3499 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'" 3500 "poll command abort successfully \n" 3501 , acb->pci_unit 3502 , srb->pccb->ccb_h.target_id 3503 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3504 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3505 arcmsr_srb_complete(srb, 1); 3506 continue; 3507 } 3508 printf("arcmsr%d: polling get an illegal srb command done srb='%p'" 3509 "srboutstandingcount=%d \n" 3510 , acb->pci_unit 3511 , srb, acb->srboutstandingcount); 3512 continue; 3513 } 3514 arcmsr_report_srb_state(acb, srb, error); 3515 } /*drain reply FIFO*/ 3516 } 3517 /* 3518 ********************************************************************** 3519 ** 3520 ********************************************************************** 3521 */ 3522 static void arcmsr_polling_hbb_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3523 { 3524 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3525 struct CommandControlBlock *srb; 3526 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3527 int index; 3528 u_int16_t error; 3529 3530 polling_ccb_retry: 3531 poll_count++; 3532 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */ 3533 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3534 while(1) { 3535 index = phbbmu->doneq_index; 3536 if((flag_srb = phbbmu->done_qbuffer[index]) == 0) { 3537 if(poll_srb_done) { 3538 break;/*chip FIFO no ccb for completion already*/ 3539 } else { 3540 UDELAY(25000); 3541 if ((poll_count > 100) && (poll_srb != NULL)) { 3542 break; 3543 } 3544 goto polling_ccb_retry; 3545 } 3546 } 3547 phbbmu->done_qbuffer[index] = 0; 3548 index++; 3549 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 3550 phbbmu->doneq_index = index; 3551 /* check if command done with no error*/ 3552 srb = (struct CommandControlBlock *) 3553 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 3554 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 3555 poll_srb_done = (srb == poll_srb) ? 1:0; 3556 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3557 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3558 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'" 3559 "poll command abort successfully \n" 3560 , acb->pci_unit 3561 , srb->pccb->ccb_h.target_id 3562 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3563 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3564 arcmsr_srb_complete(srb, 1); 3565 continue; 3566 } 3567 printf("arcmsr%d: polling get an illegal srb command done srb='%p'" 3568 "srboutstandingcount=%d \n" 3569 , acb->pci_unit 3570 , srb, acb->srboutstandingcount); 3571 continue; 3572 } 3573 arcmsr_report_srb_state(acb, srb, error); 3574 } /*drain reply FIFO*/ 3575 } 3576 /* 3577 ********************************************************************** 3578 ** 3579 ********************************************************************** 3580 */ 3581 static void arcmsr_polling_hbc_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3582 { 3583 struct CommandControlBlock *srb; 3584 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3585 u_int16_t error; 3586 3587 polling_ccb_retry: 3588 poll_count++; 3589 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3590 while(1) { 3591 if(!(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)) { 3592 if(poll_srb_done) { 3593 break;/*chip FIFO no ccb for completion already*/ 3594 } else { 3595 UDELAY(25000); 3596 if ((poll_count > 100) && (poll_srb != NULL)) { 3597 break; 3598 } 3599 if (acb->srboutstandingcount == 0) { 3600 break; 3601 } 3602 goto polling_ccb_retry; 3603 } 3604 } 3605 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 3606 /* check if command done with no error*/ 3607 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/ 3608 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE; 3609 if (poll_srb != NULL) 3610 poll_srb_done = (srb == poll_srb) ? 1:0; 3611 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3612 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3613 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n" 3614 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3615 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3616 arcmsr_srb_complete(srb, 1); 3617 continue; 3618 } 3619 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 3620 , acb->pci_unit, srb, acb->srboutstandingcount); 3621 continue; 3622 } 3623 arcmsr_report_srb_state(acb, srb, error); 3624 } /*drain reply FIFO*/ 3625 } 3626 /* 3627 ********************************************************************** 3628 ** 3629 ********************************************************************** 3630 */ 3631 static void arcmsr_polling_hbd_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3632 { 3633 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 3634 struct CommandControlBlock *srb; 3635 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3636 u_int32_t outbound_write_pointer; 3637 u_int16_t error, doneq_index; 3638 3639 polling_ccb_retry: 3640 poll_count++; 3641 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3642 while(1) { 3643 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 3644 doneq_index = phbdmu->doneq_index; 3645 if ((outbound_write_pointer & 0xFF) == (doneq_index & 0xFF)) { 3646 if(poll_srb_done) { 3647 break;/*chip FIFO no ccb for completion already*/ 3648 } else { 3649 UDELAY(25000); 3650 if ((poll_count > 100) && (poll_srb != NULL)) { 3651 break; 3652 } 3653 if (acb->srboutstandingcount == 0) { 3654 break; 3655 } 3656 goto polling_ccb_retry; 3657 } 3658 } 3659 doneq_index = arcmsr_get_doneq_index(phbdmu); 3660 flag_srb = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow; 3661 /* check if command done with no error*/ 3662 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/ 3663 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 3664 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index); 3665 if (poll_srb != NULL) 3666 poll_srb_done = (srb == poll_srb) ? 1:0; 3667 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3668 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3669 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n" 3670 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3671 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3672 arcmsr_srb_complete(srb, 1); 3673 continue; 3674 } 3675 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 3676 , acb->pci_unit, srb, acb->srboutstandingcount); 3677 continue; 3678 } 3679 arcmsr_report_srb_state(acb, srb, error); 3680 } /*drain reply FIFO*/ 3681 } 3682 /* 3683 ********************************************************************** 3684 ** 3685 ********************************************************************** 3686 */ 3687 static void arcmsr_polling_hbe_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3688 { 3689 struct CommandControlBlock *srb; 3690 u_int32_t poll_srb_done=0, poll_count=0, doneq_index; 3691 u_int16_t error, cmdSMID; 3692 3693 polling_ccb_retry: 3694 poll_count++; 3695 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3696 while(1) { 3697 doneq_index = acb->doneq_index; 3698 if((CHIP_REG_READ32(HBE_MessageUnit, 0, reply_post_producer_index) & 0xFFFF) == doneq_index) { 3699 if(poll_srb_done) { 3700 break;/*chip FIFO no ccb for completion already*/ 3701 } else { 3702 UDELAY(25000); 3703 if ((poll_count > 100) && (poll_srb != NULL)) { 3704 break; 3705 } 3706 if (acb->srboutstandingcount == 0) { 3707 break; 3708 } 3709 goto polling_ccb_retry; 3710 } 3711 } 3712 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID; 3713 doneq_index++; 3714 if (doneq_index >= acb->completionQ_entry) 3715 doneq_index = 0; 3716 acb->doneq_index = doneq_index; 3717 srb = acb->psrb_pool[cmdSMID]; 3718 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 3719 if (poll_srb != NULL) 3720 poll_srb_done = (srb == poll_srb) ? 1:0; 3721 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3722 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3723 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n" 3724 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3725 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3726 arcmsr_srb_complete(srb, 1); 3727 continue; 3728 } 3729 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 3730 , acb->pci_unit, srb, acb->srboutstandingcount); 3731 continue; 3732 } 3733 arcmsr_report_srb_state(acb, srb, error); 3734 } /*drain reply FIFO*/ 3735 CHIP_REG_WRITE32(HBE_MessageUnit, 0, reply_post_producer_index, doneq_index); 3736 } 3737 /* 3738 ********************************************************************** 3739 ********************************************************************** 3740 */ 3741 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3742 { 3743 switch (acb->adapter_type) { 3744 case ACB_ADAPTER_TYPE_A: 3745 arcmsr_polling_hba_srbdone(acb, poll_srb); 3746 break; 3747 case ACB_ADAPTER_TYPE_B: 3748 arcmsr_polling_hbb_srbdone(acb, poll_srb); 3749 break; 3750 case ACB_ADAPTER_TYPE_C: 3751 arcmsr_polling_hbc_srbdone(acb, poll_srb); 3752 break; 3753 case ACB_ADAPTER_TYPE_D: 3754 arcmsr_polling_hbd_srbdone(acb, poll_srb); 3755 break; 3756 case ACB_ADAPTER_TYPE_E: 3757 case ACB_ADAPTER_TYPE_F: 3758 arcmsr_polling_hbe_srbdone(acb, poll_srb); 3759 break; 3760 } 3761 } 3762 /* 3763 ********************************************************************** 3764 ********************************************************************** 3765 */ 3766 static void arcmsr_get_hba_config(struct AdapterControlBlock *acb) 3767 { 3768 char *acb_firm_model = acb->firm_model; 3769 char *acb_firm_version = acb->firm_version; 3770 char *acb_device_map = acb->device_map; 3771 size_t iop_firm_model = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3772 size_t iop_firm_version = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3773 size_t iop_device_map = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3774 int i; 3775 3776 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3777 if(!arcmsr_hba_wait_msgint_ready(acb)) { 3778 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3779 } 3780 i = 0; 3781 while(i < 8) { 3782 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3783 /* 8 bytes firm_model, 15, 60-67*/ 3784 acb_firm_model++; 3785 i++; 3786 } 3787 i=0; 3788 while(i < 16) { 3789 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3790 /* 16 bytes firm_version, 17, 68-83*/ 3791 acb_firm_version++; 3792 i++; 3793 } 3794 i=0; 3795 while(i < 16) { 3796 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3797 acb_device_map++; 3798 i++; 3799 } 3800 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3801 acb->firm_request_len = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3802 acb->firm_numbers_queue = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3803 acb->firm_sdram_size = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3804 acb->firm_ide_channels = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3805 acb->firm_cfg_version = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3806 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 3807 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 3808 else 3809 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3810 } 3811 /* 3812 ********************************************************************** 3813 ********************************************************************** 3814 */ 3815 static void arcmsr_get_hbb_config(struct AdapterControlBlock *acb) 3816 { 3817 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3818 char *acb_firm_model = acb->firm_model; 3819 char *acb_firm_version = acb->firm_version; 3820 char *acb_device_map = acb->device_map; 3821 size_t iop_firm_model = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3822 size_t iop_firm_version = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3823 size_t iop_device_map = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3824 int i; 3825 3826 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG); 3827 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3828 printf( "arcmsr%d: wait" "'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3829 } 3830 i = 0; 3831 while(i < 8) { 3832 *acb_firm_model = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_model+i); 3833 /* 8 bytes firm_model, 15, 60-67*/ 3834 acb_firm_model++; 3835 i++; 3836 } 3837 i = 0; 3838 while(i < 16) { 3839 *acb_firm_version = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_version+i); 3840 /* 16 bytes firm_version, 17, 68-83*/ 3841 acb_firm_version++; 3842 i++; 3843 } 3844 i = 0; 3845 while(i < 16) { 3846 *acb_device_map = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_device_map+i); 3847 acb_device_map++; 3848 i++; 3849 } 3850 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3851 acb->firm_request_len = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3852 acb->firm_numbers_queue = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3853 acb->firm_sdram_size = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3854 acb->firm_ide_channels = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3855 acb->firm_cfg_version = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3856 if(acb->firm_numbers_queue > ARCMSR_MAX_HBB_POSTQUEUE) 3857 acb->maxOutstanding = ARCMSR_MAX_HBB_POSTQUEUE - 1; 3858 else 3859 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3860 } 3861 /* 3862 ********************************************************************** 3863 ********************************************************************** 3864 */ 3865 static void arcmsr_get_hbc_config(struct AdapterControlBlock *acb) 3866 { 3867 char *acb_firm_model = acb->firm_model; 3868 char *acb_firm_version = acb->firm_version; 3869 char *acb_device_map = acb->device_map; 3870 size_t iop_firm_model = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3871 size_t iop_firm_version = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3872 size_t iop_device_map = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3873 int i; 3874 3875 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3876 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3877 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 3878 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3879 } 3880 i = 0; 3881 while(i < 8) { 3882 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3883 /* 8 bytes firm_model, 15, 60-67*/ 3884 acb_firm_model++; 3885 i++; 3886 } 3887 i = 0; 3888 while(i < 16) { 3889 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3890 /* 16 bytes firm_version, 17, 68-83*/ 3891 acb_firm_version++; 3892 i++; 3893 } 3894 i = 0; 3895 while(i < 16) { 3896 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3897 acb_device_map++; 3898 i++; 3899 } 3900 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3901 acb->firm_request_len = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3902 acb->firm_numbers_queue = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3903 acb->firm_sdram_size = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3904 acb->firm_ide_channels = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3905 acb->firm_cfg_version = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3906 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 3907 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 3908 else 3909 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3910 } 3911 /* 3912 ********************************************************************** 3913 ********************************************************************** 3914 */ 3915 static void arcmsr_get_hbd_config(struct AdapterControlBlock *acb) 3916 { 3917 char *acb_firm_model = acb->firm_model; 3918 char *acb_firm_version = acb->firm_version; 3919 char *acb_device_map = acb->device_map; 3920 size_t iop_firm_model = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3921 size_t iop_firm_version = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3922 size_t iop_device_map = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3923 int i; 3924 3925 if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) 3926 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR); 3927 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3928 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 3929 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3930 } 3931 i = 0; 3932 while(i < 8) { 3933 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3934 /* 8 bytes firm_model, 15, 60-67*/ 3935 acb_firm_model++; 3936 i++; 3937 } 3938 i = 0; 3939 while(i < 16) { 3940 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3941 /* 16 bytes firm_version, 17, 68-83*/ 3942 acb_firm_version++; 3943 i++; 3944 } 3945 i = 0; 3946 while(i < 16) { 3947 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3948 acb_device_map++; 3949 i++; 3950 } 3951 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3952 acb->firm_request_len = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3953 acb->firm_numbers_queue = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3954 acb->firm_sdram_size = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3955 acb->firm_ide_channels = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3956 acb->firm_cfg_version = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3957 if(acb->firm_numbers_queue > ARCMSR_MAX_HBD_POSTQUEUE) 3958 acb->maxOutstanding = ARCMSR_MAX_HBD_POSTQUEUE - 1; 3959 else 3960 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3961 } 3962 /* 3963 ********************************************************************** 3964 ********************************************************************** 3965 */ 3966 static void arcmsr_get_hbe_config(struct AdapterControlBlock *acb) 3967 { 3968 char *acb_firm_model = acb->firm_model; 3969 char *acb_firm_version = acb->firm_version; 3970 char *acb_device_map = acb->device_map; 3971 size_t iop_firm_model = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3972 size_t iop_firm_version = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3973 size_t iop_device_map = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3974 int i; 3975 3976 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3977 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 3978 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 3979 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 3980 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3981 } 3982 3983 i = 0; 3984 while(i < 8) { 3985 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3986 /* 8 bytes firm_model, 15, 60-67*/ 3987 acb_firm_model++; 3988 i++; 3989 } 3990 i = 0; 3991 while(i < 16) { 3992 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3993 /* 16 bytes firm_version, 17, 68-83*/ 3994 acb_firm_version++; 3995 i++; 3996 } 3997 i = 0; 3998 while(i < 16) { 3999 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 4000 acb_device_map++; 4001 i++; 4002 } 4003 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 4004 acb->firm_request_len = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 4005 acb->firm_numbers_queue = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 4006 acb->firm_sdram_size = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 4007 acb->firm_ide_channels = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 4008 acb->firm_cfg_version = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 4009 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 4010 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 4011 else 4012 acb->maxOutstanding = acb->firm_numbers_queue - 1; 4013 } 4014 /* 4015 ********************************************************************** 4016 ********************************************************************** 4017 */ 4018 static void arcmsr_get_hbf_config(struct AdapterControlBlock *acb) 4019 { 4020 u_int32_t *acb_firm_model = (u_int32_t *)acb->firm_model; 4021 u_int32_t *acb_firm_version = (u_int32_t *)acb->firm_version; 4022 u_int32_t *acb_device_map = (u_int32_t *)acb->device_map; 4023 size_t iop_firm_model = ARCMSR_FW_MODEL_OFFSET; /*firm_model,15,60-67*/ 4024 size_t iop_firm_version = ARCMSR_FW_VERS_OFFSET; /*firm_version,17,68-83*/ 4025 size_t iop_device_map = ARCMSR_FW_DEVMAP_OFFSET; 4026 int i; 4027 4028 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 4029 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 4030 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 4031 if(!arcmsr_hbe_wait_msgint_ready(acb)) 4032 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 4033 4034 i = 0; 4035 while(i < 2) { 4036 *acb_firm_model = acb->msgcode_rwbuffer[iop_firm_model]; 4037 /* 8 bytes firm_model, 15, 60-67*/ 4038 acb_firm_model++; 4039 iop_firm_model++; 4040 i++; 4041 } 4042 i = 0; 4043 while(i < 4) { 4044 *acb_firm_version = acb->msgcode_rwbuffer[iop_firm_version]; 4045 /* 16 bytes firm_version, 17, 68-83*/ 4046 acb_firm_version++; 4047 iop_firm_version++; 4048 i++; 4049 } 4050 i = 0; 4051 while(i < 4) { 4052 *acb_device_map = acb->msgcode_rwbuffer[iop_device_map]; 4053 acb_device_map++; 4054 iop_device_map++; 4055 i++; 4056 } 4057 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 4058 acb->firm_request_len = acb->msgcode_rwbuffer[1]; /*firm_request_len, 1, 04-07*/ 4059 acb->firm_numbers_queue = acb->msgcode_rwbuffer[2]; /*firm_numbers_queue, 2, 08-11*/ 4060 acb->firm_sdram_size = acb->msgcode_rwbuffer[3]; /*firm_sdram_size, 3, 12-15*/ 4061 acb->firm_ide_channels = acb->msgcode_rwbuffer[4]; /*firm_ide_channels, 4, 16-19*/ 4062 acb->firm_cfg_version = acb->msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]; /*firm_cfg_version, 25*/ 4063 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 4064 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 4065 else 4066 acb->maxOutstanding = acb->firm_numbers_queue - 1; 4067 } 4068 /* 4069 ********************************************************************** 4070 ********************************************************************** 4071 */ 4072 static void arcmsr_get_firmware_spec(struct AdapterControlBlock *acb) 4073 { 4074 switch (acb->adapter_type) { 4075 case ACB_ADAPTER_TYPE_A: 4076 arcmsr_get_hba_config(acb); 4077 break; 4078 case ACB_ADAPTER_TYPE_B: 4079 arcmsr_get_hbb_config(acb); 4080 break; 4081 case ACB_ADAPTER_TYPE_C: 4082 arcmsr_get_hbc_config(acb); 4083 break; 4084 case ACB_ADAPTER_TYPE_D: 4085 arcmsr_get_hbd_config(acb); 4086 break; 4087 case ACB_ADAPTER_TYPE_E: 4088 arcmsr_get_hbe_config(acb); 4089 break; 4090 case ACB_ADAPTER_TYPE_F: 4091 arcmsr_get_hbf_config(acb); 4092 break; 4093 } 4094 } 4095 /* 4096 ********************************************************************** 4097 ********************************************************************** 4098 */ 4099 static void arcmsr_wait_firmware_ready( struct AdapterControlBlock *acb) 4100 { 4101 int timeout=0; 4102 4103 switch (acb->adapter_type) { 4104 case ACB_ADAPTER_TYPE_A: { 4105 while ((CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0) 4106 { 4107 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 4108 { 4109 printf( "arcmsr%d:timed out waiting for firmware \n", acb->pci_unit); 4110 return; 4111 } 4112 UDELAY(15000); /* wait 15 milli-seconds */ 4113 } 4114 } 4115 break; 4116 case ACB_ADAPTER_TYPE_B: { 4117 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4118 while ((READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & ARCMSR_MESSAGE_FIRMWARE_OK) == 0) 4119 { 4120 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 4121 { 4122 printf( "arcmsr%d: timed out waiting for firmware \n", acb->pci_unit); 4123 return; 4124 } 4125 UDELAY(15000); /* wait 15 milli-seconds */ 4126 } 4127 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 4128 } 4129 break; 4130 case ACB_ADAPTER_TYPE_C: { 4131 while ((CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0) 4132 { 4133 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 4134 { 4135 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 4136 return; 4137 } 4138 UDELAY(15000); /* wait 15 milli-seconds */ 4139 } 4140 } 4141 break; 4142 case ACB_ADAPTER_TYPE_D: { 4143 while ((CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK) == 0) 4144 { 4145 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 4146 { 4147 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 4148 return; 4149 } 4150 UDELAY(15000); /* wait 15 milli-seconds */ 4151 } 4152 } 4153 break; 4154 case ACB_ADAPTER_TYPE_E: 4155 case ACB_ADAPTER_TYPE_F: { 4156 while ((CHIP_REG_READ32(HBE_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK) == 0) 4157 { 4158 if (timeout++ > 4000) /* (4000*15)/1000 = 60 sec */ 4159 { 4160 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 4161 return; 4162 } 4163 UDELAY(15000); /* wait 15 milli-seconds */ 4164 } 4165 } 4166 break; 4167 } 4168 } 4169 /* 4170 ********************************************************************** 4171 ********************************************************************** 4172 */ 4173 static void arcmsr_clear_doorbell_queue_buffer( struct AdapterControlBlock *acb) 4174 { 4175 u_int32_t outbound_doorbell; 4176 4177 switch (acb->adapter_type) { 4178 case ACB_ADAPTER_TYPE_A: { 4179 /* empty doorbell Qbuffer if door bell ringed */ 4180 outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell); 4181 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */ 4182 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK); 4183 } 4184 break; 4185 case ACB_ADAPTER_TYPE_B: { 4186 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4187 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN);/*clear interrupt and message state*/ 4188 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK); 4189 /* let IOP know data has been read */ 4190 } 4191 break; 4192 case ACB_ADAPTER_TYPE_C: { 4193 /* empty doorbell Qbuffer if door bell ringed */ 4194 outbound_doorbell = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell); 4195 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell); /*clear doorbell interrupt */ 4196 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK); 4197 CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell_clear); /* Dummy read to force pci flush */ 4198 CHIP_REG_READ32(HBC_MessageUnit, 0, inbound_doorbell); /* Dummy read to force pci flush */ 4199 } 4200 break; 4201 case ACB_ADAPTER_TYPE_D: { 4202 /* empty doorbell Qbuffer if door bell ringed */ 4203 outbound_doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell); 4204 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */ 4205 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ); 4206 } 4207 break; 4208 case ACB_ADAPTER_TYPE_E: 4209 case ACB_ADAPTER_TYPE_F: { 4210 /* empty doorbell Qbuffer if door bell ringed */ 4211 acb->in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell); 4212 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /*clear doorbell interrupt */ 4213 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK; 4214 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 4215 } 4216 break; 4217 } 4218 } 4219 /* 4220 ************************************************************************ 4221 ************************************************************************ 4222 */ 4223 static u_int32_t arcmsr_iop_confirm(struct AdapterControlBlock *acb) 4224 { 4225 unsigned long srb_phyaddr; 4226 u_int32_t srb_phyaddr_hi32; 4227 u_int32_t srb_phyaddr_lo32; 4228 4229 /* 4230 ******************************************************************** 4231 ** here we need to tell iop 331 our freesrb.HighPart 4232 ** if freesrb.HighPart is not zero 4233 ******************************************************************** 4234 */ 4235 srb_phyaddr = (unsigned long) acb->srb_phyaddr.phyaddr; 4236 srb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high; 4237 srb_phyaddr_lo32 = acb->srb_phyaddr.B.phyadd_low; 4238 switch (acb->adapter_type) { 4239 case ACB_ADAPTER_TYPE_A: { 4240 if(srb_phyaddr_hi32 != 0) { 4241 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 4242 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 4243 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4244 if(!arcmsr_hba_wait_msgint_ready(acb)) { 4245 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4246 return FALSE; 4247 } 4248 } 4249 } 4250 break; 4251 /* 4252 *********************************************************************** 4253 ** if adapter type B, set window of "post command Q" 4254 *********************************************************************** 4255 */ 4256 case ACB_ADAPTER_TYPE_B: { 4257 u_int32_t post_queue_phyaddr; 4258 struct HBB_MessageUnit *phbbmu; 4259 4260 phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4261 phbbmu->postq_index = 0; 4262 phbbmu->doneq_index = 0; 4263 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_SET_POST_WINDOW); 4264 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 4265 printf( "arcmsr%d: 'set window of post command Q' timeout\n", acb->pci_unit); 4266 return FALSE; 4267 } 4268 post_queue_phyaddr = srb_phyaddr + ARCMSR_SRBS_POOL_SIZE 4269 + offsetof(struct HBB_MessageUnit, post_qbuffer); 4270 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */ 4271 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1], srb_phyaddr_hi32); /* normal should be zero */ 4272 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ size (256+8)*4 */ 4273 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3], post_queue_phyaddr+1056); /* doneQ size (256+8)*4 */ 4274 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4], 1056); /* srb maxQ size must be --> [(256+8)*4] */ 4275 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_SET_CONFIG); 4276 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 4277 printf( "arcmsr%d: 'set command Q window' timeout \n", acb->pci_unit); 4278 return FALSE; 4279 } 4280 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_START_DRIVER_MODE); 4281 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 4282 printf( "arcmsr%d: 'start diver mode' timeout \n", acb->pci_unit); 4283 return FALSE; 4284 } 4285 } 4286 break; 4287 case ACB_ADAPTER_TYPE_C: { 4288 if(srb_phyaddr_hi32 != 0) { 4289 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 4290 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 4291 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4292 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 4293 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 4294 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4295 return FALSE; 4296 } 4297 } 4298 } 4299 break; 4300 case ACB_ADAPTER_TYPE_D: { 4301 u_int32_t post_queue_phyaddr, done_queue_phyaddr; 4302 struct HBD_MessageUnit0 *phbdmu; 4303 4304 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 4305 phbdmu->postq_index = 0; 4306 phbdmu->doneq_index = 0x40FF; 4307 post_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE 4308 + offsetof(struct HBD_MessageUnit0, post_qbuffer); 4309 done_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE 4310 + offsetof(struct HBD_MessageUnit0, done_qbuffer); 4311 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */ 4312 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 4313 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ base */ 4314 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[3], done_queue_phyaddr); /* doneQ base */ 4315 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[4], 0x100); 4316 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4317 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 4318 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4319 return FALSE; 4320 } 4321 } 4322 break; 4323 case ACB_ADAPTER_TYPE_E: { 4324 u_int32_t cdb_phyaddr_lo32; 4325 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + offsetof(struct CommandControlBlock, arcmsr_cdb); 4326 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 4327 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[1], ARCMSR_SIGNATURE_1884); 4328 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[2], cdb_phyaddr_lo32); 4329 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[3], srb_phyaddr_hi32); 4330 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[4], SRB_SIZE); 4331 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE; 4332 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[5], cdb_phyaddr_lo32); 4333 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[6], srb_phyaddr_hi32); 4334 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[7], COMPLETION_Q_POOL_SIZE); 4335 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4336 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 4337 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 4338 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 4339 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4340 return FALSE; 4341 } 4342 } 4343 break; 4344 case ACB_ADAPTER_TYPE_F: { 4345 u_int32_t cdb_phyaddr_lo32; 4346 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + offsetof(struct CommandControlBlock, arcmsr_cdb); 4347 acb->msgcode_rwbuffer[0] = ARCMSR_SIGNATURE_SET_CONFIG; 4348 acb->msgcode_rwbuffer[1] = ARCMSR_SIGNATURE_1886; 4349 acb->msgcode_rwbuffer[2] = cdb_phyaddr_lo32; 4350 acb->msgcode_rwbuffer[3] = srb_phyaddr_hi32; 4351 acb->msgcode_rwbuffer[4] = SRB_SIZE; 4352 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE; 4353 acb->msgcode_rwbuffer[5] = cdb_phyaddr_lo32; 4354 acb->msgcode_rwbuffer[6] = srb_phyaddr_hi32; 4355 acb->msgcode_rwbuffer[7] = COMPLETION_Q_POOL_SIZE; 4356 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4357 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 4358 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 4359 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 4360 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4361 return FALSE; 4362 } 4363 } 4364 break; 4365 } 4366 return (TRUE); 4367 } 4368 /* 4369 ************************************************************************ 4370 ************************************************************************ 4371 */ 4372 static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb) 4373 { 4374 if (acb->adapter_type == ACB_ADAPTER_TYPE_B) 4375 { 4376 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4377 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_ACTIVE_EOI_MODE); 4378 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 4379 printf( "arcmsr%d: 'iop enable eoi mode' timeout \n", acb->pci_unit); 4380 return; 4381 } 4382 } 4383 } 4384 /* 4385 ********************************************************************** 4386 ********************************************************************** 4387 */ 4388 static void arcmsr_iop_init(struct AdapterControlBlock *acb) 4389 { 4390 u_int32_t intmask_org; 4391 4392 /* disable all outbound interrupt */ 4393 intmask_org = arcmsr_disable_allintr(acb); 4394 arcmsr_wait_firmware_ready(acb); 4395 arcmsr_iop_confirm(acb); 4396 arcmsr_get_firmware_spec(acb); 4397 /*start background rebuild*/ 4398 arcmsr_start_adapter_bgrb(acb); 4399 /* empty doorbell Qbuffer if door bell ringed */ 4400 arcmsr_clear_doorbell_queue_buffer(acb); 4401 arcmsr_enable_eoi_mode(acb); 4402 /* enable outbound Post Queue, outbound doorbell Interrupt */ 4403 arcmsr_enable_allintr(acb, intmask_org); 4404 acb->acb_flags |= ACB_F_IOP_INITED; 4405 } 4406 /* 4407 ********************************************************************** 4408 ********************************************************************** 4409 */ 4410 static void arcmsr_map_free_srb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4411 { 4412 struct AdapterControlBlock *acb = arg; 4413 struct CommandControlBlock *srb_tmp; 4414 u_int32_t i; 4415 unsigned long srb_phyaddr = (unsigned long)segs->ds_addr; 4416 4417 acb->srb_phyaddr.phyaddr = srb_phyaddr; 4418 srb_tmp = (struct CommandControlBlock *)acb->uncacheptr; 4419 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 4420 if(bus_dmamap_create(acb->dm_segs_dmat, 4421 /*flags*/0, &srb_tmp->dm_segs_dmamap) != 0) { 4422 acb->acb_flags |= ACB_F_MAPFREESRB_FAILD; 4423 printf("arcmsr%d:" 4424 " srb dmamap bus_dmamap_create error\n", acb->pci_unit); 4425 return; 4426 } 4427 if((acb->adapter_type == ACB_ADAPTER_TYPE_C) || (acb->adapter_type == ACB_ADAPTER_TYPE_D) 4428 || (acb->adapter_type == ACB_ADAPTER_TYPE_E) || (acb->adapter_type == ACB_ADAPTER_TYPE_F)) 4429 { 4430 srb_tmp->cdb_phyaddr_low = srb_phyaddr; 4431 srb_tmp->cdb_phyaddr_high = (u_int32_t)((srb_phyaddr >> 16) >> 16); 4432 } 4433 else 4434 srb_tmp->cdb_phyaddr_low = srb_phyaddr >> 5; 4435 srb_tmp->acb = acb; 4436 srb_tmp->smid = i << 16; 4437 acb->srbworkingQ[i] = acb->psrb_pool[i] = srb_tmp; 4438 srb_phyaddr = srb_phyaddr + SRB_SIZE; 4439 srb_tmp = (struct CommandControlBlock *)((unsigned long)srb_tmp + SRB_SIZE); 4440 } 4441 if (acb->adapter_type == ACB_ADAPTER_TYPE_E) 4442 acb->pCompletionQ = (pCompletion_Q)srb_tmp; 4443 else if (acb->adapter_type == ACB_ADAPTER_TYPE_F) { 4444 acb->pCompletionQ = (pCompletion_Q)srb_tmp; 4445 acb->completeQ_phys = srb_phyaddr; 4446 memset(acb->pCompletionQ, 0xff, COMPLETION_Q_POOL_SIZE); 4447 acb->message_wbuffer = (u_int32_t *)((unsigned long)acb->pCompletionQ + COMPLETION_Q_POOL_SIZE); 4448 acb->message_rbuffer = (u_int32_t *)((unsigned long)acb->message_wbuffer + 0x100); 4449 acb->msgcode_rwbuffer = (u_int32_t *)((unsigned long)acb->message_wbuffer + 0x200); 4450 memset((void *)acb->message_wbuffer, 0, MESG_RW_BUFFER_SIZE); 4451 } 4452 acb->vir2phy_offset = (unsigned long)srb_tmp - (unsigned long)srb_phyaddr; 4453 } 4454 /* 4455 ************************************************************************ 4456 ************************************************************************ 4457 */ 4458 static void arcmsr_free_resource(struct AdapterControlBlock *acb) 4459 { 4460 /* remove the control device */ 4461 if(acb->ioctl_dev != NULL) { 4462 destroy_dev(acb->ioctl_dev); 4463 } 4464 bus_dmamap_unload(acb->srb_dmat, acb->srb_dmamap); 4465 bus_dmamap_destroy(acb->srb_dmat, acb->srb_dmamap); 4466 bus_dma_tag_destroy(acb->srb_dmat); 4467 bus_dma_tag_destroy(acb->dm_segs_dmat); 4468 bus_dma_tag_destroy(acb->parent_dmat); 4469 } 4470 /* 4471 ************************************************************************ 4472 ************************************************************************ 4473 */ 4474 static void arcmsr_mutex_init(struct AdapterControlBlock *acb) 4475 { 4476 ARCMSR_LOCK_INIT(&acb->isr_lock, "arcmsr isr lock"); 4477 ARCMSR_LOCK_INIT(&acb->srb_lock, "arcmsr srb lock"); 4478 ARCMSR_LOCK_INIT(&acb->postDone_lock, "arcmsr postQ lock"); 4479 ARCMSR_LOCK_INIT(&acb->qbuffer_lock, "arcmsr RW buffer lock"); 4480 } 4481 /* 4482 ************************************************************************ 4483 ************************************************************************ 4484 */ 4485 static void arcmsr_mutex_destroy(struct AdapterControlBlock *acb) 4486 { 4487 ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock); 4488 ARCMSR_LOCK_DESTROY(&acb->postDone_lock); 4489 ARCMSR_LOCK_DESTROY(&acb->srb_lock); 4490 ARCMSR_LOCK_DESTROY(&acb->isr_lock); 4491 } 4492 /* 4493 ************************************************************************ 4494 ************************************************************************ 4495 */ 4496 static u_int32_t arcmsr_initialize(device_t dev) 4497 { 4498 struct AdapterControlBlock *acb = device_get_softc(dev); 4499 u_int16_t pci_command; 4500 int i, j,max_coherent_size; 4501 u_int32_t vendor_dev_id; 4502 4503 vendor_dev_id = pci_get_devid(dev); 4504 acb->vendor_device_id = vendor_dev_id; 4505 acb->sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); 4506 switch (vendor_dev_id) { 4507 case PCIDevVenIDARC1880: 4508 case PCIDevVenIDARC1882: 4509 case PCIDevVenIDARC1213: 4510 case PCIDevVenIDARC1223: { 4511 acb->adapter_type = ACB_ADAPTER_TYPE_C; 4512 if ((acb->sub_device_id == ARECA_SUB_DEV_ID_1883) || 4513 (acb->sub_device_id == ARECA_SUB_DEV_ID_1216) || 4514 (acb->sub_device_id == ARECA_SUB_DEV_ID_1226)) 4515 acb->adapter_bus_speed = ACB_BUS_SPEED_12G; 4516 else 4517 acb->adapter_bus_speed = ACB_BUS_SPEED_6G; 4518 max_coherent_size = ARCMSR_SRBS_POOL_SIZE; 4519 } 4520 break; 4521 case PCIDevVenIDARC1884: 4522 acb->adapter_type = ACB_ADAPTER_TYPE_E; 4523 acb->adapter_bus_speed = ACB_BUS_SPEED_12G; 4524 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + COMPLETION_Q_POOL_SIZE; 4525 acb->completionQ_entry = COMPLETION_Q_POOL_SIZE / sizeof(struct deliver_completeQ); 4526 break; 4527 case PCIDevVenIDARC1886_: 4528 case PCIDevVenIDARC1886: 4529 acb->adapter_type = ACB_ADAPTER_TYPE_F; 4530 acb->adapter_bus_speed = ACB_BUS_SPEED_12G; 4531 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + COMPLETION_Q_POOL_SIZE + MESG_RW_BUFFER_SIZE; 4532 acb->completionQ_entry = COMPLETION_Q_POOL_SIZE / sizeof(struct deliver_completeQ); 4533 break; 4534 case PCIDevVenIDARC1214: { 4535 acb->adapter_type = ACB_ADAPTER_TYPE_D; 4536 acb->adapter_bus_speed = ACB_BUS_SPEED_6G; 4537 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBD_MessageUnit0)); 4538 } 4539 break; 4540 case PCIDevVenIDARC1200: 4541 case PCIDevVenIDARC1201: { 4542 acb->adapter_type = ACB_ADAPTER_TYPE_B; 4543 acb->adapter_bus_speed = ACB_BUS_SPEED_3G; 4544 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit)); 4545 } 4546 break; 4547 case PCIDevVenIDARC1203: { 4548 acb->adapter_type = ACB_ADAPTER_TYPE_B; 4549 acb->adapter_bus_speed = ACB_BUS_SPEED_6G; 4550 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit)); 4551 } 4552 break; 4553 case PCIDevVenIDARC1110: 4554 case PCIDevVenIDARC1120: 4555 case PCIDevVenIDARC1130: 4556 case PCIDevVenIDARC1160: 4557 case PCIDevVenIDARC1170: 4558 case PCIDevVenIDARC1210: 4559 case PCIDevVenIDARC1220: 4560 case PCIDevVenIDARC1230: 4561 case PCIDevVenIDARC1231: 4562 case PCIDevVenIDARC1260: 4563 case PCIDevVenIDARC1261: 4564 case PCIDevVenIDARC1270: 4565 case PCIDevVenIDARC1280: 4566 case PCIDevVenIDARC1212: 4567 case PCIDevVenIDARC1222: 4568 case PCIDevVenIDARC1380: 4569 case PCIDevVenIDARC1381: 4570 case PCIDevVenIDARC1680: 4571 case PCIDevVenIDARC1681: { 4572 acb->adapter_type = ACB_ADAPTER_TYPE_A; 4573 acb->adapter_bus_speed = ACB_BUS_SPEED_3G; 4574 max_coherent_size = ARCMSR_SRBS_POOL_SIZE; 4575 } 4576 break; 4577 default: { 4578 printf("arcmsr%d:" 4579 " unknown RAID adapter type \n", device_get_unit(dev)); 4580 return ENOMEM; 4581 } 4582 } 4583 if(bus_dma_tag_create( /*PCI parent*/ bus_get_dma_tag(dev), 4584 /*alignemnt*/ 1, 4585 /*boundary*/ 0, 4586 /*lowaddr*/ BUS_SPACE_MAXADDR, 4587 /*highaddr*/ BUS_SPACE_MAXADDR, 4588 /*filter*/ NULL, 4589 /*filterarg*/ NULL, 4590 /*maxsize*/ BUS_SPACE_MAXSIZE_32BIT, 4591 /*nsegments*/ BUS_SPACE_UNRESTRICTED, 4592 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4593 /*flags*/ 0, 4594 /*lockfunc*/ NULL, 4595 /*lockarg*/ NULL, 4596 &acb->parent_dmat) != 0) 4597 { 4598 printf("arcmsr%d: parent_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4599 return ENOMEM; 4600 } 4601 4602 /* Create a single tag describing a region large enough to hold all of the s/g lists we will need. */ 4603 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat, 4604 /*alignment*/ 1, 4605 /*boundary*/ 0, 4606 #ifdef PAE 4607 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 4608 #else 4609 /*lowaddr*/ BUS_SPACE_MAXADDR, 4610 #endif 4611 /*highaddr*/ BUS_SPACE_MAXADDR, 4612 /*filter*/ NULL, 4613 /*filterarg*/ NULL, 4614 /*maxsize*/ ARCMSR_MAX_SG_ENTRIES * PAGE_SIZE * ARCMSR_MAX_FREESRB_NUM, 4615 /*nsegments*/ ARCMSR_MAX_SG_ENTRIES, 4616 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4617 /*flags*/ 0, 4618 /*lockfunc*/ busdma_lock_mutex, 4619 /*lockarg*/ &acb->isr_lock, 4620 &acb->dm_segs_dmat) != 0) 4621 { 4622 bus_dma_tag_destroy(acb->parent_dmat); 4623 printf("arcmsr%d: dm_segs_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4624 return ENOMEM; 4625 } 4626 4627 /* DMA tag for our srb structures.... Allocate the freesrb memory */ 4628 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat, 4629 /*alignment*/ 0x20, 4630 /*boundary*/ 0, 4631 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 4632 /*highaddr*/ BUS_SPACE_MAXADDR, 4633 /*filter*/ NULL, 4634 /*filterarg*/ NULL, 4635 /*maxsize*/ max_coherent_size, 4636 /*nsegments*/ 1, 4637 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4638 /*flags*/ 0, 4639 /*lockfunc*/ NULL, 4640 /*lockarg*/ NULL, 4641 &acb->srb_dmat) != 0) 4642 { 4643 bus_dma_tag_destroy(acb->dm_segs_dmat); 4644 bus_dma_tag_destroy(acb->parent_dmat); 4645 printf("arcmsr%d: srb_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4646 return ENXIO; 4647 } 4648 /* Allocation for our srbs */ 4649 if(bus_dmamem_alloc(acb->srb_dmat, (void **)&acb->uncacheptr, BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, &acb->srb_dmamap) != 0) { 4650 bus_dma_tag_destroy(acb->srb_dmat); 4651 bus_dma_tag_destroy(acb->dm_segs_dmat); 4652 bus_dma_tag_destroy(acb->parent_dmat); 4653 printf("arcmsr%d: srb_dmat bus_dmamem_alloc failure!\n", device_get_unit(dev)); 4654 return ENXIO; 4655 } 4656 /* And permanently map them */ 4657 if(bus_dmamap_load(acb->srb_dmat, acb->srb_dmamap, acb->uncacheptr, max_coherent_size, arcmsr_map_free_srb, acb, /*flags*/0)) { 4658 bus_dma_tag_destroy(acb->srb_dmat); 4659 bus_dma_tag_destroy(acb->dm_segs_dmat); 4660 bus_dma_tag_destroy(acb->parent_dmat); 4661 printf("arcmsr%d: srb_dmat bus_dmamap_load failure!\n", device_get_unit(dev)); 4662 return ENXIO; 4663 } 4664 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 4665 pci_command |= PCIM_CMD_BUSMASTEREN; 4666 pci_command |= PCIM_CMD_PERRESPEN; 4667 pci_command |= PCIM_CMD_MWRICEN; 4668 /* Enable Busmaster */ 4669 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 4670 switch(acb->adapter_type) { 4671 case ACB_ADAPTER_TYPE_A: { 4672 u_int32_t rid0 = PCIR_BAR(0); 4673 vm_offset_t mem_base0; 4674 4675 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev,SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4676 if(acb->sys_res_arcmsr[0] == NULL) { 4677 arcmsr_free_resource(acb); 4678 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4679 return ENOMEM; 4680 } 4681 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4682 arcmsr_free_resource(acb); 4683 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4684 return ENXIO; 4685 } 4686 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4687 if(mem_base0 == 0) { 4688 arcmsr_free_resource(acb); 4689 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4690 return ENXIO; 4691 } 4692 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4693 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4694 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4695 acb->rid[0] = rid0; 4696 } 4697 break; 4698 case ACB_ADAPTER_TYPE_B: { 4699 struct HBB_MessageUnit *phbbmu; 4700 struct CommandControlBlock *freesrb; 4701 u_int32_t rid[]={ PCIR_BAR(0), PCIR_BAR(2) }; 4702 vm_offset_t mem_base[]={0,0}; 4703 for(i=0; i < 2; i++) { 4704 acb->sys_res_arcmsr[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid[i], RF_ACTIVE); 4705 if(acb->sys_res_arcmsr[i] == NULL) { 4706 arcmsr_free_resource(acb); 4707 printf("arcmsr%d: bus_alloc_resource %d failure!\n", device_get_unit(dev), i); 4708 return ENOMEM; 4709 } 4710 if(rman_get_start(acb->sys_res_arcmsr[i]) <= 0) { 4711 arcmsr_free_resource(acb); 4712 printf("arcmsr%d: rman_get_start %d failure!\n", device_get_unit(dev), i); 4713 return ENXIO; 4714 } 4715 mem_base[i] = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[i]); 4716 if(mem_base[i] == 0) { 4717 arcmsr_free_resource(acb); 4718 printf("arcmsr%d: rman_get_virtual %d failure!\n", device_get_unit(dev), i); 4719 return ENXIO; 4720 } 4721 acb->btag[i] = rman_get_bustag(acb->sys_res_arcmsr[i]); 4722 acb->bhandle[i] = rman_get_bushandle(acb->sys_res_arcmsr[i]); 4723 } 4724 freesrb = (struct CommandControlBlock *)acb->uncacheptr; 4725 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)freesrb+ARCMSR_SRBS_POOL_SIZE); 4726 phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4727 phbbmu->hbb_doorbell = (struct HBB_DOORBELL *)mem_base[0]; 4728 phbbmu->hbb_rwbuffer = (struct HBB_RWBUFFER *)mem_base[1]; 4729 if (vendor_dev_id == PCIDevVenIDARC1203) { 4730 phbbmu->drv2iop_doorbell = offsetof(struct HBB_DOORBELL_1203, drv2iop_doorbell); 4731 phbbmu->drv2iop_doorbell_mask = offsetof(struct HBB_DOORBELL_1203, drv2iop_doorbell_mask); 4732 phbbmu->iop2drv_doorbell = offsetof(struct HBB_DOORBELL_1203, iop2drv_doorbell); 4733 phbbmu->iop2drv_doorbell_mask = offsetof(struct HBB_DOORBELL_1203, iop2drv_doorbell_mask); 4734 } else { 4735 phbbmu->drv2iop_doorbell = offsetof(struct HBB_DOORBELL, drv2iop_doorbell); 4736 phbbmu->drv2iop_doorbell_mask = offsetof(struct HBB_DOORBELL, drv2iop_doorbell_mask); 4737 phbbmu->iop2drv_doorbell = offsetof(struct HBB_DOORBELL, iop2drv_doorbell); 4738 phbbmu->iop2drv_doorbell_mask = offsetof(struct HBB_DOORBELL, iop2drv_doorbell_mask); 4739 } 4740 acb->rid[0] = rid[0]; 4741 acb->rid[1] = rid[1]; 4742 } 4743 break; 4744 case ACB_ADAPTER_TYPE_C: { 4745 u_int32_t rid0 = PCIR_BAR(1); 4746 vm_offset_t mem_base0; 4747 4748 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4749 if(acb->sys_res_arcmsr[0] == NULL) { 4750 arcmsr_free_resource(acb); 4751 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4752 return ENOMEM; 4753 } 4754 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4755 arcmsr_free_resource(acb); 4756 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4757 return ENXIO; 4758 } 4759 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4760 if(mem_base0 == 0) { 4761 arcmsr_free_resource(acb); 4762 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4763 return ENXIO; 4764 } 4765 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4766 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4767 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4768 acb->rid[0] = rid0; 4769 } 4770 break; 4771 case ACB_ADAPTER_TYPE_D: { 4772 struct HBD_MessageUnit0 *phbdmu; 4773 u_int32_t rid0 = PCIR_BAR(0); 4774 vm_offset_t mem_base0; 4775 4776 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4777 if(acb->sys_res_arcmsr[0] == NULL) { 4778 arcmsr_free_resource(acb); 4779 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4780 return ENOMEM; 4781 } 4782 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4783 arcmsr_free_resource(acb); 4784 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4785 return ENXIO; 4786 } 4787 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4788 if(mem_base0 == 0) { 4789 arcmsr_free_resource(acb); 4790 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4791 return ENXIO; 4792 } 4793 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4794 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4795 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)acb->uncacheptr+ARCMSR_SRBS_POOL_SIZE); 4796 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 4797 phbdmu->phbdmu = (struct HBD_MessageUnit *)mem_base0; 4798 acb->rid[0] = rid0; 4799 } 4800 break; 4801 case ACB_ADAPTER_TYPE_E: { 4802 u_int32_t rid0 = PCIR_BAR(1); 4803 vm_offset_t mem_base0; 4804 4805 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4806 if(acb->sys_res_arcmsr[0] == NULL) { 4807 arcmsr_free_resource(acb); 4808 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4809 return ENOMEM; 4810 } 4811 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4812 arcmsr_free_resource(acb); 4813 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4814 return ENXIO; 4815 } 4816 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4817 if(mem_base0 == 0) { 4818 arcmsr_free_resource(acb); 4819 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4820 return ENXIO; 4821 } 4822 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4823 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4824 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4825 acb->doneq_index = 0; 4826 acb->in_doorbell = 0; 4827 acb->out_doorbell = 0; 4828 acb->rid[0] = rid0; 4829 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /*clear interrupt*/ 4830 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, ARCMSR_HBEMU_DOORBELL_SYNC); /* synchronize doorbell to 0 */ 4831 } 4832 break; 4833 case ACB_ADAPTER_TYPE_F: { 4834 u_int32_t rid0 = PCIR_BAR(0); 4835 vm_offset_t mem_base0; 4836 unsigned long host_buffer_dma; 4837 4838 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4839 if(acb->sys_res_arcmsr[0] == NULL) { 4840 arcmsr_free_resource(acb); 4841 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4842 return ENOMEM; 4843 } 4844 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4845 arcmsr_free_resource(acb); 4846 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4847 return ENXIO; 4848 } 4849 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4850 if(mem_base0 == 0) { 4851 arcmsr_free_resource(acb); 4852 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4853 return ENXIO; 4854 } 4855 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4856 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4857 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4858 acb->doneq_index = 0; 4859 acb->in_doorbell = 0; 4860 acb->out_doorbell = 0; 4861 acb->rid[0] = rid0; 4862 CHIP_REG_WRITE32(HBF_MessageUnit, 0, host_int_status, 0); /*clear interrupt*/ 4863 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, ARCMSR_HBEMU_DOORBELL_SYNC); /* synchronize doorbell to 0 */ 4864 arcmsr_wait_firmware_ready(acb); 4865 host_buffer_dma = acb->completeQ_phys + COMPLETION_Q_POOL_SIZE; 4866 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, (u_int32_t)(host_buffer_dma | 1)); /* host buffer low addr, bit0:1 all buffer active */ 4867 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr1, (u_int32_t)((host_buffer_dma >> 16) >> 16));/* host buffer high addr */ 4868 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, ARCMSR_HBFMU_DOORBELL_SYNC1); /* set host buffer physical address */ 4869 } 4870 break; 4871 } 4872 if(acb->acb_flags & ACB_F_MAPFREESRB_FAILD) { 4873 arcmsr_free_resource(acb); 4874 printf("arcmsr%d: map free srb failure!\n", device_get_unit(dev)); 4875 return ENXIO; 4876 } 4877 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_RQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ); 4878 acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER; 4879 /* 4880 ******************************************************************** 4881 ** init raid volume state 4882 ******************************************************************** 4883 */ 4884 for(i=0; i < ARCMSR_MAX_TARGETID; i++) { 4885 for(j=0; j < ARCMSR_MAX_TARGETLUN; j++) { 4886 acb->devstate[i][j] = ARECA_RAID_GONE; 4887 } 4888 } 4889 arcmsr_iop_init(acb); 4890 return(0); 4891 } 4892 4893 static int arcmsr_setup_msix(struct AdapterControlBlock *acb) 4894 { 4895 int i; 4896 4897 for (i = 0; i < acb->msix_vectors; i++) { 4898 acb->irq_id[i] = 1 + i; 4899 acb->irqres[i] = bus_alloc_resource_any(acb->pci_dev, 4900 SYS_RES_IRQ, &acb->irq_id[i], RF_ACTIVE); 4901 if (acb->irqres[i] == NULL) { 4902 printf("arcmsr: Can't allocate MSI-X resource\n"); 4903 goto irq_alloc_failed; 4904 } 4905 if (bus_setup_intr(acb->pci_dev, acb->irqres[i], 4906 INTR_MPSAFE | INTR_TYPE_CAM, NULL, arcmsr_intr_handler, 4907 acb, &acb->ih[i])) { 4908 printf("arcmsr: Cannot set up MSI-X interrupt handler\n"); 4909 goto irq_alloc_failed; 4910 } 4911 } 4912 printf("arcmsr: MSI-X INT enabled\n"); 4913 acb->acb_flags |= ACB_F_MSIX_ENABLED; 4914 return TRUE; 4915 4916 irq_alloc_failed: 4917 arcmsr_teardown_intr(acb->pci_dev, acb); 4918 return FALSE; 4919 } 4920 4921 /* 4922 ************************************************************************ 4923 ************************************************************************ 4924 */ 4925 static int arcmsr_attach(device_t dev) 4926 { 4927 struct make_dev_args args; 4928 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 4929 u_int32_t unit=device_get_unit(dev); 4930 struct ccb_setasync csa; 4931 struct cam_devq *devq; /* Device Queue to use for this SIM */ 4932 struct resource *irqres; 4933 4934 if(acb == NULL) { 4935 printf("arcmsr%d: cannot allocate softc\n", unit); 4936 return (ENOMEM); 4937 } 4938 arcmsr_mutex_init(acb); 4939 acb->pci_dev = dev; 4940 acb->pci_unit = unit; 4941 if(arcmsr_initialize(dev)) { 4942 printf("arcmsr%d: initialize failure!\n", unit); 4943 goto initialize_failed; 4944 } 4945 /* After setting up the adapter, map our interrupt */ 4946 acb->msix_vectors = ARCMSR_NUM_MSIX_VECTORS; 4947 if (pci_alloc_msix(dev, &acb->msix_vectors) == 0) { 4948 if (arcmsr_setup_msix(acb) == TRUE) 4949 goto irqx; 4950 } 4951 acb->irq_id[0] = 0; 4952 irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &acb->irq_id[0], RF_SHAREABLE | RF_ACTIVE); 4953 if(irqres == NULL || 4954 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, NULL, arcmsr_intr_handler, acb, &acb->ih[0])) { 4955 printf("arcmsr%d: unable to register interrupt handler!\n", unit); 4956 goto setup_intr_failed; 4957 } 4958 acb->irqres[0] = irqres; 4959 irqx: 4960 /* 4961 * Now let the CAM generic SCSI layer find the SCSI devices on 4962 * the bus * start queue to reset to the idle loop. * 4963 * Create device queue of SIM(s) * (MAX_START_JOB - 1) : 4964 * max_sim_transactions 4965 */ 4966 devq = cam_simq_alloc(acb->maxOutstanding); 4967 if(devq == NULL) { 4968 printf("arcmsr%d: cam_simq_alloc failure!\n", unit); 4969 goto simq_alloc_failed; 4970 } 4971 acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, &acb->isr_lock, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq); 4972 if(acb->psim == NULL) { 4973 printf("arcmsr%d: cam_sim_alloc failure!\n", unit); 4974 goto sim_alloc_failed; 4975 } 4976 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 4977 if(xpt_bus_register(acb->psim, dev, 0) != CAM_SUCCESS) { 4978 printf("arcmsr%d: xpt_bus_register failure!\n", unit); 4979 goto xpt_bus_failed; 4980 } 4981 if(xpt_create_path(&acb->ppath, /* periph */ NULL, cam_sim_path(acb->psim), CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 4982 printf("arcmsr%d: xpt_create_path failure!\n", unit); 4983 goto xpt_path_failed; 4984 } 4985 /* 4986 **************************************************** 4987 */ 4988 memset(&csa, 0, sizeof(csa)); 4989 xpt_setup_ccb(&csa.ccb_h, acb->ppath, /*priority*/5); 4990 csa.ccb_h.func_code = XPT_SASYNC_CB; 4991 csa.event_enable = AC_FOUND_DEVICE|AC_LOST_DEVICE; 4992 csa.callback = arcmsr_async; 4993 csa.callback_arg = acb->psim; 4994 xpt_action((union ccb *)&csa); 4995 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 4996 /* Create the control device. */ 4997 make_dev_args_init(&args); 4998 args.mda_devsw = &arcmsr_cdevsw; 4999 args.mda_uid = UID_ROOT; 5000 args.mda_gid = GID_WHEEL /* GID_OPERATOR */; 5001 args.mda_mode = S_IRUSR | S_IWUSR; 5002 args.mda_si_drv1 = acb; 5003 (void)make_dev_s(&args, &acb->ioctl_dev, "arcmsr%d", unit); 5004 5005 (void)make_dev_alias(acb->ioctl_dev, "arc%d", unit); 5006 arcmsr_callout_init(&acb->devmap_callout); 5007 callout_reset(&acb->devmap_callout, 60 * hz, arcmsr_polling_devmap, acb); 5008 return (0); 5009 xpt_path_failed: 5010 xpt_bus_deregister(cam_sim_path(acb->psim)); 5011 xpt_bus_failed: 5012 cam_sim_free(acb->psim, /* free_simq */ TRUE); 5013 sim_alloc_failed: 5014 cam_simq_free(devq); 5015 simq_alloc_failed: 5016 arcmsr_teardown_intr(dev, acb); 5017 setup_intr_failed: 5018 arcmsr_free_resource(acb); 5019 initialize_failed: 5020 arcmsr_mutex_destroy(acb); 5021 return ENXIO; 5022 } 5023 5024 /* 5025 ************************************************************************ 5026 ************************************************************************ 5027 */ 5028 static int arcmsr_probe(device_t dev) 5029 { 5030 u_int32_t id; 5031 u_int16_t sub_device_id; 5032 static char buf[256]; 5033 char x_type[]={"unknown"}; 5034 char *type; 5035 int raid6 = 1; 5036 5037 if (pci_get_vendor(dev) != PCI_VENDOR_ID_ARECA) { 5038 return (ENXIO); 5039 } 5040 sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); 5041 switch(id = pci_get_devid(dev)) { 5042 case PCIDevVenIDARC1110: 5043 case PCIDevVenIDARC1200: 5044 case PCIDevVenIDARC1201: 5045 case PCIDevVenIDARC1210: 5046 raid6 = 0; 5047 /*FALLTHRU*/ 5048 case PCIDevVenIDARC1120: 5049 case PCIDevVenIDARC1130: 5050 case PCIDevVenIDARC1160: 5051 case PCIDevVenIDARC1170: 5052 case PCIDevVenIDARC1220: 5053 case PCIDevVenIDARC1230: 5054 case PCIDevVenIDARC1231: 5055 case PCIDevVenIDARC1260: 5056 case PCIDevVenIDARC1261: 5057 case PCIDevVenIDARC1270: 5058 case PCIDevVenIDARC1280: 5059 type = "SATA 3G"; 5060 break; 5061 case PCIDevVenIDARC1212: 5062 case PCIDevVenIDARC1222: 5063 case PCIDevVenIDARC1380: 5064 case PCIDevVenIDARC1381: 5065 case PCIDevVenIDARC1680: 5066 case PCIDevVenIDARC1681: 5067 type = "SAS 3G"; 5068 break; 5069 case PCIDevVenIDARC1880: 5070 case PCIDevVenIDARC1882: 5071 case PCIDevVenIDARC1213: 5072 case PCIDevVenIDARC1223: 5073 if ((sub_device_id == ARECA_SUB_DEV_ID_1883) || 5074 (sub_device_id == ARECA_SUB_DEV_ID_1216) || 5075 (sub_device_id == ARECA_SUB_DEV_ID_1226)) 5076 type = "SAS 12G"; 5077 else 5078 type = "SAS 6G"; 5079 break; 5080 case PCIDevVenIDARC1884: 5081 type = "SAS 12G"; 5082 break; 5083 case PCIDevVenIDARC1886_: 5084 case PCIDevVenIDARC1886: 5085 type = "NVME,SAS-12G,SATA-6G"; 5086 break; 5087 case PCIDevVenIDARC1214: 5088 case PCIDevVenIDARC1203: 5089 type = "SATA 6G"; 5090 break; 5091 default: 5092 type = x_type; 5093 raid6 = 0; 5094 break; 5095 } 5096 if(type == x_type) 5097 return(ENXIO); 5098 sprintf(buf, "Areca %s Host Adapter RAID Controller %s\n%s\n", 5099 type, raid6 ? "(RAID6 capable)" : "", ARCMSR_DRIVER_VERSION); 5100 device_set_desc_copy(dev, buf); 5101 return (BUS_PROBE_DEFAULT); 5102 } 5103 /* 5104 ************************************************************************ 5105 ************************************************************************ 5106 */ 5107 static int arcmsr_shutdown(device_t dev) 5108 { 5109 u_int32_t i; 5110 struct CommandControlBlock *srb; 5111 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 5112 5113 /* stop adapter background rebuild */ 5114 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 5115 /* disable all outbound interrupt */ 5116 arcmsr_disable_allintr(acb); 5117 arcmsr_stop_adapter_bgrb(acb); 5118 arcmsr_flush_adapter_cache(acb); 5119 /* abort all outstanding command */ 5120 acb->acb_flags |= ACB_F_SCSISTOPADAPTER; 5121 acb->acb_flags &= ~ACB_F_IOP_INITED; 5122 if(acb->srboutstandingcount != 0) { 5123 /*clear and abort all outbound posted Q*/ 5124 arcmsr_done4abort_postqueue(acb); 5125 /* talk to iop 331 outstanding command aborted*/ 5126 arcmsr_abort_allcmd(acb); 5127 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 5128 srb = acb->psrb_pool[i]; 5129 if(srb->srb_state == ARCMSR_SRB_START) { 5130 srb->srb_state = ARCMSR_SRB_ABORTED; 5131 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 5132 arcmsr_srb_complete(srb, 1); 5133 } 5134 } 5135 } 5136 acb->srboutstandingcount = 0; 5137 acb->workingsrb_doneindex = 0; 5138 acb->workingsrb_startindex = 0; 5139 acb->pktRequestCount = 0; 5140 acb->pktReturnCount = 0; 5141 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 5142 return (0); 5143 } 5144 /* 5145 ************************************************************************ 5146 ************************************************************************ 5147 */ 5148 static void arcmsr_teardown_intr(device_t dev, struct AdapterControlBlock *acb) 5149 { 5150 int i; 5151 5152 if (acb->acb_flags & ACB_F_MSIX_ENABLED) { 5153 for (i = 0; i < acb->msix_vectors; i++) { 5154 if (acb->ih[i]) 5155 bus_teardown_intr(dev, acb->irqres[i], acb->ih[i]); 5156 if (acb->irqres[i] != NULL) 5157 bus_release_resource(dev, SYS_RES_IRQ, 5158 acb->irq_id[i], acb->irqres[i]); 5159 5160 acb->ih[i] = NULL; 5161 } 5162 pci_release_msi(dev); 5163 } else { 5164 if (acb->ih[0]) 5165 bus_teardown_intr(dev, acb->irqres[0], acb->ih[0]); 5166 if (acb->irqres[0] != NULL) 5167 bus_release_resource(dev, SYS_RES_IRQ, 5168 acb->irq_id[0], acb->irqres[0]); 5169 acb->ih[0] = NULL; 5170 } 5171 5172 } 5173 /* 5174 ************************************************************************ 5175 ************************************************************************ 5176 */ 5177 static int arcmsr_detach(device_t dev) 5178 { 5179 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 5180 int i; 5181 5182 callout_stop(&acb->devmap_callout); 5183 arcmsr_teardown_intr(dev, acb); 5184 arcmsr_shutdown(dev); 5185 arcmsr_free_resource(acb); 5186 for(i=0; (acb->sys_res_arcmsr[i]!=NULL) && (i<2); i++) { 5187 bus_release_resource(dev, SYS_RES_MEMORY, acb->rid[i], acb->sys_res_arcmsr[i]); 5188 } 5189 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 5190 xpt_async(AC_LOST_DEVICE, acb->ppath, NULL); 5191 xpt_free_path(acb->ppath); 5192 xpt_bus_deregister(cam_sim_path(acb->psim)); 5193 cam_sim_free(acb->psim, TRUE); 5194 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 5195 arcmsr_mutex_destroy(acb); 5196 return (0); 5197 } 5198 5199 #ifdef ARCMSR_DEBUG1 5200 static void arcmsr_dump_data(struct AdapterControlBlock *acb) 5201 { 5202 if((acb->pktRequestCount - acb->pktReturnCount) == 0) 5203 return; 5204 printf("Command Request Count =0x%x\n",acb->pktRequestCount); 5205 printf("Command Return Count =0x%x\n",acb->pktReturnCount); 5206 printf("Command (Req-Rtn) Count =0x%x\n",(acb->pktRequestCount - acb->pktReturnCount)); 5207 printf("Queued Command Count =0x%x\n",acb->srboutstandingcount); 5208 } 5209 #endif 5210