1 /* 2 ***************************************************************************************** 3 ** O.S : FreeBSD 4 ** FILE NAME : arcmsr.c 5 ** BY : Erich Chen, Ching Huang 6 ** Description: SCSI RAID Device Driver for 7 ** ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x) SATA/SAS RAID HOST Adapter 8 ** ARCMSR RAID Host adapter 9 ** [RAID controller:INTEL 331(PCI-X) 341(PCI-EXPRESS) chip set] 10 ****************************************************************************************** 11 ************************************************************************ 12 ** 13 ** Copyright (c) 2004-2010 ARECA Co. Ltd. 14 ** Erich Chen, Taipei Taiwan All rights reserved. 15 ** 16 ** Redistribution and use in source and binary forms, with or without 17 ** modification, are permitted provided that the following conditions 18 ** are met: 19 ** 1. Redistributions of source code must retain the above copyright 20 ** notice, this list of conditions and the following disclaimer. 21 ** 2. Redistributions in binary form must reproduce the above copyright 22 ** notice, this list of conditions and the following disclaimer in the 23 ** documentation and/or other materials provided with the distribution. 24 ** 3. The name of the author may not be used to endorse or promote products 25 ** derived from this software without specific prior written permission. 26 ** 27 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 28 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 29 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 31 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT 32 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 34 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 36 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 ************************************************************************** 38 ** History 39 ** 40 ** REV# DATE NAME DESCRIPTION 41 ** 1.00.00.00 03/31/2004 Erich Chen First release 42 ** 1.20.00.02 11/29/2004 Erich Chen bug fix with arcmsr_bus_reset when PHY error 43 ** 1.20.00.03 04/19/2005 Erich Chen add SATA 24 Ports adapter type support 44 ** clean unused function 45 ** 1.20.00.12 09/12/2005 Erich Chen bug fix with abort command handling, 46 ** firmware version check 47 ** and firmware update notify for hardware bug fix 48 ** handling if none zero high part physical address 49 ** of srb resource 50 ** 1.20.00.13 08/18/2006 Erich Chen remove pending srb and report busy 51 ** add iop message xfer 52 ** with scsi pass-through command 53 ** add new device id of sas raid adapters 54 ** code fit for SPARC64 & PPC 55 ** 1.20.00.14 02/05/2007 Erich Chen bug fix for incorrect ccb_h.status report 56 ** and cause g_vfs_done() read write error 57 ** 1.20.00.15 10/10/2007 Erich Chen support new RAID adapter type ARC120x 58 ** 1.20.00.16 10/10/2009 Erich Chen Bug fix for RAID adapter type ARC120x 59 ** bus_dmamem_alloc() with BUS_DMA_ZERO 60 ** 1.20.00.17 07/15/2010 Ching Huang Added support ARC1880 61 ** report CAM_DEV_NOT_THERE instead of CAM_SEL_TIMEOUT when device failed, 62 ** prevent cam_periph_error removing all LUN devices of one Target id 63 ** for any one LUN device failed 64 ** 1.20.00.18 10/14/2010 Ching Huang Fixed "inquiry data fails comparion at DV1 step" 65 ** 10/25/2010 Ching Huang Fixed bad range input in bus_alloc_resource for ADAPTER_TYPE_B 66 ** 1.20.00.19 11/11/2010 Ching Huang Fixed arcmsr driver prevent arcsas support for Areca SAS HBA ARC13x0 67 ** 1.20.00.20 12/08/2010 Ching Huang Avoid calling atomic_set_int function 68 ** 1.20.00.21 02/08/2011 Ching Huang Implement I/O request timeout 69 ** 02/14/2011 Ching Huang Modified pktRequestCount 70 ** 1.20.00.21 03/03/2011 Ching Huang if a command timeout, then wait its ccb back before free it 71 ****************************************************************************************** 72 * $FreeBSD$ 73 */ 74 #if 0 75 #define ARCMSR_DEBUG1 1 76 #endif 77 #include <sys/param.h> 78 #include <sys/systm.h> 79 #include <sys/malloc.h> 80 #include <sys/kernel.h> 81 #include <sys/bus.h> 82 #include <sys/queue.h> 83 #include <sys/stat.h> 84 #include <sys/devicestat.h> 85 #include <sys/kthread.h> 86 #include <sys/module.h> 87 #include <sys/proc.h> 88 #include <sys/lock.h> 89 #include <sys/sysctl.h> 90 #include <sys/poll.h> 91 #include <sys/ioccom.h> 92 #include <vm/vm.h> 93 #include <vm/vm_param.h> 94 #include <vm/pmap.h> 95 96 #include <isa/rtc.h> 97 98 #include <machine/bus.h> 99 #include <machine/resource.h> 100 #include <machine/atomic.h> 101 #include <sys/conf.h> 102 #include <sys/rman.h> 103 104 #include <cam/cam.h> 105 #include <cam/cam_ccb.h> 106 #include <cam/cam_sim.h> 107 #include <cam/cam_periph.h> 108 #include <cam/cam_xpt_periph.h> 109 #include <cam/cam_xpt_sim.h> 110 #include <cam/cam_debug.h> 111 #include <cam/scsi/scsi_all.h> 112 #include <cam/scsi/scsi_message.h> 113 /* 114 ************************************************************************** 115 ************************************************************************** 116 */ 117 #if __FreeBSD_version >= 500005 118 #include <sys/selinfo.h> 119 #include <sys/mutex.h> 120 #include <sys/endian.h> 121 #include <dev/pci/pcivar.h> 122 #include <dev/pci/pcireg.h> 123 #define ARCMSR_LOCK_INIT(l, s) mtx_init(l, s, NULL, MTX_DEF) 124 #define ARCMSR_LOCK_DESTROY(l) mtx_destroy(l) 125 #define ARCMSR_LOCK_ACQUIRE(l) mtx_lock(l) 126 #define ARCMSR_LOCK_RELEASE(l) mtx_unlock(l) 127 #define ARCMSR_LOCK_TRY(l) mtx_trylock(l) 128 #define arcmsr_htole32(x) htole32(x) 129 typedef struct mtx arcmsr_lock_t; 130 #else 131 #include <sys/select.h> 132 #include <pci/pcivar.h> 133 #include <pci/pcireg.h> 134 #define ARCMSR_LOCK_INIT(l, s) simple_lock_init(l) 135 #define ARCMSR_LOCK_DESTROY(l) 136 #define ARCMSR_LOCK_ACQUIRE(l) simple_lock(l) 137 #define ARCMSR_LOCK_RELEASE(l) simple_unlock(l) 138 #define ARCMSR_LOCK_TRY(l) simple_lock_try(l) 139 #define arcmsr_htole32(x) (x) 140 typedef struct simplelock arcmsr_lock_t; 141 #endif 142 143 #if !defined(CAM_NEW_TRAN_CODE) && __FreeBSD_version >= 700025 144 #define CAM_NEW_TRAN_CODE 1 145 #endif 146 147 #if __FreeBSD_version > 500000 148 #define arcmsr_callout_init(a) callout_init(a, /*mpsafe*/1); 149 #else 150 #define arcmsr_callout_init(a) callout_init(a); 151 #endif 152 153 #define ARCMSR_DRIVER_VERSION "Driver Version 1.20.00.21 2010-03-03" 154 #include <dev/arcmsr/arcmsr.h> 155 #define SRB_SIZE ((sizeof(struct CommandControlBlock)+0x1f) & 0xffe0) 156 #define ARCMSR_SRBS_POOL_SIZE (SRB_SIZE * ARCMSR_MAX_FREESRB_NUM) 157 /* 158 ************************************************************************** 159 ************************************************************************** 160 */ 161 #define CHIP_REG_READ32(s, b, r) bus_space_read_4(acb->btag[b], acb->bhandle[b], offsetof(struct s, r)) 162 #define CHIP_REG_WRITE32(s, b, r, d) bus_space_write_4(acb->btag[b], acb->bhandle[b], offsetof(struct s, r), d) 163 /* 164 ************************************************************************** 165 ************************************************************************** 166 */ 167 static void arcmsr_free_srb(struct CommandControlBlock *srb); 168 static struct CommandControlBlock * arcmsr_get_freesrb(struct AdapterControlBlock *acb); 169 static u_int8_t arcmsr_seek_cmd2abort(union ccb * abortccb); 170 static int arcmsr_probe(device_t dev); 171 static int arcmsr_attach(device_t dev); 172 static int arcmsr_detach(device_t dev); 173 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg); 174 static void arcmsr_iop_parking(struct AdapterControlBlock *acb); 175 static int arcmsr_shutdown(device_t dev); 176 static void arcmsr_interrupt(struct AdapterControlBlock *acb); 177 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb); 178 static void arcmsr_free_resource(struct AdapterControlBlock *acb); 179 static void arcmsr_bus_reset(struct AdapterControlBlock *acb); 180 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb); 181 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb); 182 static void arcmsr_iop_init(struct AdapterControlBlock *acb); 183 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb); 184 static void arcmsr_post_ioctldata2iop(struct AdapterControlBlock *acb); 185 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb); 186 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag); 187 static void arcmsr_iop_reset(struct AdapterControlBlock *acb); 188 static void arcmsr_report_sense_info(struct CommandControlBlock *srb); 189 static void arcmsr_build_srb(struct CommandControlBlock *srb, bus_dma_segment_t * dm_segs, u_int32_t nseg); 190 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb * pccb); 191 static int arcmsr_resume(device_t dev); 192 static int arcmsr_suspend(device_t dev); 193 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb); 194 static void arcmsr_polling_devmap(void* arg); 195 static void arcmsr_srb_timeout(void* arg); 196 #ifdef ARCMSR_DEBUG1 197 static void arcmsr_dump_data(struct AdapterControlBlock *acb); 198 #endif 199 /* 200 ************************************************************************** 201 ************************************************************************** 202 */ 203 static void UDELAY(u_int32_t us) { DELAY(us); } 204 /* 205 ************************************************************************** 206 ************************************************************************** 207 */ 208 static bus_dmamap_callback_t arcmsr_map_free_srb; 209 static bus_dmamap_callback_t arcmsr_execute_srb; 210 /* 211 ************************************************************************** 212 ************************************************************************** 213 */ 214 static d_open_t arcmsr_open; 215 static d_close_t arcmsr_close; 216 static d_ioctl_t arcmsr_ioctl; 217 218 static device_method_t arcmsr_methods[]={ 219 DEVMETHOD(device_probe, arcmsr_probe), 220 DEVMETHOD(device_attach, arcmsr_attach), 221 DEVMETHOD(device_detach, arcmsr_detach), 222 DEVMETHOD(device_shutdown, arcmsr_shutdown), 223 DEVMETHOD(device_suspend, arcmsr_suspend), 224 DEVMETHOD(device_resume, arcmsr_resume), 225 DEVMETHOD(bus_print_child, bus_generic_print_child), 226 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 227 { 0, 0 } 228 }; 229 230 static driver_t arcmsr_driver={ 231 "arcmsr", arcmsr_methods, sizeof(struct AdapterControlBlock) 232 }; 233 234 static devclass_t arcmsr_devclass; 235 DRIVER_MODULE(arcmsr, pci, arcmsr_driver, arcmsr_devclass, 0, 0); 236 MODULE_DEPEND(arcmsr, pci, 1, 1, 1); 237 MODULE_DEPEND(arcmsr, cam, 1, 1, 1); 238 #ifndef BUS_DMA_COHERENT 239 #define BUS_DMA_COHERENT 0x04 /* hint: map memory in a coherent way */ 240 #endif 241 #if __FreeBSD_version >= 501000 242 static struct cdevsw arcmsr_cdevsw={ 243 #if __FreeBSD_version >= 503000 244 .d_version = D_VERSION, 245 #endif 246 #if (__FreeBSD_version>=503000 && __FreeBSD_version<600034) 247 .d_flags = D_NEEDGIANT, 248 #endif 249 .d_open = arcmsr_open, /* open */ 250 .d_close = arcmsr_close, /* close */ 251 .d_ioctl = arcmsr_ioctl, /* ioctl */ 252 .d_name = "arcmsr", /* name */ 253 }; 254 #else 255 #define ARCMSR_CDEV_MAJOR 180 256 257 static struct cdevsw arcmsr_cdevsw = { 258 arcmsr_open, /* open */ 259 arcmsr_close, /* close */ 260 noread, /* read */ 261 nowrite, /* write */ 262 arcmsr_ioctl, /* ioctl */ 263 nopoll, /* poll */ 264 nommap, /* mmap */ 265 nostrategy, /* strategy */ 266 "arcmsr", /* name */ 267 ARCMSR_CDEV_MAJOR, /* major */ 268 nodump, /* dump */ 269 nopsize, /* psize */ 270 0 /* flags */ 271 }; 272 #endif 273 /* 274 ************************************************************************** 275 ************************************************************************** 276 */ 277 #if __FreeBSD_version < 500005 278 static int arcmsr_open(dev_t dev, int flags, int fmt, struct proc *proc) 279 #else 280 #if __FreeBSD_version < 503000 281 static int arcmsr_open(dev_t dev, int flags, int fmt, struct thread *proc) 282 #else 283 static int arcmsr_open(struct cdev *dev, int flags, int fmt, struct thread *proc) 284 #endif 285 #endif 286 { 287 #if __FreeBSD_version < 503000 288 struct AdapterControlBlock *acb=dev->si_drv1; 289 #else 290 int unit = dev2unit(dev); 291 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit); 292 #endif 293 if(acb==NULL) { 294 return ENXIO; 295 } 296 return 0; 297 } 298 /* 299 ************************************************************************** 300 ************************************************************************** 301 */ 302 #if __FreeBSD_version < 500005 303 static int arcmsr_close(dev_t dev, int flags, int fmt, struct proc *proc) 304 #else 305 #if __FreeBSD_version < 503000 306 static int arcmsr_close(dev_t dev, int flags, int fmt, struct thread *proc) 307 #else 308 static int arcmsr_close(struct cdev *dev, int flags, int fmt, struct thread *proc) 309 #endif 310 #endif 311 { 312 #if __FreeBSD_version < 503000 313 struct AdapterControlBlock *acb=dev->si_drv1; 314 #else 315 int unit = dev2unit(dev); 316 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit); 317 #endif 318 if(acb==NULL) { 319 return ENXIO; 320 } 321 return 0; 322 } 323 /* 324 ************************************************************************** 325 ************************************************************************** 326 */ 327 #if __FreeBSD_version < 500005 328 static int arcmsr_ioctl(dev_t dev, u_long ioctl_cmd, caddr_t arg, int flags, struct proc *proc) 329 #else 330 #if __FreeBSD_version < 503000 331 static int arcmsr_ioctl(dev_t dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc) 332 #else 333 static int arcmsr_ioctl(struct cdev *dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc) 334 #endif 335 #endif 336 { 337 #if __FreeBSD_version < 503000 338 struct AdapterControlBlock *acb=dev->si_drv1; 339 #else 340 int unit = dev2unit(dev); 341 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit); 342 #endif 343 344 if(acb==NULL) { 345 return ENXIO; 346 } 347 return(arcmsr_iop_ioctlcmd(acb, ioctl_cmd, arg)); 348 } 349 /* 350 ********************************************************************** 351 ********************************************************************** 352 */ 353 static u_int32_t arcmsr_disable_allintr( struct AdapterControlBlock *acb) 354 { 355 u_int32_t intmask_org=0; 356 357 switch (acb->adapter_type) { 358 case ACB_ADAPTER_TYPE_A: { 359 /* disable all outbound interrupt */ 360 intmask_org=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intmask); /* disable outbound message0 int */ 361 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE); 362 } 363 break; 364 case ACB_ADAPTER_TYPE_B: { 365 /* disable all outbound interrupt */ 366 intmask_org=CHIP_REG_READ32(HBB_DOORBELL, 367 0, iop2drv_doorbell_mask) & (~ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); /* disable outbound message0 int */ 368 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell_mask, 0); /* disable all interrupt */ 369 } 370 break; 371 case ACB_ADAPTER_TYPE_C: { 372 /* disable all outbound interrupt */ 373 intmask_org=CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask) ; /* disable outbound message0 int */ 374 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE); 375 } 376 break; 377 } 378 return(intmask_org); 379 } 380 /* 381 ********************************************************************** 382 ********************************************************************** 383 */ 384 static void arcmsr_enable_allintr( struct AdapterControlBlock *acb, u_int32_t intmask_org) 385 { 386 u_int32_t mask; 387 388 switch (acb->adapter_type) { 389 case ACB_ADAPTER_TYPE_A: { 390 /* enable outbound Post Queue, outbound doorbell Interrupt */ 391 mask=~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE|ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE); 392 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org & mask); 393 acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff; 394 } 395 break; 396 case ACB_ADAPTER_TYPE_B: { 397 /* enable ARCMSR_IOP2DRV_MESSAGE_CMD_DONE */ 398 mask=(ARCMSR_IOP2DRV_DATA_WRITE_OK|ARCMSR_IOP2DRV_DATA_READ_OK|ARCMSR_IOP2DRV_CDB_DONE|ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); 399 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell_mask, intmask_org | mask); /*1=interrupt enable, 0=interrupt disable*/ 400 acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f; 401 } 402 break; 403 case ACB_ADAPTER_TYPE_C: { 404 /* enable outbound Post Queue, outbound doorbell Interrupt */ 405 mask=~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK); 406 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org & mask); 407 acb->outbound_int_enable= ~(intmask_org & mask) & 0x0000000f; 408 } 409 break; 410 } 411 return; 412 } 413 /* 414 ********************************************************************** 415 ********************************************************************** 416 */ 417 static u_int8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb) 418 { 419 u_int32_t Index; 420 u_int8_t Retries=0x00; 421 422 do { 423 for(Index=0; Index < 100; Index++) { 424 if(CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { 425 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);/*clear interrupt*/ 426 return TRUE; 427 } 428 UDELAY(10000); 429 }/*max 1 seconds*/ 430 }while(Retries++ < 20);/*max 20 sec*/ 431 return FALSE; 432 } 433 /* 434 ********************************************************************** 435 ********************************************************************** 436 */ 437 static u_int8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb) 438 { 439 u_int32_t Index; 440 u_int8_t Retries=0x00; 441 442 do { 443 for(Index=0; Index < 100; Index++) { 444 if(CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) { 445 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt*/ 446 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 447 return TRUE; 448 } 449 UDELAY(10000); 450 }/*max 1 seconds*/ 451 }while(Retries++ < 20);/*max 20 sec*/ 452 return FALSE; 453 } 454 /* 455 ********************************************************************** 456 ********************************************************************** 457 */ 458 static u_int8_t arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock *acb) 459 { 460 u_int32_t Index; 461 u_int8_t Retries=0x00; 462 463 do { 464 for(Index=0; Index < 100; Index++) { 465 if(CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 466 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);/*clear interrupt*/ 467 return TRUE; 468 } 469 UDELAY(10000); 470 }/*max 1 seconds*/ 471 }while(Retries++ < 20);/*max 20 sec*/ 472 return FALSE; 473 } 474 /* 475 ************************************************************************ 476 ************************************************************************ 477 */ 478 static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb) 479 { 480 int retry_count=30;/* enlarge wait flush adapter cache time: 10 minute */ 481 482 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 483 do { 484 if(arcmsr_hba_wait_msgint_ready(acb)) { 485 break; 486 } else { 487 retry_count--; 488 } 489 }while(retry_count!=0); 490 return; 491 } 492 /* 493 ************************************************************************ 494 ************************************************************************ 495 */ 496 static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb) 497 { 498 int retry_count=30;/* enlarge wait flush adapter cache time: 10 minute */ 499 500 CHIP_REG_WRITE32(HBB_DOORBELL, 501 0, drv2iop_doorbell, ARCMSR_MESSAGE_FLUSH_CACHE); 502 do { 503 if(arcmsr_hbb_wait_msgint_ready(acb)) { 504 break; 505 } else { 506 retry_count--; 507 } 508 }while(retry_count!=0); 509 return; 510 } 511 /* 512 ************************************************************************ 513 ************************************************************************ 514 */ 515 static void arcmsr_flush_hbc_cache(struct AdapterControlBlock *acb) 516 { 517 int retry_count=30;/* enlarge wait flush adapter cache time: 10 minute */ 518 519 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 520 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 521 do { 522 if(arcmsr_hbc_wait_msgint_ready(acb)) { 523 break; 524 } else { 525 retry_count--; 526 } 527 }while(retry_count!=0); 528 return; 529 } 530 /* 531 ************************************************************************ 532 ************************************************************************ 533 */ 534 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb) 535 { 536 switch (acb->adapter_type) { 537 case ACB_ADAPTER_TYPE_A: { 538 arcmsr_flush_hba_cache(acb); 539 } 540 break; 541 case ACB_ADAPTER_TYPE_B: { 542 arcmsr_flush_hbb_cache(acb); 543 } 544 break; 545 case ACB_ADAPTER_TYPE_C: { 546 arcmsr_flush_hbc_cache(acb); 547 } 548 break; 549 } 550 return; 551 } 552 /* 553 ******************************************************************************* 554 ******************************************************************************* 555 */ 556 static int arcmsr_suspend(device_t dev) 557 { 558 struct AdapterControlBlock *acb = device_get_softc(dev); 559 560 /* flush controller */ 561 arcmsr_iop_parking(acb); 562 /* disable all outbound interrupt */ 563 arcmsr_disable_allintr(acb); 564 return(0); 565 } 566 /* 567 ******************************************************************************* 568 ******************************************************************************* 569 */ 570 static int arcmsr_resume(device_t dev) 571 { 572 struct AdapterControlBlock *acb = device_get_softc(dev); 573 574 arcmsr_iop_init(acb); 575 return(0); 576 } 577 /* 578 ********************************************************************************* 579 ********************************************************************************* 580 */ 581 static void arcmsr_async(void *cb_arg, u_int32_t code, struct cam_path *path, void *arg) 582 { 583 struct AdapterControlBlock *acb; 584 u_int8_t target_id, target_lun; 585 struct cam_sim * sim; 586 587 sim=(struct cam_sim *) cb_arg; 588 acb =(struct AdapterControlBlock *) cam_sim_softc(sim); 589 switch (code) { 590 case AC_LOST_DEVICE: 591 target_id=xpt_path_target_id(path); 592 target_lun=xpt_path_lun_id(path); 593 if((target_id > ARCMSR_MAX_TARGETID) || (target_lun > ARCMSR_MAX_TARGETLUN)) { 594 break; 595 } 596 printf("%s:scsi id=%d lun=%d device lost \n", device_get_name(acb->pci_dev), target_id, target_lun); 597 break; 598 default: 599 break; 600 } 601 } 602 /* 603 ********************************************************************** 604 ********************************************************************** 605 */ 606 static void arcmsr_report_sense_info(struct CommandControlBlock *srb) 607 { 608 union ccb * pccb=srb->pccb; 609 610 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 611 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 612 if(&pccb->csio.sense_data) { 613 memset(&pccb->csio.sense_data, 0, sizeof(pccb->csio.sense_data)); 614 memcpy(&pccb->csio.sense_data, srb->arcmsr_cdb.SenseData, 615 get_min(sizeof(struct SENSE_DATA), sizeof(pccb->csio.sense_data))); 616 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); /* Valid,ErrorCode */ 617 pccb->ccb_h.status |= CAM_AUTOSNS_VALID; 618 } 619 return; 620 } 621 /* 622 ********************************************************************* 623 ********************************************************************* 624 */ 625 static void arcmsr_abort_hba_allcmd(struct AdapterControlBlock *acb) 626 { 627 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 628 if(!arcmsr_hba_wait_msgint_ready(acb)) { 629 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 630 } 631 return; 632 } 633 /* 634 ********************************************************************* 635 ********************************************************************* 636 */ 637 static void arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb) 638 { 639 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_ABORT_CMD); 640 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 641 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 642 } 643 return; 644 } 645 /* 646 ********************************************************************* 647 ********************************************************************* 648 */ 649 static void arcmsr_abort_hbc_allcmd(struct AdapterControlBlock *acb) 650 { 651 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 652 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 653 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 654 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 655 } 656 return; 657 } 658 /* 659 ********************************************************************* 660 ********************************************************************* 661 */ 662 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb) 663 { 664 switch (acb->adapter_type) { 665 case ACB_ADAPTER_TYPE_A: { 666 arcmsr_abort_hba_allcmd(acb); 667 } 668 break; 669 case ACB_ADAPTER_TYPE_B: { 670 arcmsr_abort_hbb_allcmd(acb); 671 } 672 break; 673 case ACB_ADAPTER_TYPE_C: { 674 arcmsr_abort_hbc_allcmd(acb); 675 } 676 break; 677 } 678 return; 679 } 680 /* 681 ********************************************************************** 682 ********************************************************************** 683 */ 684 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag) 685 { 686 struct AdapterControlBlock *acb=srb->acb; 687 union ccb * pccb=srb->pccb; 688 689 if(srb->srb_flags & SRB_FLAG_TIMER_START) 690 callout_stop(&srb->ccb_callout); 691 if((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 692 bus_dmasync_op_t op; 693 694 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 695 op = BUS_DMASYNC_POSTREAD; 696 } else { 697 op = BUS_DMASYNC_POSTWRITE; 698 } 699 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op); 700 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap); 701 } 702 if(stand_flag==1) { 703 atomic_subtract_int(&acb->srboutstandingcount, 1); 704 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) && ( 705 acb->srboutstandingcount < ARCMSR_RELEASE_SIMQ_LEVEL)) { 706 acb->acb_flags &= ~ACB_F_CAM_DEV_QFRZN; 707 pccb->ccb_h.status |= CAM_RELEASE_SIMQ; 708 } 709 } 710 if(srb->srb_state != ARCMSR_SRB_TIMEOUT) 711 arcmsr_free_srb(srb); 712 #ifdef ARCMSR_DEBUG1 713 acb->pktReturnCount++; 714 #endif 715 xpt_done(pccb); 716 return; 717 } 718 /* 719 ************************************************************************** 720 ************************************************************************** 721 */ 722 static void arcmsr_report_srb_state(struct AdapterControlBlock *acb, struct CommandControlBlock *srb, u_int16_t error) 723 { 724 int target, lun; 725 726 target=srb->pccb->ccb_h.target_id; 727 lun=srb->pccb->ccb_h.target_lun; 728 if(error == FALSE) { 729 if(acb->devstate[target][lun]==ARECA_RAID_GONE) { 730 acb->devstate[target][lun]=ARECA_RAID_GOOD; 731 } 732 srb->pccb->ccb_h.status |= CAM_REQ_CMP; 733 arcmsr_srb_complete(srb, 1); 734 } else { 735 switch(srb->arcmsr_cdb.DeviceStatus) { 736 case ARCMSR_DEV_SELECT_TIMEOUT: { 737 if(acb->devstate[target][lun]==ARECA_RAID_GOOD) { 738 printf( "arcmsr%d: Target=%x, Lun=%x, selection timeout, raid volume was lost\n", acb->pci_unit, target, lun); 739 } 740 acb->devstate[target][lun]=ARECA_RAID_GONE; 741 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 742 arcmsr_srb_complete(srb, 1); 743 } 744 break; 745 case ARCMSR_DEV_ABORTED: 746 case ARCMSR_DEV_INIT_FAIL: { 747 acb->devstate[target][lun]=ARECA_RAID_GONE; 748 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 749 arcmsr_srb_complete(srb, 1); 750 } 751 break; 752 case SCSISTAT_CHECK_CONDITION: { 753 acb->devstate[target][lun]=ARECA_RAID_GOOD; 754 arcmsr_report_sense_info(srb); 755 arcmsr_srb_complete(srb, 1); 756 } 757 break; 758 default: 759 printf("arcmsr%d: scsi id=%d lun=%d isr got command error done,but got unknow DeviceStatus=0x%x \n" 760 , acb->pci_unit, target, lun ,srb->arcmsr_cdb.DeviceStatus); 761 acb->devstate[target][lun]=ARECA_RAID_GONE; 762 srb->pccb->ccb_h.status |= CAM_UNCOR_PARITY; 763 /*unknow error or crc error just for retry*/ 764 arcmsr_srb_complete(srb, 1); 765 break; 766 } 767 } 768 return; 769 } 770 /* 771 ************************************************************************** 772 ************************************************************************** 773 */ 774 static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, u_int32_t flag_srb, u_int16_t error) 775 { 776 struct CommandControlBlock *srb; 777 778 /* check if command done with no error*/ 779 switch (acb->adapter_type) { 780 case ACB_ADAPTER_TYPE_C: 781 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/ 782 break; 783 case ACB_ADAPTER_TYPE_A: 784 case ACB_ADAPTER_TYPE_B: 785 default: 786 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 787 break; 788 } 789 if((srb->acb!=acb) || (srb->srb_state!=ARCMSR_SRB_START)) { 790 if(srb->srb_state == ARCMSR_SRB_TIMEOUT) { 791 arcmsr_free_srb(srb); 792 printf("arcmsr%d: srb='%p' return srb has been timeouted\n", acb->pci_unit, srb); 793 return; 794 } 795 printf("arcmsr%d: return srb has been completed\n" 796 "srb='%p' srb_state=0x%x outstanding srb count=%d \n", 797 acb->pci_unit, srb, srb->srb_state, acb->srboutstandingcount); 798 return; 799 } 800 arcmsr_report_srb_state(acb, srb, error); 801 return; 802 } 803 /* 804 ************************************************************************** 805 ************************************************************************** 806 */ 807 static void arcmsr_srb_timeout(void* arg) 808 { 809 struct CommandControlBlock *srb = (struct CommandControlBlock *)arg; 810 struct AdapterControlBlock *acb; 811 int target, lun; 812 u_int8_t cmd; 813 814 target=srb->pccb->ccb_h.target_id; 815 lun=srb->pccb->ccb_h.target_lun; 816 acb = srb->acb; 817 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 818 if(srb->srb_state == ARCMSR_SRB_START) 819 { 820 cmd = srb->pccb->csio.cdb_io.cdb_bytes[0]; 821 srb->srb_state = ARCMSR_SRB_TIMEOUT; 822 srb->pccb->ccb_h.status |= CAM_CMD_TIMEOUT; 823 arcmsr_srb_complete(srb, 1); 824 printf("arcmsr%d: scsi id %d lun %d cmd=0x%x srb='%p' ccb command time out!\n", 825 acb->pci_unit, target, lun, cmd, srb); 826 } 827 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 828 #ifdef ARCMSR_DEBUG1 829 arcmsr_dump_data(acb); 830 #endif 831 } 832 833 /* 834 ********************************************************************** 835 ********************************************************************** 836 */ 837 static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb) 838 { 839 int i=0; 840 u_int32_t flag_srb; 841 u_int16_t error; 842 843 switch (acb->adapter_type) { 844 case ACB_ADAPTER_TYPE_A: { 845 u_int32_t outbound_intstatus; 846 847 /*clear and abort all outbound posted Q*/ 848 outbound_intstatus=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 849 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);/*clear interrupt*/ 850 while(((flag_srb=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_queueport)) != 0xFFFFFFFF) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) { 851 error=(flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 852 arcmsr_drain_donequeue(acb, flag_srb, error); 853 } 854 } 855 break; 856 case ACB_ADAPTER_TYPE_B: { 857 struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu; 858 859 /*clear all outbound posted Q*/ 860 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */ 861 for(i=0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) { 862 if((flag_srb=phbbmu->done_qbuffer[i])!=0) { 863 phbbmu->done_qbuffer[i]=0; 864 error=(flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 865 arcmsr_drain_donequeue(acb, flag_srb, error); 866 } 867 phbbmu->post_qbuffer[i]=0; 868 }/*drain reply FIFO*/ 869 phbbmu->doneq_index=0; 870 phbbmu->postq_index=0; 871 } 872 break; 873 case ACB_ADAPTER_TYPE_C: { 874 875 while((CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) { 876 flag_srb=CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 877 error=(flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE; 878 arcmsr_drain_donequeue(acb, flag_srb, error); 879 } 880 } 881 break; 882 } 883 return; 884 } 885 /* 886 **************************************************************************** 887 **************************************************************************** 888 */ 889 static void arcmsr_iop_reset(struct AdapterControlBlock *acb) 890 { 891 struct CommandControlBlock *srb; 892 u_int32_t intmask_org; 893 u_int32_t i=0; 894 895 if(acb->srboutstandingcount>0) { 896 /* disable all outbound interrupt */ 897 intmask_org=arcmsr_disable_allintr(acb); 898 /*clear and abort all outbound posted Q*/ 899 arcmsr_done4abort_postqueue(acb); 900 /* talk to iop 331 outstanding command aborted*/ 901 arcmsr_abort_allcmd(acb); 902 for(i=0;i<ARCMSR_MAX_FREESRB_NUM;i++) { 903 srb=acb->psrb_pool[i]; 904 if(srb->srb_state==ARCMSR_SRB_START) { 905 srb->srb_state=ARCMSR_SRB_ABORTED; 906 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 907 arcmsr_srb_complete(srb, 1); 908 printf("arcmsr%d: scsi id=%d lun=%d srb='%p' aborted\n" 909 , acb->pci_unit, srb->pccb->ccb_h.target_id 910 , srb->pccb->ccb_h.target_lun, srb); 911 } 912 } 913 /* enable all outbound interrupt */ 914 arcmsr_enable_allintr(acb, intmask_org); 915 } 916 acb->srboutstandingcount=0; 917 acb->workingsrb_doneindex=0; 918 acb->workingsrb_startindex=0; 919 #ifdef ARCMSR_DEBUG1 920 acb->pktRequestCount = 0; 921 acb->pktReturnCount = 0; 922 #endif 923 return; 924 } 925 /* 926 ********************************************************************** 927 ********************************************************************** 928 */ 929 static void arcmsr_build_srb(struct CommandControlBlock *srb, 930 bus_dma_segment_t *dm_segs, u_int32_t nseg) 931 { 932 struct ARCMSR_CDB * arcmsr_cdb= &srb->arcmsr_cdb; 933 u_int8_t * psge=(u_int8_t *)&arcmsr_cdb->u; 934 u_int32_t address_lo, address_hi; 935 union ccb * pccb=srb->pccb; 936 struct ccb_scsiio * pcsio= &pccb->csio; 937 u_int32_t arccdbsize=0x30; 938 939 memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB)); 940 arcmsr_cdb->Bus=0; 941 arcmsr_cdb->TargetID=pccb->ccb_h.target_id; 942 arcmsr_cdb->LUN=pccb->ccb_h.target_lun; 943 arcmsr_cdb->Function=1; 944 arcmsr_cdb->CdbLength=(u_int8_t)pcsio->cdb_len; 945 arcmsr_cdb->Context=0; 946 bcopy(pcsio->cdb_io.cdb_bytes, arcmsr_cdb->Cdb, pcsio->cdb_len); 947 if(nseg != 0) { 948 struct AdapterControlBlock *acb=srb->acb; 949 bus_dmasync_op_t op; 950 u_int32_t length, i, cdb_sgcount=0; 951 952 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 953 op=BUS_DMASYNC_PREREAD; 954 } else { 955 op=BUS_DMASYNC_PREWRITE; 956 arcmsr_cdb->Flags|=ARCMSR_CDB_FLAG_WRITE; 957 srb->srb_flags|=SRB_FLAG_WRITE; 958 } 959 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op); 960 for(i=0;i<nseg;i++) { 961 /* Get the physical address of the current data pointer */ 962 length=arcmsr_htole32(dm_segs[i].ds_len); 963 address_lo=arcmsr_htole32(dma_addr_lo32(dm_segs[i].ds_addr)); 964 address_hi=arcmsr_htole32(dma_addr_hi32(dm_segs[i].ds_addr)); 965 if(address_hi==0) { 966 struct SG32ENTRY * pdma_sg=(struct SG32ENTRY *)psge; 967 pdma_sg->address=address_lo; 968 pdma_sg->length=length; 969 psge += sizeof(struct SG32ENTRY); 970 arccdbsize += sizeof(struct SG32ENTRY); 971 } else { 972 u_int32_t sg64s_size=0, tmplength=length; 973 974 while(1) { 975 u_int64_t span4G, length0; 976 struct SG64ENTRY * pdma_sg=(struct SG64ENTRY *)psge; 977 978 span4G=(u_int64_t)address_lo + tmplength; 979 pdma_sg->addresshigh=address_hi; 980 pdma_sg->address=address_lo; 981 if(span4G > 0x100000000) { 982 /*see if cross 4G boundary*/ 983 length0=0x100000000-address_lo; 984 pdma_sg->length=(u_int32_t)length0|IS_SG64_ADDR; 985 address_hi=address_hi+1; 986 address_lo=0; 987 tmplength=tmplength-(u_int32_t)length0; 988 sg64s_size += sizeof(struct SG64ENTRY); 989 psge += sizeof(struct SG64ENTRY); 990 cdb_sgcount++; 991 } else { 992 pdma_sg->length=tmplength|IS_SG64_ADDR; 993 sg64s_size += sizeof(struct SG64ENTRY); 994 psge += sizeof(struct SG64ENTRY); 995 break; 996 } 997 } 998 arccdbsize += sg64s_size; 999 } 1000 cdb_sgcount++; 1001 } 1002 arcmsr_cdb->sgcount=(u_int8_t)cdb_sgcount; 1003 arcmsr_cdb->DataLength=pcsio->dxfer_len; 1004 if( arccdbsize > 256) { 1005 arcmsr_cdb->Flags|=ARCMSR_CDB_FLAG_SGL_BSIZE; 1006 } 1007 } else { 1008 arcmsr_cdb->DataLength = 0; 1009 } 1010 srb->arc_cdb_size=arccdbsize; 1011 return; 1012 } 1013 /* 1014 ************************************************************************** 1015 ************************************************************************** 1016 */ 1017 static void arcmsr_post_srb(struct AdapterControlBlock *acb, struct CommandControlBlock *srb) 1018 { 1019 u_int32_t cdb_shifted_phyaddr=(u_int32_t) srb->cdb_shifted_phyaddr; 1020 struct ARCMSR_CDB * arcmsr_cdb=(struct ARCMSR_CDB *)&srb->arcmsr_cdb; 1021 1022 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, (srb->srb_flags & SRB_FLAG_WRITE) ? BUS_DMASYNC_POSTWRITE:BUS_DMASYNC_POSTREAD); 1023 atomic_add_int(&acb->srboutstandingcount, 1); 1024 srb->srb_state=ARCMSR_SRB_START; 1025 1026 switch (acb->adapter_type) { 1027 case ACB_ADAPTER_TYPE_A: { 1028 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { 1029 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_shifted_phyaddr|ARCMSR_SRBPOST_FLAG_SGL_BSIZE); 1030 } else { 1031 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_shifted_phyaddr); 1032 } 1033 } 1034 break; 1035 case ACB_ADAPTER_TYPE_B: { 1036 struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu; 1037 int ending_index, index; 1038 1039 index=phbbmu->postq_index; 1040 ending_index=((index+1)%ARCMSR_MAX_HBB_POSTQUEUE); 1041 phbbmu->post_qbuffer[ending_index]=0; 1042 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { 1043 phbbmu->post_qbuffer[index]= cdb_shifted_phyaddr|ARCMSR_SRBPOST_FLAG_SGL_BSIZE; 1044 } else { 1045 phbbmu->post_qbuffer[index]= cdb_shifted_phyaddr; 1046 } 1047 index++; 1048 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 1049 phbbmu->postq_index=index; 1050 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_CDB_POSTED); 1051 } 1052 break; 1053 case ACB_ADAPTER_TYPE_C: 1054 { 1055 u_int32_t ccb_post_stamp, arc_cdb_size, cdb_phyaddr_hi32; 1056 1057 arc_cdb_size=(srb->arc_cdb_size>0x300)?0x300:srb->arc_cdb_size; 1058 ccb_post_stamp=(cdb_shifted_phyaddr | ((arc_cdb_size-1) >> 6) | 1); 1059 cdb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high; 1060 if(cdb_phyaddr_hi32) 1061 { 1062 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_high, cdb_phyaddr_hi32); 1063 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp); 1064 } 1065 else 1066 { 1067 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp); 1068 } 1069 } 1070 break; 1071 } 1072 return; 1073 } 1074 /* 1075 ************************************************************************ 1076 ************************************************************************ 1077 */ 1078 static struct QBUFFER * arcmsr_get_iop_rqbuffer( struct AdapterControlBlock *acb) 1079 { 1080 struct QBUFFER *qbuffer=NULL; 1081 1082 switch (acb->adapter_type) { 1083 case ACB_ADAPTER_TYPE_A: { 1084 struct HBA_MessageUnit *phbamu=(struct HBA_MessageUnit *)acb->pmu; 1085 1086 qbuffer=(struct QBUFFER *)&phbamu->message_rbuffer; 1087 } 1088 break; 1089 case ACB_ADAPTER_TYPE_B: { 1090 struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu; 1091 1092 qbuffer=(struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_rbuffer; 1093 } 1094 break; 1095 case ACB_ADAPTER_TYPE_C: { 1096 struct HBC_MessageUnit *phbcmu=(struct HBC_MessageUnit *)acb->pmu; 1097 1098 qbuffer=(struct QBUFFER *)&phbcmu->message_rbuffer; 1099 } 1100 break; 1101 } 1102 return(qbuffer); 1103 } 1104 /* 1105 ************************************************************************ 1106 ************************************************************************ 1107 */ 1108 static struct QBUFFER * arcmsr_get_iop_wqbuffer( struct AdapterControlBlock *acb) 1109 { 1110 struct QBUFFER *qbuffer=NULL; 1111 1112 switch (acb->adapter_type) { 1113 case ACB_ADAPTER_TYPE_A: { 1114 struct HBA_MessageUnit *phbamu=(struct HBA_MessageUnit *)acb->pmu; 1115 1116 qbuffer=(struct QBUFFER *)&phbamu->message_wbuffer; 1117 } 1118 break; 1119 case ACB_ADAPTER_TYPE_B: { 1120 struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu; 1121 1122 qbuffer=(struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_wbuffer; 1123 } 1124 break; 1125 case ACB_ADAPTER_TYPE_C: { 1126 struct HBC_MessageUnit *phbcmu=(struct HBC_MessageUnit *)acb->pmu; 1127 1128 qbuffer=(struct QBUFFER *)&phbcmu->message_wbuffer; 1129 } 1130 break; 1131 } 1132 return(qbuffer); 1133 } 1134 /* 1135 ************************************************************************** 1136 ************************************************************************** 1137 */ 1138 static void arcmsr_iop_message_read(struct AdapterControlBlock *acb) 1139 { 1140 switch (acb->adapter_type) { 1141 case ACB_ADAPTER_TYPE_A: { 1142 /* let IOP know data has been read */ 1143 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK); 1144 } 1145 break; 1146 case ACB_ADAPTER_TYPE_B: { 1147 /* let IOP know data has been read */ 1148 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK); 1149 } 1150 break; 1151 case ACB_ADAPTER_TYPE_C: { 1152 /* let IOP know data has been read */ 1153 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK); 1154 } 1155 } 1156 return; 1157 } 1158 /* 1159 ************************************************************************** 1160 ************************************************************************** 1161 */ 1162 static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb) 1163 { 1164 switch (acb->adapter_type) { 1165 case ACB_ADAPTER_TYPE_A: { 1166 /* 1167 ** push inbound doorbell tell iop, driver data write ok 1168 ** and wait reply on next hwinterrupt for next Qbuffer post 1169 */ 1170 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK); 1171 } 1172 break; 1173 case ACB_ADAPTER_TYPE_B: { 1174 /* 1175 ** push inbound doorbell tell iop, driver data write ok 1176 ** and wait reply on next hwinterrupt for next Qbuffer post 1177 */ 1178 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_WRITE_OK); 1179 } 1180 break; 1181 case ACB_ADAPTER_TYPE_C: { 1182 /* 1183 ** push inbound doorbell tell iop, driver data write ok 1184 ** and wait reply on next hwinterrupt for next Qbuffer post 1185 */ 1186 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK); 1187 } 1188 break; 1189 } 1190 } 1191 /* 1192 ********************************************************************** 1193 ********************************************************************** 1194 */ 1195 static void arcmsr_post_ioctldata2iop(struct AdapterControlBlock *acb) 1196 { 1197 u_int8_t *pQbuffer; 1198 struct QBUFFER *pwbuffer; 1199 u_int8_t * iop_data; 1200 int32_t allxfer_len=0; 1201 1202 pwbuffer=arcmsr_get_iop_wqbuffer(acb); 1203 iop_data=(u_int8_t *)pwbuffer->data; 1204 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) { 1205 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ); 1206 while((acb->wqbuf_firstindex!=acb->wqbuf_lastindex) 1207 && (allxfer_len<124)) { 1208 pQbuffer=&acb->wqbuffer[acb->wqbuf_firstindex]; 1209 memcpy(iop_data, pQbuffer, 1); 1210 acb->wqbuf_firstindex++; 1211 acb->wqbuf_firstindex %=ARCMSR_MAX_QBUFFER; /*if last index number set it to 0 */ 1212 iop_data++; 1213 allxfer_len++; 1214 } 1215 pwbuffer->data_len=allxfer_len; 1216 /* 1217 ** push inbound doorbell and wait reply at hwinterrupt routine for next Qbuffer post 1218 */ 1219 arcmsr_iop_message_wrote(acb); 1220 } 1221 return; 1222 } 1223 /* 1224 ************************************************************************ 1225 ************************************************************************ 1226 */ 1227 static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb) 1228 { 1229 acb->acb_flags &=~ACB_F_MSG_START_BGRB; 1230 CHIP_REG_WRITE32(HBA_MessageUnit, 1231 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1232 if(!arcmsr_hba_wait_msgint_ready(acb)) { 1233 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n" 1234 , acb->pci_unit); 1235 } 1236 return; 1237 } 1238 /* 1239 ************************************************************************ 1240 ************************************************************************ 1241 */ 1242 static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb) 1243 { 1244 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1245 CHIP_REG_WRITE32(HBB_DOORBELL, 1246 0, drv2iop_doorbell, ARCMSR_MESSAGE_STOP_BGRB); 1247 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 1248 printf( "arcmsr%d: wait 'stop adapter background rebulid' timeout \n" 1249 , acb->pci_unit); 1250 } 1251 return; 1252 } 1253 /* 1254 ************************************************************************ 1255 ************************************************************************ 1256 */ 1257 static void arcmsr_stop_hbc_bgrb(struct AdapterControlBlock *acb) 1258 { 1259 acb->acb_flags &=~ACB_F_MSG_START_BGRB; 1260 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1261 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 1262 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 1263 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1264 } 1265 return; 1266 } 1267 /* 1268 ************************************************************************ 1269 ************************************************************************ 1270 */ 1271 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb) 1272 { 1273 switch (acb->adapter_type) { 1274 case ACB_ADAPTER_TYPE_A: { 1275 arcmsr_stop_hba_bgrb(acb); 1276 } 1277 break; 1278 case ACB_ADAPTER_TYPE_B: { 1279 arcmsr_stop_hbb_bgrb(acb); 1280 } 1281 break; 1282 case ACB_ADAPTER_TYPE_C: { 1283 arcmsr_stop_hbc_bgrb(acb); 1284 } 1285 break; 1286 } 1287 return; 1288 } 1289 /* 1290 ************************************************************************ 1291 ************************************************************************ 1292 */ 1293 static void arcmsr_poll(struct cam_sim * psim) 1294 { 1295 struct AdapterControlBlock *acb; 1296 1297 acb = (struct AdapterControlBlock *)cam_sim_softc(psim); 1298 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 1299 arcmsr_interrupt(acb); 1300 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 1301 return; 1302 } 1303 /* 1304 ************************************************************************** 1305 ************************************************************************** 1306 */ 1307 static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb) 1308 { 1309 struct QBUFFER *prbuffer; 1310 u_int8_t *pQbuffer; 1311 u_int8_t *iop_data; 1312 int my_empty_len, iop_len, rqbuf_firstindex, rqbuf_lastindex; 1313 1314 /*check this iop data if overflow my rqbuffer*/ 1315 rqbuf_lastindex=acb->rqbuf_lastindex; 1316 rqbuf_firstindex=acb->rqbuf_firstindex; 1317 prbuffer=arcmsr_get_iop_rqbuffer(acb); 1318 iop_data=(u_int8_t *)prbuffer->data; 1319 iop_len=prbuffer->data_len; 1320 my_empty_len=(rqbuf_firstindex-rqbuf_lastindex-1)&(ARCMSR_MAX_QBUFFER-1); 1321 if(my_empty_len>=iop_len) { 1322 while(iop_len > 0) { 1323 pQbuffer=&acb->rqbuffer[rqbuf_lastindex]; 1324 memcpy(pQbuffer, iop_data, 1); 1325 rqbuf_lastindex++; 1326 rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;/*if last index number set it to 0 */ 1327 iop_data++; 1328 iop_len--; 1329 } 1330 acb->rqbuf_lastindex=rqbuf_lastindex; 1331 arcmsr_iop_message_read(acb); 1332 /*signature, let IOP know data has been read */ 1333 } else { 1334 acb->acb_flags|=ACB_F_IOPDATA_OVERFLOW; 1335 } 1336 return; 1337 } 1338 /* 1339 ************************************************************************** 1340 ************************************************************************** 1341 */ 1342 static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb) 1343 { 1344 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READ; 1345 /* 1346 ***************************************************************** 1347 ** check if there are any mail packages from user space program 1348 ** in my post bag, now is the time to send them into Areca's firmware 1349 ***************************************************************** 1350 */ 1351 if(acb->wqbuf_firstindex!=acb->wqbuf_lastindex) { 1352 u_int8_t *pQbuffer; 1353 struct QBUFFER *pwbuffer; 1354 u_int8_t *iop_data; 1355 int allxfer_len=0; 1356 1357 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ); 1358 pwbuffer=arcmsr_get_iop_wqbuffer(acb); 1359 iop_data=(u_int8_t *)pwbuffer->data; 1360 while((acb->wqbuf_firstindex!=acb->wqbuf_lastindex) 1361 && (allxfer_len<124)) { 1362 pQbuffer=&acb->wqbuffer[acb->wqbuf_firstindex]; 1363 memcpy(iop_data, pQbuffer, 1); 1364 acb->wqbuf_firstindex++; 1365 acb->wqbuf_firstindex %=ARCMSR_MAX_QBUFFER; /*if last index number set it to 0 */ 1366 iop_data++; 1367 allxfer_len++; 1368 } 1369 pwbuffer->data_len=allxfer_len; 1370 /* 1371 ** push inbound doorbell tell iop driver data write ok 1372 ** and wait reply on next hwinterrupt for next Qbuffer post 1373 */ 1374 arcmsr_iop_message_wrote(acb); 1375 } 1376 if(acb->wqbuf_firstindex==acb->wqbuf_lastindex) { 1377 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED; 1378 } 1379 return; 1380 } 1381 1382 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb) 1383 { 1384 /* 1385 if (ccb->ccb_h.status != CAM_REQ_CMP) 1386 printf("arcmsr_rescanLun_cb: Rescan Target=%x, lun=%x, failure status=%x\n",ccb->ccb_h.target_id,ccb->ccb_h.target_lun,ccb->ccb_h.status); 1387 else 1388 printf("arcmsr_rescanLun_cb: Rescan lun successfully!\n"); 1389 */ 1390 xpt_free_path(ccb->ccb_h.path); 1391 xpt_free_ccb(ccb); 1392 } 1393 1394 static void arcmsr_rescan_lun(struct AdapterControlBlock *acb, int target, int lun) 1395 { 1396 struct cam_path *path; 1397 union ccb *ccb; 1398 1399 if ((ccb = (union ccb *)xpt_alloc_ccb_nowait()) == NULL) 1400 return; 1401 if (xpt_create_path(&path, xpt_periph, cam_sim_path(acb->psim), target, lun) != CAM_REQ_CMP) 1402 { 1403 xpt_free_ccb(ccb); 1404 return; 1405 } 1406 /* printf("arcmsr_rescan_lun: Rescan Target=%x, Lun=%x\n", target, lun); */ 1407 bzero(ccb, sizeof(union ccb)); 1408 xpt_setup_ccb(&ccb->ccb_h, path, 5); 1409 ccb->ccb_h.func_code = XPT_SCAN_LUN; 1410 ccb->ccb_h.cbfcnp = arcmsr_rescanLun_cb; 1411 ccb->crcn.flags = CAM_FLAG_NONE; 1412 xpt_action(ccb); 1413 return; 1414 } 1415 1416 1417 static void arcmsr_abort_dr_ccbs(struct AdapterControlBlock *acb, int target, int lun) 1418 { 1419 struct CommandControlBlock *srb; 1420 u_int32_t intmask_org; 1421 int i; 1422 1423 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 1424 /* disable all outbound interrupts */ 1425 intmask_org = arcmsr_disable_allintr(acb); 1426 for (i = 0; i < ARCMSR_MAX_FREESRB_NUM; i++) 1427 { 1428 srb = acb->psrb_pool[i]; 1429 if (srb->srb_state == ARCMSR_SRB_START) 1430 { 1431 if((target == srb->pccb->ccb_h.target_id) && (lun == srb->pccb->ccb_h.target_lun)) 1432 { 1433 srb->srb_state = ARCMSR_SRB_ABORTED; 1434 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 1435 arcmsr_srb_complete(srb, 1); 1436 printf("arcmsr%d: abort scsi id %d lun %d srb=%p \n", acb->pci_unit, target, lun, srb); 1437 } 1438 } 1439 } 1440 /* enable outbound Post Queue, outbound doorbell Interrupt */ 1441 arcmsr_enable_allintr(acb, intmask_org); 1442 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 1443 } 1444 1445 1446 /* 1447 ************************************************************************** 1448 ************************************************************************** 1449 */ 1450 static void arcmsr_dr_handle(struct AdapterControlBlock *acb) { 1451 u_int32_t devicemap; 1452 u_int32_t target, lun; 1453 u_int32_t deviceMapCurrent[4]={0}; 1454 u_int8_t *pDevMap; 1455 1456 switch (acb->adapter_type) { 1457 case ACB_ADAPTER_TYPE_A: 1458 devicemap = offsetof(struct HBA_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1459 for (target= 0; target < 4; target++) 1460 { 1461 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1462 devicemap += 4; 1463 } 1464 break; 1465 1466 case ACB_ADAPTER_TYPE_B: 1467 devicemap = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1468 for (target= 0; target < 4; target++) 1469 { 1470 deviceMapCurrent[target]=bus_space_read_4(acb->btag[1], acb->bhandle[1], devicemap); 1471 devicemap += 4; 1472 } 1473 break; 1474 1475 case ACB_ADAPTER_TYPE_C: 1476 devicemap = offsetof(struct HBC_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1477 for (target= 0; target < 4; target++) 1478 { 1479 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1480 devicemap += 4; 1481 } 1482 break; 1483 } 1484 if(acb->acb_flags & ACB_F_BUS_HANG_ON) 1485 { 1486 acb->acb_flags &= ~ACB_F_BUS_HANG_ON; 1487 } 1488 /* 1489 ** adapter posted CONFIG message 1490 ** copy the new map, note if there are differences with the current map 1491 */ 1492 pDevMap = (u_int8_t *)&deviceMapCurrent[0]; 1493 for (target= 0; target < ARCMSR_MAX_TARGETID - 1; target++) 1494 { 1495 if (*pDevMap != acb->device_map[target]) 1496 { 1497 u_int8_t difference, bit_check; 1498 1499 difference= *pDevMap ^ acb->device_map[target]; 1500 for(lun=0; lun < ARCMSR_MAX_TARGETLUN; lun++) 1501 { 1502 bit_check=(1 << lun); /*check bit from 0....31*/ 1503 if(difference & bit_check) 1504 { 1505 if(acb->device_map[target] & bit_check) 1506 {/* unit departed */ 1507 printf("arcmsr_dr_handle: Target=%x, lun=%x, GONE!!!\n",target,lun); 1508 arcmsr_abort_dr_ccbs(acb, target, lun); 1509 arcmsr_rescan_lun(acb, target, lun); 1510 acb->devstate[target][lun] = ARECA_RAID_GONE; 1511 } 1512 else 1513 {/* unit arrived */ 1514 printf("arcmsr_dr_handle: Target=%x, lun=%x, Plug-IN!!!\n",target,lun); 1515 arcmsr_rescan_lun(acb, target, lun); 1516 acb->devstate[target][lun] = ARECA_RAID_GOOD; 1517 } 1518 } 1519 } 1520 /* printf("arcmsr_dr_handle: acb->device_map[%x]=0x%x, deviceMapCurrent[%x]=%x\n",target,acb->device_map[target],target,*pDevMap); */ 1521 acb->device_map[target]= *pDevMap; 1522 } 1523 pDevMap++; 1524 } 1525 } 1526 /* 1527 ************************************************************************** 1528 ************************************************************************** 1529 */ 1530 static void arcmsr_hba_message_isr(struct AdapterControlBlock *acb) { 1531 u_int32_t outbound_message; 1532 1533 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT); 1534 outbound_message = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[0]); 1535 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1536 arcmsr_dr_handle( acb ); 1537 } 1538 /* 1539 ************************************************************************** 1540 ************************************************************************** 1541 */ 1542 static void arcmsr_hbb_message_isr(struct AdapterControlBlock *acb) { 1543 u_int32_t outbound_message; 1544 1545 /* clear interrupts */ 1546 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN); 1547 outbound_message = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0]); 1548 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1549 arcmsr_dr_handle( acb ); 1550 } 1551 /* 1552 ************************************************************************** 1553 ************************************************************************** 1554 */ 1555 static void arcmsr_hbc_message_isr(struct AdapterControlBlock *acb) { 1556 u_int32_t outbound_message; 1557 1558 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR); 1559 outbound_message = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[0]); 1560 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1561 arcmsr_dr_handle( acb ); 1562 } 1563 /* 1564 ************************************************************************** 1565 ************************************************************************** 1566 */ 1567 static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb) 1568 { 1569 u_int32_t outbound_doorbell; 1570 1571 /* 1572 ******************************************************************* 1573 ** Maybe here we need to check wrqbuffer_lock is lock or not 1574 ** DOORBELL: din! don! 1575 ** check if there are any mail need to pack from firmware 1576 ******************************************************************* 1577 */ 1578 outbound_doorbell=CHIP_REG_READ32(HBA_MessageUnit, 1579 0, outbound_doorbell); 1580 CHIP_REG_WRITE32(HBA_MessageUnit, 1581 0, outbound_doorbell, outbound_doorbell); /* clear doorbell interrupt */ 1582 if(outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) { 1583 arcmsr_iop2drv_data_wrote_handle(acb); 1584 } 1585 if(outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) { 1586 arcmsr_iop2drv_data_read_handle(acb); 1587 } 1588 return; 1589 } 1590 /* 1591 ************************************************************************** 1592 ************************************************************************** 1593 */ 1594 static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *acb) 1595 { 1596 u_int32_t outbound_doorbell; 1597 1598 /* 1599 ******************************************************************* 1600 ** Maybe here we need to check wrqbuffer_lock is lock or not 1601 ** DOORBELL: din! don! 1602 ** check if there are any mail need to pack from firmware 1603 ******************************************************************* 1604 */ 1605 outbound_doorbell=CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell); 1606 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell); /* clear doorbell interrupt */ 1607 if(outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) { 1608 arcmsr_iop2drv_data_wrote_handle(acb); 1609 } 1610 if(outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) { 1611 arcmsr_iop2drv_data_read_handle(acb); 1612 } 1613 if(outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 1614 arcmsr_hbc_message_isr(acb); /* messenger of "driver to iop commands" */ 1615 } 1616 return; 1617 } 1618 /* 1619 ************************************************************************** 1620 ************************************************************************** 1621 */ 1622 static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb) 1623 { 1624 u_int32_t flag_srb; 1625 u_int16_t error; 1626 1627 /* 1628 ***************************************************************************** 1629 ** areca cdb command done 1630 ***************************************************************************** 1631 */ 1632 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 1633 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1634 while((flag_srb=CHIP_REG_READ32(HBA_MessageUnit, 1635 0, outbound_queueport)) != 0xFFFFFFFF) { 1636 /* check if command done with no error*/ 1637 error=(flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 1638 arcmsr_drain_donequeue(acb, flag_srb, error); 1639 } /*drain reply FIFO*/ 1640 return; 1641 } 1642 /* 1643 ************************************************************************** 1644 ************************************************************************** 1645 */ 1646 static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb) 1647 { 1648 struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu; 1649 u_int32_t flag_srb; 1650 int index; 1651 u_int16_t error; 1652 1653 /* 1654 ***************************************************************************** 1655 ** areca cdb command done 1656 ***************************************************************************** 1657 */ 1658 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 1659 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1660 index=phbbmu->doneq_index; 1661 while((flag_srb=phbbmu->done_qbuffer[index]) != 0) { 1662 phbbmu->done_qbuffer[index]=0; 1663 index++; 1664 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 1665 phbbmu->doneq_index=index; 1666 /* check if command done with no error*/ 1667 error=(flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 1668 arcmsr_drain_donequeue(acb, flag_srb, error); 1669 } /*drain reply FIFO*/ 1670 return; 1671 } 1672 /* 1673 ************************************************************************** 1674 ************************************************************************** 1675 */ 1676 static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb) 1677 { 1678 u_int32_t flag_srb,throttling=0; 1679 u_int16_t error; 1680 1681 /* 1682 ***************************************************************************** 1683 ** areca cdb command done 1684 ***************************************************************************** 1685 */ 1686 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1687 1688 while(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) { 1689 1690 flag_srb=CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 1691 /* check if command done with no error*/ 1692 error=(flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE; 1693 arcmsr_drain_donequeue(acb, flag_srb, error); 1694 if(throttling==ARCMSR_HBC_ISR_THROTTLING_LEVEL) { 1695 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING); 1696 break; 1697 } 1698 throttling++; 1699 } /*drain reply FIFO*/ 1700 return; 1701 } 1702 /* 1703 ********************************************************************** 1704 ********************************************************************** 1705 */ 1706 static void arcmsr_handle_hba_isr( struct AdapterControlBlock *acb) 1707 { 1708 u_int32_t outbound_intstatus; 1709 /* 1710 ********************************************* 1711 ** check outbound intstatus 1712 ********************************************* 1713 */ 1714 outbound_intstatus=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 1715 if(!outbound_intstatus) { 1716 /*it must be share irq*/ 1717 return; 1718 } 1719 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);/*clear interrupt*/ 1720 /* MU doorbell interrupts*/ 1721 if(outbound_intstatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) { 1722 arcmsr_hba_doorbell_isr(acb); 1723 } 1724 /* MU post queue interrupts*/ 1725 if(outbound_intstatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) { 1726 arcmsr_hba_postqueue_isr(acb); 1727 } 1728 if(outbound_intstatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { 1729 arcmsr_hba_message_isr(acb); 1730 } 1731 return; 1732 } 1733 /* 1734 ********************************************************************** 1735 ********************************************************************** 1736 */ 1737 static void arcmsr_handle_hbb_isr( struct AdapterControlBlock *acb) 1738 { 1739 u_int32_t outbound_doorbell; 1740 /* 1741 ********************************************* 1742 ** check outbound intstatus 1743 ********************************************* 1744 */ 1745 outbound_doorbell=CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & acb->outbound_int_enable; 1746 if(!outbound_doorbell) { 1747 /*it must be share irq*/ 1748 return; 1749 } 1750 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ~outbound_doorbell); /* clear doorbell interrupt */ 1751 CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell); 1752 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 1753 /* MU ioctl transfer doorbell interrupts*/ 1754 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) { 1755 arcmsr_iop2drv_data_wrote_handle(acb); 1756 } 1757 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) { 1758 arcmsr_iop2drv_data_read_handle(acb); 1759 } 1760 /* MU post queue interrupts*/ 1761 if(outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) { 1762 arcmsr_hbb_postqueue_isr(acb); 1763 } 1764 if(outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) { 1765 arcmsr_hbb_message_isr(acb); 1766 } 1767 return; 1768 } 1769 /* 1770 ********************************************************************** 1771 ********************************************************************** 1772 */ 1773 static void arcmsr_handle_hbc_isr( struct AdapterControlBlock *acb) 1774 { 1775 u_int32_t host_interrupt_status; 1776 /* 1777 ********************************************* 1778 ** check outbound intstatus 1779 ********************************************* 1780 */ 1781 host_interrupt_status=CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status); 1782 if(!host_interrupt_status) { 1783 /*it must be share irq*/ 1784 return; 1785 } 1786 /* MU doorbell interrupts*/ 1787 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) { 1788 arcmsr_hbc_doorbell_isr(acb); 1789 } 1790 /* MU post queue interrupts*/ 1791 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) { 1792 arcmsr_hbc_postqueue_isr(acb); 1793 } 1794 return; 1795 } 1796 /* 1797 ****************************************************************************** 1798 ****************************************************************************** 1799 */ 1800 static void arcmsr_interrupt(struct AdapterControlBlock *acb) 1801 { 1802 switch (acb->adapter_type) { 1803 case ACB_ADAPTER_TYPE_A: 1804 arcmsr_handle_hba_isr(acb); 1805 break; 1806 case ACB_ADAPTER_TYPE_B: 1807 arcmsr_handle_hbb_isr(acb); 1808 break; 1809 case ACB_ADAPTER_TYPE_C: 1810 arcmsr_handle_hbc_isr(acb); 1811 break; 1812 default: 1813 printf("arcmsr%d: interrupt service," 1814 " unknow adapter type =%d\n", acb->pci_unit, acb->adapter_type); 1815 break; 1816 } 1817 return; 1818 } 1819 /* 1820 ********************************************************************** 1821 ********************************************************************** 1822 */ 1823 static void arcmsr_intr_handler(void *arg) 1824 { 1825 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)arg; 1826 1827 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 1828 arcmsr_interrupt(acb); 1829 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 1830 } 1831 /* 1832 ****************************************************************************** 1833 ****************************************************************************** 1834 */ 1835 static void arcmsr_polling_devmap(void* arg) 1836 { 1837 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg; 1838 switch (acb->adapter_type) { 1839 case ACB_ADAPTER_TYPE_A: 1840 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 1841 break; 1842 1843 case ACB_ADAPTER_TYPE_B: 1844 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG); 1845 break; 1846 1847 case ACB_ADAPTER_TYPE_C: 1848 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 1849 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 1850 break; 1851 } 1852 1853 if((acb->acb_flags & ACB_F_SCSISTOPADAPTER) == 0) 1854 { 1855 callout_reset(&acb->devmap_callout, 5 * hz, arcmsr_polling_devmap, acb); /* polling per 5 seconds */ 1856 } 1857 } 1858 1859 /* 1860 ******************************************************************************* 1861 ** 1862 ******************************************************************************* 1863 */ 1864 static void arcmsr_iop_parking(struct AdapterControlBlock *acb) 1865 { 1866 u_int32_t intmask_org; 1867 1868 if(acb!=NULL) { 1869 /* stop adapter background rebuild */ 1870 if(acb->acb_flags & ACB_F_MSG_START_BGRB) { 1871 intmask_org = arcmsr_disable_allintr(acb); 1872 arcmsr_stop_adapter_bgrb(acb); 1873 arcmsr_flush_adapter_cache(acb); 1874 arcmsr_enable_allintr(acb, intmask_org); 1875 } 1876 } 1877 } 1878 /* 1879 *********************************************************************** 1880 ** 1881 ************************************************************************ 1882 */ 1883 u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg) 1884 { 1885 struct CMD_MESSAGE_FIELD * pcmdmessagefld; 1886 u_int32_t retvalue=EINVAL; 1887 1888 pcmdmessagefld=(struct CMD_MESSAGE_FIELD *) arg; 1889 if(memcmp(pcmdmessagefld->cmdmessage.Signature, "ARCMSR", 6)!=0) { 1890 return retvalue; 1891 } 1892 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 1893 switch(ioctl_cmd) { 1894 case ARCMSR_MESSAGE_READ_RQBUFFER: { 1895 u_int8_t * pQbuffer; 1896 u_int8_t * ptmpQbuffer=pcmdmessagefld->messagedatabuffer; 1897 u_int32_t allxfer_len=0; 1898 1899 while((acb->rqbuf_firstindex!=acb->rqbuf_lastindex) 1900 && (allxfer_len<1031)) { 1901 /*copy READ QBUFFER to srb*/ 1902 pQbuffer= &acb->rqbuffer[acb->rqbuf_firstindex]; 1903 memcpy(ptmpQbuffer, pQbuffer, 1); 1904 acb->rqbuf_firstindex++; 1905 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 1906 /*if last index number set it to 0 */ 1907 ptmpQbuffer++; 1908 allxfer_len++; 1909 } 1910 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 1911 struct QBUFFER * prbuffer; 1912 u_int8_t * iop_data; 1913 u_int32_t iop_len; 1914 1915 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 1916 prbuffer=arcmsr_get_iop_rqbuffer(acb); 1917 iop_data=(u_int8_t *)prbuffer->data; 1918 iop_len=(u_int32_t)prbuffer->data_len; 1919 /*this iop data does no chance to make me overflow again here, so just do it*/ 1920 while(iop_len>0) { 1921 pQbuffer= &acb->rqbuffer[acb->rqbuf_lastindex]; 1922 memcpy(pQbuffer, iop_data, 1); 1923 acb->rqbuf_lastindex++; 1924 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 1925 /*if last index number set it to 0 */ 1926 iop_data++; 1927 iop_len--; 1928 } 1929 arcmsr_iop_message_read(acb); 1930 /*signature, let IOP know data has been readed */ 1931 } 1932 pcmdmessagefld->cmdmessage.Length=allxfer_len; 1933 pcmdmessagefld->cmdmessage.ReturnCode=ARCMSR_MESSAGE_RETURNCODE_OK; 1934 retvalue=ARCMSR_MESSAGE_SUCCESS; 1935 } 1936 break; 1937 case ARCMSR_MESSAGE_WRITE_WQBUFFER: { 1938 u_int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex; 1939 u_int8_t * pQbuffer; 1940 u_int8_t * ptmpuserbuffer=pcmdmessagefld->messagedatabuffer; 1941 1942 user_len=pcmdmessagefld->cmdmessage.Length; 1943 /*check if data xfer length of this request will overflow my array qbuffer */ 1944 wqbuf_lastindex=acb->wqbuf_lastindex; 1945 wqbuf_firstindex=acb->wqbuf_firstindex; 1946 if(wqbuf_lastindex!=wqbuf_firstindex) { 1947 arcmsr_post_ioctldata2iop(acb); 1948 pcmdmessagefld->cmdmessage.ReturnCode=ARCMSR_MESSAGE_RETURNCODE_ERROR; 1949 } else { 1950 my_empty_len=(wqbuf_firstindex-wqbuf_lastindex-1)&(ARCMSR_MAX_QBUFFER-1); 1951 if(my_empty_len>=user_len) { 1952 while(user_len>0) { 1953 /*copy srb data to wqbuffer*/ 1954 pQbuffer= &acb->wqbuffer[acb->wqbuf_lastindex]; 1955 memcpy(pQbuffer, ptmpuserbuffer, 1); 1956 acb->wqbuf_lastindex++; 1957 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 1958 /*if last index number set it to 0 */ 1959 ptmpuserbuffer++; 1960 user_len--; 1961 } 1962 /*post fist Qbuffer*/ 1963 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) { 1964 acb->acb_flags &=~ACB_F_MESSAGE_WQBUFFER_CLEARED; 1965 arcmsr_post_ioctldata2iop(acb); 1966 } 1967 pcmdmessagefld->cmdmessage.ReturnCode=ARCMSR_MESSAGE_RETURNCODE_OK; 1968 } else { 1969 pcmdmessagefld->cmdmessage.ReturnCode=ARCMSR_MESSAGE_RETURNCODE_ERROR; 1970 } 1971 } 1972 retvalue=ARCMSR_MESSAGE_SUCCESS; 1973 } 1974 break; 1975 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: { 1976 u_int8_t * pQbuffer=acb->rqbuffer; 1977 1978 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 1979 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 1980 arcmsr_iop_message_read(acb); 1981 /*signature, let IOP know data has been readed */ 1982 } 1983 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 1984 acb->rqbuf_firstindex=0; 1985 acb->rqbuf_lastindex=0; 1986 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 1987 pcmdmessagefld->cmdmessage.ReturnCode=ARCMSR_MESSAGE_RETURNCODE_OK; 1988 retvalue=ARCMSR_MESSAGE_SUCCESS; 1989 } 1990 break; 1991 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: 1992 { 1993 u_int8_t * pQbuffer=acb->wqbuffer; 1994 1995 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 1996 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 1997 arcmsr_iop_message_read(acb); 1998 /*signature, let IOP know data has been readed */ 1999 } 2000 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ); 2001 acb->wqbuf_firstindex=0; 2002 acb->wqbuf_lastindex=0; 2003 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2004 pcmdmessagefld->cmdmessage.ReturnCode=ARCMSR_MESSAGE_RETURNCODE_OK; 2005 retvalue=ARCMSR_MESSAGE_SUCCESS; 2006 } 2007 break; 2008 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: { 2009 u_int8_t * pQbuffer; 2010 2011 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2012 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2013 arcmsr_iop_message_read(acb); 2014 /*signature, let IOP know data has been readed */ 2015 } 2016 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED 2017 |ACB_F_MESSAGE_RQBUFFER_CLEARED 2018 |ACB_F_MESSAGE_WQBUFFER_READ); 2019 acb->rqbuf_firstindex=0; 2020 acb->rqbuf_lastindex=0; 2021 acb->wqbuf_firstindex=0; 2022 acb->wqbuf_lastindex=0; 2023 pQbuffer=acb->rqbuffer; 2024 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 2025 pQbuffer=acb->wqbuffer; 2026 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 2027 pcmdmessagefld->cmdmessage.ReturnCode=ARCMSR_MESSAGE_RETURNCODE_OK; 2028 retvalue=ARCMSR_MESSAGE_SUCCESS; 2029 } 2030 break; 2031 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: { 2032 pcmdmessagefld->cmdmessage.ReturnCode=ARCMSR_MESSAGE_RETURNCODE_3F; 2033 retvalue=ARCMSR_MESSAGE_SUCCESS; 2034 } 2035 break; 2036 case ARCMSR_MESSAGE_SAY_HELLO: { 2037 u_int8_t * hello_string="Hello! I am ARCMSR"; 2038 u_int8_t * puserbuffer=(u_int8_t *)pcmdmessagefld->messagedatabuffer; 2039 2040 if(memcpy(puserbuffer, hello_string, (int16_t)strlen(hello_string))) { 2041 pcmdmessagefld->cmdmessage.ReturnCode=ARCMSR_MESSAGE_RETURNCODE_ERROR; 2042 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2043 return ENOIOCTL; 2044 } 2045 pcmdmessagefld->cmdmessage.ReturnCode=ARCMSR_MESSAGE_RETURNCODE_OK; 2046 retvalue=ARCMSR_MESSAGE_SUCCESS; 2047 } 2048 break; 2049 case ARCMSR_MESSAGE_SAY_GOODBYE: { 2050 arcmsr_iop_parking(acb); 2051 retvalue=ARCMSR_MESSAGE_SUCCESS; 2052 } 2053 break; 2054 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: { 2055 arcmsr_flush_adapter_cache(acb); 2056 retvalue=ARCMSR_MESSAGE_SUCCESS; 2057 } 2058 break; 2059 } 2060 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2061 return retvalue; 2062 } 2063 /* 2064 ************************************************************************** 2065 ************************************************************************** 2066 */ 2067 static void arcmsr_free_srb(struct CommandControlBlock *srb) 2068 { 2069 struct AdapterControlBlock *acb; 2070 int mutex; 2071 2072 acb = srb->acb; 2073 mutex = mtx_owned(&acb->qbuffer_lock); 2074 if( mutex == 0 ) 2075 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2076 srb->srb_state=ARCMSR_SRB_DONE; 2077 srb->srb_flags=0; 2078 acb->srbworkingQ[acb->workingsrb_doneindex]=srb; 2079 acb->workingsrb_doneindex++; 2080 acb->workingsrb_doneindex %= ARCMSR_MAX_FREESRB_NUM; 2081 if( mutex == 0 ) 2082 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2083 } 2084 /* 2085 ************************************************************************** 2086 ************************************************************************** 2087 */ 2088 struct CommandControlBlock * arcmsr_get_freesrb(struct AdapterControlBlock *acb) 2089 { 2090 struct CommandControlBlock *srb=NULL; 2091 u_int32_t workingsrb_startindex, workingsrb_doneindex; 2092 2093 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2094 workingsrb_doneindex=acb->workingsrb_doneindex; 2095 workingsrb_startindex=acb->workingsrb_startindex; 2096 srb=acb->srbworkingQ[workingsrb_startindex]; 2097 workingsrb_startindex++; 2098 workingsrb_startindex %= ARCMSR_MAX_FREESRB_NUM; 2099 if(workingsrb_doneindex!=workingsrb_startindex) { 2100 acb->workingsrb_startindex=workingsrb_startindex; 2101 } else { 2102 srb=NULL; 2103 } 2104 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2105 return(srb); 2106 } 2107 /* 2108 ************************************************************************** 2109 ************************************************************************** 2110 */ 2111 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb * pccb) 2112 { 2113 struct CMD_MESSAGE_FIELD * pcmdmessagefld; 2114 int retvalue = 0, transfer_len = 0; 2115 char *buffer; 2116 u_int32_t controlcode = (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[5] << 24 | 2117 (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[6] << 16 | 2118 (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[7] << 8 | 2119 (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[8]; 2120 /* 4 bytes: Areca io control code */ 2121 if((pccb->ccb_h.flags & CAM_SCATTER_VALID) == 0) { 2122 buffer = pccb->csio.data_ptr; 2123 transfer_len = pccb->csio.dxfer_len; 2124 } else { 2125 retvalue = ARCMSR_MESSAGE_FAIL; 2126 goto message_out; 2127 } 2128 if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) { 2129 retvalue = ARCMSR_MESSAGE_FAIL; 2130 goto message_out; 2131 } 2132 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) buffer; 2133 switch(controlcode) { 2134 case ARCMSR_MESSAGE_READ_RQBUFFER: { 2135 u_int8_t *pQbuffer; 2136 u_int8_t *ptmpQbuffer=pcmdmessagefld->messagedatabuffer; 2137 int32_t allxfer_len = 0; 2138 2139 while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex) 2140 && (allxfer_len < 1031)) { 2141 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex]; 2142 memcpy(ptmpQbuffer, pQbuffer, 1); 2143 acb->rqbuf_firstindex++; 2144 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 2145 ptmpQbuffer++; 2146 allxfer_len++; 2147 } 2148 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2149 struct QBUFFER *prbuffer; 2150 u_int8_t *iop_data; 2151 int32_t iop_len; 2152 2153 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2154 prbuffer=arcmsr_get_iop_rqbuffer(acb); 2155 iop_data = (u_int8_t *)prbuffer->data; 2156 iop_len =(u_int32_t)prbuffer->data_len; 2157 while (iop_len > 0) { 2158 pQbuffer= &acb->rqbuffer[acb->rqbuf_lastindex]; 2159 memcpy(pQbuffer, iop_data, 1); 2160 acb->rqbuf_lastindex++; 2161 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 2162 iop_data++; 2163 iop_len--; 2164 } 2165 arcmsr_iop_message_read(acb); 2166 } 2167 pcmdmessagefld->cmdmessage.Length = allxfer_len; 2168 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2169 retvalue=ARCMSR_MESSAGE_SUCCESS; 2170 } 2171 break; 2172 case ARCMSR_MESSAGE_WRITE_WQBUFFER: { 2173 int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex; 2174 u_int8_t *pQbuffer; 2175 u_int8_t *ptmpuserbuffer=pcmdmessagefld->messagedatabuffer; 2176 2177 user_len = pcmdmessagefld->cmdmessage.Length; 2178 wqbuf_lastindex = acb->wqbuf_lastindex; 2179 wqbuf_firstindex = acb->wqbuf_firstindex; 2180 if (wqbuf_lastindex != wqbuf_firstindex) { 2181 arcmsr_post_ioctldata2iop(acb); 2182 /* has error report sensedata */ 2183 if(&pccb->csio.sense_data) { 2184 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); 2185 /* Valid,ErrorCode */ 2186 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05; 2187 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */ 2188 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A; 2189 /* AdditionalSenseLength */ 2190 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20; 2191 /* AdditionalSenseCode */ 2192 } 2193 retvalue = ARCMSR_MESSAGE_FAIL; 2194 } else { 2195 my_empty_len = (wqbuf_firstindex-wqbuf_lastindex - 1) 2196 &(ARCMSR_MAX_QBUFFER - 1); 2197 if (my_empty_len >= user_len) { 2198 while (user_len > 0) { 2199 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex]; 2200 memcpy(pQbuffer, ptmpuserbuffer, 1); 2201 acb->wqbuf_lastindex++; 2202 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 2203 ptmpuserbuffer++; 2204 user_len--; 2205 } 2206 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) { 2207 acb->acb_flags &= 2208 ~ACB_F_MESSAGE_WQBUFFER_CLEARED; 2209 arcmsr_post_ioctldata2iop(acb); 2210 } 2211 } else { 2212 /* has error report sensedata */ 2213 if(&pccb->csio.sense_data) { 2214 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); 2215 /* Valid,ErrorCode */ 2216 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05; 2217 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */ 2218 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A; 2219 /* AdditionalSenseLength */ 2220 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20; 2221 /* AdditionalSenseCode */ 2222 } 2223 retvalue = ARCMSR_MESSAGE_FAIL; 2224 } 2225 } 2226 } 2227 break; 2228 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: { 2229 u_int8_t *pQbuffer = acb->rqbuffer; 2230 2231 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2232 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2233 arcmsr_iop_message_read(acb); 2234 } 2235 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 2236 acb->rqbuf_firstindex = 0; 2237 acb->rqbuf_lastindex = 0; 2238 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2239 pcmdmessagefld->cmdmessage.ReturnCode = 2240 ARCMSR_MESSAGE_RETURNCODE_OK; 2241 } 2242 break; 2243 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: { 2244 u_int8_t *pQbuffer = acb->wqbuffer; 2245 2246 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2247 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2248 arcmsr_iop_message_read(acb); 2249 } 2250 acb->acb_flags |= 2251 (ACB_F_MESSAGE_WQBUFFER_CLEARED | 2252 ACB_F_MESSAGE_WQBUFFER_READ); 2253 acb->wqbuf_firstindex = 0; 2254 acb->wqbuf_lastindex = 0; 2255 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2256 pcmdmessagefld->cmdmessage.ReturnCode = 2257 ARCMSR_MESSAGE_RETURNCODE_OK; 2258 } 2259 break; 2260 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: { 2261 u_int8_t *pQbuffer; 2262 2263 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2264 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2265 arcmsr_iop_message_read(acb); 2266 } 2267 acb->acb_flags |= 2268 (ACB_F_MESSAGE_WQBUFFER_CLEARED 2269 | ACB_F_MESSAGE_RQBUFFER_CLEARED 2270 | ACB_F_MESSAGE_WQBUFFER_READ); 2271 acb->rqbuf_firstindex = 0; 2272 acb->rqbuf_lastindex = 0; 2273 acb->wqbuf_firstindex = 0; 2274 acb->wqbuf_lastindex = 0; 2275 pQbuffer = acb->rqbuffer; 2276 memset(pQbuffer, 0, sizeof (struct QBUFFER)); 2277 pQbuffer = acb->wqbuffer; 2278 memset(pQbuffer, 0, sizeof (struct QBUFFER)); 2279 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2280 } 2281 break; 2282 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: { 2283 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F; 2284 } 2285 break; 2286 case ARCMSR_MESSAGE_SAY_HELLO: { 2287 int8_t * hello_string = "Hello! I am ARCMSR"; 2288 2289 memcpy(pcmdmessagefld->messagedatabuffer, hello_string 2290 , (int16_t)strlen(hello_string)); 2291 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2292 } 2293 break; 2294 case ARCMSR_MESSAGE_SAY_GOODBYE: 2295 arcmsr_iop_parking(acb); 2296 break; 2297 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: 2298 arcmsr_flush_adapter_cache(acb); 2299 break; 2300 default: 2301 retvalue = ARCMSR_MESSAGE_FAIL; 2302 } 2303 message_out: 2304 return retvalue; 2305 } 2306 /* 2307 ********************************************************************* 2308 ********************************************************************* 2309 */ 2310 static void arcmsr_execute_srb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 2311 { 2312 struct CommandControlBlock *srb=(struct CommandControlBlock *)arg; 2313 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)srb->acb; 2314 union ccb * pccb; 2315 int target, lun; 2316 2317 pccb=srb->pccb; 2318 target=pccb->ccb_h.target_id; 2319 lun=pccb->ccb_h.target_lun; 2320 #ifdef ARCMSR_DEBUG1 2321 acb->pktRequestCount++; 2322 #endif 2323 if(error != 0) { 2324 if(error != EFBIG) { 2325 printf("arcmsr%d: unexpected error %x" 2326 " returned from 'bus_dmamap_load' \n" 2327 , acb->pci_unit, error); 2328 } 2329 if((pccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_INPROG) { 2330 pccb->ccb_h.status |= CAM_REQ_TOO_BIG; 2331 } 2332 arcmsr_srb_complete(srb, 0); 2333 return; 2334 } 2335 if(nseg > ARCMSR_MAX_SG_ENTRIES) { 2336 pccb->ccb_h.status |= CAM_REQ_TOO_BIG; 2337 arcmsr_srb_complete(srb, 0); 2338 return; 2339 } 2340 if(acb->acb_flags & ACB_F_BUS_RESET) { 2341 printf("arcmsr%d: bus reset and return busy \n", acb->pci_unit); 2342 pccb->ccb_h.status |= CAM_SCSI_BUS_RESET; 2343 arcmsr_srb_complete(srb, 0); 2344 return; 2345 } 2346 if(acb->devstate[target][lun]==ARECA_RAID_GONE) { 2347 u_int8_t block_cmd, cmd; 2348 2349 cmd = pccb->csio.cdb_io.cdb_bytes[0]; 2350 block_cmd= cmd & 0x0f; 2351 if(block_cmd==0x08 || block_cmd==0x0a) { 2352 printf("arcmsr%d:block 'read/write' command " 2353 "with gone raid volume Cmd=0x%2x, TargetId=%d, Lun=%d \n" 2354 , acb->pci_unit, cmd, target, lun); 2355 pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 2356 arcmsr_srb_complete(srb, 0); 2357 return; 2358 } 2359 } 2360 if((pccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_INPROG) { 2361 if(nseg != 0) { 2362 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap); 2363 } 2364 arcmsr_srb_complete(srb, 0); 2365 return; 2366 } 2367 if(acb->srboutstandingcount >= ARCMSR_MAX_OUTSTANDING_CMD) { 2368 xpt_freeze_simq(acb->psim, 1); 2369 pccb->ccb_h.status = CAM_REQUEUE_REQ; 2370 acb->acb_flags |= ACB_F_CAM_DEV_QFRZN; 2371 arcmsr_srb_complete(srb, 0); 2372 return; 2373 } 2374 pccb->ccb_h.status |= CAM_SIM_QUEUED; 2375 arcmsr_build_srb(srb, dm_segs, nseg); 2376 arcmsr_post_srb(acb, srb); 2377 if (pccb->ccb_h.timeout != CAM_TIME_INFINITY) 2378 { 2379 arcmsr_callout_init(&srb->ccb_callout); 2380 callout_reset(&srb->ccb_callout, (pccb->ccb_h.timeout * hz ) / 1000, arcmsr_srb_timeout, srb); 2381 srb->srb_flags |= SRB_FLAG_TIMER_START; 2382 } 2383 return; 2384 } 2385 /* 2386 ***************************************************************************************** 2387 ***************************************************************************************** 2388 */ 2389 static u_int8_t arcmsr_seek_cmd2abort(union ccb * abortccb) 2390 { 2391 struct CommandControlBlock *srb; 2392 struct AdapterControlBlock *acb=(struct AdapterControlBlock *) abortccb->ccb_h.arcmsr_ccbacb_ptr; 2393 u_int32_t intmask_org; 2394 int i=0; 2395 2396 acb->num_aborts++; 2397 /* 2398 *************************************************************************** 2399 ** It is the upper layer do abort command this lock just prior to calling us. 2400 ** First determine if we currently own this command. 2401 ** Start by searching the device queue. If not found 2402 ** at all, and the system wanted us to just abort the 2403 ** command return success. 2404 *************************************************************************** 2405 */ 2406 if(acb->srboutstandingcount!=0) { 2407 /* disable all outbound interrupt */ 2408 intmask_org=arcmsr_disable_allintr(acb); 2409 for(i=0;i<ARCMSR_MAX_FREESRB_NUM;i++) { 2410 srb=acb->psrb_pool[i]; 2411 if(srb->srb_state==ARCMSR_SRB_START) { 2412 if(srb->pccb==abortccb) { 2413 srb->srb_state=ARCMSR_SRB_ABORTED; 2414 printf("arcmsr%d:scsi id=%d lun=%d abort srb '%p'" 2415 "outstanding command \n" 2416 , acb->pci_unit, abortccb->ccb_h.target_id 2417 , abortccb->ccb_h.target_lun, srb); 2418 arcmsr_polling_srbdone(acb, srb); 2419 /* enable outbound Post Queue, outbound doorbell Interrupt */ 2420 arcmsr_enable_allintr(acb, intmask_org); 2421 return (TRUE); 2422 } 2423 } 2424 } 2425 /* enable outbound Post Queue, outbound doorbell Interrupt */ 2426 arcmsr_enable_allintr(acb, intmask_org); 2427 } 2428 return(FALSE); 2429 } 2430 /* 2431 **************************************************************************** 2432 **************************************************************************** 2433 */ 2434 static void arcmsr_bus_reset(struct AdapterControlBlock *acb) 2435 { 2436 int retry=0; 2437 2438 acb->num_resets++; 2439 acb->acb_flags |=ACB_F_BUS_RESET; 2440 while(acb->srboutstandingcount!=0 && retry < 400) { 2441 arcmsr_interrupt(acb); 2442 UDELAY(25000); 2443 retry++; 2444 } 2445 arcmsr_iop_reset(acb); 2446 acb->acb_flags &= ~ACB_F_BUS_RESET; 2447 return; 2448 } 2449 /* 2450 ************************************************************************** 2451 ************************************************************************** 2452 */ 2453 static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb, 2454 union ccb * pccb) 2455 { 2456 pccb->ccb_h.status |= CAM_REQ_CMP; 2457 switch (pccb->csio.cdb_io.cdb_bytes[0]) { 2458 case INQUIRY: { 2459 unsigned char inqdata[36]; 2460 char *buffer=pccb->csio.data_ptr; 2461 2462 if (pccb->ccb_h.target_lun) { 2463 pccb->ccb_h.status |= CAM_SEL_TIMEOUT; 2464 xpt_done(pccb); 2465 return; 2466 } 2467 inqdata[0] = T_PROCESSOR; /* Periph Qualifier & Periph Dev Type */ 2468 inqdata[1] = 0; /* rem media bit & Dev Type Modifier */ 2469 inqdata[2] = 0; /* ISO, ECMA, & ANSI versions */ 2470 inqdata[3] = 0; 2471 inqdata[4] = 31; /* length of additional data */ 2472 inqdata[5] = 0; 2473 inqdata[6] = 0; 2474 inqdata[7] = 0; 2475 strncpy(&inqdata[8], "Areca ", 8); /* Vendor Identification */ 2476 strncpy(&inqdata[16], "RAID controller ", 16); /* Product Identification */ 2477 strncpy(&inqdata[32], "R001", 4); /* Product Revision */ 2478 memcpy(buffer, inqdata, sizeof(inqdata)); 2479 xpt_done(pccb); 2480 } 2481 break; 2482 case WRITE_BUFFER: 2483 case READ_BUFFER: { 2484 if (arcmsr_iop_message_xfer(acb, pccb)) { 2485 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 2486 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 2487 } 2488 xpt_done(pccb); 2489 } 2490 break; 2491 default: 2492 xpt_done(pccb); 2493 } 2494 } 2495 /* 2496 ********************************************************************* 2497 ********************************************************************* 2498 */ 2499 static void arcmsr_action(struct cam_sim * psim, union ccb * pccb) 2500 { 2501 struct AdapterControlBlock * acb; 2502 2503 acb=(struct AdapterControlBlock *) cam_sim_softc(psim); 2504 if(acb==NULL) { 2505 pccb->ccb_h.status |= CAM_REQ_INVALID; 2506 xpt_done(pccb); 2507 return; 2508 } 2509 switch (pccb->ccb_h.func_code) { 2510 case XPT_SCSI_IO: { 2511 struct CommandControlBlock *srb; 2512 int target=pccb->ccb_h.target_id; 2513 2514 if(target == 16) { 2515 /* virtual device for iop message transfer */ 2516 arcmsr_handle_virtual_command(acb, pccb); 2517 return; 2518 } 2519 if((srb=arcmsr_get_freesrb(acb)) == NULL) { 2520 pccb->ccb_h.status |= CAM_RESRC_UNAVAIL; 2521 xpt_done(pccb); 2522 return; 2523 } 2524 pccb->ccb_h.arcmsr_ccbsrb_ptr=srb; 2525 pccb->ccb_h.arcmsr_ccbacb_ptr=acb; 2526 srb->pccb=pccb; 2527 if((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 2528 if(!(pccb->ccb_h.flags & CAM_SCATTER_VALID)) { 2529 /* Single buffer */ 2530 if(!(pccb->ccb_h.flags & CAM_DATA_PHYS)) { 2531 /* Buffer is virtual */ 2532 u_int32_t error, s; 2533 2534 s=splsoftvm(); 2535 error = bus_dmamap_load(acb->dm_segs_dmat 2536 , srb->dm_segs_dmamap 2537 , pccb->csio.data_ptr 2538 , pccb->csio.dxfer_len 2539 , arcmsr_execute_srb, srb, /*flags*/0); 2540 if(error == EINPROGRESS) { 2541 xpt_freeze_simq(acb->psim, 1); 2542 pccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2543 } 2544 splx(s); 2545 } 2546 else { /* Buffer is physical */ 2547 #ifdef PAE 2548 panic("arcmsr: CAM_DATA_PHYS not supported"); 2549 #else 2550 struct bus_dma_segment seg; 2551 2552 seg.ds_addr = (bus_addr_t)pccb->csio.data_ptr; 2553 seg.ds_len = pccb->csio.dxfer_len; 2554 arcmsr_execute_srb(srb, &seg, 1, 0); 2555 #endif 2556 } 2557 } else { 2558 /* Scatter/gather list */ 2559 struct bus_dma_segment *segs; 2560 2561 if((pccb->ccb_h.flags & CAM_SG_LIST_PHYS) == 0 2562 || (pccb->ccb_h.flags & CAM_DATA_PHYS) != 0) { 2563 pccb->ccb_h.status |= CAM_PROVIDE_FAIL; 2564 xpt_done(pccb); 2565 free(srb, M_DEVBUF); 2566 return; 2567 } 2568 segs=(struct bus_dma_segment *)pccb->csio.data_ptr; 2569 arcmsr_execute_srb(srb, segs, pccb->csio.sglist_cnt, 0); 2570 } 2571 } else { 2572 arcmsr_execute_srb(srb, NULL, 0, 0); 2573 } 2574 break; 2575 } 2576 case XPT_TARGET_IO: { 2577 /* target mode not yet support vendor specific commands. */ 2578 pccb->ccb_h.status |= CAM_REQ_CMP; 2579 xpt_done(pccb); 2580 break; 2581 } 2582 case XPT_PATH_INQ: { 2583 struct ccb_pathinq *cpi= &pccb->cpi; 2584 2585 cpi->version_num=1; 2586 cpi->hba_inquiry=PI_SDTR_ABLE | PI_TAG_ABLE; 2587 cpi->target_sprt=0; 2588 cpi->hba_misc=0; 2589 cpi->hba_eng_cnt=0; 2590 cpi->max_target=ARCMSR_MAX_TARGETID; /* 0-16 */ 2591 cpi->max_lun=ARCMSR_MAX_TARGETLUN; /* 0-7 */ 2592 cpi->initiator_id=ARCMSR_SCSI_INITIATOR_ID; /* 255 */ 2593 cpi->bus_id=cam_sim_bus(psim); 2594 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2595 strncpy(cpi->hba_vid, "ARCMSR", HBA_IDLEN); 2596 strncpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN); 2597 cpi->unit_number=cam_sim_unit(psim); 2598 #ifdef CAM_NEW_TRAN_CODE 2599 cpi->transport = XPORT_SPI; 2600 cpi->transport_version = 2; 2601 cpi->protocol = PROTO_SCSI; 2602 cpi->protocol_version = SCSI_REV_2; 2603 #endif 2604 cpi->ccb_h.status |= CAM_REQ_CMP; 2605 xpt_done(pccb); 2606 break; 2607 } 2608 case XPT_ABORT: { 2609 union ccb *pabort_ccb; 2610 2611 pabort_ccb=pccb->cab.abort_ccb; 2612 switch (pabort_ccb->ccb_h.func_code) { 2613 case XPT_ACCEPT_TARGET_IO: 2614 case XPT_IMMED_NOTIFY: 2615 case XPT_CONT_TARGET_IO: 2616 if(arcmsr_seek_cmd2abort(pabort_ccb)==TRUE) { 2617 pabort_ccb->ccb_h.status |= CAM_REQ_ABORTED; 2618 xpt_done(pabort_ccb); 2619 pccb->ccb_h.status |= CAM_REQ_CMP; 2620 } else { 2621 xpt_print_path(pabort_ccb->ccb_h.path); 2622 printf("Not found\n"); 2623 pccb->ccb_h.status |= CAM_PATH_INVALID; 2624 } 2625 break; 2626 case XPT_SCSI_IO: 2627 pccb->ccb_h.status |= CAM_UA_ABORT; 2628 break; 2629 default: 2630 pccb->ccb_h.status |= CAM_REQ_INVALID; 2631 break; 2632 } 2633 xpt_done(pccb); 2634 break; 2635 } 2636 case XPT_RESET_BUS: 2637 case XPT_RESET_DEV: { 2638 u_int32_t i; 2639 2640 arcmsr_bus_reset(acb); 2641 for (i=0; i < 500; i++) { 2642 DELAY(1000); 2643 } 2644 pccb->ccb_h.status |= CAM_REQ_CMP; 2645 xpt_done(pccb); 2646 break; 2647 } 2648 case XPT_TERM_IO: { 2649 pccb->ccb_h.status |= CAM_REQ_INVALID; 2650 xpt_done(pccb); 2651 break; 2652 } 2653 case XPT_GET_TRAN_SETTINGS: { 2654 struct ccb_trans_settings *cts; 2655 2656 if(pccb->ccb_h.target_id == 16) { 2657 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 2658 xpt_done(pccb); 2659 break; 2660 } 2661 cts= &pccb->cts; 2662 #ifdef CAM_NEW_TRAN_CODE 2663 { 2664 struct ccb_trans_settings_scsi *scsi; 2665 struct ccb_trans_settings_spi *spi; 2666 2667 scsi = &cts->proto_specific.scsi; 2668 spi = &cts->xport_specific.spi; 2669 cts->protocol = PROTO_SCSI; 2670 cts->protocol_version = SCSI_REV_2; 2671 cts->transport = XPORT_SPI; 2672 cts->transport_version = 2; 2673 spi->flags = CTS_SPI_FLAGS_DISC_ENB; 2674 spi->sync_period=3; 2675 spi->sync_offset=32; 2676 spi->bus_width=MSG_EXT_WDTR_BUS_16_BIT; 2677 scsi->flags = CTS_SCSI_FLAGS_TAG_ENB; 2678 spi->valid = CTS_SPI_VALID_DISC 2679 | CTS_SPI_VALID_SYNC_RATE 2680 | CTS_SPI_VALID_SYNC_OFFSET 2681 | CTS_SPI_VALID_BUS_WIDTH; 2682 scsi->valid = CTS_SCSI_VALID_TQ; 2683 } 2684 #else 2685 { 2686 cts->flags=(CCB_TRANS_DISC_ENB | CCB_TRANS_TAG_ENB); 2687 cts->sync_period=3; 2688 cts->sync_offset=32; 2689 cts->bus_width=MSG_EXT_WDTR_BUS_16_BIT; 2690 cts->valid=CCB_TRANS_SYNC_RATE_VALID | 2691 CCB_TRANS_SYNC_OFFSET_VALID | 2692 CCB_TRANS_BUS_WIDTH_VALID | 2693 CCB_TRANS_DISC_VALID | 2694 CCB_TRANS_TQ_VALID; 2695 } 2696 #endif 2697 pccb->ccb_h.status |= CAM_REQ_CMP; 2698 xpt_done(pccb); 2699 break; 2700 } 2701 case XPT_SET_TRAN_SETTINGS: { 2702 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 2703 xpt_done(pccb); 2704 break; 2705 } 2706 case XPT_CALC_GEOMETRY: { 2707 struct ccb_calc_geometry *ccg; 2708 u_int32_t size_mb; 2709 u_int32_t secs_per_cylinder; 2710 2711 if(pccb->ccb_h.target_id == 16) { 2712 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 2713 xpt_done(pccb); 2714 break; 2715 } 2716 ccg= &pccb->ccg; 2717 if (ccg->block_size == 0) { 2718 pccb->ccb_h.status = CAM_REQ_INVALID; 2719 xpt_done(pccb); 2720 break; 2721 } 2722 if(((1024L * 1024L)/ccg->block_size) < 0) { 2723 pccb->ccb_h.status = CAM_REQ_INVALID; 2724 xpt_done(pccb); 2725 break; 2726 } 2727 size_mb=ccg->volume_size/((1024L * 1024L)/ccg->block_size); 2728 if(size_mb > 1024 ) { 2729 ccg->heads=255; 2730 ccg->secs_per_track=63; 2731 } else { 2732 ccg->heads=64; 2733 ccg->secs_per_track=32; 2734 } 2735 secs_per_cylinder=ccg->heads * ccg->secs_per_track; 2736 ccg->cylinders=ccg->volume_size / secs_per_cylinder; 2737 pccb->ccb_h.status |= CAM_REQ_CMP; 2738 xpt_done(pccb); 2739 break; 2740 } 2741 default: 2742 pccb->ccb_h.status |= CAM_REQ_INVALID; 2743 xpt_done(pccb); 2744 break; 2745 } 2746 return; 2747 } 2748 /* 2749 ********************************************************************** 2750 ********************************************************************** 2751 */ 2752 static void arcmsr_start_hba_bgrb(struct AdapterControlBlock *acb) 2753 { 2754 acb->acb_flags |= ACB_F_MSG_START_BGRB; 2755 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 2756 if(!arcmsr_hba_wait_msgint_ready(acb)) { 2757 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 2758 } 2759 return; 2760 } 2761 /* 2762 ********************************************************************** 2763 ********************************************************************** 2764 */ 2765 static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb) 2766 { 2767 acb->acb_flags |= ACB_F_MSG_START_BGRB; 2768 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_START_BGRB); 2769 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 2770 printf( "arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 2771 } 2772 return; 2773 } 2774 /* 2775 ********************************************************************** 2776 ********************************************************************** 2777 */ 2778 static void arcmsr_start_hbc_bgrb(struct AdapterControlBlock *acb) 2779 { 2780 acb->acb_flags |= ACB_F_MSG_START_BGRB; 2781 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 2782 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 2783 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 2784 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 2785 } 2786 return; 2787 } 2788 /* 2789 ********************************************************************** 2790 ********************************************************************** 2791 */ 2792 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb) 2793 { 2794 switch (acb->adapter_type) { 2795 case ACB_ADAPTER_TYPE_A: 2796 arcmsr_start_hba_bgrb(acb); 2797 break; 2798 case ACB_ADAPTER_TYPE_B: 2799 arcmsr_start_hbb_bgrb(acb); 2800 break; 2801 case ACB_ADAPTER_TYPE_C: 2802 arcmsr_start_hbc_bgrb(acb); 2803 break; 2804 } 2805 return; 2806 } 2807 /* 2808 ********************************************************************** 2809 ** 2810 ********************************************************************** 2811 */ 2812 static void arcmsr_polling_hba_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 2813 { 2814 struct CommandControlBlock *srb; 2815 u_int32_t flag_srb, outbound_intstatus, poll_srb_done=0, poll_count=0; 2816 u_int16_t error; 2817 2818 polling_ccb_retry: 2819 poll_count++; 2820 outbound_intstatus=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 2821 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus); /*clear interrupt*/ 2822 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2823 while(1) { 2824 if((flag_srb=CHIP_REG_READ32(HBA_MessageUnit, 2825 0, outbound_queueport))==0xFFFFFFFF) { 2826 if(poll_srb_done) { 2827 break;/*chip FIFO no ccb for completion already*/ 2828 } else { 2829 UDELAY(25000); 2830 if ((poll_count > 100) && (poll_srb != NULL)) { 2831 break; 2832 } 2833 goto polling_ccb_retry; 2834 } 2835 } 2836 /* check if command done with no error*/ 2837 srb=(struct CommandControlBlock *) 2838 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 2839 error=(flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 2840 poll_srb_done = (srb==poll_srb) ? 1:0; 2841 if((srb->acb!=acb) || (srb->srb_state!=ARCMSR_SRB_START)) { 2842 if(srb->srb_state==ARCMSR_SRB_ABORTED) { 2843 printf("arcmsr%d: scsi id=%d lun=%d srb='%p'" 2844 "poll command abort successfully \n" 2845 , acb->pci_unit 2846 , srb->pccb->ccb_h.target_id 2847 , srb->pccb->ccb_h.target_lun, srb); 2848 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 2849 arcmsr_srb_complete(srb, 1); 2850 continue; 2851 } 2852 printf("arcmsr%d: polling get an illegal srb command done srb='%p'" 2853 "srboutstandingcount=%d \n" 2854 , acb->pci_unit 2855 , srb, acb->srboutstandingcount); 2856 continue; 2857 } 2858 arcmsr_report_srb_state(acb, srb, error); 2859 } /*drain reply FIFO*/ 2860 return; 2861 } 2862 /* 2863 ********************************************************************** 2864 ** 2865 ********************************************************************** 2866 */ 2867 static void arcmsr_polling_hbb_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 2868 { 2869 struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu; 2870 struct CommandControlBlock *srb; 2871 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 2872 int index; 2873 u_int16_t error; 2874 2875 polling_ccb_retry: 2876 poll_count++; 2877 CHIP_REG_WRITE32(HBB_DOORBELL, 2878 0, iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */ 2879 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2880 while(1) { 2881 index=phbbmu->doneq_index; 2882 if((flag_srb=phbbmu->done_qbuffer[index]) == 0) { 2883 if(poll_srb_done) { 2884 break;/*chip FIFO no ccb for completion already*/ 2885 } else { 2886 UDELAY(25000); 2887 if ((poll_count > 100) && (poll_srb != NULL)) { 2888 break; 2889 } 2890 goto polling_ccb_retry; 2891 } 2892 } 2893 phbbmu->done_qbuffer[index]=0; 2894 index++; 2895 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 2896 phbbmu->doneq_index=index; 2897 /* check if command done with no error*/ 2898 srb=(struct CommandControlBlock *) 2899 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 2900 error=(flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 2901 poll_srb_done = (srb==poll_srb) ? 1:0; 2902 if((srb->acb!=acb) || (srb->srb_state!=ARCMSR_SRB_START)) { 2903 if(srb->srb_state==ARCMSR_SRB_ABORTED) { 2904 printf("arcmsr%d: scsi id=%d lun=%d srb='%p'" 2905 "poll command abort successfully \n" 2906 , acb->pci_unit 2907 , srb->pccb->ccb_h.target_id 2908 , srb->pccb->ccb_h.target_lun, srb); 2909 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 2910 arcmsr_srb_complete(srb, 1); 2911 continue; 2912 } 2913 printf("arcmsr%d: polling get an illegal srb command done srb='%p'" 2914 "srboutstandingcount=%d \n" 2915 , acb->pci_unit 2916 , srb, acb->srboutstandingcount); 2917 continue; 2918 } 2919 arcmsr_report_srb_state(acb, srb, error); 2920 } /*drain reply FIFO*/ 2921 return; 2922 } 2923 /* 2924 ********************************************************************** 2925 ** 2926 ********************************************************************** 2927 */ 2928 static void arcmsr_polling_hbc_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 2929 { 2930 struct CommandControlBlock *srb; 2931 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 2932 u_int16_t error; 2933 2934 polling_ccb_retry: 2935 poll_count++; 2936 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2937 while(1) { 2938 if(!(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)) { 2939 if(poll_srb_done) { 2940 break;/*chip FIFO no ccb for completion already*/ 2941 } else { 2942 UDELAY(25000); 2943 if ((poll_count > 100) && (poll_srb != NULL)) { 2944 break; 2945 } 2946 if (acb->srboutstandingcount == 0) { 2947 break; 2948 } 2949 goto polling_ccb_retry; 2950 } 2951 } 2952 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 2953 /* check if command done with no error*/ 2954 srb=(struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/ 2955 error=(flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE; 2956 if (poll_srb != NULL) 2957 poll_srb_done = (srb==poll_srb) ? 1:0; 2958 if((srb->acb!=acb) || (srb->srb_state!=ARCMSR_SRB_START)) { 2959 if(srb->srb_state==ARCMSR_SRB_ABORTED) { 2960 printf("arcmsr%d: scsi id=%d lun=%d srb='%p'poll command abort successfully \n" 2961 , acb->pci_unit, srb->pccb->ccb_h.target_id, srb->pccb->ccb_h.target_lun, srb); 2962 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 2963 arcmsr_srb_complete(srb, 1); 2964 continue; 2965 } 2966 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 2967 , acb->pci_unit, srb, acb->srboutstandingcount); 2968 continue; 2969 } 2970 arcmsr_report_srb_state(acb, srb, error); 2971 } /*drain reply FIFO*/ 2972 return; 2973 } 2974 /* 2975 ********************************************************************** 2976 ********************************************************************** 2977 */ 2978 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 2979 { 2980 switch (acb->adapter_type) { 2981 case ACB_ADAPTER_TYPE_A: { 2982 arcmsr_polling_hba_srbdone(acb, poll_srb); 2983 } 2984 break; 2985 case ACB_ADAPTER_TYPE_B: { 2986 arcmsr_polling_hbb_srbdone(acb, poll_srb); 2987 } 2988 break; 2989 case ACB_ADAPTER_TYPE_C: { 2990 arcmsr_polling_hbc_srbdone(acb, poll_srb); 2991 } 2992 break; 2993 } 2994 } 2995 /* 2996 ********************************************************************** 2997 ********************************************************************** 2998 */ 2999 static void arcmsr_get_hba_config(struct AdapterControlBlock *acb) 3000 { 3001 char *acb_firm_model=acb->firm_model; 3002 char *acb_firm_version=acb->firm_version; 3003 char *acb_device_map = acb->device_map; 3004 size_t iop_firm_model=offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3005 size_t iop_firm_version=offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3006 size_t iop_device_map = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3007 int i; 3008 3009 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3010 if(!arcmsr_hba_wait_msgint_ready(acb)) { 3011 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3012 } 3013 i=0; 3014 while(i<8) { 3015 *acb_firm_model=bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3016 /* 8 bytes firm_model, 15, 60-67*/ 3017 acb_firm_model++; 3018 i++; 3019 } 3020 i=0; 3021 while(i<16) { 3022 *acb_firm_version=bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3023 /* 16 bytes firm_version, 17, 68-83*/ 3024 acb_firm_version++; 3025 i++; 3026 } 3027 i=0; 3028 while(i<16) { 3029 *acb_device_map=bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3030 acb_device_map++; 3031 i++; 3032 } 3033 printf("ARECA RAID ADAPTER%d: %s \n", acb->pci_unit, ARCMSR_DRIVER_VERSION); 3034 printf("ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n", acb->pci_unit, acb->firm_version); 3035 acb->firm_request_len=CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3036 acb->firm_numbers_queue=CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3037 acb->firm_sdram_size=CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3038 acb->firm_ide_channels=CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3039 acb->firm_cfg_version=CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3040 return; 3041 } 3042 /* 3043 ********************************************************************** 3044 ********************************************************************** 3045 */ 3046 static void arcmsr_get_hbb_config(struct AdapterControlBlock *acb) 3047 { 3048 char *acb_firm_model=acb->firm_model; 3049 char *acb_firm_version=acb->firm_version; 3050 char *acb_device_map = acb->device_map; 3051 size_t iop_firm_model=offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3052 size_t iop_firm_version=offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3053 size_t iop_device_map = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3054 int i; 3055 3056 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG); 3057 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3058 printf( "arcmsr%d: wait" "'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3059 } 3060 i=0; 3061 while(i<8) { 3062 *acb_firm_model=bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_model+i); 3063 /* 8 bytes firm_model, 15, 60-67*/ 3064 acb_firm_model++; 3065 i++; 3066 } 3067 i=0; 3068 while(i<16) { 3069 *acb_firm_version=bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_version+i); 3070 /* 16 bytes firm_version, 17, 68-83*/ 3071 acb_firm_version++; 3072 i++; 3073 } 3074 i=0; 3075 while(i<16) { 3076 *acb_device_map=bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_device_map+i); 3077 acb_device_map++; 3078 i++; 3079 } 3080 printf("ARECA RAID ADAPTER%d: %s \n", acb->pci_unit, ARCMSR_DRIVER_VERSION); 3081 printf("ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n", acb->pci_unit, acb->firm_version); 3082 acb->firm_request_len=CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3083 acb->firm_numbers_queue=CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3084 acb->firm_sdram_size=CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3085 acb->firm_ide_channels=CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3086 acb->firm_cfg_version=CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3087 return; 3088 } 3089 /* 3090 ********************************************************************** 3091 ********************************************************************** 3092 */ 3093 static void arcmsr_get_hbc_config(struct AdapterControlBlock *acb) 3094 { 3095 char *acb_firm_model=acb->firm_model; 3096 char *acb_firm_version=acb->firm_version; 3097 char *acb_device_map = acb->device_map; 3098 size_t iop_firm_model=offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3099 size_t iop_firm_version=offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3100 size_t iop_device_map = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3101 int i; 3102 3103 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3104 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3105 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 3106 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3107 } 3108 i=0; 3109 while(i<8) { 3110 *acb_firm_model=bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3111 /* 8 bytes firm_model, 15, 60-67*/ 3112 acb_firm_model++; 3113 i++; 3114 } 3115 i=0; 3116 while(i<16) { 3117 *acb_firm_version=bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3118 /* 16 bytes firm_version, 17, 68-83*/ 3119 acb_firm_version++; 3120 i++; 3121 } 3122 i=0; 3123 while(i<16) { 3124 *acb_device_map=bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3125 acb_device_map++; 3126 i++; 3127 } 3128 printf("ARECA RAID ADAPTER%d: %s \n", acb->pci_unit, ARCMSR_DRIVER_VERSION); 3129 printf("ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n", acb->pci_unit, acb->firm_version); 3130 acb->firm_request_len =CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3131 acb->firm_numbers_queue =CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3132 acb->firm_sdram_size =CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3133 acb->firm_ide_channels =CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3134 acb->firm_cfg_version =CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3135 return; 3136 } 3137 /* 3138 ********************************************************************** 3139 ********************************************************************** 3140 */ 3141 static void arcmsr_get_firmware_spec(struct AdapterControlBlock *acb) 3142 { 3143 switch (acb->adapter_type) { 3144 case ACB_ADAPTER_TYPE_A: { 3145 arcmsr_get_hba_config(acb); 3146 } 3147 break; 3148 case ACB_ADAPTER_TYPE_B: { 3149 arcmsr_get_hbb_config(acb); 3150 } 3151 break; 3152 case ACB_ADAPTER_TYPE_C: { 3153 arcmsr_get_hbc_config(acb); 3154 } 3155 break; 3156 } 3157 return; 3158 } 3159 /* 3160 ********************************************************************** 3161 ********************************************************************** 3162 */ 3163 static void arcmsr_wait_firmware_ready( struct AdapterControlBlock *acb) 3164 { 3165 int timeout=0; 3166 3167 switch (acb->adapter_type) { 3168 case ACB_ADAPTER_TYPE_A: { 3169 while ((CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0) 3170 { 3171 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 3172 { 3173 printf( "arcmsr%d:timed out waiting for firmware \n", acb->pci_unit); 3174 return; 3175 } 3176 UDELAY(15000); /* wait 15 milli-seconds */ 3177 } 3178 } 3179 break; 3180 case ACB_ADAPTER_TYPE_B: { 3181 while ((CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & ARCMSR_MESSAGE_FIRMWARE_OK) == 0) 3182 { 3183 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 3184 { 3185 printf( "arcmsr%d: timed out waiting for firmware \n", acb->pci_unit); 3186 return; 3187 } 3188 UDELAY(15000); /* wait 15 milli-seconds */ 3189 } 3190 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 3191 } 3192 break; 3193 case ACB_ADAPTER_TYPE_C: { 3194 while ((CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0) 3195 { 3196 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 3197 { 3198 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 3199 return; 3200 } 3201 UDELAY(15000); /* wait 15 milli-seconds */ 3202 } 3203 } 3204 break; 3205 } 3206 return; 3207 } 3208 /* 3209 ********************************************************************** 3210 ********************************************************************** 3211 */ 3212 static void arcmsr_clear_doorbell_queue_buffer( struct AdapterControlBlock *acb) 3213 { 3214 u_int32_t outbound_doorbell; 3215 3216 switch (acb->adapter_type) { 3217 case ACB_ADAPTER_TYPE_A: { 3218 /* empty doorbell Qbuffer if door bell ringed */ 3219 outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell); 3220 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */ 3221 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK); 3222 3223 } 3224 break; 3225 case ACB_ADAPTER_TYPE_B: { 3226 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt and message state*/ 3227 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK); 3228 /* let IOP know data has been read */ 3229 } 3230 break; 3231 case ACB_ADAPTER_TYPE_C: { 3232 /* empty doorbell Qbuffer if door bell ringed */ 3233 outbound_doorbell = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell); 3234 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell); /*clear doorbell interrupt */ 3235 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK); 3236 3237 } 3238 break; 3239 } 3240 return; 3241 } 3242 /* 3243 ************************************************************************ 3244 ************************************************************************ 3245 */ 3246 static u_int32_t arcmsr_iop_confirm(struct AdapterControlBlock *acb) 3247 { 3248 unsigned long srb_phyaddr; 3249 u_int32_t srb_phyaddr_hi32; 3250 3251 /* 3252 ******************************************************************** 3253 ** here we need to tell iop 331 our freesrb.HighPart 3254 ** if freesrb.HighPart is not zero 3255 ******************************************************************** 3256 */ 3257 srb_phyaddr= (unsigned long) acb->srb_phyaddr.phyaddr; 3258 // srb_phyaddr_hi32=(u_int32_t) ((srb_phyaddr>>16)>>16); 3259 srb_phyaddr_hi32=acb->srb_phyaddr.B.phyadd_high; 3260 switch (acb->adapter_type) { 3261 case ACB_ADAPTER_TYPE_A: { 3262 if(srb_phyaddr_hi32!=0) { 3263 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 3264 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 3265 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 3266 if(!arcmsr_hba_wait_msgint_ready(acb)) { 3267 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 3268 return FALSE; 3269 } 3270 } 3271 } 3272 break; 3273 /* 3274 *********************************************************************** 3275 ** if adapter type B, set window of "post command Q" 3276 *********************************************************************** 3277 */ 3278 case ACB_ADAPTER_TYPE_B: { 3279 u_int32_t post_queue_phyaddr; 3280 struct HBB_MessageUnit *phbbmu; 3281 3282 phbbmu=(struct HBB_MessageUnit *)acb->pmu; 3283 phbbmu->postq_index=0; 3284 phbbmu->doneq_index=0; 3285 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_SET_POST_WINDOW); 3286 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3287 printf( "arcmsr%d: 'set window of post command Q' timeout\n", acb->pci_unit); 3288 return FALSE; 3289 } 3290 post_queue_phyaddr = srb_phyaddr + ARCMSR_SRBS_POOL_SIZE 3291 + offsetof(struct HBB_MessageUnit, post_qbuffer); 3292 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */ 3293 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1], srb_phyaddr_hi32); /* normal should be zero */ 3294 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ size (256+8)*4 */ 3295 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3], post_queue_phyaddr+1056); /* doneQ size (256+8)*4 */ 3296 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4], 1056); /* srb maxQ size must be --> [(256+8)*4] */ 3297 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_SET_CONFIG); 3298 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3299 printf( "arcmsr%d: 'set command Q window' timeout \n", acb->pci_unit); 3300 return FALSE; 3301 } 3302 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_START_DRIVER_MODE); 3303 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3304 printf( "arcmsr%d: 'start diver mode' timeout \n", acb->pci_unit); 3305 return FALSE; 3306 } 3307 } 3308 break; 3309 case ACB_ADAPTER_TYPE_C: { 3310 if(srb_phyaddr_hi32!=0) { 3311 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 3312 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 3313 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 3314 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3315 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 3316 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 3317 return FALSE; 3318 } 3319 } 3320 } 3321 break; 3322 } 3323 return TRUE; 3324 } 3325 /* 3326 ************************************************************************ 3327 ************************************************************************ 3328 */ 3329 static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb) 3330 { 3331 switch (acb->adapter_type) 3332 { 3333 case ACB_ADAPTER_TYPE_A: 3334 case ACB_ADAPTER_TYPE_C: 3335 break; 3336 case ACB_ADAPTER_TYPE_B: { 3337 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell,ARCMSR_MESSAGE_ACTIVE_EOI_MODE); 3338 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3339 printf( "arcmsr%d: 'iop enable eoi mode' timeout \n", acb->pci_unit); 3340 3341 return; 3342 } 3343 } 3344 break; 3345 } 3346 return; 3347 } 3348 /* 3349 ********************************************************************** 3350 ********************************************************************** 3351 */ 3352 static void arcmsr_iop_init(struct AdapterControlBlock *acb) 3353 { 3354 u_int32_t intmask_org; 3355 3356 /* disable all outbound interrupt */ 3357 intmask_org=arcmsr_disable_allintr(acb); 3358 arcmsr_wait_firmware_ready(acb); 3359 arcmsr_iop_confirm(acb); 3360 arcmsr_get_firmware_spec(acb); 3361 /*start background rebuild*/ 3362 arcmsr_start_adapter_bgrb(acb); 3363 /* empty doorbell Qbuffer if door bell ringed */ 3364 arcmsr_clear_doorbell_queue_buffer(acb); 3365 arcmsr_enable_eoi_mode(acb); 3366 /* enable outbound Post Queue, outbound doorbell Interrupt */ 3367 arcmsr_enable_allintr(acb, intmask_org); 3368 acb->acb_flags |=ACB_F_IOP_INITED; 3369 return; 3370 } 3371 /* 3372 ********************************************************************** 3373 ********************************************************************** 3374 */ 3375 static void arcmsr_map_free_srb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3376 { 3377 struct AdapterControlBlock *acb=arg; 3378 struct CommandControlBlock *srb_tmp; 3379 u_int8_t * dma_memptr; 3380 u_int32_t i; 3381 unsigned long srb_phyaddr=(unsigned long)segs->ds_addr; 3382 3383 dma_memptr=acb->uncacheptr; 3384 acb->srb_phyaddr.phyaddr=srb_phyaddr; 3385 srb_tmp=(struct CommandControlBlock *)dma_memptr; 3386 for(i=0;i<ARCMSR_MAX_FREESRB_NUM;i++) { 3387 if(bus_dmamap_create(acb->dm_segs_dmat, 3388 /*flags*/0, &srb_tmp->dm_segs_dmamap)!=0) { 3389 acb->acb_flags |= ACB_F_MAPFREESRB_FAILD; 3390 printf("arcmsr%d:" 3391 " srb dmamap bus_dmamap_create error\n", acb->pci_unit); 3392 return; 3393 } 3394 srb_tmp->cdb_shifted_phyaddr=(acb->adapter_type==ACB_ADAPTER_TYPE_C)?srb_phyaddr:(srb_phyaddr >> 5); 3395 srb_tmp->acb=acb; 3396 acb->srbworkingQ[i]=acb->psrb_pool[i]=srb_tmp; 3397 srb_phyaddr=srb_phyaddr+SRB_SIZE; 3398 srb_tmp = (struct CommandControlBlock *)((unsigned long)srb_tmp+SRB_SIZE); 3399 } 3400 acb->vir2phy_offset=(unsigned long)srb_tmp-(unsigned long)srb_phyaddr; 3401 return; 3402 } 3403 /* 3404 ************************************************************************ 3405 ** 3406 ** 3407 ************************************************************************ 3408 */ 3409 static void arcmsr_free_resource(struct AdapterControlBlock *acb) 3410 { 3411 /* remove the control device */ 3412 if(acb->ioctl_dev != NULL) { 3413 destroy_dev(acb->ioctl_dev); 3414 } 3415 bus_dmamap_unload(acb->srb_dmat, acb->srb_dmamap); 3416 bus_dmamap_destroy(acb->srb_dmat, acb->srb_dmamap); 3417 bus_dma_tag_destroy(acb->srb_dmat); 3418 bus_dma_tag_destroy(acb->dm_segs_dmat); 3419 bus_dma_tag_destroy(acb->parent_dmat); 3420 return; 3421 } 3422 /* 3423 ************************************************************************ 3424 ************************************************************************ 3425 */ 3426 static u_int32_t arcmsr_initialize(device_t dev) 3427 { 3428 struct AdapterControlBlock *acb=device_get_softc(dev); 3429 u_int16_t pci_command; 3430 int i, j,max_coherent_size; 3431 3432 switch (pci_get_devid(dev)) { 3433 case PCIDevVenIDARC1880: { 3434 acb->adapter_type=ACB_ADAPTER_TYPE_C; 3435 max_coherent_size=ARCMSR_SRBS_POOL_SIZE; 3436 } 3437 break; 3438 case PCIDevVenIDARC1200: 3439 case PCIDevVenIDARC1201: { 3440 acb->adapter_type=ACB_ADAPTER_TYPE_B; 3441 max_coherent_size=ARCMSR_SRBS_POOL_SIZE+(sizeof(struct HBB_MessageUnit)); 3442 } 3443 break; 3444 case PCIDevVenIDARC1110: 3445 case PCIDevVenIDARC1120: 3446 case PCIDevVenIDARC1130: 3447 case PCIDevVenIDARC1160: 3448 case PCIDevVenIDARC1170: 3449 case PCIDevVenIDARC1210: 3450 case PCIDevVenIDARC1220: 3451 case PCIDevVenIDARC1230: 3452 case PCIDevVenIDARC1231: 3453 case PCIDevVenIDARC1260: 3454 case PCIDevVenIDARC1261: 3455 case PCIDevVenIDARC1270: 3456 case PCIDevVenIDARC1280: 3457 case PCIDevVenIDARC1212: 3458 case PCIDevVenIDARC1222: 3459 case PCIDevVenIDARC1380: 3460 case PCIDevVenIDARC1381: 3461 case PCIDevVenIDARC1680: 3462 case PCIDevVenIDARC1681: { 3463 acb->adapter_type=ACB_ADAPTER_TYPE_A; 3464 max_coherent_size=ARCMSR_SRBS_POOL_SIZE; 3465 } 3466 break; 3467 default: { 3468 printf("arcmsr%d:" 3469 " unknown RAID adapter type \n", device_get_unit(dev)); 3470 return ENOMEM; 3471 } 3472 } 3473 if(bus_dma_tag_create( /*parent*/ NULL, 3474 /*alignemnt*/ 1, 3475 /*boundary*/ 0, 3476 /*lowaddr*/ BUS_SPACE_MAXADDR, 3477 /*highaddr*/ BUS_SPACE_MAXADDR, 3478 /*filter*/ NULL, 3479 /*filterarg*/ NULL, 3480 /*maxsize*/ BUS_SPACE_MAXSIZE_32BIT, 3481 /*nsegments*/ BUS_SPACE_UNRESTRICTED, 3482 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 3483 /*flags*/ 0, 3484 #if __FreeBSD_version >= 501102 3485 /*lockfunc*/ NULL, 3486 /*lockarg*/ NULL, 3487 #endif 3488 &acb->parent_dmat) != 0) 3489 { 3490 printf("arcmsr%d: parent_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 3491 return ENOMEM; 3492 } 3493 3494 /* Create a single tag describing a region large enough to hold all of the s/g lists we will need. */ 3495 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat, 3496 /*alignment*/ 1, 3497 /*boundary*/ 0, 3498 #ifdef PAE 3499 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 3500 #else 3501 /*lowaddr*/ BUS_SPACE_MAXADDR, 3502 #endif 3503 /*highaddr*/ BUS_SPACE_MAXADDR, 3504 /*filter*/ NULL, 3505 /*filterarg*/ NULL, 3506 /*maxsize*/ ARCMSR_MAX_SG_ENTRIES * PAGE_SIZE * ARCMSR_MAX_FREESRB_NUM, 3507 /*nsegments*/ ARCMSR_MAX_SG_ENTRIES, 3508 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 3509 /*flags*/ 0, 3510 #if __FreeBSD_version >= 501102 3511 /*lockfunc*/ busdma_lock_mutex, 3512 /*lockarg*/ &acb->qbuffer_lock, 3513 #endif 3514 &acb->dm_segs_dmat) != 0) 3515 { 3516 bus_dma_tag_destroy(acb->parent_dmat); 3517 printf("arcmsr%d: dm_segs_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 3518 return ENOMEM; 3519 } 3520 3521 /* DMA tag for our srb structures.... Allocate the freesrb memory */ 3522 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat, 3523 /*alignment*/ 0x20, 3524 /*boundary*/ 0, 3525 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 3526 /*highaddr*/ BUS_SPACE_MAXADDR, 3527 /*filter*/ NULL, 3528 /*filterarg*/ NULL, 3529 /*maxsize*/ max_coherent_size, 3530 /*nsegments*/ 1, 3531 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 3532 /*flags*/ 0, 3533 #if __FreeBSD_version >= 501102 3534 /*lockfunc*/ NULL, 3535 /*lockarg*/ NULL, 3536 #endif 3537 &acb->srb_dmat) != 0) 3538 { 3539 bus_dma_tag_destroy(acb->dm_segs_dmat); 3540 bus_dma_tag_destroy(acb->parent_dmat); 3541 printf("arcmsr%d: srb_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 3542 return ENXIO; 3543 } 3544 /* Allocation for our srbs */ 3545 if(bus_dmamem_alloc(acb->srb_dmat, (void **)&acb->uncacheptr, BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, &acb->srb_dmamap) != 0) { 3546 bus_dma_tag_destroy(acb->srb_dmat); 3547 bus_dma_tag_destroy(acb->dm_segs_dmat); 3548 bus_dma_tag_destroy(acb->parent_dmat); 3549 printf("arcmsr%d: srb_dmat bus_dmamem_alloc failure!\n", device_get_unit(dev)); 3550 return ENXIO; 3551 } 3552 /* And permanently map them */ 3553 if(bus_dmamap_load(acb->srb_dmat, acb->srb_dmamap, acb->uncacheptr, max_coherent_size, arcmsr_map_free_srb, acb, /*flags*/0)) { 3554 bus_dma_tag_destroy(acb->srb_dmat); 3555 bus_dma_tag_destroy(acb->dm_segs_dmat); 3556 bus_dma_tag_destroy(acb->parent_dmat); 3557 printf("arcmsr%d: srb_dmat bus_dmamap_load failure!\n", device_get_unit(dev)); 3558 return ENXIO; 3559 } 3560 pci_command=pci_read_config(dev, PCIR_COMMAND, 2); 3561 pci_command |= PCIM_CMD_BUSMASTEREN; 3562 pci_command |= PCIM_CMD_PERRESPEN; 3563 pci_command |= PCIM_CMD_MWRICEN; 3564 /* Enable Busmaster/Mem */ 3565 pci_command |= PCIM_CMD_MEMEN; 3566 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 3567 switch(acb->adapter_type) { 3568 case ACB_ADAPTER_TYPE_A: { 3569 u_int32_t rid0=PCIR_BAR(0); 3570 vm_offset_t mem_base0; 3571 3572 acb->sys_res_arcmsr[0]=bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, 0x1000, RF_ACTIVE); 3573 if(acb->sys_res_arcmsr[0] == NULL) { 3574 arcmsr_free_resource(acb); 3575 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 3576 return ENOMEM; 3577 } 3578 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 3579 arcmsr_free_resource(acb); 3580 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 3581 return ENXIO; 3582 } 3583 mem_base0=(vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 3584 if(mem_base0==0) { 3585 arcmsr_free_resource(acb); 3586 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 3587 return ENXIO; 3588 } 3589 acb->btag[0]=rman_get_bustag(acb->sys_res_arcmsr[0]); 3590 acb->bhandle[0]=rman_get_bushandle(acb->sys_res_arcmsr[0]); 3591 acb->pmu=(struct MessageUnit_UNION *)mem_base0; 3592 } 3593 break; 3594 case ACB_ADAPTER_TYPE_B: { 3595 struct HBB_MessageUnit *phbbmu; 3596 struct CommandControlBlock *freesrb; 3597 u_int32_t rid[]={ PCIR_BAR(0), PCIR_BAR(2) }; 3598 vm_offset_t mem_base[]={0,0}; 3599 for(i=0; i<2; i++) { 3600 if(i==0) { 3601 acb->sys_res_arcmsr[i]=bus_alloc_resource(dev,SYS_RES_MEMORY, &rid[i], 3602 0ul, ~0ul, sizeof(struct HBB_DOORBELL), RF_ACTIVE); 3603 } else { 3604 acb->sys_res_arcmsr[i]=bus_alloc_resource(dev, SYS_RES_MEMORY, &rid[i], 3605 0ul, ~0ul, sizeof(struct HBB_RWBUFFER), RF_ACTIVE); 3606 } 3607 if(acb->sys_res_arcmsr[i] == NULL) { 3608 arcmsr_free_resource(acb); 3609 printf("arcmsr%d: bus_alloc_resource %d failure!\n", device_get_unit(dev), i); 3610 return ENOMEM; 3611 } 3612 if(rman_get_start(acb->sys_res_arcmsr[i]) <= 0) { 3613 arcmsr_free_resource(acb); 3614 printf("arcmsr%d: rman_get_start %d failure!\n", device_get_unit(dev), i); 3615 return ENXIO; 3616 } 3617 mem_base[i]=(vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[i]); 3618 if(mem_base[i]==0) { 3619 arcmsr_free_resource(acb); 3620 printf("arcmsr%d: rman_get_virtual %d failure!\n", device_get_unit(dev), i); 3621 return ENXIO; 3622 } 3623 acb->btag[i]=rman_get_bustag(acb->sys_res_arcmsr[i]); 3624 acb->bhandle[i]=rman_get_bushandle(acb->sys_res_arcmsr[i]); 3625 } 3626 freesrb=(struct CommandControlBlock *)acb->uncacheptr; 3627 // acb->pmu=(struct MessageUnit_UNION *)&freesrb[ARCMSR_MAX_FREESRB_NUM]; 3628 acb->pmu=(struct MessageUnit_UNION *)((unsigned long)freesrb+ARCMSR_SRBS_POOL_SIZE); 3629 phbbmu=(struct HBB_MessageUnit *)acb->pmu; 3630 phbbmu->hbb_doorbell=(struct HBB_DOORBELL *)mem_base[0]; 3631 phbbmu->hbb_rwbuffer=(struct HBB_RWBUFFER *)mem_base[1]; 3632 } 3633 break; 3634 case ACB_ADAPTER_TYPE_C: { 3635 u_int32_t rid0=PCIR_BAR(1); 3636 vm_offset_t mem_base0; 3637 3638 acb->sys_res_arcmsr[0]=bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, sizeof(struct HBC_MessageUnit), RF_ACTIVE); 3639 if(acb->sys_res_arcmsr[0] == NULL) { 3640 arcmsr_free_resource(acb); 3641 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 3642 return ENOMEM; 3643 } 3644 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 3645 arcmsr_free_resource(acb); 3646 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 3647 return ENXIO; 3648 } 3649 mem_base0=(vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 3650 if(mem_base0==0) { 3651 arcmsr_free_resource(acb); 3652 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 3653 return ENXIO; 3654 } 3655 acb->btag[0]=rman_get_bustag(acb->sys_res_arcmsr[0]); 3656 acb->bhandle[0]=rman_get_bushandle(acb->sys_res_arcmsr[0]); 3657 acb->pmu=(struct MessageUnit_UNION *)mem_base0; 3658 } 3659 break; 3660 } 3661 if(acb->acb_flags & ACB_F_MAPFREESRB_FAILD) { 3662 arcmsr_free_resource(acb); 3663 printf("arcmsr%d: map free srb failure!\n", device_get_unit(dev)); 3664 return ENXIO; 3665 } 3666 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_RQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ); 3667 acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER; 3668 /* 3669 ******************************************************************** 3670 ** init raid volume state 3671 ******************************************************************** 3672 */ 3673 for(i=0;i<ARCMSR_MAX_TARGETID;i++) { 3674 for(j=0;j<ARCMSR_MAX_TARGETLUN;j++) { 3675 acb->devstate[i][j]=ARECA_RAID_GONE; 3676 } 3677 } 3678 arcmsr_iop_init(acb); 3679 return(0); 3680 } 3681 /* 3682 ************************************************************************ 3683 ************************************************************************ 3684 */ 3685 static int arcmsr_attach(device_t dev) 3686 { 3687 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 3688 u_int32_t unit=device_get_unit(dev); 3689 struct ccb_setasync csa; 3690 struct cam_devq *devq; /* Device Queue to use for this SIM */ 3691 struct resource *irqres; 3692 int rid; 3693 3694 if(acb == NULL) { 3695 printf("arcmsr%d: cannot allocate softc\n", unit); 3696 return (ENOMEM); 3697 } 3698 ARCMSR_LOCK_INIT(&acb->qbuffer_lock, "arcmsr Q buffer lock"); 3699 if(arcmsr_initialize(dev)) { 3700 printf("arcmsr%d: initialize failure!\n", unit); 3701 ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock); 3702 return ENXIO; 3703 } 3704 /* After setting up the adapter, map our interrupt */ 3705 rid=0; 3706 irqres=bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1, RF_SHAREABLE | RF_ACTIVE); 3707 if(irqres == NULL || 3708 #if __FreeBSD_version >= 700025 3709 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, NULL, arcmsr_intr_handler, acb, &acb->ih)) { 3710 #else 3711 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, arcmsr_intr_handler, acb, &acb->ih)) { 3712 #endif 3713 arcmsr_free_resource(acb); 3714 ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock); 3715 printf("arcmsr%d: unable to register interrupt handler!\n", unit); 3716 return ENXIO; 3717 } 3718 acb->irqres=irqres; 3719 acb->pci_dev=dev; 3720 acb->pci_unit=unit; 3721 /* 3722 * Now let the CAM generic SCSI layer find the SCSI devices on 3723 * the bus * start queue to reset to the idle loop. * 3724 * Create device queue of SIM(s) * (MAX_START_JOB - 1) : 3725 * max_sim_transactions 3726 */ 3727 devq=cam_simq_alloc(ARCMSR_MAX_START_JOB); 3728 if(devq == NULL) { 3729 arcmsr_free_resource(acb); 3730 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres); 3731 ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock); 3732 printf("arcmsr%d: cam_simq_alloc failure!\n", unit); 3733 return ENXIO; 3734 } 3735 #if __FreeBSD_version >= 700025 3736 acb->psim=cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, &acb->qbuffer_lock, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq); 3737 #else 3738 acb->psim=cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq); 3739 #endif 3740 if(acb->psim == NULL) { 3741 arcmsr_free_resource(acb); 3742 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres); 3743 cam_simq_free(devq); 3744 ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock); 3745 printf("arcmsr%d: cam_sim_alloc failure!\n", unit); 3746 return ENXIO; 3747 } 3748 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 3749 #if __FreeBSD_version >= 700044 3750 if(xpt_bus_register(acb->psim, dev, 0) != CAM_SUCCESS) { 3751 #else 3752 if(xpt_bus_register(acb->psim, 0) != CAM_SUCCESS) { 3753 #endif 3754 arcmsr_free_resource(acb); 3755 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres); 3756 cam_sim_free(acb->psim, /*free_devq*/TRUE); 3757 ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock); 3758 printf("arcmsr%d: xpt_bus_register failure!\n", unit); 3759 return ENXIO; 3760 } 3761 if(xpt_create_path(&acb->ppath, /* periph */ NULL, cam_sim_path(acb->psim), CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 3762 arcmsr_free_resource(acb); 3763 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres); 3764 xpt_bus_deregister(cam_sim_path(acb->psim)); 3765 cam_sim_free(acb->psim, /* free_simq */ TRUE); 3766 ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock); 3767 printf("arcmsr%d: xpt_create_path failure!\n", unit); 3768 return ENXIO; 3769 } 3770 /* 3771 **************************************************** 3772 */ 3773 xpt_setup_ccb(&csa.ccb_h, acb->ppath, /*priority*/5); 3774 csa.ccb_h.func_code=XPT_SASYNC_CB; 3775 csa.event_enable=AC_FOUND_DEVICE|AC_LOST_DEVICE; 3776 csa.callback=arcmsr_async; 3777 csa.callback_arg=acb->psim; 3778 xpt_action((union ccb *)&csa); 3779 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 3780 /* Create the control device. */ 3781 acb->ioctl_dev=make_dev(&arcmsr_cdevsw, unit, UID_ROOT, GID_WHEEL /* GID_OPERATOR */, S_IRUSR | S_IWUSR, "arcmsr%d", unit); 3782 3783 #if __FreeBSD_version < 503000 3784 acb->ioctl_dev->si_drv1=acb; 3785 #endif 3786 #if __FreeBSD_version > 500005 3787 (void)make_dev_alias(acb->ioctl_dev, "arc%d", unit); 3788 #endif 3789 arcmsr_callout_init(&acb->devmap_callout); 3790 callout_reset(&acb->devmap_callout, 60 * hz, arcmsr_polling_devmap, acb); 3791 return 0; 3792 } 3793 3794 /* 3795 ************************************************************************ 3796 ************************************************************************ 3797 */ 3798 static int arcmsr_probe(device_t dev) 3799 { 3800 u_int32_t id; 3801 static char buf[256]; 3802 char x_type[]={"X-TYPE"}; 3803 char *type; 3804 int raid6 = 1; 3805 3806 if (pci_get_vendor(dev) != PCI_VENDOR_ID_ARECA) { 3807 return (ENXIO); 3808 } 3809 switch(id=pci_get_devid(dev)) { 3810 case PCIDevVenIDARC1110: 3811 case PCIDevVenIDARC1200: 3812 case PCIDevVenIDARC1201: 3813 case PCIDevVenIDARC1210: 3814 raid6 = 0; 3815 /*FALLTHRU*/ 3816 case PCIDevVenIDARC1120: 3817 case PCIDevVenIDARC1130: 3818 case PCIDevVenIDARC1160: 3819 case PCIDevVenIDARC1170: 3820 case PCIDevVenIDARC1220: 3821 case PCIDevVenIDARC1230: 3822 case PCIDevVenIDARC1231: 3823 case PCIDevVenIDARC1260: 3824 case PCIDevVenIDARC1261: 3825 case PCIDevVenIDARC1270: 3826 case PCIDevVenIDARC1280: 3827 type = "SATA"; 3828 break; 3829 case PCIDevVenIDARC1212: 3830 case PCIDevVenIDARC1222: 3831 case PCIDevVenIDARC1380: 3832 case PCIDevVenIDARC1381: 3833 case PCIDevVenIDARC1680: 3834 case PCIDevVenIDARC1681: 3835 type = "SAS 3G"; 3836 break; 3837 case PCIDevVenIDARC1880: 3838 type = "SAS 6G"; 3839 break; 3840 default: 3841 type = x_type; 3842 break; 3843 } 3844 if(type == x_type) 3845 return(ENXIO); 3846 sprintf(buf, "Areca %s Host Adapter RAID Controller %s\n", type, raid6 ? "(RAID6 capable)" : ""); 3847 device_set_desc_copy(dev, buf); 3848 return 0; 3849 } 3850 /* 3851 ************************************************************************ 3852 ************************************************************************ 3853 */ 3854 static int arcmsr_shutdown(device_t dev) 3855 { 3856 u_int32_t i; 3857 u_int32_t intmask_org; 3858 struct CommandControlBlock *srb; 3859 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 3860 3861 /* stop adapter background rebuild */ 3862 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 3863 /* disable all outbound interrupt */ 3864 intmask_org=arcmsr_disable_allintr(acb); 3865 arcmsr_stop_adapter_bgrb(acb); 3866 arcmsr_flush_adapter_cache(acb); 3867 /* abort all outstanding command */ 3868 acb->acb_flags |= ACB_F_SCSISTOPADAPTER; 3869 acb->acb_flags &= ~ACB_F_IOP_INITED; 3870 if(acb->srboutstandingcount!=0) { 3871 /*clear and abort all outbound posted Q*/ 3872 arcmsr_done4abort_postqueue(acb); 3873 /* talk to iop 331 outstanding command aborted*/ 3874 arcmsr_abort_allcmd(acb); 3875 for(i=0;i<ARCMSR_MAX_FREESRB_NUM;i++) { 3876 srb=acb->psrb_pool[i]; 3877 if(srb->srb_state==ARCMSR_SRB_START) { 3878 srb->srb_state=ARCMSR_SRB_ABORTED; 3879 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3880 arcmsr_srb_complete(srb, 1); 3881 } 3882 } 3883 } 3884 acb->srboutstandingcount=0; 3885 acb->workingsrb_doneindex=0; 3886 acb->workingsrb_startindex=0; 3887 #ifdef ARCMSR_DEBUG1 3888 acb->pktRequestCount = 0; 3889 acb->pktReturnCount = 0; 3890 #endif 3891 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 3892 return (0); 3893 } 3894 /* 3895 ************************************************************************ 3896 ************************************************************************ 3897 */ 3898 static int arcmsr_detach(device_t dev) 3899 { 3900 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 3901 int i; 3902 3903 callout_stop(&acb->devmap_callout); 3904 bus_teardown_intr(dev, acb->irqres, acb->ih); 3905 arcmsr_shutdown(dev); 3906 arcmsr_free_resource(acb); 3907 for(i=0; (acb->sys_res_arcmsr[i]!=NULL) && (i<2); i++) { 3908 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(i), acb->sys_res_arcmsr[i]); 3909 } 3910 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres); 3911 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 3912 xpt_async(AC_LOST_DEVICE, acb->ppath, NULL); 3913 xpt_free_path(acb->ppath); 3914 xpt_bus_deregister(cam_sim_path(acb->psim)); 3915 cam_sim_free(acb->psim, TRUE); 3916 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 3917 ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock); 3918 return (0); 3919 } 3920 3921 #ifdef ARCMSR_DEBUG1 3922 static void arcmsr_dump_data(struct AdapterControlBlock *acb) 3923 { 3924 if((acb->pktRequestCount - acb->pktReturnCount) == 0) 3925 return; 3926 printf("Command Request Count =0x%x\n",acb->pktRequestCount); 3927 printf("Command Return Count =0x%x\n",acb->pktReturnCount); 3928 printf("Command (Req-Rtn) Count =0x%x\n",(acb->pktRequestCount - acb->pktReturnCount)); 3929 printf("Queued Command Count =0x%x\n",acb->srboutstandingcount); 3930 } 3931 #endif 3932 3933