1 /* 2 ******************************************************************************** 3 ** OS : FreeBSD 4 ** FILE NAME : arcmsr.c 5 ** BY : Erich Chen, Ching Huang 6 ** Description: SCSI RAID Device Driver for 7 ** ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x) 8 ** SATA/SAS RAID HOST Adapter 9 ******************************************************************************** 10 ******************************************************************************** 11 ** 12 ** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved. 13 ** 14 ** Redistribution and use in source and binary forms, with or without 15 ** modification, are permitted provided that the following conditions 16 ** are met: 17 ** 1. Redistributions of source code must retain the above copyright 18 ** notice, this list of conditions and the following disclaimer. 19 ** 2. Redistributions in binary form must reproduce the above copyright 20 ** notice, this list of conditions and the following disclaimer in the 21 ** documentation and/or other materials provided with the distribution. 22 ** 3. The name of the author may not be used to endorse or promote products 23 ** derived from this software without specific prior written permission. 24 ** 25 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 29 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT 30 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 32 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 34 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 ******************************************************************************** 36 ** History 37 ** 38 ** REV# DATE NAME DESCRIPTION 39 ** 1.00.00.00 03/31/2004 Erich Chen First release 40 ** 1.20.00.02 11/29/2004 Erich Chen bug fix with arcmsr_bus_reset when PHY error 41 ** 1.20.00.03 04/19/2005 Erich Chen add SATA 24 Ports adapter type support 42 ** clean unused function 43 ** 1.20.00.12 09/12/2005 Erich Chen bug fix with abort command handling, 44 ** firmware version check 45 ** and firmware update notify for hardware bug fix 46 ** handling if none zero high part physical address 47 ** of srb resource 48 ** 1.20.00.13 08/18/2006 Erich Chen remove pending srb and report busy 49 ** add iop message xfer 50 ** with scsi pass-through command 51 ** add new device id of sas raid adapters 52 ** code fit for SPARC64 & PPC 53 ** 1.20.00.14 02/05/2007 Erich Chen bug fix for incorrect ccb_h.status report 54 ** and cause g_vfs_done() read write error 55 ** 1.20.00.15 10/10/2007 Erich Chen support new RAID adapter type ARC120x 56 ** 1.20.00.16 10/10/2009 Erich Chen Bug fix for RAID adapter type ARC120x 57 ** bus_dmamem_alloc() with BUS_DMA_ZERO 58 ** 1.20.00.17 07/15/2010 Ching Huang Added support ARC1880 59 ** report CAM_DEV_NOT_THERE instead of CAM_SEL_TIMEOUT when device failed, 60 ** prevent cam_periph_error removing all LUN devices of one Target id 61 ** for any one LUN device failed 62 ** 1.20.00.18 10/14/2010 Ching Huang Fixed "inquiry data fails comparion at DV1 step" 63 ** 10/25/2010 Ching Huang Fixed bad range input in bus_alloc_resource for ADAPTER_TYPE_B 64 ** 1.20.00.19 11/11/2010 Ching Huang Fixed arcmsr driver prevent arcsas support for Areca SAS HBA ARC13x0 65 ** 1.20.00.20 12/08/2010 Ching Huang Avoid calling atomic_set_int function 66 ** 1.20.00.21 02/08/2011 Ching Huang Implement I/O request timeout 67 ** 02/14/2011 Ching Huang Modified pktRequestCount 68 ** 1.20.00.21 03/03/2011 Ching Huang if a command timeout, then wait its ccb back before free it 69 ** 1.20.00.22 07/04/2011 Ching Huang Fixed multiple MTX panic 70 ** 1.20.00.23 10/28/2011 Ching Huang Added TIMEOUT_DELAY in case of too many HDDs need to start 71 ** 1.20.00.23 11/08/2011 Ching Huang Added report device transfer speed 72 ** 1.20.00.23 01/30/2012 Ching Huang Fixed Request requeued and Retrying command 73 ** 1.20.00.24 06/11/2012 Ching Huang Fixed return sense data condition 74 ** 1.20.00.25 08/17/2012 Ching Huang Fixed hotplug device no function on type A adapter 75 ** 1.20.00.26 12/14/2012 Ching Huang Added support ARC1214,1224 76 ****************************************************************************************** 77 */ 78 79 #include <sys/cdefs.h> 80 __FBSDID("$FreeBSD$"); 81 82 #if 0 83 #define ARCMSR_DEBUG1 1 84 #endif 85 #include <sys/param.h> 86 #include <sys/systm.h> 87 #include <sys/malloc.h> 88 #include <sys/kernel.h> 89 #include <sys/bus.h> 90 #include <sys/queue.h> 91 #include <sys/stat.h> 92 #include <sys/devicestat.h> 93 #include <sys/kthread.h> 94 #include <sys/module.h> 95 #include <sys/proc.h> 96 #include <sys/lock.h> 97 #include <sys/sysctl.h> 98 #include <sys/poll.h> 99 #include <sys/ioccom.h> 100 #include <vm/vm.h> 101 #include <vm/vm_param.h> 102 #include <vm/pmap.h> 103 104 #include <isa/rtc.h> 105 106 #include <machine/bus.h> 107 #include <machine/resource.h> 108 #include <machine/atomic.h> 109 #include <sys/conf.h> 110 #include <sys/rman.h> 111 112 #include <cam/cam.h> 113 #include <cam/cam_ccb.h> 114 #include <cam/cam_sim.h> 115 #include <cam/cam_periph.h> 116 #include <cam/cam_xpt_periph.h> 117 #include <cam/cam_xpt_sim.h> 118 #include <cam/cam_debug.h> 119 #include <cam/scsi/scsi_all.h> 120 #include <cam/scsi/scsi_message.h> 121 /* 122 ************************************************************************** 123 ************************************************************************** 124 */ 125 #if __FreeBSD_version >= 500005 126 #include <sys/selinfo.h> 127 #include <sys/mutex.h> 128 #include <sys/endian.h> 129 #include <dev/pci/pcivar.h> 130 #include <dev/pci/pcireg.h> 131 #else 132 #include <sys/select.h> 133 #include <pci/pcivar.h> 134 #include <pci/pcireg.h> 135 #endif 136 137 #if !defined(CAM_NEW_TRAN_CODE) && __FreeBSD_version >= 700025 138 #define CAM_NEW_TRAN_CODE 1 139 #endif 140 141 #if __FreeBSD_version > 500000 142 #define arcmsr_callout_init(a) callout_init(a, /*mpsafe*/1); 143 #else 144 #define arcmsr_callout_init(a) callout_init(a); 145 #endif 146 147 #define ARCMSR_DRIVER_VERSION "Driver Version 1.20.00.26 2013-01-08" 148 #include <dev/arcmsr/arcmsr.h> 149 /* 150 ************************************************************************** 151 ************************************************************************** 152 */ 153 static void arcmsr_free_srb(struct CommandControlBlock *srb); 154 static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb); 155 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb); 156 static int arcmsr_probe(device_t dev); 157 static int arcmsr_attach(device_t dev); 158 static int arcmsr_detach(device_t dev); 159 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg); 160 static void arcmsr_iop_parking(struct AdapterControlBlock *acb); 161 static int arcmsr_shutdown(device_t dev); 162 static void arcmsr_interrupt(struct AdapterControlBlock *acb); 163 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb); 164 static void arcmsr_free_resource(struct AdapterControlBlock *acb); 165 static void arcmsr_bus_reset(struct AdapterControlBlock *acb); 166 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb); 167 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb); 168 static void arcmsr_iop_init(struct AdapterControlBlock *acb); 169 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb); 170 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, struct QBUFFER *prbuffer); 171 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb); 172 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb); 173 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag); 174 static void arcmsr_iop_reset(struct AdapterControlBlock *acb); 175 static void arcmsr_report_sense_info(struct CommandControlBlock *srb); 176 static void arcmsr_build_srb(struct CommandControlBlock *srb, bus_dma_segment_t *dm_segs, u_int32_t nseg); 177 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb); 178 static int arcmsr_resume(device_t dev); 179 static int arcmsr_suspend(device_t dev); 180 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb); 181 static void arcmsr_polling_devmap(void *arg); 182 static void arcmsr_srb_timeout(void *arg); 183 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb); 184 #ifdef ARCMSR_DEBUG1 185 static void arcmsr_dump_data(struct AdapterControlBlock *acb); 186 #endif 187 /* 188 ************************************************************************** 189 ************************************************************************** 190 */ 191 static void UDELAY(u_int32_t us) { DELAY(us); } 192 /* 193 ************************************************************************** 194 ************************************************************************** 195 */ 196 static bus_dmamap_callback_t arcmsr_map_free_srb; 197 static bus_dmamap_callback_t arcmsr_execute_srb; 198 /* 199 ************************************************************************** 200 ************************************************************************** 201 */ 202 static d_open_t arcmsr_open; 203 static d_close_t arcmsr_close; 204 static d_ioctl_t arcmsr_ioctl; 205 206 static device_method_t arcmsr_methods[]={ 207 DEVMETHOD(device_probe, arcmsr_probe), 208 DEVMETHOD(device_attach, arcmsr_attach), 209 DEVMETHOD(device_detach, arcmsr_detach), 210 DEVMETHOD(device_shutdown, arcmsr_shutdown), 211 DEVMETHOD(device_suspend, arcmsr_suspend), 212 DEVMETHOD(device_resume, arcmsr_resume), 213 214 #if __FreeBSD_version >= 803000 215 DEVMETHOD_END 216 #else 217 { 0, 0 } 218 #endif 219 }; 220 221 static driver_t arcmsr_driver={ 222 "arcmsr", arcmsr_methods, sizeof(struct AdapterControlBlock) 223 }; 224 225 static devclass_t arcmsr_devclass; 226 DRIVER_MODULE(arcmsr, pci, arcmsr_driver, arcmsr_devclass, 0, 0); 227 MODULE_DEPEND(arcmsr, pci, 1, 1, 1); 228 MODULE_DEPEND(arcmsr, cam, 1, 1, 1); 229 #ifndef BUS_DMA_COHERENT 230 #define BUS_DMA_COHERENT 0x04 /* hint: map memory in a coherent way */ 231 #endif 232 #if __FreeBSD_version >= 501000 233 static struct cdevsw arcmsr_cdevsw={ 234 #if __FreeBSD_version >= 503000 235 .d_version = D_VERSION, 236 #endif 237 #if (__FreeBSD_version>=503000 && __FreeBSD_version<600034) 238 .d_flags = D_NEEDGIANT, 239 #endif 240 .d_open = arcmsr_open, /* open */ 241 .d_close = arcmsr_close, /* close */ 242 .d_ioctl = arcmsr_ioctl, /* ioctl */ 243 .d_name = "arcmsr", /* name */ 244 }; 245 #else 246 #define ARCMSR_CDEV_MAJOR 180 247 248 static struct cdevsw arcmsr_cdevsw = { 249 arcmsr_open, /* open */ 250 arcmsr_close, /* close */ 251 noread, /* read */ 252 nowrite, /* write */ 253 arcmsr_ioctl, /* ioctl */ 254 nopoll, /* poll */ 255 nommap, /* mmap */ 256 nostrategy, /* strategy */ 257 "arcmsr", /* name */ 258 ARCMSR_CDEV_MAJOR, /* major */ 259 nodump, /* dump */ 260 nopsize, /* psize */ 261 0 /* flags */ 262 }; 263 #endif 264 /* 265 ************************************************************************** 266 ************************************************************************** 267 */ 268 #if __FreeBSD_version < 500005 269 static int arcmsr_open(dev_t dev, int flags, int fmt, struct proc *proc) 270 #else 271 #if __FreeBSD_version < 503000 272 static int arcmsr_open(dev_t dev, int flags, int fmt, struct thread *proc) 273 #else 274 static int arcmsr_open(struct cdev *dev, int flags, int fmt, struct thread *proc) 275 #endif 276 #endif 277 { 278 #if __FreeBSD_version < 503000 279 struct AdapterControlBlock *acb = dev->si_drv1; 280 #else 281 int unit = dev2unit(dev); 282 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit); 283 #endif 284 if(acb == NULL) { 285 return ENXIO; 286 } 287 return (0); 288 } 289 /* 290 ************************************************************************** 291 ************************************************************************** 292 */ 293 #if __FreeBSD_version < 500005 294 static int arcmsr_close(dev_t dev, int flags, int fmt, struct proc *proc) 295 #else 296 #if __FreeBSD_version < 503000 297 static int arcmsr_close(dev_t dev, int flags, int fmt, struct thread *proc) 298 #else 299 static int arcmsr_close(struct cdev *dev, int flags, int fmt, struct thread *proc) 300 #endif 301 #endif 302 { 303 #if __FreeBSD_version < 503000 304 struct AdapterControlBlock *acb = dev->si_drv1; 305 #else 306 int unit = dev2unit(dev); 307 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit); 308 #endif 309 if(acb == NULL) { 310 return ENXIO; 311 } 312 return 0; 313 } 314 /* 315 ************************************************************************** 316 ************************************************************************** 317 */ 318 #if __FreeBSD_version < 500005 319 static int arcmsr_ioctl(dev_t dev, u_long ioctl_cmd, caddr_t arg, int flags, struct proc *proc) 320 #else 321 #if __FreeBSD_version < 503000 322 static int arcmsr_ioctl(dev_t dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc) 323 #else 324 static int arcmsr_ioctl(struct cdev *dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc) 325 #endif 326 #endif 327 { 328 #if __FreeBSD_version < 503000 329 struct AdapterControlBlock *acb = dev->si_drv1; 330 #else 331 int unit = dev2unit(dev); 332 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit); 333 #endif 334 335 if(acb == NULL) { 336 return ENXIO; 337 } 338 return (arcmsr_iop_ioctlcmd(acb, ioctl_cmd, arg)); 339 } 340 /* 341 ********************************************************************** 342 ********************************************************************** 343 */ 344 static u_int32_t arcmsr_disable_allintr( struct AdapterControlBlock *acb) 345 { 346 u_int32_t intmask_org = 0; 347 348 switch (acb->adapter_type) { 349 case ACB_ADAPTER_TYPE_A: { 350 /* disable all outbound interrupt */ 351 intmask_org = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intmask); /* disable outbound message0 int */ 352 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE); 353 } 354 break; 355 case ACB_ADAPTER_TYPE_B: { 356 /* disable all outbound interrupt */ 357 intmask_org = CHIP_REG_READ32(HBB_DOORBELL, 358 0, iop2drv_doorbell_mask) & (~ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); /* disable outbound message0 int */ 359 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell_mask, 0); /* disable all interrupt */ 360 } 361 break; 362 case ACB_ADAPTER_TYPE_C: { 363 /* disable all outbound interrupt */ 364 intmask_org = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask) ; /* disable outbound message0 int */ 365 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE); 366 } 367 break; 368 case ACB_ADAPTER_TYPE_D: { 369 /* disable all outbound interrupt */ 370 intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable) ; /* disable outbound message0 int */ 371 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE); 372 } 373 break; 374 } 375 return (intmask_org); 376 } 377 /* 378 ********************************************************************** 379 ********************************************************************** 380 */ 381 static void arcmsr_enable_allintr( struct AdapterControlBlock *acb, u_int32_t intmask_org) 382 { 383 u_int32_t mask; 384 385 switch (acb->adapter_type) { 386 case ACB_ADAPTER_TYPE_A: { 387 /* enable outbound Post Queue, outbound doorbell Interrupt */ 388 mask = ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE|ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE); 389 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org & mask); 390 acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff; 391 } 392 break; 393 case ACB_ADAPTER_TYPE_B: { 394 /* enable ARCMSR_IOP2DRV_MESSAGE_CMD_DONE */ 395 mask = (ARCMSR_IOP2DRV_DATA_WRITE_OK|ARCMSR_IOP2DRV_DATA_READ_OK|ARCMSR_IOP2DRV_CDB_DONE|ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); 396 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell_mask, intmask_org | mask); /*1=interrupt enable, 0=interrupt disable*/ 397 acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f; 398 } 399 break; 400 case ACB_ADAPTER_TYPE_C: { 401 /* enable outbound Post Queue, outbound doorbell Interrupt */ 402 mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK); 403 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org & mask); 404 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f; 405 } 406 break; 407 case ACB_ADAPTER_TYPE_D: { 408 /* enable outbound Post Queue, outbound doorbell Interrupt */ 409 mask = ARCMSR_HBDMU_ALL_INT_ENABLE; 410 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | mask); 411 CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); 412 acb->outbound_int_enable = mask; 413 } 414 break; 415 } 416 } 417 /* 418 ********************************************************************** 419 ********************************************************************** 420 */ 421 static u_int8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb) 422 { 423 u_int32_t Index; 424 u_int8_t Retries = 0x00; 425 426 do { 427 for(Index=0; Index < 100; Index++) { 428 if(CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { 429 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);/*clear interrupt*/ 430 return TRUE; 431 } 432 UDELAY(10000); 433 }/*max 1 seconds*/ 434 }while(Retries++ < 20);/*max 20 sec*/ 435 return (FALSE); 436 } 437 /* 438 ********************************************************************** 439 ********************************************************************** 440 */ 441 static u_int8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb) 442 { 443 u_int32_t Index; 444 u_int8_t Retries = 0x00; 445 446 do { 447 for(Index=0; Index < 100; Index++) { 448 if(CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) { 449 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt*/ 450 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 451 return TRUE; 452 } 453 UDELAY(10000); 454 }/*max 1 seconds*/ 455 }while(Retries++ < 20);/*max 20 sec*/ 456 return (FALSE); 457 } 458 /* 459 ********************************************************************** 460 ********************************************************************** 461 */ 462 static u_int8_t arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock *acb) 463 { 464 u_int32_t Index; 465 u_int8_t Retries = 0x00; 466 467 do { 468 for(Index=0; Index < 100; Index++) { 469 if(CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 470 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);/*clear interrupt*/ 471 return TRUE; 472 } 473 UDELAY(10000); 474 }/*max 1 seconds*/ 475 }while(Retries++ < 20);/*max 20 sec*/ 476 return (FALSE); 477 } 478 /* 479 ********************************************************************** 480 ********************************************************************** 481 */ 482 static u_int8_t arcmsr_hbd_wait_msgint_ready(struct AdapterControlBlock *acb) 483 { 484 u_int32_t Index; 485 u_int8_t Retries = 0x00; 486 487 do { 488 for(Index=0; Index < 100; Index++) { 489 if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) { 490 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);/*clear interrupt*/ 491 return TRUE; 492 } 493 UDELAY(10000); 494 }/*max 1 seconds*/ 495 }while(Retries++ < 20);/*max 20 sec*/ 496 return (FALSE); 497 } 498 /* 499 ************************************************************************ 500 ************************************************************************ 501 */ 502 static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb) 503 { 504 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 505 506 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 507 do { 508 if(arcmsr_hba_wait_msgint_ready(acb)) { 509 break; 510 } else { 511 retry_count--; 512 } 513 }while(retry_count != 0); 514 } 515 /* 516 ************************************************************************ 517 ************************************************************************ 518 */ 519 static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb) 520 { 521 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 522 523 CHIP_REG_WRITE32(HBB_DOORBELL, 524 0, drv2iop_doorbell, ARCMSR_MESSAGE_FLUSH_CACHE); 525 do { 526 if(arcmsr_hbb_wait_msgint_ready(acb)) { 527 break; 528 } else { 529 retry_count--; 530 } 531 }while(retry_count != 0); 532 } 533 /* 534 ************************************************************************ 535 ************************************************************************ 536 */ 537 static void arcmsr_flush_hbc_cache(struct AdapterControlBlock *acb) 538 { 539 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 540 541 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 542 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 543 do { 544 if(arcmsr_hbc_wait_msgint_ready(acb)) { 545 break; 546 } else { 547 retry_count--; 548 } 549 }while(retry_count != 0); 550 } 551 /* 552 ************************************************************************ 553 ************************************************************************ 554 */ 555 static void arcmsr_flush_hbd_cache(struct AdapterControlBlock *acb) 556 { 557 int retry_count = 30; /* enlarge wait flush adapter cache time: 10 minute */ 558 559 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 560 do { 561 if(arcmsr_hbd_wait_msgint_ready(acb)) { 562 break; 563 } else { 564 retry_count--; 565 } 566 }while(retry_count != 0); 567 } 568 /* 569 ************************************************************************ 570 ************************************************************************ 571 */ 572 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb) 573 { 574 switch (acb->adapter_type) { 575 case ACB_ADAPTER_TYPE_A: { 576 arcmsr_flush_hba_cache(acb); 577 } 578 break; 579 case ACB_ADAPTER_TYPE_B: { 580 arcmsr_flush_hbb_cache(acb); 581 } 582 break; 583 case ACB_ADAPTER_TYPE_C: { 584 arcmsr_flush_hbc_cache(acb); 585 } 586 break; 587 case ACB_ADAPTER_TYPE_D: { 588 arcmsr_flush_hbd_cache(acb); 589 } 590 break; 591 } 592 } 593 /* 594 ******************************************************************************* 595 ******************************************************************************* 596 */ 597 static int arcmsr_suspend(device_t dev) 598 { 599 struct AdapterControlBlock *acb = device_get_softc(dev); 600 601 /* flush controller */ 602 arcmsr_iop_parking(acb); 603 /* disable all outbound interrupt */ 604 arcmsr_disable_allintr(acb); 605 return(0); 606 } 607 /* 608 ******************************************************************************* 609 ******************************************************************************* 610 */ 611 static int arcmsr_resume(device_t dev) 612 { 613 struct AdapterControlBlock *acb = device_get_softc(dev); 614 615 arcmsr_iop_init(acb); 616 return(0); 617 } 618 /* 619 ********************************************************************************* 620 ********************************************************************************* 621 */ 622 static void arcmsr_async(void *cb_arg, u_int32_t code, struct cam_path *path, void *arg) 623 { 624 struct AdapterControlBlock *acb; 625 u_int8_t target_id, target_lun; 626 struct cam_sim *sim; 627 628 sim = (struct cam_sim *) cb_arg; 629 acb =(struct AdapterControlBlock *) cam_sim_softc(sim); 630 switch (code) { 631 case AC_LOST_DEVICE: 632 target_id = xpt_path_target_id(path); 633 target_lun = xpt_path_lun_id(path); 634 if((target_id > ARCMSR_MAX_TARGETID) || (target_lun > ARCMSR_MAX_TARGETLUN)) { 635 break; 636 } 637 // printf("%s:scsi id=%d lun=%d device lost \n", device_get_name(acb->pci_dev), target_id, target_lun); 638 break; 639 default: 640 break; 641 } 642 } 643 /* 644 ********************************************************************** 645 ********************************************************************** 646 */ 647 static void arcmsr_report_sense_info(struct CommandControlBlock *srb) 648 { 649 union ccb *pccb = srb->pccb; 650 651 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 652 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 653 if(pccb->csio.sense_len) { 654 memset(&pccb->csio.sense_data, 0, sizeof(pccb->csio.sense_data)); 655 memcpy(&pccb->csio.sense_data, srb->arcmsr_cdb.SenseData, 656 get_min(sizeof(struct SENSE_DATA), sizeof(pccb->csio.sense_data))); 657 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); /* Valid,ErrorCode */ 658 pccb->ccb_h.status |= CAM_AUTOSNS_VALID; 659 } 660 } 661 /* 662 ********************************************************************* 663 ********************************************************************* 664 */ 665 static void arcmsr_abort_hba_allcmd(struct AdapterControlBlock *acb) 666 { 667 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 668 if(!arcmsr_hba_wait_msgint_ready(acb)) { 669 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 670 } 671 } 672 /* 673 ********************************************************************* 674 ********************************************************************* 675 */ 676 static void arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb) 677 { 678 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_ABORT_CMD); 679 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 680 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 681 } 682 } 683 /* 684 ********************************************************************* 685 ********************************************************************* 686 */ 687 static void arcmsr_abort_hbc_allcmd(struct AdapterControlBlock *acb) 688 { 689 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 690 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 691 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 692 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 693 } 694 } 695 /* 696 ********************************************************************* 697 ********************************************************************* 698 */ 699 static void arcmsr_abort_hbd_allcmd(struct AdapterControlBlock *acb) 700 { 701 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 702 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 703 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 704 } 705 } 706 /* 707 ********************************************************************* 708 ********************************************************************* 709 */ 710 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb) 711 { 712 switch (acb->adapter_type) { 713 case ACB_ADAPTER_TYPE_A: { 714 arcmsr_abort_hba_allcmd(acb); 715 } 716 break; 717 case ACB_ADAPTER_TYPE_B: { 718 arcmsr_abort_hbb_allcmd(acb); 719 } 720 break; 721 case ACB_ADAPTER_TYPE_C: { 722 arcmsr_abort_hbc_allcmd(acb); 723 } 724 break; 725 case ACB_ADAPTER_TYPE_D: { 726 arcmsr_abort_hbd_allcmd(acb); 727 } 728 break; 729 } 730 } 731 /* 732 ********************************************************************** 733 ********************************************************************** 734 */ 735 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag) 736 { 737 struct AdapterControlBlock *acb = srb->acb; 738 union ccb *pccb = srb->pccb; 739 740 if(srb->srb_flags & SRB_FLAG_TIMER_START) 741 callout_stop(&srb->ccb_callout); 742 if((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 743 bus_dmasync_op_t op; 744 745 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 746 op = BUS_DMASYNC_POSTREAD; 747 } else { 748 op = BUS_DMASYNC_POSTWRITE; 749 } 750 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op); 751 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap); 752 } 753 if(stand_flag == 1) { 754 atomic_subtract_int(&acb->srboutstandingcount, 1); 755 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) && ( 756 acb->srboutstandingcount < (acb->firm_numbers_queue -10))) { 757 acb->acb_flags &= ~ACB_F_CAM_DEV_QFRZN; 758 pccb->ccb_h.status |= CAM_RELEASE_SIMQ; 759 } 760 } 761 if(srb->srb_state != ARCMSR_SRB_TIMEOUT) 762 arcmsr_free_srb(srb); 763 acb->pktReturnCount++; 764 xpt_done(pccb); 765 } 766 /* 767 ************************************************************************** 768 ************************************************************************** 769 */ 770 static void arcmsr_report_srb_state(struct AdapterControlBlock *acb, struct CommandControlBlock *srb, u_int16_t error) 771 { 772 int target, lun; 773 774 target = srb->pccb->ccb_h.target_id; 775 lun = srb->pccb->ccb_h.target_lun; 776 if(error == FALSE) { 777 if(acb->devstate[target][lun] == ARECA_RAID_GONE) { 778 acb->devstate[target][lun] = ARECA_RAID_GOOD; 779 } 780 srb->pccb->ccb_h.status |= CAM_REQ_CMP; 781 arcmsr_srb_complete(srb, 1); 782 } else { 783 switch(srb->arcmsr_cdb.DeviceStatus) { 784 case ARCMSR_DEV_SELECT_TIMEOUT: { 785 if(acb->devstate[target][lun] == ARECA_RAID_GOOD) { 786 printf( "arcmsr%d: Target=%x, Lun=%x, selection timeout, raid volume was lost\n", acb->pci_unit, target, lun); 787 } 788 acb->devstate[target][lun] = ARECA_RAID_GONE; 789 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 790 arcmsr_srb_complete(srb, 1); 791 } 792 break; 793 case ARCMSR_DEV_ABORTED: 794 case ARCMSR_DEV_INIT_FAIL: { 795 acb->devstate[target][lun] = ARECA_RAID_GONE; 796 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 797 arcmsr_srb_complete(srb, 1); 798 } 799 break; 800 case SCSISTAT_CHECK_CONDITION: { 801 acb->devstate[target][lun] = ARECA_RAID_GOOD; 802 arcmsr_report_sense_info(srb); 803 arcmsr_srb_complete(srb, 1); 804 } 805 break; 806 default: 807 printf("arcmsr%d: scsi id=%d lun=%d isr got command error done,but got unknown DeviceStatus=0x%x \n" 808 , acb->pci_unit, target, lun ,srb->arcmsr_cdb.DeviceStatus); 809 acb->devstate[target][lun] = ARECA_RAID_GONE; 810 srb->pccb->ccb_h.status |= CAM_UNCOR_PARITY; 811 /*unknown error or crc error just for retry*/ 812 arcmsr_srb_complete(srb, 1); 813 break; 814 } 815 } 816 } 817 /* 818 ************************************************************************** 819 ************************************************************************** 820 */ 821 static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, u_int32_t flag_srb, u_int16_t error) 822 { 823 struct CommandControlBlock *srb; 824 825 /* check if command done with no error*/ 826 switch (acb->adapter_type) { 827 case ACB_ADAPTER_TYPE_C: 828 case ACB_ADAPTER_TYPE_D: 829 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0)); /*frame must be 32 bytes aligned*/ 830 break; 831 case ACB_ADAPTER_TYPE_A: 832 case ACB_ADAPTER_TYPE_B: 833 default: 834 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 835 break; 836 } 837 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 838 if(srb->srb_state == ARCMSR_SRB_TIMEOUT) { 839 arcmsr_free_srb(srb); 840 printf("arcmsr%d: srb='%p' return srb has been timeouted\n", acb->pci_unit, srb); 841 return; 842 } 843 printf("arcmsr%d: return srb has been completed\n" 844 "srb='%p' srb_state=0x%x outstanding srb count=%d \n", 845 acb->pci_unit, srb, srb->srb_state, acb->srboutstandingcount); 846 return; 847 } 848 arcmsr_report_srb_state(acb, srb, error); 849 } 850 /* 851 ************************************************************************** 852 ************************************************************************** 853 */ 854 static void arcmsr_srb_timeout(void *arg) 855 { 856 struct CommandControlBlock *srb = (struct CommandControlBlock *)arg; 857 struct AdapterControlBlock *acb; 858 int target, lun; 859 u_int8_t cmd; 860 861 target = srb->pccb->ccb_h.target_id; 862 lun = srb->pccb->ccb_h.target_lun; 863 acb = srb->acb; 864 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 865 if(srb->srb_state == ARCMSR_SRB_START) 866 { 867 cmd = srb->pccb->csio.cdb_io.cdb_bytes[0]; 868 srb->srb_state = ARCMSR_SRB_TIMEOUT; 869 srb->pccb->ccb_h.status |= CAM_CMD_TIMEOUT; 870 arcmsr_srb_complete(srb, 1); 871 printf("arcmsr%d: scsi id %d lun %d cmd=0x%x srb='%p' ccb command time out!\n", 872 acb->pci_unit, target, lun, cmd, srb); 873 } 874 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 875 #ifdef ARCMSR_DEBUG1 876 arcmsr_dump_data(acb); 877 #endif 878 } 879 880 /* 881 ********************************************************************** 882 ********************************************************************** 883 */ 884 static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb) 885 { 886 int i=0; 887 u_int32_t flag_srb; 888 u_int16_t error; 889 890 switch (acb->adapter_type) { 891 case ACB_ADAPTER_TYPE_A: { 892 u_int32_t outbound_intstatus; 893 894 /*clear and abort all outbound posted Q*/ 895 outbound_intstatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 896 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);/*clear interrupt*/ 897 while(((flag_srb=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_queueport)) != 0xFFFFFFFF) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) { 898 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 899 arcmsr_drain_donequeue(acb, flag_srb, error); 900 } 901 } 902 break; 903 case ACB_ADAPTER_TYPE_B: { 904 struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu; 905 906 /*clear all outbound posted Q*/ 907 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */ 908 for(i=0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) { 909 if((flag_srb = phbbmu->done_qbuffer[i]) != 0) { 910 phbbmu->done_qbuffer[i] = 0; 911 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 912 arcmsr_drain_donequeue(acb, flag_srb, error); 913 } 914 phbbmu->post_qbuffer[i] = 0; 915 }/*drain reply FIFO*/ 916 phbbmu->doneq_index = 0; 917 phbbmu->postq_index = 0; 918 } 919 break; 920 case ACB_ADAPTER_TYPE_C: { 921 922 while((CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) { 923 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 924 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 925 arcmsr_drain_donequeue(acb, flag_srb, error); 926 } 927 } 928 break; 929 case ACB_ADAPTER_TYPE_D: { 930 arcmsr_hbd_postqueue_isr(acb); 931 } 932 break; 933 } 934 } 935 /* 936 **************************************************************************** 937 **************************************************************************** 938 */ 939 static void arcmsr_iop_reset(struct AdapterControlBlock *acb) 940 { 941 struct CommandControlBlock *srb; 942 u_int32_t intmask_org; 943 u_int32_t i=0; 944 945 if(acb->srboutstandingcount>0) { 946 /* disable all outbound interrupt */ 947 intmask_org = arcmsr_disable_allintr(acb); 948 /*clear and abort all outbound posted Q*/ 949 arcmsr_done4abort_postqueue(acb); 950 /* talk to iop 331 outstanding command aborted*/ 951 arcmsr_abort_allcmd(acb); 952 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 953 srb = acb->psrb_pool[i]; 954 if(srb->srb_state == ARCMSR_SRB_START) { 955 srb->srb_state = ARCMSR_SRB_ABORTED; 956 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 957 arcmsr_srb_complete(srb, 1); 958 printf("arcmsr%d: scsi id=%d lun=%d srb='%p' aborted\n" 959 , acb->pci_unit, srb->pccb->ccb_h.target_id 960 , srb->pccb->ccb_h.target_lun, srb); 961 } 962 } 963 /* enable all outbound interrupt */ 964 arcmsr_enable_allintr(acb, intmask_org); 965 } 966 acb->srboutstandingcount = 0; 967 acb->workingsrb_doneindex = 0; 968 acb->workingsrb_startindex = 0; 969 acb->pktRequestCount = 0; 970 acb->pktReturnCount = 0; 971 } 972 /* 973 ********************************************************************** 974 ********************************************************************** 975 */ 976 static void arcmsr_build_srb(struct CommandControlBlock *srb, 977 bus_dma_segment_t *dm_segs, u_int32_t nseg) 978 { 979 struct ARCMSR_CDB *arcmsr_cdb = &srb->arcmsr_cdb; 980 u_int8_t *psge = (u_int8_t *)&arcmsr_cdb->u; 981 u_int32_t address_lo, address_hi; 982 union ccb *pccb = srb->pccb; 983 struct ccb_scsiio *pcsio = &pccb->csio; 984 u_int32_t arccdbsize = 0x30; 985 986 memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB)); 987 arcmsr_cdb->Bus = 0; 988 arcmsr_cdb->TargetID = pccb->ccb_h.target_id; 989 arcmsr_cdb->LUN = pccb->ccb_h.target_lun; 990 arcmsr_cdb->Function = 1; 991 arcmsr_cdb->CdbLength = (u_int8_t)pcsio->cdb_len; 992 bcopy(pcsio->cdb_io.cdb_bytes, arcmsr_cdb->Cdb, pcsio->cdb_len); 993 if(nseg != 0) { 994 struct AdapterControlBlock *acb = srb->acb; 995 bus_dmasync_op_t op; 996 u_int32_t length, i, cdb_sgcount = 0; 997 998 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 999 op = BUS_DMASYNC_PREREAD; 1000 } else { 1001 op = BUS_DMASYNC_PREWRITE; 1002 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE; 1003 srb->srb_flags |= SRB_FLAG_WRITE; 1004 } 1005 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op); 1006 for(i=0; i < nseg; i++) { 1007 /* Get the physical address of the current data pointer */ 1008 length = arcmsr_htole32(dm_segs[i].ds_len); 1009 address_lo = arcmsr_htole32(dma_addr_lo32(dm_segs[i].ds_addr)); 1010 address_hi = arcmsr_htole32(dma_addr_hi32(dm_segs[i].ds_addr)); 1011 if(address_hi == 0) { 1012 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge; 1013 pdma_sg->address = address_lo; 1014 pdma_sg->length = length; 1015 psge += sizeof(struct SG32ENTRY); 1016 arccdbsize += sizeof(struct SG32ENTRY); 1017 } else { 1018 u_int32_t sg64s_size = 0, tmplength = length; 1019 1020 while(1) { 1021 u_int64_t span4G, length0; 1022 struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge; 1023 1024 span4G = (u_int64_t)address_lo + tmplength; 1025 pdma_sg->addresshigh = address_hi; 1026 pdma_sg->address = address_lo; 1027 if(span4G > 0x100000000) { 1028 /*see if cross 4G boundary*/ 1029 length0 = 0x100000000-address_lo; 1030 pdma_sg->length = (u_int32_t)length0 | IS_SG64_ADDR; 1031 address_hi = address_hi+1; 1032 address_lo = 0; 1033 tmplength = tmplength - (u_int32_t)length0; 1034 sg64s_size += sizeof(struct SG64ENTRY); 1035 psge += sizeof(struct SG64ENTRY); 1036 cdb_sgcount++; 1037 } else { 1038 pdma_sg->length = tmplength | IS_SG64_ADDR; 1039 sg64s_size += sizeof(struct SG64ENTRY); 1040 psge += sizeof(struct SG64ENTRY); 1041 break; 1042 } 1043 } 1044 arccdbsize += sg64s_size; 1045 } 1046 cdb_sgcount++; 1047 } 1048 arcmsr_cdb->sgcount = (u_int8_t)cdb_sgcount; 1049 arcmsr_cdb->DataLength = pcsio->dxfer_len; 1050 if( arccdbsize > 256) { 1051 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE; 1052 } 1053 } else { 1054 arcmsr_cdb->DataLength = 0; 1055 } 1056 srb->arc_cdb_size = arccdbsize; 1057 arcmsr_cdb->msgPages = (arccdbsize/256) + ((arccdbsize % 256) ? 1 : 0); 1058 } 1059 /* 1060 ************************************************************************** 1061 ************************************************************************** 1062 */ 1063 static void arcmsr_post_srb(struct AdapterControlBlock *acb, struct CommandControlBlock *srb) 1064 { 1065 u_int32_t cdb_phyaddr_low = (u_int32_t) srb->cdb_phyaddr_low; 1066 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&srb->arcmsr_cdb; 1067 1068 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, (srb->srb_flags & SRB_FLAG_WRITE) ? BUS_DMASYNC_POSTWRITE:BUS_DMASYNC_POSTREAD); 1069 atomic_add_int(&acb->srboutstandingcount, 1); 1070 srb->srb_state = ARCMSR_SRB_START; 1071 1072 switch (acb->adapter_type) { 1073 case ACB_ADAPTER_TYPE_A: { 1074 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { 1075 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low|ARCMSR_SRBPOST_FLAG_SGL_BSIZE); 1076 } else { 1077 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low); 1078 } 1079 } 1080 break; 1081 case ACB_ADAPTER_TYPE_B: { 1082 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1083 int ending_index, index; 1084 1085 index = phbbmu->postq_index; 1086 ending_index = ((index+1) % ARCMSR_MAX_HBB_POSTQUEUE); 1087 phbbmu->post_qbuffer[ending_index] = 0; 1088 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { 1089 phbbmu->post_qbuffer[index] = cdb_phyaddr_low | ARCMSR_SRBPOST_FLAG_SGL_BSIZE; 1090 } else { 1091 phbbmu->post_qbuffer[index] = cdb_phyaddr_low; 1092 } 1093 index++; 1094 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 1095 phbbmu->postq_index = index; 1096 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_CDB_POSTED); 1097 } 1098 break; 1099 case ACB_ADAPTER_TYPE_C: { 1100 u_int32_t ccb_post_stamp, arc_cdb_size, cdb_phyaddr_hi32; 1101 1102 arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size; 1103 ccb_post_stamp = (cdb_phyaddr_low | ((arc_cdb_size-1) >> 6) | 1); 1104 cdb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high; 1105 if(cdb_phyaddr_hi32) 1106 { 1107 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_high, cdb_phyaddr_hi32); 1108 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp); 1109 } 1110 else 1111 { 1112 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp); 1113 } 1114 } 1115 break; 1116 case ACB_ADAPTER_TYPE_D: { 1117 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1118 u_int16_t index_stripped; 1119 u_int16_t postq_index; 1120 struct InBound_SRB *pinbound_srb; 1121 1122 ARCMSR_LOCK_ACQUIRE(&acb->postDone_lock); 1123 postq_index = phbdmu->postq_index; 1124 pinbound_srb = (struct InBound_SRB *)&phbdmu->post_qbuffer[postq_index & 0xFF]; 1125 pinbound_srb->addressHigh = srb->cdb_phyaddr_high; 1126 pinbound_srb->addressLow = srb->cdb_phyaddr_low; 1127 pinbound_srb->length = srb->arc_cdb_size >> 2; 1128 arcmsr_cdb->Context = srb->cdb_phyaddr_low; 1129 if (postq_index & 0x4000) { 1130 index_stripped = postq_index & 0xFF; 1131 index_stripped += 1; 1132 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1133 phbdmu->postq_index = index_stripped ? (index_stripped | 0x4000) : index_stripped; 1134 } else { 1135 index_stripped = postq_index; 1136 index_stripped += 1; 1137 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1138 phbdmu->postq_index = index_stripped ? index_stripped : (index_stripped | 0x4000); 1139 } 1140 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inboundlist_write_pointer, postq_index); 1141 ARCMSR_LOCK_RELEASE(&acb->postDone_lock); 1142 } 1143 break; 1144 } 1145 } 1146 /* 1147 ************************************************************************ 1148 ************************************************************************ 1149 */ 1150 static struct QBUFFER *arcmsr_get_iop_rqbuffer( struct AdapterControlBlock *acb) 1151 { 1152 struct QBUFFER *qbuffer=NULL; 1153 1154 switch (acb->adapter_type) { 1155 case ACB_ADAPTER_TYPE_A: { 1156 struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu; 1157 1158 qbuffer = (struct QBUFFER *)&phbamu->message_rbuffer; 1159 } 1160 break; 1161 case ACB_ADAPTER_TYPE_B: { 1162 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1163 1164 qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_rbuffer; 1165 } 1166 break; 1167 case ACB_ADAPTER_TYPE_C: { 1168 struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu; 1169 1170 qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer; 1171 } 1172 break; 1173 case ACB_ADAPTER_TYPE_D: { 1174 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1175 1176 qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_rbuffer; 1177 } 1178 break; 1179 } 1180 return(qbuffer); 1181 } 1182 /* 1183 ************************************************************************ 1184 ************************************************************************ 1185 */ 1186 static struct QBUFFER *arcmsr_get_iop_wqbuffer( struct AdapterControlBlock *acb) 1187 { 1188 struct QBUFFER *qbuffer = NULL; 1189 1190 switch (acb->adapter_type) { 1191 case ACB_ADAPTER_TYPE_A: { 1192 struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu; 1193 1194 qbuffer = (struct QBUFFER *)&phbamu->message_wbuffer; 1195 } 1196 break; 1197 case ACB_ADAPTER_TYPE_B: { 1198 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1199 1200 qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_wbuffer; 1201 } 1202 break; 1203 case ACB_ADAPTER_TYPE_C: { 1204 struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu; 1205 1206 qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer; 1207 } 1208 break; 1209 case ACB_ADAPTER_TYPE_D: { 1210 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1211 1212 qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_wbuffer; 1213 } 1214 break; 1215 } 1216 return(qbuffer); 1217 } 1218 /* 1219 ************************************************************************** 1220 ************************************************************************** 1221 */ 1222 static void arcmsr_iop_message_read(struct AdapterControlBlock *acb) 1223 { 1224 switch (acb->adapter_type) { 1225 case ACB_ADAPTER_TYPE_A: { 1226 /* let IOP know data has been read */ 1227 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK); 1228 } 1229 break; 1230 case ACB_ADAPTER_TYPE_B: { 1231 /* let IOP know data has been read */ 1232 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK); 1233 } 1234 break; 1235 case ACB_ADAPTER_TYPE_C: { 1236 /* let IOP know data has been read */ 1237 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK); 1238 } 1239 break; 1240 case ACB_ADAPTER_TYPE_D: { 1241 /* let IOP know data has been read */ 1242 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ); 1243 } 1244 break; 1245 } 1246 } 1247 /* 1248 ************************************************************************** 1249 ************************************************************************** 1250 */ 1251 static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb) 1252 { 1253 switch (acb->adapter_type) { 1254 case ACB_ADAPTER_TYPE_A: { 1255 /* 1256 ** push inbound doorbell tell iop, driver data write ok 1257 ** and wait reply on next hwinterrupt for next Qbuffer post 1258 */ 1259 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK); 1260 } 1261 break; 1262 case ACB_ADAPTER_TYPE_B: { 1263 /* 1264 ** push inbound doorbell tell iop, driver data write ok 1265 ** and wait reply on next hwinterrupt for next Qbuffer post 1266 */ 1267 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_WRITE_OK); 1268 } 1269 break; 1270 case ACB_ADAPTER_TYPE_C: { 1271 /* 1272 ** push inbound doorbell tell iop, driver data write ok 1273 ** and wait reply on next hwinterrupt for next Qbuffer post 1274 */ 1275 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK); 1276 } 1277 break; 1278 case ACB_ADAPTER_TYPE_D: { 1279 /* 1280 ** push inbound doorbell tell iop, driver data write ok 1281 ** and wait reply on next hwinterrupt for next Qbuffer post 1282 */ 1283 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY); 1284 } 1285 break; 1286 } 1287 } 1288 /* 1289 ************************************************************************ 1290 ************************************************************************ 1291 */ 1292 static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb) 1293 { 1294 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1295 CHIP_REG_WRITE32(HBA_MessageUnit, 1296 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1297 if(!arcmsr_hba_wait_msgint_ready(acb)) { 1298 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n" 1299 , acb->pci_unit); 1300 } 1301 } 1302 /* 1303 ************************************************************************ 1304 ************************************************************************ 1305 */ 1306 static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb) 1307 { 1308 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1309 CHIP_REG_WRITE32(HBB_DOORBELL, 1310 0, drv2iop_doorbell, ARCMSR_MESSAGE_STOP_BGRB); 1311 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 1312 printf( "arcmsr%d: wait 'stop adapter background rebulid' timeout \n" 1313 , acb->pci_unit); 1314 } 1315 } 1316 /* 1317 ************************************************************************ 1318 ************************************************************************ 1319 */ 1320 static void arcmsr_stop_hbc_bgrb(struct AdapterControlBlock *acb) 1321 { 1322 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1323 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1324 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 1325 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 1326 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1327 } 1328 } 1329 /* 1330 ************************************************************************ 1331 ************************************************************************ 1332 */ 1333 static void arcmsr_stop_hbd_bgrb(struct AdapterControlBlock *acb) 1334 { 1335 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1336 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1337 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 1338 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1339 } 1340 } 1341 /* 1342 ************************************************************************ 1343 ************************************************************************ 1344 */ 1345 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb) 1346 { 1347 switch (acb->adapter_type) { 1348 case ACB_ADAPTER_TYPE_A: { 1349 arcmsr_stop_hba_bgrb(acb); 1350 } 1351 break; 1352 case ACB_ADAPTER_TYPE_B: { 1353 arcmsr_stop_hbb_bgrb(acb); 1354 } 1355 break; 1356 case ACB_ADAPTER_TYPE_C: { 1357 arcmsr_stop_hbc_bgrb(acb); 1358 } 1359 break; 1360 case ACB_ADAPTER_TYPE_D: { 1361 arcmsr_stop_hbd_bgrb(acb); 1362 } 1363 break; 1364 } 1365 } 1366 /* 1367 ************************************************************************ 1368 ************************************************************************ 1369 */ 1370 static void arcmsr_poll(struct cam_sim *psim) 1371 { 1372 struct AdapterControlBlock *acb; 1373 int mutex; 1374 1375 acb = (struct AdapterControlBlock *)cam_sim_softc(psim); 1376 mutex = mtx_owned(&acb->isr_lock); 1377 if( mutex == 0 ) 1378 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 1379 arcmsr_interrupt(acb); 1380 if( mutex == 0 ) 1381 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 1382 } 1383 /* 1384 ************************************************************************** 1385 ************************************************************************** 1386 */ 1387 static u_int32_t arcmsr_Read_iop_rqbuffer_data_D(struct AdapterControlBlock *acb, 1388 struct QBUFFER *prbuffer) { 1389 1390 u_int8_t *pQbuffer; 1391 u_int8_t *buf1 = 0; 1392 u_int32_t *iop_data, *buf2 = 0; 1393 u_int32_t iop_len, data_len; 1394 1395 iop_data = (u_int32_t *)prbuffer->data; 1396 iop_len = (u_int32_t)prbuffer->data_len; 1397 if ( iop_len > 0 ) 1398 { 1399 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO); 1400 buf2 = (u_int32_t *)buf1; 1401 if( buf1 == NULL) 1402 return (0); 1403 data_len = iop_len; 1404 while(data_len >= 4) 1405 { 1406 *buf2++ = *iop_data++; 1407 data_len -= 4; 1408 } 1409 if(data_len) 1410 *buf2 = *iop_data; 1411 buf2 = (u_int32_t *)buf1; 1412 } 1413 while (iop_len > 0) { 1414 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex]; 1415 *pQbuffer = *buf1; 1416 acb->rqbuf_lastindex++; 1417 /* if last, index number set it to 0 */ 1418 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 1419 buf1++; 1420 iop_len--; 1421 } 1422 if(buf2) 1423 free( (u_int8_t *)buf2, M_DEVBUF); 1424 /* let IOP know data has been read */ 1425 arcmsr_iop_message_read(acb); 1426 return (1); 1427 } 1428 /* 1429 ************************************************************************** 1430 ************************************************************************** 1431 */ 1432 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, 1433 struct QBUFFER *prbuffer) { 1434 1435 u_int8_t *pQbuffer; 1436 u_int8_t *iop_data; 1437 u_int32_t iop_len; 1438 1439 if(acb->adapter_type == ACB_ADAPTER_TYPE_D) { 1440 return(arcmsr_Read_iop_rqbuffer_data_D(acb, prbuffer)); 1441 } 1442 iop_data = (u_int8_t *)prbuffer->data; 1443 iop_len = (u_int32_t)prbuffer->data_len; 1444 while (iop_len > 0) { 1445 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex]; 1446 *pQbuffer = *iop_data; 1447 acb->rqbuf_lastindex++; 1448 /* if last, index number set it to 0 */ 1449 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 1450 iop_data++; 1451 iop_len--; 1452 } 1453 /* let IOP know data has been read */ 1454 arcmsr_iop_message_read(acb); 1455 return (1); 1456 } 1457 /* 1458 ************************************************************************** 1459 ************************************************************************** 1460 */ 1461 static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb) 1462 { 1463 struct QBUFFER *prbuffer; 1464 int my_empty_len; 1465 1466 /*check this iop data if overflow my rqbuffer*/ 1467 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 1468 prbuffer = arcmsr_get_iop_rqbuffer(acb); 1469 my_empty_len = (acb->rqbuf_lastindex - acb->rqbuf_firstindex - 1) & 1470 (ARCMSR_MAX_QBUFFER-1); 1471 if(my_empty_len >= prbuffer->data_len) { 1472 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 1473 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 1474 } else { 1475 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 1476 } 1477 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 1478 } 1479 /* 1480 ********************************************************************** 1481 ********************************************************************** 1482 */ 1483 static void arcmsr_Write_data_2iop_wqbuffer_D(struct AdapterControlBlock *acb) 1484 { 1485 u_int8_t *pQbuffer; 1486 struct QBUFFER *pwbuffer; 1487 u_int8_t *buf1 = 0; 1488 u_int32_t *iop_data, *buf2 = 0; 1489 u_int32_t allxfer_len = 0, data_len; 1490 1491 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) { 1492 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO); 1493 buf2 = (u_int32_t *)buf1; 1494 if( buf1 == NULL) 1495 return; 1496 1497 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ); 1498 pwbuffer = arcmsr_get_iop_wqbuffer(acb); 1499 iop_data = (u_int32_t *)pwbuffer->data; 1500 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex) 1501 && (allxfer_len < 124)) { 1502 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex]; 1503 *buf1 = *pQbuffer; 1504 acb->wqbuf_firstindex++; 1505 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 1506 buf1++; 1507 allxfer_len++; 1508 } 1509 pwbuffer->data_len = allxfer_len; 1510 data_len = allxfer_len; 1511 buf1 = (u_int8_t *)buf2; 1512 while(data_len >= 4) 1513 { 1514 *iop_data++ = *buf2++; 1515 data_len -= 4; 1516 } 1517 if(data_len) 1518 *iop_data = *buf2; 1519 free( buf1, M_DEVBUF); 1520 arcmsr_iop_message_wrote(acb); 1521 } 1522 } 1523 /* 1524 ********************************************************************** 1525 ********************************************************************** 1526 */ 1527 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb) 1528 { 1529 u_int8_t *pQbuffer; 1530 struct QBUFFER *pwbuffer; 1531 u_int8_t *iop_data; 1532 int32_t allxfer_len=0; 1533 1534 if(acb->adapter_type == ACB_ADAPTER_TYPE_D) { 1535 arcmsr_Write_data_2iop_wqbuffer_D(acb); 1536 return; 1537 } 1538 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) { 1539 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ); 1540 pwbuffer = arcmsr_get_iop_wqbuffer(acb); 1541 iop_data = (u_int8_t *)pwbuffer->data; 1542 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex) 1543 && (allxfer_len < 124)) { 1544 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex]; 1545 *iop_data = *pQbuffer; 1546 acb->wqbuf_firstindex++; 1547 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 1548 iop_data++; 1549 allxfer_len++; 1550 } 1551 pwbuffer->data_len = allxfer_len; 1552 arcmsr_iop_message_wrote(acb); 1553 } 1554 } 1555 /* 1556 ************************************************************************** 1557 ************************************************************************** 1558 */ 1559 static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb) 1560 { 1561 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 1562 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READ; 1563 /* 1564 ***************************************************************** 1565 ** check if there are any mail packages from user space program 1566 ** in my post bag, now is the time to send them into Areca's firmware 1567 ***************************************************************** 1568 */ 1569 if(acb->wqbuf_firstindex != acb->wqbuf_lastindex) { 1570 arcmsr_Write_data_2iop_wqbuffer(acb); 1571 } 1572 if(acb->wqbuf_firstindex == acb->wqbuf_lastindex) { 1573 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED; 1574 } 1575 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 1576 } 1577 /* 1578 ************************************************************************** 1579 ************************************************************************** 1580 */ 1581 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb) 1582 { 1583 /* 1584 if (ccb->ccb_h.status != CAM_REQ_CMP) 1585 printf("arcmsr_rescanLun_cb: Rescan Target=%x, lun=%x," 1586 "failure status=%x\n", ccb->ccb_h.target_id, 1587 ccb->ccb_h.target_lun, ccb->ccb_h.status); 1588 else 1589 printf("arcmsr_rescanLun_cb: Rescan lun successfully!\n"); 1590 */ 1591 xpt_free_path(ccb->ccb_h.path); 1592 xpt_free_ccb(ccb); 1593 } 1594 1595 static void arcmsr_rescan_lun(struct AdapterControlBlock *acb, int target, int lun) 1596 { 1597 struct cam_path *path; 1598 union ccb *ccb; 1599 1600 if ((ccb = (union ccb *)xpt_alloc_ccb_nowait()) == NULL) 1601 return; 1602 if (xpt_create_path(&path, NULL, cam_sim_path(acb->psim), target, lun) 1603 != CAM_REQ_CMP) 1604 { 1605 xpt_free_ccb(ccb); 1606 return; 1607 } 1608 /* printf("arcmsr_rescan_lun: Rescan Target=%x, Lun=%x\n", target, lun); */ 1609 bzero(ccb, sizeof(union ccb)); 1610 xpt_setup_ccb(&ccb->ccb_h, path, 5); 1611 ccb->ccb_h.func_code = XPT_SCAN_LUN; 1612 ccb->ccb_h.cbfcnp = arcmsr_rescanLun_cb; 1613 ccb->crcn.flags = CAM_FLAG_NONE; 1614 xpt_action(ccb); 1615 } 1616 1617 1618 static void arcmsr_abort_dr_ccbs(struct AdapterControlBlock *acb, int target, int lun) 1619 { 1620 struct CommandControlBlock *srb; 1621 u_int32_t intmask_org; 1622 int i; 1623 1624 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 1625 /* disable all outbound interrupts */ 1626 intmask_org = arcmsr_disable_allintr(acb); 1627 for (i = 0; i < ARCMSR_MAX_FREESRB_NUM; i++) 1628 { 1629 srb = acb->psrb_pool[i]; 1630 if (srb->srb_state == ARCMSR_SRB_START) 1631 { 1632 if((target == srb->pccb->ccb_h.target_id) && (lun == srb->pccb->ccb_h.target_lun)) 1633 { 1634 srb->srb_state = ARCMSR_SRB_ABORTED; 1635 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 1636 arcmsr_srb_complete(srb, 1); 1637 printf("arcmsr%d: abort scsi id %d lun %d srb=%p \n", acb->pci_unit, target, lun, srb); 1638 } 1639 } 1640 } 1641 /* enable outbound Post Queue, outbound doorbell Interrupt */ 1642 arcmsr_enable_allintr(acb, intmask_org); 1643 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 1644 } 1645 /* 1646 ************************************************************************** 1647 ************************************************************************** 1648 */ 1649 static void arcmsr_dr_handle(struct AdapterControlBlock *acb) { 1650 u_int32_t devicemap; 1651 u_int32_t target, lun; 1652 u_int32_t deviceMapCurrent[4]={0}; 1653 u_int8_t *pDevMap; 1654 1655 switch (acb->adapter_type) { 1656 case ACB_ADAPTER_TYPE_A: 1657 devicemap = offsetof(struct HBA_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1658 for (target = 0; target < 4; target++) 1659 { 1660 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1661 devicemap += 4; 1662 } 1663 break; 1664 1665 case ACB_ADAPTER_TYPE_B: 1666 devicemap = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1667 for (target = 0; target < 4; target++) 1668 { 1669 deviceMapCurrent[target]=bus_space_read_4(acb->btag[1], acb->bhandle[1], devicemap); 1670 devicemap += 4; 1671 } 1672 break; 1673 1674 case ACB_ADAPTER_TYPE_C: 1675 devicemap = offsetof(struct HBC_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1676 for (target = 0; target < 4; target++) 1677 { 1678 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1679 devicemap += 4; 1680 } 1681 break; 1682 case ACB_ADAPTER_TYPE_D: 1683 devicemap = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1684 for (target = 0; target < 4; target++) 1685 { 1686 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1687 devicemap += 4; 1688 } 1689 break; 1690 } 1691 1692 if(acb->acb_flags & ACB_F_BUS_HANG_ON) 1693 { 1694 acb->acb_flags &= ~ACB_F_BUS_HANG_ON; 1695 } 1696 /* 1697 ** adapter posted CONFIG message 1698 ** copy the new map, note if there are differences with the current map 1699 */ 1700 pDevMap = (u_int8_t *)&deviceMapCurrent[0]; 1701 for (target = 0; target < ARCMSR_MAX_TARGETID - 1; target++) 1702 { 1703 if (*pDevMap != acb->device_map[target]) 1704 { 1705 u_int8_t difference, bit_check; 1706 1707 difference = *pDevMap ^ acb->device_map[target]; 1708 for(lun=0; lun < ARCMSR_MAX_TARGETLUN; lun++) 1709 { 1710 bit_check = (1 << lun); /*check bit from 0....31*/ 1711 if(difference & bit_check) 1712 { 1713 if(acb->device_map[target] & bit_check) 1714 {/* unit departed */ 1715 printf("arcmsr_dr_handle: Target=%x, lun=%x, GONE!!!\n",target,lun); 1716 arcmsr_abort_dr_ccbs(acb, target, lun); 1717 arcmsr_rescan_lun(acb, target, lun); 1718 acb->devstate[target][lun] = ARECA_RAID_GONE; 1719 } 1720 else 1721 {/* unit arrived */ 1722 printf("arcmsr_dr_handle: Target=%x, lun=%x, Plug-IN!!!\n",target,lun); 1723 arcmsr_rescan_lun(acb, target, lun); 1724 acb->devstate[target][lun] = ARECA_RAID_GOOD; 1725 } 1726 } 1727 } 1728 /* printf("arcmsr_dr_handle: acb->device_map[%x]=0x%x, deviceMapCurrent[%x]=%x\n",target,acb->device_map[target],target,*pDevMap); */ 1729 acb->device_map[target] = *pDevMap; 1730 } 1731 pDevMap++; 1732 } 1733 } 1734 /* 1735 ************************************************************************** 1736 ************************************************************************** 1737 */ 1738 static void arcmsr_hba_message_isr(struct AdapterControlBlock *acb) { 1739 u_int32_t outbound_message; 1740 1741 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT); 1742 outbound_message = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[0]); 1743 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1744 arcmsr_dr_handle( acb ); 1745 } 1746 /* 1747 ************************************************************************** 1748 ************************************************************************** 1749 */ 1750 static void arcmsr_hbb_message_isr(struct AdapterControlBlock *acb) { 1751 u_int32_t outbound_message; 1752 1753 /* clear interrupts */ 1754 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN); 1755 outbound_message = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0]); 1756 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1757 arcmsr_dr_handle( acb ); 1758 } 1759 /* 1760 ************************************************************************** 1761 ************************************************************************** 1762 */ 1763 static void arcmsr_hbc_message_isr(struct AdapterControlBlock *acb) { 1764 u_int32_t outbound_message; 1765 1766 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR); 1767 outbound_message = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[0]); 1768 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1769 arcmsr_dr_handle( acb ); 1770 } 1771 /* 1772 ************************************************************************** 1773 ************************************************************************** 1774 */ 1775 static void arcmsr_hbd_message_isr(struct AdapterControlBlock *acb) { 1776 u_int32_t outbound_message; 1777 1778 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR); 1779 outbound_message = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[0]); 1780 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1781 arcmsr_dr_handle( acb ); 1782 } 1783 /* 1784 ************************************************************************** 1785 ************************************************************************** 1786 */ 1787 static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb) 1788 { 1789 u_int32_t outbound_doorbell; 1790 1791 /* 1792 ******************************************************************* 1793 ** Maybe here we need to check wrqbuffer_lock is lock or not 1794 ** DOORBELL: din! don! 1795 ** check if there are any mail need to pack from firmware 1796 ******************************************************************* 1797 */ 1798 outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit, 1799 0, outbound_doorbell); 1800 CHIP_REG_WRITE32(HBA_MessageUnit, 1801 0, outbound_doorbell, outbound_doorbell); /* clear doorbell interrupt */ 1802 if(outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) { 1803 arcmsr_iop2drv_data_wrote_handle(acb); 1804 } 1805 if(outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) { 1806 arcmsr_iop2drv_data_read_handle(acb); 1807 } 1808 } 1809 /* 1810 ************************************************************************** 1811 ************************************************************************** 1812 */ 1813 static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *acb) 1814 { 1815 u_int32_t outbound_doorbell; 1816 1817 /* 1818 ******************************************************************* 1819 ** Maybe here we need to check wrqbuffer_lock is lock or not 1820 ** DOORBELL: din! don! 1821 ** check if there are any mail need to pack from firmware 1822 ******************************************************************* 1823 */ 1824 outbound_doorbell = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell); 1825 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell); /* clear doorbell interrupt */ 1826 if(outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) { 1827 arcmsr_iop2drv_data_wrote_handle(acb); 1828 } 1829 if(outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) { 1830 arcmsr_iop2drv_data_read_handle(acb); 1831 } 1832 if(outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 1833 arcmsr_hbc_message_isr(acb); /* messenger of "driver to iop commands" */ 1834 } 1835 } 1836 /* 1837 ************************************************************************** 1838 ************************************************************************** 1839 */ 1840 static void arcmsr_hbd_doorbell_isr(struct AdapterControlBlock *acb) 1841 { 1842 u_int32_t outbound_Doorbell; 1843 1844 /* 1845 ******************************************************************* 1846 ** Maybe here we need to check wrqbuffer_lock is lock or not 1847 ** DOORBELL: din! don! 1848 ** check if there are any mail need to pack from firmware 1849 ******************************************************************* 1850 */ 1851 outbound_Doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE; 1852 if(outbound_Doorbell) 1853 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_Doorbell); /* clear doorbell interrupt */ 1854 while( outbound_Doorbell & ARCMSR_HBDMU_F0_DOORBELL_CAUSE ) { 1855 if(outbound_Doorbell & ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK) { 1856 arcmsr_iop2drv_data_wrote_handle(acb); 1857 } 1858 if(outbound_Doorbell & ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK) { 1859 arcmsr_iop2drv_data_read_handle(acb); 1860 } 1861 if(outbound_Doorbell & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) { 1862 arcmsr_hbd_message_isr(acb); /* messenger of "driver to iop commands" */ 1863 } 1864 outbound_Doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE; 1865 if(outbound_Doorbell) 1866 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_Doorbell); /* clear doorbell interrupt */ 1867 } 1868 } 1869 /* 1870 ************************************************************************** 1871 ************************************************************************** 1872 */ 1873 static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb) 1874 { 1875 u_int32_t flag_srb; 1876 u_int16_t error; 1877 1878 /* 1879 ***************************************************************************** 1880 ** areca cdb command done 1881 ***************************************************************************** 1882 */ 1883 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 1884 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1885 while((flag_srb = CHIP_REG_READ32(HBA_MessageUnit, 1886 0, outbound_queueport)) != 0xFFFFFFFF) { 1887 /* check if command done with no error*/ 1888 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0) ? TRUE : FALSE; 1889 arcmsr_drain_donequeue(acb, flag_srb, error); 1890 } /*drain reply FIFO*/ 1891 } 1892 /* 1893 ************************************************************************** 1894 ************************************************************************** 1895 */ 1896 static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb) 1897 { 1898 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1899 u_int32_t flag_srb; 1900 int index; 1901 u_int16_t error; 1902 1903 /* 1904 ***************************************************************************** 1905 ** areca cdb command done 1906 ***************************************************************************** 1907 */ 1908 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 1909 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1910 index = phbbmu->doneq_index; 1911 while((flag_srb = phbbmu->done_qbuffer[index]) != 0) { 1912 phbbmu->done_qbuffer[index] = 0; 1913 index++; 1914 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 1915 phbbmu->doneq_index = index; 1916 /* check if command done with no error*/ 1917 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 1918 arcmsr_drain_donequeue(acb, flag_srb, error); 1919 } /*drain reply FIFO*/ 1920 } 1921 /* 1922 ************************************************************************** 1923 ************************************************************************** 1924 */ 1925 static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb) 1926 { 1927 u_int32_t flag_srb,throttling = 0; 1928 u_int16_t error; 1929 1930 /* 1931 ***************************************************************************** 1932 ** areca cdb command done 1933 ***************************************************************************** 1934 */ 1935 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1936 1937 while(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) { 1938 1939 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 1940 /* check if command done with no error*/ 1941 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE; 1942 arcmsr_drain_donequeue(acb, flag_srb, error); 1943 if(throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) { 1944 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING); 1945 break; 1946 } 1947 throttling++; 1948 } /*drain reply FIFO*/ 1949 } 1950 /* 1951 ********************************************************************** 1952 ** 1953 ********************************************************************** 1954 */ 1955 static uint16_t arcmsr_get_doneq_index(struct HBD_MessageUnit0 *phbdmu) 1956 { 1957 uint16_t doneq_index, index_stripped; 1958 1959 doneq_index = phbdmu->doneq_index; 1960 if (doneq_index & 0x4000) { 1961 index_stripped = doneq_index & 0xFF; 1962 index_stripped += 1; 1963 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1964 phbdmu->doneq_index = index_stripped ? 1965 (index_stripped | 0x4000) : index_stripped; 1966 } else { 1967 index_stripped = doneq_index; 1968 index_stripped += 1; 1969 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1970 phbdmu->doneq_index = index_stripped ? 1971 index_stripped : (index_stripped | 0x4000); 1972 } 1973 return (phbdmu->doneq_index); 1974 } 1975 /* 1976 ************************************************************************** 1977 ************************************************************************** 1978 */ 1979 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb) 1980 { 1981 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1982 u_int32_t outbound_write_pointer; 1983 u_int32_t addressLow; 1984 uint16_t doneq_index; 1985 u_int16_t error; 1986 /* 1987 ***************************************************************************** 1988 ** areca cdb command done 1989 ***************************************************************************** 1990 */ 1991 if((CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause) & 1992 ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT) == 0) 1993 return; 1994 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 1995 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1996 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 1997 doneq_index = phbdmu->doneq_index; 1998 while ((doneq_index & 0xFF) != (outbound_write_pointer & 0xFF)) { 1999 doneq_index = arcmsr_get_doneq_index(phbdmu); 2000 addressLow = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow; 2001 error = (addressLow & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 2002 arcmsr_drain_donequeue(acb, addressLow, error); /*Check if command done with no error */ 2003 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index); 2004 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 2005 } 2006 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_interrupt_cause, ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR); 2007 CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause); /*Dummy ioread32 to force pci flush */ 2008 } 2009 /* 2010 ********************************************************************** 2011 ********************************************************************** 2012 */ 2013 static void arcmsr_handle_hba_isr( struct AdapterControlBlock *acb) 2014 { 2015 u_int32_t outbound_intStatus; 2016 /* 2017 ********************************************* 2018 ** check outbound intstatus 2019 ********************************************* 2020 */ 2021 outbound_intStatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 2022 if(!outbound_intStatus) { 2023 /*it must be share irq*/ 2024 return; 2025 } 2026 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intStatus); /*clear interrupt*/ 2027 /* MU doorbell interrupts*/ 2028 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) { 2029 arcmsr_hba_doorbell_isr(acb); 2030 } 2031 /* MU post queue interrupts*/ 2032 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) { 2033 arcmsr_hba_postqueue_isr(acb); 2034 } 2035 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { 2036 arcmsr_hba_message_isr(acb); 2037 } 2038 } 2039 /* 2040 ********************************************************************** 2041 ********************************************************************** 2042 */ 2043 static void arcmsr_handle_hbb_isr( struct AdapterControlBlock *acb) 2044 { 2045 u_int32_t outbound_doorbell; 2046 /* 2047 ********************************************* 2048 ** check outbound intstatus 2049 ********************************************* 2050 */ 2051 outbound_doorbell = CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & acb->outbound_int_enable; 2052 if(!outbound_doorbell) { 2053 /*it must be share irq*/ 2054 return; 2055 } 2056 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ~outbound_doorbell); /* clear doorbell interrupt */ 2057 CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell); 2058 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 2059 /* MU ioctl transfer doorbell interrupts*/ 2060 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) { 2061 arcmsr_iop2drv_data_wrote_handle(acb); 2062 } 2063 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) { 2064 arcmsr_iop2drv_data_read_handle(acb); 2065 } 2066 /* MU post queue interrupts*/ 2067 if(outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) { 2068 arcmsr_hbb_postqueue_isr(acb); 2069 } 2070 if(outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) { 2071 arcmsr_hbb_message_isr(acb); 2072 } 2073 } 2074 /* 2075 ********************************************************************** 2076 ********************************************************************** 2077 */ 2078 static void arcmsr_handle_hbc_isr( struct AdapterControlBlock *acb) 2079 { 2080 u_int32_t host_interrupt_status; 2081 /* 2082 ********************************************* 2083 ** check outbound intstatus 2084 ********************************************* 2085 */ 2086 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status); 2087 if(!host_interrupt_status) { 2088 /*it must be share irq*/ 2089 return; 2090 } 2091 /* MU doorbell interrupts*/ 2092 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) { 2093 arcmsr_hbc_doorbell_isr(acb); 2094 } 2095 /* MU post queue interrupts*/ 2096 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) { 2097 arcmsr_hbc_postqueue_isr(acb); 2098 } 2099 } 2100 /* 2101 ********************************************************************** 2102 ********************************************************************** 2103 */ 2104 static void arcmsr_handle_hbd_isr( struct AdapterControlBlock *acb) 2105 { 2106 u_int32_t host_interrupt_status; 2107 u_int32_t intmask_org; 2108 /* 2109 ********************************************* 2110 ** check outbound intstatus 2111 ********************************************* 2112 */ 2113 host_interrupt_status = CHIP_REG_READ32(HBD_MessageUnit, 0, host_int_status) & acb->outbound_int_enable; 2114 if(!(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_INT)) { 2115 /*it must be share irq*/ 2116 return; 2117 } 2118 /* disable outbound interrupt */ 2119 intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable) ; /* disable outbound message0 int */ 2120 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE); 2121 /* MU doorbell interrupts*/ 2122 if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT) { 2123 arcmsr_hbd_doorbell_isr(acb); 2124 } 2125 /* MU post queue interrupts*/ 2126 if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT) { 2127 arcmsr_hbd_postqueue_isr(acb); 2128 } 2129 /* enable all outbound interrupt */ 2130 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | ARCMSR_HBDMU_ALL_INT_ENABLE); 2131 // CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); 2132 } 2133 /* 2134 ****************************************************************************** 2135 ****************************************************************************** 2136 */ 2137 static void arcmsr_interrupt(struct AdapterControlBlock *acb) 2138 { 2139 switch (acb->adapter_type) { 2140 case ACB_ADAPTER_TYPE_A: 2141 arcmsr_handle_hba_isr(acb); 2142 break; 2143 case ACB_ADAPTER_TYPE_B: 2144 arcmsr_handle_hbb_isr(acb); 2145 break; 2146 case ACB_ADAPTER_TYPE_C: 2147 arcmsr_handle_hbc_isr(acb); 2148 break; 2149 case ACB_ADAPTER_TYPE_D: 2150 arcmsr_handle_hbd_isr(acb); 2151 break; 2152 default: 2153 printf("arcmsr%d: interrupt service," 2154 " unknown adapter type =%d\n", acb->pci_unit, acb->adapter_type); 2155 break; 2156 } 2157 } 2158 /* 2159 ********************************************************************** 2160 ********************************************************************** 2161 */ 2162 static void arcmsr_intr_handler(void *arg) 2163 { 2164 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg; 2165 2166 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 2167 arcmsr_interrupt(acb); 2168 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 2169 } 2170 /* 2171 ****************************************************************************** 2172 ****************************************************************************** 2173 */ 2174 static void arcmsr_polling_devmap(void *arg) 2175 { 2176 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg; 2177 switch (acb->adapter_type) { 2178 case ACB_ADAPTER_TYPE_A: 2179 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2180 break; 2181 2182 case ACB_ADAPTER_TYPE_B: 2183 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG); 2184 break; 2185 2186 case ACB_ADAPTER_TYPE_C: 2187 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2188 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 2189 break; 2190 2191 case ACB_ADAPTER_TYPE_D: 2192 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2193 break; 2194 } 2195 2196 if((acb->acb_flags & ACB_F_SCSISTOPADAPTER) == 0) 2197 { 2198 callout_reset(&acb->devmap_callout, 5 * hz, arcmsr_polling_devmap, acb); /* polling per 5 seconds */ 2199 } 2200 } 2201 2202 /* 2203 ******************************************************************************* 2204 ** 2205 ******************************************************************************* 2206 */ 2207 static void arcmsr_iop_parking(struct AdapterControlBlock *acb) 2208 { 2209 u_int32_t intmask_org; 2210 2211 if(acb != NULL) { 2212 /* stop adapter background rebuild */ 2213 if(acb->acb_flags & ACB_F_MSG_START_BGRB) { 2214 intmask_org = arcmsr_disable_allintr(acb); 2215 arcmsr_stop_adapter_bgrb(acb); 2216 arcmsr_flush_adapter_cache(acb); 2217 arcmsr_enable_allintr(acb, intmask_org); 2218 } 2219 } 2220 } 2221 /* 2222 *********************************************************************** 2223 ** 2224 ************************************************************************ 2225 */ 2226 u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg) 2227 { 2228 struct CMD_MESSAGE_FIELD *pcmdmessagefld; 2229 u_int32_t retvalue = EINVAL; 2230 2231 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) arg; 2232 if(memcmp(pcmdmessagefld->cmdmessage.Signature, "ARCMSR", 6)!=0) { 2233 return retvalue; 2234 } 2235 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2236 switch(ioctl_cmd) { 2237 case ARCMSR_MESSAGE_READ_RQBUFFER: { 2238 u_int8_t *pQbuffer; 2239 u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer; 2240 u_int32_t allxfer_len=0; 2241 2242 while((acb->rqbuf_firstindex != acb->rqbuf_lastindex) 2243 && (allxfer_len < 1031)) { 2244 /*copy READ QBUFFER to srb*/ 2245 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex]; 2246 *ptmpQbuffer = *pQbuffer; 2247 acb->rqbuf_firstindex++; 2248 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 2249 /*if last index number set it to 0 */ 2250 ptmpQbuffer++; 2251 allxfer_len++; 2252 } 2253 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2254 struct QBUFFER *prbuffer; 2255 2256 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2257 prbuffer = arcmsr_get_iop_rqbuffer(acb); 2258 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 2259 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 2260 } 2261 pcmdmessagefld->cmdmessage.Length = allxfer_len; 2262 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2263 retvalue = ARCMSR_MESSAGE_SUCCESS; 2264 } 2265 break; 2266 case ARCMSR_MESSAGE_WRITE_WQBUFFER: { 2267 u_int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex; 2268 u_int8_t *pQbuffer; 2269 u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer; 2270 2271 user_len = pcmdmessagefld->cmdmessage.Length; 2272 /*check if data xfer length of this request will overflow my array qbuffer */ 2273 wqbuf_lastindex = acb->wqbuf_lastindex; 2274 wqbuf_firstindex = acb->wqbuf_firstindex; 2275 if(wqbuf_lastindex != wqbuf_firstindex) { 2276 arcmsr_Write_data_2iop_wqbuffer(acb); 2277 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2278 } else { 2279 my_empty_len = (wqbuf_firstindex - wqbuf_lastindex - 1) & 2280 (ARCMSR_MAX_QBUFFER - 1); 2281 if(my_empty_len >= user_len) { 2282 while(user_len > 0) { 2283 /*copy srb data to wqbuffer*/ 2284 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex]; 2285 *pQbuffer = *ptmpuserbuffer; 2286 acb->wqbuf_lastindex++; 2287 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 2288 /*if last index number set it to 0 */ 2289 ptmpuserbuffer++; 2290 user_len--; 2291 } 2292 /*post fist Qbuffer*/ 2293 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) { 2294 acb->acb_flags &= ~ACB_F_MESSAGE_WQBUFFER_CLEARED; 2295 arcmsr_Write_data_2iop_wqbuffer(acb); 2296 } 2297 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2298 } else { 2299 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2300 } 2301 } 2302 retvalue = ARCMSR_MESSAGE_SUCCESS; 2303 } 2304 break; 2305 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: { 2306 u_int8_t *pQbuffer = acb->rqbuffer; 2307 2308 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2309 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2310 arcmsr_iop_message_read(acb); 2311 /*signature, let IOP know data has been readed */ 2312 } 2313 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 2314 acb->rqbuf_firstindex = 0; 2315 acb->rqbuf_lastindex = 0; 2316 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2317 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2318 retvalue = ARCMSR_MESSAGE_SUCCESS; 2319 } 2320 break; 2321 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: 2322 { 2323 u_int8_t *pQbuffer = acb->wqbuffer; 2324 2325 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2326 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2327 arcmsr_iop_message_read(acb); 2328 /*signature, let IOP know data has been readed */ 2329 } 2330 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ); 2331 acb->wqbuf_firstindex = 0; 2332 acb->wqbuf_lastindex = 0; 2333 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2334 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2335 retvalue = ARCMSR_MESSAGE_SUCCESS; 2336 } 2337 break; 2338 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: { 2339 u_int8_t *pQbuffer; 2340 2341 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2342 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2343 arcmsr_iop_message_read(acb); 2344 /*signature, let IOP know data has been readed */ 2345 } 2346 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED 2347 |ACB_F_MESSAGE_RQBUFFER_CLEARED 2348 |ACB_F_MESSAGE_WQBUFFER_READ); 2349 acb->rqbuf_firstindex = 0; 2350 acb->rqbuf_lastindex = 0; 2351 acb->wqbuf_firstindex = 0; 2352 acb->wqbuf_lastindex = 0; 2353 pQbuffer = acb->rqbuffer; 2354 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 2355 pQbuffer = acb->wqbuffer; 2356 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 2357 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2358 retvalue = ARCMSR_MESSAGE_SUCCESS; 2359 } 2360 break; 2361 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: { 2362 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F; 2363 retvalue = ARCMSR_MESSAGE_SUCCESS; 2364 } 2365 break; 2366 case ARCMSR_MESSAGE_SAY_HELLO: { 2367 u_int8_t *hello_string = "Hello! I am ARCMSR"; 2368 u_int8_t *puserbuffer = (u_int8_t *)pcmdmessagefld->messagedatabuffer; 2369 2370 if(memcpy(puserbuffer, hello_string, (int16_t)strlen(hello_string))) { 2371 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2372 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2373 return ENOIOCTL; 2374 } 2375 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2376 retvalue = ARCMSR_MESSAGE_SUCCESS; 2377 } 2378 break; 2379 case ARCMSR_MESSAGE_SAY_GOODBYE: { 2380 arcmsr_iop_parking(acb); 2381 retvalue = ARCMSR_MESSAGE_SUCCESS; 2382 } 2383 break; 2384 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: { 2385 arcmsr_flush_adapter_cache(acb); 2386 retvalue = ARCMSR_MESSAGE_SUCCESS; 2387 } 2388 break; 2389 } 2390 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2391 return (retvalue); 2392 } 2393 /* 2394 ************************************************************************** 2395 ************************************************************************** 2396 */ 2397 static void arcmsr_free_srb(struct CommandControlBlock *srb) 2398 { 2399 struct AdapterControlBlock *acb; 2400 2401 acb = srb->acb; 2402 ARCMSR_LOCK_ACQUIRE(&acb->srb_lock); 2403 srb->srb_state = ARCMSR_SRB_DONE; 2404 srb->srb_flags = 0; 2405 acb->srbworkingQ[acb->workingsrb_doneindex] = srb; 2406 acb->workingsrb_doneindex++; 2407 acb->workingsrb_doneindex %= ARCMSR_MAX_FREESRB_NUM; 2408 ARCMSR_LOCK_RELEASE(&acb->srb_lock); 2409 } 2410 /* 2411 ************************************************************************** 2412 ************************************************************************** 2413 */ 2414 struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb) 2415 { 2416 struct CommandControlBlock *srb = NULL; 2417 u_int32_t workingsrb_startindex, workingsrb_doneindex; 2418 2419 ARCMSR_LOCK_ACQUIRE(&acb->srb_lock); 2420 workingsrb_doneindex = acb->workingsrb_doneindex; 2421 workingsrb_startindex = acb->workingsrb_startindex; 2422 srb = acb->srbworkingQ[workingsrb_startindex]; 2423 workingsrb_startindex++; 2424 workingsrb_startindex %= ARCMSR_MAX_FREESRB_NUM; 2425 if(workingsrb_doneindex != workingsrb_startindex) { 2426 acb->workingsrb_startindex = workingsrb_startindex; 2427 } else { 2428 srb = NULL; 2429 } 2430 ARCMSR_LOCK_RELEASE(&acb->srb_lock); 2431 return(srb); 2432 } 2433 /* 2434 ************************************************************************** 2435 ************************************************************************** 2436 */ 2437 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb) 2438 { 2439 struct CMD_MESSAGE_FIELD *pcmdmessagefld; 2440 int retvalue = 0, transfer_len = 0; 2441 char *buffer; 2442 u_int32_t controlcode = (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[5] << 24 | 2443 (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[6] << 16 | 2444 (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[7] << 8 | 2445 (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[8]; 2446 /* 4 bytes: Areca io control code */ 2447 if ((pccb->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_VADDR) { 2448 buffer = pccb->csio.data_ptr; 2449 transfer_len = pccb->csio.dxfer_len; 2450 } else { 2451 retvalue = ARCMSR_MESSAGE_FAIL; 2452 goto message_out; 2453 } 2454 if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) { 2455 retvalue = ARCMSR_MESSAGE_FAIL; 2456 goto message_out; 2457 } 2458 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) buffer; 2459 switch(controlcode) { 2460 case ARCMSR_MESSAGE_READ_RQBUFFER: { 2461 u_int8_t *pQbuffer; 2462 u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer; 2463 int32_t allxfer_len = 0; 2464 2465 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2466 while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex) 2467 && (allxfer_len < 1031)) { 2468 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex]; 2469 *ptmpQbuffer = *pQbuffer; 2470 acb->rqbuf_firstindex++; 2471 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 2472 ptmpQbuffer++; 2473 allxfer_len++; 2474 } 2475 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2476 struct QBUFFER *prbuffer; 2477 2478 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2479 prbuffer = arcmsr_get_iop_rqbuffer(acb); 2480 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 2481 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 2482 } 2483 pcmdmessagefld->cmdmessage.Length = allxfer_len; 2484 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2485 retvalue = ARCMSR_MESSAGE_SUCCESS; 2486 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2487 } 2488 break; 2489 case ARCMSR_MESSAGE_WRITE_WQBUFFER: { 2490 int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex; 2491 u_int8_t *pQbuffer; 2492 u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer; 2493 2494 user_len = pcmdmessagefld->cmdmessage.Length; 2495 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2496 wqbuf_lastindex = acb->wqbuf_lastindex; 2497 wqbuf_firstindex = acb->wqbuf_firstindex; 2498 if (wqbuf_lastindex != wqbuf_firstindex) { 2499 arcmsr_Write_data_2iop_wqbuffer(acb); 2500 /* has error report sensedata */ 2501 if(pccb->csio.sense_len) { 2502 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); 2503 /* Valid,ErrorCode */ 2504 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05; 2505 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */ 2506 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A; 2507 /* AdditionalSenseLength */ 2508 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20; 2509 /* AdditionalSenseCode */ 2510 } 2511 retvalue = ARCMSR_MESSAGE_FAIL; 2512 } else { 2513 my_empty_len = (wqbuf_firstindex-wqbuf_lastindex - 1) 2514 &(ARCMSR_MAX_QBUFFER - 1); 2515 if (my_empty_len >= user_len) { 2516 while (user_len > 0) { 2517 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex]; 2518 *pQbuffer = *ptmpuserbuffer; 2519 acb->wqbuf_lastindex++; 2520 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 2521 ptmpuserbuffer++; 2522 user_len--; 2523 } 2524 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) { 2525 acb->acb_flags &= 2526 ~ACB_F_MESSAGE_WQBUFFER_CLEARED; 2527 arcmsr_Write_data_2iop_wqbuffer(acb); 2528 } 2529 } else { 2530 /* has error report sensedata */ 2531 if(pccb->csio.sense_len) { 2532 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); 2533 /* Valid,ErrorCode */ 2534 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05; 2535 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */ 2536 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A; 2537 /* AdditionalSenseLength */ 2538 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20; 2539 /* AdditionalSenseCode */ 2540 } 2541 retvalue = ARCMSR_MESSAGE_FAIL; 2542 } 2543 } 2544 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2545 } 2546 break; 2547 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: { 2548 u_int8_t *pQbuffer = acb->rqbuffer; 2549 2550 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2551 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2552 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2553 arcmsr_iop_message_read(acb); 2554 } 2555 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 2556 acb->rqbuf_firstindex = 0; 2557 acb->rqbuf_lastindex = 0; 2558 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2559 pcmdmessagefld->cmdmessage.ReturnCode = 2560 ARCMSR_MESSAGE_RETURNCODE_OK; 2561 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2562 } 2563 break; 2564 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: { 2565 u_int8_t *pQbuffer = acb->wqbuffer; 2566 2567 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2568 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2569 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2570 arcmsr_iop_message_read(acb); 2571 } 2572 acb->acb_flags |= 2573 (ACB_F_MESSAGE_WQBUFFER_CLEARED | 2574 ACB_F_MESSAGE_WQBUFFER_READ); 2575 acb->wqbuf_firstindex = 0; 2576 acb->wqbuf_lastindex = 0; 2577 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2578 pcmdmessagefld->cmdmessage.ReturnCode = 2579 ARCMSR_MESSAGE_RETURNCODE_OK; 2580 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2581 } 2582 break; 2583 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: { 2584 u_int8_t *pQbuffer; 2585 2586 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2587 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2588 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2589 arcmsr_iop_message_read(acb); 2590 } 2591 acb->acb_flags |= 2592 (ACB_F_MESSAGE_WQBUFFER_CLEARED 2593 | ACB_F_MESSAGE_RQBUFFER_CLEARED 2594 | ACB_F_MESSAGE_WQBUFFER_READ); 2595 acb->rqbuf_firstindex = 0; 2596 acb->rqbuf_lastindex = 0; 2597 acb->wqbuf_firstindex = 0; 2598 acb->wqbuf_lastindex = 0; 2599 pQbuffer = acb->rqbuffer; 2600 memset(pQbuffer, 0, sizeof (struct QBUFFER)); 2601 pQbuffer = acb->wqbuffer; 2602 memset(pQbuffer, 0, sizeof (struct QBUFFER)); 2603 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2604 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2605 } 2606 break; 2607 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: { 2608 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F; 2609 } 2610 break; 2611 case ARCMSR_MESSAGE_SAY_HELLO: { 2612 int8_t *hello_string = "Hello! I am ARCMSR"; 2613 2614 memcpy(pcmdmessagefld->messagedatabuffer, hello_string 2615 , (int16_t)strlen(hello_string)); 2616 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2617 } 2618 break; 2619 case ARCMSR_MESSAGE_SAY_GOODBYE: 2620 arcmsr_iop_parking(acb); 2621 break; 2622 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: 2623 arcmsr_flush_adapter_cache(acb); 2624 break; 2625 default: 2626 retvalue = ARCMSR_MESSAGE_FAIL; 2627 } 2628 message_out: 2629 return (retvalue); 2630 } 2631 /* 2632 ********************************************************************* 2633 ********************************************************************* 2634 */ 2635 static void arcmsr_execute_srb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 2636 { 2637 struct CommandControlBlock *srb = (struct CommandControlBlock *)arg; 2638 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)srb->acb; 2639 union ccb *pccb; 2640 int target, lun; 2641 2642 pccb = srb->pccb; 2643 target = pccb->ccb_h.target_id; 2644 lun = pccb->ccb_h.target_lun; 2645 acb->pktRequestCount++; 2646 if(error != 0) { 2647 if(error != EFBIG) { 2648 printf("arcmsr%d: unexpected error %x" 2649 " returned from 'bus_dmamap_load' \n" 2650 , acb->pci_unit, error); 2651 } 2652 if((pccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_INPROG) { 2653 pccb->ccb_h.status |= CAM_REQ_TOO_BIG; 2654 } 2655 arcmsr_srb_complete(srb, 0); 2656 return; 2657 } 2658 if(nseg > ARCMSR_MAX_SG_ENTRIES) { 2659 pccb->ccb_h.status |= CAM_REQ_TOO_BIG; 2660 arcmsr_srb_complete(srb, 0); 2661 return; 2662 } 2663 if(acb->acb_flags & ACB_F_BUS_RESET) { 2664 printf("arcmsr%d: bus reset and return busy \n", acb->pci_unit); 2665 pccb->ccb_h.status |= CAM_SCSI_BUS_RESET; 2666 arcmsr_srb_complete(srb, 0); 2667 return; 2668 } 2669 if(acb->devstate[target][lun] == ARECA_RAID_GONE) { 2670 u_int8_t block_cmd, cmd; 2671 2672 cmd = pccb->csio.cdb_io.cdb_bytes[0]; 2673 block_cmd = cmd & 0x0f; 2674 if(block_cmd == 0x08 || block_cmd == 0x0a) { 2675 printf("arcmsr%d:block 'read/write' command " 2676 "with gone raid volume Cmd=0x%2x, TargetId=%d, Lun=%d \n" 2677 , acb->pci_unit, cmd, target, lun); 2678 pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 2679 arcmsr_srb_complete(srb, 0); 2680 return; 2681 } 2682 } 2683 if((pccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_INPROG) { 2684 if(nseg != 0) { 2685 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap); 2686 } 2687 arcmsr_srb_complete(srb, 0); 2688 return; 2689 } 2690 if(acb->srboutstandingcount >= acb->firm_numbers_queue) { 2691 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) == 0) 2692 { 2693 xpt_freeze_simq(acb->psim, 1); 2694 acb->acb_flags |= ACB_F_CAM_DEV_QFRZN; 2695 } 2696 pccb->ccb_h.status &= ~CAM_SIM_QUEUED; 2697 pccb->ccb_h.status |= CAM_REQUEUE_REQ; 2698 arcmsr_srb_complete(srb, 0); 2699 return; 2700 } 2701 pccb->ccb_h.status |= CAM_SIM_QUEUED; 2702 arcmsr_build_srb(srb, dm_segs, nseg); 2703 arcmsr_post_srb(acb, srb); 2704 if (pccb->ccb_h.timeout != CAM_TIME_INFINITY) 2705 { 2706 arcmsr_callout_init(&srb->ccb_callout); 2707 callout_reset(&srb->ccb_callout, ((pccb->ccb_h.timeout + (ARCMSR_TIMEOUT_DELAY * 1000)) * hz) / 1000, arcmsr_srb_timeout, srb); 2708 srb->srb_flags |= SRB_FLAG_TIMER_START; 2709 } 2710 } 2711 /* 2712 ***************************************************************************************** 2713 ***************************************************************************************** 2714 */ 2715 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb) 2716 { 2717 struct CommandControlBlock *srb; 2718 struct AdapterControlBlock *acb = (struct AdapterControlBlock *) abortccb->ccb_h.arcmsr_ccbacb_ptr; 2719 u_int32_t intmask_org; 2720 int i = 0; 2721 2722 acb->num_aborts++; 2723 /* 2724 *************************************************************************** 2725 ** It is the upper layer do abort command this lock just prior to calling us. 2726 ** First determine if we currently own this command. 2727 ** Start by searching the device queue. If not found 2728 ** at all, and the system wanted us to just abort the 2729 ** command return success. 2730 *************************************************************************** 2731 */ 2732 if(acb->srboutstandingcount != 0) { 2733 /* disable all outbound interrupt */ 2734 intmask_org = arcmsr_disable_allintr(acb); 2735 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 2736 srb = acb->psrb_pool[i]; 2737 if(srb->srb_state == ARCMSR_SRB_START) { 2738 if(srb->pccb == abortccb) { 2739 srb->srb_state = ARCMSR_SRB_ABORTED; 2740 printf("arcmsr%d:scsi id=%d lun=%d abort srb '%p'" 2741 "outstanding command \n" 2742 , acb->pci_unit, abortccb->ccb_h.target_id 2743 , abortccb->ccb_h.target_lun, srb); 2744 arcmsr_polling_srbdone(acb, srb); 2745 /* enable outbound Post Queue, outbound doorbell Interrupt */ 2746 arcmsr_enable_allintr(acb, intmask_org); 2747 return (TRUE); 2748 } 2749 } 2750 } 2751 /* enable outbound Post Queue, outbound doorbell Interrupt */ 2752 arcmsr_enable_allintr(acb, intmask_org); 2753 } 2754 return(FALSE); 2755 } 2756 /* 2757 **************************************************************************** 2758 **************************************************************************** 2759 */ 2760 static void arcmsr_bus_reset(struct AdapterControlBlock *acb) 2761 { 2762 int retry = 0; 2763 2764 acb->num_resets++; 2765 acb->acb_flags |= ACB_F_BUS_RESET; 2766 while(acb->srboutstandingcount != 0 && retry < 400) { 2767 arcmsr_interrupt(acb); 2768 UDELAY(25000); 2769 retry++; 2770 } 2771 arcmsr_iop_reset(acb); 2772 acb->acb_flags &= ~ACB_F_BUS_RESET; 2773 } 2774 /* 2775 ************************************************************************** 2776 ************************************************************************** 2777 */ 2778 static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb, 2779 union ccb *pccb) 2780 { 2781 if (pccb->ccb_h.target_lun) { 2782 pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 2783 xpt_done(pccb); 2784 return; 2785 } 2786 pccb->ccb_h.status |= CAM_REQ_CMP; 2787 switch (pccb->csio.cdb_io.cdb_bytes[0]) { 2788 case INQUIRY: { 2789 unsigned char inqdata[36]; 2790 char *buffer = pccb->csio.data_ptr; 2791 2792 inqdata[0] = T_PROCESSOR; /* Periph Qualifier & Periph Dev Type */ 2793 inqdata[1] = 0; /* rem media bit & Dev Type Modifier */ 2794 inqdata[2] = 0; /* ISO, ECMA, & ANSI versions */ 2795 inqdata[3] = 0; 2796 inqdata[4] = 31; /* length of additional data */ 2797 inqdata[5] = 0; 2798 inqdata[6] = 0; 2799 inqdata[7] = 0; 2800 strncpy(&inqdata[8], "Areca ", 8); /* Vendor Identification */ 2801 strncpy(&inqdata[16], "RAID controller ", 16); /* Product Identification */ 2802 strncpy(&inqdata[32], "R001", 4); /* Product Revision */ 2803 memcpy(buffer, inqdata, sizeof(inqdata)); 2804 xpt_done(pccb); 2805 } 2806 break; 2807 case WRITE_BUFFER: 2808 case READ_BUFFER: { 2809 if (arcmsr_iop_message_xfer(acb, pccb)) { 2810 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 2811 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 2812 } 2813 xpt_done(pccb); 2814 } 2815 break; 2816 default: 2817 xpt_done(pccb); 2818 } 2819 } 2820 /* 2821 ********************************************************************* 2822 ********************************************************************* 2823 */ 2824 static void arcmsr_action(struct cam_sim *psim, union ccb *pccb) 2825 { 2826 struct AdapterControlBlock *acb; 2827 2828 acb = (struct AdapterControlBlock *) cam_sim_softc(psim); 2829 if(acb == NULL) { 2830 pccb->ccb_h.status |= CAM_REQ_INVALID; 2831 xpt_done(pccb); 2832 return; 2833 } 2834 switch (pccb->ccb_h.func_code) { 2835 case XPT_SCSI_IO: { 2836 struct CommandControlBlock *srb; 2837 int target = pccb->ccb_h.target_id; 2838 int error; 2839 2840 if(target == 16) { 2841 /* virtual device for iop message transfer */ 2842 arcmsr_handle_virtual_command(acb, pccb); 2843 return; 2844 } 2845 if((srb = arcmsr_get_freesrb(acb)) == NULL) { 2846 pccb->ccb_h.status |= CAM_RESRC_UNAVAIL; 2847 xpt_done(pccb); 2848 return; 2849 } 2850 pccb->ccb_h.arcmsr_ccbsrb_ptr = srb; 2851 pccb->ccb_h.arcmsr_ccbacb_ptr = acb; 2852 srb->pccb = pccb; 2853 error = bus_dmamap_load_ccb(acb->dm_segs_dmat 2854 , srb->dm_segs_dmamap 2855 , pccb 2856 , arcmsr_execute_srb, srb, /*flags*/0); 2857 if(error == EINPROGRESS) { 2858 xpt_freeze_simq(acb->psim, 1); 2859 pccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2860 } 2861 break; 2862 } 2863 case XPT_TARGET_IO: { 2864 /* target mode not yet support vendor specific commands. */ 2865 pccb->ccb_h.status |= CAM_REQ_CMP; 2866 xpt_done(pccb); 2867 break; 2868 } 2869 case XPT_PATH_INQ: { 2870 struct ccb_pathinq *cpi = &pccb->cpi; 2871 2872 cpi->version_num = 1; 2873 cpi->hba_inquiry = PI_SDTR_ABLE | PI_TAG_ABLE; 2874 cpi->target_sprt = 0; 2875 cpi->hba_misc = 0; 2876 cpi->hba_eng_cnt = 0; 2877 cpi->max_target = ARCMSR_MAX_TARGETID; /* 0-16 */ 2878 cpi->max_lun = ARCMSR_MAX_TARGETLUN; /* 0-7 */ 2879 cpi->initiator_id = ARCMSR_SCSI_INITIATOR_ID; /* 255 */ 2880 cpi->bus_id = cam_sim_bus(psim); 2881 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2882 strncpy(cpi->hba_vid, "ARCMSR", HBA_IDLEN); 2883 strncpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN); 2884 cpi->unit_number = cam_sim_unit(psim); 2885 #ifdef CAM_NEW_TRAN_CODE 2886 if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G) 2887 cpi->base_transfer_speed = 600000; 2888 else 2889 cpi->base_transfer_speed = 300000; 2890 if((acb->vendor_device_id == PCIDevVenIDARC1880) || 2891 (acb->vendor_device_id == PCIDevVenIDARC1680) || 2892 (acb->vendor_device_id == PCIDevVenIDARC1214)) 2893 { 2894 cpi->transport = XPORT_SAS; 2895 cpi->transport_version = 0; 2896 cpi->protocol_version = SCSI_REV_SPC2; 2897 } 2898 else 2899 { 2900 cpi->transport = XPORT_SPI; 2901 cpi->transport_version = 2; 2902 cpi->protocol_version = SCSI_REV_2; 2903 } 2904 cpi->protocol = PROTO_SCSI; 2905 #endif 2906 cpi->ccb_h.status |= CAM_REQ_CMP; 2907 xpt_done(pccb); 2908 break; 2909 } 2910 case XPT_ABORT: { 2911 union ccb *pabort_ccb; 2912 2913 pabort_ccb = pccb->cab.abort_ccb; 2914 switch (pabort_ccb->ccb_h.func_code) { 2915 case XPT_ACCEPT_TARGET_IO: 2916 case XPT_IMMED_NOTIFY: 2917 case XPT_CONT_TARGET_IO: 2918 if(arcmsr_seek_cmd2abort(pabort_ccb)==TRUE) { 2919 pabort_ccb->ccb_h.status |= CAM_REQ_ABORTED; 2920 xpt_done(pabort_ccb); 2921 pccb->ccb_h.status |= CAM_REQ_CMP; 2922 } else { 2923 xpt_print_path(pabort_ccb->ccb_h.path); 2924 printf("Not found\n"); 2925 pccb->ccb_h.status |= CAM_PATH_INVALID; 2926 } 2927 break; 2928 case XPT_SCSI_IO: 2929 pccb->ccb_h.status |= CAM_UA_ABORT; 2930 break; 2931 default: 2932 pccb->ccb_h.status |= CAM_REQ_INVALID; 2933 break; 2934 } 2935 xpt_done(pccb); 2936 break; 2937 } 2938 case XPT_RESET_BUS: 2939 case XPT_RESET_DEV: { 2940 u_int32_t i; 2941 2942 arcmsr_bus_reset(acb); 2943 for (i=0; i < 500; i++) { 2944 DELAY(1000); 2945 } 2946 pccb->ccb_h.status |= CAM_REQ_CMP; 2947 xpt_done(pccb); 2948 break; 2949 } 2950 case XPT_TERM_IO: { 2951 pccb->ccb_h.status |= CAM_REQ_INVALID; 2952 xpt_done(pccb); 2953 break; 2954 } 2955 case XPT_GET_TRAN_SETTINGS: { 2956 struct ccb_trans_settings *cts; 2957 2958 if(pccb->ccb_h.target_id == 16) { 2959 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 2960 xpt_done(pccb); 2961 break; 2962 } 2963 cts = &pccb->cts; 2964 #ifdef CAM_NEW_TRAN_CODE 2965 { 2966 struct ccb_trans_settings_scsi *scsi; 2967 struct ccb_trans_settings_spi *spi; 2968 struct ccb_trans_settings_sas *sas; 2969 2970 scsi = &cts->proto_specific.scsi; 2971 scsi->flags = CTS_SCSI_FLAGS_TAG_ENB; 2972 scsi->valid = CTS_SCSI_VALID_TQ; 2973 cts->protocol = PROTO_SCSI; 2974 2975 if((acb->vendor_device_id == PCIDevVenIDARC1880) || 2976 (acb->vendor_device_id == PCIDevVenIDARC1680) || 2977 (acb->vendor_device_id == PCIDevVenIDARC1214)) 2978 { 2979 cts->protocol_version = SCSI_REV_SPC2; 2980 cts->transport_version = 0; 2981 cts->transport = XPORT_SAS; 2982 sas = &cts->xport_specific.sas; 2983 sas->valid = CTS_SAS_VALID_SPEED; 2984 if((acb->vendor_device_id == PCIDevVenIDARC1880) || 2985 (acb->vendor_device_id == PCIDevVenIDARC1214)) 2986 sas->bitrate = 600000; 2987 else if(acb->vendor_device_id == PCIDevVenIDARC1680) 2988 sas->bitrate = 300000; 2989 } 2990 else 2991 { 2992 cts->protocol_version = SCSI_REV_2; 2993 cts->transport_version = 2; 2994 cts->transport = XPORT_SPI; 2995 spi = &cts->xport_specific.spi; 2996 spi->flags = CTS_SPI_FLAGS_DISC_ENB; 2997 spi->sync_period = 2; 2998 spi->sync_offset = 32; 2999 spi->bus_width = MSG_EXT_WDTR_BUS_16_BIT; 3000 spi->valid = CTS_SPI_VALID_DISC 3001 | CTS_SPI_VALID_SYNC_RATE 3002 | CTS_SPI_VALID_SYNC_OFFSET 3003 | CTS_SPI_VALID_BUS_WIDTH; 3004 } 3005 } 3006 #else 3007 { 3008 cts->flags = (CCB_TRANS_DISC_ENB | CCB_TRANS_TAG_ENB); 3009 cts->sync_period = 2; 3010 cts->sync_offset = 32; 3011 cts->bus_width = MSG_EXT_WDTR_BUS_16_BIT; 3012 cts->valid = CCB_TRANS_SYNC_RATE_VALID | 3013 CCB_TRANS_SYNC_OFFSET_VALID | 3014 CCB_TRANS_BUS_WIDTH_VALID | 3015 CCB_TRANS_DISC_VALID | 3016 CCB_TRANS_TQ_VALID; 3017 } 3018 #endif 3019 pccb->ccb_h.status |= CAM_REQ_CMP; 3020 xpt_done(pccb); 3021 break; 3022 } 3023 case XPT_SET_TRAN_SETTINGS: { 3024 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 3025 xpt_done(pccb); 3026 break; 3027 } 3028 case XPT_CALC_GEOMETRY: 3029 if(pccb->ccb_h.target_id == 16) { 3030 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 3031 xpt_done(pccb); 3032 break; 3033 } 3034 #if __FreeBSD_version >= 500000 3035 cam_calc_geometry(&pccb->ccg, 1); 3036 #else 3037 { 3038 struct ccb_calc_geometry *ccg; 3039 u_int32_t size_mb; 3040 u_int32_t secs_per_cylinder; 3041 3042 ccg = &pccb->ccg; 3043 if (ccg->block_size == 0) { 3044 pccb->ccb_h.status = CAM_REQ_INVALID; 3045 xpt_done(pccb); 3046 break; 3047 } 3048 if(((1024L * 1024L)/ccg->block_size) < 0) { 3049 pccb->ccb_h.status = CAM_REQ_INVALID; 3050 xpt_done(pccb); 3051 break; 3052 } 3053 size_mb = ccg->volume_size/((1024L * 1024L)/ccg->block_size); 3054 if(size_mb > 1024 ) { 3055 ccg->heads = 255; 3056 ccg->secs_per_track = 63; 3057 } else { 3058 ccg->heads = 64; 3059 ccg->secs_per_track = 32; 3060 } 3061 secs_per_cylinder = ccg->heads * ccg->secs_per_track; 3062 ccg->cylinders = ccg->volume_size / secs_per_cylinder; 3063 pccb->ccb_h.status |= CAM_REQ_CMP; 3064 } 3065 #endif 3066 xpt_done(pccb); 3067 break; 3068 default: 3069 pccb->ccb_h.status |= CAM_REQ_INVALID; 3070 xpt_done(pccb); 3071 break; 3072 } 3073 } 3074 /* 3075 ********************************************************************** 3076 ********************************************************************** 3077 */ 3078 static void arcmsr_start_hba_bgrb(struct AdapterControlBlock *acb) 3079 { 3080 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3081 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3082 if(!arcmsr_hba_wait_msgint_ready(acb)) { 3083 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3084 } 3085 } 3086 /* 3087 ********************************************************************** 3088 ********************************************************************** 3089 */ 3090 static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb) 3091 { 3092 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3093 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_START_BGRB); 3094 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3095 printf( "arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3096 } 3097 } 3098 /* 3099 ********************************************************************** 3100 ********************************************************************** 3101 */ 3102 static void arcmsr_start_hbc_bgrb(struct AdapterControlBlock *acb) 3103 { 3104 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3105 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3106 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3107 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 3108 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3109 } 3110 } 3111 /* 3112 ********************************************************************** 3113 ********************************************************************** 3114 */ 3115 static void arcmsr_start_hbd_bgrb(struct AdapterControlBlock *acb) 3116 { 3117 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3118 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3119 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 3120 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3121 } 3122 } 3123 /* 3124 ********************************************************************** 3125 ********************************************************************** 3126 */ 3127 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb) 3128 { 3129 switch (acb->adapter_type) { 3130 case ACB_ADAPTER_TYPE_A: 3131 arcmsr_start_hba_bgrb(acb); 3132 break; 3133 case ACB_ADAPTER_TYPE_B: 3134 arcmsr_start_hbb_bgrb(acb); 3135 break; 3136 case ACB_ADAPTER_TYPE_C: 3137 arcmsr_start_hbc_bgrb(acb); 3138 break; 3139 case ACB_ADAPTER_TYPE_D: 3140 arcmsr_start_hbd_bgrb(acb); 3141 break; 3142 } 3143 } 3144 /* 3145 ********************************************************************** 3146 ** 3147 ********************************************************************** 3148 */ 3149 static void arcmsr_polling_hba_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3150 { 3151 struct CommandControlBlock *srb; 3152 u_int32_t flag_srb, outbound_intstatus, poll_srb_done=0, poll_count=0; 3153 u_int16_t error; 3154 3155 polling_ccb_retry: 3156 poll_count++; 3157 outbound_intstatus=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 3158 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus); /*clear interrupt*/ 3159 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3160 while(1) { 3161 if((flag_srb = CHIP_REG_READ32(HBA_MessageUnit, 3162 0, outbound_queueport)) == 0xFFFFFFFF) { 3163 if(poll_srb_done) { 3164 break;/*chip FIFO no ccb for completion already*/ 3165 } else { 3166 UDELAY(25000); 3167 if ((poll_count > 100) && (poll_srb != NULL)) { 3168 break; 3169 } 3170 goto polling_ccb_retry; 3171 } 3172 } 3173 /* check if command done with no error*/ 3174 srb = (struct CommandControlBlock *) 3175 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 3176 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 3177 poll_srb_done = (srb == poll_srb) ? 1:0; 3178 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3179 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3180 printf("arcmsr%d: scsi id=%d lun=%d srb='%p'" 3181 "poll command abort successfully \n" 3182 , acb->pci_unit 3183 , srb->pccb->ccb_h.target_id 3184 , srb->pccb->ccb_h.target_lun, srb); 3185 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3186 arcmsr_srb_complete(srb, 1); 3187 continue; 3188 } 3189 printf("arcmsr%d: polling get an illegal srb command done srb='%p'" 3190 "srboutstandingcount=%d \n" 3191 , acb->pci_unit 3192 , srb, acb->srboutstandingcount); 3193 continue; 3194 } 3195 arcmsr_report_srb_state(acb, srb, error); 3196 } /*drain reply FIFO*/ 3197 } 3198 /* 3199 ********************************************************************** 3200 ** 3201 ********************************************************************** 3202 */ 3203 static void arcmsr_polling_hbb_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3204 { 3205 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3206 struct CommandControlBlock *srb; 3207 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3208 int index; 3209 u_int16_t error; 3210 3211 polling_ccb_retry: 3212 poll_count++; 3213 CHIP_REG_WRITE32(HBB_DOORBELL, 3214 0, iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */ 3215 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3216 while(1) { 3217 index = phbbmu->doneq_index; 3218 if((flag_srb = phbbmu->done_qbuffer[index]) == 0) { 3219 if(poll_srb_done) { 3220 break;/*chip FIFO no ccb for completion already*/ 3221 } else { 3222 UDELAY(25000); 3223 if ((poll_count > 100) && (poll_srb != NULL)) { 3224 break; 3225 } 3226 goto polling_ccb_retry; 3227 } 3228 } 3229 phbbmu->done_qbuffer[index] = 0; 3230 index++; 3231 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 3232 phbbmu->doneq_index = index; 3233 /* check if command done with no error*/ 3234 srb = (struct CommandControlBlock *) 3235 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 3236 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 3237 poll_srb_done = (srb == poll_srb) ? 1:0; 3238 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3239 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3240 printf("arcmsr%d: scsi id=%d lun=%d srb='%p'" 3241 "poll command abort successfully \n" 3242 , acb->pci_unit 3243 , srb->pccb->ccb_h.target_id 3244 , srb->pccb->ccb_h.target_lun, srb); 3245 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3246 arcmsr_srb_complete(srb, 1); 3247 continue; 3248 } 3249 printf("arcmsr%d: polling get an illegal srb command done srb='%p'" 3250 "srboutstandingcount=%d \n" 3251 , acb->pci_unit 3252 , srb, acb->srboutstandingcount); 3253 continue; 3254 } 3255 arcmsr_report_srb_state(acb, srb, error); 3256 } /*drain reply FIFO*/ 3257 } 3258 /* 3259 ********************************************************************** 3260 ** 3261 ********************************************************************** 3262 */ 3263 static void arcmsr_polling_hbc_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3264 { 3265 struct CommandControlBlock *srb; 3266 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3267 u_int16_t error; 3268 3269 polling_ccb_retry: 3270 poll_count++; 3271 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3272 while(1) { 3273 if(!(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)) { 3274 if(poll_srb_done) { 3275 break;/*chip FIFO no ccb for completion already*/ 3276 } else { 3277 UDELAY(25000); 3278 if ((poll_count > 100) && (poll_srb != NULL)) { 3279 break; 3280 } 3281 if (acb->srboutstandingcount == 0) { 3282 break; 3283 } 3284 goto polling_ccb_retry; 3285 } 3286 } 3287 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 3288 /* check if command done with no error*/ 3289 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/ 3290 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE; 3291 if (poll_srb != NULL) 3292 poll_srb_done = (srb == poll_srb) ? 1:0; 3293 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3294 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3295 printf("arcmsr%d: scsi id=%d lun=%d srb='%p'poll command abort successfully \n" 3296 , acb->pci_unit, srb->pccb->ccb_h.target_id, srb->pccb->ccb_h.target_lun, srb); 3297 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3298 arcmsr_srb_complete(srb, 1); 3299 continue; 3300 } 3301 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 3302 , acb->pci_unit, srb, acb->srboutstandingcount); 3303 continue; 3304 } 3305 arcmsr_report_srb_state(acb, srb, error); 3306 } /*drain reply FIFO*/ 3307 } 3308 /* 3309 ********************************************************************** 3310 ** 3311 ********************************************************************** 3312 */ 3313 static void arcmsr_polling_hbd_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3314 { 3315 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 3316 struct CommandControlBlock *srb; 3317 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3318 u_int32_t outbound_write_pointer; 3319 u_int16_t error, doneq_index; 3320 3321 polling_ccb_retry: 3322 poll_count++; 3323 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3324 while(1) { 3325 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 3326 doneq_index = phbdmu->doneq_index; 3327 if ((outbound_write_pointer & 0xFF) == (doneq_index & 0xFF)) { 3328 if(poll_srb_done) { 3329 break;/*chip FIFO no ccb for completion already*/ 3330 } else { 3331 UDELAY(25000); 3332 if ((poll_count > 100) && (poll_srb != NULL)) { 3333 break; 3334 } 3335 if (acb->srboutstandingcount == 0) { 3336 break; 3337 } 3338 goto polling_ccb_retry; 3339 } 3340 } 3341 doneq_index = arcmsr_get_doneq_index(phbdmu); 3342 flag_srb = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow; 3343 /* check if command done with no error*/ 3344 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/ 3345 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 3346 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index); 3347 if (poll_srb != NULL) 3348 poll_srb_done = (srb == poll_srb) ? 1:0; 3349 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3350 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3351 printf("arcmsr%d: scsi id=%d lun=%d srb='%p'poll command abort successfully \n" 3352 , acb->pci_unit, srb->pccb->ccb_h.target_id, srb->pccb->ccb_h.target_lun, srb); 3353 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3354 arcmsr_srb_complete(srb, 1); 3355 continue; 3356 } 3357 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 3358 , acb->pci_unit, srb, acb->srboutstandingcount); 3359 continue; 3360 } 3361 arcmsr_report_srb_state(acb, srb, error); 3362 } /*drain reply FIFO*/ 3363 } 3364 /* 3365 ********************************************************************** 3366 ********************************************************************** 3367 */ 3368 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3369 { 3370 switch (acb->adapter_type) { 3371 case ACB_ADAPTER_TYPE_A: { 3372 arcmsr_polling_hba_srbdone(acb, poll_srb); 3373 } 3374 break; 3375 case ACB_ADAPTER_TYPE_B: { 3376 arcmsr_polling_hbb_srbdone(acb, poll_srb); 3377 } 3378 break; 3379 case ACB_ADAPTER_TYPE_C: { 3380 arcmsr_polling_hbc_srbdone(acb, poll_srb); 3381 } 3382 break; 3383 case ACB_ADAPTER_TYPE_D: { 3384 arcmsr_polling_hbd_srbdone(acb, poll_srb); 3385 } 3386 break; 3387 } 3388 } 3389 /* 3390 ********************************************************************** 3391 ********************************************************************** 3392 */ 3393 static void arcmsr_get_hba_config(struct AdapterControlBlock *acb) 3394 { 3395 char *acb_firm_model = acb->firm_model; 3396 char *acb_firm_version = acb->firm_version; 3397 char *acb_device_map = acb->device_map; 3398 size_t iop_firm_model = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3399 size_t iop_firm_version = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3400 size_t iop_device_map = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3401 int i; 3402 3403 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3404 if(!arcmsr_hba_wait_msgint_ready(acb)) { 3405 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3406 } 3407 i = 0; 3408 while(i < 8) { 3409 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3410 /* 8 bytes firm_model, 15, 60-67*/ 3411 acb_firm_model++; 3412 i++; 3413 } 3414 i=0; 3415 while(i < 16) { 3416 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3417 /* 16 bytes firm_version, 17, 68-83*/ 3418 acb_firm_version++; 3419 i++; 3420 } 3421 i=0; 3422 while(i < 16) { 3423 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3424 acb_device_map++; 3425 i++; 3426 } 3427 printf("ARECA RAID ADAPTER%d: %s \n", acb->pci_unit, ARCMSR_DRIVER_VERSION); 3428 printf("ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n", acb->pci_unit, acb->firm_version); 3429 acb->firm_request_len = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3430 acb->firm_numbers_queue = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3431 acb->firm_sdram_size = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3432 acb->firm_ide_channels = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3433 acb->firm_cfg_version = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3434 } 3435 /* 3436 ********************************************************************** 3437 ********************************************************************** 3438 */ 3439 static void arcmsr_get_hbb_config(struct AdapterControlBlock *acb) 3440 { 3441 char *acb_firm_model = acb->firm_model; 3442 char *acb_firm_version = acb->firm_version; 3443 char *acb_device_map = acb->device_map; 3444 size_t iop_firm_model = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3445 size_t iop_firm_version = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3446 size_t iop_device_map = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3447 int i; 3448 3449 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG); 3450 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3451 printf( "arcmsr%d: wait" "'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3452 } 3453 i = 0; 3454 while(i < 8) { 3455 *acb_firm_model = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_model+i); 3456 /* 8 bytes firm_model, 15, 60-67*/ 3457 acb_firm_model++; 3458 i++; 3459 } 3460 i = 0; 3461 while(i < 16) { 3462 *acb_firm_version = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_version+i); 3463 /* 16 bytes firm_version, 17, 68-83*/ 3464 acb_firm_version++; 3465 i++; 3466 } 3467 i = 0; 3468 while(i < 16) { 3469 *acb_device_map = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_device_map+i); 3470 acb_device_map++; 3471 i++; 3472 } 3473 printf("ARECA RAID ADAPTER%d: %s \n", acb->pci_unit, ARCMSR_DRIVER_VERSION); 3474 printf("ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n", acb->pci_unit, acb->firm_version); 3475 acb->firm_request_len = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3476 acb->firm_numbers_queue = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3477 acb->firm_sdram_size = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3478 acb->firm_ide_channels = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3479 acb->firm_cfg_version = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3480 } 3481 /* 3482 ********************************************************************** 3483 ********************************************************************** 3484 */ 3485 static void arcmsr_get_hbc_config(struct AdapterControlBlock *acb) 3486 { 3487 char *acb_firm_model = acb->firm_model; 3488 char *acb_firm_version = acb->firm_version; 3489 char *acb_device_map = acb->device_map; 3490 size_t iop_firm_model = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3491 size_t iop_firm_version = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3492 size_t iop_device_map = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3493 int i; 3494 3495 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3496 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3497 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 3498 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3499 } 3500 i = 0; 3501 while(i < 8) { 3502 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3503 /* 8 bytes firm_model, 15, 60-67*/ 3504 acb_firm_model++; 3505 i++; 3506 } 3507 i = 0; 3508 while(i < 16) { 3509 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3510 /* 16 bytes firm_version, 17, 68-83*/ 3511 acb_firm_version++; 3512 i++; 3513 } 3514 i = 0; 3515 while(i < 16) { 3516 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3517 acb_device_map++; 3518 i++; 3519 } 3520 printf("ARECA RAID ADAPTER%d: %s \n", acb->pci_unit, ARCMSR_DRIVER_VERSION); 3521 printf("ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n", acb->pci_unit, acb->firm_version); 3522 acb->firm_request_len = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3523 acb->firm_numbers_queue = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3524 acb->firm_sdram_size = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3525 acb->firm_ide_channels = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3526 acb->firm_cfg_version = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3527 } 3528 /* 3529 ********************************************************************** 3530 ********************************************************************** 3531 */ 3532 static void arcmsr_get_hbd_config(struct AdapterControlBlock *acb) 3533 { 3534 char *acb_firm_model = acb->firm_model; 3535 char *acb_firm_version = acb->firm_version; 3536 char *acb_device_map = acb->device_map; 3537 size_t iop_firm_model = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3538 size_t iop_firm_version = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3539 size_t iop_device_map = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3540 int i; 3541 3542 if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) 3543 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR); 3544 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3545 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 3546 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3547 } 3548 i = 0; 3549 while(i < 8) { 3550 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3551 /* 8 bytes firm_model, 15, 60-67*/ 3552 acb_firm_model++; 3553 i++; 3554 } 3555 i = 0; 3556 while(i < 16) { 3557 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3558 /* 16 bytes firm_version, 17, 68-83*/ 3559 acb_firm_version++; 3560 i++; 3561 } 3562 i = 0; 3563 while(i < 16) { 3564 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3565 acb_device_map++; 3566 i++; 3567 } 3568 printf("ARECA RAID ADAPTER%d: %s \n", acb->pci_unit, ARCMSR_DRIVER_VERSION); 3569 printf("ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n", acb->pci_unit, acb->firm_version); 3570 acb->firm_request_len = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_request_len, 1, 04-07*/ 3571 acb->firm_numbers_queue = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_numbers_queue, 2, 08-11*/ 3572 acb->firm_sdram_size = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_sdram_size, 3, 12-15*/ 3573 acb->firm_ide_channels = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[5]); /*firm_ide_channels, 4, 16-19*/ 3574 acb->firm_cfg_version = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3575 } 3576 /* 3577 ********************************************************************** 3578 ********************************************************************** 3579 */ 3580 static void arcmsr_get_firmware_spec(struct AdapterControlBlock *acb) 3581 { 3582 switch (acb->adapter_type) { 3583 case ACB_ADAPTER_TYPE_A: { 3584 arcmsr_get_hba_config(acb); 3585 } 3586 break; 3587 case ACB_ADAPTER_TYPE_B: { 3588 arcmsr_get_hbb_config(acb); 3589 } 3590 break; 3591 case ACB_ADAPTER_TYPE_C: { 3592 arcmsr_get_hbc_config(acb); 3593 } 3594 break; 3595 case ACB_ADAPTER_TYPE_D: { 3596 arcmsr_get_hbd_config(acb); 3597 } 3598 break; 3599 } 3600 } 3601 /* 3602 ********************************************************************** 3603 ********************************************************************** 3604 */ 3605 static void arcmsr_wait_firmware_ready( struct AdapterControlBlock *acb) 3606 { 3607 int timeout=0; 3608 3609 switch (acb->adapter_type) { 3610 case ACB_ADAPTER_TYPE_A: { 3611 while ((CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0) 3612 { 3613 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 3614 { 3615 printf( "arcmsr%d:timed out waiting for firmware \n", acb->pci_unit); 3616 return; 3617 } 3618 UDELAY(15000); /* wait 15 milli-seconds */ 3619 } 3620 } 3621 break; 3622 case ACB_ADAPTER_TYPE_B: { 3623 while ((CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & ARCMSR_MESSAGE_FIRMWARE_OK) == 0) 3624 { 3625 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 3626 { 3627 printf( "arcmsr%d: timed out waiting for firmware \n", acb->pci_unit); 3628 return; 3629 } 3630 UDELAY(15000); /* wait 15 milli-seconds */ 3631 } 3632 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 3633 } 3634 break; 3635 case ACB_ADAPTER_TYPE_C: { 3636 while ((CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0) 3637 { 3638 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 3639 { 3640 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 3641 return; 3642 } 3643 UDELAY(15000); /* wait 15 milli-seconds */ 3644 } 3645 } 3646 break; 3647 case ACB_ADAPTER_TYPE_D: { 3648 while ((CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK) == 0) 3649 { 3650 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 3651 { 3652 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 3653 return; 3654 } 3655 UDELAY(15000); /* wait 15 milli-seconds */ 3656 } 3657 } 3658 break; 3659 } 3660 } 3661 /* 3662 ********************************************************************** 3663 ********************************************************************** 3664 */ 3665 static void arcmsr_clear_doorbell_queue_buffer( struct AdapterControlBlock *acb) 3666 { 3667 u_int32_t outbound_doorbell; 3668 3669 switch (acb->adapter_type) { 3670 case ACB_ADAPTER_TYPE_A: { 3671 /* empty doorbell Qbuffer if door bell ringed */ 3672 outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell); 3673 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */ 3674 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK); 3675 3676 } 3677 break; 3678 case ACB_ADAPTER_TYPE_B: { 3679 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt and message state*/ 3680 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK); 3681 /* let IOP know data has been read */ 3682 } 3683 break; 3684 case ACB_ADAPTER_TYPE_C: { 3685 /* empty doorbell Qbuffer if door bell ringed */ 3686 outbound_doorbell = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell); 3687 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell); /*clear doorbell interrupt */ 3688 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK); 3689 CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell_clear); /* Dummy read to force pci flush */ 3690 CHIP_REG_READ32(HBC_MessageUnit, 0, inbound_doorbell); /* Dummy read to force pci flush */ 3691 } 3692 break; 3693 case ACB_ADAPTER_TYPE_D: { 3694 /* empty doorbell Qbuffer if door bell ringed */ 3695 outbound_doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell); 3696 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */ 3697 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ); 3698 3699 } 3700 break; 3701 } 3702 } 3703 /* 3704 ************************************************************************ 3705 ************************************************************************ 3706 */ 3707 static u_int32_t arcmsr_iop_confirm(struct AdapterControlBlock *acb) 3708 { 3709 unsigned long srb_phyaddr; 3710 u_int32_t srb_phyaddr_hi32; 3711 u_int32_t srb_phyaddr_lo32; 3712 3713 /* 3714 ******************************************************************** 3715 ** here we need to tell iop 331 our freesrb.HighPart 3716 ** if freesrb.HighPart is not zero 3717 ******************************************************************** 3718 */ 3719 srb_phyaddr = (unsigned long) acb->srb_phyaddr.phyaddr; 3720 srb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high; 3721 srb_phyaddr_lo32 = acb->srb_phyaddr.B.phyadd_low; 3722 switch (acb->adapter_type) { 3723 case ACB_ADAPTER_TYPE_A: { 3724 if(srb_phyaddr_hi32 != 0) { 3725 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 3726 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 3727 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 3728 if(!arcmsr_hba_wait_msgint_ready(acb)) { 3729 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 3730 return FALSE; 3731 } 3732 } 3733 } 3734 break; 3735 /* 3736 *********************************************************************** 3737 ** if adapter type B, set window of "post command Q" 3738 *********************************************************************** 3739 */ 3740 case ACB_ADAPTER_TYPE_B: { 3741 u_int32_t post_queue_phyaddr; 3742 struct HBB_MessageUnit *phbbmu; 3743 3744 phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3745 phbbmu->postq_index = 0; 3746 phbbmu->doneq_index = 0; 3747 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_SET_POST_WINDOW); 3748 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3749 printf( "arcmsr%d: 'set window of post command Q' timeout\n", acb->pci_unit); 3750 return FALSE; 3751 } 3752 post_queue_phyaddr = srb_phyaddr + ARCMSR_SRBS_POOL_SIZE 3753 + offsetof(struct HBB_MessageUnit, post_qbuffer); 3754 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */ 3755 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1], srb_phyaddr_hi32); /* normal should be zero */ 3756 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ size (256+8)*4 */ 3757 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3], post_queue_phyaddr+1056); /* doneQ size (256+8)*4 */ 3758 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4], 1056); /* srb maxQ size must be --> [(256+8)*4] */ 3759 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_SET_CONFIG); 3760 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3761 printf( "arcmsr%d: 'set command Q window' timeout \n", acb->pci_unit); 3762 return FALSE; 3763 } 3764 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_START_DRIVER_MODE); 3765 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3766 printf( "arcmsr%d: 'start diver mode' timeout \n", acb->pci_unit); 3767 return FALSE; 3768 } 3769 } 3770 break; 3771 case ACB_ADAPTER_TYPE_C: { 3772 if(srb_phyaddr_hi32 != 0) { 3773 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 3774 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 3775 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 3776 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3777 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 3778 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 3779 return FALSE; 3780 } 3781 } 3782 } 3783 break; 3784 case ACB_ADAPTER_TYPE_D: { 3785 u_int32_t post_queue_phyaddr, done_queue_phyaddr; 3786 struct HBD_MessageUnit0 *phbdmu; 3787 3788 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 3789 phbdmu->postq_index = 0; 3790 phbdmu->doneq_index = 0x40FF; 3791 post_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE 3792 + offsetof(struct HBD_MessageUnit0, post_qbuffer); 3793 done_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE 3794 + offsetof(struct HBD_MessageUnit0, done_qbuffer); 3795 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */ 3796 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 3797 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ base */ 3798 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[3], done_queue_phyaddr); /* doneQ base */ 3799 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[4], 0x100); 3800 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 3801 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 3802 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 3803 return FALSE; 3804 } 3805 } 3806 break; 3807 } 3808 return (TRUE); 3809 } 3810 /* 3811 ************************************************************************ 3812 ************************************************************************ 3813 */ 3814 static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb) 3815 { 3816 switch (acb->adapter_type) 3817 { 3818 case ACB_ADAPTER_TYPE_A: 3819 case ACB_ADAPTER_TYPE_C: 3820 case ACB_ADAPTER_TYPE_D: 3821 break; 3822 case ACB_ADAPTER_TYPE_B: { 3823 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell,ARCMSR_MESSAGE_ACTIVE_EOI_MODE); 3824 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3825 printf( "arcmsr%d: 'iop enable eoi mode' timeout \n", acb->pci_unit); 3826 return; 3827 } 3828 } 3829 break; 3830 } 3831 } 3832 /* 3833 ********************************************************************** 3834 ********************************************************************** 3835 */ 3836 static void arcmsr_iop_init(struct AdapterControlBlock *acb) 3837 { 3838 u_int32_t intmask_org; 3839 3840 /* disable all outbound interrupt */ 3841 intmask_org = arcmsr_disable_allintr(acb); 3842 arcmsr_wait_firmware_ready(acb); 3843 arcmsr_iop_confirm(acb); 3844 arcmsr_get_firmware_spec(acb); 3845 /*start background rebuild*/ 3846 arcmsr_start_adapter_bgrb(acb); 3847 /* empty doorbell Qbuffer if door bell ringed */ 3848 arcmsr_clear_doorbell_queue_buffer(acb); 3849 arcmsr_enable_eoi_mode(acb); 3850 /* enable outbound Post Queue, outbound doorbell Interrupt */ 3851 arcmsr_enable_allintr(acb, intmask_org); 3852 acb->acb_flags |= ACB_F_IOP_INITED; 3853 } 3854 /* 3855 ********************************************************************** 3856 ********************************************************************** 3857 */ 3858 static void arcmsr_map_free_srb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3859 { 3860 struct AdapterControlBlock *acb = arg; 3861 struct CommandControlBlock *srb_tmp; 3862 u_int32_t i; 3863 unsigned long srb_phyaddr = (unsigned long)segs->ds_addr; 3864 3865 acb->srb_phyaddr.phyaddr = srb_phyaddr; 3866 srb_tmp = (struct CommandControlBlock *)acb->uncacheptr; 3867 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 3868 if(bus_dmamap_create(acb->dm_segs_dmat, 3869 /*flags*/0, &srb_tmp->dm_segs_dmamap) != 0) { 3870 acb->acb_flags |= ACB_F_MAPFREESRB_FAILD; 3871 printf("arcmsr%d:" 3872 " srb dmamap bus_dmamap_create error\n", acb->pci_unit); 3873 return; 3874 } 3875 if((acb->adapter_type == ACB_ADAPTER_TYPE_C) || (acb->adapter_type == ACB_ADAPTER_TYPE_D)) 3876 { 3877 srb_tmp->cdb_phyaddr_low = srb_phyaddr; 3878 srb_tmp->cdb_phyaddr_high = (u_int32_t)((srb_phyaddr >> 16) >> 16); 3879 } 3880 else 3881 srb_tmp->cdb_phyaddr_low = srb_phyaddr >> 5; 3882 srb_tmp->acb = acb; 3883 acb->srbworkingQ[i] = acb->psrb_pool[i] = srb_tmp; 3884 srb_phyaddr = srb_phyaddr + SRB_SIZE; 3885 srb_tmp = (struct CommandControlBlock *)((unsigned long)srb_tmp + SRB_SIZE); 3886 } 3887 acb->vir2phy_offset = (unsigned long)srb_tmp - (unsigned long)srb_phyaddr; 3888 } 3889 /* 3890 ************************************************************************ 3891 ************************************************************************ 3892 */ 3893 static void arcmsr_free_resource(struct AdapterControlBlock *acb) 3894 { 3895 /* remove the control device */ 3896 if(acb->ioctl_dev != NULL) { 3897 destroy_dev(acb->ioctl_dev); 3898 } 3899 bus_dmamap_unload(acb->srb_dmat, acb->srb_dmamap); 3900 bus_dmamap_destroy(acb->srb_dmat, acb->srb_dmamap); 3901 bus_dma_tag_destroy(acb->srb_dmat); 3902 bus_dma_tag_destroy(acb->dm_segs_dmat); 3903 bus_dma_tag_destroy(acb->parent_dmat); 3904 } 3905 /* 3906 ************************************************************************ 3907 ************************************************************************ 3908 */ 3909 static void arcmsr_mutex_init(struct AdapterControlBlock *acb) 3910 { 3911 ARCMSR_LOCK_INIT(&acb->isr_lock, "arcmsr isr lock"); 3912 ARCMSR_LOCK_INIT(&acb->srb_lock, "arcmsr srb lock"); 3913 ARCMSR_LOCK_INIT(&acb->postDone_lock, "arcmsr postQ lock"); 3914 ARCMSR_LOCK_INIT(&acb->qbuffer_lock, "arcmsr RW buffer lock"); 3915 } 3916 /* 3917 ************************************************************************ 3918 ************************************************************************ 3919 */ 3920 static void arcmsr_mutex_destroy(struct AdapterControlBlock *acb) 3921 { 3922 ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock); 3923 ARCMSR_LOCK_DESTROY(&acb->postDone_lock); 3924 ARCMSR_LOCK_DESTROY(&acb->srb_lock); 3925 ARCMSR_LOCK_DESTROY(&acb->isr_lock); 3926 } 3927 /* 3928 ************************************************************************ 3929 ************************************************************************ 3930 */ 3931 static u_int32_t arcmsr_initialize(device_t dev) 3932 { 3933 struct AdapterControlBlock *acb = device_get_softc(dev); 3934 u_int16_t pci_command; 3935 int i, j,max_coherent_size; 3936 u_int32_t vendor_dev_id; 3937 3938 vendor_dev_id = pci_get_devid(dev); 3939 acb->vendor_device_id = vendor_dev_id; 3940 switch (vendor_dev_id) { 3941 case PCIDevVenIDARC1880: 3942 case PCIDevVenIDARC1882: 3943 case PCIDevVenIDARC1213: 3944 case PCIDevVenIDARC1223: { 3945 acb->adapter_type = ACB_ADAPTER_TYPE_C; 3946 acb->adapter_bus_speed = ACB_BUS_SPEED_6G; 3947 max_coherent_size = ARCMSR_SRBS_POOL_SIZE; 3948 } 3949 break; 3950 case PCIDevVenIDARC1214: { 3951 acb->adapter_type = ACB_ADAPTER_TYPE_D; 3952 acb->adapter_bus_speed = ACB_BUS_SPEED_6G; 3953 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBD_MessageUnit0)); 3954 } 3955 break; 3956 case PCIDevVenIDARC1200: 3957 case PCIDevVenIDARC1201: { 3958 acb->adapter_type = ACB_ADAPTER_TYPE_B; 3959 acb->adapter_bus_speed = ACB_BUS_SPEED_3G; 3960 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit)); 3961 } 3962 break; 3963 case PCIDevVenIDARC1110: 3964 case PCIDevVenIDARC1120: 3965 case PCIDevVenIDARC1130: 3966 case PCIDevVenIDARC1160: 3967 case PCIDevVenIDARC1170: 3968 case PCIDevVenIDARC1210: 3969 case PCIDevVenIDARC1220: 3970 case PCIDevVenIDARC1230: 3971 case PCIDevVenIDARC1231: 3972 case PCIDevVenIDARC1260: 3973 case PCIDevVenIDARC1261: 3974 case PCIDevVenIDARC1270: 3975 case PCIDevVenIDARC1280: 3976 case PCIDevVenIDARC1212: 3977 case PCIDevVenIDARC1222: 3978 case PCIDevVenIDARC1380: 3979 case PCIDevVenIDARC1381: 3980 case PCIDevVenIDARC1680: 3981 case PCIDevVenIDARC1681: { 3982 acb->adapter_type = ACB_ADAPTER_TYPE_A; 3983 acb->adapter_bus_speed = ACB_BUS_SPEED_3G; 3984 max_coherent_size = ARCMSR_SRBS_POOL_SIZE; 3985 } 3986 break; 3987 default: { 3988 printf("arcmsr%d:" 3989 " unknown RAID adapter type \n", device_get_unit(dev)); 3990 return ENOMEM; 3991 } 3992 } 3993 #if __FreeBSD_version >= 700000 3994 if(bus_dma_tag_create( /*PCI parent*/ bus_get_dma_tag(dev), 3995 #else 3996 if(bus_dma_tag_create( /*PCI parent*/ NULL, 3997 #endif 3998 /*alignemnt*/ 1, 3999 /*boundary*/ 0, 4000 /*lowaddr*/ BUS_SPACE_MAXADDR, 4001 /*highaddr*/ BUS_SPACE_MAXADDR, 4002 /*filter*/ NULL, 4003 /*filterarg*/ NULL, 4004 /*maxsize*/ BUS_SPACE_MAXSIZE_32BIT, 4005 /*nsegments*/ BUS_SPACE_UNRESTRICTED, 4006 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4007 /*flags*/ 0, 4008 #if __FreeBSD_version >= 501102 4009 /*lockfunc*/ NULL, 4010 /*lockarg*/ NULL, 4011 #endif 4012 &acb->parent_dmat) != 0) 4013 { 4014 printf("arcmsr%d: parent_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4015 return ENOMEM; 4016 } 4017 4018 /* Create a single tag describing a region large enough to hold all of the s/g lists we will need. */ 4019 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat, 4020 /*alignment*/ 1, 4021 /*boundary*/ 0, 4022 #ifdef PAE 4023 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 4024 #else 4025 /*lowaddr*/ BUS_SPACE_MAXADDR, 4026 #endif 4027 /*highaddr*/ BUS_SPACE_MAXADDR, 4028 /*filter*/ NULL, 4029 /*filterarg*/ NULL, 4030 /*maxsize*/ ARCMSR_MAX_SG_ENTRIES * PAGE_SIZE * ARCMSR_MAX_FREESRB_NUM, 4031 /*nsegments*/ ARCMSR_MAX_SG_ENTRIES, 4032 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4033 /*flags*/ 0, 4034 #if __FreeBSD_version >= 501102 4035 /*lockfunc*/ busdma_lock_mutex, 4036 /*lockarg*/ &acb->isr_lock, 4037 #endif 4038 &acb->dm_segs_dmat) != 0) 4039 { 4040 bus_dma_tag_destroy(acb->parent_dmat); 4041 printf("arcmsr%d: dm_segs_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4042 return ENOMEM; 4043 } 4044 4045 /* DMA tag for our srb structures.... Allocate the freesrb memory */ 4046 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat, 4047 /*alignment*/ 0x20, 4048 /*boundary*/ 0, 4049 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 4050 /*highaddr*/ BUS_SPACE_MAXADDR, 4051 /*filter*/ NULL, 4052 /*filterarg*/ NULL, 4053 /*maxsize*/ max_coherent_size, 4054 /*nsegments*/ 1, 4055 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4056 /*flags*/ 0, 4057 #if __FreeBSD_version >= 501102 4058 /*lockfunc*/ NULL, 4059 /*lockarg*/ NULL, 4060 #endif 4061 &acb->srb_dmat) != 0) 4062 { 4063 bus_dma_tag_destroy(acb->dm_segs_dmat); 4064 bus_dma_tag_destroy(acb->parent_dmat); 4065 printf("arcmsr%d: srb_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4066 return ENXIO; 4067 } 4068 /* Allocation for our srbs */ 4069 if(bus_dmamem_alloc(acb->srb_dmat, (void **)&acb->uncacheptr, BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, &acb->srb_dmamap) != 0) { 4070 bus_dma_tag_destroy(acb->srb_dmat); 4071 bus_dma_tag_destroy(acb->dm_segs_dmat); 4072 bus_dma_tag_destroy(acb->parent_dmat); 4073 printf("arcmsr%d: srb_dmat bus_dmamem_alloc failure!\n", device_get_unit(dev)); 4074 return ENXIO; 4075 } 4076 /* And permanently map them */ 4077 if(bus_dmamap_load(acb->srb_dmat, acb->srb_dmamap, acb->uncacheptr, max_coherent_size, arcmsr_map_free_srb, acb, /*flags*/0)) { 4078 bus_dma_tag_destroy(acb->srb_dmat); 4079 bus_dma_tag_destroy(acb->dm_segs_dmat); 4080 bus_dma_tag_destroy(acb->parent_dmat); 4081 printf("arcmsr%d: srb_dmat bus_dmamap_load failure!\n", device_get_unit(dev)); 4082 return ENXIO; 4083 } 4084 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 4085 pci_command |= PCIM_CMD_BUSMASTEREN; 4086 pci_command |= PCIM_CMD_PERRESPEN; 4087 pci_command |= PCIM_CMD_MWRICEN; 4088 /* Enable Busmaster/Mem */ 4089 pci_command |= PCIM_CMD_MEMEN; 4090 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 4091 switch(acb->adapter_type) { 4092 case ACB_ADAPTER_TYPE_A: { 4093 u_int32_t rid0 = PCIR_BAR(0); 4094 vm_offset_t mem_base0; 4095 4096 acb->sys_res_arcmsr[0] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, 0x1000, RF_ACTIVE); 4097 if(acb->sys_res_arcmsr[0] == NULL) { 4098 arcmsr_free_resource(acb); 4099 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4100 return ENOMEM; 4101 } 4102 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4103 arcmsr_free_resource(acb); 4104 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4105 return ENXIO; 4106 } 4107 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4108 if(mem_base0 == 0) { 4109 arcmsr_free_resource(acb); 4110 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4111 return ENXIO; 4112 } 4113 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4114 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4115 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4116 } 4117 break; 4118 case ACB_ADAPTER_TYPE_B: { 4119 struct HBB_MessageUnit *phbbmu; 4120 struct CommandControlBlock *freesrb; 4121 u_int32_t rid[]={ PCIR_BAR(0), PCIR_BAR(2) }; 4122 vm_offset_t mem_base[]={0,0}; 4123 for(i=0; i < 2; i++) { 4124 if(i == 0) { 4125 acb->sys_res_arcmsr[i] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid[i], 4126 0ul, ~0ul, sizeof(struct HBB_DOORBELL), RF_ACTIVE); 4127 } else { 4128 acb->sys_res_arcmsr[i] = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid[i], 4129 0ul, ~0ul, sizeof(struct HBB_RWBUFFER), RF_ACTIVE); 4130 } 4131 if(acb->sys_res_arcmsr[i] == NULL) { 4132 arcmsr_free_resource(acb); 4133 printf("arcmsr%d: bus_alloc_resource %d failure!\n", device_get_unit(dev), i); 4134 return ENOMEM; 4135 } 4136 if(rman_get_start(acb->sys_res_arcmsr[i]) <= 0) { 4137 arcmsr_free_resource(acb); 4138 printf("arcmsr%d: rman_get_start %d failure!\n", device_get_unit(dev), i); 4139 return ENXIO; 4140 } 4141 mem_base[i] = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[i]); 4142 if(mem_base[i] == 0) { 4143 arcmsr_free_resource(acb); 4144 printf("arcmsr%d: rman_get_virtual %d failure!\n", device_get_unit(dev), i); 4145 return ENXIO; 4146 } 4147 acb->btag[i] = rman_get_bustag(acb->sys_res_arcmsr[i]); 4148 acb->bhandle[i] = rman_get_bushandle(acb->sys_res_arcmsr[i]); 4149 } 4150 freesrb = (struct CommandControlBlock *)acb->uncacheptr; 4151 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)freesrb+ARCMSR_SRBS_POOL_SIZE); 4152 phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4153 phbbmu->hbb_doorbell = (struct HBB_DOORBELL *)mem_base[0]; 4154 phbbmu->hbb_rwbuffer = (struct HBB_RWBUFFER *)mem_base[1]; 4155 } 4156 break; 4157 case ACB_ADAPTER_TYPE_C: { 4158 u_int32_t rid0 = PCIR_BAR(1); 4159 vm_offset_t mem_base0; 4160 4161 acb->sys_res_arcmsr[0] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, sizeof(struct HBC_MessageUnit), RF_ACTIVE); 4162 if(acb->sys_res_arcmsr[0] == NULL) { 4163 arcmsr_free_resource(acb); 4164 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4165 return ENOMEM; 4166 } 4167 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4168 arcmsr_free_resource(acb); 4169 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4170 return ENXIO; 4171 } 4172 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4173 if(mem_base0 == 0) { 4174 arcmsr_free_resource(acb); 4175 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4176 return ENXIO; 4177 } 4178 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4179 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4180 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4181 } 4182 break; 4183 case ACB_ADAPTER_TYPE_D: { 4184 struct HBD_MessageUnit0 *phbdmu; 4185 u_int32_t rid0 = PCIR_BAR(0); 4186 vm_offset_t mem_base0; 4187 4188 acb->sys_res_arcmsr[0] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, sizeof(struct HBD_MessageUnit), RF_ACTIVE); 4189 if(acb->sys_res_arcmsr[0] == NULL) { 4190 arcmsr_free_resource(acb); 4191 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4192 return ENOMEM; 4193 } 4194 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4195 arcmsr_free_resource(acb); 4196 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4197 return ENXIO; 4198 } 4199 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4200 if(mem_base0 == 0) { 4201 arcmsr_free_resource(acb); 4202 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4203 return ENXIO; 4204 } 4205 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4206 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4207 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)acb->uncacheptr+ARCMSR_SRBS_POOL_SIZE); 4208 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 4209 phbdmu->phbdmu = (struct HBD_MessageUnit *)mem_base0; 4210 } 4211 break; 4212 } 4213 if(acb->acb_flags & ACB_F_MAPFREESRB_FAILD) { 4214 arcmsr_free_resource(acb); 4215 printf("arcmsr%d: map free srb failure!\n", device_get_unit(dev)); 4216 return ENXIO; 4217 } 4218 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_RQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ); 4219 acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER; 4220 /* 4221 ******************************************************************** 4222 ** init raid volume state 4223 ******************************************************************** 4224 */ 4225 for(i=0; i < ARCMSR_MAX_TARGETID; i++) { 4226 for(j=0; j < ARCMSR_MAX_TARGETLUN; j++) { 4227 acb->devstate[i][j] = ARECA_RAID_GONE; 4228 } 4229 } 4230 arcmsr_iop_init(acb); 4231 return(0); 4232 } 4233 /* 4234 ************************************************************************ 4235 ************************************************************************ 4236 */ 4237 static int arcmsr_attach(device_t dev) 4238 { 4239 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 4240 u_int32_t unit=device_get_unit(dev); 4241 struct ccb_setasync csa; 4242 struct cam_devq *devq; /* Device Queue to use for this SIM */ 4243 struct resource *irqres; 4244 int rid; 4245 4246 if(acb == NULL) { 4247 printf("arcmsr%d: cannot allocate softc\n", unit); 4248 return (ENOMEM); 4249 } 4250 arcmsr_mutex_init(acb); 4251 if(arcmsr_initialize(dev)) { 4252 printf("arcmsr%d: initialize failure!\n", unit); 4253 arcmsr_mutex_destroy(acb); 4254 return ENXIO; 4255 } 4256 /* After setting up the adapter, map our interrupt */ 4257 rid = 0; 4258 irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1, RF_SHAREABLE | RF_ACTIVE); 4259 if(irqres == NULL || 4260 #if __FreeBSD_version >= 700025 4261 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, NULL, arcmsr_intr_handler, acb, &acb->ih)) { 4262 #else 4263 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, arcmsr_intr_handler, acb, &acb->ih)) { 4264 #endif 4265 arcmsr_free_resource(acb); 4266 arcmsr_mutex_destroy(acb); 4267 printf("arcmsr%d: unable to register interrupt handler!\n", unit); 4268 return ENXIO; 4269 } 4270 acb->irqres = irqres; 4271 acb->pci_dev = dev; 4272 acb->pci_unit = unit; 4273 /* 4274 * Now let the CAM generic SCSI layer find the SCSI devices on 4275 * the bus * start queue to reset to the idle loop. * 4276 * Create device queue of SIM(s) * (MAX_START_JOB - 1) : 4277 * max_sim_transactions 4278 */ 4279 devq = cam_simq_alloc(ARCMSR_MAX_START_JOB); 4280 if(devq == NULL) { 4281 arcmsr_free_resource(acb); 4282 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres); 4283 arcmsr_mutex_destroy(acb); 4284 printf("arcmsr%d: cam_simq_alloc failure!\n", unit); 4285 return ENXIO; 4286 } 4287 #if __FreeBSD_version >= 700025 4288 acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, &acb->isr_lock, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq); 4289 #else 4290 acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq); 4291 #endif 4292 if(acb->psim == NULL) { 4293 arcmsr_free_resource(acb); 4294 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres); 4295 cam_simq_free(devq); 4296 arcmsr_mutex_destroy(acb); 4297 printf("arcmsr%d: cam_sim_alloc failure!\n", unit); 4298 return ENXIO; 4299 } 4300 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 4301 #if __FreeBSD_version >= 700044 4302 if(xpt_bus_register(acb->psim, dev, 0) != CAM_SUCCESS) { 4303 #else 4304 if(xpt_bus_register(acb->psim, 0) != CAM_SUCCESS) { 4305 #endif 4306 arcmsr_free_resource(acb); 4307 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres); 4308 cam_sim_free(acb->psim, /*free_devq*/TRUE); 4309 arcmsr_mutex_destroy(acb); 4310 printf("arcmsr%d: xpt_bus_register failure!\n", unit); 4311 return ENXIO; 4312 } 4313 if(xpt_create_path(&acb->ppath, /* periph */ NULL, cam_sim_path(acb->psim), CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 4314 arcmsr_free_resource(acb); 4315 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres); 4316 xpt_bus_deregister(cam_sim_path(acb->psim)); 4317 cam_sim_free(acb->psim, /* free_simq */ TRUE); 4318 arcmsr_mutex_destroy(acb); 4319 printf("arcmsr%d: xpt_create_path failure!\n", unit); 4320 return ENXIO; 4321 } 4322 /* 4323 **************************************************** 4324 */ 4325 xpt_setup_ccb(&csa.ccb_h, acb->ppath, /*priority*/5); 4326 csa.ccb_h.func_code = XPT_SASYNC_CB; 4327 csa.event_enable = AC_FOUND_DEVICE|AC_LOST_DEVICE; 4328 csa.callback = arcmsr_async; 4329 csa.callback_arg = acb->psim; 4330 xpt_action((union ccb *)&csa); 4331 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 4332 /* Create the control device. */ 4333 acb->ioctl_dev = make_dev(&arcmsr_cdevsw, unit, UID_ROOT, GID_WHEEL /* GID_OPERATOR */, S_IRUSR | S_IWUSR, "arcmsr%d", unit); 4334 4335 #if __FreeBSD_version < 503000 4336 acb->ioctl_dev->si_drv1 = acb; 4337 #endif 4338 #if __FreeBSD_version > 500005 4339 (void)make_dev_alias(acb->ioctl_dev, "arc%d", unit); 4340 #endif 4341 arcmsr_callout_init(&acb->devmap_callout); 4342 callout_reset(&acb->devmap_callout, 60 * hz, arcmsr_polling_devmap, acb); 4343 return (0); 4344 } 4345 4346 /* 4347 ************************************************************************ 4348 ************************************************************************ 4349 */ 4350 static int arcmsr_probe(device_t dev) 4351 { 4352 u_int32_t id; 4353 static char buf[256]; 4354 char x_type[]={"X-TYPE"}; 4355 char *type; 4356 int raid6 = 1; 4357 4358 if (pci_get_vendor(dev) != PCI_VENDOR_ID_ARECA) { 4359 return (ENXIO); 4360 } 4361 switch(id = pci_get_devid(dev)) { 4362 case PCIDevVenIDARC1110: 4363 case PCIDevVenIDARC1200: 4364 case PCIDevVenIDARC1201: 4365 case PCIDevVenIDARC1210: 4366 raid6 = 0; 4367 /*FALLTHRU*/ 4368 case PCIDevVenIDARC1120: 4369 case PCIDevVenIDARC1130: 4370 case PCIDevVenIDARC1160: 4371 case PCIDevVenIDARC1170: 4372 case PCIDevVenIDARC1220: 4373 case PCIDevVenIDARC1230: 4374 case PCIDevVenIDARC1231: 4375 case PCIDevVenIDARC1260: 4376 case PCIDevVenIDARC1261: 4377 case PCIDevVenIDARC1270: 4378 case PCIDevVenIDARC1280: 4379 type = "SATA 3G"; 4380 break; 4381 case PCIDevVenIDARC1212: 4382 case PCIDevVenIDARC1222: 4383 case PCIDevVenIDARC1380: 4384 case PCIDevVenIDARC1381: 4385 case PCIDevVenIDARC1680: 4386 case PCIDevVenIDARC1681: 4387 type = "SAS 3G"; 4388 break; 4389 case PCIDevVenIDARC1880: 4390 case PCIDevVenIDARC1882: 4391 case PCIDevVenIDARC1213: 4392 case PCIDevVenIDARC1223: 4393 type = "SAS 6G"; 4394 break; 4395 case PCIDevVenIDARC1214: 4396 type = "SATA 6G"; 4397 break; 4398 default: 4399 type = x_type; 4400 break; 4401 } 4402 if(type == x_type) 4403 return(ENXIO); 4404 sprintf(buf, "Areca %s Host Adapter RAID Controller %s\n", type, raid6 ? "(RAID6 capable)" : ""); 4405 device_set_desc_copy(dev, buf); 4406 return (BUS_PROBE_DEFAULT); 4407 } 4408 /* 4409 ************************************************************************ 4410 ************************************************************************ 4411 */ 4412 static int arcmsr_shutdown(device_t dev) 4413 { 4414 u_int32_t i; 4415 u_int32_t intmask_org; 4416 struct CommandControlBlock *srb; 4417 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 4418 4419 /* stop adapter background rebuild */ 4420 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 4421 /* disable all outbound interrupt */ 4422 intmask_org = arcmsr_disable_allintr(acb); 4423 arcmsr_stop_adapter_bgrb(acb); 4424 arcmsr_flush_adapter_cache(acb); 4425 /* abort all outstanding command */ 4426 acb->acb_flags |= ACB_F_SCSISTOPADAPTER; 4427 acb->acb_flags &= ~ACB_F_IOP_INITED; 4428 if(acb->srboutstandingcount != 0) { 4429 /*clear and abort all outbound posted Q*/ 4430 arcmsr_done4abort_postqueue(acb); 4431 /* talk to iop 331 outstanding command aborted*/ 4432 arcmsr_abort_allcmd(acb); 4433 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 4434 srb = acb->psrb_pool[i]; 4435 if(srb->srb_state == ARCMSR_SRB_START) { 4436 srb->srb_state = ARCMSR_SRB_ABORTED; 4437 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 4438 arcmsr_srb_complete(srb, 1); 4439 } 4440 } 4441 } 4442 acb->srboutstandingcount = 0; 4443 acb->workingsrb_doneindex = 0; 4444 acb->workingsrb_startindex = 0; 4445 acb->pktRequestCount = 0; 4446 acb->pktReturnCount = 0; 4447 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 4448 return (0); 4449 } 4450 /* 4451 ************************************************************************ 4452 ************************************************************************ 4453 */ 4454 static int arcmsr_detach(device_t dev) 4455 { 4456 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 4457 int i; 4458 4459 callout_stop(&acb->devmap_callout); 4460 bus_teardown_intr(dev, acb->irqres, acb->ih); 4461 arcmsr_shutdown(dev); 4462 arcmsr_free_resource(acb); 4463 for(i=0; (acb->sys_res_arcmsr[i]!=NULL) && (i<2); i++) { 4464 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(i), acb->sys_res_arcmsr[i]); 4465 } 4466 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres); 4467 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 4468 xpt_async(AC_LOST_DEVICE, acb->ppath, NULL); 4469 xpt_free_path(acb->ppath); 4470 xpt_bus_deregister(cam_sim_path(acb->psim)); 4471 cam_sim_free(acb->psim, TRUE); 4472 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 4473 arcmsr_mutex_destroy(acb); 4474 return (0); 4475 } 4476 4477 #ifdef ARCMSR_DEBUG1 4478 static void arcmsr_dump_data(struct AdapterControlBlock *acb) 4479 { 4480 if((acb->pktRequestCount - acb->pktReturnCount) == 0) 4481 return; 4482 printf("Command Request Count =0x%x\n",acb->pktRequestCount); 4483 printf("Command Return Count =0x%x\n",acb->pktReturnCount); 4484 printf("Command (Req-Rtn) Count =0x%x\n",(acb->pktRequestCount - acb->pktReturnCount)); 4485 printf("Queued Command Count =0x%x\n",acb->srboutstandingcount); 4486 } 4487 #endif 4488 4489