1 /* 2 ******************************************************************************** 3 ** OS : FreeBSD 4 ** FILE NAME : arcmsr.c 5 ** BY : Erich Chen, Ching Huang 6 ** Description: SCSI RAID Device Driver for 7 ** ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x) 8 ** SATA/SAS RAID HOST Adapter 9 ******************************************************************************** 10 ******************************************************************************** 11 ** 12 ** SPDX-License-Identifier: BSD-3-Clause 13 ** 14 ** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved. 15 ** 16 ** Redistribution and use in source and binary forms, with or without 17 ** modification, are permitted provided that the following conditions 18 ** are met: 19 ** 1. Redistributions of source code must retain the above copyright 20 ** notice, this list of conditions and the following disclaimer. 21 ** 2. Redistributions in binary form must reproduce the above copyright 22 ** notice, this list of conditions and the following disclaimer in the 23 ** documentation and/or other materials provided with the distribution. 24 ** 3. The name of the author may not be used to endorse or promote products 25 ** derived from this software without specific prior written permission. 26 ** 27 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 28 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 29 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 31 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT 32 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 34 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 36 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 ******************************************************************************** 38 ** History 39 ** 40 ** REV# DATE NAME DESCRIPTION 41 ** 1.00.00.00 03/31/2004 Erich Chen First release 42 ** 1.20.00.02 11/29/2004 Erich Chen bug fix with arcmsr_bus_reset when PHY error 43 ** 1.20.00.03 04/19/2005 Erich Chen add SATA 24 Ports adapter type support 44 ** clean unused function 45 ** 1.20.00.12 09/12/2005 Erich Chen bug fix with abort command handling, 46 ** firmware version check 47 ** and firmware update notify for hardware bug fix 48 ** handling if none zero high part physical address 49 ** of srb resource 50 ** 1.20.00.13 08/18/2006 Erich Chen remove pending srb and report busy 51 ** add iop message xfer 52 ** with scsi pass-through command 53 ** add new device id of sas raid adapters 54 ** code fit for SPARC64 & PPC 55 ** 1.20.00.14 02/05/2007 Erich Chen bug fix for incorrect ccb_h.status report 56 ** and cause g_vfs_done() read write error 57 ** 1.20.00.15 10/10/2007 Erich Chen support new RAID adapter type ARC120x 58 ** 1.20.00.16 10/10/2009 Erich Chen Bug fix for RAID adapter type ARC120x 59 ** bus_dmamem_alloc() with BUS_DMA_ZERO 60 ** 1.20.00.17 07/15/2010 Ching Huang Added support ARC1880 61 ** report CAM_DEV_NOT_THERE instead of CAM_SEL_TIMEOUT when device failed, 62 ** prevent cam_periph_error removing all LUN devices of one Target id 63 ** for any one LUN device failed 64 ** 1.20.00.18 10/14/2010 Ching Huang Fixed "inquiry data fails comparion at DV1 step" 65 ** 10/25/2010 Ching Huang Fixed bad range input in bus_alloc_resource for ADAPTER_TYPE_B 66 ** 1.20.00.19 11/11/2010 Ching Huang Fixed arcmsr driver prevent arcsas support for Areca SAS HBA ARC13x0 67 ** 1.20.00.20 12/08/2010 Ching Huang Avoid calling atomic_set_int function 68 ** 1.20.00.21 02/08/2011 Ching Huang Implement I/O request timeout 69 ** 02/14/2011 Ching Huang Modified pktRequestCount 70 ** 1.20.00.21 03/03/2011 Ching Huang if a command timeout, then wait its ccb back before free it 71 ** 1.20.00.22 07/04/2011 Ching Huang Fixed multiple MTX panic 72 ** 1.20.00.23 10/28/2011 Ching Huang Added TIMEOUT_DELAY in case of too many HDDs need to start 73 ** 1.20.00.23 11/08/2011 Ching Huang Added report device transfer speed 74 ** 1.20.00.23 01/30/2012 Ching Huang Fixed Request requeued and Retrying command 75 ** 1.20.00.24 06/11/2012 Ching Huang Fixed return sense data condition 76 ** 1.20.00.25 08/17/2012 Ching Huang Fixed hotplug device no function on type A adapter 77 ** 1.20.00.26 12/14/2012 Ching Huang Added support ARC1214,1224,1264,1284 78 ** 1.20.00.27 05/06/2013 Ching Huang Fixed out standing cmd full on ARC-12x4 79 ** 1.20.00.28 09/13/2013 Ching Huang Removed recursive mutex in arcmsr_abort_dr_ccbs 80 ** 1.20.00.29 12/18/2013 Ching Huang Change simq allocation number, support ARC1883 81 ** 1.30.00.00 11/30/2015 Ching Huang Added support ARC1203 82 ** 1.40.00.00 07/11/2017 Ching Huang Added support ARC1884 83 ** 1.40.00.01 10/30/2017 Ching Huang Fixed release memory resource 84 ** 1.50.00.00 09/30/2020 Ching Huang Added support ARC-1886, NVMe/SAS/SATA controller 85 ** 1.50.00.01 02/26/2021 Ching Huang Fixed no action of hot plugging device on type_F adapter 86 ** 1.50.00.02 04/16/2021 Ching Huang Fixed scsi command timeout on ARC-1886 when 87 ** scatter-gather count large than some number 88 ** 1.50.00.03 05/04/2021 Ching Huang Fixed doorbell status arrived late on ARC-1886 89 ** 1.50.00.04 12/08/2021 Ching Huang Fixed boot up hung under ARC-1886 with no volume created 90 ** 1.50.00.05 03/23/2023 Ching Huang Fixed reading buffer empty length error 91 ****************************************************************************************** 92 */ 93 94 #include <sys/cdefs.h> 95 #if 0 96 #define ARCMSR_DEBUG1 1 97 #endif 98 #include <sys/param.h> 99 #include <sys/systm.h> 100 #include <sys/malloc.h> 101 #include <sys/kernel.h> 102 #include <sys/bus.h> 103 #include <sys/queue.h> 104 #include <sys/stat.h> 105 #include <sys/devicestat.h> 106 #include <sys/kthread.h> 107 #include <sys/module.h> 108 #include <sys/proc.h> 109 #include <sys/lock.h> 110 #include <sys/sysctl.h> 111 #include <sys/poll.h> 112 #include <sys/ioccom.h> 113 #include <vm/vm.h> 114 #include <vm/vm_param.h> 115 #include <vm/pmap.h> 116 117 #include <isa/rtc.h> 118 119 #include <machine/bus.h> 120 #include <machine/resource.h> 121 #include <machine/atomic.h> 122 #include <sys/conf.h> 123 #include <sys/rman.h> 124 125 #include <cam/cam.h> 126 #include <cam/cam_ccb.h> 127 #include <cam/cam_sim.h> 128 #include <cam/cam_periph.h> 129 #include <cam/cam_xpt_periph.h> 130 #include <cam/cam_xpt_sim.h> 131 #include <cam/cam_debug.h> 132 #include <cam/scsi/scsi_all.h> 133 #include <cam/scsi/scsi_message.h> 134 /* 135 ************************************************************************** 136 ************************************************************************** 137 */ 138 #include <sys/selinfo.h> 139 #include <sys/mutex.h> 140 #include <sys/endian.h> 141 #include <dev/pci/pcivar.h> 142 #include <dev/pci/pcireg.h> 143 144 #define arcmsr_callout_init(a) callout_init(a, /*mpsafe*/1); 145 146 #define ARCMSR_DRIVER_VERSION "arcmsr version 1.50.00.05 2023-03-23" 147 #include <dev/arcmsr/arcmsr.h> 148 /* 149 ************************************************************************** 150 ************************************************************************** 151 */ 152 static void arcmsr_free_srb(struct CommandControlBlock *srb); 153 static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb); 154 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb); 155 static int arcmsr_probe(device_t dev); 156 static int arcmsr_attach(device_t dev); 157 static int arcmsr_detach(device_t dev); 158 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg); 159 static void arcmsr_iop_parking(struct AdapterControlBlock *acb); 160 static int arcmsr_shutdown(device_t dev); 161 static void arcmsr_interrupt(struct AdapterControlBlock *acb); 162 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb); 163 static void arcmsr_free_resource(struct AdapterControlBlock *acb); 164 static void arcmsr_bus_reset(struct AdapterControlBlock *acb); 165 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb); 166 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb); 167 static void arcmsr_iop_init(struct AdapterControlBlock *acb); 168 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb); 169 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, struct QBUFFER *prbuffer); 170 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb); 171 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb); 172 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag); 173 static void arcmsr_iop_reset(struct AdapterControlBlock *acb); 174 static void arcmsr_report_sense_info(struct CommandControlBlock *srb); 175 static void arcmsr_build_srb(struct CommandControlBlock *srb, bus_dma_segment_t *dm_segs, u_int32_t nseg); 176 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb); 177 static int arcmsr_resume(device_t dev); 178 static int arcmsr_suspend(device_t dev); 179 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb); 180 static void arcmsr_polling_devmap(void *arg); 181 static void arcmsr_srb_timeout(void *arg); 182 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb); 183 static void arcmsr_hbe_postqueue_isr(struct AdapterControlBlock *acb); 184 static void arcmsr_hbf_postqueue_isr(struct AdapterControlBlock *acb); 185 static void arcmsr_teardown_intr(device_t dev, struct AdapterControlBlock *acb); 186 #ifdef ARCMSR_DEBUG1 187 static void arcmsr_dump_data(struct AdapterControlBlock *acb); 188 #endif 189 /* 190 ************************************************************************** 191 ************************************************************************** 192 */ 193 static void UDELAY(u_int32_t us) { DELAY(us); } 194 /* 195 ************************************************************************** 196 ************************************************************************** 197 */ 198 static bus_dmamap_callback_t arcmsr_map_free_srb; 199 static bus_dmamap_callback_t arcmsr_execute_srb; 200 /* 201 ************************************************************************** 202 ************************************************************************** 203 */ 204 static d_open_t arcmsr_open; 205 static d_close_t arcmsr_close; 206 static d_ioctl_t arcmsr_ioctl; 207 208 static device_method_t arcmsr_methods[]={ 209 DEVMETHOD(device_probe, arcmsr_probe), 210 DEVMETHOD(device_attach, arcmsr_attach), 211 DEVMETHOD(device_detach, arcmsr_detach), 212 DEVMETHOD(device_shutdown, arcmsr_shutdown), 213 DEVMETHOD(device_suspend, arcmsr_suspend), 214 DEVMETHOD(device_resume, arcmsr_resume), 215 DEVMETHOD_END 216 }; 217 218 static driver_t arcmsr_driver={ 219 "arcmsr", arcmsr_methods, sizeof(struct AdapterControlBlock) 220 }; 221 222 DRIVER_MODULE(arcmsr, pci, arcmsr_driver, 0, 0); 223 MODULE_DEPEND(arcmsr, pci, 1, 1, 1); 224 MODULE_DEPEND(arcmsr, cam, 1, 1, 1); 225 #ifndef BUS_DMA_COHERENT 226 #define BUS_DMA_COHERENT 0x04 /* hint: map memory in a coherent way */ 227 #endif 228 static struct cdevsw arcmsr_cdevsw={ 229 .d_version = D_VERSION, 230 .d_open = arcmsr_open, /* open */ 231 .d_close = arcmsr_close, /* close */ 232 .d_ioctl = arcmsr_ioctl, /* ioctl */ 233 .d_name = "arcmsr", /* name */ 234 }; 235 /* 236 ************************************************************************** 237 ************************************************************************** 238 */ 239 static int arcmsr_open(struct cdev *dev, int flags, int fmt, struct thread *proc) 240 { 241 return (0); 242 } 243 /* 244 ************************************************************************** 245 ************************************************************************** 246 */ 247 static int arcmsr_close(struct cdev *dev, int flags, int fmt, struct thread *proc) 248 { 249 return 0; 250 } 251 /* 252 ************************************************************************** 253 ************************************************************************** 254 */ 255 static int arcmsr_ioctl(struct cdev *dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc) 256 { 257 struct AdapterControlBlock *acb = dev->si_drv1; 258 259 return (arcmsr_iop_ioctlcmd(acb, ioctl_cmd, arg)); 260 } 261 /* 262 ********************************************************************** 263 ********************************************************************** 264 */ 265 static u_int32_t arcmsr_disable_allintr( struct AdapterControlBlock *acb) 266 { 267 u_int32_t intmask_org = 0; 268 269 switch (acb->adapter_type) { 270 case ACB_ADAPTER_TYPE_A: { 271 /* disable all outbound interrupt */ 272 intmask_org = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intmask); /* disable outbound message0 int */ 273 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE); 274 } 275 break; 276 case ACB_ADAPTER_TYPE_B: { 277 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 278 /* disable all outbound interrupt */ 279 intmask_org = READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask) 280 & (~ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); /* disable outbound message0 int */ 281 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask, 0); /* disable all interrupt */ 282 } 283 break; 284 case ACB_ADAPTER_TYPE_C: { 285 /* disable all outbound interrupt */ 286 intmask_org = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask); /* disable outbound message0 int */ 287 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE); 288 } 289 break; 290 case ACB_ADAPTER_TYPE_D: { 291 /* disable all outbound interrupt */ 292 intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); /* disable outbound message0 int */ 293 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE); 294 } 295 break; 296 case ACB_ADAPTER_TYPE_E: 297 case ACB_ADAPTER_TYPE_F: { 298 /* disable all outbound interrupt */ 299 intmask_org = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_mask); /* disable outbound message0 int */ 300 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_mask, intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE); 301 } 302 break; 303 } 304 return (intmask_org); 305 } 306 /* 307 ********************************************************************** 308 ********************************************************************** 309 */ 310 static void arcmsr_enable_allintr( struct AdapterControlBlock *acb, u_int32_t intmask_org) 311 { 312 u_int32_t mask; 313 314 switch (acb->adapter_type) { 315 case ACB_ADAPTER_TYPE_A: { 316 /* enable outbound Post Queue, outbound doorbell Interrupt */ 317 mask = ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE|ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE); 318 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org & mask); 319 acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff; 320 } 321 break; 322 case ACB_ADAPTER_TYPE_B: { 323 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 324 /* enable ARCMSR_IOP2DRV_MESSAGE_CMD_DONE */ 325 mask = (ARCMSR_IOP2DRV_DATA_WRITE_OK|ARCMSR_IOP2DRV_DATA_READ_OK|ARCMSR_IOP2DRV_CDB_DONE|ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); 326 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask, intmask_org | mask); /*1=interrupt enable, 0=interrupt disable*/ 327 acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f; 328 } 329 break; 330 case ACB_ADAPTER_TYPE_C: { 331 /* enable outbound Post Queue, outbound doorbell Interrupt */ 332 mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK); 333 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org & mask); 334 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f; 335 } 336 break; 337 case ACB_ADAPTER_TYPE_D: { 338 /* enable outbound Post Queue, outbound doorbell Interrupt */ 339 mask = ARCMSR_HBDMU_ALL_INT_ENABLE; 340 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | mask); 341 CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); 342 acb->outbound_int_enable = mask; 343 } 344 break; 345 case ACB_ADAPTER_TYPE_E: 346 case ACB_ADAPTER_TYPE_F: { 347 /* enable outbound Post Queue, outbound doorbell Interrupt */ 348 mask = ~(ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR); 349 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_mask, intmask_org & mask); 350 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f; 351 } 352 break; 353 } 354 } 355 /* 356 ********************************************************************** 357 ********************************************************************** 358 */ 359 static u_int8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb) 360 { 361 u_int32_t Index; 362 u_int8_t Retries = 0x00; 363 364 do { 365 for(Index=0; Index < 100; Index++) { 366 if(CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { 367 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);/*clear interrupt*/ 368 return TRUE; 369 } 370 UDELAY(10000); 371 }/*max 1 seconds*/ 372 }while(Retries++ < 20);/*max 20 sec*/ 373 return (FALSE); 374 } 375 /* 376 ********************************************************************** 377 ********************************************************************** 378 */ 379 static u_int8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb) 380 { 381 u_int32_t Index; 382 u_int8_t Retries = 0x00; 383 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 384 385 do { 386 for(Index=0; Index < 100; Index++) { 387 if(READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) { 388 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt*/ 389 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 390 return TRUE; 391 } 392 UDELAY(10000); 393 }/*max 1 seconds*/ 394 }while(Retries++ < 20);/*max 20 sec*/ 395 return (FALSE); 396 } 397 /* 398 ********************************************************************** 399 ********************************************************************** 400 */ 401 static u_int8_t arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock *acb) 402 { 403 u_int32_t Index; 404 u_int8_t Retries = 0x00; 405 406 do { 407 for(Index=0; Index < 100; Index++) { 408 if(CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 409 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);/*clear interrupt*/ 410 return TRUE; 411 } 412 UDELAY(10000); 413 }/*max 1 seconds*/ 414 }while(Retries++ < 20);/*max 20 sec*/ 415 return (FALSE); 416 } 417 /* 418 ********************************************************************** 419 ********************************************************************** 420 */ 421 static u_int8_t arcmsr_hbd_wait_msgint_ready(struct AdapterControlBlock *acb) 422 { 423 u_int32_t Index; 424 u_int8_t Retries = 0x00; 425 426 do { 427 for(Index=0; Index < 100; Index++) { 428 if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) { 429 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);/*clear interrupt*/ 430 return TRUE; 431 } 432 UDELAY(10000); 433 }/*max 1 seconds*/ 434 }while(Retries++ < 20);/*max 20 sec*/ 435 return (FALSE); 436 } 437 /* 438 ********************************************************************** 439 ********************************************************************** 440 */ 441 static u_int8_t arcmsr_hbe_wait_msgint_ready(struct AdapterControlBlock *acb) 442 { 443 u_int32_t Index, read_doorbell; 444 u_int8_t Retries = 0x00; 445 446 do { 447 for(Index=0; Index < 100; Index++) { 448 read_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell); 449 if((read_doorbell ^ acb->in_doorbell) & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) { 450 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0);/*clear interrupt*/ 451 acb->in_doorbell = read_doorbell; 452 return TRUE; 453 } 454 UDELAY(10000); 455 }/*max 1 seconds*/ 456 }while(Retries++ < 20);/*max 20 sec*/ 457 return (FALSE); 458 } 459 /* 460 ************************************************************************ 461 ************************************************************************ 462 */ 463 static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb) 464 { 465 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 466 467 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 468 do { 469 if(arcmsr_hba_wait_msgint_ready(acb)) { 470 break; 471 } else { 472 retry_count--; 473 } 474 }while(retry_count != 0); 475 } 476 /* 477 ************************************************************************ 478 ************************************************************************ 479 */ 480 static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb) 481 { 482 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 483 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 484 485 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_FLUSH_CACHE); 486 do { 487 if(arcmsr_hbb_wait_msgint_ready(acb)) { 488 break; 489 } else { 490 retry_count--; 491 } 492 }while(retry_count != 0); 493 } 494 /* 495 ************************************************************************ 496 ************************************************************************ 497 */ 498 static void arcmsr_flush_hbc_cache(struct AdapterControlBlock *acb) 499 { 500 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 501 502 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 503 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 504 do { 505 if(arcmsr_hbc_wait_msgint_ready(acb)) { 506 break; 507 } else { 508 retry_count--; 509 } 510 }while(retry_count != 0); 511 } 512 /* 513 ************************************************************************ 514 ************************************************************************ 515 */ 516 static void arcmsr_flush_hbd_cache(struct AdapterControlBlock *acb) 517 { 518 int retry_count = 30; /* enlarge wait flush adapter cache time: 10 minute */ 519 520 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 521 do { 522 if(arcmsr_hbd_wait_msgint_ready(acb)) { 523 break; 524 } else { 525 retry_count--; 526 } 527 }while(retry_count != 0); 528 } 529 /* 530 ************************************************************************ 531 ************************************************************************ 532 */ 533 static void arcmsr_flush_hbe_cache(struct AdapterControlBlock *acb) 534 { 535 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 536 537 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 538 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 539 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 540 do { 541 if(arcmsr_hbe_wait_msgint_ready(acb)) { 542 break; 543 } else { 544 retry_count--; 545 } 546 }while(retry_count != 0); 547 } 548 /* 549 ************************************************************************ 550 ************************************************************************ 551 */ 552 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb) 553 { 554 switch (acb->adapter_type) { 555 case ACB_ADAPTER_TYPE_A: { 556 arcmsr_flush_hba_cache(acb); 557 } 558 break; 559 case ACB_ADAPTER_TYPE_B: { 560 arcmsr_flush_hbb_cache(acb); 561 } 562 break; 563 case ACB_ADAPTER_TYPE_C: { 564 arcmsr_flush_hbc_cache(acb); 565 } 566 break; 567 case ACB_ADAPTER_TYPE_D: { 568 arcmsr_flush_hbd_cache(acb); 569 } 570 break; 571 case ACB_ADAPTER_TYPE_E: 572 case ACB_ADAPTER_TYPE_F: { 573 arcmsr_flush_hbe_cache(acb); 574 } 575 break; 576 } 577 } 578 /* 579 ******************************************************************************* 580 ******************************************************************************* 581 */ 582 static int arcmsr_suspend(device_t dev) 583 { 584 struct AdapterControlBlock *acb = device_get_softc(dev); 585 586 /* flush controller */ 587 arcmsr_iop_parking(acb); 588 /* disable all outbound interrupt */ 589 arcmsr_disable_allintr(acb); 590 return(0); 591 } 592 /* 593 ******************************************************************************* 594 ******************************************************************************* 595 */ 596 static int arcmsr_resume(device_t dev) 597 { 598 struct AdapterControlBlock *acb = device_get_softc(dev); 599 600 arcmsr_iop_init(acb); 601 return(0); 602 } 603 /* 604 ********************************************************************************* 605 ********************************************************************************* 606 */ 607 static void arcmsr_async(void *cb_arg, u_int32_t code, struct cam_path *path, void *arg) 608 { 609 u_int8_t target_id, target_lun; 610 611 switch (code) { 612 case AC_LOST_DEVICE: 613 target_id = xpt_path_target_id(path); 614 target_lun = xpt_path_lun_id(path); 615 if((target_id > ARCMSR_MAX_TARGETID) || (target_lun > ARCMSR_MAX_TARGETLUN)) { 616 break; 617 } 618 break; 619 default: 620 break; 621 } 622 } 623 /* 624 ********************************************************************** 625 ********************************************************************** 626 */ 627 static void arcmsr_report_sense_info(struct CommandControlBlock *srb) 628 { 629 union ccb *pccb = srb->pccb; 630 631 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 632 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 633 if(pccb->csio.sense_len) { 634 memset(&pccb->csio.sense_data, 0, sizeof(pccb->csio.sense_data)); 635 memcpy(&pccb->csio.sense_data, srb->arcmsr_cdb.SenseData, 636 get_min(sizeof(struct SENSE_DATA), sizeof(pccb->csio.sense_data))); 637 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); /* Valid,ErrorCode */ 638 pccb->ccb_h.status |= CAM_AUTOSNS_VALID; 639 } 640 } 641 /* 642 ********************************************************************* 643 ********************************************************************* 644 */ 645 static void arcmsr_abort_hba_allcmd(struct AdapterControlBlock *acb) 646 { 647 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 648 if(!arcmsr_hba_wait_msgint_ready(acb)) { 649 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 650 } 651 } 652 /* 653 ********************************************************************* 654 ********************************************************************* 655 */ 656 static void arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb) 657 { 658 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 659 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_ABORT_CMD); 660 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 661 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 662 } 663 } 664 /* 665 ********************************************************************* 666 ********************************************************************* 667 */ 668 static void arcmsr_abort_hbc_allcmd(struct AdapterControlBlock *acb) 669 { 670 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 671 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 672 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 673 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 674 } 675 } 676 /* 677 ********************************************************************* 678 ********************************************************************* 679 */ 680 static void arcmsr_abort_hbd_allcmd(struct AdapterControlBlock *acb) 681 { 682 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 683 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 684 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 685 } 686 } 687 /* 688 ********************************************************************* 689 ********************************************************************* 690 */ 691 static void arcmsr_abort_hbe_allcmd(struct AdapterControlBlock *acb) 692 { 693 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 694 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 695 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 696 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 697 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 698 } 699 } 700 /* 701 ********************************************************************* 702 ********************************************************************* 703 */ 704 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb) 705 { 706 switch (acb->adapter_type) { 707 case ACB_ADAPTER_TYPE_A: { 708 arcmsr_abort_hba_allcmd(acb); 709 } 710 break; 711 case ACB_ADAPTER_TYPE_B: { 712 arcmsr_abort_hbb_allcmd(acb); 713 } 714 break; 715 case ACB_ADAPTER_TYPE_C: { 716 arcmsr_abort_hbc_allcmd(acb); 717 } 718 break; 719 case ACB_ADAPTER_TYPE_D: { 720 arcmsr_abort_hbd_allcmd(acb); 721 } 722 break; 723 case ACB_ADAPTER_TYPE_E: 724 case ACB_ADAPTER_TYPE_F: { 725 arcmsr_abort_hbe_allcmd(acb); 726 } 727 break; 728 } 729 } 730 /* 731 ********************************************************************** 732 ********************************************************************** 733 */ 734 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag) 735 { 736 struct AdapterControlBlock *acb = srb->acb; 737 union ccb *pccb = srb->pccb; 738 739 if(srb->srb_flags & SRB_FLAG_TIMER_START) 740 callout_stop(&srb->ccb_callout); 741 if((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 742 bus_dmasync_op_t op; 743 744 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 745 op = BUS_DMASYNC_POSTREAD; 746 } else { 747 op = BUS_DMASYNC_POSTWRITE; 748 } 749 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op); 750 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap); 751 } 752 if(stand_flag == 1) { 753 atomic_subtract_int(&acb->srboutstandingcount, 1); 754 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) && ( 755 acb->srboutstandingcount < (acb->maxOutstanding -10))) { 756 acb->acb_flags &= ~ACB_F_CAM_DEV_QFRZN; 757 pccb->ccb_h.status |= CAM_RELEASE_SIMQ; 758 } 759 } 760 if(srb->srb_state != ARCMSR_SRB_TIMEOUT) 761 arcmsr_free_srb(srb); 762 acb->pktReturnCount++; 763 xpt_done(pccb); 764 } 765 /* 766 ************************************************************************** 767 ************************************************************************** 768 */ 769 static void arcmsr_report_srb_state(struct AdapterControlBlock *acb, struct CommandControlBlock *srb, u_int16_t error) 770 { 771 int target, lun; 772 773 target = srb->pccb->ccb_h.target_id; 774 lun = srb->pccb->ccb_h.target_lun; 775 if(error == FALSE) { 776 if(acb->devstate[target][lun] == ARECA_RAID_GONE) { 777 acb->devstate[target][lun] = ARECA_RAID_GOOD; 778 } 779 srb->pccb->ccb_h.status |= CAM_REQ_CMP; 780 arcmsr_srb_complete(srb, 1); 781 } else { 782 switch(srb->arcmsr_cdb.DeviceStatus) { 783 case ARCMSR_DEV_SELECT_TIMEOUT: { 784 if(acb->devstate[target][lun] == ARECA_RAID_GOOD) { 785 printf( "arcmsr%d: Target=%x, Lun=%x, selection timeout, raid volume was lost\n", acb->pci_unit, target, lun); 786 } 787 acb->devstate[target][lun] = ARECA_RAID_GONE; 788 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 789 arcmsr_srb_complete(srb, 1); 790 } 791 break; 792 case ARCMSR_DEV_ABORTED: 793 case ARCMSR_DEV_INIT_FAIL: { 794 acb->devstate[target][lun] = ARECA_RAID_GONE; 795 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 796 arcmsr_srb_complete(srb, 1); 797 } 798 break; 799 case SCSISTAT_CHECK_CONDITION: { 800 acb->devstate[target][lun] = ARECA_RAID_GOOD; 801 arcmsr_report_sense_info(srb); 802 arcmsr_srb_complete(srb, 1); 803 } 804 break; 805 default: 806 printf("arcmsr%d: scsi id=%d lun=%d isr got command error done,but got unknown DeviceStatus=0x%x \n" 807 , acb->pci_unit, target, lun ,srb->arcmsr_cdb.DeviceStatus); 808 acb->devstate[target][lun] = ARECA_RAID_GONE; 809 srb->pccb->ccb_h.status |= CAM_UNCOR_PARITY; 810 /*unknown error or crc error just for retry*/ 811 arcmsr_srb_complete(srb, 1); 812 break; 813 } 814 } 815 } 816 /* 817 ************************************************************************** 818 ************************************************************************** 819 */ 820 static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, u_int32_t flag_srb, u_int16_t error) 821 { 822 struct CommandControlBlock *srb; 823 824 /* check if command done with no error*/ 825 switch (acb->adapter_type) { 826 case ACB_ADAPTER_TYPE_A: 827 case ACB_ADAPTER_TYPE_B: 828 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 829 break; 830 case ACB_ADAPTER_TYPE_C: 831 case ACB_ADAPTER_TYPE_D: 832 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0)); /*frame must be 32 bytes aligned*/ 833 break; 834 case ACB_ADAPTER_TYPE_E: 835 case ACB_ADAPTER_TYPE_F: 836 srb = acb->psrb_pool[flag_srb]; 837 break; 838 default: 839 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 840 break; 841 } 842 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 843 if(srb->srb_state == ARCMSR_SRB_TIMEOUT) { 844 arcmsr_free_srb(srb); 845 printf("arcmsr%d: srb='%p' return srb has been timeouted\n", acb->pci_unit, srb); 846 return; 847 } 848 printf("arcmsr%d: return srb has been completed\n" 849 "srb='%p' srb_state=0x%x outstanding srb count=%d \n", 850 acb->pci_unit, srb, srb->srb_state, acb->srboutstandingcount); 851 return; 852 } 853 arcmsr_report_srb_state(acb, srb, error); 854 } 855 /* 856 ************************************************************************** 857 ************************************************************************** 858 */ 859 static void arcmsr_srb_timeout(void *arg) 860 { 861 struct CommandControlBlock *srb = (struct CommandControlBlock *)arg; 862 struct AdapterControlBlock *acb; 863 int target, lun; 864 u_int8_t cmd; 865 866 target = srb->pccb->ccb_h.target_id; 867 lun = srb->pccb->ccb_h.target_lun; 868 acb = srb->acb; 869 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 870 if(srb->srb_state == ARCMSR_SRB_START) 871 { 872 cmd = scsiio_cdb_ptr(&srb->pccb->csio)[0]; 873 srb->srb_state = ARCMSR_SRB_TIMEOUT; 874 srb->pccb->ccb_h.status |= CAM_CMD_TIMEOUT; 875 arcmsr_srb_complete(srb, 1); 876 printf("arcmsr%d: scsi id %d lun %d cmd=0x%x srb='%p' ccb command time out!\n", 877 acb->pci_unit, target, lun, cmd, srb); 878 } 879 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 880 #ifdef ARCMSR_DEBUG1 881 arcmsr_dump_data(acb); 882 #endif 883 } 884 885 /* 886 ********************************************************************** 887 ********************************************************************** 888 */ 889 static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb) 890 { 891 int i=0; 892 u_int32_t flag_srb; 893 u_int16_t error; 894 895 switch (acb->adapter_type) { 896 case ACB_ADAPTER_TYPE_A: { 897 u_int32_t outbound_intstatus; 898 899 /*clear and abort all outbound posted Q*/ 900 outbound_intstatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 901 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);/*clear interrupt*/ 902 while(((flag_srb=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_queueport)) != 0xFFFFFFFF) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) { 903 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 904 arcmsr_drain_donequeue(acb, flag_srb, error); 905 } 906 } 907 break; 908 case ACB_ADAPTER_TYPE_B: { 909 struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu; 910 911 /*clear all outbound posted Q*/ 912 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */ 913 for(i=0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) { 914 if((flag_srb = phbbmu->done_qbuffer[i]) != 0) { 915 phbbmu->done_qbuffer[i] = 0; 916 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 917 arcmsr_drain_donequeue(acb, flag_srb, error); 918 } 919 phbbmu->post_qbuffer[i] = 0; 920 }/*drain reply FIFO*/ 921 phbbmu->doneq_index = 0; 922 phbbmu->postq_index = 0; 923 } 924 break; 925 case ACB_ADAPTER_TYPE_C: { 926 while((CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) { 927 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 928 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 929 arcmsr_drain_donequeue(acb, flag_srb, error); 930 } 931 } 932 break; 933 case ACB_ADAPTER_TYPE_D: 934 arcmsr_hbd_postqueue_isr(acb); 935 break; 936 case ACB_ADAPTER_TYPE_E: 937 arcmsr_hbe_postqueue_isr(acb); 938 break; 939 case ACB_ADAPTER_TYPE_F: 940 arcmsr_hbf_postqueue_isr(acb); 941 break; 942 } 943 } 944 /* 945 **************************************************************************** 946 **************************************************************************** 947 */ 948 static void arcmsr_iop_reset(struct AdapterControlBlock *acb) 949 { 950 struct CommandControlBlock *srb; 951 u_int32_t intmask_org; 952 u_int32_t i=0; 953 954 if(acb->srboutstandingcount>0) { 955 /* disable all outbound interrupt */ 956 intmask_org = arcmsr_disable_allintr(acb); 957 /*clear and abort all outbound posted Q*/ 958 arcmsr_done4abort_postqueue(acb); 959 /* talk to iop 331 outstanding command aborted*/ 960 arcmsr_abort_allcmd(acb); 961 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 962 srb = acb->psrb_pool[i]; 963 if(srb->srb_state == ARCMSR_SRB_START) { 964 srb->srb_state = ARCMSR_SRB_ABORTED; 965 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 966 arcmsr_srb_complete(srb, 1); 967 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p' aborted\n" 968 , acb->pci_unit, srb->pccb->ccb_h.target_id 969 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 970 } 971 } 972 /* enable all outbound interrupt */ 973 arcmsr_enable_allintr(acb, intmask_org); 974 } 975 acb->srboutstandingcount = 0; 976 acb->workingsrb_doneindex = 0; 977 acb->workingsrb_startindex = 0; 978 acb->pktRequestCount = 0; 979 acb->pktReturnCount = 0; 980 } 981 /* 982 ********************************************************************** 983 ********************************************************************** 984 */ 985 static void arcmsr_build_srb(struct CommandControlBlock *srb, 986 bus_dma_segment_t *dm_segs, u_int32_t nseg) 987 { 988 struct ARCMSR_CDB *arcmsr_cdb = &srb->arcmsr_cdb; 989 u_int8_t *psge = (u_int8_t *)&arcmsr_cdb->u; 990 u_int32_t address_lo, address_hi; 991 union ccb *pccb = srb->pccb; 992 struct ccb_scsiio *pcsio = &pccb->csio; 993 u_int32_t arccdbsize = 0x30; 994 995 memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB)); 996 arcmsr_cdb->Bus = 0; 997 arcmsr_cdb->TargetID = pccb->ccb_h.target_id; 998 arcmsr_cdb->LUN = pccb->ccb_h.target_lun; 999 arcmsr_cdb->Function = 1; 1000 arcmsr_cdb->CdbLength = (u_int8_t)pcsio->cdb_len; 1001 bcopy(scsiio_cdb_ptr(pcsio), arcmsr_cdb->Cdb, pcsio->cdb_len); 1002 if(nseg != 0) { 1003 struct AdapterControlBlock *acb = srb->acb; 1004 bus_dmasync_op_t op; 1005 u_int32_t length, i, cdb_sgcount = 0; 1006 1007 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1008 op = BUS_DMASYNC_PREREAD; 1009 } else { 1010 op = BUS_DMASYNC_PREWRITE; 1011 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE; 1012 srb->srb_flags |= SRB_FLAG_WRITE; 1013 } 1014 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op); 1015 for(i=0; i < nseg; i++) { 1016 /* Get the physical address of the current data pointer */ 1017 length = arcmsr_htole32(dm_segs[i].ds_len); 1018 address_lo = arcmsr_htole32(dma_addr_lo32(dm_segs[i].ds_addr)); 1019 address_hi = arcmsr_htole32(dma_addr_hi32(dm_segs[i].ds_addr)); 1020 if(address_hi == 0) { 1021 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge; 1022 pdma_sg->address = address_lo; 1023 pdma_sg->length = length; 1024 psge += sizeof(struct SG32ENTRY); 1025 arccdbsize += sizeof(struct SG32ENTRY); 1026 } else { 1027 u_int32_t sg64s_size = 0, tmplength = length; 1028 1029 while(1) { 1030 u_int64_t span4G, length0; 1031 struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge; 1032 1033 span4G = (u_int64_t)address_lo + tmplength; 1034 pdma_sg->addresshigh = address_hi; 1035 pdma_sg->address = address_lo; 1036 if(span4G > 0x100000000) { 1037 /*see if cross 4G boundary*/ 1038 length0 = 0x100000000-address_lo; 1039 pdma_sg->length = (u_int32_t)length0 | IS_SG64_ADDR; 1040 address_hi = address_hi+1; 1041 address_lo = 0; 1042 tmplength = tmplength - (u_int32_t)length0; 1043 sg64s_size += sizeof(struct SG64ENTRY); 1044 psge += sizeof(struct SG64ENTRY); 1045 cdb_sgcount++; 1046 } else { 1047 pdma_sg->length = tmplength | IS_SG64_ADDR; 1048 sg64s_size += sizeof(struct SG64ENTRY); 1049 psge += sizeof(struct SG64ENTRY); 1050 break; 1051 } 1052 } 1053 arccdbsize += sg64s_size; 1054 } 1055 cdb_sgcount++; 1056 } 1057 arcmsr_cdb->sgcount = (u_int8_t)cdb_sgcount; 1058 arcmsr_cdb->DataLength = pcsio->dxfer_len; 1059 if( arccdbsize > 256) { 1060 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE; 1061 } 1062 } else { 1063 arcmsr_cdb->DataLength = 0; 1064 } 1065 srb->arc_cdb_size = arccdbsize; 1066 arcmsr_cdb->msgPages = (arccdbsize/256) + ((arccdbsize % 256) ? 1 : 0); 1067 } 1068 /* 1069 ************************************************************************** 1070 ************************************************************************** 1071 */ 1072 static void arcmsr_post_srb(struct AdapterControlBlock *acb, struct CommandControlBlock *srb) 1073 { 1074 u_int32_t cdb_phyaddr_low = (u_int32_t) srb->cdb_phyaddr_low; 1075 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&srb->arcmsr_cdb; 1076 1077 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, (srb->srb_flags & SRB_FLAG_WRITE) ? BUS_DMASYNC_POSTWRITE:BUS_DMASYNC_POSTREAD); 1078 atomic_add_int(&acb->srboutstandingcount, 1); 1079 srb->srb_state = ARCMSR_SRB_START; 1080 1081 switch (acb->adapter_type) { 1082 case ACB_ADAPTER_TYPE_A: { 1083 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { 1084 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low|ARCMSR_SRBPOST_FLAG_SGL_BSIZE); 1085 } else { 1086 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low); 1087 } 1088 } 1089 break; 1090 case ACB_ADAPTER_TYPE_B: { 1091 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1092 int ending_index, index; 1093 1094 index = phbbmu->postq_index; 1095 ending_index = ((index+1) % ARCMSR_MAX_HBB_POSTQUEUE); 1096 phbbmu->post_qbuffer[ending_index] = 0; 1097 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { 1098 phbbmu->post_qbuffer[index] = cdb_phyaddr_low | ARCMSR_SRBPOST_FLAG_SGL_BSIZE; 1099 } else { 1100 phbbmu->post_qbuffer[index] = cdb_phyaddr_low; 1101 } 1102 index++; 1103 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 1104 phbbmu->postq_index = index; 1105 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_CDB_POSTED); 1106 } 1107 break; 1108 case ACB_ADAPTER_TYPE_C: { 1109 u_int32_t ccb_post_stamp, arc_cdb_size, cdb_phyaddr_hi32; 1110 1111 arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size; 1112 ccb_post_stamp = (cdb_phyaddr_low | ((arc_cdb_size-1) >> 6) | 1); 1113 cdb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high; 1114 if(cdb_phyaddr_hi32) 1115 { 1116 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_high, cdb_phyaddr_hi32); 1117 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp); 1118 } 1119 else 1120 { 1121 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp); 1122 } 1123 } 1124 break; 1125 case ACB_ADAPTER_TYPE_D: { 1126 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1127 u_int16_t index_stripped; 1128 u_int16_t postq_index; 1129 struct InBound_SRB *pinbound_srb; 1130 1131 ARCMSR_LOCK_ACQUIRE(&acb->postDone_lock); 1132 postq_index = phbdmu->postq_index; 1133 pinbound_srb = (struct InBound_SRB *)&phbdmu->post_qbuffer[postq_index & 0xFF]; 1134 pinbound_srb->addressHigh = srb->cdb_phyaddr_high; 1135 pinbound_srb->addressLow = srb->cdb_phyaddr_low; 1136 pinbound_srb->length = srb->arc_cdb_size >> 2; 1137 arcmsr_cdb->Context = srb->cdb_phyaddr_low; 1138 if (postq_index & 0x4000) { 1139 index_stripped = postq_index & 0xFF; 1140 index_stripped += 1; 1141 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1142 phbdmu->postq_index = index_stripped ? (index_stripped | 0x4000) : index_stripped; 1143 } else { 1144 index_stripped = postq_index; 1145 index_stripped += 1; 1146 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1147 phbdmu->postq_index = index_stripped ? index_stripped : (index_stripped | 0x4000); 1148 } 1149 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inboundlist_write_pointer, postq_index); 1150 ARCMSR_LOCK_RELEASE(&acb->postDone_lock); 1151 } 1152 break; 1153 case ACB_ADAPTER_TYPE_E: { 1154 u_int32_t ccb_post_stamp, arc_cdb_size; 1155 1156 arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size; 1157 ccb_post_stamp = (srb->smid | ((arc_cdb_size-1) >> 6)); 1158 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_queueport_high, 0); 1159 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_queueport_low, ccb_post_stamp); 1160 } 1161 break; 1162 case ACB_ADAPTER_TYPE_F: { 1163 u_int32_t ccb_post_stamp, arc_cdb_size; 1164 1165 if (srb->arc_cdb_size <= 0x300) 1166 arc_cdb_size = (srb->arc_cdb_size - 1) >> 6 | 1; 1167 else { 1168 arc_cdb_size = ((srb->arc_cdb_size + 0xff) >> 8) + 2; 1169 if (arc_cdb_size > 0xF) 1170 arc_cdb_size = 0xF; 1171 arc_cdb_size = (arc_cdb_size << 1) | 1; 1172 } 1173 ccb_post_stamp = (srb->smid | arc_cdb_size); 1174 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_queueport_high, 0); 1175 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_queueport_low, ccb_post_stamp); 1176 } 1177 break; 1178 } 1179 } 1180 /* 1181 ************************************************************************ 1182 ************************************************************************ 1183 */ 1184 static struct QBUFFER *arcmsr_get_iop_rqbuffer( struct AdapterControlBlock *acb) 1185 { 1186 struct QBUFFER *qbuffer=NULL; 1187 1188 switch (acb->adapter_type) { 1189 case ACB_ADAPTER_TYPE_A: { 1190 struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu; 1191 1192 qbuffer = (struct QBUFFER *)&phbamu->message_rbuffer; 1193 } 1194 break; 1195 case ACB_ADAPTER_TYPE_B: { 1196 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1197 1198 qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_rbuffer; 1199 } 1200 break; 1201 case ACB_ADAPTER_TYPE_C: { 1202 struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu; 1203 1204 qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer; 1205 } 1206 break; 1207 case ACB_ADAPTER_TYPE_D: { 1208 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1209 1210 qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_rbuffer; 1211 } 1212 break; 1213 case ACB_ADAPTER_TYPE_E: { 1214 struct HBE_MessageUnit *phbcmu = (struct HBE_MessageUnit *)acb->pmu; 1215 1216 qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer; 1217 } 1218 break; 1219 case ACB_ADAPTER_TYPE_F: 1220 qbuffer = (struct QBUFFER *)acb->message_rbuffer; 1221 break; 1222 } 1223 return(qbuffer); 1224 } 1225 /* 1226 ************************************************************************ 1227 ************************************************************************ 1228 */ 1229 static struct QBUFFER *arcmsr_get_iop_wqbuffer( struct AdapterControlBlock *acb) 1230 { 1231 struct QBUFFER *qbuffer = NULL; 1232 1233 switch (acb->adapter_type) { 1234 case ACB_ADAPTER_TYPE_A: { 1235 struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu; 1236 1237 qbuffer = (struct QBUFFER *)&phbamu->message_wbuffer; 1238 } 1239 break; 1240 case ACB_ADAPTER_TYPE_B: { 1241 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1242 1243 qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_wbuffer; 1244 } 1245 break; 1246 case ACB_ADAPTER_TYPE_C: { 1247 struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu; 1248 1249 qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer; 1250 } 1251 break; 1252 case ACB_ADAPTER_TYPE_D: { 1253 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1254 1255 qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_wbuffer; 1256 } 1257 break; 1258 case ACB_ADAPTER_TYPE_E: { 1259 struct HBE_MessageUnit *phbcmu = (struct HBE_MessageUnit *)acb->pmu; 1260 1261 qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer; 1262 } 1263 break; 1264 case ACB_ADAPTER_TYPE_F: 1265 qbuffer = (struct QBUFFER *)acb->message_wbuffer; 1266 break; 1267 } 1268 return(qbuffer); 1269 } 1270 /* 1271 ************************************************************************** 1272 ************************************************************************** 1273 */ 1274 static void arcmsr_iop_message_read(struct AdapterControlBlock *acb) 1275 { 1276 switch (acb->adapter_type) { 1277 case ACB_ADAPTER_TYPE_A: { 1278 /* let IOP know data has been read */ 1279 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK); 1280 } 1281 break; 1282 case ACB_ADAPTER_TYPE_B: { 1283 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1284 /* let IOP know data has been read */ 1285 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK); 1286 } 1287 break; 1288 case ACB_ADAPTER_TYPE_C: { 1289 /* let IOP know data has been read */ 1290 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK); 1291 } 1292 break; 1293 case ACB_ADAPTER_TYPE_D: { 1294 /* let IOP know data has been read */ 1295 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ); 1296 } 1297 break; 1298 case ACB_ADAPTER_TYPE_E: 1299 case ACB_ADAPTER_TYPE_F: { 1300 /* let IOP know data has been read */ 1301 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK; 1302 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 1303 } 1304 break; 1305 } 1306 } 1307 /* 1308 ************************************************************************** 1309 ************************************************************************** 1310 */ 1311 static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb) 1312 { 1313 switch (acb->adapter_type) { 1314 case ACB_ADAPTER_TYPE_A: { 1315 /* 1316 ** push inbound doorbell tell iop, driver data write ok 1317 ** and wait reply on next hwinterrupt for next Qbuffer post 1318 */ 1319 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK); 1320 } 1321 break; 1322 case ACB_ADAPTER_TYPE_B: { 1323 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1324 /* 1325 ** push inbound doorbell tell iop, driver data write ok 1326 ** and wait reply on next hwinterrupt for next Qbuffer post 1327 */ 1328 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_WRITE_OK); 1329 } 1330 break; 1331 case ACB_ADAPTER_TYPE_C: { 1332 /* 1333 ** push inbound doorbell tell iop, driver data write ok 1334 ** and wait reply on next hwinterrupt for next Qbuffer post 1335 */ 1336 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK); 1337 } 1338 break; 1339 case ACB_ADAPTER_TYPE_D: { 1340 /* 1341 ** push inbound doorbell tell iop, driver data write ok 1342 ** and wait reply on next hwinterrupt for next Qbuffer post 1343 */ 1344 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY); 1345 } 1346 break; 1347 case ACB_ADAPTER_TYPE_E: 1348 case ACB_ADAPTER_TYPE_F: { 1349 /* 1350 ** push inbound doorbell tell iop, driver data write ok 1351 ** and wait reply on next hwinterrupt for next Qbuffer post 1352 */ 1353 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK; 1354 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 1355 } 1356 break; 1357 } 1358 } 1359 /* 1360 ************************************************************************ 1361 ************************************************************************ 1362 */ 1363 static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb) 1364 { 1365 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1366 CHIP_REG_WRITE32(HBA_MessageUnit, 1367 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1368 if(!arcmsr_hba_wait_msgint_ready(acb)) { 1369 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n" 1370 , acb->pci_unit); 1371 } 1372 } 1373 /* 1374 ************************************************************************ 1375 ************************************************************************ 1376 */ 1377 static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb) 1378 { 1379 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1380 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1381 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_STOP_BGRB); 1382 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 1383 printf( "arcmsr%d: wait 'stop adapter background rebulid' timeout \n" 1384 , acb->pci_unit); 1385 } 1386 } 1387 /* 1388 ************************************************************************ 1389 ************************************************************************ 1390 */ 1391 static void arcmsr_stop_hbc_bgrb(struct AdapterControlBlock *acb) 1392 { 1393 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1394 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1395 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 1396 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 1397 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1398 } 1399 } 1400 /* 1401 ************************************************************************ 1402 ************************************************************************ 1403 */ 1404 static void arcmsr_stop_hbd_bgrb(struct AdapterControlBlock *acb) 1405 { 1406 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1407 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1408 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 1409 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1410 } 1411 } 1412 /* 1413 ************************************************************************ 1414 ************************************************************************ 1415 */ 1416 static void arcmsr_stop_hbe_bgrb(struct AdapterControlBlock *acb) 1417 { 1418 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1419 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1420 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 1421 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 1422 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 1423 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1424 } 1425 } 1426 /* 1427 ************************************************************************ 1428 ************************************************************************ 1429 */ 1430 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb) 1431 { 1432 switch (acb->adapter_type) { 1433 case ACB_ADAPTER_TYPE_A: { 1434 arcmsr_stop_hba_bgrb(acb); 1435 } 1436 break; 1437 case ACB_ADAPTER_TYPE_B: { 1438 arcmsr_stop_hbb_bgrb(acb); 1439 } 1440 break; 1441 case ACB_ADAPTER_TYPE_C: { 1442 arcmsr_stop_hbc_bgrb(acb); 1443 } 1444 break; 1445 case ACB_ADAPTER_TYPE_D: { 1446 arcmsr_stop_hbd_bgrb(acb); 1447 } 1448 break; 1449 case ACB_ADAPTER_TYPE_E: 1450 case ACB_ADAPTER_TYPE_F: { 1451 arcmsr_stop_hbe_bgrb(acb); 1452 } 1453 break; 1454 } 1455 } 1456 /* 1457 ************************************************************************ 1458 ************************************************************************ 1459 */ 1460 static void arcmsr_poll(struct cam_sim *psim) 1461 { 1462 struct AdapterControlBlock *acb; 1463 int mutex; 1464 1465 acb = (struct AdapterControlBlock *)cam_sim_softc(psim); 1466 mutex = mtx_owned(&acb->isr_lock); 1467 if( mutex == 0 ) 1468 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 1469 arcmsr_interrupt(acb); 1470 if( mutex == 0 ) 1471 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 1472 } 1473 /* 1474 ************************************************************************** 1475 ************************************************************************** 1476 */ 1477 static u_int32_t arcmsr_Read_iop_rqbuffer_data_D(struct AdapterControlBlock *acb, 1478 struct QBUFFER *prbuffer) { 1479 u_int8_t *pQbuffer; 1480 u_int8_t *buf1 = NULL; 1481 u_int32_t *iop_data, *buf2 = NULL; 1482 u_int32_t iop_len, data_len; 1483 1484 iop_data = (u_int32_t *)prbuffer->data; 1485 iop_len = (u_int32_t)prbuffer->data_len; 1486 if ( iop_len > 0 ) 1487 { 1488 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO); 1489 buf2 = (u_int32_t *)buf1; 1490 if( buf1 == NULL) 1491 return (0); 1492 data_len = iop_len; 1493 while(data_len >= 4) 1494 { 1495 *buf2++ = *iop_data++; 1496 data_len -= 4; 1497 } 1498 if(data_len) 1499 *buf2 = *iop_data; 1500 buf2 = (u_int32_t *)buf1; 1501 } 1502 while (iop_len > 0) { 1503 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex]; 1504 *pQbuffer = *buf1; 1505 acb->rqbuf_lastindex++; 1506 /* if last, index number set it to 0 */ 1507 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 1508 buf1++; 1509 iop_len--; 1510 } 1511 if(buf2) 1512 free( (u_int8_t *)buf2, M_DEVBUF); 1513 /* let IOP know data has been read */ 1514 arcmsr_iop_message_read(acb); 1515 return (1); 1516 } 1517 /* 1518 ************************************************************************** 1519 ************************************************************************** 1520 */ 1521 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, 1522 struct QBUFFER *prbuffer) { 1523 u_int8_t *pQbuffer; 1524 u_int8_t *iop_data; 1525 u_int32_t iop_len; 1526 1527 if(acb->adapter_type >= ACB_ADAPTER_TYPE_B) { 1528 return(arcmsr_Read_iop_rqbuffer_data_D(acb, prbuffer)); 1529 } 1530 iop_data = (u_int8_t *)prbuffer->data; 1531 iop_len = (u_int32_t)prbuffer->data_len; 1532 while (iop_len > 0) { 1533 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex]; 1534 *pQbuffer = *iop_data; 1535 acb->rqbuf_lastindex++; 1536 /* if last, index number set it to 0 */ 1537 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 1538 iop_data++; 1539 iop_len--; 1540 } 1541 /* let IOP know data has been read */ 1542 arcmsr_iop_message_read(acb); 1543 return (1); 1544 } 1545 /* 1546 ************************************************************************** 1547 ************************************************************************** 1548 */ 1549 static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb) 1550 { 1551 struct QBUFFER *prbuffer; 1552 int my_empty_len; 1553 1554 /*check this iop data if overflow my rqbuffer*/ 1555 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 1556 prbuffer = arcmsr_get_iop_rqbuffer(acb); 1557 if (acb->rqbuf_lastindex >= acb->rqbuf_firstindex) 1558 my_empty_len = (ARCMSR_MAX_QBUFFER - 1) - (acb->rqbuf_lastindex - acb->rqbuf_firstindex); 1559 else 1560 my_empty_len = acb->rqbuf_firstindex - acb->rqbuf_lastindex - 1; 1561 if(my_empty_len >= prbuffer->data_len) { 1562 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 1563 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 1564 } else { 1565 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 1566 } 1567 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 1568 } 1569 /* 1570 ********************************************************************** 1571 ********************************************************************** 1572 */ 1573 static void arcmsr_Write_data_2iop_wqbuffer_D(struct AdapterControlBlock *acb) 1574 { 1575 u_int8_t *pQbuffer; 1576 struct QBUFFER *pwbuffer; 1577 u_int8_t *buf1 = NULL; 1578 u_int32_t *iop_data, *buf2 = NULL; 1579 u_int32_t allxfer_len = 0, data_len; 1580 1581 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) { 1582 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO); 1583 buf2 = (u_int32_t *)buf1; 1584 if( buf1 == NULL) 1585 return; 1586 1587 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ); 1588 pwbuffer = arcmsr_get_iop_wqbuffer(acb); 1589 iop_data = (u_int32_t *)pwbuffer->data; 1590 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex) 1591 && (allxfer_len < 124)) { 1592 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex]; 1593 *buf1 = *pQbuffer; 1594 acb->wqbuf_firstindex++; 1595 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 1596 buf1++; 1597 allxfer_len++; 1598 } 1599 pwbuffer->data_len = allxfer_len; 1600 data_len = allxfer_len; 1601 buf1 = (u_int8_t *)buf2; 1602 while(data_len >= 4) 1603 { 1604 *iop_data++ = *buf2++; 1605 data_len -= 4; 1606 } 1607 if(data_len) 1608 *iop_data = *buf2; 1609 free( buf1, M_DEVBUF); 1610 arcmsr_iop_message_wrote(acb); 1611 } 1612 } 1613 /* 1614 ********************************************************************** 1615 ********************************************************************** 1616 */ 1617 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb) 1618 { 1619 u_int8_t *pQbuffer; 1620 struct QBUFFER *pwbuffer; 1621 u_int8_t *iop_data; 1622 int32_t allxfer_len=0; 1623 1624 if(acb->adapter_type >= ACB_ADAPTER_TYPE_B) { 1625 arcmsr_Write_data_2iop_wqbuffer_D(acb); 1626 return; 1627 } 1628 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) { 1629 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ); 1630 pwbuffer = arcmsr_get_iop_wqbuffer(acb); 1631 iop_data = (u_int8_t *)pwbuffer->data; 1632 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex) 1633 && (allxfer_len < 124)) { 1634 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex]; 1635 *iop_data = *pQbuffer; 1636 acb->wqbuf_firstindex++; 1637 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 1638 iop_data++; 1639 allxfer_len++; 1640 } 1641 pwbuffer->data_len = allxfer_len; 1642 arcmsr_iop_message_wrote(acb); 1643 } 1644 } 1645 /* 1646 ************************************************************************** 1647 ************************************************************************** 1648 */ 1649 static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb) 1650 { 1651 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 1652 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READ; 1653 /* 1654 ***************************************************************** 1655 ** check if there are any mail packages from user space program 1656 ** in my post bag, now is the time to send them into Areca's firmware 1657 ***************************************************************** 1658 */ 1659 if(acb->wqbuf_firstindex != acb->wqbuf_lastindex) { 1660 arcmsr_Write_data_2iop_wqbuffer(acb); 1661 } 1662 if(acb->wqbuf_firstindex == acb->wqbuf_lastindex) { 1663 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED; 1664 } 1665 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 1666 } 1667 /* 1668 ************************************************************************** 1669 ************************************************************************** 1670 */ 1671 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb) 1672 { 1673 /* 1674 if (ccb->ccb_h.status != CAM_REQ_CMP) 1675 printf("arcmsr_rescanLun_cb: Rescan Target=%x, lun=%x," 1676 "failure status=%x\n", ccb->ccb_h.target_id, 1677 ccb->ccb_h.target_lun, ccb->ccb_h.status); 1678 else 1679 printf("arcmsr_rescanLun_cb: Rescan lun successfully!\n"); 1680 */ 1681 xpt_free_path(ccb->ccb_h.path); 1682 xpt_free_ccb(ccb); 1683 } 1684 1685 static void arcmsr_rescan_lun(struct AdapterControlBlock *acb, int target, int lun) 1686 { 1687 struct cam_path *path; 1688 union ccb *ccb; 1689 1690 if ((ccb = (union ccb *)xpt_alloc_ccb_nowait()) == NULL) 1691 return; 1692 if (xpt_create_path(&path, NULL, cam_sim_path(acb->psim), target, lun) != CAM_REQ_CMP) 1693 { 1694 xpt_free_ccb(ccb); 1695 return; 1696 } 1697 /* printf("arcmsr_rescan_lun: Rescan Target=%x, Lun=%x\n", target, lun); */ 1698 xpt_setup_ccb(&ccb->ccb_h, path, 5); 1699 ccb->ccb_h.func_code = XPT_SCAN_LUN; 1700 ccb->ccb_h.cbfcnp = arcmsr_rescanLun_cb; 1701 ccb->crcn.flags = CAM_FLAG_NONE; 1702 xpt_action(ccb); 1703 } 1704 1705 static void arcmsr_abort_dr_ccbs(struct AdapterControlBlock *acb, int target, int lun) 1706 { 1707 struct CommandControlBlock *srb; 1708 u_int32_t intmask_org; 1709 int i; 1710 1711 /* disable all outbound interrupts */ 1712 intmask_org = arcmsr_disable_allintr(acb); 1713 for (i = 0; i < ARCMSR_MAX_FREESRB_NUM; i++) 1714 { 1715 srb = acb->psrb_pool[i]; 1716 if (srb->srb_state == ARCMSR_SRB_START) 1717 { 1718 if((target == srb->pccb->ccb_h.target_id) && (lun == srb->pccb->ccb_h.target_lun)) 1719 { 1720 srb->srb_state = ARCMSR_SRB_ABORTED; 1721 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 1722 arcmsr_srb_complete(srb, 1); 1723 printf("arcmsr%d: abort scsi id %d lun %d srb=%p \n", acb->pci_unit, target, lun, srb); 1724 } 1725 } 1726 } 1727 /* enable outbound Post Queue, outbound doorbell Interrupt */ 1728 arcmsr_enable_allintr(acb, intmask_org); 1729 } 1730 /* 1731 ************************************************************************** 1732 ************************************************************************** 1733 */ 1734 static void arcmsr_dr_handle(struct AdapterControlBlock *acb) { 1735 u_int32_t devicemap; 1736 u_int32_t target, lun; 1737 u_int32_t deviceMapCurrent[4]={0}; 1738 u_int8_t *pDevMap; 1739 1740 switch (acb->adapter_type) { 1741 case ACB_ADAPTER_TYPE_A: 1742 devicemap = offsetof(struct HBA_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1743 for (target = 0; target < 4; target++) 1744 { 1745 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1746 devicemap += 4; 1747 } 1748 break; 1749 1750 case ACB_ADAPTER_TYPE_B: 1751 devicemap = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1752 for (target = 0; target < 4; target++) 1753 { 1754 deviceMapCurrent[target]=bus_space_read_4(acb->btag[1], acb->bhandle[1], devicemap); 1755 devicemap += 4; 1756 } 1757 break; 1758 1759 case ACB_ADAPTER_TYPE_C: 1760 devicemap = offsetof(struct HBC_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1761 for (target = 0; target < 4; target++) 1762 { 1763 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1764 devicemap += 4; 1765 } 1766 break; 1767 case ACB_ADAPTER_TYPE_D: 1768 devicemap = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1769 for (target = 0; target < 4; target++) 1770 { 1771 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1772 devicemap += 4; 1773 } 1774 break; 1775 case ACB_ADAPTER_TYPE_E: 1776 devicemap = offsetof(struct HBE_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1777 for (target = 0; target < 4; target++) 1778 { 1779 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1780 devicemap += 4; 1781 } 1782 break; 1783 case ACB_ADAPTER_TYPE_F: 1784 devicemap = ARCMSR_FW_DEVMAP_OFFSET; 1785 for (target = 0; target < 4; target++) 1786 { 1787 deviceMapCurrent[target] = acb->msgcode_rwbuffer[devicemap]; 1788 devicemap += 1; 1789 } 1790 break; 1791 } 1792 1793 if(acb->acb_flags & ACB_F_BUS_HANG_ON) 1794 { 1795 acb->acb_flags &= ~ACB_F_BUS_HANG_ON; 1796 } 1797 /* 1798 ** adapter posted CONFIG message 1799 ** copy the new map, note if there are differences with the current map 1800 */ 1801 pDevMap = (u_int8_t *)&deviceMapCurrent[0]; 1802 for (target = 0; target < ARCMSR_MAX_TARGETID - 1; target++) 1803 { 1804 if (*pDevMap != acb->device_map[target]) 1805 { 1806 u_int8_t difference, bit_check; 1807 1808 difference = *pDevMap ^ acb->device_map[target]; 1809 for(lun=0; lun < ARCMSR_MAX_TARGETLUN; lun++) 1810 { 1811 bit_check = (1 << lun); /*check bit from 0....31*/ 1812 if(difference & bit_check) 1813 { 1814 if(acb->device_map[target] & bit_check) 1815 {/* unit departed */ 1816 printf("arcmsr_dr_handle: Target=%x, lun=%x, GONE!!!\n",target,lun); 1817 arcmsr_abort_dr_ccbs(acb, target, lun); 1818 arcmsr_rescan_lun(acb, target, lun); 1819 acb->devstate[target][lun] = ARECA_RAID_GONE; 1820 } 1821 else 1822 {/* unit arrived */ 1823 printf("arcmsr_dr_handle: Target=%x, lun=%x, Plug-IN!!!\n",target,lun); 1824 arcmsr_rescan_lun(acb, target, lun); 1825 acb->devstate[target][lun] = ARECA_RAID_GOOD; 1826 } 1827 } 1828 } 1829 /* printf("arcmsr_dr_handle: acb->device_map[%x]=0x%x, deviceMapCurrent[%x]=%x\n",target,acb->device_map[target],target,*pDevMap); */ 1830 acb->device_map[target] = *pDevMap; 1831 } 1832 pDevMap++; 1833 } 1834 } 1835 /* 1836 ************************************************************************** 1837 ************************************************************************** 1838 */ 1839 static void arcmsr_hba_message_isr(struct AdapterControlBlock *acb) { 1840 u_int32_t outbound_message; 1841 1842 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT); 1843 outbound_message = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[0]); 1844 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1845 arcmsr_dr_handle( acb ); 1846 } 1847 /* 1848 ************************************************************************** 1849 ************************************************************************** 1850 */ 1851 static void arcmsr_hbb_message_isr(struct AdapterControlBlock *acb) { 1852 u_int32_t outbound_message; 1853 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1854 1855 /* clear interrupts */ 1856 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN); 1857 outbound_message = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0]); 1858 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1859 arcmsr_dr_handle( acb ); 1860 } 1861 /* 1862 ************************************************************************** 1863 ************************************************************************** 1864 */ 1865 static void arcmsr_hbc_message_isr(struct AdapterControlBlock *acb) { 1866 u_int32_t outbound_message; 1867 1868 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR); 1869 outbound_message = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[0]); 1870 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1871 arcmsr_dr_handle( acb ); 1872 } 1873 /* 1874 ************************************************************************** 1875 ************************************************************************** 1876 */ 1877 static void arcmsr_hbd_message_isr(struct AdapterControlBlock *acb) { 1878 u_int32_t outbound_message; 1879 1880 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR); 1881 outbound_message = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[0]); 1882 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1883 arcmsr_dr_handle( acb ); 1884 } 1885 /* 1886 ************************************************************************** 1887 ************************************************************************** 1888 */ 1889 static void arcmsr_hbe_message_isr(struct AdapterControlBlock *acb) { 1890 u_int32_t outbound_message; 1891 1892 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); 1893 if (acb->adapter_type == ACB_ADAPTER_TYPE_E) 1894 outbound_message = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[0]); 1895 else 1896 outbound_message = acb->msgcode_rwbuffer[0]; 1897 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1898 arcmsr_dr_handle( acb ); 1899 } 1900 /* 1901 ************************************************************************** 1902 ************************************************************************** 1903 */ 1904 static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb) 1905 { 1906 u_int32_t doorbell_status; 1907 1908 /* 1909 ******************************************************************* 1910 ** Maybe here we need to check wrqbuffer_lock is lock or not 1911 ** DOORBELL: din! don! 1912 ** check if there are any mail need to pack from firmware 1913 ******************************************************************* 1914 */ 1915 doorbell_status = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell); 1916 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */ 1917 if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) { 1918 arcmsr_iop2drv_data_wrote_handle(acb); 1919 } 1920 if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) { 1921 arcmsr_iop2drv_data_read_handle(acb); 1922 } 1923 } 1924 /* 1925 ************************************************************************** 1926 ************************************************************************** 1927 */ 1928 static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *acb) 1929 { 1930 u_int32_t doorbell_status; 1931 1932 /* 1933 ******************************************************************* 1934 ** Maybe here we need to check wrqbuffer_lock is lock or not 1935 ** DOORBELL: din! don! 1936 ** check if there are any mail need to pack from firmware 1937 ******************************************************************* 1938 */ 1939 doorbell_status = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell); 1940 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, doorbell_status); /* clear doorbell interrupt */ 1941 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) { 1942 arcmsr_iop2drv_data_wrote_handle(acb); 1943 } 1944 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) { 1945 arcmsr_iop2drv_data_read_handle(acb); 1946 } 1947 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 1948 arcmsr_hbc_message_isr(acb); /* messenger of "driver to iop commands" */ 1949 } 1950 } 1951 /* 1952 ************************************************************************** 1953 ************************************************************************** 1954 */ 1955 static void arcmsr_hbd_doorbell_isr(struct AdapterControlBlock *acb) 1956 { 1957 u_int32_t doorbell_status; 1958 1959 /* 1960 ******************************************************************* 1961 ** Maybe here we need to check wrqbuffer_lock is lock or not 1962 ** DOORBELL: din! don! 1963 ** check if there are any mail need to pack from firmware 1964 ******************************************************************* 1965 */ 1966 doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE; 1967 if(doorbell_status) 1968 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */ 1969 while( doorbell_status & ARCMSR_HBDMU_F0_DOORBELL_CAUSE ) { 1970 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK) { 1971 arcmsr_iop2drv_data_wrote_handle(acb); 1972 } 1973 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK) { 1974 arcmsr_iop2drv_data_read_handle(acb); 1975 } 1976 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) { 1977 arcmsr_hbd_message_isr(acb); /* messenger of "driver to iop commands" */ 1978 } 1979 doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE; 1980 if(doorbell_status) 1981 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */ 1982 } 1983 } 1984 /* 1985 ************************************************************************** 1986 ************************************************************************** 1987 */ 1988 static void arcmsr_hbe_doorbell_isr(struct AdapterControlBlock *acb) 1989 { 1990 u_int32_t doorbell_status, in_doorbell; 1991 1992 /* 1993 ******************************************************************* 1994 ** Maybe here we need to check wrqbuffer_lock is lock or not 1995 ** DOORBELL: din! don! 1996 ** check if there are any mail need to pack from firmware 1997 ******************************************************************* 1998 */ 1999 in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell); 2000 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /* clear doorbell interrupt */ 2001 doorbell_status = in_doorbell ^ acb->in_doorbell; 2002 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) { 2003 arcmsr_iop2drv_data_wrote_handle(acb); 2004 } 2005 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK) { 2006 arcmsr_iop2drv_data_read_handle(acb); 2007 } 2008 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) { 2009 arcmsr_hbe_message_isr(acb); /* messenger of "driver to iop commands" */ 2010 } 2011 acb->in_doorbell = in_doorbell; 2012 } 2013 /* 2014 ************************************************************************** 2015 ************************************************************************** 2016 */ 2017 static void arcmsr_hbf_doorbell_isr(struct AdapterControlBlock *acb) 2018 { 2019 u_int32_t doorbell_status, in_doorbell; 2020 2021 /* 2022 ******************************************************************* 2023 ** Maybe here we need to check wrqbuffer_lock is lock or not 2024 ** DOORBELL: din! don! 2025 ** check if there are any mail need to pack from firmware 2026 ******************************************************************* 2027 */ 2028 while(1) { 2029 in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell); 2030 if ((in_doorbell != 0) && (in_doorbell != 0xFFFFFFFF)) 2031 break; 2032 } 2033 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /* clear doorbell interrupt */ 2034 doorbell_status = in_doorbell ^ acb->in_doorbell; 2035 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) { 2036 arcmsr_iop2drv_data_wrote_handle(acb); 2037 } 2038 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK) { 2039 arcmsr_iop2drv_data_read_handle(acb); 2040 } 2041 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) { 2042 arcmsr_hbe_message_isr(acb); /* messenger of "driver to iop commands" */ 2043 } 2044 acb->in_doorbell = in_doorbell; 2045 } 2046 /* 2047 ************************************************************************** 2048 ************************************************************************** 2049 */ 2050 static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb) 2051 { 2052 u_int32_t flag_srb; 2053 u_int16_t error; 2054 2055 /* 2056 ***************************************************************************** 2057 ** areca cdb command done 2058 ***************************************************************************** 2059 */ 2060 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 2061 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2062 while((flag_srb = CHIP_REG_READ32(HBA_MessageUnit, 2063 0, outbound_queueport)) != 0xFFFFFFFF) { 2064 /* check if command done with no error*/ 2065 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0) ? TRUE : FALSE; 2066 arcmsr_drain_donequeue(acb, flag_srb, error); 2067 } /*drain reply FIFO*/ 2068 } 2069 /* 2070 ************************************************************************** 2071 ************************************************************************** 2072 */ 2073 static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb) 2074 { 2075 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 2076 u_int32_t flag_srb; 2077 int index; 2078 u_int16_t error; 2079 2080 /* 2081 ***************************************************************************** 2082 ** areca cdb command done 2083 ***************************************************************************** 2084 */ 2085 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 2086 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2087 index = phbbmu->doneq_index; 2088 while((flag_srb = phbbmu->done_qbuffer[index]) != 0) { 2089 phbbmu->done_qbuffer[index] = 0; 2090 index++; 2091 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 2092 phbbmu->doneq_index = index; 2093 /* check if command done with no error*/ 2094 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 2095 arcmsr_drain_donequeue(acb, flag_srb, error); 2096 } /*drain reply FIFO*/ 2097 } 2098 /* 2099 ************************************************************************** 2100 ************************************************************************** 2101 */ 2102 static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb) 2103 { 2104 u_int32_t flag_srb,throttling = 0; 2105 u_int16_t error; 2106 2107 /* 2108 ***************************************************************************** 2109 ** areca cdb command done 2110 ***************************************************************************** 2111 */ 2112 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2113 do { 2114 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 2115 if (flag_srb == 0xFFFFFFFF) 2116 break; 2117 /* check if command done with no error*/ 2118 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE; 2119 arcmsr_drain_donequeue(acb, flag_srb, error); 2120 throttling++; 2121 if(throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) { 2122 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING); 2123 throttling = 0; 2124 } 2125 } while(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR); 2126 } 2127 /* 2128 ********************************************************************** 2129 ** 2130 ********************************************************************** 2131 */ 2132 static uint16_t arcmsr_get_doneq_index(struct HBD_MessageUnit0 *phbdmu) 2133 { 2134 uint16_t doneq_index, index_stripped; 2135 2136 doneq_index = phbdmu->doneq_index; 2137 if (doneq_index & 0x4000) { 2138 index_stripped = doneq_index & 0xFF; 2139 index_stripped += 1; 2140 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 2141 phbdmu->doneq_index = index_stripped ? 2142 (index_stripped | 0x4000) : index_stripped; 2143 } else { 2144 index_stripped = doneq_index; 2145 index_stripped += 1; 2146 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 2147 phbdmu->doneq_index = index_stripped ? 2148 index_stripped : (index_stripped | 0x4000); 2149 } 2150 return (phbdmu->doneq_index); 2151 } 2152 /* 2153 ************************************************************************** 2154 ************************************************************************** 2155 */ 2156 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb) 2157 { 2158 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 2159 u_int32_t outbound_write_pointer; 2160 u_int32_t addressLow; 2161 uint16_t doneq_index; 2162 u_int16_t error; 2163 /* 2164 ***************************************************************************** 2165 ** areca cdb command done 2166 ***************************************************************************** 2167 */ 2168 if((CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause) & 2169 ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT) == 0) 2170 return; 2171 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 2172 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2173 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 2174 doneq_index = phbdmu->doneq_index; 2175 while ((doneq_index & 0xFF) != (outbound_write_pointer & 0xFF)) { 2176 doneq_index = arcmsr_get_doneq_index(phbdmu); 2177 addressLow = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow; 2178 error = (addressLow & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 2179 arcmsr_drain_donequeue(acb, addressLow, error); /*Check if command done with no error */ 2180 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index); 2181 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 2182 } 2183 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_interrupt_cause, ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR); 2184 CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause); /*Dummy ioread32 to force pci flush */ 2185 } 2186 /* 2187 ************************************************************************** 2188 ************************************************************************** 2189 */ 2190 static void arcmsr_hbe_postqueue_isr(struct AdapterControlBlock *acb) 2191 { 2192 u_int16_t error; 2193 uint32_t doneq_index; 2194 uint16_t cmdSMID; 2195 2196 /* 2197 ***************************************************************************** 2198 ** areca cdb command done 2199 ***************************************************************************** 2200 */ 2201 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2202 doneq_index = acb->doneq_index; 2203 while ((CHIP_REG_READ32(HBE_MessageUnit, 0, reply_post_producer_index) & 0xFFFF) != doneq_index) { 2204 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID; 2205 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 2206 arcmsr_drain_donequeue(acb, (u_int32_t)cmdSMID, error); 2207 doneq_index++; 2208 if (doneq_index >= acb->completionQ_entry) 2209 doneq_index = 0; 2210 } 2211 acb->doneq_index = doneq_index; 2212 CHIP_REG_WRITE32(HBE_MessageUnit, 0, reply_post_consumer_index, doneq_index); 2213 } 2214 2215 static void arcmsr_hbf_postqueue_isr(struct AdapterControlBlock *acb) 2216 { 2217 uint16_t error; 2218 uint32_t doneq_index; 2219 uint16_t cmdSMID; 2220 2221 /* 2222 ***************************************************************************** 2223 ** areca cdb command done 2224 ***************************************************************************** 2225 */ 2226 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2227 doneq_index = acb->doneq_index; 2228 while (1) { 2229 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID; 2230 if (cmdSMID == 0xffff) 2231 break; 2232 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 2233 arcmsr_drain_donequeue(acb, (u_int32_t)cmdSMID, error); 2234 acb->pCompletionQ[doneq_index].cmdSMID = 0xffff; 2235 doneq_index++; 2236 if (doneq_index >= acb->completionQ_entry) 2237 doneq_index = 0; 2238 } 2239 acb->doneq_index = doneq_index; 2240 CHIP_REG_WRITE32(HBF_MessageUnit, 0, reply_post_consumer_index, doneq_index); 2241 } 2242 2243 /* 2244 ********************************************************************** 2245 ********************************************************************** 2246 */ 2247 static void arcmsr_handle_hba_isr( struct AdapterControlBlock *acb) 2248 { 2249 u_int32_t outbound_intStatus; 2250 /* 2251 ********************************************* 2252 ** check outbound intstatus 2253 ********************************************* 2254 */ 2255 outbound_intStatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 2256 if(!outbound_intStatus) { 2257 /*it must be share irq*/ 2258 return; 2259 } 2260 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intStatus); /*clear interrupt*/ 2261 /* MU doorbell interrupts*/ 2262 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) { 2263 arcmsr_hba_doorbell_isr(acb); 2264 } 2265 /* MU post queue interrupts*/ 2266 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) { 2267 arcmsr_hba_postqueue_isr(acb); 2268 } 2269 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { 2270 arcmsr_hba_message_isr(acb); 2271 } 2272 } 2273 /* 2274 ********************************************************************** 2275 ********************************************************************** 2276 */ 2277 static void arcmsr_handle_hbb_isr( struct AdapterControlBlock *acb) 2278 { 2279 u_int32_t outbound_doorbell; 2280 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 2281 /* 2282 ********************************************* 2283 ** check outbound intstatus 2284 ********************************************* 2285 */ 2286 outbound_doorbell = READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & acb->outbound_int_enable; 2287 if(!outbound_doorbell) { 2288 /*it must be share irq*/ 2289 return; 2290 } 2291 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ~outbound_doorbell); /* clear doorbell interrupt */ 2292 READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell); 2293 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 2294 /* MU ioctl transfer doorbell interrupts*/ 2295 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) { 2296 arcmsr_iop2drv_data_wrote_handle(acb); 2297 } 2298 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) { 2299 arcmsr_iop2drv_data_read_handle(acb); 2300 } 2301 /* MU post queue interrupts*/ 2302 if(outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) { 2303 arcmsr_hbb_postqueue_isr(acb); 2304 } 2305 if(outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) { 2306 arcmsr_hbb_message_isr(acb); 2307 } 2308 } 2309 /* 2310 ********************************************************************** 2311 ********************************************************************** 2312 */ 2313 static void arcmsr_handle_hbc_isr( struct AdapterControlBlock *acb) 2314 { 2315 u_int32_t host_interrupt_status; 2316 /* 2317 ********************************************* 2318 ** check outbound intstatus 2319 ********************************************* 2320 */ 2321 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & 2322 (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | 2323 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR); 2324 if(!host_interrupt_status) { 2325 /*it must be share irq*/ 2326 return; 2327 } 2328 do { 2329 /* MU doorbell interrupts*/ 2330 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) { 2331 arcmsr_hbc_doorbell_isr(acb); 2332 } 2333 /* MU post queue interrupts*/ 2334 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) { 2335 arcmsr_hbc_postqueue_isr(acb); 2336 } 2337 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status); 2338 } while (host_interrupt_status & (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR)); 2339 } 2340 /* 2341 ********************************************************************** 2342 ********************************************************************** 2343 */ 2344 static void arcmsr_handle_hbd_isr( struct AdapterControlBlock *acb) 2345 { 2346 u_int32_t host_interrupt_status; 2347 u_int32_t intmask_org; 2348 /* 2349 ********************************************* 2350 ** check outbound intstatus 2351 ********************************************* 2352 */ 2353 host_interrupt_status = CHIP_REG_READ32(HBD_MessageUnit, 0, host_int_status) & acb->outbound_int_enable; 2354 if(!(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_INT)) { 2355 /*it must be share irq*/ 2356 return; 2357 } 2358 /* disable outbound interrupt */ 2359 intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable) ; /* disable outbound message0 int */ 2360 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE); 2361 /* MU doorbell interrupts*/ 2362 if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT) { 2363 arcmsr_hbd_doorbell_isr(acb); 2364 } 2365 /* MU post queue interrupts*/ 2366 if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT) { 2367 arcmsr_hbd_postqueue_isr(acb); 2368 } 2369 /* enable all outbound interrupt */ 2370 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | ARCMSR_HBDMU_ALL_INT_ENABLE); 2371 // CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); 2372 } 2373 /* 2374 ********************************************************************** 2375 ********************************************************************** 2376 */ 2377 static void arcmsr_handle_hbe_isr( struct AdapterControlBlock *acb) 2378 { 2379 u_int32_t host_interrupt_status; 2380 /* 2381 ********************************************* 2382 ** check outbound intstatus 2383 ********************************************* 2384 */ 2385 host_interrupt_status = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_status) & 2386 (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | 2387 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR); 2388 if(!host_interrupt_status) { 2389 /*it must be share irq*/ 2390 return; 2391 } 2392 do { 2393 /* MU doorbell interrupts*/ 2394 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) { 2395 arcmsr_hbe_doorbell_isr(acb); 2396 } 2397 /* MU post queue interrupts*/ 2398 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) { 2399 arcmsr_hbe_postqueue_isr(acb); 2400 } 2401 host_interrupt_status = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_status); 2402 } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR)); 2403 } 2404 2405 static void arcmsr_handle_hbf_isr( struct AdapterControlBlock *acb) 2406 { 2407 u_int32_t host_interrupt_status; 2408 /* 2409 ********************************************* 2410 ** check outbound intstatus 2411 ********************************************* 2412 */ 2413 host_interrupt_status = CHIP_REG_READ32(HBF_MessageUnit, 0, host_int_status) & 2414 (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | 2415 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR); 2416 if(!host_interrupt_status) { 2417 /*it must be share irq*/ 2418 return; 2419 } 2420 do { 2421 /* MU doorbell interrupts*/ 2422 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) { 2423 arcmsr_hbf_doorbell_isr(acb); 2424 } 2425 /* MU post queue interrupts*/ 2426 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) { 2427 arcmsr_hbf_postqueue_isr(acb); 2428 } 2429 host_interrupt_status = CHIP_REG_READ32(HBF_MessageUnit, 0, host_int_status); 2430 } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR)); 2431 } 2432 /* 2433 ****************************************************************************** 2434 ****************************************************************************** 2435 */ 2436 static void arcmsr_interrupt(struct AdapterControlBlock *acb) 2437 { 2438 switch (acb->adapter_type) { 2439 case ACB_ADAPTER_TYPE_A: 2440 arcmsr_handle_hba_isr(acb); 2441 break; 2442 case ACB_ADAPTER_TYPE_B: 2443 arcmsr_handle_hbb_isr(acb); 2444 break; 2445 case ACB_ADAPTER_TYPE_C: 2446 arcmsr_handle_hbc_isr(acb); 2447 break; 2448 case ACB_ADAPTER_TYPE_D: 2449 arcmsr_handle_hbd_isr(acb); 2450 break; 2451 case ACB_ADAPTER_TYPE_E: 2452 arcmsr_handle_hbe_isr(acb); 2453 break; 2454 case ACB_ADAPTER_TYPE_F: 2455 arcmsr_handle_hbf_isr(acb); 2456 break; 2457 default: 2458 printf("arcmsr%d: interrupt service," 2459 " unknown adapter type =%d\n", acb->pci_unit, acb->adapter_type); 2460 break; 2461 } 2462 } 2463 /* 2464 ********************************************************************** 2465 ********************************************************************** 2466 */ 2467 static void arcmsr_intr_handler(void *arg) 2468 { 2469 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg; 2470 2471 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 2472 arcmsr_interrupt(acb); 2473 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 2474 } 2475 /* 2476 ****************************************************************************** 2477 ****************************************************************************** 2478 */ 2479 static void arcmsr_polling_devmap(void *arg) 2480 { 2481 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg; 2482 switch (acb->adapter_type) { 2483 case ACB_ADAPTER_TYPE_A: 2484 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2485 break; 2486 2487 case ACB_ADAPTER_TYPE_B: { 2488 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 2489 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG); 2490 } 2491 break; 2492 2493 case ACB_ADAPTER_TYPE_C: 2494 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2495 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 2496 break; 2497 2498 case ACB_ADAPTER_TYPE_D: 2499 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2500 break; 2501 2502 case ACB_ADAPTER_TYPE_E: 2503 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2504 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 2505 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 2506 break; 2507 2508 case ACB_ADAPTER_TYPE_F: { 2509 u_int32_t outMsg1 = CHIP_REG_READ32(HBF_MessageUnit, 0, outbound_msgaddr1); 2510 if (!(outMsg1 & ARCMSR_HBFMU_MESSAGE_FIRMWARE_OK) || 2511 (outMsg1 & ARCMSR_HBFMU_MESSAGE_NO_VOLUME_CHANGE)) 2512 goto nxt6s; 2513 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2514 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 2515 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 2516 break; 2517 } 2518 } 2519 nxt6s: 2520 if((acb->acb_flags & ACB_F_SCSISTOPADAPTER) == 0) 2521 { 2522 callout_reset(&acb->devmap_callout, 5 * hz, arcmsr_polling_devmap, acb); /* polling per 5 seconds */ 2523 } 2524 } 2525 2526 /* 2527 ******************************************************************************* 2528 ** 2529 ******************************************************************************* 2530 */ 2531 static void arcmsr_iop_parking(struct AdapterControlBlock *acb) 2532 { 2533 u_int32_t intmask_org; 2534 2535 if(acb != NULL) { 2536 /* stop adapter background rebuild */ 2537 if(acb->acb_flags & ACB_F_MSG_START_BGRB) { 2538 intmask_org = arcmsr_disable_allintr(acb); 2539 arcmsr_stop_adapter_bgrb(acb); 2540 arcmsr_flush_adapter_cache(acb); 2541 arcmsr_enable_allintr(acb, intmask_org); 2542 } 2543 } 2544 } 2545 /* 2546 *********************************************************************** 2547 ** 2548 ************************************************************************ 2549 */ 2550 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg) 2551 { 2552 struct CMD_MESSAGE_FIELD *pcmdmessagefld; 2553 u_int32_t retvalue = EINVAL; 2554 2555 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) arg; 2556 if(memcmp(pcmdmessagefld->cmdmessage.Signature, "ARCMSR", 6)!=0) { 2557 return retvalue; 2558 } 2559 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2560 switch(ioctl_cmd) { 2561 case ARCMSR_MESSAGE_READ_RQBUFFER: { 2562 u_int8_t *pQbuffer; 2563 u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer; 2564 u_int32_t allxfer_len=0; 2565 2566 while((acb->rqbuf_firstindex != acb->rqbuf_lastindex) 2567 && (allxfer_len < 1031)) { 2568 /*copy READ QBUFFER to srb*/ 2569 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex]; 2570 *ptmpQbuffer = *pQbuffer; 2571 acb->rqbuf_firstindex++; 2572 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 2573 /*if last index number set it to 0 */ 2574 ptmpQbuffer++; 2575 allxfer_len++; 2576 } 2577 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2578 struct QBUFFER *prbuffer; 2579 2580 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2581 prbuffer = arcmsr_get_iop_rqbuffer(acb); 2582 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 2583 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 2584 } 2585 pcmdmessagefld->cmdmessage.Length = allxfer_len; 2586 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2587 retvalue = ARCMSR_MESSAGE_SUCCESS; 2588 } 2589 break; 2590 case ARCMSR_MESSAGE_WRITE_WQBUFFER: { 2591 u_int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex; 2592 u_int8_t *pQbuffer; 2593 u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer; 2594 2595 user_len = pcmdmessagefld->cmdmessage.Length; 2596 /*check if data xfer length of this request will overflow my array qbuffer */ 2597 wqbuf_lastindex = acb->wqbuf_lastindex; 2598 wqbuf_firstindex = acb->wqbuf_firstindex; 2599 if(wqbuf_lastindex != wqbuf_firstindex) { 2600 arcmsr_Write_data_2iop_wqbuffer(acb); 2601 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2602 } else { 2603 my_empty_len = (wqbuf_firstindex - wqbuf_lastindex - 1) & 2604 (ARCMSR_MAX_QBUFFER - 1); 2605 if(my_empty_len >= user_len) { 2606 while(user_len > 0) { 2607 /*copy srb data to wqbuffer*/ 2608 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex]; 2609 *pQbuffer = *ptmpuserbuffer; 2610 acb->wqbuf_lastindex++; 2611 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 2612 /*if last index number set it to 0 */ 2613 ptmpuserbuffer++; 2614 user_len--; 2615 } 2616 /*post fist Qbuffer*/ 2617 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) { 2618 acb->acb_flags &= ~ACB_F_MESSAGE_WQBUFFER_CLEARED; 2619 arcmsr_Write_data_2iop_wqbuffer(acb); 2620 } 2621 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2622 } else { 2623 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2624 } 2625 } 2626 retvalue = ARCMSR_MESSAGE_SUCCESS; 2627 } 2628 break; 2629 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: { 2630 u_int8_t *pQbuffer = acb->rqbuffer; 2631 2632 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2633 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2634 arcmsr_iop_message_read(acb); 2635 /*signature, let IOP know data has been readed */ 2636 } 2637 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 2638 acb->rqbuf_firstindex = 0; 2639 acb->rqbuf_lastindex = 0; 2640 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2641 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2642 retvalue = ARCMSR_MESSAGE_SUCCESS; 2643 } 2644 break; 2645 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: 2646 { 2647 u_int8_t *pQbuffer = acb->wqbuffer; 2648 2649 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2650 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2651 arcmsr_iop_message_read(acb); 2652 /*signature, let IOP know data has been readed */ 2653 } 2654 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ); 2655 acb->wqbuf_firstindex = 0; 2656 acb->wqbuf_lastindex = 0; 2657 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2658 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2659 retvalue = ARCMSR_MESSAGE_SUCCESS; 2660 } 2661 break; 2662 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: { 2663 u_int8_t *pQbuffer; 2664 2665 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2666 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2667 arcmsr_iop_message_read(acb); 2668 /*signature, let IOP know data has been readed */ 2669 } 2670 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED 2671 |ACB_F_MESSAGE_RQBUFFER_CLEARED 2672 |ACB_F_MESSAGE_WQBUFFER_READ); 2673 acb->rqbuf_firstindex = 0; 2674 acb->rqbuf_lastindex = 0; 2675 acb->wqbuf_firstindex = 0; 2676 acb->wqbuf_lastindex = 0; 2677 pQbuffer = acb->rqbuffer; 2678 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 2679 pQbuffer = acb->wqbuffer; 2680 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 2681 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2682 retvalue = ARCMSR_MESSAGE_SUCCESS; 2683 } 2684 break; 2685 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: { 2686 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F; 2687 retvalue = ARCMSR_MESSAGE_SUCCESS; 2688 } 2689 break; 2690 case ARCMSR_MESSAGE_SAY_HELLO: { 2691 u_int8_t *hello_string = "Hello! I am ARCMSR"; 2692 u_int8_t *puserbuffer = (u_int8_t *)pcmdmessagefld->messagedatabuffer; 2693 2694 if(memcpy(puserbuffer, hello_string, (int16_t)strlen(hello_string))) { 2695 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2696 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2697 return ENOIOCTL; 2698 } 2699 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2700 retvalue = ARCMSR_MESSAGE_SUCCESS; 2701 } 2702 break; 2703 case ARCMSR_MESSAGE_SAY_GOODBYE: { 2704 arcmsr_iop_parking(acb); 2705 retvalue = ARCMSR_MESSAGE_SUCCESS; 2706 } 2707 break; 2708 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: { 2709 arcmsr_flush_adapter_cache(acb); 2710 retvalue = ARCMSR_MESSAGE_SUCCESS; 2711 } 2712 break; 2713 } 2714 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2715 return (retvalue); 2716 } 2717 /* 2718 ************************************************************************** 2719 ************************************************************************** 2720 */ 2721 static void arcmsr_free_srb(struct CommandControlBlock *srb) 2722 { 2723 struct AdapterControlBlock *acb; 2724 2725 acb = srb->acb; 2726 ARCMSR_LOCK_ACQUIRE(&acb->srb_lock); 2727 srb->srb_state = ARCMSR_SRB_DONE; 2728 srb->srb_flags = 0; 2729 acb->srbworkingQ[acb->workingsrb_doneindex] = srb; 2730 acb->workingsrb_doneindex++; 2731 acb->workingsrb_doneindex %= ARCMSR_MAX_FREESRB_NUM; 2732 ARCMSR_LOCK_RELEASE(&acb->srb_lock); 2733 } 2734 /* 2735 ************************************************************************** 2736 ************************************************************************** 2737 */ 2738 static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb) 2739 { 2740 struct CommandControlBlock *srb = NULL; 2741 u_int32_t workingsrb_startindex, workingsrb_doneindex; 2742 2743 ARCMSR_LOCK_ACQUIRE(&acb->srb_lock); 2744 workingsrb_doneindex = acb->workingsrb_doneindex; 2745 workingsrb_startindex = acb->workingsrb_startindex; 2746 srb = acb->srbworkingQ[workingsrb_startindex]; 2747 workingsrb_startindex++; 2748 workingsrb_startindex %= ARCMSR_MAX_FREESRB_NUM; 2749 if(workingsrb_doneindex != workingsrb_startindex) { 2750 acb->workingsrb_startindex = workingsrb_startindex; 2751 } else { 2752 srb = NULL; 2753 } 2754 ARCMSR_LOCK_RELEASE(&acb->srb_lock); 2755 return(srb); 2756 } 2757 /* 2758 ************************************************************************** 2759 ************************************************************************** 2760 */ 2761 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb) 2762 { 2763 struct CMD_MESSAGE_FIELD *pcmdmessagefld; 2764 int retvalue = 0, transfer_len = 0; 2765 char *buffer; 2766 uint8_t *ptr = scsiio_cdb_ptr(&pccb->csio); 2767 u_int32_t controlcode = (u_int32_t ) ptr[5] << 24 | 2768 (u_int32_t ) ptr[6] << 16 | 2769 (u_int32_t ) ptr[7] << 8 | 2770 (u_int32_t ) ptr[8]; 2771 /* 4 bytes: Areca io control code */ 2772 if ((pccb->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_VADDR) { 2773 buffer = pccb->csio.data_ptr; 2774 transfer_len = pccb->csio.dxfer_len; 2775 } else { 2776 retvalue = ARCMSR_MESSAGE_FAIL; 2777 goto message_out; 2778 } 2779 if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) { 2780 retvalue = ARCMSR_MESSAGE_FAIL; 2781 goto message_out; 2782 } 2783 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) buffer; 2784 switch(controlcode) { 2785 case ARCMSR_MESSAGE_READ_RQBUFFER: { 2786 u_int8_t *pQbuffer; 2787 u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer; 2788 int32_t allxfer_len = 0; 2789 2790 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2791 while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex) 2792 && (allxfer_len < 1031)) { 2793 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex]; 2794 *ptmpQbuffer = *pQbuffer; 2795 acb->rqbuf_firstindex++; 2796 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 2797 ptmpQbuffer++; 2798 allxfer_len++; 2799 } 2800 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2801 struct QBUFFER *prbuffer; 2802 2803 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2804 prbuffer = arcmsr_get_iop_rqbuffer(acb); 2805 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 2806 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 2807 } 2808 pcmdmessagefld->cmdmessage.Length = allxfer_len; 2809 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2810 retvalue = ARCMSR_MESSAGE_SUCCESS; 2811 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2812 } 2813 break; 2814 case ARCMSR_MESSAGE_WRITE_WQBUFFER: { 2815 int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex; 2816 u_int8_t *pQbuffer; 2817 u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer; 2818 2819 user_len = pcmdmessagefld->cmdmessage.Length; 2820 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2821 wqbuf_lastindex = acb->wqbuf_lastindex; 2822 wqbuf_firstindex = acb->wqbuf_firstindex; 2823 if (wqbuf_lastindex != wqbuf_firstindex) { 2824 arcmsr_Write_data_2iop_wqbuffer(acb); 2825 /* has error report sensedata */ 2826 if(pccb->csio.sense_len) { 2827 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); 2828 /* Valid,ErrorCode */ 2829 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05; 2830 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */ 2831 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A; 2832 /* AdditionalSenseLength */ 2833 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20; 2834 /* AdditionalSenseCode */ 2835 } 2836 retvalue = ARCMSR_MESSAGE_FAIL; 2837 } else { 2838 my_empty_len = (wqbuf_firstindex-wqbuf_lastindex - 1) 2839 &(ARCMSR_MAX_QBUFFER - 1); 2840 if (my_empty_len >= user_len) { 2841 while (user_len > 0) { 2842 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex]; 2843 *pQbuffer = *ptmpuserbuffer; 2844 acb->wqbuf_lastindex++; 2845 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 2846 ptmpuserbuffer++; 2847 user_len--; 2848 } 2849 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) { 2850 acb->acb_flags &= 2851 ~ACB_F_MESSAGE_WQBUFFER_CLEARED; 2852 arcmsr_Write_data_2iop_wqbuffer(acb); 2853 } 2854 } else { 2855 /* has error report sensedata */ 2856 if(pccb->csio.sense_len) { 2857 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); 2858 /* Valid,ErrorCode */ 2859 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05; 2860 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */ 2861 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A; 2862 /* AdditionalSenseLength */ 2863 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20; 2864 /* AdditionalSenseCode */ 2865 } 2866 retvalue = ARCMSR_MESSAGE_FAIL; 2867 } 2868 } 2869 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2870 } 2871 break; 2872 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: { 2873 u_int8_t *pQbuffer = acb->rqbuffer; 2874 2875 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2876 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2877 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2878 arcmsr_iop_message_read(acb); 2879 } 2880 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 2881 acb->rqbuf_firstindex = 0; 2882 acb->rqbuf_lastindex = 0; 2883 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2884 pcmdmessagefld->cmdmessage.ReturnCode = 2885 ARCMSR_MESSAGE_RETURNCODE_OK; 2886 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2887 } 2888 break; 2889 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: { 2890 u_int8_t *pQbuffer = acb->wqbuffer; 2891 2892 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2893 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2894 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2895 arcmsr_iop_message_read(acb); 2896 } 2897 acb->acb_flags |= 2898 (ACB_F_MESSAGE_WQBUFFER_CLEARED | 2899 ACB_F_MESSAGE_WQBUFFER_READ); 2900 acb->wqbuf_firstindex = 0; 2901 acb->wqbuf_lastindex = 0; 2902 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2903 pcmdmessagefld->cmdmessage.ReturnCode = 2904 ARCMSR_MESSAGE_RETURNCODE_OK; 2905 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2906 } 2907 break; 2908 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: { 2909 u_int8_t *pQbuffer; 2910 2911 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2912 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2913 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2914 arcmsr_iop_message_read(acb); 2915 } 2916 acb->acb_flags |= 2917 (ACB_F_MESSAGE_WQBUFFER_CLEARED 2918 | ACB_F_MESSAGE_RQBUFFER_CLEARED 2919 | ACB_F_MESSAGE_WQBUFFER_READ); 2920 acb->rqbuf_firstindex = 0; 2921 acb->rqbuf_lastindex = 0; 2922 acb->wqbuf_firstindex = 0; 2923 acb->wqbuf_lastindex = 0; 2924 pQbuffer = acb->rqbuffer; 2925 memset(pQbuffer, 0, sizeof (struct QBUFFER)); 2926 pQbuffer = acb->wqbuffer; 2927 memset(pQbuffer, 0, sizeof (struct QBUFFER)); 2928 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2929 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2930 } 2931 break; 2932 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: { 2933 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F; 2934 } 2935 break; 2936 case ARCMSR_MESSAGE_SAY_HELLO: { 2937 int8_t *hello_string = "Hello! I am ARCMSR"; 2938 2939 memcpy(pcmdmessagefld->messagedatabuffer, hello_string 2940 , (int16_t)strlen(hello_string)); 2941 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2942 } 2943 break; 2944 case ARCMSR_MESSAGE_SAY_GOODBYE: 2945 arcmsr_iop_parking(acb); 2946 break; 2947 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: 2948 arcmsr_flush_adapter_cache(acb); 2949 break; 2950 default: 2951 retvalue = ARCMSR_MESSAGE_FAIL; 2952 } 2953 message_out: 2954 return (retvalue); 2955 } 2956 /* 2957 ********************************************************************* 2958 ********************************************************************* 2959 */ 2960 static void arcmsr_execute_srb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 2961 { 2962 struct CommandControlBlock *srb = (struct CommandControlBlock *)arg; 2963 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)srb->acb; 2964 union ccb *pccb; 2965 int target, lun; 2966 2967 pccb = srb->pccb; 2968 target = pccb->ccb_h.target_id; 2969 lun = pccb->ccb_h.target_lun; 2970 acb->pktRequestCount++; 2971 if(error != 0) { 2972 if(error != EFBIG) { 2973 printf("arcmsr%d: unexpected error %x" 2974 " returned from 'bus_dmamap_load' \n" 2975 , acb->pci_unit, error); 2976 } 2977 if((pccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_INPROG) { 2978 pccb->ccb_h.status |= CAM_REQ_TOO_BIG; 2979 } 2980 arcmsr_srb_complete(srb, 0); 2981 return; 2982 } 2983 if(nseg > ARCMSR_MAX_SG_ENTRIES) { 2984 pccb->ccb_h.status |= CAM_REQ_TOO_BIG; 2985 arcmsr_srb_complete(srb, 0); 2986 return; 2987 } 2988 if(acb->acb_flags & ACB_F_BUS_RESET) { 2989 printf("arcmsr%d: bus reset and return busy \n", acb->pci_unit); 2990 pccb->ccb_h.status |= CAM_SCSI_BUS_RESET; 2991 arcmsr_srb_complete(srb, 0); 2992 return; 2993 } 2994 if(acb->devstate[target][lun] == ARECA_RAID_GONE) { 2995 u_int8_t block_cmd, cmd; 2996 2997 cmd = scsiio_cdb_ptr(&pccb->csio)[0]; 2998 block_cmd = cmd & 0x0f; 2999 if(block_cmd == 0x08 || block_cmd == 0x0a) { 3000 printf("arcmsr%d:block 'read/write' command " 3001 "with gone raid volume Cmd=0x%2x, TargetId=%d, Lun=%d \n" 3002 , acb->pci_unit, cmd, target, lun); 3003 pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 3004 arcmsr_srb_complete(srb, 0); 3005 return; 3006 } 3007 } 3008 if((pccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_INPROG) { 3009 if(nseg != 0) { 3010 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap); 3011 } 3012 arcmsr_srb_complete(srb, 0); 3013 return; 3014 } 3015 if(acb->srboutstandingcount >= acb->maxOutstanding) { 3016 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) == 0) 3017 { 3018 xpt_freeze_simq(acb->psim, 1); 3019 acb->acb_flags |= ACB_F_CAM_DEV_QFRZN; 3020 } 3021 pccb->ccb_h.status &= ~CAM_SIM_QUEUED; 3022 pccb->ccb_h.status |= CAM_REQUEUE_REQ; 3023 arcmsr_srb_complete(srb, 0); 3024 return; 3025 } 3026 pccb->ccb_h.status |= CAM_SIM_QUEUED; 3027 arcmsr_build_srb(srb, dm_segs, nseg); 3028 arcmsr_post_srb(acb, srb); 3029 if (pccb->ccb_h.timeout != CAM_TIME_INFINITY) 3030 { 3031 arcmsr_callout_init(&srb->ccb_callout); 3032 callout_reset_sbt(&srb->ccb_callout, SBT_1MS * 3033 (pccb->ccb_h.timeout + (ARCMSR_TIMEOUT_DELAY * 1000)), 0, 3034 arcmsr_srb_timeout, srb, 0); 3035 srb->srb_flags |= SRB_FLAG_TIMER_START; 3036 } 3037 } 3038 /* 3039 ***************************************************************************************** 3040 ***************************************************************************************** 3041 */ 3042 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb) 3043 { 3044 struct CommandControlBlock *srb; 3045 struct AdapterControlBlock *acb = (struct AdapterControlBlock *) abortccb->ccb_h.arcmsr_ccbacb_ptr; 3046 u_int32_t intmask_org; 3047 int i = 0; 3048 3049 acb->num_aborts++; 3050 /* 3051 *************************************************************************** 3052 ** It is the upper layer do abort command this lock just prior to calling us. 3053 ** First determine if we currently own this command. 3054 ** Start by searching the device queue. If not found 3055 ** at all, and the system wanted us to just abort the 3056 ** command return success. 3057 *************************************************************************** 3058 */ 3059 if(acb->srboutstandingcount != 0) { 3060 /* disable all outbound interrupt */ 3061 intmask_org = arcmsr_disable_allintr(acb); 3062 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 3063 srb = acb->psrb_pool[i]; 3064 if(srb->srb_state == ARCMSR_SRB_START) { 3065 if(srb->pccb == abortccb) { 3066 srb->srb_state = ARCMSR_SRB_ABORTED; 3067 printf("arcmsr%d:scsi id=%d lun=%jx abort srb '%p'" 3068 "outstanding command \n" 3069 , acb->pci_unit, abortccb->ccb_h.target_id 3070 , (uintmax_t)abortccb->ccb_h.target_lun, srb); 3071 arcmsr_polling_srbdone(acb, srb); 3072 /* enable outbound Post Queue, outbound doorbell Interrupt */ 3073 arcmsr_enable_allintr(acb, intmask_org); 3074 return (TRUE); 3075 } 3076 } 3077 } 3078 /* enable outbound Post Queue, outbound doorbell Interrupt */ 3079 arcmsr_enable_allintr(acb, intmask_org); 3080 } 3081 return(FALSE); 3082 } 3083 /* 3084 **************************************************************************** 3085 **************************************************************************** 3086 */ 3087 static void arcmsr_bus_reset(struct AdapterControlBlock *acb) 3088 { 3089 int retry = 0; 3090 3091 acb->num_resets++; 3092 acb->acb_flags |= ACB_F_BUS_RESET; 3093 while(acb->srboutstandingcount != 0 && retry < 400) { 3094 arcmsr_interrupt(acb); 3095 UDELAY(25000); 3096 retry++; 3097 } 3098 arcmsr_iop_reset(acb); 3099 acb->acb_flags &= ~ACB_F_BUS_RESET; 3100 } 3101 /* 3102 ************************************************************************** 3103 ************************************************************************** 3104 */ 3105 static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb, 3106 union ccb *pccb) 3107 { 3108 if (pccb->ccb_h.target_lun) { 3109 pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 3110 xpt_done(pccb); 3111 return; 3112 } 3113 pccb->ccb_h.status |= CAM_REQ_CMP; 3114 switch (scsiio_cdb_ptr(&pccb->csio)[0]) { 3115 case INQUIRY: { 3116 unsigned char inqdata[36]; 3117 char *buffer = pccb->csio.data_ptr; 3118 3119 inqdata[0] = T_PROCESSOR; /* Periph Qualifier & Periph Dev Type */ 3120 inqdata[1] = 0; /* rem media bit & Dev Type Modifier */ 3121 inqdata[2] = 0; /* ISO, ECMA, & ANSI versions */ 3122 inqdata[3] = 0; 3123 inqdata[4] = 31; /* length of additional data */ 3124 inqdata[5] = 0; 3125 inqdata[6] = 0; 3126 inqdata[7] = 0; 3127 strncpy(&inqdata[8], "Areca ", 8); /* Vendor Identification */ 3128 strncpy(&inqdata[16], "RAID controller ", 16); /* Product Identification */ 3129 strncpy(&inqdata[32], "R001", 4); /* Product Revision */ 3130 memcpy(buffer, inqdata, sizeof(inqdata)); 3131 xpt_done(pccb); 3132 } 3133 break; 3134 case WRITE_BUFFER: 3135 case READ_BUFFER: { 3136 if (arcmsr_iop_message_xfer(acb, pccb)) { 3137 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 3138 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 3139 } 3140 xpt_done(pccb); 3141 } 3142 break; 3143 default: 3144 xpt_done(pccb); 3145 } 3146 } 3147 /* 3148 ********************************************************************* 3149 ********************************************************************* 3150 */ 3151 static void arcmsr_action(struct cam_sim *psim, union ccb *pccb) 3152 { 3153 struct AdapterControlBlock *acb; 3154 3155 acb = (struct AdapterControlBlock *) cam_sim_softc(psim); 3156 if(acb == NULL) { 3157 pccb->ccb_h.status |= CAM_REQ_INVALID; 3158 xpt_done(pccb); 3159 return; 3160 } 3161 switch (pccb->ccb_h.func_code) { 3162 case XPT_SCSI_IO: { 3163 struct CommandControlBlock *srb; 3164 int target = pccb->ccb_h.target_id; 3165 int error; 3166 3167 if (pccb->ccb_h.flags & CAM_CDB_PHYS) { 3168 pccb->ccb_h.status = CAM_REQ_INVALID; 3169 xpt_done(pccb); 3170 return; 3171 } 3172 3173 if(target == 16) { 3174 /* virtual device for iop message transfer */ 3175 arcmsr_handle_virtual_command(acb, pccb); 3176 return; 3177 } 3178 if((srb = arcmsr_get_freesrb(acb)) == NULL) { 3179 pccb->ccb_h.status |= CAM_RESRC_UNAVAIL; 3180 xpt_done(pccb); 3181 return; 3182 } 3183 pccb->ccb_h.arcmsr_ccbsrb_ptr = srb; 3184 pccb->ccb_h.arcmsr_ccbacb_ptr = acb; 3185 srb->pccb = pccb; 3186 error = bus_dmamap_load_ccb(acb->dm_segs_dmat 3187 , srb->dm_segs_dmamap 3188 , pccb 3189 , arcmsr_execute_srb, srb, /*flags*/0); 3190 if(error == EINPROGRESS) { 3191 xpt_freeze_simq(acb->psim, 1); 3192 pccb->ccb_h.status |= CAM_RELEASE_SIMQ; 3193 } 3194 break; 3195 } 3196 case XPT_PATH_INQ: { 3197 struct ccb_pathinq *cpi = &pccb->cpi; 3198 3199 cpi->version_num = 1; 3200 cpi->hba_inquiry = PI_SDTR_ABLE | PI_TAG_ABLE; 3201 cpi->target_sprt = 0; 3202 cpi->hba_misc = 0; 3203 cpi->hba_eng_cnt = 0; 3204 cpi->max_target = ARCMSR_MAX_TARGETID; /* 0-16 */ 3205 cpi->max_lun = ARCMSR_MAX_TARGETLUN; /* 0-7 */ 3206 cpi->initiator_id = ARCMSR_SCSI_INITIATOR_ID; /* 255 */ 3207 cpi->bus_id = cam_sim_bus(psim); 3208 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 3209 strlcpy(cpi->hba_vid, "ARCMSR", HBA_IDLEN); 3210 strlcpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN); 3211 cpi->unit_number = cam_sim_unit(psim); 3212 if(acb->adapter_bus_speed == ACB_BUS_SPEED_12G) 3213 cpi->base_transfer_speed = 1200000; 3214 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G) 3215 cpi->base_transfer_speed = 600000; 3216 else 3217 cpi->base_transfer_speed = 300000; 3218 if((acb->vendor_device_id == PCIDevVenIDARC1880) || 3219 (acb->vendor_device_id == PCIDevVenIDARC1884) || 3220 (acb->vendor_device_id == PCIDevVenIDARC1680) || 3221 (acb->vendor_device_id == PCIDevVenIDARC1214)) 3222 { 3223 cpi->transport = XPORT_SAS; 3224 cpi->transport_version = 0; 3225 cpi->protocol_version = SCSI_REV_SPC2; 3226 } 3227 else 3228 { 3229 cpi->transport = XPORT_SPI; 3230 cpi->transport_version = 2; 3231 cpi->protocol_version = SCSI_REV_2; 3232 } 3233 cpi->protocol = PROTO_SCSI; 3234 cpi->ccb_h.status |= CAM_REQ_CMP; 3235 xpt_done(pccb); 3236 break; 3237 } 3238 case XPT_ABORT: { 3239 union ccb *pabort_ccb; 3240 3241 pabort_ccb = pccb->cab.abort_ccb; 3242 switch (pabort_ccb->ccb_h.func_code) { 3243 case XPT_ACCEPT_TARGET_IO: 3244 case XPT_CONT_TARGET_IO: 3245 if(arcmsr_seek_cmd2abort(pabort_ccb)==TRUE) { 3246 pabort_ccb->ccb_h.status |= CAM_REQ_ABORTED; 3247 xpt_done(pabort_ccb); 3248 pccb->ccb_h.status |= CAM_REQ_CMP; 3249 } else { 3250 xpt_print_path(pabort_ccb->ccb_h.path); 3251 printf("Not found\n"); 3252 pccb->ccb_h.status |= CAM_PATH_INVALID; 3253 } 3254 break; 3255 case XPT_SCSI_IO: 3256 pccb->ccb_h.status |= CAM_UA_ABORT; 3257 break; 3258 default: 3259 pccb->ccb_h.status |= CAM_REQ_INVALID; 3260 break; 3261 } 3262 xpt_done(pccb); 3263 break; 3264 } 3265 case XPT_RESET_BUS: 3266 case XPT_RESET_DEV: { 3267 u_int32_t i; 3268 3269 arcmsr_bus_reset(acb); 3270 for (i=0; i < 500; i++) { 3271 DELAY(1000); 3272 } 3273 pccb->ccb_h.status |= CAM_REQ_CMP; 3274 xpt_done(pccb); 3275 break; 3276 } 3277 case XPT_TERM_IO: { 3278 pccb->ccb_h.status |= CAM_REQ_INVALID; 3279 xpt_done(pccb); 3280 break; 3281 } 3282 case XPT_GET_TRAN_SETTINGS: { 3283 struct ccb_trans_settings *cts; 3284 3285 if(pccb->ccb_h.target_id == 16) { 3286 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 3287 xpt_done(pccb); 3288 break; 3289 } 3290 cts = &pccb->cts; 3291 { 3292 struct ccb_trans_settings_scsi *scsi; 3293 struct ccb_trans_settings_spi *spi; 3294 struct ccb_trans_settings_sas *sas; 3295 3296 scsi = &cts->proto_specific.scsi; 3297 scsi->flags = CTS_SCSI_FLAGS_TAG_ENB; 3298 scsi->valid = CTS_SCSI_VALID_TQ; 3299 cts->protocol = PROTO_SCSI; 3300 3301 if((acb->vendor_device_id == PCIDevVenIDARC1880) || 3302 (acb->vendor_device_id == PCIDevVenIDARC1884) || 3303 (acb->vendor_device_id == PCIDevVenIDARC1680) || 3304 (acb->vendor_device_id == PCIDevVenIDARC1214)) 3305 { 3306 cts->protocol_version = SCSI_REV_SPC2; 3307 cts->transport_version = 0; 3308 cts->transport = XPORT_SAS; 3309 sas = &cts->xport_specific.sas; 3310 sas->valid = CTS_SAS_VALID_SPEED; 3311 if (acb->adapter_bus_speed == ACB_BUS_SPEED_12G) 3312 sas->bitrate = 1200000; 3313 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G) 3314 sas->bitrate = 600000; 3315 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_3G) 3316 sas->bitrate = 300000; 3317 } 3318 else 3319 { 3320 cts->protocol_version = SCSI_REV_2; 3321 cts->transport_version = 2; 3322 cts->transport = XPORT_SPI; 3323 spi = &cts->xport_specific.spi; 3324 spi->flags = CTS_SPI_FLAGS_DISC_ENB; 3325 if (acb->adapter_bus_speed == ACB_BUS_SPEED_6G) 3326 spi->sync_period = 1; 3327 else 3328 spi->sync_period = 2; 3329 spi->sync_offset = 32; 3330 spi->bus_width = MSG_EXT_WDTR_BUS_16_BIT; 3331 spi->valid = CTS_SPI_VALID_DISC 3332 | CTS_SPI_VALID_SYNC_RATE 3333 | CTS_SPI_VALID_SYNC_OFFSET 3334 | CTS_SPI_VALID_BUS_WIDTH; 3335 } 3336 } 3337 pccb->ccb_h.status |= CAM_REQ_CMP; 3338 xpt_done(pccb); 3339 break; 3340 } 3341 case XPT_SET_TRAN_SETTINGS: { 3342 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 3343 xpt_done(pccb); 3344 break; 3345 } 3346 case XPT_CALC_GEOMETRY: 3347 if(pccb->ccb_h.target_id == 16) { 3348 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 3349 xpt_done(pccb); 3350 break; 3351 } 3352 cam_calc_geometry(&pccb->ccg, 1); 3353 xpt_done(pccb); 3354 break; 3355 default: 3356 pccb->ccb_h.status |= CAM_REQ_INVALID; 3357 xpt_done(pccb); 3358 break; 3359 } 3360 } 3361 /* 3362 ********************************************************************** 3363 ********************************************************************** 3364 */ 3365 static void arcmsr_start_hba_bgrb(struct AdapterControlBlock *acb) 3366 { 3367 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3368 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3369 if(!arcmsr_hba_wait_msgint_ready(acb)) { 3370 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3371 } 3372 } 3373 /* 3374 ********************************************************************** 3375 ********************************************************************** 3376 */ 3377 static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb) 3378 { 3379 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3380 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3381 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_START_BGRB); 3382 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3383 printf( "arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3384 } 3385 } 3386 /* 3387 ********************************************************************** 3388 ********************************************************************** 3389 */ 3390 static void arcmsr_start_hbc_bgrb(struct AdapterControlBlock *acb) 3391 { 3392 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3393 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3394 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3395 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 3396 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3397 } 3398 } 3399 /* 3400 ********************************************************************** 3401 ********************************************************************** 3402 */ 3403 static void arcmsr_start_hbd_bgrb(struct AdapterControlBlock *acb) 3404 { 3405 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3406 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3407 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 3408 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3409 } 3410 } 3411 /* 3412 ********************************************************************** 3413 ********************************************************************** 3414 */ 3415 static void arcmsr_start_hbe_bgrb(struct AdapterControlBlock *acb) 3416 { 3417 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3418 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3419 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 3420 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 3421 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 3422 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3423 } 3424 } 3425 /* 3426 ********************************************************************** 3427 ********************************************************************** 3428 */ 3429 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb) 3430 { 3431 switch (acb->adapter_type) { 3432 case ACB_ADAPTER_TYPE_A: 3433 arcmsr_start_hba_bgrb(acb); 3434 break; 3435 case ACB_ADAPTER_TYPE_B: 3436 arcmsr_start_hbb_bgrb(acb); 3437 break; 3438 case ACB_ADAPTER_TYPE_C: 3439 arcmsr_start_hbc_bgrb(acb); 3440 break; 3441 case ACB_ADAPTER_TYPE_D: 3442 arcmsr_start_hbd_bgrb(acb); 3443 break; 3444 case ACB_ADAPTER_TYPE_E: 3445 case ACB_ADAPTER_TYPE_F: 3446 arcmsr_start_hbe_bgrb(acb); 3447 break; 3448 } 3449 } 3450 /* 3451 ********************************************************************** 3452 ** 3453 ********************************************************************** 3454 */ 3455 static void arcmsr_polling_hba_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3456 { 3457 struct CommandControlBlock *srb; 3458 u_int32_t flag_srb, outbound_intstatus, poll_srb_done=0, poll_count=0; 3459 u_int16_t error; 3460 3461 polling_ccb_retry: 3462 poll_count++; 3463 outbound_intstatus=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 3464 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus); /*clear interrupt*/ 3465 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3466 while(1) { 3467 if((flag_srb = CHIP_REG_READ32(HBA_MessageUnit, 3468 0, outbound_queueport)) == 0xFFFFFFFF) { 3469 if(poll_srb_done) { 3470 break;/*chip FIFO no ccb for completion already*/ 3471 } else { 3472 UDELAY(25000); 3473 if ((poll_count > 100) && (poll_srb != NULL)) { 3474 break; 3475 } 3476 goto polling_ccb_retry; 3477 } 3478 } 3479 /* check if command done with no error*/ 3480 srb = (struct CommandControlBlock *) 3481 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 3482 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 3483 poll_srb_done = (srb == poll_srb) ? 1:0; 3484 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3485 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3486 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'" 3487 "poll command abort successfully \n" 3488 , acb->pci_unit 3489 , srb->pccb->ccb_h.target_id 3490 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3491 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3492 arcmsr_srb_complete(srb, 1); 3493 continue; 3494 } 3495 printf("arcmsr%d: polling get an illegal srb command done srb='%p'" 3496 "srboutstandingcount=%d \n" 3497 , acb->pci_unit 3498 , srb, acb->srboutstandingcount); 3499 continue; 3500 } 3501 arcmsr_report_srb_state(acb, srb, error); 3502 } /*drain reply FIFO*/ 3503 } 3504 /* 3505 ********************************************************************** 3506 ** 3507 ********************************************************************** 3508 */ 3509 static void arcmsr_polling_hbb_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3510 { 3511 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3512 struct CommandControlBlock *srb; 3513 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3514 int index; 3515 u_int16_t error; 3516 3517 polling_ccb_retry: 3518 poll_count++; 3519 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */ 3520 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3521 while(1) { 3522 index = phbbmu->doneq_index; 3523 if((flag_srb = phbbmu->done_qbuffer[index]) == 0) { 3524 if(poll_srb_done) { 3525 break;/*chip FIFO no ccb for completion already*/ 3526 } else { 3527 UDELAY(25000); 3528 if ((poll_count > 100) && (poll_srb != NULL)) { 3529 break; 3530 } 3531 goto polling_ccb_retry; 3532 } 3533 } 3534 phbbmu->done_qbuffer[index] = 0; 3535 index++; 3536 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 3537 phbbmu->doneq_index = index; 3538 /* check if command done with no error*/ 3539 srb = (struct CommandControlBlock *) 3540 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 3541 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 3542 poll_srb_done = (srb == poll_srb) ? 1:0; 3543 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3544 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3545 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'" 3546 "poll command abort successfully \n" 3547 , acb->pci_unit 3548 , srb->pccb->ccb_h.target_id 3549 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3550 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3551 arcmsr_srb_complete(srb, 1); 3552 continue; 3553 } 3554 printf("arcmsr%d: polling get an illegal srb command done srb='%p'" 3555 "srboutstandingcount=%d \n" 3556 , acb->pci_unit 3557 , srb, acb->srboutstandingcount); 3558 continue; 3559 } 3560 arcmsr_report_srb_state(acb, srb, error); 3561 } /*drain reply FIFO*/ 3562 } 3563 /* 3564 ********************************************************************** 3565 ** 3566 ********************************************************************** 3567 */ 3568 static void arcmsr_polling_hbc_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3569 { 3570 struct CommandControlBlock *srb; 3571 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3572 u_int16_t error; 3573 3574 polling_ccb_retry: 3575 poll_count++; 3576 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3577 while(1) { 3578 if(!(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)) { 3579 if(poll_srb_done) { 3580 break;/*chip FIFO no ccb for completion already*/ 3581 } else { 3582 UDELAY(25000); 3583 if ((poll_count > 100) && (poll_srb != NULL)) { 3584 break; 3585 } 3586 if (acb->srboutstandingcount == 0) { 3587 break; 3588 } 3589 goto polling_ccb_retry; 3590 } 3591 } 3592 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 3593 /* check if command done with no error*/ 3594 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/ 3595 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE; 3596 if (poll_srb != NULL) 3597 poll_srb_done = (srb == poll_srb) ? 1:0; 3598 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3599 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3600 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n" 3601 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3602 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3603 arcmsr_srb_complete(srb, 1); 3604 continue; 3605 } 3606 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 3607 , acb->pci_unit, srb, acb->srboutstandingcount); 3608 continue; 3609 } 3610 arcmsr_report_srb_state(acb, srb, error); 3611 } /*drain reply FIFO*/ 3612 } 3613 /* 3614 ********************************************************************** 3615 ** 3616 ********************************************************************** 3617 */ 3618 static void arcmsr_polling_hbd_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3619 { 3620 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 3621 struct CommandControlBlock *srb; 3622 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3623 u_int32_t outbound_write_pointer; 3624 u_int16_t error, doneq_index; 3625 3626 polling_ccb_retry: 3627 poll_count++; 3628 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3629 while(1) { 3630 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 3631 doneq_index = phbdmu->doneq_index; 3632 if ((outbound_write_pointer & 0xFF) == (doneq_index & 0xFF)) { 3633 if(poll_srb_done) { 3634 break;/*chip FIFO no ccb for completion already*/ 3635 } else { 3636 UDELAY(25000); 3637 if ((poll_count > 100) && (poll_srb != NULL)) { 3638 break; 3639 } 3640 if (acb->srboutstandingcount == 0) { 3641 break; 3642 } 3643 goto polling_ccb_retry; 3644 } 3645 } 3646 doneq_index = arcmsr_get_doneq_index(phbdmu); 3647 flag_srb = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow; 3648 /* check if command done with no error*/ 3649 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/ 3650 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 3651 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index); 3652 if (poll_srb != NULL) 3653 poll_srb_done = (srb == poll_srb) ? 1:0; 3654 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3655 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3656 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n" 3657 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3658 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3659 arcmsr_srb_complete(srb, 1); 3660 continue; 3661 } 3662 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 3663 , acb->pci_unit, srb, acb->srboutstandingcount); 3664 continue; 3665 } 3666 arcmsr_report_srb_state(acb, srb, error); 3667 } /*drain reply FIFO*/ 3668 } 3669 /* 3670 ********************************************************************** 3671 ** 3672 ********************************************************************** 3673 */ 3674 static void arcmsr_polling_hbe_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3675 { 3676 struct CommandControlBlock *srb; 3677 u_int32_t poll_srb_done=0, poll_count=0, doneq_index; 3678 u_int16_t error, cmdSMID; 3679 3680 polling_ccb_retry: 3681 poll_count++; 3682 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3683 while(1) { 3684 doneq_index = acb->doneq_index; 3685 if((CHIP_REG_READ32(HBE_MessageUnit, 0, reply_post_producer_index) & 0xFFFF) == doneq_index) { 3686 if(poll_srb_done) { 3687 break;/*chip FIFO no ccb for completion already*/ 3688 } else { 3689 UDELAY(25000); 3690 if ((poll_count > 100) && (poll_srb != NULL)) { 3691 break; 3692 } 3693 if (acb->srboutstandingcount == 0) { 3694 break; 3695 } 3696 goto polling_ccb_retry; 3697 } 3698 } 3699 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID; 3700 doneq_index++; 3701 if (doneq_index >= acb->completionQ_entry) 3702 doneq_index = 0; 3703 acb->doneq_index = doneq_index; 3704 srb = acb->psrb_pool[cmdSMID]; 3705 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 3706 if (poll_srb != NULL) 3707 poll_srb_done = (srb == poll_srb) ? 1:0; 3708 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3709 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3710 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n" 3711 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3712 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3713 arcmsr_srb_complete(srb, 1); 3714 continue; 3715 } 3716 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 3717 , acb->pci_unit, srb, acb->srboutstandingcount); 3718 continue; 3719 } 3720 arcmsr_report_srb_state(acb, srb, error); 3721 } /*drain reply FIFO*/ 3722 CHIP_REG_WRITE32(HBE_MessageUnit, 0, reply_post_producer_index, doneq_index); 3723 } 3724 /* 3725 ********************************************************************** 3726 ********************************************************************** 3727 */ 3728 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3729 { 3730 switch (acb->adapter_type) { 3731 case ACB_ADAPTER_TYPE_A: 3732 arcmsr_polling_hba_srbdone(acb, poll_srb); 3733 break; 3734 case ACB_ADAPTER_TYPE_B: 3735 arcmsr_polling_hbb_srbdone(acb, poll_srb); 3736 break; 3737 case ACB_ADAPTER_TYPE_C: 3738 arcmsr_polling_hbc_srbdone(acb, poll_srb); 3739 break; 3740 case ACB_ADAPTER_TYPE_D: 3741 arcmsr_polling_hbd_srbdone(acb, poll_srb); 3742 break; 3743 case ACB_ADAPTER_TYPE_E: 3744 case ACB_ADAPTER_TYPE_F: 3745 arcmsr_polling_hbe_srbdone(acb, poll_srb); 3746 break; 3747 } 3748 } 3749 /* 3750 ********************************************************************** 3751 ********************************************************************** 3752 */ 3753 static void arcmsr_get_hba_config(struct AdapterControlBlock *acb) 3754 { 3755 char *acb_firm_model = acb->firm_model; 3756 char *acb_firm_version = acb->firm_version; 3757 char *acb_device_map = acb->device_map; 3758 size_t iop_firm_model = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3759 size_t iop_firm_version = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3760 size_t iop_device_map = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3761 int i; 3762 3763 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3764 if(!arcmsr_hba_wait_msgint_ready(acb)) { 3765 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3766 } 3767 i = 0; 3768 while(i < 8) { 3769 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3770 /* 8 bytes firm_model, 15, 60-67*/ 3771 acb_firm_model++; 3772 i++; 3773 } 3774 i=0; 3775 while(i < 16) { 3776 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3777 /* 16 bytes firm_version, 17, 68-83*/ 3778 acb_firm_version++; 3779 i++; 3780 } 3781 i=0; 3782 while(i < 16) { 3783 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3784 acb_device_map++; 3785 i++; 3786 } 3787 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3788 acb->firm_request_len = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3789 acb->firm_numbers_queue = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3790 acb->firm_sdram_size = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3791 acb->firm_ide_channels = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3792 acb->firm_cfg_version = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3793 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 3794 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 3795 else 3796 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3797 } 3798 /* 3799 ********************************************************************** 3800 ********************************************************************** 3801 */ 3802 static void arcmsr_get_hbb_config(struct AdapterControlBlock *acb) 3803 { 3804 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3805 char *acb_firm_model = acb->firm_model; 3806 char *acb_firm_version = acb->firm_version; 3807 char *acb_device_map = acb->device_map; 3808 size_t iop_firm_model = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3809 size_t iop_firm_version = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3810 size_t iop_device_map = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3811 int i; 3812 3813 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG); 3814 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3815 printf( "arcmsr%d: wait" "'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3816 } 3817 i = 0; 3818 while(i < 8) { 3819 *acb_firm_model = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_model+i); 3820 /* 8 bytes firm_model, 15, 60-67*/ 3821 acb_firm_model++; 3822 i++; 3823 } 3824 i = 0; 3825 while(i < 16) { 3826 *acb_firm_version = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_version+i); 3827 /* 16 bytes firm_version, 17, 68-83*/ 3828 acb_firm_version++; 3829 i++; 3830 } 3831 i = 0; 3832 while(i < 16) { 3833 *acb_device_map = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_device_map+i); 3834 acb_device_map++; 3835 i++; 3836 } 3837 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3838 acb->firm_request_len = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3839 acb->firm_numbers_queue = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3840 acb->firm_sdram_size = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3841 acb->firm_ide_channels = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3842 acb->firm_cfg_version = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3843 if(acb->firm_numbers_queue > ARCMSR_MAX_HBB_POSTQUEUE) 3844 acb->maxOutstanding = ARCMSR_MAX_HBB_POSTQUEUE - 1; 3845 else 3846 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3847 } 3848 /* 3849 ********************************************************************** 3850 ********************************************************************** 3851 */ 3852 static void arcmsr_get_hbc_config(struct AdapterControlBlock *acb) 3853 { 3854 char *acb_firm_model = acb->firm_model; 3855 char *acb_firm_version = acb->firm_version; 3856 char *acb_device_map = acb->device_map; 3857 size_t iop_firm_model = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3858 size_t iop_firm_version = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3859 size_t iop_device_map = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3860 int i; 3861 3862 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3863 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3864 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 3865 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3866 } 3867 i = 0; 3868 while(i < 8) { 3869 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3870 /* 8 bytes firm_model, 15, 60-67*/ 3871 acb_firm_model++; 3872 i++; 3873 } 3874 i = 0; 3875 while(i < 16) { 3876 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3877 /* 16 bytes firm_version, 17, 68-83*/ 3878 acb_firm_version++; 3879 i++; 3880 } 3881 i = 0; 3882 while(i < 16) { 3883 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3884 acb_device_map++; 3885 i++; 3886 } 3887 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3888 acb->firm_request_len = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3889 acb->firm_numbers_queue = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3890 acb->firm_sdram_size = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3891 acb->firm_ide_channels = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3892 acb->firm_cfg_version = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3893 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 3894 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 3895 else 3896 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3897 } 3898 /* 3899 ********************************************************************** 3900 ********************************************************************** 3901 */ 3902 static void arcmsr_get_hbd_config(struct AdapterControlBlock *acb) 3903 { 3904 char *acb_firm_model = acb->firm_model; 3905 char *acb_firm_version = acb->firm_version; 3906 char *acb_device_map = acb->device_map; 3907 size_t iop_firm_model = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3908 size_t iop_firm_version = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3909 size_t iop_device_map = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3910 int i; 3911 3912 if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) 3913 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR); 3914 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3915 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 3916 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3917 } 3918 i = 0; 3919 while(i < 8) { 3920 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3921 /* 8 bytes firm_model, 15, 60-67*/ 3922 acb_firm_model++; 3923 i++; 3924 } 3925 i = 0; 3926 while(i < 16) { 3927 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3928 /* 16 bytes firm_version, 17, 68-83*/ 3929 acb_firm_version++; 3930 i++; 3931 } 3932 i = 0; 3933 while(i < 16) { 3934 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3935 acb_device_map++; 3936 i++; 3937 } 3938 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3939 acb->firm_request_len = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3940 acb->firm_numbers_queue = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3941 acb->firm_sdram_size = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3942 acb->firm_ide_channels = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3943 acb->firm_cfg_version = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3944 if(acb->firm_numbers_queue > ARCMSR_MAX_HBD_POSTQUEUE) 3945 acb->maxOutstanding = ARCMSR_MAX_HBD_POSTQUEUE - 1; 3946 else 3947 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3948 } 3949 /* 3950 ********************************************************************** 3951 ********************************************************************** 3952 */ 3953 static void arcmsr_get_hbe_config(struct AdapterControlBlock *acb) 3954 { 3955 char *acb_firm_model = acb->firm_model; 3956 char *acb_firm_version = acb->firm_version; 3957 char *acb_device_map = acb->device_map; 3958 size_t iop_firm_model = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3959 size_t iop_firm_version = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3960 size_t iop_device_map = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3961 int i; 3962 3963 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3964 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 3965 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 3966 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 3967 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3968 } 3969 3970 i = 0; 3971 while(i < 8) { 3972 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3973 /* 8 bytes firm_model, 15, 60-67*/ 3974 acb_firm_model++; 3975 i++; 3976 } 3977 i = 0; 3978 while(i < 16) { 3979 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3980 /* 16 bytes firm_version, 17, 68-83*/ 3981 acb_firm_version++; 3982 i++; 3983 } 3984 i = 0; 3985 while(i < 16) { 3986 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3987 acb_device_map++; 3988 i++; 3989 } 3990 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3991 acb->firm_request_len = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3992 acb->firm_numbers_queue = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3993 acb->firm_sdram_size = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3994 acb->firm_ide_channels = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3995 acb->firm_cfg_version = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3996 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 3997 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 3998 else 3999 acb->maxOutstanding = acb->firm_numbers_queue - 1; 4000 } 4001 /* 4002 ********************************************************************** 4003 ********************************************************************** 4004 */ 4005 static void arcmsr_get_hbf_config(struct AdapterControlBlock *acb) 4006 { 4007 u_int32_t *acb_firm_model = (u_int32_t *)acb->firm_model; 4008 u_int32_t *acb_firm_version = (u_int32_t *)acb->firm_version; 4009 u_int32_t *acb_device_map = (u_int32_t *)acb->device_map; 4010 size_t iop_firm_model = ARCMSR_FW_MODEL_OFFSET; /*firm_model,15,60-67*/ 4011 size_t iop_firm_version = ARCMSR_FW_VERS_OFFSET; /*firm_version,17,68-83*/ 4012 size_t iop_device_map = ARCMSR_FW_DEVMAP_OFFSET; 4013 int i; 4014 4015 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 4016 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 4017 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 4018 if(!arcmsr_hbe_wait_msgint_ready(acb)) 4019 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 4020 4021 i = 0; 4022 while(i < 2) { 4023 *acb_firm_model = acb->msgcode_rwbuffer[iop_firm_model]; 4024 /* 8 bytes firm_model, 15, 60-67*/ 4025 acb_firm_model++; 4026 iop_firm_model++; 4027 i++; 4028 } 4029 i = 0; 4030 while(i < 4) { 4031 *acb_firm_version = acb->msgcode_rwbuffer[iop_firm_version]; 4032 /* 16 bytes firm_version, 17, 68-83*/ 4033 acb_firm_version++; 4034 iop_firm_version++; 4035 i++; 4036 } 4037 i = 0; 4038 while(i < 4) { 4039 *acb_device_map = acb->msgcode_rwbuffer[iop_device_map]; 4040 acb_device_map++; 4041 iop_device_map++; 4042 i++; 4043 } 4044 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 4045 acb->firm_request_len = acb->msgcode_rwbuffer[1]; /*firm_request_len, 1, 04-07*/ 4046 acb->firm_numbers_queue = acb->msgcode_rwbuffer[2]; /*firm_numbers_queue, 2, 08-11*/ 4047 acb->firm_sdram_size = acb->msgcode_rwbuffer[3]; /*firm_sdram_size, 3, 12-15*/ 4048 acb->firm_ide_channels = acb->msgcode_rwbuffer[4]; /*firm_ide_channels, 4, 16-19*/ 4049 acb->firm_cfg_version = acb->msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]; /*firm_cfg_version, 25*/ 4050 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 4051 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 4052 else 4053 acb->maxOutstanding = acb->firm_numbers_queue - 1; 4054 } 4055 /* 4056 ********************************************************************** 4057 ********************************************************************** 4058 */ 4059 static void arcmsr_get_firmware_spec(struct AdapterControlBlock *acb) 4060 { 4061 switch (acb->adapter_type) { 4062 case ACB_ADAPTER_TYPE_A: 4063 arcmsr_get_hba_config(acb); 4064 break; 4065 case ACB_ADAPTER_TYPE_B: 4066 arcmsr_get_hbb_config(acb); 4067 break; 4068 case ACB_ADAPTER_TYPE_C: 4069 arcmsr_get_hbc_config(acb); 4070 break; 4071 case ACB_ADAPTER_TYPE_D: 4072 arcmsr_get_hbd_config(acb); 4073 break; 4074 case ACB_ADAPTER_TYPE_E: 4075 arcmsr_get_hbe_config(acb); 4076 break; 4077 case ACB_ADAPTER_TYPE_F: 4078 arcmsr_get_hbf_config(acb); 4079 break; 4080 } 4081 } 4082 /* 4083 ********************************************************************** 4084 ********************************************************************** 4085 */ 4086 static void arcmsr_wait_firmware_ready( struct AdapterControlBlock *acb) 4087 { 4088 int timeout=0; 4089 4090 switch (acb->adapter_type) { 4091 case ACB_ADAPTER_TYPE_A: { 4092 while ((CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0) 4093 { 4094 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 4095 { 4096 printf( "arcmsr%d:timed out waiting for firmware \n", acb->pci_unit); 4097 return; 4098 } 4099 UDELAY(15000); /* wait 15 milli-seconds */ 4100 } 4101 } 4102 break; 4103 case ACB_ADAPTER_TYPE_B: { 4104 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4105 while ((READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & ARCMSR_MESSAGE_FIRMWARE_OK) == 0) 4106 { 4107 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 4108 { 4109 printf( "arcmsr%d: timed out waiting for firmware \n", acb->pci_unit); 4110 return; 4111 } 4112 UDELAY(15000); /* wait 15 milli-seconds */ 4113 } 4114 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 4115 } 4116 break; 4117 case ACB_ADAPTER_TYPE_C: { 4118 while ((CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0) 4119 { 4120 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 4121 { 4122 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 4123 return; 4124 } 4125 UDELAY(15000); /* wait 15 milli-seconds */ 4126 } 4127 } 4128 break; 4129 case ACB_ADAPTER_TYPE_D: { 4130 while ((CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK) == 0) 4131 { 4132 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 4133 { 4134 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 4135 return; 4136 } 4137 UDELAY(15000); /* wait 15 milli-seconds */ 4138 } 4139 } 4140 break; 4141 case ACB_ADAPTER_TYPE_E: 4142 case ACB_ADAPTER_TYPE_F: { 4143 while ((CHIP_REG_READ32(HBE_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK) == 0) 4144 { 4145 if (timeout++ > 4000) /* (4000*15)/1000 = 60 sec */ 4146 { 4147 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 4148 return; 4149 } 4150 UDELAY(15000); /* wait 15 milli-seconds */ 4151 } 4152 } 4153 break; 4154 } 4155 } 4156 /* 4157 ********************************************************************** 4158 ********************************************************************** 4159 */ 4160 static void arcmsr_clear_doorbell_queue_buffer( struct AdapterControlBlock *acb) 4161 { 4162 u_int32_t outbound_doorbell; 4163 4164 switch (acb->adapter_type) { 4165 case ACB_ADAPTER_TYPE_A: { 4166 /* empty doorbell Qbuffer if door bell ringed */ 4167 outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell); 4168 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */ 4169 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK); 4170 } 4171 break; 4172 case ACB_ADAPTER_TYPE_B: { 4173 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4174 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN);/*clear interrupt and message state*/ 4175 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK); 4176 /* let IOP know data has been read */ 4177 } 4178 break; 4179 case ACB_ADAPTER_TYPE_C: { 4180 /* empty doorbell Qbuffer if door bell ringed */ 4181 outbound_doorbell = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell); 4182 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell); /*clear doorbell interrupt */ 4183 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK); 4184 CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell_clear); /* Dummy read to force pci flush */ 4185 CHIP_REG_READ32(HBC_MessageUnit, 0, inbound_doorbell); /* Dummy read to force pci flush */ 4186 } 4187 break; 4188 case ACB_ADAPTER_TYPE_D: { 4189 /* empty doorbell Qbuffer if door bell ringed */ 4190 outbound_doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell); 4191 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */ 4192 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ); 4193 } 4194 break; 4195 case ACB_ADAPTER_TYPE_E: 4196 case ACB_ADAPTER_TYPE_F: { 4197 /* empty doorbell Qbuffer if door bell ringed */ 4198 acb->in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell); 4199 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /*clear doorbell interrupt */ 4200 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK; 4201 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 4202 } 4203 break; 4204 } 4205 } 4206 /* 4207 ************************************************************************ 4208 ************************************************************************ 4209 */ 4210 static u_int32_t arcmsr_iop_confirm(struct AdapterControlBlock *acb) 4211 { 4212 unsigned long srb_phyaddr; 4213 u_int32_t srb_phyaddr_hi32; 4214 u_int32_t srb_phyaddr_lo32; 4215 4216 /* 4217 ******************************************************************** 4218 ** here we need to tell iop 331 our freesrb.HighPart 4219 ** if freesrb.HighPart is not zero 4220 ******************************************************************** 4221 */ 4222 srb_phyaddr = (unsigned long) acb->srb_phyaddr.phyaddr; 4223 srb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high; 4224 srb_phyaddr_lo32 = acb->srb_phyaddr.B.phyadd_low; 4225 switch (acb->adapter_type) { 4226 case ACB_ADAPTER_TYPE_A: { 4227 if(srb_phyaddr_hi32 != 0) { 4228 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 4229 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 4230 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4231 if(!arcmsr_hba_wait_msgint_ready(acb)) { 4232 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4233 return FALSE; 4234 } 4235 } 4236 } 4237 break; 4238 /* 4239 *********************************************************************** 4240 ** if adapter type B, set window of "post command Q" 4241 *********************************************************************** 4242 */ 4243 case ACB_ADAPTER_TYPE_B: { 4244 u_int32_t post_queue_phyaddr; 4245 struct HBB_MessageUnit *phbbmu; 4246 4247 phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4248 phbbmu->postq_index = 0; 4249 phbbmu->doneq_index = 0; 4250 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_SET_POST_WINDOW); 4251 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 4252 printf( "arcmsr%d: 'set window of post command Q' timeout\n", acb->pci_unit); 4253 return FALSE; 4254 } 4255 post_queue_phyaddr = srb_phyaddr + ARCMSR_SRBS_POOL_SIZE 4256 + offsetof(struct HBB_MessageUnit, post_qbuffer); 4257 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */ 4258 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1], srb_phyaddr_hi32); /* normal should be zero */ 4259 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ size (256+8)*4 */ 4260 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3], post_queue_phyaddr+1056); /* doneQ size (256+8)*4 */ 4261 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4], 1056); /* srb maxQ size must be --> [(256+8)*4] */ 4262 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_SET_CONFIG); 4263 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 4264 printf( "arcmsr%d: 'set command Q window' timeout \n", acb->pci_unit); 4265 return FALSE; 4266 } 4267 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_START_DRIVER_MODE); 4268 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 4269 printf( "arcmsr%d: 'start diver mode' timeout \n", acb->pci_unit); 4270 return FALSE; 4271 } 4272 } 4273 break; 4274 case ACB_ADAPTER_TYPE_C: { 4275 if(srb_phyaddr_hi32 != 0) { 4276 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 4277 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 4278 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4279 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 4280 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 4281 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4282 return FALSE; 4283 } 4284 } 4285 } 4286 break; 4287 case ACB_ADAPTER_TYPE_D: { 4288 u_int32_t post_queue_phyaddr, done_queue_phyaddr; 4289 struct HBD_MessageUnit0 *phbdmu; 4290 4291 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 4292 phbdmu->postq_index = 0; 4293 phbdmu->doneq_index = 0x40FF; 4294 post_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE 4295 + offsetof(struct HBD_MessageUnit0, post_qbuffer); 4296 done_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE 4297 + offsetof(struct HBD_MessageUnit0, done_qbuffer); 4298 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */ 4299 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 4300 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ base */ 4301 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[3], done_queue_phyaddr); /* doneQ base */ 4302 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[4], 0x100); 4303 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4304 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 4305 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4306 return FALSE; 4307 } 4308 } 4309 break; 4310 case ACB_ADAPTER_TYPE_E: { 4311 u_int32_t cdb_phyaddr_lo32; 4312 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + offsetof(struct CommandControlBlock, arcmsr_cdb); 4313 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 4314 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[1], ARCMSR_SIGNATURE_1884); 4315 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[2], cdb_phyaddr_lo32); 4316 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[3], srb_phyaddr_hi32); 4317 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[4], SRB_SIZE); 4318 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE; 4319 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[5], cdb_phyaddr_lo32); 4320 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[6], srb_phyaddr_hi32); 4321 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[7], COMPLETION_Q_POOL_SIZE); 4322 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4323 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 4324 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 4325 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 4326 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4327 return FALSE; 4328 } 4329 } 4330 break; 4331 case ACB_ADAPTER_TYPE_F: { 4332 u_int32_t cdb_phyaddr_lo32; 4333 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + offsetof(struct CommandControlBlock, arcmsr_cdb); 4334 acb->msgcode_rwbuffer[0] = ARCMSR_SIGNATURE_SET_CONFIG; 4335 acb->msgcode_rwbuffer[1] = ARCMSR_SIGNATURE_1886; 4336 acb->msgcode_rwbuffer[2] = cdb_phyaddr_lo32; 4337 acb->msgcode_rwbuffer[3] = srb_phyaddr_hi32; 4338 acb->msgcode_rwbuffer[4] = SRB_SIZE; 4339 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE; 4340 acb->msgcode_rwbuffer[5] = cdb_phyaddr_lo32; 4341 acb->msgcode_rwbuffer[6] = srb_phyaddr_hi32; 4342 acb->msgcode_rwbuffer[7] = COMPLETION_Q_POOL_SIZE; 4343 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4344 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 4345 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 4346 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 4347 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4348 return FALSE; 4349 } 4350 } 4351 break; 4352 } 4353 return (TRUE); 4354 } 4355 /* 4356 ************************************************************************ 4357 ************************************************************************ 4358 */ 4359 static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb) 4360 { 4361 if (acb->adapter_type == ACB_ADAPTER_TYPE_B) 4362 { 4363 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4364 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_ACTIVE_EOI_MODE); 4365 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 4366 printf( "arcmsr%d: 'iop enable eoi mode' timeout \n", acb->pci_unit); 4367 return; 4368 } 4369 } 4370 } 4371 /* 4372 ********************************************************************** 4373 ********************************************************************** 4374 */ 4375 static void arcmsr_iop_init(struct AdapterControlBlock *acb) 4376 { 4377 u_int32_t intmask_org; 4378 4379 /* disable all outbound interrupt */ 4380 intmask_org = arcmsr_disable_allintr(acb); 4381 arcmsr_wait_firmware_ready(acb); 4382 arcmsr_iop_confirm(acb); 4383 arcmsr_get_firmware_spec(acb); 4384 /*start background rebuild*/ 4385 arcmsr_start_adapter_bgrb(acb); 4386 /* empty doorbell Qbuffer if door bell ringed */ 4387 arcmsr_clear_doorbell_queue_buffer(acb); 4388 arcmsr_enable_eoi_mode(acb); 4389 /* enable outbound Post Queue, outbound doorbell Interrupt */ 4390 arcmsr_enable_allintr(acb, intmask_org); 4391 acb->acb_flags |= ACB_F_IOP_INITED; 4392 } 4393 /* 4394 ********************************************************************** 4395 ********************************************************************** 4396 */ 4397 static void arcmsr_map_free_srb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4398 { 4399 struct AdapterControlBlock *acb = arg; 4400 struct CommandControlBlock *srb_tmp; 4401 u_int32_t i; 4402 unsigned long srb_phyaddr = (unsigned long)segs->ds_addr; 4403 4404 acb->srb_phyaddr.phyaddr = srb_phyaddr; 4405 srb_tmp = (struct CommandControlBlock *)acb->uncacheptr; 4406 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 4407 if(bus_dmamap_create(acb->dm_segs_dmat, 4408 /*flags*/0, &srb_tmp->dm_segs_dmamap) != 0) { 4409 acb->acb_flags |= ACB_F_MAPFREESRB_FAILD; 4410 printf("arcmsr%d:" 4411 " srb dmamap bus_dmamap_create error\n", acb->pci_unit); 4412 return; 4413 } 4414 if((acb->adapter_type == ACB_ADAPTER_TYPE_C) || (acb->adapter_type == ACB_ADAPTER_TYPE_D) 4415 || (acb->adapter_type == ACB_ADAPTER_TYPE_E) || (acb->adapter_type == ACB_ADAPTER_TYPE_F)) 4416 { 4417 srb_tmp->cdb_phyaddr_low = srb_phyaddr; 4418 srb_tmp->cdb_phyaddr_high = (u_int32_t)((srb_phyaddr >> 16) >> 16); 4419 } 4420 else 4421 srb_tmp->cdb_phyaddr_low = srb_phyaddr >> 5; 4422 srb_tmp->acb = acb; 4423 srb_tmp->smid = i << 16; 4424 acb->srbworkingQ[i] = acb->psrb_pool[i] = srb_tmp; 4425 srb_phyaddr = srb_phyaddr + SRB_SIZE; 4426 srb_tmp = (struct CommandControlBlock *)((unsigned long)srb_tmp + SRB_SIZE); 4427 } 4428 if (acb->adapter_type == ACB_ADAPTER_TYPE_E) 4429 acb->pCompletionQ = (pCompletion_Q)srb_tmp; 4430 else if (acb->adapter_type == ACB_ADAPTER_TYPE_F) { 4431 acb->pCompletionQ = (pCompletion_Q)srb_tmp; 4432 acb->completeQ_phys = srb_phyaddr; 4433 memset(acb->pCompletionQ, 0xff, COMPLETION_Q_POOL_SIZE); 4434 acb->message_wbuffer = (u_int32_t *)((unsigned long)acb->pCompletionQ + COMPLETION_Q_POOL_SIZE); 4435 acb->message_rbuffer = (u_int32_t *)((unsigned long)acb->message_wbuffer + 0x100); 4436 acb->msgcode_rwbuffer = (u_int32_t *)((unsigned long)acb->message_wbuffer + 0x200); 4437 memset((void *)acb->message_wbuffer, 0, MESG_RW_BUFFER_SIZE); 4438 } 4439 acb->vir2phy_offset = (unsigned long)srb_tmp - (unsigned long)srb_phyaddr; 4440 } 4441 /* 4442 ************************************************************************ 4443 ************************************************************************ 4444 */ 4445 static void arcmsr_free_resource(struct AdapterControlBlock *acb) 4446 { 4447 /* remove the control device */ 4448 if(acb->ioctl_dev != NULL) { 4449 destroy_dev(acb->ioctl_dev); 4450 } 4451 bus_dmamap_unload(acb->srb_dmat, acb->srb_dmamap); 4452 bus_dmamap_destroy(acb->srb_dmat, acb->srb_dmamap); 4453 bus_dma_tag_destroy(acb->srb_dmat); 4454 bus_dma_tag_destroy(acb->dm_segs_dmat); 4455 bus_dma_tag_destroy(acb->parent_dmat); 4456 } 4457 /* 4458 ************************************************************************ 4459 ************************************************************************ 4460 */ 4461 static void arcmsr_mutex_init(struct AdapterControlBlock *acb) 4462 { 4463 ARCMSR_LOCK_INIT(&acb->isr_lock, "arcmsr isr lock"); 4464 ARCMSR_LOCK_INIT(&acb->srb_lock, "arcmsr srb lock"); 4465 ARCMSR_LOCK_INIT(&acb->postDone_lock, "arcmsr postQ lock"); 4466 ARCMSR_LOCK_INIT(&acb->qbuffer_lock, "arcmsr RW buffer lock"); 4467 } 4468 /* 4469 ************************************************************************ 4470 ************************************************************************ 4471 */ 4472 static void arcmsr_mutex_destroy(struct AdapterControlBlock *acb) 4473 { 4474 ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock); 4475 ARCMSR_LOCK_DESTROY(&acb->postDone_lock); 4476 ARCMSR_LOCK_DESTROY(&acb->srb_lock); 4477 ARCMSR_LOCK_DESTROY(&acb->isr_lock); 4478 } 4479 /* 4480 ************************************************************************ 4481 ************************************************************************ 4482 */ 4483 static u_int32_t arcmsr_initialize(device_t dev) 4484 { 4485 struct AdapterControlBlock *acb = device_get_softc(dev); 4486 u_int16_t pci_command; 4487 int i, j,max_coherent_size; 4488 u_int32_t vendor_dev_id; 4489 4490 vendor_dev_id = pci_get_devid(dev); 4491 acb->vendor_device_id = vendor_dev_id; 4492 acb->sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); 4493 switch (vendor_dev_id) { 4494 case PCIDevVenIDARC1880: 4495 case PCIDevVenIDARC1882: 4496 case PCIDevVenIDARC1213: 4497 case PCIDevVenIDARC1223: { 4498 acb->adapter_type = ACB_ADAPTER_TYPE_C; 4499 if ((acb->sub_device_id == ARECA_SUB_DEV_ID_1883) || 4500 (acb->sub_device_id == ARECA_SUB_DEV_ID_1216) || 4501 (acb->sub_device_id == ARECA_SUB_DEV_ID_1226)) 4502 acb->adapter_bus_speed = ACB_BUS_SPEED_12G; 4503 else 4504 acb->adapter_bus_speed = ACB_BUS_SPEED_6G; 4505 max_coherent_size = ARCMSR_SRBS_POOL_SIZE; 4506 } 4507 break; 4508 case PCIDevVenIDARC1884: 4509 acb->adapter_type = ACB_ADAPTER_TYPE_E; 4510 acb->adapter_bus_speed = ACB_BUS_SPEED_12G; 4511 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + COMPLETION_Q_POOL_SIZE; 4512 acb->completionQ_entry = COMPLETION_Q_POOL_SIZE / sizeof(struct deliver_completeQ); 4513 break; 4514 case PCIDevVenIDARC1886_: 4515 case PCIDevVenIDARC1886: 4516 acb->adapter_type = ACB_ADAPTER_TYPE_F; 4517 acb->adapter_bus_speed = ACB_BUS_SPEED_12G; 4518 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + COMPLETION_Q_POOL_SIZE + MESG_RW_BUFFER_SIZE; 4519 acb->completionQ_entry = COMPLETION_Q_POOL_SIZE / sizeof(struct deliver_completeQ); 4520 break; 4521 case PCIDevVenIDARC1214: { 4522 acb->adapter_type = ACB_ADAPTER_TYPE_D; 4523 acb->adapter_bus_speed = ACB_BUS_SPEED_6G; 4524 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBD_MessageUnit0)); 4525 } 4526 break; 4527 case PCIDevVenIDARC1200: 4528 case PCIDevVenIDARC1201: { 4529 acb->adapter_type = ACB_ADAPTER_TYPE_B; 4530 acb->adapter_bus_speed = ACB_BUS_SPEED_3G; 4531 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit)); 4532 } 4533 break; 4534 case PCIDevVenIDARC1203: { 4535 acb->adapter_type = ACB_ADAPTER_TYPE_B; 4536 acb->adapter_bus_speed = ACB_BUS_SPEED_6G; 4537 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit)); 4538 } 4539 break; 4540 case PCIDevVenIDARC1110: 4541 case PCIDevVenIDARC1120: 4542 case PCIDevVenIDARC1130: 4543 case PCIDevVenIDARC1160: 4544 case PCIDevVenIDARC1170: 4545 case PCIDevVenIDARC1210: 4546 case PCIDevVenIDARC1220: 4547 case PCIDevVenIDARC1230: 4548 case PCIDevVenIDARC1231: 4549 case PCIDevVenIDARC1260: 4550 case PCIDevVenIDARC1261: 4551 case PCIDevVenIDARC1270: 4552 case PCIDevVenIDARC1280: 4553 case PCIDevVenIDARC1212: 4554 case PCIDevVenIDARC1222: 4555 case PCIDevVenIDARC1380: 4556 case PCIDevVenIDARC1381: 4557 case PCIDevVenIDARC1680: 4558 case PCIDevVenIDARC1681: { 4559 acb->adapter_type = ACB_ADAPTER_TYPE_A; 4560 acb->adapter_bus_speed = ACB_BUS_SPEED_3G; 4561 max_coherent_size = ARCMSR_SRBS_POOL_SIZE; 4562 } 4563 break; 4564 default: { 4565 printf("arcmsr%d:" 4566 " unknown RAID adapter type \n", device_get_unit(dev)); 4567 return ENOMEM; 4568 } 4569 } 4570 if(bus_dma_tag_create( /*PCI parent*/ bus_get_dma_tag(dev), 4571 /*alignemnt*/ 1, 4572 /*boundary*/ 0, 4573 /*lowaddr*/ BUS_SPACE_MAXADDR, 4574 /*highaddr*/ BUS_SPACE_MAXADDR, 4575 /*filter*/ NULL, 4576 /*filterarg*/ NULL, 4577 /*maxsize*/ BUS_SPACE_MAXSIZE_32BIT, 4578 /*nsegments*/ BUS_SPACE_UNRESTRICTED, 4579 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4580 /*flags*/ 0, 4581 /*lockfunc*/ NULL, 4582 /*lockarg*/ NULL, 4583 &acb->parent_dmat) != 0) 4584 { 4585 printf("arcmsr%d: parent_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4586 return ENOMEM; 4587 } 4588 4589 /* Create a single tag describing a region large enough to hold all of the s/g lists we will need. */ 4590 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat, 4591 /*alignment*/ 1, 4592 /*boundary*/ 0, 4593 #ifdef PAE 4594 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 4595 #else 4596 /*lowaddr*/ BUS_SPACE_MAXADDR, 4597 #endif 4598 /*highaddr*/ BUS_SPACE_MAXADDR, 4599 /*filter*/ NULL, 4600 /*filterarg*/ NULL, 4601 /*maxsize*/ ARCMSR_MAX_SG_ENTRIES * PAGE_SIZE * ARCMSR_MAX_FREESRB_NUM, 4602 /*nsegments*/ ARCMSR_MAX_SG_ENTRIES, 4603 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4604 /*flags*/ 0, 4605 /*lockfunc*/ busdma_lock_mutex, 4606 /*lockarg*/ &acb->isr_lock, 4607 &acb->dm_segs_dmat) != 0) 4608 { 4609 bus_dma_tag_destroy(acb->parent_dmat); 4610 printf("arcmsr%d: dm_segs_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4611 return ENOMEM; 4612 } 4613 4614 /* DMA tag for our srb structures.... Allocate the freesrb memory */ 4615 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat, 4616 /*alignment*/ 0x20, 4617 /*boundary*/ 0, 4618 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 4619 /*highaddr*/ BUS_SPACE_MAXADDR, 4620 /*filter*/ NULL, 4621 /*filterarg*/ NULL, 4622 /*maxsize*/ max_coherent_size, 4623 /*nsegments*/ 1, 4624 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4625 /*flags*/ 0, 4626 /*lockfunc*/ NULL, 4627 /*lockarg*/ NULL, 4628 &acb->srb_dmat) != 0) 4629 { 4630 bus_dma_tag_destroy(acb->dm_segs_dmat); 4631 bus_dma_tag_destroy(acb->parent_dmat); 4632 printf("arcmsr%d: srb_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4633 return ENXIO; 4634 } 4635 /* Allocation for our srbs */ 4636 if(bus_dmamem_alloc(acb->srb_dmat, (void **)&acb->uncacheptr, BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, &acb->srb_dmamap) != 0) { 4637 bus_dma_tag_destroy(acb->srb_dmat); 4638 bus_dma_tag_destroy(acb->dm_segs_dmat); 4639 bus_dma_tag_destroy(acb->parent_dmat); 4640 printf("arcmsr%d: srb_dmat bus_dmamem_alloc failure!\n", device_get_unit(dev)); 4641 return ENXIO; 4642 } 4643 /* And permanently map them */ 4644 if(bus_dmamap_load(acb->srb_dmat, acb->srb_dmamap, acb->uncacheptr, max_coherent_size, arcmsr_map_free_srb, acb, /*flags*/0)) { 4645 bus_dma_tag_destroy(acb->srb_dmat); 4646 bus_dma_tag_destroy(acb->dm_segs_dmat); 4647 bus_dma_tag_destroy(acb->parent_dmat); 4648 printf("arcmsr%d: srb_dmat bus_dmamap_load failure!\n", device_get_unit(dev)); 4649 return ENXIO; 4650 } 4651 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 4652 pci_command |= PCIM_CMD_BUSMASTEREN; 4653 pci_command |= PCIM_CMD_PERRESPEN; 4654 pci_command |= PCIM_CMD_MWRICEN; 4655 /* Enable Busmaster */ 4656 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 4657 switch(acb->adapter_type) { 4658 case ACB_ADAPTER_TYPE_A: { 4659 u_int32_t rid0 = PCIR_BAR(0); 4660 vm_offset_t mem_base0; 4661 4662 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev,SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4663 if(acb->sys_res_arcmsr[0] == NULL) { 4664 arcmsr_free_resource(acb); 4665 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4666 return ENOMEM; 4667 } 4668 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4669 arcmsr_free_resource(acb); 4670 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4671 return ENXIO; 4672 } 4673 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4674 if(mem_base0 == 0) { 4675 arcmsr_free_resource(acb); 4676 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4677 return ENXIO; 4678 } 4679 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4680 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4681 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4682 acb->rid[0] = rid0; 4683 } 4684 break; 4685 case ACB_ADAPTER_TYPE_B: { 4686 struct HBB_MessageUnit *phbbmu; 4687 struct CommandControlBlock *freesrb; 4688 u_int32_t rid[]={ PCIR_BAR(0), PCIR_BAR(2) }; 4689 vm_offset_t mem_base[]={0,0}; 4690 for(i=0; i < 2; i++) { 4691 acb->sys_res_arcmsr[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid[i], RF_ACTIVE); 4692 if(acb->sys_res_arcmsr[i] == NULL) { 4693 arcmsr_free_resource(acb); 4694 printf("arcmsr%d: bus_alloc_resource %d failure!\n", device_get_unit(dev), i); 4695 return ENOMEM; 4696 } 4697 if(rman_get_start(acb->sys_res_arcmsr[i]) <= 0) { 4698 arcmsr_free_resource(acb); 4699 printf("arcmsr%d: rman_get_start %d failure!\n", device_get_unit(dev), i); 4700 return ENXIO; 4701 } 4702 mem_base[i] = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[i]); 4703 if(mem_base[i] == 0) { 4704 arcmsr_free_resource(acb); 4705 printf("arcmsr%d: rman_get_virtual %d failure!\n", device_get_unit(dev), i); 4706 return ENXIO; 4707 } 4708 acb->btag[i] = rman_get_bustag(acb->sys_res_arcmsr[i]); 4709 acb->bhandle[i] = rman_get_bushandle(acb->sys_res_arcmsr[i]); 4710 } 4711 freesrb = (struct CommandControlBlock *)acb->uncacheptr; 4712 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)freesrb+ARCMSR_SRBS_POOL_SIZE); 4713 phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4714 phbbmu->hbb_doorbell = (struct HBB_DOORBELL *)mem_base[0]; 4715 phbbmu->hbb_rwbuffer = (struct HBB_RWBUFFER *)mem_base[1]; 4716 if (vendor_dev_id == PCIDevVenIDARC1203) { 4717 phbbmu->drv2iop_doorbell = offsetof(struct HBB_DOORBELL_1203, drv2iop_doorbell); 4718 phbbmu->drv2iop_doorbell_mask = offsetof(struct HBB_DOORBELL_1203, drv2iop_doorbell_mask); 4719 phbbmu->iop2drv_doorbell = offsetof(struct HBB_DOORBELL_1203, iop2drv_doorbell); 4720 phbbmu->iop2drv_doorbell_mask = offsetof(struct HBB_DOORBELL_1203, iop2drv_doorbell_mask); 4721 } else { 4722 phbbmu->drv2iop_doorbell = offsetof(struct HBB_DOORBELL, drv2iop_doorbell); 4723 phbbmu->drv2iop_doorbell_mask = offsetof(struct HBB_DOORBELL, drv2iop_doorbell_mask); 4724 phbbmu->iop2drv_doorbell = offsetof(struct HBB_DOORBELL, iop2drv_doorbell); 4725 phbbmu->iop2drv_doorbell_mask = offsetof(struct HBB_DOORBELL, iop2drv_doorbell_mask); 4726 } 4727 acb->rid[0] = rid[0]; 4728 acb->rid[1] = rid[1]; 4729 } 4730 break; 4731 case ACB_ADAPTER_TYPE_C: { 4732 u_int32_t rid0 = PCIR_BAR(1); 4733 vm_offset_t mem_base0; 4734 4735 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4736 if(acb->sys_res_arcmsr[0] == NULL) { 4737 arcmsr_free_resource(acb); 4738 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4739 return ENOMEM; 4740 } 4741 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4742 arcmsr_free_resource(acb); 4743 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4744 return ENXIO; 4745 } 4746 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4747 if(mem_base0 == 0) { 4748 arcmsr_free_resource(acb); 4749 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4750 return ENXIO; 4751 } 4752 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4753 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4754 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4755 acb->rid[0] = rid0; 4756 } 4757 break; 4758 case ACB_ADAPTER_TYPE_D: { 4759 struct HBD_MessageUnit0 *phbdmu; 4760 u_int32_t rid0 = PCIR_BAR(0); 4761 vm_offset_t mem_base0; 4762 4763 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4764 if(acb->sys_res_arcmsr[0] == NULL) { 4765 arcmsr_free_resource(acb); 4766 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4767 return ENOMEM; 4768 } 4769 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4770 arcmsr_free_resource(acb); 4771 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4772 return ENXIO; 4773 } 4774 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4775 if(mem_base0 == 0) { 4776 arcmsr_free_resource(acb); 4777 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4778 return ENXIO; 4779 } 4780 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4781 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4782 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)acb->uncacheptr+ARCMSR_SRBS_POOL_SIZE); 4783 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 4784 phbdmu->phbdmu = (struct HBD_MessageUnit *)mem_base0; 4785 acb->rid[0] = rid0; 4786 } 4787 break; 4788 case ACB_ADAPTER_TYPE_E: { 4789 u_int32_t rid0 = PCIR_BAR(1); 4790 vm_offset_t mem_base0; 4791 4792 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4793 if(acb->sys_res_arcmsr[0] == NULL) { 4794 arcmsr_free_resource(acb); 4795 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4796 return ENOMEM; 4797 } 4798 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4799 arcmsr_free_resource(acb); 4800 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4801 return ENXIO; 4802 } 4803 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4804 if(mem_base0 == 0) { 4805 arcmsr_free_resource(acb); 4806 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4807 return ENXIO; 4808 } 4809 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4810 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4811 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4812 acb->doneq_index = 0; 4813 acb->in_doorbell = 0; 4814 acb->out_doorbell = 0; 4815 acb->rid[0] = rid0; 4816 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /*clear interrupt*/ 4817 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, ARCMSR_HBEMU_DOORBELL_SYNC); /* synchronize doorbell to 0 */ 4818 } 4819 break; 4820 case ACB_ADAPTER_TYPE_F: { 4821 u_int32_t rid0 = PCIR_BAR(0); 4822 vm_offset_t mem_base0; 4823 unsigned long host_buffer_dma; 4824 4825 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4826 if(acb->sys_res_arcmsr[0] == NULL) { 4827 arcmsr_free_resource(acb); 4828 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4829 return ENOMEM; 4830 } 4831 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4832 arcmsr_free_resource(acb); 4833 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4834 return ENXIO; 4835 } 4836 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4837 if(mem_base0 == 0) { 4838 arcmsr_free_resource(acb); 4839 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4840 return ENXIO; 4841 } 4842 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4843 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4844 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4845 acb->doneq_index = 0; 4846 acb->in_doorbell = 0; 4847 acb->out_doorbell = 0; 4848 acb->rid[0] = rid0; 4849 CHIP_REG_WRITE32(HBF_MessageUnit, 0, host_int_status, 0); /*clear interrupt*/ 4850 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, ARCMSR_HBEMU_DOORBELL_SYNC); /* synchronize doorbell to 0 */ 4851 arcmsr_wait_firmware_ready(acb); 4852 host_buffer_dma = acb->completeQ_phys + COMPLETION_Q_POOL_SIZE; 4853 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, (u_int32_t)(host_buffer_dma | 1)); /* host buffer low addr, bit0:1 all buffer active */ 4854 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr1, (u_int32_t)((host_buffer_dma >> 16) >> 16));/* host buffer high addr */ 4855 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, ARCMSR_HBFMU_DOORBELL_SYNC1); /* set host buffer physical address */ 4856 } 4857 break; 4858 } 4859 if(acb->acb_flags & ACB_F_MAPFREESRB_FAILD) { 4860 arcmsr_free_resource(acb); 4861 printf("arcmsr%d: map free srb failure!\n", device_get_unit(dev)); 4862 return ENXIO; 4863 } 4864 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_RQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ); 4865 acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER; 4866 /* 4867 ******************************************************************** 4868 ** init raid volume state 4869 ******************************************************************** 4870 */ 4871 for(i=0; i < ARCMSR_MAX_TARGETID; i++) { 4872 for(j=0; j < ARCMSR_MAX_TARGETLUN; j++) { 4873 acb->devstate[i][j] = ARECA_RAID_GONE; 4874 } 4875 } 4876 arcmsr_iop_init(acb); 4877 return(0); 4878 } 4879 4880 static int arcmsr_setup_msix(struct AdapterControlBlock *acb) 4881 { 4882 int i; 4883 4884 for (i = 0; i < acb->msix_vectors; i++) { 4885 acb->irq_id[i] = 1 + i; 4886 acb->irqres[i] = bus_alloc_resource_any(acb->pci_dev, 4887 SYS_RES_IRQ, &acb->irq_id[i], RF_ACTIVE); 4888 if (acb->irqres[i] == NULL) { 4889 printf("arcmsr: Can't allocate MSI-X resource\n"); 4890 goto irq_alloc_failed; 4891 } 4892 if (bus_setup_intr(acb->pci_dev, acb->irqres[i], 4893 INTR_MPSAFE | INTR_TYPE_CAM, NULL, arcmsr_intr_handler, 4894 acb, &acb->ih[i])) { 4895 printf("arcmsr: Cannot set up MSI-X interrupt handler\n"); 4896 goto irq_alloc_failed; 4897 } 4898 } 4899 printf("arcmsr: MSI-X INT enabled\n"); 4900 acb->acb_flags |= ACB_F_MSIX_ENABLED; 4901 return TRUE; 4902 4903 irq_alloc_failed: 4904 arcmsr_teardown_intr(acb->pci_dev, acb); 4905 return FALSE; 4906 } 4907 4908 /* 4909 ************************************************************************ 4910 ************************************************************************ 4911 */ 4912 static int arcmsr_attach(device_t dev) 4913 { 4914 struct make_dev_args args; 4915 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 4916 u_int32_t unit=device_get_unit(dev); 4917 struct ccb_setasync csa; 4918 struct cam_devq *devq; /* Device Queue to use for this SIM */ 4919 struct resource *irqres; 4920 4921 if(acb == NULL) { 4922 printf("arcmsr%d: cannot allocate softc\n", unit); 4923 return (ENOMEM); 4924 } 4925 arcmsr_mutex_init(acb); 4926 acb->pci_dev = dev; 4927 acb->pci_unit = unit; 4928 if(arcmsr_initialize(dev)) { 4929 printf("arcmsr%d: initialize failure!\n", unit); 4930 goto initialize_failed; 4931 } 4932 /* After setting up the adapter, map our interrupt */ 4933 acb->msix_vectors = ARCMSR_NUM_MSIX_VECTORS; 4934 if (pci_alloc_msix(dev, &acb->msix_vectors) == 0) { 4935 if (arcmsr_setup_msix(acb) == TRUE) 4936 goto irqx; 4937 } 4938 acb->irq_id[0] = 0; 4939 irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &acb->irq_id[0], RF_SHAREABLE | RF_ACTIVE); 4940 if(irqres == NULL || 4941 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, NULL, arcmsr_intr_handler, acb, &acb->ih[0])) { 4942 printf("arcmsr%d: unable to register interrupt handler!\n", unit); 4943 goto setup_intr_failed; 4944 } 4945 acb->irqres[0] = irqres; 4946 irqx: 4947 /* 4948 * Now let the CAM generic SCSI layer find the SCSI devices on 4949 * the bus * start queue to reset to the idle loop. * 4950 * Create device queue of SIM(s) * (MAX_START_JOB - 1) : 4951 * max_sim_transactions 4952 */ 4953 devq = cam_simq_alloc(acb->maxOutstanding); 4954 if(devq == NULL) { 4955 printf("arcmsr%d: cam_simq_alloc failure!\n", unit); 4956 goto simq_alloc_failed; 4957 } 4958 acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, &acb->isr_lock, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq); 4959 if(acb->psim == NULL) { 4960 printf("arcmsr%d: cam_sim_alloc failure!\n", unit); 4961 goto sim_alloc_failed; 4962 } 4963 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 4964 if(xpt_bus_register(acb->psim, dev, 0) != CAM_SUCCESS) { 4965 printf("arcmsr%d: xpt_bus_register failure!\n", unit); 4966 goto xpt_bus_failed; 4967 } 4968 if(xpt_create_path(&acb->ppath, /* periph */ NULL, cam_sim_path(acb->psim), CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 4969 printf("arcmsr%d: xpt_create_path failure!\n", unit); 4970 goto xpt_path_failed; 4971 } 4972 /* 4973 **************************************************** 4974 */ 4975 memset(&csa, 0, sizeof(csa)); 4976 xpt_setup_ccb(&csa.ccb_h, acb->ppath, /*priority*/5); 4977 csa.ccb_h.func_code = XPT_SASYNC_CB; 4978 csa.event_enable = AC_FOUND_DEVICE|AC_LOST_DEVICE; 4979 csa.callback = arcmsr_async; 4980 csa.callback_arg = acb->psim; 4981 xpt_action((union ccb *)&csa); 4982 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 4983 /* Create the control device. */ 4984 make_dev_args_init(&args); 4985 args.mda_devsw = &arcmsr_cdevsw; 4986 args.mda_uid = UID_ROOT; 4987 args.mda_gid = GID_WHEEL /* GID_OPERATOR */; 4988 args.mda_mode = S_IRUSR | S_IWUSR; 4989 args.mda_si_drv1 = acb; 4990 (void)make_dev_s(&args, &acb->ioctl_dev, "arcmsr%d", unit); 4991 4992 (void)make_dev_alias(acb->ioctl_dev, "arc%d", unit); 4993 arcmsr_callout_init(&acb->devmap_callout); 4994 callout_reset(&acb->devmap_callout, 60 * hz, arcmsr_polling_devmap, acb); 4995 return (0); 4996 xpt_path_failed: 4997 xpt_bus_deregister(cam_sim_path(acb->psim)); 4998 xpt_bus_failed: 4999 cam_sim_free(acb->psim, /* free_simq */ TRUE); 5000 sim_alloc_failed: 5001 cam_simq_free(devq); 5002 simq_alloc_failed: 5003 arcmsr_teardown_intr(dev, acb); 5004 setup_intr_failed: 5005 arcmsr_free_resource(acb); 5006 initialize_failed: 5007 arcmsr_mutex_destroy(acb); 5008 return ENXIO; 5009 } 5010 5011 /* 5012 ************************************************************************ 5013 ************************************************************************ 5014 */ 5015 static int arcmsr_probe(device_t dev) 5016 { 5017 u_int32_t id; 5018 u_int16_t sub_device_id; 5019 static char buf[256]; 5020 char x_type[]={"unknown"}; 5021 char *type; 5022 int raid6 = 1; 5023 5024 if (pci_get_vendor(dev) != PCI_VENDOR_ID_ARECA) { 5025 return (ENXIO); 5026 } 5027 sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); 5028 switch(id = pci_get_devid(dev)) { 5029 case PCIDevVenIDARC1110: 5030 case PCIDevVenIDARC1200: 5031 case PCIDevVenIDARC1201: 5032 case PCIDevVenIDARC1210: 5033 raid6 = 0; 5034 /*FALLTHRU*/ 5035 case PCIDevVenIDARC1120: 5036 case PCIDevVenIDARC1130: 5037 case PCIDevVenIDARC1160: 5038 case PCIDevVenIDARC1170: 5039 case PCIDevVenIDARC1220: 5040 case PCIDevVenIDARC1230: 5041 case PCIDevVenIDARC1231: 5042 case PCIDevVenIDARC1260: 5043 case PCIDevVenIDARC1261: 5044 case PCIDevVenIDARC1270: 5045 case PCIDevVenIDARC1280: 5046 type = "SATA 3G"; 5047 break; 5048 case PCIDevVenIDARC1212: 5049 case PCIDevVenIDARC1222: 5050 case PCIDevVenIDARC1380: 5051 case PCIDevVenIDARC1381: 5052 case PCIDevVenIDARC1680: 5053 case PCIDevVenIDARC1681: 5054 type = "SAS 3G"; 5055 break; 5056 case PCIDevVenIDARC1880: 5057 case PCIDevVenIDARC1882: 5058 case PCIDevVenIDARC1213: 5059 case PCIDevVenIDARC1223: 5060 if ((sub_device_id == ARECA_SUB_DEV_ID_1883) || 5061 (sub_device_id == ARECA_SUB_DEV_ID_1216) || 5062 (sub_device_id == ARECA_SUB_DEV_ID_1226)) 5063 type = "SAS 12G"; 5064 else 5065 type = "SAS 6G"; 5066 break; 5067 case PCIDevVenIDARC1884: 5068 type = "SAS 12G"; 5069 break; 5070 case PCIDevVenIDARC1886_: 5071 case PCIDevVenIDARC1886: 5072 type = "NVME,SAS-12G,SATA-6G"; 5073 break; 5074 case PCIDevVenIDARC1214: 5075 case PCIDevVenIDARC1203: 5076 type = "SATA 6G"; 5077 break; 5078 default: 5079 type = x_type; 5080 raid6 = 0; 5081 break; 5082 } 5083 if(type == x_type) 5084 return(ENXIO); 5085 sprintf(buf, "Areca %s Host Adapter RAID Controller %s\n%s\n", 5086 type, raid6 ? "(RAID6 capable)" : "", ARCMSR_DRIVER_VERSION); 5087 device_set_desc_copy(dev, buf); 5088 return (BUS_PROBE_DEFAULT); 5089 } 5090 /* 5091 ************************************************************************ 5092 ************************************************************************ 5093 */ 5094 static int arcmsr_shutdown(device_t dev) 5095 { 5096 u_int32_t i; 5097 struct CommandControlBlock *srb; 5098 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 5099 5100 /* stop adapter background rebuild */ 5101 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 5102 /* disable all outbound interrupt */ 5103 arcmsr_disable_allintr(acb); 5104 arcmsr_stop_adapter_bgrb(acb); 5105 arcmsr_flush_adapter_cache(acb); 5106 /* abort all outstanding command */ 5107 acb->acb_flags |= ACB_F_SCSISTOPADAPTER; 5108 acb->acb_flags &= ~ACB_F_IOP_INITED; 5109 if(acb->srboutstandingcount != 0) { 5110 /*clear and abort all outbound posted Q*/ 5111 arcmsr_done4abort_postqueue(acb); 5112 /* talk to iop 331 outstanding command aborted*/ 5113 arcmsr_abort_allcmd(acb); 5114 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 5115 srb = acb->psrb_pool[i]; 5116 if(srb->srb_state == ARCMSR_SRB_START) { 5117 srb->srb_state = ARCMSR_SRB_ABORTED; 5118 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 5119 arcmsr_srb_complete(srb, 1); 5120 } 5121 } 5122 } 5123 acb->srboutstandingcount = 0; 5124 acb->workingsrb_doneindex = 0; 5125 acb->workingsrb_startindex = 0; 5126 acb->pktRequestCount = 0; 5127 acb->pktReturnCount = 0; 5128 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 5129 return (0); 5130 } 5131 /* 5132 ************************************************************************ 5133 ************************************************************************ 5134 */ 5135 static void arcmsr_teardown_intr(device_t dev, struct AdapterControlBlock *acb) 5136 { 5137 int i; 5138 5139 if (acb->acb_flags & ACB_F_MSIX_ENABLED) { 5140 for (i = 0; i < acb->msix_vectors; i++) { 5141 if (acb->ih[i]) 5142 bus_teardown_intr(dev, acb->irqres[i], acb->ih[i]); 5143 if (acb->irqres[i] != NULL) 5144 bus_release_resource(dev, SYS_RES_IRQ, 5145 acb->irq_id[i], acb->irqres[i]); 5146 5147 acb->ih[i] = NULL; 5148 } 5149 pci_release_msi(dev); 5150 } else { 5151 if (acb->ih[0]) 5152 bus_teardown_intr(dev, acb->irqres[0], acb->ih[0]); 5153 if (acb->irqres[0] != NULL) 5154 bus_release_resource(dev, SYS_RES_IRQ, 5155 acb->irq_id[0], acb->irqres[0]); 5156 acb->ih[0] = NULL; 5157 } 5158 5159 } 5160 /* 5161 ************************************************************************ 5162 ************************************************************************ 5163 */ 5164 static int arcmsr_detach(device_t dev) 5165 { 5166 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 5167 int i; 5168 5169 callout_stop(&acb->devmap_callout); 5170 arcmsr_teardown_intr(dev, acb); 5171 arcmsr_shutdown(dev); 5172 arcmsr_free_resource(acb); 5173 for(i=0; (acb->sys_res_arcmsr[i]!=NULL) && (i<2); i++) { 5174 bus_release_resource(dev, SYS_RES_MEMORY, acb->rid[i], acb->sys_res_arcmsr[i]); 5175 } 5176 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 5177 xpt_async(AC_LOST_DEVICE, acb->ppath, NULL); 5178 xpt_free_path(acb->ppath); 5179 xpt_bus_deregister(cam_sim_path(acb->psim)); 5180 cam_sim_free(acb->psim, TRUE); 5181 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 5182 arcmsr_mutex_destroy(acb); 5183 return (0); 5184 } 5185 5186 #ifdef ARCMSR_DEBUG1 5187 static void arcmsr_dump_data(struct AdapterControlBlock *acb) 5188 { 5189 if((acb->pktRequestCount - acb->pktReturnCount) == 0) 5190 return; 5191 printf("Command Request Count =0x%x\n",acb->pktRequestCount); 5192 printf("Command Return Count =0x%x\n",acb->pktReturnCount); 5193 printf("Command (Req-Rtn) Count =0x%x\n",(acb->pktRequestCount - acb->pktReturnCount)); 5194 printf("Queued Command Count =0x%x\n",acb->srboutstandingcount); 5195 } 5196 #endif 5197