1 /* 2 ******************************************************************************** 3 ** OS : FreeBSD 4 ** FILE NAME : arcmsr.c 5 ** BY : Erich Chen, Ching Huang 6 ** Description: SCSI RAID Device Driver for 7 ** ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x) 8 ** SATA/SAS RAID HOST Adapter 9 ******************************************************************************** 10 ******************************************************************************** 11 ** 12 ** SPDX-License-Identifier: BSD-3-Clause 13 ** 14 ** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved. 15 ** 16 ** Redistribution and use in source and binary forms, with or without 17 ** modification, are permitted provided that the following conditions 18 ** are met: 19 ** 1. Redistributions of source code must retain the above copyright 20 ** notice, this list of conditions and the following disclaimer. 21 ** 2. Redistributions in binary form must reproduce the above copyright 22 ** notice, this list of conditions and the following disclaimer in the 23 ** documentation and/or other materials provided with the distribution. 24 ** 3. The name of the author may not be used to endorse or promote products 25 ** derived from this software without specific prior written permission. 26 ** 27 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 28 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 29 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 30 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 31 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT 32 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 33 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 34 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 35 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 36 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 37 ******************************************************************************** 38 ** History 39 ** 40 ** REV# DATE NAME DESCRIPTION 41 ** 1.00.00.00 03/31/2004 Erich Chen First release 42 ** 1.20.00.02 11/29/2004 Erich Chen bug fix with arcmsr_bus_reset when PHY error 43 ** 1.20.00.03 04/19/2005 Erich Chen add SATA 24 Ports adapter type support 44 ** clean unused function 45 ** 1.20.00.12 09/12/2005 Erich Chen bug fix with abort command handling, 46 ** firmware version check 47 ** and firmware update notify for hardware bug fix 48 ** handling if none zero high part physical address 49 ** of srb resource 50 ** 1.20.00.13 08/18/2006 Erich Chen remove pending srb and report busy 51 ** add iop message xfer 52 ** with scsi pass-through command 53 ** add new device id of sas raid adapters 54 ** code fit for SPARC64 & PPC 55 ** 1.20.00.14 02/05/2007 Erich Chen bug fix for incorrect ccb_h.status report 56 ** and cause g_vfs_done() read write error 57 ** 1.20.00.15 10/10/2007 Erich Chen support new RAID adapter type ARC120x 58 ** 1.20.00.16 10/10/2009 Erich Chen Bug fix for RAID adapter type ARC120x 59 ** bus_dmamem_alloc() with BUS_DMA_ZERO 60 ** 1.20.00.17 07/15/2010 Ching Huang Added support ARC1880 61 ** report CAM_DEV_NOT_THERE instead of CAM_SEL_TIMEOUT when device failed, 62 ** prevent cam_periph_error removing all LUN devices of one Target id 63 ** for any one LUN device failed 64 ** 1.20.00.18 10/14/2010 Ching Huang Fixed "inquiry data fails comparion at DV1 step" 65 ** 10/25/2010 Ching Huang Fixed bad range input in bus_alloc_resource for ADAPTER_TYPE_B 66 ** 1.20.00.19 11/11/2010 Ching Huang Fixed arcmsr driver prevent arcsas support for Areca SAS HBA ARC13x0 67 ** 1.20.00.20 12/08/2010 Ching Huang Avoid calling atomic_set_int function 68 ** 1.20.00.21 02/08/2011 Ching Huang Implement I/O request timeout 69 ** 02/14/2011 Ching Huang Modified pktRequestCount 70 ** 1.20.00.21 03/03/2011 Ching Huang if a command timeout, then wait its ccb back before free it 71 ** 1.20.00.22 07/04/2011 Ching Huang Fixed multiple MTX panic 72 ** 1.20.00.23 10/28/2011 Ching Huang Added TIMEOUT_DELAY in case of too many HDDs need to start 73 ** 1.20.00.23 11/08/2011 Ching Huang Added report device transfer speed 74 ** 1.20.00.23 01/30/2012 Ching Huang Fixed Request requeued and Retrying command 75 ** 1.20.00.24 06/11/2012 Ching Huang Fixed return sense data condition 76 ** 1.20.00.25 08/17/2012 Ching Huang Fixed hotplug device no function on type A adapter 77 ** 1.20.00.26 12/14/2012 Ching Huang Added support ARC1214,1224,1264,1284 78 ** 1.20.00.27 05/06/2013 Ching Huang Fixed out standing cmd full on ARC-12x4 79 ** 1.20.00.28 09/13/2013 Ching Huang Removed recursive mutex in arcmsr_abort_dr_ccbs 80 ** 1.20.00.29 12/18/2013 Ching Huang Change simq allocation number, support ARC1883 81 ** 1.30.00.00 11/30/2015 Ching Huang Added support ARC1203 82 ** 1.40.00.00 07/11/2017 Ching Huang Added support ARC1884 83 ** 1.40.00.01 10/30/2017 Ching Huang Fixed release memory resource 84 ** 1.50.00.00 09/30/2020 Ching Huang Added support ARC-1886, NVMe/SAS/SATA controller 85 ** 1.50.00.01 02/26/2021 Ching Huang Fixed no action of hot plugging device on type_F adapter 86 ****************************************************************************************** 87 */ 88 89 #include <sys/cdefs.h> 90 __FBSDID("$FreeBSD$"); 91 92 #if 0 93 #define ARCMSR_DEBUG1 1 94 #endif 95 #include <sys/param.h> 96 #include <sys/systm.h> 97 #include <sys/malloc.h> 98 #include <sys/kernel.h> 99 #include <sys/bus.h> 100 #include <sys/queue.h> 101 #include <sys/stat.h> 102 #include <sys/devicestat.h> 103 #include <sys/kthread.h> 104 #include <sys/module.h> 105 #include <sys/proc.h> 106 #include <sys/lock.h> 107 #include <sys/sysctl.h> 108 #include <sys/poll.h> 109 #include <sys/ioccom.h> 110 #include <vm/vm.h> 111 #include <vm/vm_param.h> 112 #include <vm/pmap.h> 113 114 #include <isa/rtc.h> 115 116 #include <machine/bus.h> 117 #include <machine/resource.h> 118 #include <machine/atomic.h> 119 #include <sys/conf.h> 120 #include <sys/rman.h> 121 122 #include <cam/cam.h> 123 #include <cam/cam_ccb.h> 124 #include <cam/cam_sim.h> 125 #include <cam/cam_periph.h> 126 #include <cam/cam_xpt_periph.h> 127 #include <cam/cam_xpt_sim.h> 128 #include <cam/cam_debug.h> 129 #include <cam/scsi/scsi_all.h> 130 #include <cam/scsi/scsi_message.h> 131 /* 132 ************************************************************************** 133 ************************************************************************** 134 */ 135 #include <sys/selinfo.h> 136 #include <sys/mutex.h> 137 #include <sys/endian.h> 138 #include <dev/pci/pcivar.h> 139 #include <dev/pci/pcireg.h> 140 141 #define arcmsr_callout_init(a) callout_init(a, /*mpsafe*/1); 142 143 #define ARCMSR_DRIVER_VERSION "arcmsr version 1.50.00.01 2021-02-26" 144 #include <dev/arcmsr/arcmsr.h> 145 /* 146 ************************************************************************** 147 ************************************************************************** 148 */ 149 static void arcmsr_free_srb(struct CommandControlBlock *srb); 150 static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb); 151 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb); 152 static int arcmsr_probe(device_t dev); 153 static int arcmsr_attach(device_t dev); 154 static int arcmsr_detach(device_t dev); 155 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg); 156 static void arcmsr_iop_parking(struct AdapterControlBlock *acb); 157 static int arcmsr_shutdown(device_t dev); 158 static void arcmsr_interrupt(struct AdapterControlBlock *acb); 159 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb); 160 static void arcmsr_free_resource(struct AdapterControlBlock *acb); 161 static void arcmsr_bus_reset(struct AdapterControlBlock *acb); 162 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb); 163 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb); 164 static void arcmsr_iop_init(struct AdapterControlBlock *acb); 165 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb); 166 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, struct QBUFFER *prbuffer); 167 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb); 168 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb); 169 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag); 170 static void arcmsr_iop_reset(struct AdapterControlBlock *acb); 171 static void arcmsr_report_sense_info(struct CommandControlBlock *srb); 172 static void arcmsr_build_srb(struct CommandControlBlock *srb, bus_dma_segment_t *dm_segs, u_int32_t nseg); 173 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb); 174 static int arcmsr_resume(device_t dev); 175 static int arcmsr_suspend(device_t dev); 176 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb); 177 static void arcmsr_polling_devmap(void *arg); 178 static void arcmsr_srb_timeout(void *arg); 179 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb); 180 static void arcmsr_hbe_postqueue_isr(struct AdapterControlBlock *acb); 181 static void arcmsr_hbf_postqueue_isr(struct AdapterControlBlock *acb); 182 static void arcmsr_teardown_intr(device_t dev, struct AdapterControlBlock *acb); 183 #ifdef ARCMSR_DEBUG1 184 static void arcmsr_dump_data(struct AdapterControlBlock *acb); 185 #endif 186 /* 187 ************************************************************************** 188 ************************************************************************** 189 */ 190 static void UDELAY(u_int32_t us) { DELAY(us); } 191 /* 192 ************************************************************************** 193 ************************************************************************** 194 */ 195 static bus_dmamap_callback_t arcmsr_map_free_srb; 196 static bus_dmamap_callback_t arcmsr_execute_srb; 197 /* 198 ************************************************************************** 199 ************************************************************************** 200 */ 201 static d_open_t arcmsr_open; 202 static d_close_t arcmsr_close; 203 static d_ioctl_t arcmsr_ioctl; 204 205 static device_method_t arcmsr_methods[]={ 206 DEVMETHOD(device_probe, arcmsr_probe), 207 DEVMETHOD(device_attach, arcmsr_attach), 208 DEVMETHOD(device_detach, arcmsr_detach), 209 DEVMETHOD(device_shutdown, arcmsr_shutdown), 210 DEVMETHOD(device_suspend, arcmsr_suspend), 211 DEVMETHOD(device_resume, arcmsr_resume), 212 DEVMETHOD_END 213 }; 214 215 static driver_t arcmsr_driver={ 216 "arcmsr", arcmsr_methods, sizeof(struct AdapterControlBlock) 217 }; 218 219 static devclass_t arcmsr_devclass; 220 DRIVER_MODULE(arcmsr, pci, arcmsr_driver, arcmsr_devclass, 0, 0); 221 MODULE_DEPEND(arcmsr, pci, 1, 1, 1); 222 MODULE_DEPEND(arcmsr, cam, 1, 1, 1); 223 #ifndef BUS_DMA_COHERENT 224 #define BUS_DMA_COHERENT 0x04 /* hint: map memory in a coherent way */ 225 #endif 226 static struct cdevsw arcmsr_cdevsw={ 227 .d_version = D_VERSION, 228 .d_open = arcmsr_open, /* open */ 229 .d_close = arcmsr_close, /* close */ 230 .d_ioctl = arcmsr_ioctl, /* ioctl */ 231 .d_name = "arcmsr", /* name */ 232 }; 233 /* 234 ************************************************************************** 235 ************************************************************************** 236 */ 237 static int arcmsr_open(struct cdev *dev, int flags, int fmt, struct thread *proc) 238 { 239 int unit = dev2unit(dev); 240 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit); 241 242 if (acb == NULL) { 243 return ENXIO; 244 } 245 return (0); 246 } 247 /* 248 ************************************************************************** 249 ************************************************************************** 250 */ 251 static int arcmsr_close(struct cdev *dev, int flags, int fmt, struct thread *proc) 252 { 253 int unit = dev2unit(dev); 254 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit); 255 256 if (acb == NULL) { 257 return ENXIO; 258 } 259 return 0; 260 } 261 /* 262 ************************************************************************** 263 ************************************************************************** 264 */ 265 static int arcmsr_ioctl(struct cdev *dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc) 266 { 267 int unit = dev2unit(dev); 268 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit); 269 270 if (acb == NULL) { 271 return ENXIO; 272 } 273 return (arcmsr_iop_ioctlcmd(acb, ioctl_cmd, arg)); 274 } 275 /* 276 ********************************************************************** 277 ********************************************************************** 278 */ 279 static u_int32_t arcmsr_disable_allintr( struct AdapterControlBlock *acb) 280 { 281 u_int32_t intmask_org = 0; 282 283 switch (acb->adapter_type) { 284 case ACB_ADAPTER_TYPE_A: { 285 /* disable all outbound interrupt */ 286 intmask_org = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intmask); /* disable outbound message0 int */ 287 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE); 288 } 289 break; 290 case ACB_ADAPTER_TYPE_B: { 291 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 292 /* disable all outbound interrupt */ 293 intmask_org = READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask) 294 & (~ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); /* disable outbound message0 int */ 295 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask, 0); /* disable all interrupt */ 296 } 297 break; 298 case ACB_ADAPTER_TYPE_C: { 299 /* disable all outbound interrupt */ 300 intmask_org = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask); /* disable outbound message0 int */ 301 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE); 302 } 303 break; 304 case ACB_ADAPTER_TYPE_D: { 305 /* disable all outbound interrupt */ 306 intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); /* disable outbound message0 int */ 307 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE); 308 } 309 break; 310 case ACB_ADAPTER_TYPE_E: 311 case ACB_ADAPTER_TYPE_F: { 312 /* disable all outbound interrupt */ 313 intmask_org = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_mask); /* disable outbound message0 int */ 314 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_mask, intmask_org | ARCMSR_HBEMU_ALL_INTMASKENABLE); 315 } 316 break; 317 } 318 return (intmask_org); 319 } 320 /* 321 ********************************************************************** 322 ********************************************************************** 323 */ 324 static void arcmsr_enable_allintr( struct AdapterControlBlock *acb, u_int32_t intmask_org) 325 { 326 u_int32_t mask; 327 328 switch (acb->adapter_type) { 329 case ACB_ADAPTER_TYPE_A: { 330 /* enable outbound Post Queue, outbound doorbell Interrupt */ 331 mask = ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE|ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE); 332 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org & mask); 333 acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff; 334 } 335 break; 336 case ACB_ADAPTER_TYPE_B: { 337 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 338 /* enable ARCMSR_IOP2DRV_MESSAGE_CMD_DONE */ 339 mask = (ARCMSR_IOP2DRV_DATA_WRITE_OK|ARCMSR_IOP2DRV_DATA_READ_OK|ARCMSR_IOP2DRV_CDB_DONE|ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); 340 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell_mask, intmask_org | mask); /*1=interrupt enable, 0=interrupt disable*/ 341 acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f; 342 } 343 break; 344 case ACB_ADAPTER_TYPE_C: { 345 /* enable outbound Post Queue, outbound doorbell Interrupt */ 346 mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK); 347 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org & mask); 348 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f; 349 } 350 break; 351 case ACB_ADAPTER_TYPE_D: { 352 /* enable outbound Post Queue, outbound doorbell Interrupt */ 353 mask = ARCMSR_HBDMU_ALL_INT_ENABLE; 354 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | mask); 355 CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); 356 acb->outbound_int_enable = mask; 357 } 358 break; 359 case ACB_ADAPTER_TYPE_E: 360 case ACB_ADAPTER_TYPE_F: { 361 /* enable outbound Post Queue, outbound doorbell Interrupt */ 362 mask = ~(ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR | ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR); 363 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_mask, intmask_org & mask); 364 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f; 365 } 366 break; 367 } 368 } 369 /* 370 ********************************************************************** 371 ********************************************************************** 372 */ 373 static u_int8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb) 374 { 375 u_int32_t Index; 376 u_int8_t Retries = 0x00; 377 378 do { 379 for(Index=0; Index < 100; Index++) { 380 if(CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { 381 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);/*clear interrupt*/ 382 return TRUE; 383 } 384 UDELAY(10000); 385 }/*max 1 seconds*/ 386 }while(Retries++ < 20);/*max 20 sec*/ 387 return (FALSE); 388 } 389 /* 390 ********************************************************************** 391 ********************************************************************** 392 */ 393 static u_int8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb) 394 { 395 u_int32_t Index; 396 u_int8_t Retries = 0x00; 397 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 398 399 do { 400 for(Index=0; Index < 100; Index++) { 401 if(READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) { 402 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt*/ 403 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 404 return TRUE; 405 } 406 UDELAY(10000); 407 }/*max 1 seconds*/ 408 }while(Retries++ < 20);/*max 20 sec*/ 409 return (FALSE); 410 } 411 /* 412 ********************************************************************** 413 ********************************************************************** 414 */ 415 static u_int8_t arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock *acb) 416 { 417 u_int32_t Index; 418 u_int8_t Retries = 0x00; 419 420 do { 421 for(Index=0; Index < 100; Index++) { 422 if(CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 423 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);/*clear interrupt*/ 424 return TRUE; 425 } 426 UDELAY(10000); 427 }/*max 1 seconds*/ 428 }while(Retries++ < 20);/*max 20 sec*/ 429 return (FALSE); 430 } 431 /* 432 ********************************************************************** 433 ********************************************************************** 434 */ 435 static u_int8_t arcmsr_hbd_wait_msgint_ready(struct AdapterControlBlock *acb) 436 { 437 u_int32_t Index; 438 u_int8_t Retries = 0x00; 439 440 do { 441 for(Index=0; Index < 100; Index++) { 442 if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) { 443 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);/*clear interrupt*/ 444 return TRUE; 445 } 446 UDELAY(10000); 447 }/*max 1 seconds*/ 448 }while(Retries++ < 20);/*max 20 sec*/ 449 return (FALSE); 450 } 451 /* 452 ********************************************************************** 453 ********************************************************************** 454 */ 455 static u_int8_t arcmsr_hbe_wait_msgint_ready(struct AdapterControlBlock *acb) 456 { 457 u_int32_t Index, read_doorbell; 458 u_int8_t Retries = 0x00; 459 460 do { 461 for(Index=0; Index < 100; Index++) { 462 read_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell); 463 if((read_doorbell ^ acb->in_doorbell) & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) { 464 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0);/*clear interrupt*/ 465 acb->in_doorbell = read_doorbell; 466 return TRUE; 467 } 468 UDELAY(10000); 469 }/*max 1 seconds*/ 470 }while(Retries++ < 20);/*max 20 sec*/ 471 return (FALSE); 472 } 473 /* 474 ************************************************************************ 475 ************************************************************************ 476 */ 477 static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb) 478 { 479 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 480 481 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 482 do { 483 if(arcmsr_hba_wait_msgint_ready(acb)) { 484 break; 485 } else { 486 retry_count--; 487 } 488 }while(retry_count != 0); 489 } 490 /* 491 ************************************************************************ 492 ************************************************************************ 493 */ 494 static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb) 495 { 496 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 497 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 498 499 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_FLUSH_CACHE); 500 do { 501 if(arcmsr_hbb_wait_msgint_ready(acb)) { 502 break; 503 } else { 504 retry_count--; 505 } 506 }while(retry_count != 0); 507 } 508 /* 509 ************************************************************************ 510 ************************************************************************ 511 */ 512 static void arcmsr_flush_hbc_cache(struct AdapterControlBlock *acb) 513 { 514 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 515 516 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 517 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 518 do { 519 if(arcmsr_hbc_wait_msgint_ready(acb)) { 520 break; 521 } else { 522 retry_count--; 523 } 524 }while(retry_count != 0); 525 } 526 /* 527 ************************************************************************ 528 ************************************************************************ 529 */ 530 static void arcmsr_flush_hbd_cache(struct AdapterControlBlock *acb) 531 { 532 int retry_count = 30; /* enlarge wait flush adapter cache time: 10 minute */ 533 534 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 535 do { 536 if(arcmsr_hbd_wait_msgint_ready(acb)) { 537 break; 538 } else { 539 retry_count--; 540 } 541 }while(retry_count != 0); 542 } 543 /* 544 ************************************************************************ 545 ************************************************************************ 546 */ 547 static void arcmsr_flush_hbe_cache(struct AdapterControlBlock *acb) 548 { 549 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 550 551 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 552 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 553 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 554 do { 555 if(arcmsr_hbe_wait_msgint_ready(acb)) { 556 break; 557 } else { 558 retry_count--; 559 } 560 }while(retry_count != 0); 561 } 562 /* 563 ************************************************************************ 564 ************************************************************************ 565 */ 566 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb) 567 { 568 switch (acb->adapter_type) { 569 case ACB_ADAPTER_TYPE_A: { 570 arcmsr_flush_hba_cache(acb); 571 } 572 break; 573 case ACB_ADAPTER_TYPE_B: { 574 arcmsr_flush_hbb_cache(acb); 575 } 576 break; 577 case ACB_ADAPTER_TYPE_C: { 578 arcmsr_flush_hbc_cache(acb); 579 } 580 break; 581 case ACB_ADAPTER_TYPE_D: { 582 arcmsr_flush_hbd_cache(acb); 583 } 584 break; 585 case ACB_ADAPTER_TYPE_E: 586 case ACB_ADAPTER_TYPE_F: { 587 arcmsr_flush_hbe_cache(acb); 588 } 589 break; 590 } 591 } 592 /* 593 ******************************************************************************* 594 ******************************************************************************* 595 */ 596 static int arcmsr_suspend(device_t dev) 597 { 598 struct AdapterControlBlock *acb = device_get_softc(dev); 599 600 /* flush controller */ 601 arcmsr_iop_parking(acb); 602 /* disable all outbound interrupt */ 603 arcmsr_disable_allintr(acb); 604 return(0); 605 } 606 /* 607 ******************************************************************************* 608 ******************************************************************************* 609 */ 610 static int arcmsr_resume(device_t dev) 611 { 612 struct AdapterControlBlock *acb = device_get_softc(dev); 613 614 arcmsr_iop_init(acb); 615 return(0); 616 } 617 /* 618 ********************************************************************************* 619 ********************************************************************************* 620 */ 621 static void arcmsr_async(void *cb_arg, u_int32_t code, struct cam_path *path, void *arg) 622 { 623 struct AdapterControlBlock *acb; 624 u_int8_t target_id, target_lun; 625 struct cam_sim *sim; 626 627 sim = (struct cam_sim *) cb_arg; 628 acb =(struct AdapterControlBlock *) cam_sim_softc(sim); 629 switch (code) { 630 case AC_LOST_DEVICE: 631 target_id = xpt_path_target_id(path); 632 target_lun = xpt_path_lun_id(path); 633 if((target_id > ARCMSR_MAX_TARGETID) || (target_lun > ARCMSR_MAX_TARGETLUN)) { 634 break; 635 } 636 // printf("%s:scsi id=%d lun=%d device lost \n", device_get_name(acb->pci_dev), target_id, target_lun); 637 break; 638 default: 639 break; 640 } 641 } 642 /* 643 ********************************************************************** 644 ********************************************************************** 645 */ 646 static void arcmsr_report_sense_info(struct CommandControlBlock *srb) 647 { 648 union ccb *pccb = srb->pccb; 649 650 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 651 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 652 if(pccb->csio.sense_len) { 653 memset(&pccb->csio.sense_data, 0, sizeof(pccb->csio.sense_data)); 654 memcpy(&pccb->csio.sense_data, srb->arcmsr_cdb.SenseData, 655 get_min(sizeof(struct SENSE_DATA), sizeof(pccb->csio.sense_data))); 656 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); /* Valid,ErrorCode */ 657 pccb->ccb_h.status |= CAM_AUTOSNS_VALID; 658 } 659 } 660 /* 661 ********************************************************************* 662 ********************************************************************* 663 */ 664 static void arcmsr_abort_hba_allcmd(struct AdapterControlBlock *acb) 665 { 666 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 667 if(!arcmsr_hba_wait_msgint_ready(acb)) { 668 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 669 } 670 } 671 /* 672 ********************************************************************* 673 ********************************************************************* 674 */ 675 static void arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb) 676 { 677 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 678 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_ABORT_CMD); 679 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 680 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 681 } 682 } 683 /* 684 ********************************************************************* 685 ********************************************************************* 686 */ 687 static void arcmsr_abort_hbc_allcmd(struct AdapterControlBlock *acb) 688 { 689 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 690 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 691 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 692 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 693 } 694 } 695 /* 696 ********************************************************************* 697 ********************************************************************* 698 */ 699 static void arcmsr_abort_hbd_allcmd(struct AdapterControlBlock *acb) 700 { 701 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 702 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 703 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 704 } 705 } 706 /* 707 ********************************************************************* 708 ********************************************************************* 709 */ 710 static void arcmsr_abort_hbe_allcmd(struct AdapterControlBlock *acb) 711 { 712 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 713 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 714 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 715 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 716 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 717 } 718 } 719 /* 720 ********************************************************************* 721 ********************************************************************* 722 */ 723 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb) 724 { 725 switch (acb->adapter_type) { 726 case ACB_ADAPTER_TYPE_A: { 727 arcmsr_abort_hba_allcmd(acb); 728 } 729 break; 730 case ACB_ADAPTER_TYPE_B: { 731 arcmsr_abort_hbb_allcmd(acb); 732 } 733 break; 734 case ACB_ADAPTER_TYPE_C: { 735 arcmsr_abort_hbc_allcmd(acb); 736 } 737 break; 738 case ACB_ADAPTER_TYPE_D: { 739 arcmsr_abort_hbd_allcmd(acb); 740 } 741 break; 742 case ACB_ADAPTER_TYPE_E: 743 case ACB_ADAPTER_TYPE_F: { 744 arcmsr_abort_hbe_allcmd(acb); 745 } 746 break; 747 } 748 } 749 /* 750 ********************************************************************** 751 ********************************************************************** 752 */ 753 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag) 754 { 755 struct AdapterControlBlock *acb = srb->acb; 756 union ccb *pccb = srb->pccb; 757 758 if(srb->srb_flags & SRB_FLAG_TIMER_START) 759 callout_stop(&srb->ccb_callout); 760 if((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 761 bus_dmasync_op_t op; 762 763 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 764 op = BUS_DMASYNC_POSTREAD; 765 } else { 766 op = BUS_DMASYNC_POSTWRITE; 767 } 768 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op); 769 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap); 770 } 771 if(stand_flag == 1) { 772 atomic_subtract_int(&acb->srboutstandingcount, 1); 773 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) && ( 774 acb->srboutstandingcount < (acb->maxOutstanding -10))) { 775 acb->acb_flags &= ~ACB_F_CAM_DEV_QFRZN; 776 pccb->ccb_h.status |= CAM_RELEASE_SIMQ; 777 } 778 } 779 if(srb->srb_state != ARCMSR_SRB_TIMEOUT) 780 arcmsr_free_srb(srb); 781 acb->pktReturnCount++; 782 xpt_done(pccb); 783 } 784 /* 785 ************************************************************************** 786 ************************************************************************** 787 */ 788 static void arcmsr_report_srb_state(struct AdapterControlBlock *acb, struct CommandControlBlock *srb, u_int16_t error) 789 { 790 int target, lun; 791 792 target = srb->pccb->ccb_h.target_id; 793 lun = srb->pccb->ccb_h.target_lun; 794 if(error == FALSE) { 795 if(acb->devstate[target][lun] == ARECA_RAID_GONE) { 796 acb->devstate[target][lun] = ARECA_RAID_GOOD; 797 } 798 srb->pccb->ccb_h.status |= CAM_REQ_CMP; 799 arcmsr_srb_complete(srb, 1); 800 } else { 801 switch(srb->arcmsr_cdb.DeviceStatus) { 802 case ARCMSR_DEV_SELECT_TIMEOUT: { 803 if(acb->devstate[target][lun] == ARECA_RAID_GOOD) { 804 printf( "arcmsr%d: Target=%x, Lun=%x, selection timeout, raid volume was lost\n", acb->pci_unit, target, lun); 805 } 806 acb->devstate[target][lun] = ARECA_RAID_GONE; 807 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 808 arcmsr_srb_complete(srb, 1); 809 } 810 break; 811 case ARCMSR_DEV_ABORTED: 812 case ARCMSR_DEV_INIT_FAIL: { 813 acb->devstate[target][lun] = ARECA_RAID_GONE; 814 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 815 arcmsr_srb_complete(srb, 1); 816 } 817 break; 818 case SCSISTAT_CHECK_CONDITION: { 819 acb->devstate[target][lun] = ARECA_RAID_GOOD; 820 arcmsr_report_sense_info(srb); 821 arcmsr_srb_complete(srb, 1); 822 } 823 break; 824 default: 825 printf("arcmsr%d: scsi id=%d lun=%d isr got command error done,but got unknown DeviceStatus=0x%x \n" 826 , acb->pci_unit, target, lun ,srb->arcmsr_cdb.DeviceStatus); 827 acb->devstate[target][lun] = ARECA_RAID_GONE; 828 srb->pccb->ccb_h.status |= CAM_UNCOR_PARITY; 829 /*unknown error or crc error just for retry*/ 830 arcmsr_srb_complete(srb, 1); 831 break; 832 } 833 } 834 } 835 /* 836 ************************************************************************** 837 ************************************************************************** 838 */ 839 static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, u_int32_t flag_srb, u_int16_t error) 840 { 841 struct CommandControlBlock *srb; 842 843 /* check if command done with no error*/ 844 switch (acb->adapter_type) { 845 case ACB_ADAPTER_TYPE_A: 846 case ACB_ADAPTER_TYPE_B: 847 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 848 break; 849 case ACB_ADAPTER_TYPE_C: 850 case ACB_ADAPTER_TYPE_D: 851 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0)); /*frame must be 32 bytes aligned*/ 852 break; 853 case ACB_ADAPTER_TYPE_E: 854 case ACB_ADAPTER_TYPE_F: 855 srb = acb->psrb_pool[flag_srb]; 856 break; 857 default: 858 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 859 break; 860 } 861 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 862 if(srb->srb_state == ARCMSR_SRB_TIMEOUT) { 863 arcmsr_free_srb(srb); 864 printf("arcmsr%d: srb='%p' return srb has been timeouted\n", acb->pci_unit, srb); 865 return; 866 } 867 printf("arcmsr%d: return srb has been completed\n" 868 "srb='%p' srb_state=0x%x outstanding srb count=%d \n", 869 acb->pci_unit, srb, srb->srb_state, acb->srboutstandingcount); 870 return; 871 } 872 arcmsr_report_srb_state(acb, srb, error); 873 } 874 /* 875 ************************************************************************** 876 ************************************************************************** 877 */ 878 static void arcmsr_srb_timeout(void *arg) 879 { 880 struct CommandControlBlock *srb = (struct CommandControlBlock *)arg; 881 struct AdapterControlBlock *acb; 882 int target, lun; 883 u_int8_t cmd; 884 885 target = srb->pccb->ccb_h.target_id; 886 lun = srb->pccb->ccb_h.target_lun; 887 acb = srb->acb; 888 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 889 if(srb->srb_state == ARCMSR_SRB_START) 890 { 891 cmd = scsiio_cdb_ptr(&srb->pccb->csio)[0]; 892 srb->srb_state = ARCMSR_SRB_TIMEOUT; 893 srb->pccb->ccb_h.status |= CAM_CMD_TIMEOUT; 894 arcmsr_srb_complete(srb, 1); 895 printf("arcmsr%d: scsi id %d lun %d cmd=0x%x srb='%p' ccb command time out!\n", 896 acb->pci_unit, target, lun, cmd, srb); 897 } 898 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 899 #ifdef ARCMSR_DEBUG1 900 arcmsr_dump_data(acb); 901 #endif 902 } 903 904 /* 905 ********************************************************************** 906 ********************************************************************** 907 */ 908 static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb) 909 { 910 int i=0; 911 u_int32_t flag_srb; 912 u_int16_t error; 913 914 switch (acb->adapter_type) { 915 case ACB_ADAPTER_TYPE_A: { 916 u_int32_t outbound_intstatus; 917 918 /*clear and abort all outbound posted Q*/ 919 outbound_intstatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 920 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);/*clear interrupt*/ 921 while(((flag_srb=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_queueport)) != 0xFFFFFFFF) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) { 922 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 923 arcmsr_drain_donequeue(acb, flag_srb, error); 924 } 925 } 926 break; 927 case ACB_ADAPTER_TYPE_B: { 928 struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu; 929 930 /*clear all outbound posted Q*/ 931 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */ 932 for(i=0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) { 933 if((flag_srb = phbbmu->done_qbuffer[i]) != 0) { 934 phbbmu->done_qbuffer[i] = 0; 935 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 936 arcmsr_drain_donequeue(acb, flag_srb, error); 937 } 938 phbbmu->post_qbuffer[i] = 0; 939 }/*drain reply FIFO*/ 940 phbbmu->doneq_index = 0; 941 phbbmu->postq_index = 0; 942 } 943 break; 944 case ACB_ADAPTER_TYPE_C: { 945 while((CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) { 946 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 947 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 948 arcmsr_drain_donequeue(acb, flag_srb, error); 949 } 950 } 951 break; 952 case ACB_ADAPTER_TYPE_D: 953 arcmsr_hbd_postqueue_isr(acb); 954 break; 955 case ACB_ADAPTER_TYPE_E: 956 arcmsr_hbe_postqueue_isr(acb); 957 break; 958 case ACB_ADAPTER_TYPE_F: 959 arcmsr_hbf_postqueue_isr(acb); 960 break; 961 } 962 } 963 /* 964 **************************************************************************** 965 **************************************************************************** 966 */ 967 static void arcmsr_iop_reset(struct AdapterControlBlock *acb) 968 { 969 struct CommandControlBlock *srb; 970 u_int32_t intmask_org; 971 u_int32_t i=0; 972 973 if(acb->srboutstandingcount>0) { 974 /* disable all outbound interrupt */ 975 intmask_org = arcmsr_disable_allintr(acb); 976 /*clear and abort all outbound posted Q*/ 977 arcmsr_done4abort_postqueue(acb); 978 /* talk to iop 331 outstanding command aborted*/ 979 arcmsr_abort_allcmd(acb); 980 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 981 srb = acb->psrb_pool[i]; 982 if(srb->srb_state == ARCMSR_SRB_START) { 983 srb->srb_state = ARCMSR_SRB_ABORTED; 984 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 985 arcmsr_srb_complete(srb, 1); 986 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p' aborted\n" 987 , acb->pci_unit, srb->pccb->ccb_h.target_id 988 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 989 } 990 } 991 /* enable all outbound interrupt */ 992 arcmsr_enable_allintr(acb, intmask_org); 993 } 994 acb->srboutstandingcount = 0; 995 acb->workingsrb_doneindex = 0; 996 acb->workingsrb_startindex = 0; 997 acb->pktRequestCount = 0; 998 acb->pktReturnCount = 0; 999 } 1000 /* 1001 ********************************************************************** 1002 ********************************************************************** 1003 */ 1004 static void arcmsr_build_srb(struct CommandControlBlock *srb, 1005 bus_dma_segment_t *dm_segs, u_int32_t nseg) 1006 { 1007 struct ARCMSR_CDB *arcmsr_cdb = &srb->arcmsr_cdb; 1008 u_int8_t *psge = (u_int8_t *)&arcmsr_cdb->u; 1009 u_int32_t address_lo, address_hi; 1010 union ccb *pccb = srb->pccb; 1011 struct ccb_scsiio *pcsio = &pccb->csio; 1012 u_int32_t arccdbsize = 0x30; 1013 1014 memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB)); 1015 arcmsr_cdb->Bus = 0; 1016 arcmsr_cdb->TargetID = pccb->ccb_h.target_id; 1017 arcmsr_cdb->LUN = pccb->ccb_h.target_lun; 1018 arcmsr_cdb->Function = 1; 1019 arcmsr_cdb->CdbLength = (u_int8_t)pcsio->cdb_len; 1020 bcopy(scsiio_cdb_ptr(pcsio), arcmsr_cdb->Cdb, pcsio->cdb_len); 1021 if(nseg != 0) { 1022 struct AdapterControlBlock *acb = srb->acb; 1023 bus_dmasync_op_t op; 1024 u_int32_t length, i, cdb_sgcount = 0; 1025 1026 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1027 op = BUS_DMASYNC_PREREAD; 1028 } else { 1029 op = BUS_DMASYNC_PREWRITE; 1030 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE; 1031 srb->srb_flags |= SRB_FLAG_WRITE; 1032 } 1033 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op); 1034 for(i=0; i < nseg; i++) { 1035 /* Get the physical address of the current data pointer */ 1036 length = arcmsr_htole32(dm_segs[i].ds_len); 1037 address_lo = arcmsr_htole32(dma_addr_lo32(dm_segs[i].ds_addr)); 1038 address_hi = arcmsr_htole32(dma_addr_hi32(dm_segs[i].ds_addr)); 1039 if(address_hi == 0) { 1040 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge; 1041 pdma_sg->address = address_lo; 1042 pdma_sg->length = length; 1043 psge += sizeof(struct SG32ENTRY); 1044 arccdbsize += sizeof(struct SG32ENTRY); 1045 } else { 1046 u_int32_t sg64s_size = 0, tmplength = length; 1047 1048 while(1) { 1049 u_int64_t span4G, length0; 1050 struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge; 1051 1052 span4G = (u_int64_t)address_lo + tmplength; 1053 pdma_sg->addresshigh = address_hi; 1054 pdma_sg->address = address_lo; 1055 if(span4G > 0x100000000) { 1056 /*see if cross 4G boundary*/ 1057 length0 = 0x100000000-address_lo; 1058 pdma_sg->length = (u_int32_t)length0 | IS_SG64_ADDR; 1059 address_hi = address_hi+1; 1060 address_lo = 0; 1061 tmplength = tmplength - (u_int32_t)length0; 1062 sg64s_size += sizeof(struct SG64ENTRY); 1063 psge += sizeof(struct SG64ENTRY); 1064 cdb_sgcount++; 1065 } else { 1066 pdma_sg->length = tmplength | IS_SG64_ADDR; 1067 sg64s_size += sizeof(struct SG64ENTRY); 1068 psge += sizeof(struct SG64ENTRY); 1069 break; 1070 } 1071 } 1072 arccdbsize += sg64s_size; 1073 } 1074 cdb_sgcount++; 1075 } 1076 arcmsr_cdb->sgcount = (u_int8_t)cdb_sgcount; 1077 arcmsr_cdb->DataLength = pcsio->dxfer_len; 1078 if( arccdbsize > 256) { 1079 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE; 1080 } 1081 } else { 1082 arcmsr_cdb->DataLength = 0; 1083 } 1084 srb->arc_cdb_size = arccdbsize; 1085 arcmsr_cdb->msgPages = (arccdbsize/256) + ((arccdbsize % 256) ? 1 : 0); 1086 } 1087 /* 1088 ************************************************************************** 1089 ************************************************************************** 1090 */ 1091 static void arcmsr_post_srb(struct AdapterControlBlock *acb, struct CommandControlBlock *srb) 1092 { 1093 u_int32_t cdb_phyaddr_low = (u_int32_t) srb->cdb_phyaddr_low; 1094 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&srb->arcmsr_cdb; 1095 1096 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, (srb->srb_flags & SRB_FLAG_WRITE) ? BUS_DMASYNC_POSTWRITE:BUS_DMASYNC_POSTREAD); 1097 atomic_add_int(&acb->srboutstandingcount, 1); 1098 srb->srb_state = ARCMSR_SRB_START; 1099 1100 switch (acb->adapter_type) { 1101 case ACB_ADAPTER_TYPE_A: { 1102 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { 1103 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low|ARCMSR_SRBPOST_FLAG_SGL_BSIZE); 1104 } else { 1105 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low); 1106 } 1107 } 1108 break; 1109 case ACB_ADAPTER_TYPE_B: { 1110 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1111 int ending_index, index; 1112 1113 index = phbbmu->postq_index; 1114 ending_index = ((index+1) % ARCMSR_MAX_HBB_POSTQUEUE); 1115 phbbmu->post_qbuffer[ending_index] = 0; 1116 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { 1117 phbbmu->post_qbuffer[index] = cdb_phyaddr_low | ARCMSR_SRBPOST_FLAG_SGL_BSIZE; 1118 } else { 1119 phbbmu->post_qbuffer[index] = cdb_phyaddr_low; 1120 } 1121 index++; 1122 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 1123 phbbmu->postq_index = index; 1124 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_CDB_POSTED); 1125 } 1126 break; 1127 case ACB_ADAPTER_TYPE_C: { 1128 u_int32_t ccb_post_stamp, arc_cdb_size, cdb_phyaddr_hi32; 1129 1130 arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size; 1131 ccb_post_stamp = (cdb_phyaddr_low | ((arc_cdb_size-1) >> 6) | 1); 1132 cdb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high; 1133 if(cdb_phyaddr_hi32) 1134 { 1135 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_high, cdb_phyaddr_hi32); 1136 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp); 1137 } 1138 else 1139 { 1140 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp); 1141 } 1142 } 1143 break; 1144 case ACB_ADAPTER_TYPE_D: { 1145 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1146 u_int16_t index_stripped; 1147 u_int16_t postq_index; 1148 struct InBound_SRB *pinbound_srb; 1149 1150 ARCMSR_LOCK_ACQUIRE(&acb->postDone_lock); 1151 postq_index = phbdmu->postq_index; 1152 pinbound_srb = (struct InBound_SRB *)&phbdmu->post_qbuffer[postq_index & 0xFF]; 1153 pinbound_srb->addressHigh = srb->cdb_phyaddr_high; 1154 pinbound_srb->addressLow = srb->cdb_phyaddr_low; 1155 pinbound_srb->length = srb->arc_cdb_size >> 2; 1156 arcmsr_cdb->Context = srb->cdb_phyaddr_low; 1157 if (postq_index & 0x4000) { 1158 index_stripped = postq_index & 0xFF; 1159 index_stripped += 1; 1160 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1161 phbdmu->postq_index = index_stripped ? (index_stripped | 0x4000) : index_stripped; 1162 } else { 1163 index_stripped = postq_index; 1164 index_stripped += 1; 1165 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1166 phbdmu->postq_index = index_stripped ? index_stripped : (index_stripped | 0x4000); 1167 } 1168 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inboundlist_write_pointer, postq_index); 1169 ARCMSR_LOCK_RELEASE(&acb->postDone_lock); 1170 } 1171 break; 1172 case ACB_ADAPTER_TYPE_E: { 1173 u_int32_t ccb_post_stamp, arc_cdb_size; 1174 1175 arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size; 1176 ccb_post_stamp = (srb->smid | ((arc_cdb_size-1) >> 6)); 1177 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_queueport_high, 0); 1178 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_queueport_low, ccb_post_stamp); 1179 } 1180 break; 1181 case ACB_ADAPTER_TYPE_F: { 1182 u_int32_t ccb_post_stamp, arc_cdb_size; 1183 1184 if (srb->arc_cdb_size <= 0x300) 1185 arc_cdb_size = (srb->arc_cdb_size - 1) >> 6 | 1; 1186 else 1187 arc_cdb_size = (((srb->arc_cdb_size + 0xff) >> 8) + 2) << 1 | 1; 1188 ccb_post_stamp = (srb->smid | arc_cdb_size); 1189 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_queueport_high, 0); 1190 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_queueport_low, ccb_post_stamp); 1191 } 1192 break; 1193 } 1194 } 1195 /* 1196 ************************************************************************ 1197 ************************************************************************ 1198 */ 1199 static struct QBUFFER *arcmsr_get_iop_rqbuffer( struct AdapterControlBlock *acb) 1200 { 1201 struct QBUFFER *qbuffer=NULL; 1202 1203 switch (acb->adapter_type) { 1204 case ACB_ADAPTER_TYPE_A: { 1205 struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu; 1206 1207 qbuffer = (struct QBUFFER *)&phbamu->message_rbuffer; 1208 } 1209 break; 1210 case ACB_ADAPTER_TYPE_B: { 1211 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1212 1213 qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_rbuffer; 1214 } 1215 break; 1216 case ACB_ADAPTER_TYPE_C: { 1217 struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu; 1218 1219 qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer; 1220 } 1221 break; 1222 case ACB_ADAPTER_TYPE_D: { 1223 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1224 1225 qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_rbuffer; 1226 } 1227 break; 1228 case ACB_ADAPTER_TYPE_E: { 1229 struct HBE_MessageUnit *phbcmu = (struct HBE_MessageUnit *)acb->pmu; 1230 1231 qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer; 1232 } 1233 break; 1234 case ACB_ADAPTER_TYPE_F: 1235 qbuffer = (struct QBUFFER *)acb->message_rbuffer; 1236 break; 1237 } 1238 return(qbuffer); 1239 } 1240 /* 1241 ************************************************************************ 1242 ************************************************************************ 1243 */ 1244 static struct QBUFFER *arcmsr_get_iop_wqbuffer( struct AdapterControlBlock *acb) 1245 { 1246 struct QBUFFER *qbuffer = NULL; 1247 1248 switch (acb->adapter_type) { 1249 case ACB_ADAPTER_TYPE_A: { 1250 struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu; 1251 1252 qbuffer = (struct QBUFFER *)&phbamu->message_wbuffer; 1253 } 1254 break; 1255 case ACB_ADAPTER_TYPE_B: { 1256 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1257 1258 qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_wbuffer; 1259 } 1260 break; 1261 case ACB_ADAPTER_TYPE_C: { 1262 struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu; 1263 1264 qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer; 1265 } 1266 break; 1267 case ACB_ADAPTER_TYPE_D: { 1268 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1269 1270 qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_wbuffer; 1271 } 1272 break; 1273 case ACB_ADAPTER_TYPE_E: { 1274 struct HBE_MessageUnit *phbcmu = (struct HBE_MessageUnit *)acb->pmu; 1275 1276 qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer; 1277 } 1278 break; 1279 case ACB_ADAPTER_TYPE_F: 1280 qbuffer = (struct QBUFFER *)acb->message_wbuffer; 1281 break; 1282 } 1283 return(qbuffer); 1284 } 1285 /* 1286 ************************************************************************** 1287 ************************************************************************** 1288 */ 1289 static void arcmsr_iop_message_read(struct AdapterControlBlock *acb) 1290 { 1291 switch (acb->adapter_type) { 1292 case ACB_ADAPTER_TYPE_A: { 1293 /* let IOP know data has been read */ 1294 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK); 1295 } 1296 break; 1297 case ACB_ADAPTER_TYPE_B: { 1298 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1299 /* let IOP know data has been read */ 1300 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK); 1301 } 1302 break; 1303 case ACB_ADAPTER_TYPE_C: { 1304 /* let IOP know data has been read */ 1305 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK); 1306 } 1307 break; 1308 case ACB_ADAPTER_TYPE_D: { 1309 /* let IOP know data has been read */ 1310 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ); 1311 } 1312 break; 1313 case ACB_ADAPTER_TYPE_E: 1314 case ACB_ADAPTER_TYPE_F: { 1315 /* let IOP know data has been read */ 1316 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK; 1317 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 1318 } 1319 break; 1320 } 1321 } 1322 /* 1323 ************************************************************************** 1324 ************************************************************************** 1325 */ 1326 static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb) 1327 { 1328 switch (acb->adapter_type) { 1329 case ACB_ADAPTER_TYPE_A: { 1330 /* 1331 ** push inbound doorbell tell iop, driver data write ok 1332 ** and wait reply on next hwinterrupt for next Qbuffer post 1333 */ 1334 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK); 1335 } 1336 break; 1337 case ACB_ADAPTER_TYPE_B: { 1338 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1339 /* 1340 ** push inbound doorbell tell iop, driver data write ok 1341 ** and wait reply on next hwinterrupt for next Qbuffer post 1342 */ 1343 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_WRITE_OK); 1344 } 1345 break; 1346 case ACB_ADAPTER_TYPE_C: { 1347 /* 1348 ** push inbound doorbell tell iop, driver data write ok 1349 ** and wait reply on next hwinterrupt for next Qbuffer post 1350 */ 1351 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK); 1352 } 1353 break; 1354 case ACB_ADAPTER_TYPE_D: { 1355 /* 1356 ** push inbound doorbell tell iop, driver data write ok 1357 ** and wait reply on next hwinterrupt for next Qbuffer post 1358 */ 1359 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY); 1360 } 1361 break; 1362 case ACB_ADAPTER_TYPE_E: 1363 case ACB_ADAPTER_TYPE_F: { 1364 /* 1365 ** push inbound doorbell tell iop, driver data write ok 1366 ** and wait reply on next hwinterrupt for next Qbuffer post 1367 */ 1368 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_WRITE_OK; 1369 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 1370 } 1371 break; 1372 } 1373 } 1374 /* 1375 ************************************************************************ 1376 ************************************************************************ 1377 */ 1378 static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb) 1379 { 1380 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1381 CHIP_REG_WRITE32(HBA_MessageUnit, 1382 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1383 if(!arcmsr_hba_wait_msgint_ready(acb)) { 1384 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n" 1385 , acb->pci_unit); 1386 } 1387 } 1388 /* 1389 ************************************************************************ 1390 ************************************************************************ 1391 */ 1392 static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb) 1393 { 1394 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1395 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1396 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_STOP_BGRB); 1397 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 1398 printf( "arcmsr%d: wait 'stop adapter background rebulid' timeout \n" 1399 , acb->pci_unit); 1400 } 1401 } 1402 /* 1403 ************************************************************************ 1404 ************************************************************************ 1405 */ 1406 static void arcmsr_stop_hbc_bgrb(struct AdapterControlBlock *acb) 1407 { 1408 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1409 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1410 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 1411 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 1412 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1413 } 1414 } 1415 /* 1416 ************************************************************************ 1417 ************************************************************************ 1418 */ 1419 static void arcmsr_stop_hbd_bgrb(struct AdapterControlBlock *acb) 1420 { 1421 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1422 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1423 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 1424 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1425 } 1426 } 1427 /* 1428 ************************************************************************ 1429 ************************************************************************ 1430 */ 1431 static void arcmsr_stop_hbe_bgrb(struct AdapterControlBlock *acb) 1432 { 1433 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1434 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1435 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 1436 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 1437 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 1438 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1439 } 1440 } 1441 /* 1442 ************************************************************************ 1443 ************************************************************************ 1444 */ 1445 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb) 1446 { 1447 switch (acb->adapter_type) { 1448 case ACB_ADAPTER_TYPE_A: { 1449 arcmsr_stop_hba_bgrb(acb); 1450 } 1451 break; 1452 case ACB_ADAPTER_TYPE_B: { 1453 arcmsr_stop_hbb_bgrb(acb); 1454 } 1455 break; 1456 case ACB_ADAPTER_TYPE_C: { 1457 arcmsr_stop_hbc_bgrb(acb); 1458 } 1459 break; 1460 case ACB_ADAPTER_TYPE_D: { 1461 arcmsr_stop_hbd_bgrb(acb); 1462 } 1463 break; 1464 case ACB_ADAPTER_TYPE_E: 1465 case ACB_ADAPTER_TYPE_F: { 1466 arcmsr_stop_hbe_bgrb(acb); 1467 } 1468 break; 1469 } 1470 } 1471 /* 1472 ************************************************************************ 1473 ************************************************************************ 1474 */ 1475 static void arcmsr_poll(struct cam_sim *psim) 1476 { 1477 struct AdapterControlBlock *acb; 1478 int mutex; 1479 1480 acb = (struct AdapterControlBlock *)cam_sim_softc(psim); 1481 mutex = mtx_owned(&acb->isr_lock); 1482 if( mutex == 0 ) 1483 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 1484 arcmsr_interrupt(acb); 1485 if( mutex == 0 ) 1486 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 1487 } 1488 /* 1489 ************************************************************************** 1490 ************************************************************************** 1491 */ 1492 static u_int32_t arcmsr_Read_iop_rqbuffer_data_D(struct AdapterControlBlock *acb, 1493 struct QBUFFER *prbuffer) { 1494 u_int8_t *pQbuffer; 1495 u_int8_t *buf1 = NULL; 1496 u_int32_t *iop_data, *buf2 = NULL; 1497 u_int32_t iop_len, data_len; 1498 1499 iop_data = (u_int32_t *)prbuffer->data; 1500 iop_len = (u_int32_t)prbuffer->data_len; 1501 if ( iop_len > 0 ) 1502 { 1503 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO); 1504 buf2 = (u_int32_t *)buf1; 1505 if( buf1 == NULL) 1506 return (0); 1507 data_len = iop_len; 1508 while(data_len >= 4) 1509 { 1510 *buf2++ = *iop_data++; 1511 data_len -= 4; 1512 } 1513 if(data_len) 1514 *buf2 = *iop_data; 1515 buf2 = (u_int32_t *)buf1; 1516 } 1517 while (iop_len > 0) { 1518 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex]; 1519 *pQbuffer = *buf1; 1520 acb->rqbuf_lastindex++; 1521 /* if last, index number set it to 0 */ 1522 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 1523 buf1++; 1524 iop_len--; 1525 } 1526 if(buf2) 1527 free( (u_int8_t *)buf2, M_DEVBUF); 1528 /* let IOP know data has been read */ 1529 arcmsr_iop_message_read(acb); 1530 return (1); 1531 } 1532 /* 1533 ************************************************************************** 1534 ************************************************************************** 1535 */ 1536 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, 1537 struct QBUFFER *prbuffer) { 1538 u_int8_t *pQbuffer; 1539 u_int8_t *iop_data; 1540 u_int32_t iop_len; 1541 1542 if(acb->adapter_type >= ACB_ADAPTER_TYPE_B) { 1543 return(arcmsr_Read_iop_rqbuffer_data_D(acb, prbuffer)); 1544 } 1545 iop_data = (u_int8_t *)prbuffer->data; 1546 iop_len = (u_int32_t)prbuffer->data_len; 1547 while (iop_len > 0) { 1548 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex]; 1549 *pQbuffer = *iop_data; 1550 acb->rqbuf_lastindex++; 1551 /* if last, index number set it to 0 */ 1552 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 1553 iop_data++; 1554 iop_len--; 1555 } 1556 /* let IOP know data has been read */ 1557 arcmsr_iop_message_read(acb); 1558 return (1); 1559 } 1560 /* 1561 ************************************************************************** 1562 ************************************************************************** 1563 */ 1564 static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb) 1565 { 1566 struct QBUFFER *prbuffer; 1567 int my_empty_len; 1568 1569 /*check this iop data if overflow my rqbuffer*/ 1570 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 1571 prbuffer = arcmsr_get_iop_rqbuffer(acb); 1572 my_empty_len = (acb->rqbuf_lastindex - acb->rqbuf_firstindex - 1) & 1573 (ARCMSR_MAX_QBUFFER-1); 1574 if(my_empty_len >= prbuffer->data_len) { 1575 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 1576 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 1577 } else { 1578 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 1579 } 1580 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 1581 } 1582 /* 1583 ********************************************************************** 1584 ********************************************************************** 1585 */ 1586 static void arcmsr_Write_data_2iop_wqbuffer_D(struct AdapterControlBlock *acb) 1587 { 1588 u_int8_t *pQbuffer; 1589 struct QBUFFER *pwbuffer; 1590 u_int8_t *buf1 = NULL; 1591 u_int32_t *iop_data, *buf2 = NULL; 1592 u_int32_t allxfer_len = 0, data_len; 1593 1594 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) { 1595 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO); 1596 buf2 = (u_int32_t *)buf1; 1597 if( buf1 == NULL) 1598 return; 1599 1600 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ); 1601 pwbuffer = arcmsr_get_iop_wqbuffer(acb); 1602 iop_data = (u_int32_t *)pwbuffer->data; 1603 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex) 1604 && (allxfer_len < 124)) { 1605 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex]; 1606 *buf1 = *pQbuffer; 1607 acb->wqbuf_firstindex++; 1608 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 1609 buf1++; 1610 allxfer_len++; 1611 } 1612 pwbuffer->data_len = allxfer_len; 1613 data_len = allxfer_len; 1614 buf1 = (u_int8_t *)buf2; 1615 while(data_len >= 4) 1616 { 1617 *iop_data++ = *buf2++; 1618 data_len -= 4; 1619 } 1620 if(data_len) 1621 *iop_data = *buf2; 1622 free( buf1, M_DEVBUF); 1623 arcmsr_iop_message_wrote(acb); 1624 } 1625 } 1626 /* 1627 ********************************************************************** 1628 ********************************************************************** 1629 */ 1630 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb) 1631 { 1632 u_int8_t *pQbuffer; 1633 struct QBUFFER *pwbuffer; 1634 u_int8_t *iop_data; 1635 int32_t allxfer_len=0; 1636 1637 if(acb->adapter_type >= ACB_ADAPTER_TYPE_B) { 1638 arcmsr_Write_data_2iop_wqbuffer_D(acb); 1639 return; 1640 } 1641 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) { 1642 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ); 1643 pwbuffer = arcmsr_get_iop_wqbuffer(acb); 1644 iop_data = (u_int8_t *)pwbuffer->data; 1645 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex) 1646 && (allxfer_len < 124)) { 1647 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex]; 1648 *iop_data = *pQbuffer; 1649 acb->wqbuf_firstindex++; 1650 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 1651 iop_data++; 1652 allxfer_len++; 1653 } 1654 pwbuffer->data_len = allxfer_len; 1655 arcmsr_iop_message_wrote(acb); 1656 } 1657 } 1658 /* 1659 ************************************************************************** 1660 ************************************************************************** 1661 */ 1662 static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb) 1663 { 1664 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 1665 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READ; 1666 /* 1667 ***************************************************************** 1668 ** check if there are any mail packages from user space program 1669 ** in my post bag, now is the time to send them into Areca's firmware 1670 ***************************************************************** 1671 */ 1672 if(acb->wqbuf_firstindex != acb->wqbuf_lastindex) { 1673 arcmsr_Write_data_2iop_wqbuffer(acb); 1674 } 1675 if(acb->wqbuf_firstindex == acb->wqbuf_lastindex) { 1676 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED; 1677 } 1678 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 1679 } 1680 /* 1681 ************************************************************************** 1682 ************************************************************************** 1683 */ 1684 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb) 1685 { 1686 /* 1687 if (ccb->ccb_h.status != CAM_REQ_CMP) 1688 printf("arcmsr_rescanLun_cb: Rescan Target=%x, lun=%x," 1689 "failure status=%x\n", ccb->ccb_h.target_id, 1690 ccb->ccb_h.target_lun, ccb->ccb_h.status); 1691 else 1692 printf("arcmsr_rescanLun_cb: Rescan lun successfully!\n"); 1693 */ 1694 xpt_free_path(ccb->ccb_h.path); 1695 xpt_free_ccb(ccb); 1696 } 1697 1698 static void arcmsr_rescan_lun(struct AdapterControlBlock *acb, int target, int lun) 1699 { 1700 struct cam_path *path; 1701 union ccb *ccb; 1702 1703 if ((ccb = (union ccb *)xpt_alloc_ccb_nowait()) == NULL) 1704 return; 1705 if (xpt_create_path(&path, NULL, cam_sim_path(acb->psim), target, lun) != CAM_REQ_CMP) 1706 { 1707 xpt_free_ccb(ccb); 1708 return; 1709 } 1710 /* printf("arcmsr_rescan_lun: Rescan Target=%x, Lun=%x\n", target, lun); */ 1711 xpt_setup_ccb(&ccb->ccb_h, path, 5); 1712 ccb->ccb_h.func_code = XPT_SCAN_LUN; 1713 ccb->ccb_h.cbfcnp = arcmsr_rescanLun_cb; 1714 ccb->crcn.flags = CAM_FLAG_NONE; 1715 xpt_action(ccb); 1716 } 1717 1718 static void arcmsr_abort_dr_ccbs(struct AdapterControlBlock *acb, int target, int lun) 1719 { 1720 struct CommandControlBlock *srb; 1721 u_int32_t intmask_org; 1722 int i; 1723 1724 /* disable all outbound interrupts */ 1725 intmask_org = arcmsr_disable_allintr(acb); 1726 for (i = 0; i < ARCMSR_MAX_FREESRB_NUM; i++) 1727 { 1728 srb = acb->psrb_pool[i]; 1729 if (srb->srb_state == ARCMSR_SRB_START) 1730 { 1731 if((target == srb->pccb->ccb_h.target_id) && (lun == srb->pccb->ccb_h.target_lun)) 1732 { 1733 srb->srb_state = ARCMSR_SRB_ABORTED; 1734 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 1735 arcmsr_srb_complete(srb, 1); 1736 printf("arcmsr%d: abort scsi id %d lun %d srb=%p \n", acb->pci_unit, target, lun, srb); 1737 } 1738 } 1739 } 1740 /* enable outbound Post Queue, outbound doorbell Interrupt */ 1741 arcmsr_enable_allintr(acb, intmask_org); 1742 } 1743 /* 1744 ************************************************************************** 1745 ************************************************************************** 1746 */ 1747 static void arcmsr_dr_handle(struct AdapterControlBlock *acb) { 1748 u_int32_t devicemap; 1749 u_int32_t target, lun; 1750 u_int32_t deviceMapCurrent[4]={0}; 1751 u_int8_t *pDevMap; 1752 1753 switch (acb->adapter_type) { 1754 case ACB_ADAPTER_TYPE_A: 1755 devicemap = offsetof(struct HBA_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1756 for (target = 0; target < 4; target++) 1757 { 1758 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1759 devicemap += 4; 1760 } 1761 break; 1762 1763 case ACB_ADAPTER_TYPE_B: 1764 devicemap = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1765 for (target = 0; target < 4; target++) 1766 { 1767 deviceMapCurrent[target]=bus_space_read_4(acb->btag[1], acb->bhandle[1], devicemap); 1768 devicemap += 4; 1769 } 1770 break; 1771 1772 case ACB_ADAPTER_TYPE_C: 1773 devicemap = offsetof(struct HBC_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1774 for (target = 0; target < 4; target++) 1775 { 1776 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1777 devicemap += 4; 1778 } 1779 break; 1780 case ACB_ADAPTER_TYPE_D: 1781 devicemap = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1782 for (target = 0; target < 4; target++) 1783 { 1784 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1785 devicemap += 4; 1786 } 1787 break; 1788 case ACB_ADAPTER_TYPE_E: 1789 devicemap = offsetof(struct HBE_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1790 for (target = 0; target < 4; target++) 1791 { 1792 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1793 devicemap += 4; 1794 } 1795 break; 1796 case ACB_ADAPTER_TYPE_F: 1797 devicemap = ARCMSR_FW_DEVMAP_OFFSET; 1798 for (target = 0; target < 4; target++) 1799 { 1800 deviceMapCurrent[target] = acb->msgcode_rwbuffer[devicemap]; 1801 devicemap += 1; 1802 } 1803 break; 1804 } 1805 1806 if(acb->acb_flags & ACB_F_BUS_HANG_ON) 1807 { 1808 acb->acb_flags &= ~ACB_F_BUS_HANG_ON; 1809 } 1810 /* 1811 ** adapter posted CONFIG message 1812 ** copy the new map, note if there are differences with the current map 1813 */ 1814 pDevMap = (u_int8_t *)&deviceMapCurrent[0]; 1815 for (target = 0; target < ARCMSR_MAX_TARGETID - 1; target++) 1816 { 1817 if (*pDevMap != acb->device_map[target]) 1818 { 1819 u_int8_t difference, bit_check; 1820 1821 difference = *pDevMap ^ acb->device_map[target]; 1822 for(lun=0; lun < ARCMSR_MAX_TARGETLUN; lun++) 1823 { 1824 bit_check = (1 << lun); /*check bit from 0....31*/ 1825 if(difference & bit_check) 1826 { 1827 if(acb->device_map[target] & bit_check) 1828 {/* unit departed */ 1829 printf("arcmsr_dr_handle: Target=%x, lun=%x, GONE!!!\n",target,lun); 1830 arcmsr_abort_dr_ccbs(acb, target, lun); 1831 arcmsr_rescan_lun(acb, target, lun); 1832 acb->devstate[target][lun] = ARECA_RAID_GONE; 1833 } 1834 else 1835 {/* unit arrived */ 1836 printf("arcmsr_dr_handle: Target=%x, lun=%x, Plug-IN!!!\n",target,lun); 1837 arcmsr_rescan_lun(acb, target, lun); 1838 acb->devstate[target][lun] = ARECA_RAID_GOOD; 1839 } 1840 } 1841 } 1842 /* printf("arcmsr_dr_handle: acb->device_map[%x]=0x%x, deviceMapCurrent[%x]=%x\n",target,acb->device_map[target],target,*pDevMap); */ 1843 acb->device_map[target] = *pDevMap; 1844 } 1845 pDevMap++; 1846 } 1847 } 1848 /* 1849 ************************************************************************** 1850 ************************************************************************** 1851 */ 1852 static void arcmsr_hba_message_isr(struct AdapterControlBlock *acb) { 1853 u_int32_t outbound_message; 1854 1855 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT); 1856 outbound_message = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[0]); 1857 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1858 arcmsr_dr_handle( acb ); 1859 } 1860 /* 1861 ************************************************************************** 1862 ************************************************************************** 1863 */ 1864 static void arcmsr_hbb_message_isr(struct AdapterControlBlock *acb) { 1865 u_int32_t outbound_message; 1866 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1867 1868 /* clear interrupts */ 1869 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN); 1870 outbound_message = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0]); 1871 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1872 arcmsr_dr_handle( acb ); 1873 } 1874 /* 1875 ************************************************************************** 1876 ************************************************************************** 1877 */ 1878 static void arcmsr_hbc_message_isr(struct AdapterControlBlock *acb) { 1879 u_int32_t outbound_message; 1880 1881 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR); 1882 outbound_message = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[0]); 1883 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1884 arcmsr_dr_handle( acb ); 1885 } 1886 /* 1887 ************************************************************************** 1888 ************************************************************************** 1889 */ 1890 static void arcmsr_hbd_message_isr(struct AdapterControlBlock *acb) { 1891 u_int32_t outbound_message; 1892 1893 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR); 1894 outbound_message = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[0]); 1895 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1896 arcmsr_dr_handle( acb ); 1897 } 1898 /* 1899 ************************************************************************** 1900 ************************************************************************** 1901 */ 1902 static void arcmsr_hbe_message_isr(struct AdapterControlBlock *acb) { 1903 u_int32_t outbound_message; 1904 1905 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); 1906 if (acb->adapter_type == ACB_ADAPTER_TYPE_E) 1907 outbound_message = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[0]); 1908 else 1909 outbound_message = acb->msgcode_rwbuffer[0]; 1910 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1911 arcmsr_dr_handle( acb ); 1912 } 1913 /* 1914 ************************************************************************** 1915 ************************************************************************** 1916 */ 1917 static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb) 1918 { 1919 u_int32_t doorbell_status; 1920 1921 /* 1922 ******************************************************************* 1923 ** Maybe here we need to check wrqbuffer_lock is lock or not 1924 ** DOORBELL: din! don! 1925 ** check if there are any mail need to pack from firmware 1926 ******************************************************************* 1927 */ 1928 doorbell_status = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell); 1929 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */ 1930 if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) { 1931 arcmsr_iop2drv_data_wrote_handle(acb); 1932 } 1933 if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) { 1934 arcmsr_iop2drv_data_read_handle(acb); 1935 } 1936 } 1937 /* 1938 ************************************************************************** 1939 ************************************************************************** 1940 */ 1941 static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *acb) 1942 { 1943 u_int32_t doorbell_status; 1944 1945 /* 1946 ******************************************************************* 1947 ** Maybe here we need to check wrqbuffer_lock is lock or not 1948 ** DOORBELL: din! don! 1949 ** check if there are any mail need to pack from firmware 1950 ******************************************************************* 1951 */ 1952 doorbell_status = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell); 1953 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, doorbell_status); /* clear doorbell interrupt */ 1954 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) { 1955 arcmsr_iop2drv_data_wrote_handle(acb); 1956 } 1957 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) { 1958 arcmsr_iop2drv_data_read_handle(acb); 1959 } 1960 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 1961 arcmsr_hbc_message_isr(acb); /* messenger of "driver to iop commands" */ 1962 } 1963 } 1964 /* 1965 ************************************************************************** 1966 ************************************************************************** 1967 */ 1968 static void arcmsr_hbd_doorbell_isr(struct AdapterControlBlock *acb) 1969 { 1970 u_int32_t doorbell_status; 1971 1972 /* 1973 ******************************************************************* 1974 ** Maybe here we need to check wrqbuffer_lock is lock or not 1975 ** DOORBELL: din! don! 1976 ** check if there are any mail need to pack from firmware 1977 ******************************************************************* 1978 */ 1979 doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE; 1980 if(doorbell_status) 1981 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */ 1982 while( doorbell_status & ARCMSR_HBDMU_F0_DOORBELL_CAUSE ) { 1983 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK) { 1984 arcmsr_iop2drv_data_wrote_handle(acb); 1985 } 1986 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK) { 1987 arcmsr_iop2drv_data_read_handle(acb); 1988 } 1989 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) { 1990 arcmsr_hbd_message_isr(acb); /* messenger of "driver to iop commands" */ 1991 } 1992 doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE; 1993 if(doorbell_status) 1994 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */ 1995 } 1996 } 1997 /* 1998 ************************************************************************** 1999 ************************************************************************** 2000 */ 2001 static void arcmsr_hbe_doorbell_isr(struct AdapterControlBlock *acb) 2002 { 2003 u_int32_t doorbell_status, in_doorbell; 2004 2005 /* 2006 ******************************************************************* 2007 ** Maybe here we need to check wrqbuffer_lock is lock or not 2008 ** DOORBELL: din! don! 2009 ** check if there are any mail need to pack from firmware 2010 ******************************************************************* 2011 */ 2012 in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell); 2013 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /* clear doorbell interrupt */ 2014 doorbell_status = in_doorbell ^ acb->in_doorbell; 2015 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_WRITE_OK) { 2016 arcmsr_iop2drv_data_wrote_handle(acb); 2017 } 2018 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_DATA_READ_OK) { 2019 arcmsr_iop2drv_data_read_handle(acb); 2020 } 2021 if(doorbell_status & ARCMSR_HBEMU_IOP2DRV_MESSAGE_CMD_DONE) { 2022 arcmsr_hbe_message_isr(acb); /* messenger of "driver to iop commands" */ 2023 } 2024 acb->in_doorbell = in_doorbell; 2025 } 2026 /* 2027 ************************************************************************** 2028 ************************************************************************** 2029 */ 2030 static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb) 2031 { 2032 u_int32_t flag_srb; 2033 u_int16_t error; 2034 2035 /* 2036 ***************************************************************************** 2037 ** areca cdb command done 2038 ***************************************************************************** 2039 */ 2040 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 2041 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2042 while((flag_srb = CHIP_REG_READ32(HBA_MessageUnit, 2043 0, outbound_queueport)) != 0xFFFFFFFF) { 2044 /* check if command done with no error*/ 2045 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0) ? TRUE : FALSE; 2046 arcmsr_drain_donequeue(acb, flag_srb, error); 2047 } /*drain reply FIFO*/ 2048 } 2049 /* 2050 ************************************************************************** 2051 ************************************************************************** 2052 */ 2053 static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb) 2054 { 2055 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 2056 u_int32_t flag_srb; 2057 int index; 2058 u_int16_t error; 2059 2060 /* 2061 ***************************************************************************** 2062 ** areca cdb command done 2063 ***************************************************************************** 2064 */ 2065 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 2066 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 2067 index = phbbmu->doneq_index; 2068 while((flag_srb = phbbmu->done_qbuffer[index]) != 0) { 2069 phbbmu->done_qbuffer[index] = 0; 2070 index++; 2071 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 2072 phbbmu->doneq_index = index; 2073 /* check if command done with no error*/ 2074 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 2075 arcmsr_drain_donequeue(acb, flag_srb, error); 2076 } /*drain reply FIFO*/ 2077 } 2078 /* 2079 ************************************************************************** 2080 ************************************************************************** 2081 */ 2082 static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb) 2083 { 2084 u_int32_t flag_srb,throttling = 0; 2085 u_int16_t error; 2086 2087 /* 2088 ***************************************************************************** 2089 ** areca cdb command done 2090 ***************************************************************************** 2091 */ 2092 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2093 do { 2094 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 2095 if (flag_srb == 0xFFFFFFFF) 2096 break; 2097 /* check if command done with no error*/ 2098 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE; 2099 arcmsr_drain_donequeue(acb, flag_srb, error); 2100 throttling++; 2101 if(throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) { 2102 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING); 2103 throttling = 0; 2104 } 2105 } while(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR); 2106 } 2107 /* 2108 ********************************************************************** 2109 ** 2110 ********************************************************************** 2111 */ 2112 static uint16_t arcmsr_get_doneq_index(struct HBD_MessageUnit0 *phbdmu) 2113 { 2114 uint16_t doneq_index, index_stripped; 2115 2116 doneq_index = phbdmu->doneq_index; 2117 if (doneq_index & 0x4000) { 2118 index_stripped = doneq_index & 0xFF; 2119 index_stripped += 1; 2120 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 2121 phbdmu->doneq_index = index_stripped ? 2122 (index_stripped | 0x4000) : index_stripped; 2123 } else { 2124 index_stripped = doneq_index; 2125 index_stripped += 1; 2126 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 2127 phbdmu->doneq_index = index_stripped ? 2128 index_stripped : (index_stripped | 0x4000); 2129 } 2130 return (phbdmu->doneq_index); 2131 } 2132 /* 2133 ************************************************************************** 2134 ************************************************************************** 2135 */ 2136 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb) 2137 { 2138 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 2139 u_int32_t outbound_write_pointer; 2140 u_int32_t addressLow; 2141 uint16_t doneq_index; 2142 u_int16_t error; 2143 /* 2144 ***************************************************************************** 2145 ** areca cdb command done 2146 ***************************************************************************** 2147 */ 2148 if((CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause) & 2149 ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT) == 0) 2150 return; 2151 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 2152 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2153 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 2154 doneq_index = phbdmu->doneq_index; 2155 while ((doneq_index & 0xFF) != (outbound_write_pointer & 0xFF)) { 2156 doneq_index = arcmsr_get_doneq_index(phbdmu); 2157 addressLow = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow; 2158 error = (addressLow & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 2159 arcmsr_drain_donequeue(acb, addressLow, error); /*Check if command done with no error */ 2160 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index); 2161 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 2162 } 2163 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_interrupt_cause, ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR); 2164 CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause); /*Dummy ioread32 to force pci flush */ 2165 } 2166 /* 2167 ************************************************************************** 2168 ************************************************************************** 2169 */ 2170 static void arcmsr_hbe_postqueue_isr(struct AdapterControlBlock *acb) 2171 { 2172 u_int16_t error; 2173 uint32_t doneq_index; 2174 uint16_t cmdSMID; 2175 2176 /* 2177 ***************************************************************************** 2178 ** areca cdb command done 2179 ***************************************************************************** 2180 */ 2181 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2182 doneq_index = acb->doneq_index; 2183 while ((CHIP_REG_READ32(HBE_MessageUnit, 0, reply_post_producer_index) & 0xFFFF) != doneq_index) { 2184 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID; 2185 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 2186 arcmsr_drain_donequeue(acb, (u_int32_t)cmdSMID, error); 2187 doneq_index++; 2188 if (doneq_index >= acb->completionQ_entry) 2189 doneq_index = 0; 2190 } 2191 acb->doneq_index = doneq_index; 2192 CHIP_REG_WRITE32(HBE_MessageUnit, 0, reply_post_consumer_index, doneq_index); 2193 } 2194 2195 static void arcmsr_hbf_postqueue_isr(struct AdapterControlBlock *acb) 2196 { 2197 uint16_t error; 2198 uint32_t doneq_index; 2199 uint16_t cmdSMID; 2200 2201 /* 2202 ***************************************************************************** 2203 ** areca cdb command done 2204 ***************************************************************************** 2205 */ 2206 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2207 doneq_index = acb->doneq_index; 2208 while (1) { 2209 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID; 2210 if (cmdSMID == 0xffff) 2211 break; 2212 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 2213 arcmsr_drain_donequeue(acb, (u_int32_t)cmdSMID, error); 2214 acb->pCompletionQ[doneq_index].cmdSMID = 0xffff; 2215 doneq_index++; 2216 if (doneq_index >= acb->completionQ_entry) 2217 doneq_index = 0; 2218 } 2219 acb->doneq_index = doneq_index; 2220 CHIP_REG_WRITE32(HBF_MessageUnit, 0, reply_post_consumer_index, doneq_index); 2221 } 2222 2223 /* 2224 ********************************************************************** 2225 ********************************************************************** 2226 */ 2227 static void arcmsr_handle_hba_isr( struct AdapterControlBlock *acb) 2228 { 2229 u_int32_t outbound_intStatus; 2230 /* 2231 ********************************************* 2232 ** check outbound intstatus 2233 ********************************************* 2234 */ 2235 outbound_intStatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 2236 if(!outbound_intStatus) { 2237 /*it must be share irq*/ 2238 return; 2239 } 2240 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intStatus); /*clear interrupt*/ 2241 /* MU doorbell interrupts*/ 2242 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) { 2243 arcmsr_hba_doorbell_isr(acb); 2244 } 2245 /* MU post queue interrupts*/ 2246 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) { 2247 arcmsr_hba_postqueue_isr(acb); 2248 } 2249 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { 2250 arcmsr_hba_message_isr(acb); 2251 } 2252 } 2253 /* 2254 ********************************************************************** 2255 ********************************************************************** 2256 */ 2257 static void arcmsr_handle_hbb_isr( struct AdapterControlBlock *acb) 2258 { 2259 u_int32_t outbound_doorbell; 2260 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 2261 /* 2262 ********************************************* 2263 ** check outbound intstatus 2264 ********************************************* 2265 */ 2266 outbound_doorbell = READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & acb->outbound_int_enable; 2267 if(!outbound_doorbell) { 2268 /*it must be share irq*/ 2269 return; 2270 } 2271 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ~outbound_doorbell); /* clear doorbell interrupt */ 2272 READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell); 2273 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 2274 /* MU ioctl transfer doorbell interrupts*/ 2275 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) { 2276 arcmsr_iop2drv_data_wrote_handle(acb); 2277 } 2278 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) { 2279 arcmsr_iop2drv_data_read_handle(acb); 2280 } 2281 /* MU post queue interrupts*/ 2282 if(outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) { 2283 arcmsr_hbb_postqueue_isr(acb); 2284 } 2285 if(outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) { 2286 arcmsr_hbb_message_isr(acb); 2287 } 2288 } 2289 /* 2290 ********************************************************************** 2291 ********************************************************************** 2292 */ 2293 static void arcmsr_handle_hbc_isr( struct AdapterControlBlock *acb) 2294 { 2295 u_int32_t host_interrupt_status; 2296 /* 2297 ********************************************* 2298 ** check outbound intstatus 2299 ********************************************* 2300 */ 2301 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & 2302 (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | 2303 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR); 2304 if(!host_interrupt_status) { 2305 /*it must be share irq*/ 2306 return; 2307 } 2308 do { 2309 /* MU doorbell interrupts*/ 2310 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) { 2311 arcmsr_hbc_doorbell_isr(acb); 2312 } 2313 /* MU post queue interrupts*/ 2314 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) { 2315 arcmsr_hbc_postqueue_isr(acb); 2316 } 2317 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status); 2318 } while (host_interrupt_status & (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR)); 2319 } 2320 /* 2321 ********************************************************************** 2322 ********************************************************************** 2323 */ 2324 static void arcmsr_handle_hbd_isr( struct AdapterControlBlock *acb) 2325 { 2326 u_int32_t host_interrupt_status; 2327 u_int32_t intmask_org; 2328 /* 2329 ********************************************* 2330 ** check outbound intstatus 2331 ********************************************* 2332 */ 2333 host_interrupt_status = CHIP_REG_READ32(HBD_MessageUnit, 0, host_int_status) & acb->outbound_int_enable; 2334 if(!(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_INT)) { 2335 /*it must be share irq*/ 2336 return; 2337 } 2338 /* disable outbound interrupt */ 2339 intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable) ; /* disable outbound message0 int */ 2340 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE); 2341 /* MU doorbell interrupts*/ 2342 if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT) { 2343 arcmsr_hbd_doorbell_isr(acb); 2344 } 2345 /* MU post queue interrupts*/ 2346 if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT) { 2347 arcmsr_hbd_postqueue_isr(acb); 2348 } 2349 /* enable all outbound interrupt */ 2350 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | ARCMSR_HBDMU_ALL_INT_ENABLE); 2351 // CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); 2352 } 2353 /* 2354 ********************************************************************** 2355 ********************************************************************** 2356 */ 2357 static void arcmsr_handle_hbe_isr( struct AdapterControlBlock *acb) 2358 { 2359 u_int32_t host_interrupt_status; 2360 /* 2361 ********************************************* 2362 ** check outbound intstatus 2363 ********************************************* 2364 */ 2365 host_interrupt_status = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_status) & 2366 (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | 2367 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR); 2368 if(!host_interrupt_status) { 2369 /*it must be share irq*/ 2370 return; 2371 } 2372 do { 2373 /* MU doorbell interrupts*/ 2374 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) { 2375 arcmsr_hbe_doorbell_isr(acb); 2376 } 2377 /* MU post queue interrupts*/ 2378 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) { 2379 arcmsr_hbe_postqueue_isr(acb); 2380 } 2381 host_interrupt_status = CHIP_REG_READ32(HBE_MessageUnit, 0, host_int_status); 2382 } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR)); 2383 } 2384 2385 static void arcmsr_handle_hbf_isr( struct AdapterControlBlock *acb) 2386 { 2387 u_int32_t host_interrupt_status; 2388 /* 2389 ********************************************* 2390 ** check outbound intstatus 2391 ********************************************* 2392 */ 2393 host_interrupt_status = CHIP_REG_READ32(HBF_MessageUnit, 0, host_int_status) & 2394 (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | 2395 ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR); 2396 if(!host_interrupt_status) { 2397 /*it must be share irq*/ 2398 return; 2399 } 2400 do { 2401 /* MU doorbell interrupts*/ 2402 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR) { 2403 arcmsr_hbe_doorbell_isr(acb); 2404 } 2405 /* MU post queue interrupts*/ 2406 if(host_interrupt_status & ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR) { 2407 arcmsr_hbf_postqueue_isr(acb); 2408 } 2409 host_interrupt_status = CHIP_REG_READ32(HBF_MessageUnit, 0, host_int_status); 2410 } while (host_interrupt_status & (ARCMSR_HBEMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBEMU_OUTBOUND_DOORBELL_ISR)); 2411 } 2412 /* 2413 ****************************************************************************** 2414 ****************************************************************************** 2415 */ 2416 static void arcmsr_interrupt(struct AdapterControlBlock *acb) 2417 { 2418 switch (acb->adapter_type) { 2419 case ACB_ADAPTER_TYPE_A: 2420 arcmsr_handle_hba_isr(acb); 2421 break; 2422 case ACB_ADAPTER_TYPE_B: 2423 arcmsr_handle_hbb_isr(acb); 2424 break; 2425 case ACB_ADAPTER_TYPE_C: 2426 arcmsr_handle_hbc_isr(acb); 2427 break; 2428 case ACB_ADAPTER_TYPE_D: 2429 arcmsr_handle_hbd_isr(acb); 2430 break; 2431 case ACB_ADAPTER_TYPE_E: 2432 arcmsr_handle_hbe_isr(acb); 2433 break; 2434 case ACB_ADAPTER_TYPE_F: 2435 arcmsr_handle_hbf_isr(acb); 2436 break; 2437 default: 2438 printf("arcmsr%d: interrupt service," 2439 " unknown adapter type =%d\n", acb->pci_unit, acb->adapter_type); 2440 break; 2441 } 2442 } 2443 /* 2444 ********************************************************************** 2445 ********************************************************************** 2446 */ 2447 static void arcmsr_intr_handler(void *arg) 2448 { 2449 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg; 2450 2451 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 2452 arcmsr_interrupt(acb); 2453 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 2454 } 2455 /* 2456 ****************************************************************************** 2457 ****************************************************************************** 2458 */ 2459 static void arcmsr_polling_devmap(void *arg) 2460 { 2461 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg; 2462 switch (acb->adapter_type) { 2463 case ACB_ADAPTER_TYPE_A: 2464 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2465 break; 2466 2467 case ACB_ADAPTER_TYPE_B: { 2468 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 2469 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG); 2470 } 2471 break; 2472 2473 case ACB_ADAPTER_TYPE_C: 2474 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2475 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 2476 break; 2477 2478 case ACB_ADAPTER_TYPE_D: 2479 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2480 break; 2481 2482 case ACB_ADAPTER_TYPE_E: 2483 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2484 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 2485 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 2486 break; 2487 2488 case ACB_ADAPTER_TYPE_F: { 2489 u_int32_t outMsg1 = CHIP_REG_READ32(HBF_MessageUnit, 0, outbound_msgaddr1); 2490 if (!(outMsg1 & ARCMSR_HBFMU_MESSAGE_FIRMWARE_OK) || 2491 (outMsg1 & ARCMSR_HBFMU_MESSAGE_NO_VOLUME_CHANGE)) 2492 goto nxt6s; 2493 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2494 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 2495 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 2496 break; 2497 } 2498 } 2499 nxt6s: 2500 if((acb->acb_flags & ACB_F_SCSISTOPADAPTER) == 0) 2501 { 2502 callout_reset(&acb->devmap_callout, 5 * hz, arcmsr_polling_devmap, acb); /* polling per 5 seconds */ 2503 } 2504 } 2505 2506 /* 2507 ******************************************************************************* 2508 ** 2509 ******************************************************************************* 2510 */ 2511 static void arcmsr_iop_parking(struct AdapterControlBlock *acb) 2512 { 2513 u_int32_t intmask_org; 2514 2515 if(acb != NULL) { 2516 /* stop adapter background rebuild */ 2517 if(acb->acb_flags & ACB_F_MSG_START_BGRB) { 2518 intmask_org = arcmsr_disable_allintr(acb); 2519 arcmsr_stop_adapter_bgrb(acb); 2520 arcmsr_flush_adapter_cache(acb); 2521 arcmsr_enable_allintr(acb, intmask_org); 2522 } 2523 } 2524 } 2525 /* 2526 *********************************************************************** 2527 ** 2528 ************************************************************************ 2529 */ 2530 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg) 2531 { 2532 struct CMD_MESSAGE_FIELD *pcmdmessagefld; 2533 u_int32_t retvalue = EINVAL; 2534 2535 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) arg; 2536 if(memcmp(pcmdmessagefld->cmdmessage.Signature, "ARCMSR", 6)!=0) { 2537 return retvalue; 2538 } 2539 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2540 switch(ioctl_cmd) { 2541 case ARCMSR_MESSAGE_READ_RQBUFFER: { 2542 u_int8_t *pQbuffer; 2543 u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer; 2544 u_int32_t allxfer_len=0; 2545 2546 while((acb->rqbuf_firstindex != acb->rqbuf_lastindex) 2547 && (allxfer_len < 1031)) { 2548 /*copy READ QBUFFER to srb*/ 2549 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex]; 2550 *ptmpQbuffer = *pQbuffer; 2551 acb->rqbuf_firstindex++; 2552 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 2553 /*if last index number set it to 0 */ 2554 ptmpQbuffer++; 2555 allxfer_len++; 2556 } 2557 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2558 struct QBUFFER *prbuffer; 2559 2560 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2561 prbuffer = arcmsr_get_iop_rqbuffer(acb); 2562 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 2563 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 2564 } 2565 pcmdmessagefld->cmdmessage.Length = allxfer_len; 2566 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2567 retvalue = ARCMSR_MESSAGE_SUCCESS; 2568 } 2569 break; 2570 case ARCMSR_MESSAGE_WRITE_WQBUFFER: { 2571 u_int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex; 2572 u_int8_t *pQbuffer; 2573 u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer; 2574 2575 user_len = pcmdmessagefld->cmdmessage.Length; 2576 /*check if data xfer length of this request will overflow my array qbuffer */ 2577 wqbuf_lastindex = acb->wqbuf_lastindex; 2578 wqbuf_firstindex = acb->wqbuf_firstindex; 2579 if(wqbuf_lastindex != wqbuf_firstindex) { 2580 arcmsr_Write_data_2iop_wqbuffer(acb); 2581 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2582 } else { 2583 my_empty_len = (wqbuf_firstindex - wqbuf_lastindex - 1) & 2584 (ARCMSR_MAX_QBUFFER - 1); 2585 if(my_empty_len >= user_len) { 2586 while(user_len > 0) { 2587 /*copy srb data to wqbuffer*/ 2588 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex]; 2589 *pQbuffer = *ptmpuserbuffer; 2590 acb->wqbuf_lastindex++; 2591 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 2592 /*if last index number set it to 0 */ 2593 ptmpuserbuffer++; 2594 user_len--; 2595 } 2596 /*post fist Qbuffer*/ 2597 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) { 2598 acb->acb_flags &= ~ACB_F_MESSAGE_WQBUFFER_CLEARED; 2599 arcmsr_Write_data_2iop_wqbuffer(acb); 2600 } 2601 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2602 } else { 2603 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2604 } 2605 } 2606 retvalue = ARCMSR_MESSAGE_SUCCESS; 2607 } 2608 break; 2609 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: { 2610 u_int8_t *pQbuffer = acb->rqbuffer; 2611 2612 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2613 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2614 arcmsr_iop_message_read(acb); 2615 /*signature, let IOP know data has been readed */ 2616 } 2617 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 2618 acb->rqbuf_firstindex = 0; 2619 acb->rqbuf_lastindex = 0; 2620 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2621 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2622 retvalue = ARCMSR_MESSAGE_SUCCESS; 2623 } 2624 break; 2625 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: 2626 { 2627 u_int8_t *pQbuffer = acb->wqbuffer; 2628 2629 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2630 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2631 arcmsr_iop_message_read(acb); 2632 /*signature, let IOP know data has been readed */ 2633 } 2634 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ); 2635 acb->wqbuf_firstindex = 0; 2636 acb->wqbuf_lastindex = 0; 2637 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2638 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2639 retvalue = ARCMSR_MESSAGE_SUCCESS; 2640 } 2641 break; 2642 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: { 2643 u_int8_t *pQbuffer; 2644 2645 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2646 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2647 arcmsr_iop_message_read(acb); 2648 /*signature, let IOP know data has been readed */ 2649 } 2650 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED 2651 |ACB_F_MESSAGE_RQBUFFER_CLEARED 2652 |ACB_F_MESSAGE_WQBUFFER_READ); 2653 acb->rqbuf_firstindex = 0; 2654 acb->rqbuf_lastindex = 0; 2655 acb->wqbuf_firstindex = 0; 2656 acb->wqbuf_lastindex = 0; 2657 pQbuffer = acb->rqbuffer; 2658 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 2659 pQbuffer = acb->wqbuffer; 2660 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 2661 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2662 retvalue = ARCMSR_MESSAGE_SUCCESS; 2663 } 2664 break; 2665 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: { 2666 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F; 2667 retvalue = ARCMSR_MESSAGE_SUCCESS; 2668 } 2669 break; 2670 case ARCMSR_MESSAGE_SAY_HELLO: { 2671 u_int8_t *hello_string = "Hello! I am ARCMSR"; 2672 u_int8_t *puserbuffer = (u_int8_t *)pcmdmessagefld->messagedatabuffer; 2673 2674 if(memcpy(puserbuffer, hello_string, (int16_t)strlen(hello_string))) { 2675 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2676 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2677 return ENOIOCTL; 2678 } 2679 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2680 retvalue = ARCMSR_MESSAGE_SUCCESS; 2681 } 2682 break; 2683 case ARCMSR_MESSAGE_SAY_GOODBYE: { 2684 arcmsr_iop_parking(acb); 2685 retvalue = ARCMSR_MESSAGE_SUCCESS; 2686 } 2687 break; 2688 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: { 2689 arcmsr_flush_adapter_cache(acb); 2690 retvalue = ARCMSR_MESSAGE_SUCCESS; 2691 } 2692 break; 2693 } 2694 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2695 return (retvalue); 2696 } 2697 /* 2698 ************************************************************************** 2699 ************************************************************************** 2700 */ 2701 static void arcmsr_free_srb(struct CommandControlBlock *srb) 2702 { 2703 struct AdapterControlBlock *acb; 2704 2705 acb = srb->acb; 2706 ARCMSR_LOCK_ACQUIRE(&acb->srb_lock); 2707 srb->srb_state = ARCMSR_SRB_DONE; 2708 srb->srb_flags = 0; 2709 acb->srbworkingQ[acb->workingsrb_doneindex] = srb; 2710 acb->workingsrb_doneindex++; 2711 acb->workingsrb_doneindex %= ARCMSR_MAX_FREESRB_NUM; 2712 ARCMSR_LOCK_RELEASE(&acb->srb_lock); 2713 } 2714 /* 2715 ************************************************************************** 2716 ************************************************************************** 2717 */ 2718 static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb) 2719 { 2720 struct CommandControlBlock *srb = NULL; 2721 u_int32_t workingsrb_startindex, workingsrb_doneindex; 2722 2723 ARCMSR_LOCK_ACQUIRE(&acb->srb_lock); 2724 workingsrb_doneindex = acb->workingsrb_doneindex; 2725 workingsrb_startindex = acb->workingsrb_startindex; 2726 srb = acb->srbworkingQ[workingsrb_startindex]; 2727 workingsrb_startindex++; 2728 workingsrb_startindex %= ARCMSR_MAX_FREESRB_NUM; 2729 if(workingsrb_doneindex != workingsrb_startindex) { 2730 acb->workingsrb_startindex = workingsrb_startindex; 2731 } else { 2732 srb = NULL; 2733 } 2734 ARCMSR_LOCK_RELEASE(&acb->srb_lock); 2735 return(srb); 2736 } 2737 /* 2738 ************************************************************************** 2739 ************************************************************************** 2740 */ 2741 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb) 2742 { 2743 struct CMD_MESSAGE_FIELD *pcmdmessagefld; 2744 int retvalue = 0, transfer_len = 0; 2745 char *buffer; 2746 uint8_t *ptr = scsiio_cdb_ptr(&pccb->csio); 2747 u_int32_t controlcode = (u_int32_t ) ptr[5] << 24 | 2748 (u_int32_t ) ptr[6] << 16 | 2749 (u_int32_t ) ptr[7] << 8 | 2750 (u_int32_t ) ptr[8]; 2751 /* 4 bytes: Areca io control code */ 2752 if ((pccb->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_VADDR) { 2753 buffer = pccb->csio.data_ptr; 2754 transfer_len = pccb->csio.dxfer_len; 2755 } else { 2756 retvalue = ARCMSR_MESSAGE_FAIL; 2757 goto message_out; 2758 } 2759 if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) { 2760 retvalue = ARCMSR_MESSAGE_FAIL; 2761 goto message_out; 2762 } 2763 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) buffer; 2764 switch(controlcode) { 2765 case ARCMSR_MESSAGE_READ_RQBUFFER: { 2766 u_int8_t *pQbuffer; 2767 u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer; 2768 int32_t allxfer_len = 0; 2769 2770 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2771 while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex) 2772 && (allxfer_len < 1031)) { 2773 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex]; 2774 *ptmpQbuffer = *pQbuffer; 2775 acb->rqbuf_firstindex++; 2776 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 2777 ptmpQbuffer++; 2778 allxfer_len++; 2779 } 2780 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2781 struct QBUFFER *prbuffer; 2782 2783 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2784 prbuffer = arcmsr_get_iop_rqbuffer(acb); 2785 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 2786 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 2787 } 2788 pcmdmessagefld->cmdmessage.Length = allxfer_len; 2789 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2790 retvalue = ARCMSR_MESSAGE_SUCCESS; 2791 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2792 } 2793 break; 2794 case ARCMSR_MESSAGE_WRITE_WQBUFFER: { 2795 int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex; 2796 u_int8_t *pQbuffer; 2797 u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer; 2798 2799 user_len = pcmdmessagefld->cmdmessage.Length; 2800 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2801 wqbuf_lastindex = acb->wqbuf_lastindex; 2802 wqbuf_firstindex = acb->wqbuf_firstindex; 2803 if (wqbuf_lastindex != wqbuf_firstindex) { 2804 arcmsr_Write_data_2iop_wqbuffer(acb); 2805 /* has error report sensedata */ 2806 if(pccb->csio.sense_len) { 2807 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); 2808 /* Valid,ErrorCode */ 2809 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05; 2810 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */ 2811 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A; 2812 /* AdditionalSenseLength */ 2813 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20; 2814 /* AdditionalSenseCode */ 2815 } 2816 retvalue = ARCMSR_MESSAGE_FAIL; 2817 } else { 2818 my_empty_len = (wqbuf_firstindex-wqbuf_lastindex - 1) 2819 &(ARCMSR_MAX_QBUFFER - 1); 2820 if (my_empty_len >= user_len) { 2821 while (user_len > 0) { 2822 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex]; 2823 *pQbuffer = *ptmpuserbuffer; 2824 acb->wqbuf_lastindex++; 2825 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 2826 ptmpuserbuffer++; 2827 user_len--; 2828 } 2829 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) { 2830 acb->acb_flags &= 2831 ~ACB_F_MESSAGE_WQBUFFER_CLEARED; 2832 arcmsr_Write_data_2iop_wqbuffer(acb); 2833 } 2834 } else { 2835 /* has error report sensedata */ 2836 if(pccb->csio.sense_len) { 2837 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); 2838 /* Valid,ErrorCode */ 2839 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05; 2840 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */ 2841 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A; 2842 /* AdditionalSenseLength */ 2843 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20; 2844 /* AdditionalSenseCode */ 2845 } 2846 retvalue = ARCMSR_MESSAGE_FAIL; 2847 } 2848 } 2849 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2850 } 2851 break; 2852 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: { 2853 u_int8_t *pQbuffer = acb->rqbuffer; 2854 2855 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2856 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2857 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2858 arcmsr_iop_message_read(acb); 2859 } 2860 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 2861 acb->rqbuf_firstindex = 0; 2862 acb->rqbuf_lastindex = 0; 2863 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2864 pcmdmessagefld->cmdmessage.ReturnCode = 2865 ARCMSR_MESSAGE_RETURNCODE_OK; 2866 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2867 } 2868 break; 2869 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: { 2870 u_int8_t *pQbuffer = acb->wqbuffer; 2871 2872 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2873 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2874 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2875 arcmsr_iop_message_read(acb); 2876 } 2877 acb->acb_flags |= 2878 (ACB_F_MESSAGE_WQBUFFER_CLEARED | 2879 ACB_F_MESSAGE_WQBUFFER_READ); 2880 acb->wqbuf_firstindex = 0; 2881 acb->wqbuf_lastindex = 0; 2882 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2883 pcmdmessagefld->cmdmessage.ReturnCode = 2884 ARCMSR_MESSAGE_RETURNCODE_OK; 2885 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2886 } 2887 break; 2888 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: { 2889 u_int8_t *pQbuffer; 2890 2891 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2892 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2893 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2894 arcmsr_iop_message_read(acb); 2895 } 2896 acb->acb_flags |= 2897 (ACB_F_MESSAGE_WQBUFFER_CLEARED 2898 | ACB_F_MESSAGE_RQBUFFER_CLEARED 2899 | ACB_F_MESSAGE_WQBUFFER_READ); 2900 acb->rqbuf_firstindex = 0; 2901 acb->rqbuf_lastindex = 0; 2902 acb->wqbuf_firstindex = 0; 2903 acb->wqbuf_lastindex = 0; 2904 pQbuffer = acb->rqbuffer; 2905 memset(pQbuffer, 0, sizeof (struct QBUFFER)); 2906 pQbuffer = acb->wqbuffer; 2907 memset(pQbuffer, 0, sizeof (struct QBUFFER)); 2908 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2909 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2910 } 2911 break; 2912 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: { 2913 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F; 2914 } 2915 break; 2916 case ARCMSR_MESSAGE_SAY_HELLO: { 2917 int8_t *hello_string = "Hello! I am ARCMSR"; 2918 2919 memcpy(pcmdmessagefld->messagedatabuffer, hello_string 2920 , (int16_t)strlen(hello_string)); 2921 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2922 } 2923 break; 2924 case ARCMSR_MESSAGE_SAY_GOODBYE: 2925 arcmsr_iop_parking(acb); 2926 break; 2927 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: 2928 arcmsr_flush_adapter_cache(acb); 2929 break; 2930 default: 2931 retvalue = ARCMSR_MESSAGE_FAIL; 2932 } 2933 message_out: 2934 return (retvalue); 2935 } 2936 /* 2937 ********************************************************************* 2938 ********************************************************************* 2939 */ 2940 static void arcmsr_execute_srb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 2941 { 2942 struct CommandControlBlock *srb = (struct CommandControlBlock *)arg; 2943 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)srb->acb; 2944 union ccb *pccb; 2945 int target, lun; 2946 2947 pccb = srb->pccb; 2948 target = pccb->ccb_h.target_id; 2949 lun = pccb->ccb_h.target_lun; 2950 acb->pktRequestCount++; 2951 if(error != 0) { 2952 if(error != EFBIG) { 2953 printf("arcmsr%d: unexpected error %x" 2954 " returned from 'bus_dmamap_load' \n" 2955 , acb->pci_unit, error); 2956 } 2957 if((pccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_INPROG) { 2958 pccb->ccb_h.status |= CAM_REQ_TOO_BIG; 2959 } 2960 arcmsr_srb_complete(srb, 0); 2961 return; 2962 } 2963 if(nseg > ARCMSR_MAX_SG_ENTRIES) { 2964 pccb->ccb_h.status |= CAM_REQ_TOO_BIG; 2965 arcmsr_srb_complete(srb, 0); 2966 return; 2967 } 2968 if(acb->acb_flags & ACB_F_BUS_RESET) { 2969 printf("arcmsr%d: bus reset and return busy \n", acb->pci_unit); 2970 pccb->ccb_h.status |= CAM_SCSI_BUS_RESET; 2971 arcmsr_srb_complete(srb, 0); 2972 return; 2973 } 2974 if(acb->devstate[target][lun] == ARECA_RAID_GONE) { 2975 u_int8_t block_cmd, cmd; 2976 2977 cmd = scsiio_cdb_ptr(&pccb->csio)[0]; 2978 block_cmd = cmd & 0x0f; 2979 if(block_cmd == 0x08 || block_cmd == 0x0a) { 2980 printf("arcmsr%d:block 'read/write' command " 2981 "with gone raid volume Cmd=0x%2x, TargetId=%d, Lun=%d \n" 2982 , acb->pci_unit, cmd, target, lun); 2983 pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 2984 arcmsr_srb_complete(srb, 0); 2985 return; 2986 } 2987 } 2988 if((pccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_INPROG) { 2989 if(nseg != 0) { 2990 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap); 2991 } 2992 arcmsr_srb_complete(srb, 0); 2993 return; 2994 } 2995 if(acb->srboutstandingcount >= acb->maxOutstanding) { 2996 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) == 0) 2997 { 2998 xpt_freeze_simq(acb->psim, 1); 2999 acb->acb_flags |= ACB_F_CAM_DEV_QFRZN; 3000 } 3001 pccb->ccb_h.status &= ~CAM_SIM_QUEUED; 3002 pccb->ccb_h.status |= CAM_REQUEUE_REQ; 3003 arcmsr_srb_complete(srb, 0); 3004 return; 3005 } 3006 pccb->ccb_h.status |= CAM_SIM_QUEUED; 3007 arcmsr_build_srb(srb, dm_segs, nseg); 3008 arcmsr_post_srb(acb, srb); 3009 if (pccb->ccb_h.timeout != CAM_TIME_INFINITY) 3010 { 3011 arcmsr_callout_init(&srb->ccb_callout); 3012 callout_reset_sbt(&srb->ccb_callout, SBT_1MS * 3013 (pccb->ccb_h.timeout + (ARCMSR_TIMEOUT_DELAY * 1000)), 0, 3014 arcmsr_srb_timeout, srb, 0); 3015 srb->srb_flags |= SRB_FLAG_TIMER_START; 3016 } 3017 } 3018 /* 3019 ***************************************************************************************** 3020 ***************************************************************************************** 3021 */ 3022 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb) 3023 { 3024 struct CommandControlBlock *srb; 3025 struct AdapterControlBlock *acb = (struct AdapterControlBlock *) abortccb->ccb_h.arcmsr_ccbacb_ptr; 3026 u_int32_t intmask_org; 3027 int i = 0; 3028 3029 acb->num_aborts++; 3030 /* 3031 *************************************************************************** 3032 ** It is the upper layer do abort command this lock just prior to calling us. 3033 ** First determine if we currently own this command. 3034 ** Start by searching the device queue. If not found 3035 ** at all, and the system wanted us to just abort the 3036 ** command return success. 3037 *************************************************************************** 3038 */ 3039 if(acb->srboutstandingcount != 0) { 3040 /* disable all outbound interrupt */ 3041 intmask_org = arcmsr_disable_allintr(acb); 3042 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 3043 srb = acb->psrb_pool[i]; 3044 if(srb->srb_state == ARCMSR_SRB_START) { 3045 if(srb->pccb == abortccb) { 3046 srb->srb_state = ARCMSR_SRB_ABORTED; 3047 printf("arcmsr%d:scsi id=%d lun=%jx abort srb '%p'" 3048 "outstanding command \n" 3049 , acb->pci_unit, abortccb->ccb_h.target_id 3050 , (uintmax_t)abortccb->ccb_h.target_lun, srb); 3051 arcmsr_polling_srbdone(acb, srb); 3052 /* enable outbound Post Queue, outbound doorbell Interrupt */ 3053 arcmsr_enable_allintr(acb, intmask_org); 3054 return (TRUE); 3055 } 3056 } 3057 } 3058 /* enable outbound Post Queue, outbound doorbell Interrupt */ 3059 arcmsr_enable_allintr(acb, intmask_org); 3060 } 3061 return(FALSE); 3062 } 3063 /* 3064 **************************************************************************** 3065 **************************************************************************** 3066 */ 3067 static void arcmsr_bus_reset(struct AdapterControlBlock *acb) 3068 { 3069 int retry = 0; 3070 3071 acb->num_resets++; 3072 acb->acb_flags |= ACB_F_BUS_RESET; 3073 while(acb->srboutstandingcount != 0 && retry < 400) { 3074 arcmsr_interrupt(acb); 3075 UDELAY(25000); 3076 retry++; 3077 } 3078 arcmsr_iop_reset(acb); 3079 acb->acb_flags &= ~ACB_F_BUS_RESET; 3080 } 3081 /* 3082 ************************************************************************** 3083 ************************************************************************** 3084 */ 3085 static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb, 3086 union ccb *pccb) 3087 { 3088 if (pccb->ccb_h.target_lun) { 3089 pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 3090 xpt_done(pccb); 3091 return; 3092 } 3093 pccb->ccb_h.status |= CAM_REQ_CMP; 3094 switch (scsiio_cdb_ptr(&pccb->csio)[0]) { 3095 case INQUIRY: { 3096 unsigned char inqdata[36]; 3097 char *buffer = pccb->csio.data_ptr; 3098 3099 inqdata[0] = T_PROCESSOR; /* Periph Qualifier & Periph Dev Type */ 3100 inqdata[1] = 0; /* rem media bit & Dev Type Modifier */ 3101 inqdata[2] = 0; /* ISO, ECMA, & ANSI versions */ 3102 inqdata[3] = 0; 3103 inqdata[4] = 31; /* length of additional data */ 3104 inqdata[5] = 0; 3105 inqdata[6] = 0; 3106 inqdata[7] = 0; 3107 strncpy(&inqdata[8], "Areca ", 8); /* Vendor Identification */ 3108 strncpy(&inqdata[16], "RAID controller ", 16); /* Product Identification */ 3109 strncpy(&inqdata[32], "R001", 4); /* Product Revision */ 3110 memcpy(buffer, inqdata, sizeof(inqdata)); 3111 xpt_done(pccb); 3112 } 3113 break; 3114 case WRITE_BUFFER: 3115 case READ_BUFFER: { 3116 if (arcmsr_iop_message_xfer(acb, pccb)) { 3117 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 3118 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 3119 } 3120 xpt_done(pccb); 3121 } 3122 break; 3123 default: 3124 xpt_done(pccb); 3125 } 3126 } 3127 /* 3128 ********************************************************************* 3129 ********************************************************************* 3130 */ 3131 static void arcmsr_action(struct cam_sim *psim, union ccb *pccb) 3132 { 3133 struct AdapterControlBlock *acb; 3134 3135 acb = (struct AdapterControlBlock *) cam_sim_softc(psim); 3136 if(acb == NULL) { 3137 pccb->ccb_h.status |= CAM_REQ_INVALID; 3138 xpt_done(pccb); 3139 return; 3140 } 3141 switch (pccb->ccb_h.func_code) { 3142 case XPT_SCSI_IO: { 3143 struct CommandControlBlock *srb; 3144 int target = pccb->ccb_h.target_id; 3145 int error; 3146 3147 if (pccb->ccb_h.flags & CAM_CDB_PHYS) { 3148 pccb->ccb_h.status = CAM_REQ_INVALID; 3149 xpt_done(pccb); 3150 return; 3151 } 3152 3153 if(target == 16) { 3154 /* virtual device for iop message transfer */ 3155 arcmsr_handle_virtual_command(acb, pccb); 3156 return; 3157 } 3158 if((srb = arcmsr_get_freesrb(acb)) == NULL) { 3159 pccb->ccb_h.status |= CAM_RESRC_UNAVAIL; 3160 xpt_done(pccb); 3161 return; 3162 } 3163 pccb->ccb_h.arcmsr_ccbsrb_ptr = srb; 3164 pccb->ccb_h.arcmsr_ccbacb_ptr = acb; 3165 srb->pccb = pccb; 3166 error = bus_dmamap_load_ccb(acb->dm_segs_dmat 3167 , srb->dm_segs_dmamap 3168 , pccb 3169 , arcmsr_execute_srb, srb, /*flags*/0); 3170 if(error == EINPROGRESS) { 3171 xpt_freeze_simq(acb->psim, 1); 3172 pccb->ccb_h.status |= CAM_RELEASE_SIMQ; 3173 } 3174 break; 3175 } 3176 case XPT_PATH_INQ: { 3177 struct ccb_pathinq *cpi = &pccb->cpi; 3178 3179 cpi->version_num = 1; 3180 cpi->hba_inquiry = PI_SDTR_ABLE | PI_TAG_ABLE; 3181 cpi->target_sprt = 0; 3182 cpi->hba_misc = 0; 3183 cpi->hba_eng_cnt = 0; 3184 cpi->max_target = ARCMSR_MAX_TARGETID; /* 0-16 */ 3185 cpi->max_lun = ARCMSR_MAX_TARGETLUN; /* 0-7 */ 3186 cpi->initiator_id = ARCMSR_SCSI_INITIATOR_ID; /* 255 */ 3187 cpi->bus_id = cam_sim_bus(psim); 3188 strlcpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 3189 strlcpy(cpi->hba_vid, "ARCMSR", HBA_IDLEN); 3190 strlcpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN); 3191 cpi->unit_number = cam_sim_unit(psim); 3192 if(acb->adapter_bus_speed == ACB_BUS_SPEED_12G) 3193 cpi->base_transfer_speed = 1200000; 3194 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G) 3195 cpi->base_transfer_speed = 600000; 3196 else 3197 cpi->base_transfer_speed = 300000; 3198 if((acb->vendor_device_id == PCIDevVenIDARC1880) || 3199 (acb->vendor_device_id == PCIDevVenIDARC1884) || 3200 (acb->vendor_device_id == PCIDevVenIDARC1680) || 3201 (acb->vendor_device_id == PCIDevVenIDARC1214)) 3202 { 3203 cpi->transport = XPORT_SAS; 3204 cpi->transport_version = 0; 3205 cpi->protocol_version = SCSI_REV_SPC2; 3206 } 3207 else 3208 { 3209 cpi->transport = XPORT_SPI; 3210 cpi->transport_version = 2; 3211 cpi->protocol_version = SCSI_REV_2; 3212 } 3213 cpi->protocol = PROTO_SCSI; 3214 cpi->ccb_h.status |= CAM_REQ_CMP; 3215 xpt_done(pccb); 3216 break; 3217 } 3218 case XPT_ABORT: { 3219 union ccb *pabort_ccb; 3220 3221 pabort_ccb = pccb->cab.abort_ccb; 3222 switch (pabort_ccb->ccb_h.func_code) { 3223 case XPT_ACCEPT_TARGET_IO: 3224 case XPT_CONT_TARGET_IO: 3225 if(arcmsr_seek_cmd2abort(pabort_ccb)==TRUE) { 3226 pabort_ccb->ccb_h.status |= CAM_REQ_ABORTED; 3227 xpt_done(pabort_ccb); 3228 pccb->ccb_h.status |= CAM_REQ_CMP; 3229 } else { 3230 xpt_print_path(pabort_ccb->ccb_h.path); 3231 printf("Not found\n"); 3232 pccb->ccb_h.status |= CAM_PATH_INVALID; 3233 } 3234 break; 3235 case XPT_SCSI_IO: 3236 pccb->ccb_h.status |= CAM_UA_ABORT; 3237 break; 3238 default: 3239 pccb->ccb_h.status |= CAM_REQ_INVALID; 3240 break; 3241 } 3242 xpt_done(pccb); 3243 break; 3244 } 3245 case XPT_RESET_BUS: 3246 case XPT_RESET_DEV: { 3247 u_int32_t i; 3248 3249 arcmsr_bus_reset(acb); 3250 for (i=0; i < 500; i++) { 3251 DELAY(1000); 3252 } 3253 pccb->ccb_h.status |= CAM_REQ_CMP; 3254 xpt_done(pccb); 3255 break; 3256 } 3257 case XPT_TERM_IO: { 3258 pccb->ccb_h.status |= CAM_REQ_INVALID; 3259 xpt_done(pccb); 3260 break; 3261 } 3262 case XPT_GET_TRAN_SETTINGS: { 3263 struct ccb_trans_settings *cts; 3264 3265 if(pccb->ccb_h.target_id == 16) { 3266 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 3267 xpt_done(pccb); 3268 break; 3269 } 3270 cts = &pccb->cts; 3271 { 3272 struct ccb_trans_settings_scsi *scsi; 3273 struct ccb_trans_settings_spi *spi; 3274 struct ccb_trans_settings_sas *sas; 3275 3276 scsi = &cts->proto_specific.scsi; 3277 scsi->flags = CTS_SCSI_FLAGS_TAG_ENB; 3278 scsi->valid = CTS_SCSI_VALID_TQ; 3279 cts->protocol = PROTO_SCSI; 3280 3281 if((acb->vendor_device_id == PCIDevVenIDARC1880) || 3282 (acb->vendor_device_id == PCIDevVenIDARC1884) || 3283 (acb->vendor_device_id == PCIDevVenIDARC1680) || 3284 (acb->vendor_device_id == PCIDevVenIDARC1214)) 3285 { 3286 cts->protocol_version = SCSI_REV_SPC2; 3287 cts->transport_version = 0; 3288 cts->transport = XPORT_SAS; 3289 sas = &cts->xport_specific.sas; 3290 sas->valid = CTS_SAS_VALID_SPEED; 3291 if (acb->adapter_bus_speed == ACB_BUS_SPEED_12G) 3292 sas->bitrate = 1200000; 3293 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G) 3294 sas->bitrate = 600000; 3295 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_3G) 3296 sas->bitrate = 300000; 3297 } 3298 else 3299 { 3300 cts->protocol_version = SCSI_REV_2; 3301 cts->transport_version = 2; 3302 cts->transport = XPORT_SPI; 3303 spi = &cts->xport_specific.spi; 3304 spi->flags = CTS_SPI_FLAGS_DISC_ENB; 3305 if (acb->adapter_bus_speed == ACB_BUS_SPEED_6G) 3306 spi->sync_period = 1; 3307 else 3308 spi->sync_period = 2; 3309 spi->sync_offset = 32; 3310 spi->bus_width = MSG_EXT_WDTR_BUS_16_BIT; 3311 spi->valid = CTS_SPI_VALID_DISC 3312 | CTS_SPI_VALID_SYNC_RATE 3313 | CTS_SPI_VALID_SYNC_OFFSET 3314 | CTS_SPI_VALID_BUS_WIDTH; 3315 } 3316 } 3317 pccb->ccb_h.status |= CAM_REQ_CMP; 3318 xpt_done(pccb); 3319 break; 3320 } 3321 case XPT_SET_TRAN_SETTINGS: { 3322 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 3323 xpt_done(pccb); 3324 break; 3325 } 3326 case XPT_CALC_GEOMETRY: 3327 if(pccb->ccb_h.target_id == 16) { 3328 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 3329 xpt_done(pccb); 3330 break; 3331 } 3332 cam_calc_geometry(&pccb->ccg, 1); 3333 xpt_done(pccb); 3334 break; 3335 default: 3336 pccb->ccb_h.status |= CAM_REQ_INVALID; 3337 xpt_done(pccb); 3338 break; 3339 } 3340 } 3341 /* 3342 ********************************************************************** 3343 ********************************************************************** 3344 */ 3345 static void arcmsr_start_hba_bgrb(struct AdapterControlBlock *acb) 3346 { 3347 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3348 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3349 if(!arcmsr_hba_wait_msgint_ready(acb)) { 3350 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3351 } 3352 } 3353 /* 3354 ********************************************************************** 3355 ********************************************************************** 3356 */ 3357 static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb) 3358 { 3359 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3360 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3361 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_START_BGRB); 3362 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3363 printf( "arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3364 } 3365 } 3366 /* 3367 ********************************************************************** 3368 ********************************************************************** 3369 */ 3370 static void arcmsr_start_hbc_bgrb(struct AdapterControlBlock *acb) 3371 { 3372 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3373 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3374 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3375 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 3376 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3377 } 3378 } 3379 /* 3380 ********************************************************************** 3381 ********************************************************************** 3382 */ 3383 static void arcmsr_start_hbd_bgrb(struct AdapterControlBlock *acb) 3384 { 3385 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3386 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3387 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 3388 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3389 } 3390 } 3391 /* 3392 ********************************************************************** 3393 ********************************************************************** 3394 */ 3395 static void arcmsr_start_hbe_bgrb(struct AdapterControlBlock *acb) 3396 { 3397 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3398 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3399 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 3400 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 3401 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 3402 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3403 } 3404 } 3405 /* 3406 ********************************************************************** 3407 ********************************************************************** 3408 */ 3409 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb) 3410 { 3411 switch (acb->adapter_type) { 3412 case ACB_ADAPTER_TYPE_A: 3413 arcmsr_start_hba_bgrb(acb); 3414 break; 3415 case ACB_ADAPTER_TYPE_B: 3416 arcmsr_start_hbb_bgrb(acb); 3417 break; 3418 case ACB_ADAPTER_TYPE_C: 3419 arcmsr_start_hbc_bgrb(acb); 3420 break; 3421 case ACB_ADAPTER_TYPE_D: 3422 arcmsr_start_hbd_bgrb(acb); 3423 break; 3424 case ACB_ADAPTER_TYPE_E: 3425 case ACB_ADAPTER_TYPE_F: 3426 arcmsr_start_hbe_bgrb(acb); 3427 break; 3428 } 3429 } 3430 /* 3431 ********************************************************************** 3432 ** 3433 ********************************************************************** 3434 */ 3435 static void arcmsr_polling_hba_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3436 { 3437 struct CommandControlBlock *srb; 3438 u_int32_t flag_srb, outbound_intstatus, poll_srb_done=0, poll_count=0; 3439 u_int16_t error; 3440 3441 polling_ccb_retry: 3442 poll_count++; 3443 outbound_intstatus=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 3444 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus); /*clear interrupt*/ 3445 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3446 while(1) { 3447 if((flag_srb = CHIP_REG_READ32(HBA_MessageUnit, 3448 0, outbound_queueport)) == 0xFFFFFFFF) { 3449 if(poll_srb_done) { 3450 break;/*chip FIFO no ccb for completion already*/ 3451 } else { 3452 UDELAY(25000); 3453 if ((poll_count > 100) && (poll_srb != NULL)) { 3454 break; 3455 } 3456 goto polling_ccb_retry; 3457 } 3458 } 3459 /* check if command done with no error*/ 3460 srb = (struct CommandControlBlock *) 3461 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 3462 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 3463 poll_srb_done = (srb == poll_srb) ? 1:0; 3464 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3465 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3466 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'" 3467 "poll command abort successfully \n" 3468 , acb->pci_unit 3469 , srb->pccb->ccb_h.target_id 3470 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3471 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3472 arcmsr_srb_complete(srb, 1); 3473 continue; 3474 } 3475 printf("arcmsr%d: polling get an illegal srb command done srb='%p'" 3476 "srboutstandingcount=%d \n" 3477 , acb->pci_unit 3478 , srb, acb->srboutstandingcount); 3479 continue; 3480 } 3481 arcmsr_report_srb_state(acb, srb, error); 3482 } /*drain reply FIFO*/ 3483 } 3484 /* 3485 ********************************************************************** 3486 ** 3487 ********************************************************************** 3488 */ 3489 static void arcmsr_polling_hbb_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3490 { 3491 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3492 struct CommandControlBlock *srb; 3493 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3494 int index; 3495 u_int16_t error; 3496 3497 polling_ccb_retry: 3498 poll_count++; 3499 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */ 3500 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3501 while(1) { 3502 index = phbbmu->doneq_index; 3503 if((flag_srb = phbbmu->done_qbuffer[index]) == 0) { 3504 if(poll_srb_done) { 3505 break;/*chip FIFO no ccb for completion already*/ 3506 } else { 3507 UDELAY(25000); 3508 if ((poll_count > 100) && (poll_srb != NULL)) { 3509 break; 3510 } 3511 goto polling_ccb_retry; 3512 } 3513 } 3514 phbbmu->done_qbuffer[index] = 0; 3515 index++; 3516 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 3517 phbbmu->doneq_index = index; 3518 /* check if command done with no error*/ 3519 srb = (struct CommandControlBlock *) 3520 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 3521 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 3522 poll_srb_done = (srb == poll_srb) ? 1:0; 3523 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3524 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3525 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'" 3526 "poll command abort successfully \n" 3527 , acb->pci_unit 3528 , srb->pccb->ccb_h.target_id 3529 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3530 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3531 arcmsr_srb_complete(srb, 1); 3532 continue; 3533 } 3534 printf("arcmsr%d: polling get an illegal srb command done srb='%p'" 3535 "srboutstandingcount=%d \n" 3536 , acb->pci_unit 3537 , srb, acb->srboutstandingcount); 3538 continue; 3539 } 3540 arcmsr_report_srb_state(acb, srb, error); 3541 } /*drain reply FIFO*/ 3542 } 3543 /* 3544 ********************************************************************** 3545 ** 3546 ********************************************************************** 3547 */ 3548 static void arcmsr_polling_hbc_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3549 { 3550 struct CommandControlBlock *srb; 3551 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3552 u_int16_t error; 3553 3554 polling_ccb_retry: 3555 poll_count++; 3556 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3557 while(1) { 3558 if(!(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)) { 3559 if(poll_srb_done) { 3560 break;/*chip FIFO no ccb for completion already*/ 3561 } else { 3562 UDELAY(25000); 3563 if ((poll_count > 100) && (poll_srb != NULL)) { 3564 break; 3565 } 3566 if (acb->srboutstandingcount == 0) { 3567 break; 3568 } 3569 goto polling_ccb_retry; 3570 } 3571 } 3572 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 3573 /* check if command done with no error*/ 3574 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/ 3575 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE; 3576 if (poll_srb != NULL) 3577 poll_srb_done = (srb == poll_srb) ? 1:0; 3578 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3579 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3580 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n" 3581 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3582 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3583 arcmsr_srb_complete(srb, 1); 3584 continue; 3585 } 3586 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 3587 , acb->pci_unit, srb, acb->srboutstandingcount); 3588 continue; 3589 } 3590 arcmsr_report_srb_state(acb, srb, error); 3591 } /*drain reply FIFO*/ 3592 } 3593 /* 3594 ********************************************************************** 3595 ** 3596 ********************************************************************** 3597 */ 3598 static void arcmsr_polling_hbd_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3599 { 3600 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 3601 struct CommandControlBlock *srb; 3602 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3603 u_int32_t outbound_write_pointer; 3604 u_int16_t error, doneq_index; 3605 3606 polling_ccb_retry: 3607 poll_count++; 3608 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3609 while(1) { 3610 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 3611 doneq_index = phbdmu->doneq_index; 3612 if ((outbound_write_pointer & 0xFF) == (doneq_index & 0xFF)) { 3613 if(poll_srb_done) { 3614 break;/*chip FIFO no ccb for completion already*/ 3615 } else { 3616 UDELAY(25000); 3617 if ((poll_count > 100) && (poll_srb != NULL)) { 3618 break; 3619 } 3620 if (acb->srboutstandingcount == 0) { 3621 break; 3622 } 3623 goto polling_ccb_retry; 3624 } 3625 } 3626 doneq_index = arcmsr_get_doneq_index(phbdmu); 3627 flag_srb = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow; 3628 /* check if command done with no error*/ 3629 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/ 3630 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 3631 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index); 3632 if (poll_srb != NULL) 3633 poll_srb_done = (srb == poll_srb) ? 1:0; 3634 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3635 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3636 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n" 3637 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3638 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3639 arcmsr_srb_complete(srb, 1); 3640 continue; 3641 } 3642 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 3643 , acb->pci_unit, srb, acb->srboutstandingcount); 3644 continue; 3645 } 3646 arcmsr_report_srb_state(acb, srb, error); 3647 } /*drain reply FIFO*/ 3648 } 3649 /* 3650 ********************************************************************** 3651 ** 3652 ********************************************************************** 3653 */ 3654 static void arcmsr_polling_hbe_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3655 { 3656 struct CommandControlBlock *srb; 3657 u_int32_t poll_srb_done=0, poll_count=0, doneq_index; 3658 u_int16_t error, cmdSMID; 3659 3660 polling_ccb_retry: 3661 poll_count++; 3662 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3663 while(1) { 3664 doneq_index = acb->doneq_index; 3665 if((CHIP_REG_READ32(HBE_MessageUnit, 0, reply_post_producer_index) & 0xFFFF) == doneq_index) { 3666 if(poll_srb_done) { 3667 break;/*chip FIFO no ccb for completion already*/ 3668 } else { 3669 UDELAY(25000); 3670 if ((poll_count > 100) && (poll_srb != NULL)) { 3671 break; 3672 } 3673 if (acb->srboutstandingcount == 0) { 3674 break; 3675 } 3676 goto polling_ccb_retry; 3677 } 3678 } 3679 cmdSMID = acb->pCompletionQ[doneq_index].cmdSMID; 3680 doneq_index++; 3681 if (doneq_index >= acb->completionQ_entry) 3682 doneq_index = 0; 3683 acb->doneq_index = doneq_index; 3684 srb = acb->psrb_pool[cmdSMID]; 3685 error = (acb->pCompletionQ[doneq_index].cmdFlag & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 3686 if (poll_srb != NULL) 3687 poll_srb_done = (srb == poll_srb) ? 1:0; 3688 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3689 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3690 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n" 3691 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3692 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3693 arcmsr_srb_complete(srb, 1); 3694 continue; 3695 } 3696 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 3697 , acb->pci_unit, srb, acb->srboutstandingcount); 3698 continue; 3699 } 3700 arcmsr_report_srb_state(acb, srb, error); 3701 } /*drain reply FIFO*/ 3702 CHIP_REG_WRITE32(HBE_MessageUnit, 0, reply_post_producer_index, doneq_index); 3703 } 3704 /* 3705 ********************************************************************** 3706 ********************************************************************** 3707 */ 3708 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3709 { 3710 switch (acb->adapter_type) { 3711 case ACB_ADAPTER_TYPE_A: 3712 arcmsr_polling_hba_srbdone(acb, poll_srb); 3713 break; 3714 case ACB_ADAPTER_TYPE_B: 3715 arcmsr_polling_hbb_srbdone(acb, poll_srb); 3716 break; 3717 case ACB_ADAPTER_TYPE_C: 3718 arcmsr_polling_hbc_srbdone(acb, poll_srb); 3719 break; 3720 case ACB_ADAPTER_TYPE_D: 3721 arcmsr_polling_hbd_srbdone(acb, poll_srb); 3722 break; 3723 case ACB_ADAPTER_TYPE_E: 3724 case ACB_ADAPTER_TYPE_F: 3725 arcmsr_polling_hbe_srbdone(acb, poll_srb); 3726 break; 3727 } 3728 } 3729 /* 3730 ********************************************************************** 3731 ********************************************************************** 3732 */ 3733 static void arcmsr_get_hba_config(struct AdapterControlBlock *acb) 3734 { 3735 char *acb_firm_model = acb->firm_model; 3736 char *acb_firm_version = acb->firm_version; 3737 char *acb_device_map = acb->device_map; 3738 size_t iop_firm_model = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3739 size_t iop_firm_version = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3740 size_t iop_device_map = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3741 int i; 3742 3743 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3744 if(!arcmsr_hba_wait_msgint_ready(acb)) { 3745 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3746 } 3747 i = 0; 3748 while(i < 8) { 3749 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3750 /* 8 bytes firm_model, 15, 60-67*/ 3751 acb_firm_model++; 3752 i++; 3753 } 3754 i=0; 3755 while(i < 16) { 3756 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3757 /* 16 bytes firm_version, 17, 68-83*/ 3758 acb_firm_version++; 3759 i++; 3760 } 3761 i=0; 3762 while(i < 16) { 3763 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3764 acb_device_map++; 3765 i++; 3766 } 3767 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3768 acb->firm_request_len = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3769 acb->firm_numbers_queue = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3770 acb->firm_sdram_size = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3771 acb->firm_ide_channels = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3772 acb->firm_cfg_version = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3773 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 3774 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 3775 else 3776 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3777 } 3778 /* 3779 ********************************************************************** 3780 ********************************************************************** 3781 */ 3782 static void arcmsr_get_hbb_config(struct AdapterControlBlock *acb) 3783 { 3784 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3785 char *acb_firm_model = acb->firm_model; 3786 char *acb_firm_version = acb->firm_version; 3787 char *acb_device_map = acb->device_map; 3788 size_t iop_firm_model = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3789 size_t iop_firm_version = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3790 size_t iop_device_map = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3791 int i; 3792 3793 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG); 3794 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3795 printf( "arcmsr%d: wait" "'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3796 } 3797 i = 0; 3798 while(i < 8) { 3799 *acb_firm_model = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_model+i); 3800 /* 8 bytes firm_model, 15, 60-67*/ 3801 acb_firm_model++; 3802 i++; 3803 } 3804 i = 0; 3805 while(i < 16) { 3806 *acb_firm_version = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_version+i); 3807 /* 16 bytes firm_version, 17, 68-83*/ 3808 acb_firm_version++; 3809 i++; 3810 } 3811 i = 0; 3812 while(i < 16) { 3813 *acb_device_map = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_device_map+i); 3814 acb_device_map++; 3815 i++; 3816 } 3817 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3818 acb->firm_request_len = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3819 acb->firm_numbers_queue = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3820 acb->firm_sdram_size = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3821 acb->firm_ide_channels = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3822 acb->firm_cfg_version = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3823 if(acb->firm_numbers_queue > ARCMSR_MAX_HBB_POSTQUEUE) 3824 acb->maxOutstanding = ARCMSR_MAX_HBB_POSTQUEUE - 1; 3825 else 3826 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3827 } 3828 /* 3829 ********************************************************************** 3830 ********************************************************************** 3831 */ 3832 static void arcmsr_get_hbc_config(struct AdapterControlBlock *acb) 3833 { 3834 char *acb_firm_model = acb->firm_model; 3835 char *acb_firm_version = acb->firm_version; 3836 char *acb_device_map = acb->device_map; 3837 size_t iop_firm_model = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3838 size_t iop_firm_version = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3839 size_t iop_device_map = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3840 int i; 3841 3842 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3843 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3844 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 3845 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3846 } 3847 i = 0; 3848 while(i < 8) { 3849 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3850 /* 8 bytes firm_model, 15, 60-67*/ 3851 acb_firm_model++; 3852 i++; 3853 } 3854 i = 0; 3855 while(i < 16) { 3856 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3857 /* 16 bytes firm_version, 17, 68-83*/ 3858 acb_firm_version++; 3859 i++; 3860 } 3861 i = 0; 3862 while(i < 16) { 3863 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3864 acb_device_map++; 3865 i++; 3866 } 3867 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3868 acb->firm_request_len = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3869 acb->firm_numbers_queue = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3870 acb->firm_sdram_size = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3871 acb->firm_ide_channels = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3872 acb->firm_cfg_version = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3873 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 3874 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 3875 else 3876 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3877 } 3878 /* 3879 ********************************************************************** 3880 ********************************************************************** 3881 */ 3882 static void arcmsr_get_hbd_config(struct AdapterControlBlock *acb) 3883 { 3884 char *acb_firm_model = acb->firm_model; 3885 char *acb_firm_version = acb->firm_version; 3886 char *acb_device_map = acb->device_map; 3887 size_t iop_firm_model = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3888 size_t iop_firm_version = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3889 size_t iop_device_map = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3890 int i; 3891 3892 if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) 3893 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR); 3894 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3895 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 3896 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3897 } 3898 i = 0; 3899 while(i < 8) { 3900 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3901 /* 8 bytes firm_model, 15, 60-67*/ 3902 acb_firm_model++; 3903 i++; 3904 } 3905 i = 0; 3906 while(i < 16) { 3907 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3908 /* 16 bytes firm_version, 17, 68-83*/ 3909 acb_firm_version++; 3910 i++; 3911 } 3912 i = 0; 3913 while(i < 16) { 3914 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3915 acb_device_map++; 3916 i++; 3917 } 3918 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3919 acb->firm_request_len = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3920 acb->firm_numbers_queue = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3921 acb->firm_sdram_size = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3922 acb->firm_ide_channels = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3923 acb->firm_cfg_version = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3924 if(acb->firm_numbers_queue > ARCMSR_MAX_HBD_POSTQUEUE) 3925 acb->maxOutstanding = ARCMSR_MAX_HBD_POSTQUEUE - 1; 3926 else 3927 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3928 } 3929 /* 3930 ********************************************************************** 3931 ********************************************************************** 3932 */ 3933 static void arcmsr_get_hbe_config(struct AdapterControlBlock *acb) 3934 { 3935 char *acb_firm_model = acb->firm_model; 3936 char *acb_firm_version = acb->firm_version; 3937 char *acb_device_map = acb->device_map; 3938 size_t iop_firm_model = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3939 size_t iop_firm_version = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3940 size_t iop_device_map = offsetof(struct HBE_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3941 int i; 3942 3943 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3944 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 3945 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 3946 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 3947 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3948 } 3949 3950 i = 0; 3951 while(i < 8) { 3952 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3953 /* 8 bytes firm_model, 15, 60-67*/ 3954 acb_firm_model++; 3955 i++; 3956 } 3957 i = 0; 3958 while(i < 16) { 3959 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3960 /* 16 bytes firm_version, 17, 68-83*/ 3961 acb_firm_version++; 3962 i++; 3963 } 3964 i = 0; 3965 while(i < 16) { 3966 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3967 acb_device_map++; 3968 i++; 3969 } 3970 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3971 acb->firm_request_len = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3972 acb->firm_numbers_queue = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3973 acb->firm_sdram_size = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3974 acb->firm_ide_channels = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3975 acb->firm_cfg_version = CHIP_REG_READ32(HBE_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3976 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 3977 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 3978 else 3979 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3980 } 3981 /* 3982 ********************************************************************** 3983 ********************************************************************** 3984 */ 3985 static void arcmsr_get_hbf_config(struct AdapterControlBlock *acb) 3986 { 3987 u_int32_t *acb_firm_model = (u_int32_t *)acb->firm_model; 3988 u_int32_t *acb_firm_version = (u_int32_t *)acb->firm_version; 3989 u_int32_t *acb_device_map = (u_int32_t *)acb->device_map; 3990 size_t iop_firm_model = ARCMSR_FW_MODEL_OFFSET; /*firm_model,15,60-67*/ 3991 size_t iop_firm_version = ARCMSR_FW_VERS_OFFSET; /*firm_version,17,68-83*/ 3992 size_t iop_device_map = ARCMSR_FW_DEVMAP_OFFSET; 3993 int i; 3994 3995 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3996 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 3997 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 3998 if(!arcmsr_hbe_wait_msgint_ready(acb)) 3999 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 4000 4001 i = 0; 4002 while(i < 2) { 4003 *acb_firm_model = acb->msgcode_rwbuffer[iop_firm_model]; 4004 /* 8 bytes firm_model, 15, 60-67*/ 4005 acb_firm_model++; 4006 iop_firm_model++; 4007 i++; 4008 } 4009 i = 0; 4010 while(i < 4) { 4011 *acb_firm_version = acb->msgcode_rwbuffer[iop_firm_version]; 4012 /* 16 bytes firm_version, 17, 68-83*/ 4013 acb_firm_version++; 4014 iop_firm_version++; 4015 i++; 4016 } 4017 i = 0; 4018 while(i < 4) { 4019 *acb_device_map = acb->msgcode_rwbuffer[iop_device_map]; 4020 acb_device_map++; 4021 iop_device_map++; 4022 i++; 4023 } 4024 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 4025 acb->firm_request_len = acb->msgcode_rwbuffer[1]; /*firm_request_len, 1, 04-07*/ 4026 acb->firm_numbers_queue = acb->msgcode_rwbuffer[2]; /*firm_numbers_queue, 2, 08-11*/ 4027 acb->firm_sdram_size = acb->msgcode_rwbuffer[3]; /*firm_sdram_size, 3, 12-15*/ 4028 acb->firm_ide_channels = acb->msgcode_rwbuffer[4]; /*firm_ide_channels, 4, 16-19*/ 4029 acb->firm_cfg_version = acb->msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]; /*firm_cfg_version, 25*/ 4030 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 4031 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 4032 else 4033 acb->maxOutstanding = acb->firm_numbers_queue - 1; 4034 } 4035 /* 4036 ********************************************************************** 4037 ********************************************************************** 4038 */ 4039 static void arcmsr_get_firmware_spec(struct AdapterControlBlock *acb) 4040 { 4041 switch (acb->adapter_type) { 4042 case ACB_ADAPTER_TYPE_A: 4043 arcmsr_get_hba_config(acb); 4044 break; 4045 case ACB_ADAPTER_TYPE_B: 4046 arcmsr_get_hbb_config(acb); 4047 break; 4048 case ACB_ADAPTER_TYPE_C: 4049 arcmsr_get_hbc_config(acb); 4050 break; 4051 case ACB_ADAPTER_TYPE_D: 4052 arcmsr_get_hbd_config(acb); 4053 break; 4054 case ACB_ADAPTER_TYPE_E: 4055 arcmsr_get_hbe_config(acb); 4056 break; 4057 case ACB_ADAPTER_TYPE_F: 4058 arcmsr_get_hbf_config(acb); 4059 break; 4060 } 4061 } 4062 /* 4063 ********************************************************************** 4064 ********************************************************************** 4065 */ 4066 static void arcmsr_wait_firmware_ready( struct AdapterControlBlock *acb) 4067 { 4068 int timeout=0; 4069 4070 switch (acb->adapter_type) { 4071 case ACB_ADAPTER_TYPE_A: { 4072 while ((CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0) 4073 { 4074 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 4075 { 4076 printf( "arcmsr%d:timed out waiting for firmware \n", acb->pci_unit); 4077 return; 4078 } 4079 UDELAY(15000); /* wait 15 milli-seconds */ 4080 } 4081 } 4082 break; 4083 case ACB_ADAPTER_TYPE_B: { 4084 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4085 while ((READ_CHIP_REG32(0, phbbmu->iop2drv_doorbell) & ARCMSR_MESSAGE_FIRMWARE_OK) == 0) 4086 { 4087 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 4088 { 4089 printf( "arcmsr%d: timed out waiting for firmware \n", acb->pci_unit); 4090 return; 4091 } 4092 UDELAY(15000); /* wait 15 milli-seconds */ 4093 } 4094 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 4095 } 4096 break; 4097 case ACB_ADAPTER_TYPE_C: { 4098 while ((CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0) 4099 { 4100 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 4101 { 4102 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 4103 return; 4104 } 4105 UDELAY(15000); /* wait 15 milli-seconds */ 4106 } 4107 } 4108 break; 4109 case ACB_ADAPTER_TYPE_D: { 4110 while ((CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK) == 0) 4111 { 4112 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 4113 { 4114 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 4115 return; 4116 } 4117 UDELAY(15000); /* wait 15 milli-seconds */ 4118 } 4119 } 4120 break; 4121 case ACB_ADAPTER_TYPE_E: 4122 case ACB_ADAPTER_TYPE_F: { 4123 while ((CHIP_REG_READ32(HBE_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBEMU_MESSAGE_FIRMWARE_OK) == 0) 4124 { 4125 if (timeout++ > 4000) /* (4000*15)/1000 = 60 sec */ 4126 { 4127 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 4128 return; 4129 } 4130 UDELAY(15000); /* wait 15 milli-seconds */ 4131 } 4132 } 4133 break; 4134 } 4135 } 4136 /* 4137 ********************************************************************** 4138 ********************************************************************** 4139 */ 4140 static void arcmsr_clear_doorbell_queue_buffer( struct AdapterControlBlock *acb) 4141 { 4142 u_int32_t outbound_doorbell; 4143 4144 switch (acb->adapter_type) { 4145 case ACB_ADAPTER_TYPE_A: { 4146 /* empty doorbell Qbuffer if door bell ringed */ 4147 outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell); 4148 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */ 4149 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK); 4150 } 4151 break; 4152 case ACB_ADAPTER_TYPE_B: { 4153 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4154 WRITE_CHIP_REG32(0, phbbmu->iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN);/*clear interrupt and message state*/ 4155 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK); 4156 /* let IOP know data has been read */ 4157 } 4158 break; 4159 case ACB_ADAPTER_TYPE_C: { 4160 /* empty doorbell Qbuffer if door bell ringed */ 4161 outbound_doorbell = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell); 4162 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell); /*clear doorbell interrupt */ 4163 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK); 4164 CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell_clear); /* Dummy read to force pci flush */ 4165 CHIP_REG_READ32(HBC_MessageUnit, 0, inbound_doorbell); /* Dummy read to force pci flush */ 4166 } 4167 break; 4168 case ACB_ADAPTER_TYPE_D: { 4169 /* empty doorbell Qbuffer if door bell ringed */ 4170 outbound_doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell); 4171 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */ 4172 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ); 4173 } 4174 break; 4175 case ACB_ADAPTER_TYPE_E: 4176 case ACB_ADAPTER_TYPE_F: { 4177 /* empty doorbell Qbuffer if door bell ringed */ 4178 acb->in_doorbell = CHIP_REG_READ32(HBE_MessageUnit, 0, iobound_doorbell); 4179 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /*clear doorbell interrupt */ 4180 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_DATA_READ_OK; 4181 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 4182 } 4183 break; 4184 } 4185 } 4186 /* 4187 ************************************************************************ 4188 ************************************************************************ 4189 */ 4190 static u_int32_t arcmsr_iop_confirm(struct AdapterControlBlock *acb) 4191 { 4192 unsigned long srb_phyaddr; 4193 u_int32_t srb_phyaddr_hi32; 4194 u_int32_t srb_phyaddr_lo32; 4195 4196 /* 4197 ******************************************************************** 4198 ** here we need to tell iop 331 our freesrb.HighPart 4199 ** if freesrb.HighPart is not zero 4200 ******************************************************************** 4201 */ 4202 srb_phyaddr = (unsigned long) acb->srb_phyaddr.phyaddr; 4203 srb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high; 4204 srb_phyaddr_lo32 = acb->srb_phyaddr.B.phyadd_low; 4205 switch (acb->adapter_type) { 4206 case ACB_ADAPTER_TYPE_A: { 4207 if(srb_phyaddr_hi32 != 0) { 4208 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 4209 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 4210 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4211 if(!arcmsr_hba_wait_msgint_ready(acb)) { 4212 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4213 return FALSE; 4214 } 4215 } 4216 } 4217 break; 4218 /* 4219 *********************************************************************** 4220 ** if adapter type B, set window of "post command Q" 4221 *********************************************************************** 4222 */ 4223 case ACB_ADAPTER_TYPE_B: { 4224 u_int32_t post_queue_phyaddr; 4225 struct HBB_MessageUnit *phbbmu; 4226 4227 phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4228 phbbmu->postq_index = 0; 4229 phbbmu->doneq_index = 0; 4230 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_SET_POST_WINDOW); 4231 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 4232 printf( "arcmsr%d: 'set window of post command Q' timeout\n", acb->pci_unit); 4233 return FALSE; 4234 } 4235 post_queue_phyaddr = srb_phyaddr + ARCMSR_SRBS_POOL_SIZE 4236 + offsetof(struct HBB_MessageUnit, post_qbuffer); 4237 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */ 4238 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1], srb_phyaddr_hi32); /* normal should be zero */ 4239 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ size (256+8)*4 */ 4240 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3], post_queue_phyaddr+1056); /* doneQ size (256+8)*4 */ 4241 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4], 1056); /* srb maxQ size must be --> [(256+8)*4] */ 4242 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_SET_CONFIG); 4243 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 4244 printf( "arcmsr%d: 'set command Q window' timeout \n", acb->pci_unit); 4245 return FALSE; 4246 } 4247 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_START_DRIVER_MODE); 4248 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 4249 printf( "arcmsr%d: 'start diver mode' timeout \n", acb->pci_unit); 4250 return FALSE; 4251 } 4252 } 4253 break; 4254 case ACB_ADAPTER_TYPE_C: { 4255 if(srb_phyaddr_hi32 != 0) { 4256 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 4257 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 4258 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4259 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 4260 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 4261 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4262 return FALSE; 4263 } 4264 } 4265 } 4266 break; 4267 case ACB_ADAPTER_TYPE_D: { 4268 u_int32_t post_queue_phyaddr, done_queue_phyaddr; 4269 struct HBD_MessageUnit0 *phbdmu; 4270 4271 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 4272 phbdmu->postq_index = 0; 4273 phbdmu->doneq_index = 0x40FF; 4274 post_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE 4275 + offsetof(struct HBD_MessageUnit0, post_qbuffer); 4276 done_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE 4277 + offsetof(struct HBD_MessageUnit0, done_qbuffer); 4278 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */ 4279 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 4280 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ base */ 4281 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[3], done_queue_phyaddr); /* doneQ base */ 4282 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[4], 0x100); 4283 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4284 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 4285 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4286 return FALSE; 4287 } 4288 } 4289 break; 4290 case ACB_ADAPTER_TYPE_E: { 4291 u_int32_t cdb_phyaddr_lo32; 4292 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + offsetof(struct CommandControlBlock, arcmsr_cdb); 4293 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 4294 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[1], ARCMSR_SIGNATURE_1884); 4295 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[2], cdb_phyaddr_lo32); 4296 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[3], srb_phyaddr_hi32); 4297 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[4], SRB_SIZE); 4298 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE; 4299 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[5], cdb_phyaddr_lo32); 4300 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[6], srb_phyaddr_hi32); 4301 CHIP_REG_WRITE32(HBE_MessageUnit, 0, msgcode_rwbuffer[7], COMPLETION_Q_POOL_SIZE); 4302 CHIP_REG_WRITE32(HBE_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4303 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 4304 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 4305 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 4306 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4307 return FALSE; 4308 } 4309 } 4310 break; 4311 case ACB_ADAPTER_TYPE_F: { 4312 u_int32_t cdb_phyaddr_lo32; 4313 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + offsetof(struct CommandControlBlock, arcmsr_cdb); 4314 acb->msgcode_rwbuffer[0] = ARCMSR_SIGNATURE_SET_CONFIG; 4315 acb->msgcode_rwbuffer[1] = ARCMSR_SIGNATURE_1886; 4316 acb->msgcode_rwbuffer[2] = cdb_phyaddr_lo32; 4317 acb->msgcode_rwbuffer[3] = srb_phyaddr_hi32; 4318 acb->msgcode_rwbuffer[4] = SRB_SIZE; 4319 cdb_phyaddr_lo32 = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE; 4320 acb->msgcode_rwbuffer[5] = cdb_phyaddr_lo32; 4321 acb->msgcode_rwbuffer[6] = srb_phyaddr_hi32; 4322 acb->msgcode_rwbuffer[7] = COMPLETION_Q_POOL_SIZE; 4323 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 4324 acb->out_doorbell ^= ARCMSR_HBEMU_DRV2IOP_MESSAGE_CMD_DONE; 4325 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, acb->out_doorbell); 4326 if(!arcmsr_hbe_wait_msgint_ready(acb)) { 4327 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 4328 return FALSE; 4329 } 4330 } 4331 break; 4332 } 4333 return (TRUE); 4334 } 4335 /* 4336 ************************************************************************ 4337 ************************************************************************ 4338 */ 4339 static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb) 4340 { 4341 if (acb->adapter_type == ACB_ADAPTER_TYPE_B) 4342 { 4343 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4344 WRITE_CHIP_REG32(0, phbbmu->drv2iop_doorbell, ARCMSR_MESSAGE_ACTIVE_EOI_MODE); 4345 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 4346 printf( "arcmsr%d: 'iop enable eoi mode' timeout \n", acb->pci_unit); 4347 return; 4348 } 4349 } 4350 } 4351 /* 4352 ********************************************************************** 4353 ********************************************************************** 4354 */ 4355 static void arcmsr_iop_init(struct AdapterControlBlock *acb) 4356 { 4357 u_int32_t intmask_org; 4358 4359 /* disable all outbound interrupt */ 4360 intmask_org = arcmsr_disable_allintr(acb); 4361 arcmsr_wait_firmware_ready(acb); 4362 arcmsr_iop_confirm(acb); 4363 arcmsr_get_firmware_spec(acb); 4364 /*start background rebuild*/ 4365 arcmsr_start_adapter_bgrb(acb); 4366 /* empty doorbell Qbuffer if door bell ringed */ 4367 arcmsr_clear_doorbell_queue_buffer(acb); 4368 arcmsr_enable_eoi_mode(acb); 4369 /* enable outbound Post Queue, outbound doorbell Interrupt */ 4370 arcmsr_enable_allintr(acb, intmask_org); 4371 acb->acb_flags |= ACB_F_IOP_INITED; 4372 } 4373 /* 4374 ********************************************************************** 4375 ********************************************************************** 4376 */ 4377 static void arcmsr_map_free_srb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 4378 { 4379 struct AdapterControlBlock *acb = arg; 4380 struct CommandControlBlock *srb_tmp; 4381 u_int32_t i; 4382 unsigned long srb_phyaddr = (unsigned long)segs->ds_addr; 4383 4384 acb->srb_phyaddr.phyaddr = srb_phyaddr; 4385 srb_tmp = (struct CommandControlBlock *)acb->uncacheptr; 4386 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 4387 if(bus_dmamap_create(acb->dm_segs_dmat, 4388 /*flags*/0, &srb_tmp->dm_segs_dmamap) != 0) { 4389 acb->acb_flags |= ACB_F_MAPFREESRB_FAILD; 4390 printf("arcmsr%d:" 4391 " srb dmamap bus_dmamap_create error\n", acb->pci_unit); 4392 return; 4393 } 4394 if((acb->adapter_type == ACB_ADAPTER_TYPE_C) || (acb->adapter_type == ACB_ADAPTER_TYPE_D) 4395 || (acb->adapter_type == ACB_ADAPTER_TYPE_E) || (acb->adapter_type == ACB_ADAPTER_TYPE_F)) 4396 { 4397 srb_tmp->cdb_phyaddr_low = srb_phyaddr; 4398 srb_tmp->cdb_phyaddr_high = (u_int32_t)((srb_phyaddr >> 16) >> 16); 4399 } 4400 else 4401 srb_tmp->cdb_phyaddr_low = srb_phyaddr >> 5; 4402 srb_tmp->acb = acb; 4403 srb_tmp->smid = i << 16; 4404 acb->srbworkingQ[i] = acb->psrb_pool[i] = srb_tmp; 4405 srb_phyaddr = srb_phyaddr + SRB_SIZE; 4406 srb_tmp = (struct CommandControlBlock *)((unsigned long)srb_tmp + SRB_SIZE); 4407 } 4408 if (acb->adapter_type == ACB_ADAPTER_TYPE_E) 4409 acb->pCompletionQ = (pCompletion_Q)srb_tmp; 4410 else if (acb->adapter_type == ACB_ADAPTER_TYPE_F) { 4411 acb->pCompletionQ = (pCompletion_Q)srb_tmp; 4412 acb->completeQ_phys = srb_phyaddr; 4413 memset(acb->pCompletionQ, 0xff, COMPLETION_Q_POOL_SIZE); 4414 acb->message_wbuffer = (u_int32_t *)((unsigned long)acb->pCompletionQ + COMPLETION_Q_POOL_SIZE); 4415 acb->message_rbuffer = (u_int32_t *)((unsigned long)acb->message_wbuffer + 0x100); 4416 acb->msgcode_rwbuffer = (u_int32_t *)((unsigned long)acb->message_wbuffer + 0x200); 4417 memset((void *)acb->message_wbuffer, 0, MESG_RW_BUFFER_SIZE); 4418 } 4419 acb->vir2phy_offset = (unsigned long)srb_tmp - (unsigned long)srb_phyaddr; 4420 } 4421 /* 4422 ************************************************************************ 4423 ************************************************************************ 4424 */ 4425 static void arcmsr_free_resource(struct AdapterControlBlock *acb) 4426 { 4427 /* remove the control device */ 4428 if(acb->ioctl_dev != NULL) { 4429 destroy_dev(acb->ioctl_dev); 4430 } 4431 bus_dmamap_unload(acb->srb_dmat, acb->srb_dmamap); 4432 bus_dmamap_destroy(acb->srb_dmat, acb->srb_dmamap); 4433 bus_dma_tag_destroy(acb->srb_dmat); 4434 bus_dma_tag_destroy(acb->dm_segs_dmat); 4435 bus_dma_tag_destroy(acb->parent_dmat); 4436 } 4437 /* 4438 ************************************************************************ 4439 ************************************************************************ 4440 */ 4441 static void arcmsr_mutex_init(struct AdapterControlBlock *acb) 4442 { 4443 ARCMSR_LOCK_INIT(&acb->isr_lock, "arcmsr isr lock"); 4444 ARCMSR_LOCK_INIT(&acb->srb_lock, "arcmsr srb lock"); 4445 ARCMSR_LOCK_INIT(&acb->postDone_lock, "arcmsr postQ lock"); 4446 ARCMSR_LOCK_INIT(&acb->qbuffer_lock, "arcmsr RW buffer lock"); 4447 } 4448 /* 4449 ************************************************************************ 4450 ************************************************************************ 4451 */ 4452 static void arcmsr_mutex_destroy(struct AdapterControlBlock *acb) 4453 { 4454 ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock); 4455 ARCMSR_LOCK_DESTROY(&acb->postDone_lock); 4456 ARCMSR_LOCK_DESTROY(&acb->srb_lock); 4457 ARCMSR_LOCK_DESTROY(&acb->isr_lock); 4458 } 4459 /* 4460 ************************************************************************ 4461 ************************************************************************ 4462 */ 4463 static u_int32_t arcmsr_initialize(device_t dev) 4464 { 4465 struct AdapterControlBlock *acb = device_get_softc(dev); 4466 u_int16_t pci_command; 4467 int i, j,max_coherent_size; 4468 u_int32_t vendor_dev_id; 4469 4470 vendor_dev_id = pci_get_devid(dev); 4471 acb->vendor_device_id = vendor_dev_id; 4472 acb->sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); 4473 switch (vendor_dev_id) { 4474 case PCIDevVenIDARC1880: 4475 case PCIDevVenIDARC1882: 4476 case PCIDevVenIDARC1213: 4477 case PCIDevVenIDARC1223: { 4478 acb->adapter_type = ACB_ADAPTER_TYPE_C; 4479 if ((acb->sub_device_id == ARECA_SUB_DEV_ID_1883) || 4480 (acb->sub_device_id == ARECA_SUB_DEV_ID_1216) || 4481 (acb->sub_device_id == ARECA_SUB_DEV_ID_1226)) 4482 acb->adapter_bus_speed = ACB_BUS_SPEED_12G; 4483 else 4484 acb->adapter_bus_speed = ACB_BUS_SPEED_6G; 4485 max_coherent_size = ARCMSR_SRBS_POOL_SIZE; 4486 } 4487 break; 4488 case PCIDevVenIDARC1884: 4489 acb->adapter_type = ACB_ADAPTER_TYPE_E; 4490 acb->adapter_bus_speed = ACB_BUS_SPEED_12G; 4491 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + COMPLETION_Q_POOL_SIZE; 4492 acb->completionQ_entry = COMPLETION_Q_POOL_SIZE / sizeof(struct deliver_completeQ); 4493 break; 4494 case PCIDevVenIDARC1886_: 4495 case PCIDevVenIDARC1886: 4496 acb->adapter_type = ACB_ADAPTER_TYPE_F; 4497 acb->adapter_bus_speed = ACB_BUS_SPEED_12G; 4498 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + COMPLETION_Q_POOL_SIZE + MESG_RW_BUFFER_SIZE; 4499 acb->completionQ_entry = COMPLETION_Q_POOL_SIZE / sizeof(struct deliver_completeQ); 4500 break; 4501 case PCIDevVenIDARC1214: { 4502 acb->adapter_type = ACB_ADAPTER_TYPE_D; 4503 acb->adapter_bus_speed = ACB_BUS_SPEED_6G; 4504 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBD_MessageUnit0)); 4505 } 4506 break; 4507 case PCIDevVenIDARC1200: 4508 case PCIDevVenIDARC1201: { 4509 acb->adapter_type = ACB_ADAPTER_TYPE_B; 4510 acb->adapter_bus_speed = ACB_BUS_SPEED_3G; 4511 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit)); 4512 } 4513 break; 4514 case PCIDevVenIDARC1203: { 4515 acb->adapter_type = ACB_ADAPTER_TYPE_B; 4516 acb->adapter_bus_speed = ACB_BUS_SPEED_6G; 4517 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit)); 4518 } 4519 break; 4520 case PCIDevVenIDARC1110: 4521 case PCIDevVenIDARC1120: 4522 case PCIDevVenIDARC1130: 4523 case PCIDevVenIDARC1160: 4524 case PCIDevVenIDARC1170: 4525 case PCIDevVenIDARC1210: 4526 case PCIDevVenIDARC1220: 4527 case PCIDevVenIDARC1230: 4528 case PCIDevVenIDARC1231: 4529 case PCIDevVenIDARC1260: 4530 case PCIDevVenIDARC1261: 4531 case PCIDevVenIDARC1270: 4532 case PCIDevVenIDARC1280: 4533 case PCIDevVenIDARC1212: 4534 case PCIDevVenIDARC1222: 4535 case PCIDevVenIDARC1380: 4536 case PCIDevVenIDARC1381: 4537 case PCIDevVenIDARC1680: 4538 case PCIDevVenIDARC1681: { 4539 acb->adapter_type = ACB_ADAPTER_TYPE_A; 4540 acb->adapter_bus_speed = ACB_BUS_SPEED_3G; 4541 max_coherent_size = ARCMSR_SRBS_POOL_SIZE; 4542 } 4543 break; 4544 default: { 4545 printf("arcmsr%d:" 4546 " unknown RAID adapter type \n", device_get_unit(dev)); 4547 return ENOMEM; 4548 } 4549 } 4550 if(bus_dma_tag_create( /*PCI parent*/ bus_get_dma_tag(dev), 4551 /*alignemnt*/ 1, 4552 /*boundary*/ 0, 4553 /*lowaddr*/ BUS_SPACE_MAXADDR, 4554 /*highaddr*/ BUS_SPACE_MAXADDR, 4555 /*filter*/ NULL, 4556 /*filterarg*/ NULL, 4557 /*maxsize*/ BUS_SPACE_MAXSIZE_32BIT, 4558 /*nsegments*/ BUS_SPACE_UNRESTRICTED, 4559 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4560 /*flags*/ 0, 4561 /*lockfunc*/ NULL, 4562 /*lockarg*/ NULL, 4563 &acb->parent_dmat) != 0) 4564 { 4565 printf("arcmsr%d: parent_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4566 return ENOMEM; 4567 } 4568 4569 /* Create a single tag describing a region large enough to hold all of the s/g lists we will need. */ 4570 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat, 4571 /*alignment*/ 1, 4572 /*boundary*/ 0, 4573 #ifdef PAE 4574 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 4575 #else 4576 /*lowaddr*/ BUS_SPACE_MAXADDR, 4577 #endif 4578 /*highaddr*/ BUS_SPACE_MAXADDR, 4579 /*filter*/ NULL, 4580 /*filterarg*/ NULL, 4581 /*maxsize*/ ARCMSR_MAX_SG_ENTRIES * PAGE_SIZE * ARCMSR_MAX_FREESRB_NUM, 4582 /*nsegments*/ ARCMSR_MAX_SG_ENTRIES, 4583 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4584 /*flags*/ 0, 4585 /*lockfunc*/ busdma_lock_mutex, 4586 /*lockarg*/ &acb->isr_lock, 4587 &acb->dm_segs_dmat) != 0) 4588 { 4589 bus_dma_tag_destroy(acb->parent_dmat); 4590 printf("arcmsr%d: dm_segs_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4591 return ENOMEM; 4592 } 4593 4594 /* DMA tag for our srb structures.... Allocate the freesrb memory */ 4595 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat, 4596 /*alignment*/ 0x20, 4597 /*boundary*/ 0, 4598 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 4599 /*highaddr*/ BUS_SPACE_MAXADDR, 4600 /*filter*/ NULL, 4601 /*filterarg*/ NULL, 4602 /*maxsize*/ max_coherent_size, 4603 /*nsegments*/ 1, 4604 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4605 /*flags*/ 0, 4606 /*lockfunc*/ NULL, 4607 /*lockarg*/ NULL, 4608 &acb->srb_dmat) != 0) 4609 { 4610 bus_dma_tag_destroy(acb->dm_segs_dmat); 4611 bus_dma_tag_destroy(acb->parent_dmat); 4612 printf("arcmsr%d: srb_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4613 return ENXIO; 4614 } 4615 /* Allocation for our srbs */ 4616 if(bus_dmamem_alloc(acb->srb_dmat, (void **)&acb->uncacheptr, BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, &acb->srb_dmamap) != 0) { 4617 bus_dma_tag_destroy(acb->srb_dmat); 4618 bus_dma_tag_destroy(acb->dm_segs_dmat); 4619 bus_dma_tag_destroy(acb->parent_dmat); 4620 printf("arcmsr%d: srb_dmat bus_dmamem_alloc failure!\n", device_get_unit(dev)); 4621 return ENXIO; 4622 } 4623 /* And permanently map them */ 4624 if(bus_dmamap_load(acb->srb_dmat, acb->srb_dmamap, acb->uncacheptr, max_coherent_size, arcmsr_map_free_srb, acb, /*flags*/0)) { 4625 bus_dma_tag_destroy(acb->srb_dmat); 4626 bus_dma_tag_destroy(acb->dm_segs_dmat); 4627 bus_dma_tag_destroy(acb->parent_dmat); 4628 printf("arcmsr%d: srb_dmat bus_dmamap_load failure!\n", device_get_unit(dev)); 4629 return ENXIO; 4630 } 4631 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 4632 pci_command |= PCIM_CMD_BUSMASTEREN; 4633 pci_command |= PCIM_CMD_PERRESPEN; 4634 pci_command |= PCIM_CMD_MWRICEN; 4635 /* Enable Busmaster */ 4636 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 4637 switch(acb->adapter_type) { 4638 case ACB_ADAPTER_TYPE_A: { 4639 u_int32_t rid0 = PCIR_BAR(0); 4640 vm_offset_t mem_base0; 4641 4642 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev,SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4643 if(acb->sys_res_arcmsr[0] == NULL) { 4644 arcmsr_free_resource(acb); 4645 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4646 return ENOMEM; 4647 } 4648 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4649 arcmsr_free_resource(acb); 4650 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4651 return ENXIO; 4652 } 4653 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4654 if(mem_base0 == 0) { 4655 arcmsr_free_resource(acb); 4656 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4657 return ENXIO; 4658 } 4659 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4660 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4661 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4662 acb->rid[0] = rid0; 4663 } 4664 break; 4665 case ACB_ADAPTER_TYPE_B: { 4666 struct HBB_MessageUnit *phbbmu; 4667 struct CommandControlBlock *freesrb; 4668 u_int32_t rid[]={ PCIR_BAR(0), PCIR_BAR(2) }; 4669 vm_offset_t mem_base[]={0,0}; 4670 for(i=0; i < 2; i++) { 4671 acb->sys_res_arcmsr[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid[i], RF_ACTIVE); 4672 if(acb->sys_res_arcmsr[i] == NULL) { 4673 arcmsr_free_resource(acb); 4674 printf("arcmsr%d: bus_alloc_resource %d failure!\n", device_get_unit(dev), i); 4675 return ENOMEM; 4676 } 4677 if(rman_get_start(acb->sys_res_arcmsr[i]) <= 0) { 4678 arcmsr_free_resource(acb); 4679 printf("arcmsr%d: rman_get_start %d failure!\n", device_get_unit(dev), i); 4680 return ENXIO; 4681 } 4682 mem_base[i] = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[i]); 4683 if(mem_base[i] == 0) { 4684 arcmsr_free_resource(acb); 4685 printf("arcmsr%d: rman_get_virtual %d failure!\n", device_get_unit(dev), i); 4686 return ENXIO; 4687 } 4688 acb->btag[i] = rman_get_bustag(acb->sys_res_arcmsr[i]); 4689 acb->bhandle[i] = rman_get_bushandle(acb->sys_res_arcmsr[i]); 4690 } 4691 freesrb = (struct CommandControlBlock *)acb->uncacheptr; 4692 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)freesrb+ARCMSR_SRBS_POOL_SIZE); 4693 phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4694 phbbmu->hbb_doorbell = (struct HBB_DOORBELL *)mem_base[0]; 4695 phbbmu->hbb_rwbuffer = (struct HBB_RWBUFFER *)mem_base[1]; 4696 if (vendor_dev_id == PCIDevVenIDARC1203) { 4697 phbbmu->drv2iop_doorbell = offsetof(struct HBB_DOORBELL_1203, drv2iop_doorbell); 4698 phbbmu->drv2iop_doorbell_mask = offsetof(struct HBB_DOORBELL_1203, drv2iop_doorbell_mask); 4699 phbbmu->iop2drv_doorbell = offsetof(struct HBB_DOORBELL_1203, iop2drv_doorbell); 4700 phbbmu->iop2drv_doorbell_mask = offsetof(struct HBB_DOORBELL_1203, iop2drv_doorbell_mask); 4701 } else { 4702 phbbmu->drv2iop_doorbell = offsetof(struct HBB_DOORBELL, drv2iop_doorbell); 4703 phbbmu->drv2iop_doorbell_mask = offsetof(struct HBB_DOORBELL, drv2iop_doorbell_mask); 4704 phbbmu->iop2drv_doorbell = offsetof(struct HBB_DOORBELL, iop2drv_doorbell); 4705 phbbmu->iop2drv_doorbell_mask = offsetof(struct HBB_DOORBELL, iop2drv_doorbell_mask); 4706 } 4707 acb->rid[0] = rid[0]; 4708 acb->rid[1] = rid[1]; 4709 } 4710 break; 4711 case ACB_ADAPTER_TYPE_C: { 4712 u_int32_t rid0 = PCIR_BAR(1); 4713 vm_offset_t mem_base0; 4714 4715 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4716 if(acb->sys_res_arcmsr[0] == NULL) { 4717 arcmsr_free_resource(acb); 4718 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4719 return ENOMEM; 4720 } 4721 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4722 arcmsr_free_resource(acb); 4723 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4724 return ENXIO; 4725 } 4726 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4727 if(mem_base0 == 0) { 4728 arcmsr_free_resource(acb); 4729 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4730 return ENXIO; 4731 } 4732 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4733 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4734 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4735 acb->rid[0] = rid0; 4736 } 4737 break; 4738 case ACB_ADAPTER_TYPE_D: { 4739 struct HBD_MessageUnit0 *phbdmu; 4740 u_int32_t rid0 = PCIR_BAR(0); 4741 vm_offset_t mem_base0; 4742 4743 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4744 if(acb->sys_res_arcmsr[0] == NULL) { 4745 arcmsr_free_resource(acb); 4746 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4747 return ENOMEM; 4748 } 4749 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4750 arcmsr_free_resource(acb); 4751 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4752 return ENXIO; 4753 } 4754 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4755 if(mem_base0 == 0) { 4756 arcmsr_free_resource(acb); 4757 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4758 return ENXIO; 4759 } 4760 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4761 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4762 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)acb->uncacheptr+ARCMSR_SRBS_POOL_SIZE); 4763 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 4764 phbdmu->phbdmu = (struct HBD_MessageUnit *)mem_base0; 4765 acb->rid[0] = rid0; 4766 } 4767 break; 4768 case ACB_ADAPTER_TYPE_E: { 4769 u_int32_t rid0 = PCIR_BAR(1); 4770 vm_offset_t mem_base0; 4771 4772 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4773 if(acb->sys_res_arcmsr[0] == NULL) { 4774 arcmsr_free_resource(acb); 4775 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4776 return ENOMEM; 4777 } 4778 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4779 arcmsr_free_resource(acb); 4780 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4781 return ENXIO; 4782 } 4783 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4784 if(mem_base0 == 0) { 4785 arcmsr_free_resource(acb); 4786 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4787 return ENXIO; 4788 } 4789 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4790 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4791 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4792 acb->doneq_index = 0; 4793 acb->in_doorbell = 0; 4794 acb->out_doorbell = 0; 4795 acb->rid[0] = rid0; 4796 CHIP_REG_WRITE32(HBE_MessageUnit, 0, host_int_status, 0); /*clear interrupt*/ 4797 CHIP_REG_WRITE32(HBE_MessageUnit, 0, iobound_doorbell, ARCMSR_HBEMU_DOORBELL_SYNC); /* synchronize doorbell to 0 */ 4798 } 4799 break; 4800 case ACB_ADAPTER_TYPE_F: { 4801 u_int32_t rid0 = PCIR_BAR(0); 4802 vm_offset_t mem_base0; 4803 unsigned long host_buffer_dma; 4804 4805 acb->sys_res_arcmsr[0] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid0, RF_ACTIVE); 4806 if(acb->sys_res_arcmsr[0] == NULL) { 4807 arcmsr_free_resource(acb); 4808 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4809 return ENOMEM; 4810 } 4811 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4812 arcmsr_free_resource(acb); 4813 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4814 return ENXIO; 4815 } 4816 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4817 if(mem_base0 == 0) { 4818 arcmsr_free_resource(acb); 4819 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4820 return ENXIO; 4821 } 4822 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4823 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4824 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4825 acb->doneq_index = 0; 4826 acb->in_doorbell = 0; 4827 acb->out_doorbell = 0; 4828 acb->rid[0] = rid0; 4829 arcmsr_wait_firmware_ready(acb); 4830 CHIP_REG_WRITE32(HBF_MessageUnit, 0, host_int_status, 0); /*clear interrupt*/ 4831 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, ARCMSR_HBEMU_DOORBELL_SYNC); /* synchronize doorbell to 0 */ 4832 host_buffer_dma = acb->completeQ_phys + COMPLETION_Q_POOL_SIZE; 4833 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr0, (u_int32_t)(host_buffer_dma | 1)); /* host buffer low addr, bit0:1 all buffer active */ 4834 CHIP_REG_WRITE32(HBF_MessageUnit, 0, inbound_msgaddr1, (u_int32_t)((host_buffer_dma >> 16) >> 16));/* host buffer high addr */ 4835 CHIP_REG_WRITE32(HBF_MessageUnit, 0, iobound_doorbell, ARCMSR_HBFMU_DOORBELL_SYNC1); /* set host buffer physical address */ 4836 } 4837 break; 4838 } 4839 if(acb->acb_flags & ACB_F_MAPFREESRB_FAILD) { 4840 arcmsr_free_resource(acb); 4841 printf("arcmsr%d: map free srb failure!\n", device_get_unit(dev)); 4842 return ENXIO; 4843 } 4844 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_RQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ); 4845 acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER; 4846 /* 4847 ******************************************************************** 4848 ** init raid volume state 4849 ******************************************************************** 4850 */ 4851 for(i=0; i < ARCMSR_MAX_TARGETID; i++) { 4852 for(j=0; j < ARCMSR_MAX_TARGETLUN; j++) { 4853 acb->devstate[i][j] = ARECA_RAID_GONE; 4854 } 4855 } 4856 arcmsr_iop_init(acb); 4857 return(0); 4858 } 4859 4860 static int arcmsr_setup_msix(struct AdapterControlBlock *acb) 4861 { 4862 int i; 4863 4864 for (i = 0; i < acb->msix_vectors; i++) { 4865 acb->irq_id[i] = 1 + i; 4866 acb->irqres[i] = bus_alloc_resource_any(acb->pci_dev, 4867 SYS_RES_IRQ, &acb->irq_id[i], RF_ACTIVE); 4868 if (acb->irqres[i] == NULL) { 4869 printf("arcmsr: Can't allocate MSI-X resource\n"); 4870 goto irq_alloc_failed; 4871 } 4872 if (bus_setup_intr(acb->pci_dev, acb->irqres[i], 4873 INTR_MPSAFE | INTR_TYPE_CAM, NULL, arcmsr_intr_handler, 4874 acb, &acb->ih[i])) { 4875 printf("arcmsr: Cannot set up MSI-X interrupt handler\n"); 4876 goto irq_alloc_failed; 4877 } 4878 } 4879 printf("arcmsr: MSI-X INT enabled\n"); 4880 acb->acb_flags |= ACB_F_MSIX_ENABLED; 4881 return TRUE; 4882 4883 irq_alloc_failed: 4884 arcmsr_teardown_intr(acb->pci_dev, acb); 4885 return FALSE; 4886 } 4887 4888 /* 4889 ************************************************************************ 4890 ************************************************************************ 4891 */ 4892 static int arcmsr_attach(device_t dev) 4893 { 4894 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 4895 u_int32_t unit=device_get_unit(dev); 4896 struct ccb_setasync csa; 4897 struct cam_devq *devq; /* Device Queue to use for this SIM */ 4898 struct resource *irqres; 4899 4900 if(acb == NULL) { 4901 printf("arcmsr%d: cannot allocate softc\n", unit); 4902 return (ENOMEM); 4903 } 4904 arcmsr_mutex_init(acb); 4905 acb->pci_dev = dev; 4906 acb->pci_unit = unit; 4907 if(arcmsr_initialize(dev)) { 4908 printf("arcmsr%d: initialize failure!\n", unit); 4909 goto initialize_failed; 4910 } 4911 /* After setting up the adapter, map our interrupt */ 4912 acb->msix_vectors = ARCMSR_NUM_MSIX_VECTORS; 4913 if (pci_alloc_msix(dev, &acb->msix_vectors) == 0) { 4914 if (arcmsr_setup_msix(acb) == TRUE) 4915 goto irqx; 4916 } 4917 acb->irq_id[0] = 0; 4918 irqres = bus_alloc_resource_any(dev, SYS_RES_IRQ, &acb->irq_id[0], RF_SHAREABLE | RF_ACTIVE); 4919 if(irqres == NULL || 4920 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, NULL, arcmsr_intr_handler, acb, &acb->ih[0])) { 4921 printf("arcmsr%d: unable to register interrupt handler!\n", unit); 4922 goto setup_intr_failed; 4923 } 4924 acb->irqres[0] = irqres; 4925 irqx: 4926 /* 4927 * Now let the CAM generic SCSI layer find the SCSI devices on 4928 * the bus * start queue to reset to the idle loop. * 4929 * Create device queue of SIM(s) * (MAX_START_JOB - 1) : 4930 * max_sim_transactions 4931 */ 4932 devq = cam_simq_alloc(acb->maxOutstanding); 4933 if(devq == NULL) { 4934 printf("arcmsr%d: cam_simq_alloc failure!\n", unit); 4935 goto simq_alloc_failed; 4936 } 4937 acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, &acb->isr_lock, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq); 4938 if(acb->psim == NULL) { 4939 printf("arcmsr%d: cam_sim_alloc failure!\n", unit); 4940 goto sim_alloc_failed; 4941 } 4942 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 4943 if(xpt_bus_register(acb->psim, dev, 0) != CAM_SUCCESS) { 4944 printf("arcmsr%d: xpt_bus_register failure!\n", unit); 4945 goto xpt_bus_failed; 4946 } 4947 if(xpt_create_path(&acb->ppath, /* periph */ NULL, cam_sim_path(acb->psim), CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 4948 printf("arcmsr%d: xpt_create_path failure!\n", unit); 4949 goto xpt_path_failed; 4950 } 4951 /* 4952 **************************************************** 4953 */ 4954 xpt_setup_ccb(&csa.ccb_h, acb->ppath, /*priority*/5); 4955 csa.ccb_h.func_code = XPT_SASYNC_CB; 4956 csa.event_enable = AC_FOUND_DEVICE|AC_LOST_DEVICE; 4957 csa.callback = arcmsr_async; 4958 csa.callback_arg = acb->psim; 4959 xpt_action((union ccb *)&csa); 4960 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 4961 /* Create the control device. */ 4962 acb->ioctl_dev = make_dev(&arcmsr_cdevsw, unit, UID_ROOT, GID_WHEEL /* GID_OPERATOR */, S_IRUSR | S_IWUSR, "arcmsr%d", unit); 4963 4964 (void)make_dev_alias(acb->ioctl_dev, "arc%d", unit); 4965 arcmsr_callout_init(&acb->devmap_callout); 4966 callout_reset(&acb->devmap_callout, 60 * hz, arcmsr_polling_devmap, acb); 4967 return (0); 4968 xpt_path_failed: 4969 xpt_bus_deregister(cam_sim_path(acb->psim)); 4970 xpt_bus_failed: 4971 cam_sim_free(acb->psim, /* free_simq */ TRUE); 4972 sim_alloc_failed: 4973 cam_simq_free(devq); 4974 simq_alloc_failed: 4975 arcmsr_teardown_intr(dev, acb); 4976 setup_intr_failed: 4977 arcmsr_free_resource(acb); 4978 initialize_failed: 4979 arcmsr_mutex_destroy(acb); 4980 return ENXIO; 4981 } 4982 4983 /* 4984 ************************************************************************ 4985 ************************************************************************ 4986 */ 4987 static int arcmsr_probe(device_t dev) 4988 { 4989 u_int32_t id; 4990 u_int16_t sub_device_id; 4991 static char buf[256]; 4992 char x_type[]={"unknown"}; 4993 char *type; 4994 int raid6 = 1; 4995 4996 if (pci_get_vendor(dev) != PCI_VENDOR_ID_ARECA) { 4997 return (ENXIO); 4998 } 4999 sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); 5000 switch(id = pci_get_devid(dev)) { 5001 case PCIDevVenIDARC1110: 5002 case PCIDevVenIDARC1200: 5003 case PCIDevVenIDARC1201: 5004 case PCIDevVenIDARC1210: 5005 raid6 = 0; 5006 /*FALLTHRU*/ 5007 case PCIDevVenIDARC1120: 5008 case PCIDevVenIDARC1130: 5009 case PCIDevVenIDARC1160: 5010 case PCIDevVenIDARC1170: 5011 case PCIDevVenIDARC1220: 5012 case PCIDevVenIDARC1230: 5013 case PCIDevVenIDARC1231: 5014 case PCIDevVenIDARC1260: 5015 case PCIDevVenIDARC1261: 5016 case PCIDevVenIDARC1270: 5017 case PCIDevVenIDARC1280: 5018 type = "SATA 3G"; 5019 break; 5020 case PCIDevVenIDARC1212: 5021 case PCIDevVenIDARC1222: 5022 case PCIDevVenIDARC1380: 5023 case PCIDevVenIDARC1381: 5024 case PCIDevVenIDARC1680: 5025 case PCIDevVenIDARC1681: 5026 type = "SAS 3G"; 5027 break; 5028 case PCIDevVenIDARC1880: 5029 case PCIDevVenIDARC1882: 5030 case PCIDevVenIDARC1213: 5031 case PCIDevVenIDARC1223: 5032 if ((sub_device_id == ARECA_SUB_DEV_ID_1883) || 5033 (sub_device_id == ARECA_SUB_DEV_ID_1216) || 5034 (sub_device_id == ARECA_SUB_DEV_ID_1226)) 5035 type = "SAS 12G"; 5036 else 5037 type = "SAS 6G"; 5038 break; 5039 case PCIDevVenIDARC1884: 5040 type = "SAS 12G"; 5041 break; 5042 case PCIDevVenIDARC1886_: 5043 case PCIDevVenIDARC1886: 5044 type = "NVME,SAS-12G,SATA-6G"; 5045 break; 5046 case PCIDevVenIDARC1214: 5047 case PCIDevVenIDARC1203: 5048 type = "SATA 6G"; 5049 break; 5050 default: 5051 type = x_type; 5052 raid6 = 0; 5053 break; 5054 } 5055 if(type == x_type) 5056 return(ENXIO); 5057 sprintf(buf, "Areca %s Host Adapter RAID Controller %s\n%s\n", 5058 type, raid6 ? "(RAID6 capable)" : "", ARCMSR_DRIVER_VERSION); 5059 device_set_desc_copy(dev, buf); 5060 return (BUS_PROBE_DEFAULT); 5061 } 5062 /* 5063 ************************************************************************ 5064 ************************************************************************ 5065 */ 5066 static int arcmsr_shutdown(device_t dev) 5067 { 5068 u_int32_t i; 5069 u_int32_t intmask_org; 5070 struct CommandControlBlock *srb; 5071 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 5072 5073 /* stop adapter background rebuild */ 5074 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 5075 /* disable all outbound interrupt */ 5076 intmask_org = arcmsr_disable_allintr(acb); 5077 arcmsr_stop_adapter_bgrb(acb); 5078 arcmsr_flush_adapter_cache(acb); 5079 /* abort all outstanding command */ 5080 acb->acb_flags |= ACB_F_SCSISTOPADAPTER; 5081 acb->acb_flags &= ~ACB_F_IOP_INITED; 5082 if(acb->srboutstandingcount != 0) { 5083 /*clear and abort all outbound posted Q*/ 5084 arcmsr_done4abort_postqueue(acb); 5085 /* talk to iop 331 outstanding command aborted*/ 5086 arcmsr_abort_allcmd(acb); 5087 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 5088 srb = acb->psrb_pool[i]; 5089 if(srb->srb_state == ARCMSR_SRB_START) { 5090 srb->srb_state = ARCMSR_SRB_ABORTED; 5091 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 5092 arcmsr_srb_complete(srb, 1); 5093 } 5094 } 5095 } 5096 acb->srboutstandingcount = 0; 5097 acb->workingsrb_doneindex = 0; 5098 acb->workingsrb_startindex = 0; 5099 acb->pktRequestCount = 0; 5100 acb->pktReturnCount = 0; 5101 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 5102 return (0); 5103 } 5104 /* 5105 ************************************************************************ 5106 ************************************************************************ 5107 */ 5108 static void arcmsr_teardown_intr(device_t dev, struct AdapterControlBlock *acb) 5109 { 5110 int i; 5111 5112 if (acb->acb_flags & ACB_F_MSIX_ENABLED) { 5113 for (i = 0; i < acb->msix_vectors; i++) { 5114 if (acb->ih[i]) 5115 bus_teardown_intr(dev, acb->irqres[i], acb->ih[i]); 5116 if (acb->irqres[i] != NULL) 5117 bus_release_resource(dev, SYS_RES_IRQ, 5118 acb->irq_id[i], acb->irqres[i]); 5119 5120 acb->ih[i] = NULL; 5121 } 5122 pci_release_msi(dev); 5123 } else { 5124 if (acb->ih[0]) 5125 bus_teardown_intr(dev, acb->irqres[0], acb->ih[0]); 5126 if (acb->irqres[0] != NULL) 5127 bus_release_resource(dev, SYS_RES_IRQ, 5128 acb->irq_id[0], acb->irqres[0]); 5129 acb->ih[0] = NULL; 5130 } 5131 5132 } 5133 /* 5134 ************************************************************************ 5135 ************************************************************************ 5136 */ 5137 static int arcmsr_detach(device_t dev) 5138 { 5139 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 5140 int i; 5141 5142 callout_stop(&acb->devmap_callout); 5143 arcmsr_teardown_intr(dev, acb); 5144 arcmsr_shutdown(dev); 5145 arcmsr_free_resource(acb); 5146 for(i=0; (acb->sys_res_arcmsr[i]!=NULL) && (i<2); i++) { 5147 bus_release_resource(dev, SYS_RES_MEMORY, acb->rid[i], acb->sys_res_arcmsr[i]); 5148 } 5149 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 5150 xpt_async(AC_LOST_DEVICE, acb->ppath, NULL); 5151 xpt_free_path(acb->ppath); 5152 xpt_bus_deregister(cam_sim_path(acb->psim)); 5153 cam_sim_free(acb->psim, TRUE); 5154 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 5155 arcmsr_mutex_destroy(acb); 5156 return (0); 5157 } 5158 5159 #ifdef ARCMSR_DEBUG1 5160 static void arcmsr_dump_data(struct AdapterControlBlock *acb) 5161 { 5162 if((acb->pktRequestCount - acb->pktReturnCount) == 0) 5163 return; 5164 printf("Command Request Count =0x%x\n",acb->pktRequestCount); 5165 printf("Command Return Count =0x%x\n",acb->pktReturnCount); 5166 printf("Command (Req-Rtn) Count =0x%x\n",(acb->pktRequestCount - acb->pktReturnCount)); 5167 printf("Queued Command Count =0x%x\n",acb->srboutstandingcount); 5168 } 5169 #endif 5170