1 /* 2 ******************************************************************************** 3 ** OS : FreeBSD 4 ** FILE NAME : arcmsr.c 5 ** BY : Erich Chen, Ching Huang 6 ** Description: SCSI RAID Device Driver for 7 ** ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x) 8 ** SATA/SAS RAID HOST Adapter 9 ******************************************************************************** 10 ******************************************************************************** 11 ** 12 ** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved. 13 ** 14 ** Redistribution and use in source and binary forms, with or without 15 ** modification, are permitted provided that the following conditions 16 ** are met: 17 ** 1. Redistributions of source code must retain the above copyright 18 ** notice, this list of conditions and the following disclaimer. 19 ** 2. Redistributions in binary form must reproduce the above copyright 20 ** notice, this list of conditions and the following disclaimer in the 21 ** documentation and/or other materials provided with the distribution. 22 ** 3. The name of the author may not be used to endorse or promote products 23 ** derived from this software without specific prior written permission. 24 ** 25 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 29 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT 30 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 32 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 34 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 ******************************************************************************** 36 ** History 37 ** 38 ** REV# DATE NAME DESCRIPTION 39 ** 1.00.00.00 03/31/2004 Erich Chen First release 40 ** 1.20.00.02 11/29/2004 Erich Chen bug fix with arcmsr_bus_reset when PHY error 41 ** 1.20.00.03 04/19/2005 Erich Chen add SATA 24 Ports adapter type support 42 ** clean unused function 43 ** 1.20.00.12 09/12/2005 Erich Chen bug fix with abort command handling, 44 ** firmware version check 45 ** and firmware update notify for hardware bug fix 46 ** handling if none zero high part physical address 47 ** of srb resource 48 ** 1.20.00.13 08/18/2006 Erich Chen remove pending srb and report busy 49 ** add iop message xfer 50 ** with scsi pass-through command 51 ** add new device id of sas raid adapters 52 ** code fit for SPARC64 & PPC 53 ** 1.20.00.14 02/05/2007 Erich Chen bug fix for incorrect ccb_h.status report 54 ** and cause g_vfs_done() read write error 55 ** 1.20.00.15 10/10/2007 Erich Chen support new RAID adapter type ARC120x 56 ** 1.20.00.16 10/10/2009 Erich Chen Bug fix for RAID adapter type ARC120x 57 ** bus_dmamem_alloc() with BUS_DMA_ZERO 58 ** 1.20.00.17 07/15/2010 Ching Huang Added support ARC1880 59 ** report CAM_DEV_NOT_THERE instead of CAM_SEL_TIMEOUT when device failed, 60 ** prevent cam_periph_error removing all LUN devices of one Target id 61 ** for any one LUN device failed 62 ** 1.20.00.18 10/14/2010 Ching Huang Fixed "inquiry data fails comparion at DV1 step" 63 ** 10/25/2010 Ching Huang Fixed bad range input in bus_alloc_resource for ADAPTER_TYPE_B 64 ** 1.20.00.19 11/11/2010 Ching Huang Fixed arcmsr driver prevent arcsas support for Areca SAS HBA ARC13x0 65 ** 1.20.00.20 12/08/2010 Ching Huang Avoid calling atomic_set_int function 66 ** 1.20.00.21 02/08/2011 Ching Huang Implement I/O request timeout 67 ** 02/14/2011 Ching Huang Modified pktRequestCount 68 ** 1.20.00.21 03/03/2011 Ching Huang if a command timeout, then wait its ccb back before free it 69 ** 1.20.00.22 07/04/2011 Ching Huang Fixed multiple MTX panic 70 ** 1.20.00.23 10/28/2011 Ching Huang Added TIMEOUT_DELAY in case of too many HDDs need to start 71 ** 1.20.00.23 11/08/2011 Ching Huang Added report device transfer speed 72 ** 1.20.00.23 01/30/2012 Ching Huang Fixed Request requeued and Retrying command 73 ** 1.20.00.24 06/11/2012 Ching Huang Fixed return sense data condition 74 ** 1.20.00.25 08/17/2012 Ching Huang Fixed hotplug device no function on type A adapter 75 ** 1.20.00.26 12/14/2012 Ching Huang Added support ARC1214,1224,1264,1284 76 ** 1.20.00.27 05/06/2013 Ching Huang Fixed out standing cmd full on ARC-12x4 77 ****************************************************************************************** 78 */ 79 80 #include <sys/cdefs.h> 81 __FBSDID("$FreeBSD$"); 82 83 #if 0 84 #define ARCMSR_DEBUG1 1 85 #endif 86 #include <sys/param.h> 87 #include <sys/systm.h> 88 #include <sys/malloc.h> 89 #include <sys/kernel.h> 90 #include <sys/bus.h> 91 #include <sys/queue.h> 92 #include <sys/stat.h> 93 #include <sys/devicestat.h> 94 #include <sys/kthread.h> 95 #include <sys/module.h> 96 #include <sys/proc.h> 97 #include <sys/lock.h> 98 #include <sys/sysctl.h> 99 #include <sys/poll.h> 100 #include <sys/ioccom.h> 101 #include <vm/vm.h> 102 #include <vm/vm_param.h> 103 #include <vm/pmap.h> 104 105 #include <isa/rtc.h> 106 107 #include <machine/bus.h> 108 #include <machine/resource.h> 109 #include <machine/atomic.h> 110 #include <sys/conf.h> 111 #include <sys/rman.h> 112 113 #include <cam/cam.h> 114 #include <cam/cam_ccb.h> 115 #include <cam/cam_sim.h> 116 #include <cam/cam_periph.h> 117 #include <cam/cam_xpt_periph.h> 118 #include <cam/cam_xpt_sim.h> 119 #include <cam/cam_debug.h> 120 #include <cam/scsi/scsi_all.h> 121 #include <cam/scsi/scsi_message.h> 122 /* 123 ************************************************************************** 124 ************************************************************************** 125 */ 126 #if __FreeBSD_version >= 500005 127 #include <sys/selinfo.h> 128 #include <sys/mutex.h> 129 #include <sys/endian.h> 130 #include <dev/pci/pcivar.h> 131 #include <dev/pci/pcireg.h> 132 #else 133 #include <sys/select.h> 134 #include <pci/pcivar.h> 135 #include <pci/pcireg.h> 136 #endif 137 138 #if !defined(CAM_NEW_TRAN_CODE) && __FreeBSD_version >= 700025 139 #define CAM_NEW_TRAN_CODE 1 140 #endif 141 142 #if __FreeBSD_version > 500000 143 #define arcmsr_callout_init(a) callout_init(a, /*mpsafe*/1); 144 #else 145 #define arcmsr_callout_init(a) callout_init(a); 146 #endif 147 148 #define ARCMSR_DRIVER_VERSION "Driver Version 1.20.00.27 2013-05-06" 149 #include <dev/arcmsr/arcmsr.h> 150 /* 151 ************************************************************************** 152 ************************************************************************** 153 */ 154 static void arcmsr_free_srb(struct CommandControlBlock *srb); 155 static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb); 156 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb); 157 static int arcmsr_probe(device_t dev); 158 static int arcmsr_attach(device_t dev); 159 static int arcmsr_detach(device_t dev); 160 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg); 161 static void arcmsr_iop_parking(struct AdapterControlBlock *acb); 162 static int arcmsr_shutdown(device_t dev); 163 static void arcmsr_interrupt(struct AdapterControlBlock *acb); 164 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb); 165 static void arcmsr_free_resource(struct AdapterControlBlock *acb); 166 static void arcmsr_bus_reset(struct AdapterControlBlock *acb); 167 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb); 168 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb); 169 static void arcmsr_iop_init(struct AdapterControlBlock *acb); 170 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb); 171 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, struct QBUFFER *prbuffer); 172 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb); 173 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb); 174 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag); 175 static void arcmsr_iop_reset(struct AdapterControlBlock *acb); 176 static void arcmsr_report_sense_info(struct CommandControlBlock *srb); 177 static void arcmsr_build_srb(struct CommandControlBlock *srb, bus_dma_segment_t *dm_segs, u_int32_t nseg); 178 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb); 179 static int arcmsr_resume(device_t dev); 180 static int arcmsr_suspend(device_t dev); 181 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb); 182 static void arcmsr_polling_devmap(void *arg); 183 static void arcmsr_srb_timeout(void *arg); 184 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb); 185 #ifdef ARCMSR_DEBUG1 186 static void arcmsr_dump_data(struct AdapterControlBlock *acb); 187 #endif 188 /* 189 ************************************************************************** 190 ************************************************************************** 191 */ 192 static void UDELAY(u_int32_t us) { DELAY(us); } 193 /* 194 ************************************************************************** 195 ************************************************************************** 196 */ 197 static bus_dmamap_callback_t arcmsr_map_free_srb; 198 static bus_dmamap_callback_t arcmsr_execute_srb; 199 /* 200 ************************************************************************** 201 ************************************************************************** 202 */ 203 static d_open_t arcmsr_open; 204 static d_close_t arcmsr_close; 205 static d_ioctl_t arcmsr_ioctl; 206 207 static device_method_t arcmsr_methods[]={ 208 DEVMETHOD(device_probe, arcmsr_probe), 209 DEVMETHOD(device_attach, arcmsr_attach), 210 DEVMETHOD(device_detach, arcmsr_detach), 211 DEVMETHOD(device_shutdown, arcmsr_shutdown), 212 DEVMETHOD(device_suspend, arcmsr_suspend), 213 DEVMETHOD(device_resume, arcmsr_resume), 214 215 #if __FreeBSD_version >= 803000 216 DEVMETHOD_END 217 #else 218 { 0, 0 } 219 #endif 220 }; 221 222 static driver_t arcmsr_driver={ 223 "arcmsr", arcmsr_methods, sizeof(struct AdapterControlBlock) 224 }; 225 226 static devclass_t arcmsr_devclass; 227 DRIVER_MODULE(arcmsr, pci, arcmsr_driver, arcmsr_devclass, 0, 0); 228 MODULE_DEPEND(arcmsr, pci, 1, 1, 1); 229 MODULE_DEPEND(arcmsr, cam, 1, 1, 1); 230 #ifndef BUS_DMA_COHERENT 231 #define BUS_DMA_COHERENT 0x04 /* hint: map memory in a coherent way */ 232 #endif 233 #if __FreeBSD_version >= 501000 234 static struct cdevsw arcmsr_cdevsw={ 235 #if __FreeBSD_version >= 503000 236 .d_version = D_VERSION, 237 #endif 238 #if (__FreeBSD_version>=503000 && __FreeBSD_version<600034) 239 .d_flags = D_NEEDGIANT, 240 #endif 241 .d_open = arcmsr_open, /* open */ 242 .d_close = arcmsr_close, /* close */ 243 .d_ioctl = arcmsr_ioctl, /* ioctl */ 244 .d_name = "arcmsr", /* name */ 245 }; 246 #else 247 #define ARCMSR_CDEV_MAJOR 180 248 249 static struct cdevsw arcmsr_cdevsw = { 250 arcmsr_open, /* open */ 251 arcmsr_close, /* close */ 252 noread, /* read */ 253 nowrite, /* write */ 254 arcmsr_ioctl, /* ioctl */ 255 nopoll, /* poll */ 256 nommap, /* mmap */ 257 nostrategy, /* strategy */ 258 "arcmsr", /* name */ 259 ARCMSR_CDEV_MAJOR, /* major */ 260 nodump, /* dump */ 261 nopsize, /* psize */ 262 0 /* flags */ 263 }; 264 #endif 265 /* 266 ************************************************************************** 267 ************************************************************************** 268 */ 269 #if __FreeBSD_version < 500005 270 static int arcmsr_open(dev_t dev, int flags, int fmt, struct proc *proc) 271 #else 272 #if __FreeBSD_version < 503000 273 static int arcmsr_open(dev_t dev, int flags, int fmt, struct thread *proc) 274 #else 275 static int arcmsr_open(struct cdev *dev, int flags, int fmt, struct thread *proc) 276 #endif 277 #endif 278 { 279 #if __FreeBSD_version < 503000 280 struct AdapterControlBlock *acb = dev->si_drv1; 281 #else 282 int unit = dev2unit(dev); 283 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit); 284 #endif 285 if(acb == NULL) { 286 return ENXIO; 287 } 288 return (0); 289 } 290 /* 291 ************************************************************************** 292 ************************************************************************** 293 */ 294 #if __FreeBSD_version < 500005 295 static int arcmsr_close(dev_t dev, int flags, int fmt, struct proc *proc) 296 #else 297 #if __FreeBSD_version < 503000 298 static int arcmsr_close(dev_t dev, int flags, int fmt, struct thread *proc) 299 #else 300 static int arcmsr_close(struct cdev *dev, int flags, int fmt, struct thread *proc) 301 #endif 302 #endif 303 { 304 #if __FreeBSD_version < 503000 305 struct AdapterControlBlock *acb = dev->si_drv1; 306 #else 307 int unit = dev2unit(dev); 308 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit); 309 #endif 310 if(acb == NULL) { 311 return ENXIO; 312 } 313 return 0; 314 } 315 /* 316 ************************************************************************** 317 ************************************************************************** 318 */ 319 #if __FreeBSD_version < 500005 320 static int arcmsr_ioctl(dev_t dev, u_long ioctl_cmd, caddr_t arg, int flags, struct proc *proc) 321 #else 322 #if __FreeBSD_version < 503000 323 static int arcmsr_ioctl(dev_t dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc) 324 #else 325 static int arcmsr_ioctl(struct cdev *dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc) 326 #endif 327 #endif 328 { 329 #if __FreeBSD_version < 503000 330 struct AdapterControlBlock *acb = dev->si_drv1; 331 #else 332 int unit = dev2unit(dev); 333 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit); 334 #endif 335 336 if(acb == NULL) { 337 return ENXIO; 338 } 339 return (arcmsr_iop_ioctlcmd(acb, ioctl_cmd, arg)); 340 } 341 /* 342 ********************************************************************** 343 ********************************************************************** 344 */ 345 static u_int32_t arcmsr_disable_allintr( struct AdapterControlBlock *acb) 346 { 347 u_int32_t intmask_org = 0; 348 349 switch (acb->adapter_type) { 350 case ACB_ADAPTER_TYPE_A: { 351 /* disable all outbound interrupt */ 352 intmask_org = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intmask); /* disable outbound message0 int */ 353 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE); 354 } 355 break; 356 case ACB_ADAPTER_TYPE_B: { 357 /* disable all outbound interrupt */ 358 intmask_org = CHIP_REG_READ32(HBB_DOORBELL, 359 0, iop2drv_doorbell_mask) & (~ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); /* disable outbound message0 int */ 360 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell_mask, 0); /* disable all interrupt */ 361 } 362 break; 363 case ACB_ADAPTER_TYPE_C: { 364 /* disable all outbound interrupt */ 365 intmask_org = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask) ; /* disable outbound message0 int */ 366 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE); 367 } 368 break; 369 case ACB_ADAPTER_TYPE_D: { 370 /* disable all outbound interrupt */ 371 intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable) ; /* disable outbound message0 int */ 372 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE); 373 } 374 break; 375 } 376 return (intmask_org); 377 } 378 /* 379 ********************************************************************** 380 ********************************************************************** 381 */ 382 static void arcmsr_enable_allintr( struct AdapterControlBlock *acb, u_int32_t intmask_org) 383 { 384 u_int32_t mask; 385 386 switch (acb->adapter_type) { 387 case ACB_ADAPTER_TYPE_A: { 388 /* enable outbound Post Queue, outbound doorbell Interrupt */ 389 mask = ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE|ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE); 390 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org & mask); 391 acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff; 392 } 393 break; 394 case ACB_ADAPTER_TYPE_B: { 395 /* enable ARCMSR_IOP2DRV_MESSAGE_CMD_DONE */ 396 mask = (ARCMSR_IOP2DRV_DATA_WRITE_OK|ARCMSR_IOP2DRV_DATA_READ_OK|ARCMSR_IOP2DRV_CDB_DONE|ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); 397 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell_mask, intmask_org | mask); /*1=interrupt enable, 0=interrupt disable*/ 398 acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f; 399 } 400 break; 401 case ACB_ADAPTER_TYPE_C: { 402 /* enable outbound Post Queue, outbound doorbell Interrupt */ 403 mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK); 404 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org & mask); 405 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f; 406 } 407 break; 408 case ACB_ADAPTER_TYPE_D: { 409 /* enable outbound Post Queue, outbound doorbell Interrupt */ 410 mask = ARCMSR_HBDMU_ALL_INT_ENABLE; 411 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | mask); 412 CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); 413 acb->outbound_int_enable = mask; 414 } 415 break; 416 } 417 } 418 /* 419 ********************************************************************** 420 ********************************************************************** 421 */ 422 static u_int8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb) 423 { 424 u_int32_t Index; 425 u_int8_t Retries = 0x00; 426 427 do { 428 for(Index=0; Index < 100; Index++) { 429 if(CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { 430 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);/*clear interrupt*/ 431 return TRUE; 432 } 433 UDELAY(10000); 434 }/*max 1 seconds*/ 435 }while(Retries++ < 20);/*max 20 sec*/ 436 return (FALSE); 437 } 438 /* 439 ********************************************************************** 440 ********************************************************************** 441 */ 442 static u_int8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb) 443 { 444 u_int32_t Index; 445 u_int8_t Retries = 0x00; 446 447 do { 448 for(Index=0; Index < 100; Index++) { 449 if(CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) { 450 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt*/ 451 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 452 return TRUE; 453 } 454 UDELAY(10000); 455 }/*max 1 seconds*/ 456 }while(Retries++ < 20);/*max 20 sec*/ 457 return (FALSE); 458 } 459 /* 460 ********************************************************************** 461 ********************************************************************** 462 */ 463 static u_int8_t arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock *acb) 464 { 465 u_int32_t Index; 466 u_int8_t Retries = 0x00; 467 468 do { 469 for(Index=0; Index < 100; Index++) { 470 if(CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 471 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);/*clear interrupt*/ 472 return TRUE; 473 } 474 UDELAY(10000); 475 }/*max 1 seconds*/ 476 }while(Retries++ < 20);/*max 20 sec*/ 477 return (FALSE); 478 } 479 /* 480 ********************************************************************** 481 ********************************************************************** 482 */ 483 static u_int8_t arcmsr_hbd_wait_msgint_ready(struct AdapterControlBlock *acb) 484 { 485 u_int32_t Index; 486 u_int8_t Retries = 0x00; 487 488 do { 489 for(Index=0; Index < 100; Index++) { 490 if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) { 491 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);/*clear interrupt*/ 492 return TRUE; 493 } 494 UDELAY(10000); 495 }/*max 1 seconds*/ 496 }while(Retries++ < 20);/*max 20 sec*/ 497 return (FALSE); 498 } 499 /* 500 ************************************************************************ 501 ************************************************************************ 502 */ 503 static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb) 504 { 505 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 506 507 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 508 do { 509 if(arcmsr_hba_wait_msgint_ready(acb)) { 510 break; 511 } else { 512 retry_count--; 513 } 514 }while(retry_count != 0); 515 } 516 /* 517 ************************************************************************ 518 ************************************************************************ 519 */ 520 static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb) 521 { 522 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 523 524 CHIP_REG_WRITE32(HBB_DOORBELL, 525 0, drv2iop_doorbell, ARCMSR_MESSAGE_FLUSH_CACHE); 526 do { 527 if(arcmsr_hbb_wait_msgint_ready(acb)) { 528 break; 529 } else { 530 retry_count--; 531 } 532 }while(retry_count != 0); 533 } 534 /* 535 ************************************************************************ 536 ************************************************************************ 537 */ 538 static void arcmsr_flush_hbc_cache(struct AdapterControlBlock *acb) 539 { 540 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 541 542 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 543 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 544 do { 545 if(arcmsr_hbc_wait_msgint_ready(acb)) { 546 break; 547 } else { 548 retry_count--; 549 } 550 }while(retry_count != 0); 551 } 552 /* 553 ************************************************************************ 554 ************************************************************************ 555 */ 556 static void arcmsr_flush_hbd_cache(struct AdapterControlBlock *acb) 557 { 558 int retry_count = 30; /* enlarge wait flush adapter cache time: 10 minute */ 559 560 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 561 do { 562 if(arcmsr_hbd_wait_msgint_ready(acb)) { 563 break; 564 } else { 565 retry_count--; 566 } 567 }while(retry_count != 0); 568 } 569 /* 570 ************************************************************************ 571 ************************************************************************ 572 */ 573 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb) 574 { 575 switch (acb->adapter_type) { 576 case ACB_ADAPTER_TYPE_A: { 577 arcmsr_flush_hba_cache(acb); 578 } 579 break; 580 case ACB_ADAPTER_TYPE_B: { 581 arcmsr_flush_hbb_cache(acb); 582 } 583 break; 584 case ACB_ADAPTER_TYPE_C: { 585 arcmsr_flush_hbc_cache(acb); 586 } 587 break; 588 case ACB_ADAPTER_TYPE_D: { 589 arcmsr_flush_hbd_cache(acb); 590 } 591 break; 592 } 593 } 594 /* 595 ******************************************************************************* 596 ******************************************************************************* 597 */ 598 static int arcmsr_suspend(device_t dev) 599 { 600 struct AdapterControlBlock *acb = device_get_softc(dev); 601 602 /* flush controller */ 603 arcmsr_iop_parking(acb); 604 /* disable all outbound interrupt */ 605 arcmsr_disable_allintr(acb); 606 return(0); 607 } 608 /* 609 ******************************************************************************* 610 ******************************************************************************* 611 */ 612 static int arcmsr_resume(device_t dev) 613 { 614 struct AdapterControlBlock *acb = device_get_softc(dev); 615 616 arcmsr_iop_init(acb); 617 return(0); 618 } 619 /* 620 ********************************************************************************* 621 ********************************************************************************* 622 */ 623 static void arcmsr_async(void *cb_arg, u_int32_t code, struct cam_path *path, void *arg) 624 { 625 struct AdapterControlBlock *acb; 626 u_int8_t target_id, target_lun; 627 struct cam_sim *sim; 628 629 sim = (struct cam_sim *) cb_arg; 630 acb =(struct AdapterControlBlock *) cam_sim_softc(sim); 631 switch (code) { 632 case AC_LOST_DEVICE: 633 target_id = xpt_path_target_id(path); 634 target_lun = xpt_path_lun_id(path); 635 if((target_id > ARCMSR_MAX_TARGETID) || (target_lun > ARCMSR_MAX_TARGETLUN)) { 636 break; 637 } 638 // printf("%s:scsi id=%d lun=%d device lost \n", device_get_name(acb->pci_dev), target_id, target_lun); 639 break; 640 default: 641 break; 642 } 643 } 644 /* 645 ********************************************************************** 646 ********************************************************************** 647 */ 648 static void arcmsr_report_sense_info(struct CommandControlBlock *srb) 649 { 650 union ccb *pccb = srb->pccb; 651 652 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 653 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 654 if(pccb->csio.sense_len) { 655 memset(&pccb->csio.sense_data, 0, sizeof(pccb->csio.sense_data)); 656 memcpy(&pccb->csio.sense_data, srb->arcmsr_cdb.SenseData, 657 get_min(sizeof(struct SENSE_DATA), sizeof(pccb->csio.sense_data))); 658 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); /* Valid,ErrorCode */ 659 pccb->ccb_h.status |= CAM_AUTOSNS_VALID; 660 } 661 } 662 /* 663 ********************************************************************* 664 ********************************************************************* 665 */ 666 static void arcmsr_abort_hba_allcmd(struct AdapterControlBlock *acb) 667 { 668 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 669 if(!arcmsr_hba_wait_msgint_ready(acb)) { 670 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 671 } 672 } 673 /* 674 ********************************************************************* 675 ********************************************************************* 676 */ 677 static void arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb) 678 { 679 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_ABORT_CMD); 680 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 681 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 682 } 683 } 684 /* 685 ********************************************************************* 686 ********************************************************************* 687 */ 688 static void arcmsr_abort_hbc_allcmd(struct AdapterControlBlock *acb) 689 { 690 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 691 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 692 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 693 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 694 } 695 } 696 /* 697 ********************************************************************* 698 ********************************************************************* 699 */ 700 static void arcmsr_abort_hbd_allcmd(struct AdapterControlBlock *acb) 701 { 702 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 703 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 704 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 705 } 706 } 707 /* 708 ********************************************************************* 709 ********************************************************************* 710 */ 711 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb) 712 { 713 switch (acb->adapter_type) { 714 case ACB_ADAPTER_TYPE_A: { 715 arcmsr_abort_hba_allcmd(acb); 716 } 717 break; 718 case ACB_ADAPTER_TYPE_B: { 719 arcmsr_abort_hbb_allcmd(acb); 720 } 721 break; 722 case ACB_ADAPTER_TYPE_C: { 723 arcmsr_abort_hbc_allcmd(acb); 724 } 725 break; 726 case ACB_ADAPTER_TYPE_D: { 727 arcmsr_abort_hbd_allcmd(acb); 728 } 729 break; 730 } 731 } 732 /* 733 ********************************************************************** 734 ********************************************************************** 735 */ 736 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag) 737 { 738 struct AdapterControlBlock *acb = srb->acb; 739 union ccb *pccb = srb->pccb; 740 741 if(srb->srb_flags & SRB_FLAG_TIMER_START) 742 callout_stop(&srb->ccb_callout); 743 if((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 744 bus_dmasync_op_t op; 745 746 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 747 op = BUS_DMASYNC_POSTREAD; 748 } else { 749 op = BUS_DMASYNC_POSTWRITE; 750 } 751 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op); 752 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap); 753 } 754 if(stand_flag == 1) { 755 atomic_subtract_int(&acb->srboutstandingcount, 1); 756 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) && ( 757 acb->srboutstandingcount < (acb->maxOutstanding -10))) { 758 acb->acb_flags &= ~ACB_F_CAM_DEV_QFRZN; 759 pccb->ccb_h.status |= CAM_RELEASE_SIMQ; 760 } 761 } 762 if(srb->srb_state != ARCMSR_SRB_TIMEOUT) 763 arcmsr_free_srb(srb); 764 acb->pktReturnCount++; 765 xpt_done(pccb); 766 } 767 /* 768 ************************************************************************** 769 ************************************************************************** 770 */ 771 static void arcmsr_report_srb_state(struct AdapterControlBlock *acb, struct CommandControlBlock *srb, u_int16_t error) 772 { 773 int target, lun; 774 775 target = srb->pccb->ccb_h.target_id; 776 lun = srb->pccb->ccb_h.target_lun; 777 if(error == FALSE) { 778 if(acb->devstate[target][lun] == ARECA_RAID_GONE) { 779 acb->devstate[target][lun] = ARECA_RAID_GOOD; 780 } 781 srb->pccb->ccb_h.status |= CAM_REQ_CMP; 782 arcmsr_srb_complete(srb, 1); 783 } else { 784 switch(srb->arcmsr_cdb.DeviceStatus) { 785 case ARCMSR_DEV_SELECT_TIMEOUT: { 786 if(acb->devstate[target][lun] == ARECA_RAID_GOOD) { 787 printf( "arcmsr%d: Target=%x, Lun=%x, selection timeout, raid volume was lost\n", acb->pci_unit, target, lun); 788 } 789 acb->devstate[target][lun] = ARECA_RAID_GONE; 790 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 791 arcmsr_srb_complete(srb, 1); 792 } 793 break; 794 case ARCMSR_DEV_ABORTED: 795 case ARCMSR_DEV_INIT_FAIL: { 796 acb->devstate[target][lun] = ARECA_RAID_GONE; 797 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 798 arcmsr_srb_complete(srb, 1); 799 } 800 break; 801 case SCSISTAT_CHECK_CONDITION: { 802 acb->devstate[target][lun] = ARECA_RAID_GOOD; 803 arcmsr_report_sense_info(srb); 804 arcmsr_srb_complete(srb, 1); 805 } 806 break; 807 default: 808 printf("arcmsr%d: scsi id=%d lun=%d isr got command error done,but got unknown DeviceStatus=0x%x \n" 809 , acb->pci_unit, target, lun ,srb->arcmsr_cdb.DeviceStatus); 810 acb->devstate[target][lun] = ARECA_RAID_GONE; 811 srb->pccb->ccb_h.status |= CAM_UNCOR_PARITY; 812 /*unknown error or crc error just for retry*/ 813 arcmsr_srb_complete(srb, 1); 814 break; 815 } 816 } 817 } 818 /* 819 ************************************************************************** 820 ************************************************************************** 821 */ 822 static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, u_int32_t flag_srb, u_int16_t error) 823 { 824 struct CommandControlBlock *srb; 825 826 /* check if command done with no error*/ 827 switch (acb->adapter_type) { 828 case ACB_ADAPTER_TYPE_C: 829 case ACB_ADAPTER_TYPE_D: 830 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0)); /*frame must be 32 bytes aligned*/ 831 break; 832 case ACB_ADAPTER_TYPE_A: 833 case ACB_ADAPTER_TYPE_B: 834 default: 835 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 836 break; 837 } 838 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 839 if(srb->srb_state == ARCMSR_SRB_TIMEOUT) { 840 arcmsr_free_srb(srb); 841 printf("arcmsr%d: srb='%p' return srb has been timeouted\n", acb->pci_unit, srb); 842 return; 843 } 844 printf("arcmsr%d: return srb has been completed\n" 845 "srb='%p' srb_state=0x%x outstanding srb count=%d \n", 846 acb->pci_unit, srb, srb->srb_state, acb->srboutstandingcount); 847 return; 848 } 849 arcmsr_report_srb_state(acb, srb, error); 850 } 851 /* 852 ************************************************************************** 853 ************************************************************************** 854 */ 855 static void arcmsr_srb_timeout(void *arg) 856 { 857 struct CommandControlBlock *srb = (struct CommandControlBlock *)arg; 858 struct AdapterControlBlock *acb; 859 int target, lun; 860 u_int8_t cmd; 861 862 target = srb->pccb->ccb_h.target_id; 863 lun = srb->pccb->ccb_h.target_lun; 864 acb = srb->acb; 865 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 866 if(srb->srb_state == ARCMSR_SRB_START) 867 { 868 cmd = srb->pccb->csio.cdb_io.cdb_bytes[0]; 869 srb->srb_state = ARCMSR_SRB_TIMEOUT; 870 srb->pccb->ccb_h.status |= CAM_CMD_TIMEOUT; 871 arcmsr_srb_complete(srb, 1); 872 printf("arcmsr%d: scsi id %d lun %d cmd=0x%x srb='%p' ccb command time out!\n", 873 acb->pci_unit, target, lun, cmd, srb); 874 } 875 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 876 #ifdef ARCMSR_DEBUG1 877 arcmsr_dump_data(acb); 878 #endif 879 } 880 881 /* 882 ********************************************************************** 883 ********************************************************************** 884 */ 885 static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb) 886 { 887 int i=0; 888 u_int32_t flag_srb; 889 u_int16_t error; 890 891 switch (acb->adapter_type) { 892 case ACB_ADAPTER_TYPE_A: { 893 u_int32_t outbound_intstatus; 894 895 /*clear and abort all outbound posted Q*/ 896 outbound_intstatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 897 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);/*clear interrupt*/ 898 while(((flag_srb=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_queueport)) != 0xFFFFFFFF) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) { 899 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 900 arcmsr_drain_donequeue(acb, flag_srb, error); 901 } 902 } 903 break; 904 case ACB_ADAPTER_TYPE_B: { 905 struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu; 906 907 /*clear all outbound posted Q*/ 908 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */ 909 for(i=0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) { 910 if((flag_srb = phbbmu->done_qbuffer[i]) != 0) { 911 phbbmu->done_qbuffer[i] = 0; 912 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 913 arcmsr_drain_donequeue(acb, flag_srb, error); 914 } 915 phbbmu->post_qbuffer[i] = 0; 916 }/*drain reply FIFO*/ 917 phbbmu->doneq_index = 0; 918 phbbmu->postq_index = 0; 919 } 920 break; 921 case ACB_ADAPTER_TYPE_C: { 922 923 while((CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) { 924 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 925 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 926 arcmsr_drain_donequeue(acb, flag_srb, error); 927 } 928 } 929 break; 930 case ACB_ADAPTER_TYPE_D: { 931 arcmsr_hbd_postqueue_isr(acb); 932 } 933 break; 934 } 935 } 936 /* 937 **************************************************************************** 938 **************************************************************************** 939 */ 940 static void arcmsr_iop_reset(struct AdapterControlBlock *acb) 941 { 942 struct CommandControlBlock *srb; 943 u_int32_t intmask_org; 944 u_int32_t i=0; 945 946 if(acb->srboutstandingcount>0) { 947 /* disable all outbound interrupt */ 948 intmask_org = arcmsr_disable_allintr(acb); 949 /*clear and abort all outbound posted Q*/ 950 arcmsr_done4abort_postqueue(acb); 951 /* talk to iop 331 outstanding command aborted*/ 952 arcmsr_abort_allcmd(acb); 953 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 954 srb = acb->psrb_pool[i]; 955 if(srb->srb_state == ARCMSR_SRB_START) { 956 srb->srb_state = ARCMSR_SRB_ABORTED; 957 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 958 arcmsr_srb_complete(srb, 1); 959 printf("arcmsr%d: scsi id=%d lun=%d srb='%p' aborted\n" 960 , acb->pci_unit, srb->pccb->ccb_h.target_id 961 , srb->pccb->ccb_h.target_lun, srb); 962 } 963 } 964 /* enable all outbound interrupt */ 965 arcmsr_enable_allintr(acb, intmask_org); 966 } 967 acb->srboutstandingcount = 0; 968 acb->workingsrb_doneindex = 0; 969 acb->workingsrb_startindex = 0; 970 acb->pktRequestCount = 0; 971 acb->pktReturnCount = 0; 972 } 973 /* 974 ********************************************************************** 975 ********************************************************************** 976 */ 977 static void arcmsr_build_srb(struct CommandControlBlock *srb, 978 bus_dma_segment_t *dm_segs, u_int32_t nseg) 979 { 980 struct ARCMSR_CDB *arcmsr_cdb = &srb->arcmsr_cdb; 981 u_int8_t *psge = (u_int8_t *)&arcmsr_cdb->u; 982 u_int32_t address_lo, address_hi; 983 union ccb *pccb = srb->pccb; 984 struct ccb_scsiio *pcsio = &pccb->csio; 985 u_int32_t arccdbsize = 0x30; 986 987 memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB)); 988 arcmsr_cdb->Bus = 0; 989 arcmsr_cdb->TargetID = pccb->ccb_h.target_id; 990 arcmsr_cdb->LUN = pccb->ccb_h.target_lun; 991 arcmsr_cdb->Function = 1; 992 arcmsr_cdb->CdbLength = (u_int8_t)pcsio->cdb_len; 993 bcopy(pcsio->cdb_io.cdb_bytes, arcmsr_cdb->Cdb, pcsio->cdb_len); 994 if(nseg != 0) { 995 struct AdapterControlBlock *acb = srb->acb; 996 bus_dmasync_op_t op; 997 u_int32_t length, i, cdb_sgcount = 0; 998 999 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1000 op = BUS_DMASYNC_PREREAD; 1001 } else { 1002 op = BUS_DMASYNC_PREWRITE; 1003 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE; 1004 srb->srb_flags |= SRB_FLAG_WRITE; 1005 } 1006 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op); 1007 for(i=0; i < nseg; i++) { 1008 /* Get the physical address of the current data pointer */ 1009 length = arcmsr_htole32(dm_segs[i].ds_len); 1010 address_lo = arcmsr_htole32(dma_addr_lo32(dm_segs[i].ds_addr)); 1011 address_hi = arcmsr_htole32(dma_addr_hi32(dm_segs[i].ds_addr)); 1012 if(address_hi == 0) { 1013 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge; 1014 pdma_sg->address = address_lo; 1015 pdma_sg->length = length; 1016 psge += sizeof(struct SG32ENTRY); 1017 arccdbsize += sizeof(struct SG32ENTRY); 1018 } else { 1019 u_int32_t sg64s_size = 0, tmplength = length; 1020 1021 while(1) { 1022 u_int64_t span4G, length0; 1023 struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge; 1024 1025 span4G = (u_int64_t)address_lo + tmplength; 1026 pdma_sg->addresshigh = address_hi; 1027 pdma_sg->address = address_lo; 1028 if(span4G > 0x100000000) { 1029 /*see if cross 4G boundary*/ 1030 length0 = 0x100000000-address_lo; 1031 pdma_sg->length = (u_int32_t)length0 | IS_SG64_ADDR; 1032 address_hi = address_hi+1; 1033 address_lo = 0; 1034 tmplength = tmplength - (u_int32_t)length0; 1035 sg64s_size += sizeof(struct SG64ENTRY); 1036 psge += sizeof(struct SG64ENTRY); 1037 cdb_sgcount++; 1038 } else { 1039 pdma_sg->length = tmplength | IS_SG64_ADDR; 1040 sg64s_size += sizeof(struct SG64ENTRY); 1041 psge += sizeof(struct SG64ENTRY); 1042 break; 1043 } 1044 } 1045 arccdbsize += sg64s_size; 1046 } 1047 cdb_sgcount++; 1048 } 1049 arcmsr_cdb->sgcount = (u_int8_t)cdb_sgcount; 1050 arcmsr_cdb->DataLength = pcsio->dxfer_len; 1051 if( arccdbsize > 256) { 1052 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE; 1053 } 1054 } else { 1055 arcmsr_cdb->DataLength = 0; 1056 } 1057 srb->arc_cdb_size = arccdbsize; 1058 arcmsr_cdb->msgPages = (arccdbsize/256) + ((arccdbsize % 256) ? 1 : 0); 1059 } 1060 /* 1061 ************************************************************************** 1062 ************************************************************************** 1063 */ 1064 static void arcmsr_post_srb(struct AdapterControlBlock *acb, struct CommandControlBlock *srb) 1065 { 1066 u_int32_t cdb_phyaddr_low = (u_int32_t) srb->cdb_phyaddr_low; 1067 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&srb->arcmsr_cdb; 1068 1069 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, (srb->srb_flags & SRB_FLAG_WRITE) ? BUS_DMASYNC_POSTWRITE:BUS_DMASYNC_POSTREAD); 1070 atomic_add_int(&acb->srboutstandingcount, 1); 1071 srb->srb_state = ARCMSR_SRB_START; 1072 1073 switch (acb->adapter_type) { 1074 case ACB_ADAPTER_TYPE_A: { 1075 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { 1076 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low|ARCMSR_SRBPOST_FLAG_SGL_BSIZE); 1077 } else { 1078 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low); 1079 } 1080 } 1081 break; 1082 case ACB_ADAPTER_TYPE_B: { 1083 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1084 int ending_index, index; 1085 1086 index = phbbmu->postq_index; 1087 ending_index = ((index+1) % ARCMSR_MAX_HBB_POSTQUEUE); 1088 phbbmu->post_qbuffer[ending_index] = 0; 1089 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { 1090 phbbmu->post_qbuffer[index] = cdb_phyaddr_low | ARCMSR_SRBPOST_FLAG_SGL_BSIZE; 1091 } else { 1092 phbbmu->post_qbuffer[index] = cdb_phyaddr_low; 1093 } 1094 index++; 1095 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 1096 phbbmu->postq_index = index; 1097 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_CDB_POSTED); 1098 } 1099 break; 1100 case ACB_ADAPTER_TYPE_C: { 1101 u_int32_t ccb_post_stamp, arc_cdb_size, cdb_phyaddr_hi32; 1102 1103 arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size; 1104 ccb_post_stamp = (cdb_phyaddr_low | ((arc_cdb_size-1) >> 6) | 1); 1105 cdb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high; 1106 if(cdb_phyaddr_hi32) 1107 { 1108 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_high, cdb_phyaddr_hi32); 1109 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp); 1110 } 1111 else 1112 { 1113 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp); 1114 } 1115 } 1116 break; 1117 case ACB_ADAPTER_TYPE_D: { 1118 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1119 u_int16_t index_stripped; 1120 u_int16_t postq_index; 1121 struct InBound_SRB *pinbound_srb; 1122 1123 ARCMSR_LOCK_ACQUIRE(&acb->postDone_lock); 1124 postq_index = phbdmu->postq_index; 1125 pinbound_srb = (struct InBound_SRB *)&phbdmu->post_qbuffer[postq_index & 0xFF]; 1126 pinbound_srb->addressHigh = srb->cdb_phyaddr_high; 1127 pinbound_srb->addressLow = srb->cdb_phyaddr_low; 1128 pinbound_srb->length = srb->arc_cdb_size >> 2; 1129 arcmsr_cdb->Context = srb->cdb_phyaddr_low; 1130 if (postq_index & 0x4000) { 1131 index_stripped = postq_index & 0xFF; 1132 index_stripped += 1; 1133 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1134 phbdmu->postq_index = index_stripped ? (index_stripped | 0x4000) : index_stripped; 1135 } else { 1136 index_stripped = postq_index; 1137 index_stripped += 1; 1138 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1139 phbdmu->postq_index = index_stripped ? index_stripped : (index_stripped | 0x4000); 1140 } 1141 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inboundlist_write_pointer, postq_index); 1142 ARCMSR_LOCK_RELEASE(&acb->postDone_lock); 1143 } 1144 break; 1145 } 1146 } 1147 /* 1148 ************************************************************************ 1149 ************************************************************************ 1150 */ 1151 static struct QBUFFER *arcmsr_get_iop_rqbuffer( struct AdapterControlBlock *acb) 1152 { 1153 struct QBUFFER *qbuffer=NULL; 1154 1155 switch (acb->adapter_type) { 1156 case ACB_ADAPTER_TYPE_A: { 1157 struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu; 1158 1159 qbuffer = (struct QBUFFER *)&phbamu->message_rbuffer; 1160 } 1161 break; 1162 case ACB_ADAPTER_TYPE_B: { 1163 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1164 1165 qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_rbuffer; 1166 } 1167 break; 1168 case ACB_ADAPTER_TYPE_C: { 1169 struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu; 1170 1171 qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer; 1172 } 1173 break; 1174 case ACB_ADAPTER_TYPE_D: { 1175 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1176 1177 qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_rbuffer; 1178 } 1179 break; 1180 } 1181 return(qbuffer); 1182 } 1183 /* 1184 ************************************************************************ 1185 ************************************************************************ 1186 */ 1187 static struct QBUFFER *arcmsr_get_iop_wqbuffer( struct AdapterControlBlock *acb) 1188 { 1189 struct QBUFFER *qbuffer = NULL; 1190 1191 switch (acb->adapter_type) { 1192 case ACB_ADAPTER_TYPE_A: { 1193 struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu; 1194 1195 qbuffer = (struct QBUFFER *)&phbamu->message_wbuffer; 1196 } 1197 break; 1198 case ACB_ADAPTER_TYPE_B: { 1199 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1200 1201 qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_wbuffer; 1202 } 1203 break; 1204 case ACB_ADAPTER_TYPE_C: { 1205 struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu; 1206 1207 qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer; 1208 } 1209 break; 1210 case ACB_ADAPTER_TYPE_D: { 1211 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1212 1213 qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_wbuffer; 1214 } 1215 break; 1216 } 1217 return(qbuffer); 1218 } 1219 /* 1220 ************************************************************************** 1221 ************************************************************************** 1222 */ 1223 static void arcmsr_iop_message_read(struct AdapterControlBlock *acb) 1224 { 1225 switch (acb->adapter_type) { 1226 case ACB_ADAPTER_TYPE_A: { 1227 /* let IOP know data has been read */ 1228 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK); 1229 } 1230 break; 1231 case ACB_ADAPTER_TYPE_B: { 1232 /* let IOP know data has been read */ 1233 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK); 1234 } 1235 break; 1236 case ACB_ADAPTER_TYPE_C: { 1237 /* let IOP know data has been read */ 1238 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK); 1239 } 1240 break; 1241 case ACB_ADAPTER_TYPE_D: { 1242 /* let IOP know data has been read */ 1243 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ); 1244 } 1245 break; 1246 } 1247 } 1248 /* 1249 ************************************************************************** 1250 ************************************************************************** 1251 */ 1252 static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb) 1253 { 1254 switch (acb->adapter_type) { 1255 case ACB_ADAPTER_TYPE_A: { 1256 /* 1257 ** push inbound doorbell tell iop, driver data write ok 1258 ** and wait reply on next hwinterrupt for next Qbuffer post 1259 */ 1260 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK); 1261 } 1262 break; 1263 case ACB_ADAPTER_TYPE_B: { 1264 /* 1265 ** push inbound doorbell tell iop, driver data write ok 1266 ** and wait reply on next hwinterrupt for next Qbuffer post 1267 */ 1268 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_WRITE_OK); 1269 } 1270 break; 1271 case ACB_ADAPTER_TYPE_C: { 1272 /* 1273 ** push inbound doorbell tell iop, driver data write ok 1274 ** and wait reply on next hwinterrupt for next Qbuffer post 1275 */ 1276 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK); 1277 } 1278 break; 1279 case ACB_ADAPTER_TYPE_D: { 1280 /* 1281 ** push inbound doorbell tell iop, driver data write ok 1282 ** and wait reply on next hwinterrupt for next Qbuffer post 1283 */ 1284 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY); 1285 } 1286 break; 1287 } 1288 } 1289 /* 1290 ************************************************************************ 1291 ************************************************************************ 1292 */ 1293 static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb) 1294 { 1295 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1296 CHIP_REG_WRITE32(HBA_MessageUnit, 1297 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1298 if(!arcmsr_hba_wait_msgint_ready(acb)) { 1299 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n" 1300 , acb->pci_unit); 1301 } 1302 } 1303 /* 1304 ************************************************************************ 1305 ************************************************************************ 1306 */ 1307 static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb) 1308 { 1309 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1310 CHIP_REG_WRITE32(HBB_DOORBELL, 1311 0, drv2iop_doorbell, ARCMSR_MESSAGE_STOP_BGRB); 1312 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 1313 printf( "arcmsr%d: wait 'stop adapter background rebulid' timeout \n" 1314 , acb->pci_unit); 1315 } 1316 } 1317 /* 1318 ************************************************************************ 1319 ************************************************************************ 1320 */ 1321 static void arcmsr_stop_hbc_bgrb(struct AdapterControlBlock *acb) 1322 { 1323 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1324 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1325 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 1326 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 1327 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1328 } 1329 } 1330 /* 1331 ************************************************************************ 1332 ************************************************************************ 1333 */ 1334 static void arcmsr_stop_hbd_bgrb(struct AdapterControlBlock *acb) 1335 { 1336 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1337 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1338 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 1339 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1340 } 1341 } 1342 /* 1343 ************************************************************************ 1344 ************************************************************************ 1345 */ 1346 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb) 1347 { 1348 switch (acb->adapter_type) { 1349 case ACB_ADAPTER_TYPE_A: { 1350 arcmsr_stop_hba_bgrb(acb); 1351 } 1352 break; 1353 case ACB_ADAPTER_TYPE_B: { 1354 arcmsr_stop_hbb_bgrb(acb); 1355 } 1356 break; 1357 case ACB_ADAPTER_TYPE_C: { 1358 arcmsr_stop_hbc_bgrb(acb); 1359 } 1360 break; 1361 case ACB_ADAPTER_TYPE_D: { 1362 arcmsr_stop_hbd_bgrb(acb); 1363 } 1364 break; 1365 } 1366 } 1367 /* 1368 ************************************************************************ 1369 ************************************************************************ 1370 */ 1371 static void arcmsr_poll(struct cam_sim *psim) 1372 { 1373 struct AdapterControlBlock *acb; 1374 int mutex; 1375 1376 acb = (struct AdapterControlBlock *)cam_sim_softc(psim); 1377 mutex = mtx_owned(&acb->isr_lock); 1378 if( mutex == 0 ) 1379 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 1380 arcmsr_interrupt(acb); 1381 if( mutex == 0 ) 1382 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 1383 } 1384 /* 1385 ************************************************************************** 1386 ************************************************************************** 1387 */ 1388 static u_int32_t arcmsr_Read_iop_rqbuffer_data_D(struct AdapterControlBlock *acb, 1389 struct QBUFFER *prbuffer) { 1390 1391 u_int8_t *pQbuffer; 1392 u_int8_t *buf1 = 0; 1393 u_int32_t *iop_data, *buf2 = 0; 1394 u_int32_t iop_len, data_len; 1395 1396 iop_data = (u_int32_t *)prbuffer->data; 1397 iop_len = (u_int32_t)prbuffer->data_len; 1398 if ( iop_len > 0 ) 1399 { 1400 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO); 1401 buf2 = (u_int32_t *)buf1; 1402 if( buf1 == NULL) 1403 return (0); 1404 data_len = iop_len; 1405 while(data_len >= 4) 1406 { 1407 *buf2++ = *iop_data++; 1408 data_len -= 4; 1409 } 1410 if(data_len) 1411 *buf2 = *iop_data; 1412 buf2 = (u_int32_t *)buf1; 1413 } 1414 while (iop_len > 0) { 1415 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex]; 1416 *pQbuffer = *buf1; 1417 acb->rqbuf_lastindex++; 1418 /* if last, index number set it to 0 */ 1419 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 1420 buf1++; 1421 iop_len--; 1422 } 1423 if(buf2) 1424 free( (u_int8_t *)buf2, M_DEVBUF); 1425 /* let IOP know data has been read */ 1426 arcmsr_iop_message_read(acb); 1427 return (1); 1428 } 1429 /* 1430 ************************************************************************** 1431 ************************************************************************** 1432 */ 1433 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, 1434 struct QBUFFER *prbuffer) { 1435 1436 u_int8_t *pQbuffer; 1437 u_int8_t *iop_data; 1438 u_int32_t iop_len; 1439 1440 if(acb->adapter_type == ACB_ADAPTER_TYPE_D) { 1441 return(arcmsr_Read_iop_rqbuffer_data_D(acb, prbuffer)); 1442 } 1443 iop_data = (u_int8_t *)prbuffer->data; 1444 iop_len = (u_int32_t)prbuffer->data_len; 1445 while (iop_len > 0) { 1446 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex]; 1447 *pQbuffer = *iop_data; 1448 acb->rqbuf_lastindex++; 1449 /* if last, index number set it to 0 */ 1450 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 1451 iop_data++; 1452 iop_len--; 1453 } 1454 /* let IOP know data has been read */ 1455 arcmsr_iop_message_read(acb); 1456 return (1); 1457 } 1458 /* 1459 ************************************************************************** 1460 ************************************************************************** 1461 */ 1462 static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb) 1463 { 1464 struct QBUFFER *prbuffer; 1465 int my_empty_len; 1466 1467 /*check this iop data if overflow my rqbuffer*/ 1468 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 1469 prbuffer = arcmsr_get_iop_rqbuffer(acb); 1470 my_empty_len = (acb->rqbuf_lastindex - acb->rqbuf_firstindex - 1) & 1471 (ARCMSR_MAX_QBUFFER-1); 1472 if(my_empty_len >= prbuffer->data_len) { 1473 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 1474 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 1475 } else { 1476 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 1477 } 1478 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 1479 } 1480 /* 1481 ********************************************************************** 1482 ********************************************************************** 1483 */ 1484 static void arcmsr_Write_data_2iop_wqbuffer_D(struct AdapterControlBlock *acb) 1485 { 1486 u_int8_t *pQbuffer; 1487 struct QBUFFER *pwbuffer; 1488 u_int8_t *buf1 = 0; 1489 u_int32_t *iop_data, *buf2 = 0; 1490 u_int32_t allxfer_len = 0, data_len; 1491 1492 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) { 1493 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO); 1494 buf2 = (u_int32_t *)buf1; 1495 if( buf1 == NULL) 1496 return; 1497 1498 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ); 1499 pwbuffer = arcmsr_get_iop_wqbuffer(acb); 1500 iop_data = (u_int32_t *)pwbuffer->data; 1501 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex) 1502 && (allxfer_len < 124)) { 1503 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex]; 1504 *buf1 = *pQbuffer; 1505 acb->wqbuf_firstindex++; 1506 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 1507 buf1++; 1508 allxfer_len++; 1509 } 1510 pwbuffer->data_len = allxfer_len; 1511 data_len = allxfer_len; 1512 buf1 = (u_int8_t *)buf2; 1513 while(data_len >= 4) 1514 { 1515 *iop_data++ = *buf2++; 1516 data_len -= 4; 1517 } 1518 if(data_len) 1519 *iop_data = *buf2; 1520 free( buf1, M_DEVBUF); 1521 arcmsr_iop_message_wrote(acb); 1522 } 1523 } 1524 /* 1525 ********************************************************************** 1526 ********************************************************************** 1527 */ 1528 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb) 1529 { 1530 u_int8_t *pQbuffer; 1531 struct QBUFFER *pwbuffer; 1532 u_int8_t *iop_data; 1533 int32_t allxfer_len=0; 1534 1535 if(acb->adapter_type == ACB_ADAPTER_TYPE_D) { 1536 arcmsr_Write_data_2iop_wqbuffer_D(acb); 1537 return; 1538 } 1539 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) { 1540 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ); 1541 pwbuffer = arcmsr_get_iop_wqbuffer(acb); 1542 iop_data = (u_int8_t *)pwbuffer->data; 1543 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex) 1544 && (allxfer_len < 124)) { 1545 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex]; 1546 *iop_data = *pQbuffer; 1547 acb->wqbuf_firstindex++; 1548 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 1549 iop_data++; 1550 allxfer_len++; 1551 } 1552 pwbuffer->data_len = allxfer_len; 1553 arcmsr_iop_message_wrote(acb); 1554 } 1555 } 1556 /* 1557 ************************************************************************** 1558 ************************************************************************** 1559 */ 1560 static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb) 1561 { 1562 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 1563 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READ; 1564 /* 1565 ***************************************************************** 1566 ** check if there are any mail packages from user space program 1567 ** in my post bag, now is the time to send them into Areca's firmware 1568 ***************************************************************** 1569 */ 1570 if(acb->wqbuf_firstindex != acb->wqbuf_lastindex) { 1571 arcmsr_Write_data_2iop_wqbuffer(acb); 1572 } 1573 if(acb->wqbuf_firstindex == acb->wqbuf_lastindex) { 1574 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED; 1575 } 1576 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 1577 } 1578 /* 1579 ************************************************************************** 1580 ************************************************************************** 1581 */ 1582 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb) 1583 { 1584 /* 1585 if (ccb->ccb_h.status != CAM_REQ_CMP) 1586 printf("arcmsr_rescanLun_cb: Rescan Target=%x, lun=%x," 1587 "failure status=%x\n", ccb->ccb_h.target_id, 1588 ccb->ccb_h.target_lun, ccb->ccb_h.status); 1589 else 1590 printf("arcmsr_rescanLun_cb: Rescan lun successfully!\n"); 1591 */ 1592 xpt_free_path(ccb->ccb_h.path); 1593 xpt_free_ccb(ccb); 1594 } 1595 1596 static void arcmsr_rescan_lun(struct AdapterControlBlock *acb, int target, int lun) 1597 { 1598 struct cam_path *path; 1599 union ccb *ccb; 1600 1601 if ((ccb = (union ccb *)xpt_alloc_ccb_nowait()) == NULL) 1602 return; 1603 if (xpt_create_path(&path, NULL, cam_sim_path(acb->psim), target, lun) != CAM_REQ_CMP) 1604 { 1605 xpt_free_ccb(ccb); 1606 return; 1607 } 1608 /* printf("arcmsr_rescan_lun: Rescan Target=%x, Lun=%x\n", target, lun); */ 1609 bzero(ccb, sizeof(union ccb)); 1610 xpt_setup_ccb(&ccb->ccb_h, path, 5); 1611 ccb->ccb_h.func_code = XPT_SCAN_LUN; 1612 ccb->ccb_h.cbfcnp = arcmsr_rescanLun_cb; 1613 ccb->crcn.flags = CAM_FLAG_NONE; 1614 xpt_action(ccb); 1615 } 1616 1617 1618 static void arcmsr_abort_dr_ccbs(struct AdapterControlBlock *acb, int target, int lun) 1619 { 1620 struct CommandControlBlock *srb; 1621 u_int32_t intmask_org; 1622 int i; 1623 1624 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 1625 /* disable all outbound interrupts */ 1626 intmask_org = arcmsr_disable_allintr(acb); 1627 for (i = 0; i < ARCMSR_MAX_FREESRB_NUM; i++) 1628 { 1629 srb = acb->psrb_pool[i]; 1630 if (srb->srb_state == ARCMSR_SRB_START) 1631 { 1632 if((target == srb->pccb->ccb_h.target_id) && (lun == srb->pccb->ccb_h.target_lun)) 1633 { 1634 srb->srb_state = ARCMSR_SRB_ABORTED; 1635 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 1636 arcmsr_srb_complete(srb, 1); 1637 printf("arcmsr%d: abort scsi id %d lun %d srb=%p \n", acb->pci_unit, target, lun, srb); 1638 } 1639 } 1640 } 1641 /* enable outbound Post Queue, outbound doorbell Interrupt */ 1642 arcmsr_enable_allintr(acb, intmask_org); 1643 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 1644 } 1645 /* 1646 ************************************************************************** 1647 ************************************************************************** 1648 */ 1649 static void arcmsr_dr_handle(struct AdapterControlBlock *acb) { 1650 u_int32_t devicemap; 1651 u_int32_t target, lun; 1652 u_int32_t deviceMapCurrent[4]={0}; 1653 u_int8_t *pDevMap; 1654 1655 switch (acb->adapter_type) { 1656 case ACB_ADAPTER_TYPE_A: 1657 devicemap = offsetof(struct HBA_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1658 for (target = 0; target < 4; target++) 1659 { 1660 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1661 devicemap += 4; 1662 } 1663 break; 1664 1665 case ACB_ADAPTER_TYPE_B: 1666 devicemap = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1667 for (target = 0; target < 4; target++) 1668 { 1669 deviceMapCurrent[target]=bus_space_read_4(acb->btag[1], acb->bhandle[1], devicemap); 1670 devicemap += 4; 1671 } 1672 break; 1673 1674 case ACB_ADAPTER_TYPE_C: 1675 devicemap = offsetof(struct HBC_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1676 for (target = 0; target < 4; target++) 1677 { 1678 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1679 devicemap += 4; 1680 } 1681 break; 1682 case ACB_ADAPTER_TYPE_D: 1683 devicemap = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1684 for (target = 0; target < 4; target++) 1685 { 1686 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1687 devicemap += 4; 1688 } 1689 break; 1690 } 1691 1692 if(acb->acb_flags & ACB_F_BUS_HANG_ON) 1693 { 1694 acb->acb_flags &= ~ACB_F_BUS_HANG_ON; 1695 } 1696 /* 1697 ** adapter posted CONFIG message 1698 ** copy the new map, note if there are differences with the current map 1699 */ 1700 pDevMap = (u_int8_t *)&deviceMapCurrent[0]; 1701 for (target = 0; target < ARCMSR_MAX_TARGETID - 1; target++) 1702 { 1703 if (*pDevMap != acb->device_map[target]) 1704 { 1705 u_int8_t difference, bit_check; 1706 1707 difference = *pDevMap ^ acb->device_map[target]; 1708 for(lun=0; lun < ARCMSR_MAX_TARGETLUN; lun++) 1709 { 1710 bit_check = (1 << lun); /*check bit from 0....31*/ 1711 if(difference & bit_check) 1712 { 1713 if(acb->device_map[target] & bit_check) 1714 {/* unit departed */ 1715 printf("arcmsr_dr_handle: Target=%x, lun=%x, GONE!!!\n",target,lun); 1716 arcmsr_abort_dr_ccbs(acb, target, lun); 1717 arcmsr_rescan_lun(acb, target, lun); 1718 acb->devstate[target][lun] = ARECA_RAID_GONE; 1719 } 1720 else 1721 {/* unit arrived */ 1722 printf("arcmsr_dr_handle: Target=%x, lun=%x, Plug-IN!!!\n",target,lun); 1723 arcmsr_rescan_lun(acb, target, lun); 1724 acb->devstate[target][lun] = ARECA_RAID_GOOD; 1725 } 1726 } 1727 } 1728 /* printf("arcmsr_dr_handle: acb->device_map[%x]=0x%x, deviceMapCurrent[%x]=%x\n",target,acb->device_map[target],target,*pDevMap); */ 1729 acb->device_map[target] = *pDevMap; 1730 } 1731 pDevMap++; 1732 } 1733 } 1734 /* 1735 ************************************************************************** 1736 ************************************************************************** 1737 */ 1738 static void arcmsr_hba_message_isr(struct AdapterControlBlock *acb) { 1739 u_int32_t outbound_message; 1740 1741 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT); 1742 outbound_message = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[0]); 1743 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1744 arcmsr_dr_handle( acb ); 1745 } 1746 /* 1747 ************************************************************************** 1748 ************************************************************************** 1749 */ 1750 static void arcmsr_hbb_message_isr(struct AdapterControlBlock *acb) { 1751 u_int32_t outbound_message; 1752 1753 /* clear interrupts */ 1754 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN); 1755 outbound_message = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0]); 1756 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1757 arcmsr_dr_handle( acb ); 1758 } 1759 /* 1760 ************************************************************************** 1761 ************************************************************************** 1762 */ 1763 static void arcmsr_hbc_message_isr(struct AdapterControlBlock *acb) { 1764 u_int32_t outbound_message; 1765 1766 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR); 1767 outbound_message = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[0]); 1768 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1769 arcmsr_dr_handle( acb ); 1770 } 1771 /* 1772 ************************************************************************** 1773 ************************************************************************** 1774 */ 1775 static void arcmsr_hbd_message_isr(struct AdapterControlBlock *acb) { 1776 u_int32_t outbound_message; 1777 1778 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR); 1779 outbound_message = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[0]); 1780 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1781 arcmsr_dr_handle( acb ); 1782 } 1783 /* 1784 ************************************************************************** 1785 ************************************************************************** 1786 */ 1787 static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb) 1788 { 1789 u_int32_t outbound_doorbell; 1790 1791 /* 1792 ******************************************************************* 1793 ** Maybe here we need to check wrqbuffer_lock is lock or not 1794 ** DOORBELL: din! don! 1795 ** check if there are any mail need to pack from firmware 1796 ******************************************************************* 1797 */ 1798 outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit, 1799 0, outbound_doorbell); 1800 CHIP_REG_WRITE32(HBA_MessageUnit, 1801 0, outbound_doorbell, outbound_doorbell); /* clear doorbell interrupt */ 1802 if(outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) { 1803 arcmsr_iop2drv_data_wrote_handle(acb); 1804 } 1805 if(outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) { 1806 arcmsr_iop2drv_data_read_handle(acb); 1807 } 1808 } 1809 /* 1810 ************************************************************************** 1811 ************************************************************************** 1812 */ 1813 static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *acb) 1814 { 1815 u_int32_t outbound_doorbell; 1816 1817 /* 1818 ******************************************************************* 1819 ** Maybe here we need to check wrqbuffer_lock is lock or not 1820 ** DOORBELL: din! don! 1821 ** check if there are any mail need to pack from firmware 1822 ******************************************************************* 1823 */ 1824 outbound_doorbell = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell); 1825 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell); /* clear doorbell interrupt */ 1826 if(outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) { 1827 arcmsr_iop2drv_data_wrote_handle(acb); 1828 } 1829 if(outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) { 1830 arcmsr_iop2drv_data_read_handle(acb); 1831 } 1832 if(outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 1833 arcmsr_hbc_message_isr(acb); /* messenger of "driver to iop commands" */ 1834 } 1835 } 1836 /* 1837 ************************************************************************** 1838 ************************************************************************** 1839 */ 1840 static void arcmsr_hbd_doorbell_isr(struct AdapterControlBlock *acb) 1841 { 1842 u_int32_t outbound_Doorbell; 1843 1844 /* 1845 ******************************************************************* 1846 ** Maybe here we need to check wrqbuffer_lock is lock or not 1847 ** DOORBELL: din! don! 1848 ** check if there are any mail need to pack from firmware 1849 ******************************************************************* 1850 */ 1851 outbound_Doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE; 1852 if(outbound_Doorbell) 1853 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_Doorbell); /* clear doorbell interrupt */ 1854 while( outbound_Doorbell & ARCMSR_HBDMU_F0_DOORBELL_CAUSE ) { 1855 if(outbound_Doorbell & ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK) { 1856 arcmsr_iop2drv_data_wrote_handle(acb); 1857 } 1858 if(outbound_Doorbell & ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK) { 1859 arcmsr_iop2drv_data_read_handle(acb); 1860 } 1861 if(outbound_Doorbell & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) { 1862 arcmsr_hbd_message_isr(acb); /* messenger of "driver to iop commands" */ 1863 } 1864 outbound_Doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE; 1865 if(outbound_Doorbell) 1866 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_Doorbell); /* clear doorbell interrupt */ 1867 } 1868 } 1869 /* 1870 ************************************************************************** 1871 ************************************************************************** 1872 */ 1873 static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb) 1874 { 1875 u_int32_t flag_srb; 1876 u_int16_t error; 1877 1878 /* 1879 ***************************************************************************** 1880 ** areca cdb command done 1881 ***************************************************************************** 1882 */ 1883 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 1884 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1885 while((flag_srb = CHIP_REG_READ32(HBA_MessageUnit, 1886 0, outbound_queueport)) != 0xFFFFFFFF) { 1887 /* check if command done with no error*/ 1888 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0) ? TRUE : FALSE; 1889 arcmsr_drain_donequeue(acb, flag_srb, error); 1890 } /*drain reply FIFO*/ 1891 } 1892 /* 1893 ************************************************************************** 1894 ************************************************************************** 1895 */ 1896 static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb) 1897 { 1898 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1899 u_int32_t flag_srb; 1900 int index; 1901 u_int16_t error; 1902 1903 /* 1904 ***************************************************************************** 1905 ** areca cdb command done 1906 ***************************************************************************** 1907 */ 1908 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 1909 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1910 index = phbbmu->doneq_index; 1911 while((flag_srb = phbbmu->done_qbuffer[index]) != 0) { 1912 phbbmu->done_qbuffer[index] = 0; 1913 index++; 1914 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 1915 phbbmu->doneq_index = index; 1916 /* check if command done with no error*/ 1917 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 1918 arcmsr_drain_donequeue(acb, flag_srb, error); 1919 } /*drain reply FIFO*/ 1920 } 1921 /* 1922 ************************************************************************** 1923 ************************************************************************** 1924 */ 1925 static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb) 1926 { 1927 u_int32_t flag_srb,throttling = 0; 1928 u_int16_t error; 1929 1930 /* 1931 ***************************************************************************** 1932 ** areca cdb command done 1933 ***************************************************************************** 1934 */ 1935 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1936 1937 while(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) { 1938 1939 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 1940 /* check if command done with no error*/ 1941 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE; 1942 arcmsr_drain_donequeue(acb, flag_srb, error); 1943 throttling++; 1944 if(throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) { 1945 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING); 1946 throttling = 0; 1947 } 1948 } /*drain reply FIFO*/ 1949 } 1950 /* 1951 ********************************************************************** 1952 ** 1953 ********************************************************************** 1954 */ 1955 static uint16_t arcmsr_get_doneq_index(struct HBD_MessageUnit0 *phbdmu) 1956 { 1957 uint16_t doneq_index, index_stripped; 1958 1959 doneq_index = phbdmu->doneq_index; 1960 if (doneq_index & 0x4000) { 1961 index_stripped = doneq_index & 0xFF; 1962 index_stripped += 1; 1963 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1964 phbdmu->doneq_index = index_stripped ? 1965 (index_stripped | 0x4000) : index_stripped; 1966 } else { 1967 index_stripped = doneq_index; 1968 index_stripped += 1; 1969 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1970 phbdmu->doneq_index = index_stripped ? 1971 index_stripped : (index_stripped | 0x4000); 1972 } 1973 return (phbdmu->doneq_index); 1974 } 1975 /* 1976 ************************************************************************** 1977 ************************************************************************** 1978 */ 1979 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb) 1980 { 1981 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1982 u_int32_t outbound_write_pointer; 1983 u_int32_t addressLow; 1984 uint16_t doneq_index; 1985 u_int16_t error; 1986 /* 1987 ***************************************************************************** 1988 ** areca cdb command done 1989 ***************************************************************************** 1990 */ 1991 if((CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause) & 1992 ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT) == 0) 1993 return; 1994 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 1995 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1996 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 1997 doneq_index = phbdmu->doneq_index; 1998 while ((doneq_index & 0xFF) != (outbound_write_pointer & 0xFF)) { 1999 doneq_index = arcmsr_get_doneq_index(phbdmu); 2000 addressLow = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow; 2001 error = (addressLow & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 2002 arcmsr_drain_donequeue(acb, addressLow, error); /*Check if command done with no error */ 2003 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index); 2004 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 2005 } 2006 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_interrupt_cause, ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR); 2007 CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause); /*Dummy ioread32 to force pci flush */ 2008 } 2009 /* 2010 ********************************************************************** 2011 ********************************************************************** 2012 */ 2013 static void arcmsr_handle_hba_isr( struct AdapterControlBlock *acb) 2014 { 2015 u_int32_t outbound_intStatus; 2016 /* 2017 ********************************************* 2018 ** check outbound intstatus 2019 ********************************************* 2020 */ 2021 outbound_intStatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 2022 if(!outbound_intStatus) { 2023 /*it must be share irq*/ 2024 return; 2025 } 2026 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intStatus); /*clear interrupt*/ 2027 /* MU doorbell interrupts*/ 2028 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) { 2029 arcmsr_hba_doorbell_isr(acb); 2030 } 2031 /* MU post queue interrupts*/ 2032 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) { 2033 arcmsr_hba_postqueue_isr(acb); 2034 } 2035 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { 2036 arcmsr_hba_message_isr(acb); 2037 } 2038 } 2039 /* 2040 ********************************************************************** 2041 ********************************************************************** 2042 */ 2043 static void arcmsr_handle_hbb_isr( struct AdapterControlBlock *acb) 2044 { 2045 u_int32_t outbound_doorbell; 2046 /* 2047 ********************************************* 2048 ** check outbound intstatus 2049 ********************************************* 2050 */ 2051 outbound_doorbell = CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & acb->outbound_int_enable; 2052 if(!outbound_doorbell) { 2053 /*it must be share irq*/ 2054 return; 2055 } 2056 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ~outbound_doorbell); /* clear doorbell interrupt */ 2057 CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell); 2058 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 2059 /* MU ioctl transfer doorbell interrupts*/ 2060 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) { 2061 arcmsr_iop2drv_data_wrote_handle(acb); 2062 } 2063 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) { 2064 arcmsr_iop2drv_data_read_handle(acb); 2065 } 2066 /* MU post queue interrupts*/ 2067 if(outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) { 2068 arcmsr_hbb_postqueue_isr(acb); 2069 } 2070 if(outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) { 2071 arcmsr_hbb_message_isr(acb); 2072 } 2073 } 2074 /* 2075 ********************************************************************** 2076 ********************************************************************** 2077 */ 2078 static void arcmsr_handle_hbc_isr( struct AdapterControlBlock *acb) 2079 { 2080 u_int32_t host_interrupt_status; 2081 /* 2082 ********************************************* 2083 ** check outbound intstatus 2084 ********************************************* 2085 */ 2086 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status); 2087 if(!host_interrupt_status) { 2088 /*it must be share irq*/ 2089 return; 2090 } 2091 /* MU doorbell interrupts*/ 2092 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) { 2093 arcmsr_hbc_doorbell_isr(acb); 2094 } 2095 /* MU post queue interrupts*/ 2096 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) { 2097 arcmsr_hbc_postqueue_isr(acb); 2098 } 2099 } 2100 /* 2101 ********************************************************************** 2102 ********************************************************************** 2103 */ 2104 static void arcmsr_handle_hbd_isr( struct AdapterControlBlock *acb) 2105 { 2106 u_int32_t host_interrupt_status; 2107 u_int32_t intmask_org; 2108 /* 2109 ********************************************* 2110 ** check outbound intstatus 2111 ********************************************* 2112 */ 2113 host_interrupt_status = CHIP_REG_READ32(HBD_MessageUnit, 0, host_int_status) & acb->outbound_int_enable; 2114 if(!(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_INT)) { 2115 /*it must be share irq*/ 2116 return; 2117 } 2118 /* disable outbound interrupt */ 2119 intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable) ; /* disable outbound message0 int */ 2120 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE); 2121 /* MU doorbell interrupts*/ 2122 if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT) { 2123 arcmsr_hbd_doorbell_isr(acb); 2124 } 2125 /* MU post queue interrupts*/ 2126 if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT) { 2127 arcmsr_hbd_postqueue_isr(acb); 2128 } 2129 /* enable all outbound interrupt */ 2130 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | ARCMSR_HBDMU_ALL_INT_ENABLE); 2131 // CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); 2132 } 2133 /* 2134 ****************************************************************************** 2135 ****************************************************************************** 2136 */ 2137 static void arcmsr_interrupt(struct AdapterControlBlock *acb) 2138 { 2139 switch (acb->adapter_type) { 2140 case ACB_ADAPTER_TYPE_A: 2141 arcmsr_handle_hba_isr(acb); 2142 break; 2143 case ACB_ADAPTER_TYPE_B: 2144 arcmsr_handle_hbb_isr(acb); 2145 break; 2146 case ACB_ADAPTER_TYPE_C: 2147 arcmsr_handle_hbc_isr(acb); 2148 break; 2149 case ACB_ADAPTER_TYPE_D: 2150 arcmsr_handle_hbd_isr(acb); 2151 break; 2152 default: 2153 printf("arcmsr%d: interrupt service," 2154 " unknown adapter type =%d\n", acb->pci_unit, acb->adapter_type); 2155 break; 2156 } 2157 } 2158 /* 2159 ********************************************************************** 2160 ********************************************************************** 2161 */ 2162 static void arcmsr_intr_handler(void *arg) 2163 { 2164 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg; 2165 2166 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 2167 arcmsr_interrupt(acb); 2168 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 2169 } 2170 /* 2171 ****************************************************************************** 2172 ****************************************************************************** 2173 */ 2174 static void arcmsr_polling_devmap(void *arg) 2175 { 2176 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg; 2177 switch (acb->adapter_type) { 2178 case ACB_ADAPTER_TYPE_A: 2179 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2180 break; 2181 2182 case ACB_ADAPTER_TYPE_B: 2183 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG); 2184 break; 2185 2186 case ACB_ADAPTER_TYPE_C: 2187 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2188 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 2189 break; 2190 2191 case ACB_ADAPTER_TYPE_D: 2192 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2193 break; 2194 } 2195 2196 if((acb->acb_flags & ACB_F_SCSISTOPADAPTER) == 0) 2197 { 2198 callout_reset(&acb->devmap_callout, 5 * hz, arcmsr_polling_devmap, acb); /* polling per 5 seconds */ 2199 } 2200 } 2201 2202 /* 2203 ******************************************************************************* 2204 ** 2205 ******************************************************************************* 2206 */ 2207 static void arcmsr_iop_parking(struct AdapterControlBlock *acb) 2208 { 2209 u_int32_t intmask_org; 2210 2211 if(acb != NULL) { 2212 /* stop adapter background rebuild */ 2213 if(acb->acb_flags & ACB_F_MSG_START_BGRB) { 2214 intmask_org = arcmsr_disable_allintr(acb); 2215 arcmsr_stop_adapter_bgrb(acb); 2216 arcmsr_flush_adapter_cache(acb); 2217 arcmsr_enable_allintr(acb, intmask_org); 2218 } 2219 } 2220 } 2221 /* 2222 *********************************************************************** 2223 ** 2224 ************************************************************************ 2225 */ 2226 u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg) 2227 { 2228 struct CMD_MESSAGE_FIELD *pcmdmessagefld; 2229 u_int32_t retvalue = EINVAL; 2230 2231 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) arg; 2232 if(memcmp(pcmdmessagefld->cmdmessage.Signature, "ARCMSR", 6)!=0) { 2233 return retvalue; 2234 } 2235 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2236 switch(ioctl_cmd) { 2237 case ARCMSR_MESSAGE_READ_RQBUFFER: { 2238 u_int8_t *pQbuffer; 2239 u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer; 2240 u_int32_t allxfer_len=0; 2241 2242 while((acb->rqbuf_firstindex != acb->rqbuf_lastindex) 2243 && (allxfer_len < 1031)) { 2244 /*copy READ QBUFFER to srb*/ 2245 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex]; 2246 *ptmpQbuffer = *pQbuffer; 2247 acb->rqbuf_firstindex++; 2248 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 2249 /*if last index number set it to 0 */ 2250 ptmpQbuffer++; 2251 allxfer_len++; 2252 } 2253 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2254 struct QBUFFER *prbuffer; 2255 2256 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2257 prbuffer = arcmsr_get_iop_rqbuffer(acb); 2258 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 2259 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 2260 } 2261 pcmdmessagefld->cmdmessage.Length = allxfer_len; 2262 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2263 retvalue = ARCMSR_MESSAGE_SUCCESS; 2264 } 2265 break; 2266 case ARCMSR_MESSAGE_WRITE_WQBUFFER: { 2267 u_int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex; 2268 u_int8_t *pQbuffer; 2269 u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer; 2270 2271 user_len = pcmdmessagefld->cmdmessage.Length; 2272 /*check if data xfer length of this request will overflow my array qbuffer */ 2273 wqbuf_lastindex = acb->wqbuf_lastindex; 2274 wqbuf_firstindex = acb->wqbuf_firstindex; 2275 if(wqbuf_lastindex != wqbuf_firstindex) { 2276 arcmsr_Write_data_2iop_wqbuffer(acb); 2277 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2278 } else { 2279 my_empty_len = (wqbuf_firstindex - wqbuf_lastindex - 1) & 2280 (ARCMSR_MAX_QBUFFER - 1); 2281 if(my_empty_len >= user_len) { 2282 while(user_len > 0) { 2283 /*copy srb data to wqbuffer*/ 2284 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex]; 2285 *pQbuffer = *ptmpuserbuffer; 2286 acb->wqbuf_lastindex++; 2287 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 2288 /*if last index number set it to 0 */ 2289 ptmpuserbuffer++; 2290 user_len--; 2291 } 2292 /*post fist Qbuffer*/ 2293 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) { 2294 acb->acb_flags &= ~ACB_F_MESSAGE_WQBUFFER_CLEARED; 2295 arcmsr_Write_data_2iop_wqbuffer(acb); 2296 } 2297 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2298 } else { 2299 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2300 } 2301 } 2302 retvalue = ARCMSR_MESSAGE_SUCCESS; 2303 } 2304 break; 2305 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: { 2306 u_int8_t *pQbuffer = acb->rqbuffer; 2307 2308 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2309 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2310 arcmsr_iop_message_read(acb); 2311 /*signature, let IOP know data has been readed */ 2312 } 2313 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 2314 acb->rqbuf_firstindex = 0; 2315 acb->rqbuf_lastindex = 0; 2316 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2317 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2318 retvalue = ARCMSR_MESSAGE_SUCCESS; 2319 } 2320 break; 2321 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: 2322 { 2323 u_int8_t *pQbuffer = acb->wqbuffer; 2324 2325 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2326 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2327 arcmsr_iop_message_read(acb); 2328 /*signature, let IOP know data has been readed */ 2329 } 2330 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ); 2331 acb->wqbuf_firstindex = 0; 2332 acb->wqbuf_lastindex = 0; 2333 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2334 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2335 retvalue = ARCMSR_MESSAGE_SUCCESS; 2336 } 2337 break; 2338 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: { 2339 u_int8_t *pQbuffer; 2340 2341 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2342 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2343 arcmsr_iop_message_read(acb); 2344 /*signature, let IOP know data has been readed */ 2345 } 2346 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED 2347 |ACB_F_MESSAGE_RQBUFFER_CLEARED 2348 |ACB_F_MESSAGE_WQBUFFER_READ); 2349 acb->rqbuf_firstindex = 0; 2350 acb->rqbuf_lastindex = 0; 2351 acb->wqbuf_firstindex = 0; 2352 acb->wqbuf_lastindex = 0; 2353 pQbuffer = acb->rqbuffer; 2354 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 2355 pQbuffer = acb->wqbuffer; 2356 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 2357 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2358 retvalue = ARCMSR_MESSAGE_SUCCESS; 2359 } 2360 break; 2361 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: { 2362 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F; 2363 retvalue = ARCMSR_MESSAGE_SUCCESS; 2364 } 2365 break; 2366 case ARCMSR_MESSAGE_SAY_HELLO: { 2367 u_int8_t *hello_string = "Hello! I am ARCMSR"; 2368 u_int8_t *puserbuffer = (u_int8_t *)pcmdmessagefld->messagedatabuffer; 2369 2370 if(memcpy(puserbuffer, hello_string, (int16_t)strlen(hello_string))) { 2371 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2372 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2373 return ENOIOCTL; 2374 } 2375 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2376 retvalue = ARCMSR_MESSAGE_SUCCESS; 2377 } 2378 break; 2379 case ARCMSR_MESSAGE_SAY_GOODBYE: { 2380 arcmsr_iop_parking(acb); 2381 retvalue = ARCMSR_MESSAGE_SUCCESS; 2382 } 2383 break; 2384 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: { 2385 arcmsr_flush_adapter_cache(acb); 2386 retvalue = ARCMSR_MESSAGE_SUCCESS; 2387 } 2388 break; 2389 } 2390 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2391 return (retvalue); 2392 } 2393 /* 2394 ************************************************************************** 2395 ************************************************************************** 2396 */ 2397 static void arcmsr_free_srb(struct CommandControlBlock *srb) 2398 { 2399 struct AdapterControlBlock *acb; 2400 2401 acb = srb->acb; 2402 ARCMSR_LOCK_ACQUIRE(&acb->srb_lock); 2403 srb->srb_state = ARCMSR_SRB_DONE; 2404 srb->srb_flags = 0; 2405 acb->srbworkingQ[acb->workingsrb_doneindex] = srb; 2406 acb->workingsrb_doneindex++; 2407 acb->workingsrb_doneindex %= ARCMSR_MAX_FREESRB_NUM; 2408 ARCMSR_LOCK_RELEASE(&acb->srb_lock); 2409 } 2410 /* 2411 ************************************************************************** 2412 ************************************************************************** 2413 */ 2414 struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb) 2415 { 2416 struct CommandControlBlock *srb = NULL; 2417 u_int32_t workingsrb_startindex, workingsrb_doneindex; 2418 2419 ARCMSR_LOCK_ACQUIRE(&acb->srb_lock); 2420 workingsrb_doneindex = acb->workingsrb_doneindex; 2421 workingsrb_startindex = acb->workingsrb_startindex; 2422 srb = acb->srbworkingQ[workingsrb_startindex]; 2423 workingsrb_startindex++; 2424 workingsrb_startindex %= ARCMSR_MAX_FREESRB_NUM; 2425 if(workingsrb_doneindex != workingsrb_startindex) { 2426 acb->workingsrb_startindex = workingsrb_startindex; 2427 } else { 2428 srb = NULL; 2429 } 2430 ARCMSR_LOCK_RELEASE(&acb->srb_lock); 2431 return(srb); 2432 } 2433 /* 2434 ************************************************************************** 2435 ************************************************************************** 2436 */ 2437 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb) 2438 { 2439 struct CMD_MESSAGE_FIELD *pcmdmessagefld; 2440 int retvalue = 0, transfer_len = 0; 2441 char *buffer; 2442 u_int32_t controlcode = (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[5] << 24 | 2443 (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[6] << 16 | 2444 (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[7] << 8 | 2445 (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[8]; 2446 /* 4 bytes: Areca io control code */ 2447 if ((pccb->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_VADDR) { 2448 buffer = pccb->csio.data_ptr; 2449 transfer_len = pccb->csio.dxfer_len; 2450 } else { 2451 retvalue = ARCMSR_MESSAGE_FAIL; 2452 goto message_out; 2453 } 2454 if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) { 2455 retvalue = ARCMSR_MESSAGE_FAIL; 2456 goto message_out; 2457 } 2458 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) buffer; 2459 switch(controlcode) { 2460 case ARCMSR_MESSAGE_READ_RQBUFFER: { 2461 u_int8_t *pQbuffer; 2462 u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer; 2463 int32_t allxfer_len = 0; 2464 2465 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2466 while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex) 2467 && (allxfer_len < 1031)) { 2468 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex]; 2469 *ptmpQbuffer = *pQbuffer; 2470 acb->rqbuf_firstindex++; 2471 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 2472 ptmpQbuffer++; 2473 allxfer_len++; 2474 } 2475 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2476 struct QBUFFER *prbuffer; 2477 2478 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2479 prbuffer = arcmsr_get_iop_rqbuffer(acb); 2480 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 2481 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 2482 } 2483 pcmdmessagefld->cmdmessage.Length = allxfer_len; 2484 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2485 retvalue = ARCMSR_MESSAGE_SUCCESS; 2486 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2487 } 2488 break; 2489 case ARCMSR_MESSAGE_WRITE_WQBUFFER: { 2490 int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex; 2491 u_int8_t *pQbuffer; 2492 u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer; 2493 2494 user_len = pcmdmessagefld->cmdmessage.Length; 2495 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2496 wqbuf_lastindex = acb->wqbuf_lastindex; 2497 wqbuf_firstindex = acb->wqbuf_firstindex; 2498 if (wqbuf_lastindex != wqbuf_firstindex) { 2499 arcmsr_Write_data_2iop_wqbuffer(acb); 2500 /* has error report sensedata */ 2501 if(pccb->csio.sense_len) { 2502 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); 2503 /* Valid,ErrorCode */ 2504 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05; 2505 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */ 2506 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A; 2507 /* AdditionalSenseLength */ 2508 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20; 2509 /* AdditionalSenseCode */ 2510 } 2511 retvalue = ARCMSR_MESSAGE_FAIL; 2512 } else { 2513 my_empty_len = (wqbuf_firstindex-wqbuf_lastindex - 1) 2514 &(ARCMSR_MAX_QBUFFER - 1); 2515 if (my_empty_len >= user_len) { 2516 while (user_len > 0) { 2517 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex]; 2518 *pQbuffer = *ptmpuserbuffer; 2519 acb->wqbuf_lastindex++; 2520 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 2521 ptmpuserbuffer++; 2522 user_len--; 2523 } 2524 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) { 2525 acb->acb_flags &= 2526 ~ACB_F_MESSAGE_WQBUFFER_CLEARED; 2527 arcmsr_Write_data_2iop_wqbuffer(acb); 2528 } 2529 } else { 2530 /* has error report sensedata */ 2531 if(pccb->csio.sense_len) { 2532 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); 2533 /* Valid,ErrorCode */ 2534 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05; 2535 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */ 2536 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A; 2537 /* AdditionalSenseLength */ 2538 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20; 2539 /* AdditionalSenseCode */ 2540 } 2541 retvalue = ARCMSR_MESSAGE_FAIL; 2542 } 2543 } 2544 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2545 } 2546 break; 2547 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: { 2548 u_int8_t *pQbuffer = acb->rqbuffer; 2549 2550 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2551 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2552 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2553 arcmsr_iop_message_read(acb); 2554 } 2555 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 2556 acb->rqbuf_firstindex = 0; 2557 acb->rqbuf_lastindex = 0; 2558 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2559 pcmdmessagefld->cmdmessage.ReturnCode = 2560 ARCMSR_MESSAGE_RETURNCODE_OK; 2561 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2562 } 2563 break; 2564 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: { 2565 u_int8_t *pQbuffer = acb->wqbuffer; 2566 2567 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2568 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2569 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2570 arcmsr_iop_message_read(acb); 2571 } 2572 acb->acb_flags |= 2573 (ACB_F_MESSAGE_WQBUFFER_CLEARED | 2574 ACB_F_MESSAGE_WQBUFFER_READ); 2575 acb->wqbuf_firstindex = 0; 2576 acb->wqbuf_lastindex = 0; 2577 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2578 pcmdmessagefld->cmdmessage.ReturnCode = 2579 ARCMSR_MESSAGE_RETURNCODE_OK; 2580 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2581 } 2582 break; 2583 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: { 2584 u_int8_t *pQbuffer; 2585 2586 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2587 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2588 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2589 arcmsr_iop_message_read(acb); 2590 } 2591 acb->acb_flags |= 2592 (ACB_F_MESSAGE_WQBUFFER_CLEARED 2593 | ACB_F_MESSAGE_RQBUFFER_CLEARED 2594 | ACB_F_MESSAGE_WQBUFFER_READ); 2595 acb->rqbuf_firstindex = 0; 2596 acb->rqbuf_lastindex = 0; 2597 acb->wqbuf_firstindex = 0; 2598 acb->wqbuf_lastindex = 0; 2599 pQbuffer = acb->rqbuffer; 2600 memset(pQbuffer, 0, sizeof (struct QBUFFER)); 2601 pQbuffer = acb->wqbuffer; 2602 memset(pQbuffer, 0, sizeof (struct QBUFFER)); 2603 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2604 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2605 } 2606 break; 2607 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: { 2608 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F; 2609 } 2610 break; 2611 case ARCMSR_MESSAGE_SAY_HELLO: { 2612 int8_t *hello_string = "Hello! I am ARCMSR"; 2613 2614 memcpy(pcmdmessagefld->messagedatabuffer, hello_string 2615 , (int16_t)strlen(hello_string)); 2616 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2617 } 2618 break; 2619 case ARCMSR_MESSAGE_SAY_GOODBYE: 2620 arcmsr_iop_parking(acb); 2621 break; 2622 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: 2623 arcmsr_flush_adapter_cache(acb); 2624 break; 2625 default: 2626 retvalue = ARCMSR_MESSAGE_FAIL; 2627 } 2628 message_out: 2629 return (retvalue); 2630 } 2631 /* 2632 ********************************************************************* 2633 ********************************************************************* 2634 */ 2635 static void arcmsr_execute_srb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 2636 { 2637 struct CommandControlBlock *srb = (struct CommandControlBlock *)arg; 2638 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)srb->acb; 2639 union ccb *pccb; 2640 int target, lun; 2641 2642 pccb = srb->pccb; 2643 target = pccb->ccb_h.target_id; 2644 lun = pccb->ccb_h.target_lun; 2645 acb->pktRequestCount++; 2646 if(error != 0) { 2647 if(error != EFBIG) { 2648 printf("arcmsr%d: unexpected error %x" 2649 " returned from 'bus_dmamap_load' \n" 2650 , acb->pci_unit, error); 2651 } 2652 if((pccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_INPROG) { 2653 pccb->ccb_h.status |= CAM_REQ_TOO_BIG; 2654 } 2655 arcmsr_srb_complete(srb, 0); 2656 return; 2657 } 2658 if(nseg > ARCMSR_MAX_SG_ENTRIES) { 2659 pccb->ccb_h.status |= CAM_REQ_TOO_BIG; 2660 arcmsr_srb_complete(srb, 0); 2661 return; 2662 } 2663 if(acb->acb_flags & ACB_F_BUS_RESET) { 2664 printf("arcmsr%d: bus reset and return busy \n", acb->pci_unit); 2665 pccb->ccb_h.status |= CAM_SCSI_BUS_RESET; 2666 arcmsr_srb_complete(srb, 0); 2667 return; 2668 } 2669 if(acb->devstate[target][lun] == ARECA_RAID_GONE) { 2670 u_int8_t block_cmd, cmd; 2671 2672 cmd = pccb->csio.cdb_io.cdb_bytes[0]; 2673 block_cmd = cmd & 0x0f; 2674 if(block_cmd == 0x08 || block_cmd == 0x0a) { 2675 printf("arcmsr%d:block 'read/write' command " 2676 "with gone raid volume Cmd=0x%2x, TargetId=%d, Lun=%d \n" 2677 , acb->pci_unit, cmd, target, lun); 2678 pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 2679 arcmsr_srb_complete(srb, 0); 2680 return; 2681 } 2682 } 2683 if((pccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_INPROG) { 2684 if(nseg != 0) { 2685 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap); 2686 } 2687 arcmsr_srb_complete(srb, 0); 2688 return; 2689 } 2690 if(acb->srboutstandingcount >= acb->maxOutstanding) { 2691 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) == 0) 2692 { 2693 xpt_freeze_simq(acb->psim, 1); 2694 acb->acb_flags |= ACB_F_CAM_DEV_QFRZN; 2695 } 2696 pccb->ccb_h.status &= ~CAM_SIM_QUEUED; 2697 pccb->ccb_h.status |= CAM_REQUEUE_REQ; 2698 arcmsr_srb_complete(srb, 0); 2699 return; 2700 } 2701 pccb->ccb_h.status |= CAM_SIM_QUEUED; 2702 arcmsr_build_srb(srb, dm_segs, nseg); 2703 arcmsr_post_srb(acb, srb); 2704 if (pccb->ccb_h.timeout != CAM_TIME_INFINITY) 2705 { 2706 arcmsr_callout_init(&srb->ccb_callout); 2707 callout_reset(&srb->ccb_callout, ((pccb->ccb_h.timeout + (ARCMSR_TIMEOUT_DELAY * 1000)) * hz) / 1000, arcmsr_srb_timeout, srb); 2708 srb->srb_flags |= SRB_FLAG_TIMER_START; 2709 } 2710 } 2711 /* 2712 ***************************************************************************************** 2713 ***************************************************************************************** 2714 */ 2715 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb) 2716 { 2717 struct CommandControlBlock *srb; 2718 struct AdapterControlBlock *acb = (struct AdapterControlBlock *) abortccb->ccb_h.arcmsr_ccbacb_ptr; 2719 u_int32_t intmask_org; 2720 int i = 0; 2721 2722 acb->num_aborts++; 2723 /* 2724 *************************************************************************** 2725 ** It is the upper layer do abort command this lock just prior to calling us. 2726 ** First determine if we currently own this command. 2727 ** Start by searching the device queue. If not found 2728 ** at all, and the system wanted us to just abort the 2729 ** command return success. 2730 *************************************************************************** 2731 */ 2732 if(acb->srboutstandingcount != 0) { 2733 /* disable all outbound interrupt */ 2734 intmask_org = arcmsr_disable_allintr(acb); 2735 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 2736 srb = acb->psrb_pool[i]; 2737 if(srb->srb_state == ARCMSR_SRB_START) { 2738 if(srb->pccb == abortccb) { 2739 srb->srb_state = ARCMSR_SRB_ABORTED; 2740 printf("arcmsr%d:scsi id=%d lun=%d abort srb '%p'" 2741 "outstanding command \n" 2742 , acb->pci_unit, abortccb->ccb_h.target_id 2743 , abortccb->ccb_h.target_lun, srb); 2744 arcmsr_polling_srbdone(acb, srb); 2745 /* enable outbound Post Queue, outbound doorbell Interrupt */ 2746 arcmsr_enable_allintr(acb, intmask_org); 2747 return (TRUE); 2748 } 2749 } 2750 } 2751 /* enable outbound Post Queue, outbound doorbell Interrupt */ 2752 arcmsr_enable_allintr(acb, intmask_org); 2753 } 2754 return(FALSE); 2755 } 2756 /* 2757 **************************************************************************** 2758 **************************************************************************** 2759 */ 2760 static void arcmsr_bus_reset(struct AdapterControlBlock *acb) 2761 { 2762 int retry = 0; 2763 2764 acb->num_resets++; 2765 acb->acb_flags |= ACB_F_BUS_RESET; 2766 while(acb->srboutstandingcount != 0 && retry < 400) { 2767 arcmsr_interrupt(acb); 2768 UDELAY(25000); 2769 retry++; 2770 } 2771 arcmsr_iop_reset(acb); 2772 acb->acb_flags &= ~ACB_F_BUS_RESET; 2773 } 2774 /* 2775 ************************************************************************** 2776 ************************************************************************** 2777 */ 2778 static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb, 2779 union ccb *pccb) 2780 { 2781 if (pccb->ccb_h.target_lun) { 2782 pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 2783 xpt_done(pccb); 2784 return; 2785 } 2786 pccb->ccb_h.status |= CAM_REQ_CMP; 2787 switch (pccb->csio.cdb_io.cdb_bytes[0]) { 2788 case INQUIRY: { 2789 unsigned char inqdata[36]; 2790 char *buffer = pccb->csio.data_ptr; 2791 2792 inqdata[0] = T_PROCESSOR; /* Periph Qualifier & Periph Dev Type */ 2793 inqdata[1] = 0; /* rem media bit & Dev Type Modifier */ 2794 inqdata[2] = 0; /* ISO, ECMA, & ANSI versions */ 2795 inqdata[3] = 0; 2796 inqdata[4] = 31; /* length of additional data */ 2797 inqdata[5] = 0; 2798 inqdata[6] = 0; 2799 inqdata[7] = 0; 2800 strncpy(&inqdata[8], "Areca ", 8); /* Vendor Identification */ 2801 strncpy(&inqdata[16], "RAID controller ", 16); /* Product Identification */ 2802 strncpy(&inqdata[32], "R001", 4); /* Product Revision */ 2803 memcpy(buffer, inqdata, sizeof(inqdata)); 2804 xpt_done(pccb); 2805 } 2806 break; 2807 case WRITE_BUFFER: 2808 case READ_BUFFER: { 2809 if (arcmsr_iop_message_xfer(acb, pccb)) { 2810 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 2811 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 2812 } 2813 xpt_done(pccb); 2814 } 2815 break; 2816 default: 2817 xpt_done(pccb); 2818 } 2819 } 2820 /* 2821 ********************************************************************* 2822 ********************************************************************* 2823 */ 2824 static void arcmsr_action(struct cam_sim *psim, union ccb *pccb) 2825 { 2826 struct AdapterControlBlock *acb; 2827 2828 acb = (struct AdapterControlBlock *) cam_sim_softc(psim); 2829 if(acb == NULL) { 2830 pccb->ccb_h.status |= CAM_REQ_INVALID; 2831 xpt_done(pccb); 2832 return; 2833 } 2834 switch (pccb->ccb_h.func_code) { 2835 case XPT_SCSI_IO: { 2836 struct CommandControlBlock *srb; 2837 int target = pccb->ccb_h.target_id; 2838 int error; 2839 2840 if(target == 16) { 2841 /* virtual device for iop message transfer */ 2842 arcmsr_handle_virtual_command(acb, pccb); 2843 return; 2844 } 2845 if((srb = arcmsr_get_freesrb(acb)) == NULL) { 2846 pccb->ccb_h.status |= CAM_RESRC_UNAVAIL; 2847 xpt_done(pccb); 2848 return; 2849 } 2850 pccb->ccb_h.arcmsr_ccbsrb_ptr = srb; 2851 pccb->ccb_h.arcmsr_ccbacb_ptr = acb; 2852 srb->pccb = pccb; 2853 error = bus_dmamap_load_ccb(acb->dm_segs_dmat 2854 , srb->dm_segs_dmamap 2855 , pccb 2856 , arcmsr_execute_srb, srb, /*flags*/0); 2857 if(error == EINPROGRESS) { 2858 xpt_freeze_simq(acb->psim, 1); 2859 pccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2860 } 2861 break; 2862 } 2863 case XPT_TARGET_IO: { 2864 /* target mode not yet support vendor specific commands. */ 2865 pccb->ccb_h.status |= CAM_REQ_CMP; 2866 xpt_done(pccb); 2867 break; 2868 } 2869 case XPT_PATH_INQ: { 2870 struct ccb_pathinq *cpi = &pccb->cpi; 2871 2872 cpi->version_num = 1; 2873 cpi->hba_inquiry = PI_SDTR_ABLE | PI_TAG_ABLE; 2874 cpi->target_sprt = 0; 2875 cpi->hba_misc = 0; 2876 cpi->hba_eng_cnt = 0; 2877 cpi->max_target = ARCMSR_MAX_TARGETID; /* 0-16 */ 2878 cpi->max_lun = ARCMSR_MAX_TARGETLUN; /* 0-7 */ 2879 cpi->initiator_id = ARCMSR_SCSI_INITIATOR_ID; /* 255 */ 2880 cpi->bus_id = cam_sim_bus(psim); 2881 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2882 strncpy(cpi->hba_vid, "ARCMSR", HBA_IDLEN); 2883 strncpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN); 2884 cpi->unit_number = cam_sim_unit(psim); 2885 #ifdef CAM_NEW_TRAN_CODE 2886 if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G) 2887 cpi->base_transfer_speed = 600000; 2888 else 2889 cpi->base_transfer_speed = 300000; 2890 if((acb->vendor_device_id == PCIDevVenIDARC1880) || 2891 (acb->vendor_device_id == PCIDevVenIDARC1680) || 2892 (acb->vendor_device_id == PCIDevVenIDARC1214)) 2893 { 2894 cpi->transport = XPORT_SAS; 2895 cpi->transport_version = 0; 2896 cpi->protocol_version = SCSI_REV_SPC2; 2897 } 2898 else 2899 { 2900 cpi->transport = XPORT_SPI; 2901 cpi->transport_version = 2; 2902 cpi->protocol_version = SCSI_REV_2; 2903 } 2904 cpi->protocol = PROTO_SCSI; 2905 #endif 2906 cpi->ccb_h.status |= CAM_REQ_CMP; 2907 xpt_done(pccb); 2908 break; 2909 } 2910 case XPT_ABORT: { 2911 union ccb *pabort_ccb; 2912 2913 pabort_ccb = pccb->cab.abort_ccb; 2914 switch (pabort_ccb->ccb_h.func_code) { 2915 case XPT_ACCEPT_TARGET_IO: 2916 case XPT_IMMED_NOTIFY: 2917 case XPT_CONT_TARGET_IO: 2918 if(arcmsr_seek_cmd2abort(pabort_ccb)==TRUE) { 2919 pabort_ccb->ccb_h.status |= CAM_REQ_ABORTED; 2920 xpt_done(pabort_ccb); 2921 pccb->ccb_h.status |= CAM_REQ_CMP; 2922 } else { 2923 xpt_print_path(pabort_ccb->ccb_h.path); 2924 printf("Not found\n"); 2925 pccb->ccb_h.status |= CAM_PATH_INVALID; 2926 } 2927 break; 2928 case XPT_SCSI_IO: 2929 pccb->ccb_h.status |= CAM_UA_ABORT; 2930 break; 2931 default: 2932 pccb->ccb_h.status |= CAM_REQ_INVALID; 2933 break; 2934 } 2935 xpt_done(pccb); 2936 break; 2937 } 2938 case XPT_RESET_BUS: 2939 case XPT_RESET_DEV: { 2940 u_int32_t i; 2941 2942 arcmsr_bus_reset(acb); 2943 for (i=0; i < 500; i++) { 2944 DELAY(1000); 2945 } 2946 pccb->ccb_h.status |= CAM_REQ_CMP; 2947 xpt_done(pccb); 2948 break; 2949 } 2950 case XPT_TERM_IO: { 2951 pccb->ccb_h.status |= CAM_REQ_INVALID; 2952 xpt_done(pccb); 2953 break; 2954 } 2955 case XPT_GET_TRAN_SETTINGS: { 2956 struct ccb_trans_settings *cts; 2957 2958 if(pccb->ccb_h.target_id == 16) { 2959 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 2960 xpt_done(pccb); 2961 break; 2962 } 2963 cts = &pccb->cts; 2964 #ifdef CAM_NEW_TRAN_CODE 2965 { 2966 struct ccb_trans_settings_scsi *scsi; 2967 struct ccb_trans_settings_spi *spi; 2968 struct ccb_trans_settings_sas *sas; 2969 2970 scsi = &cts->proto_specific.scsi; 2971 scsi->flags = CTS_SCSI_FLAGS_TAG_ENB; 2972 scsi->valid = CTS_SCSI_VALID_TQ; 2973 cts->protocol = PROTO_SCSI; 2974 2975 if((acb->vendor_device_id == PCIDevVenIDARC1880) || 2976 (acb->vendor_device_id == PCIDevVenIDARC1680) || 2977 (acb->vendor_device_id == PCIDevVenIDARC1214)) 2978 { 2979 cts->protocol_version = SCSI_REV_SPC2; 2980 cts->transport_version = 0; 2981 cts->transport = XPORT_SAS; 2982 sas = &cts->xport_specific.sas; 2983 sas->valid = CTS_SAS_VALID_SPEED; 2984 if((acb->vendor_device_id == PCIDevVenIDARC1880) || 2985 (acb->vendor_device_id == PCIDevVenIDARC1214)) 2986 sas->bitrate = 600000; 2987 else if(acb->vendor_device_id == PCIDevVenIDARC1680) 2988 sas->bitrate = 300000; 2989 } 2990 else 2991 { 2992 cts->protocol_version = SCSI_REV_2; 2993 cts->transport_version = 2; 2994 cts->transport = XPORT_SPI; 2995 spi = &cts->xport_specific.spi; 2996 spi->flags = CTS_SPI_FLAGS_DISC_ENB; 2997 spi->sync_period = 2; 2998 spi->sync_offset = 32; 2999 spi->bus_width = MSG_EXT_WDTR_BUS_16_BIT; 3000 spi->valid = CTS_SPI_VALID_DISC 3001 | CTS_SPI_VALID_SYNC_RATE 3002 | CTS_SPI_VALID_SYNC_OFFSET 3003 | CTS_SPI_VALID_BUS_WIDTH; 3004 } 3005 } 3006 #else 3007 { 3008 cts->flags = (CCB_TRANS_DISC_ENB | CCB_TRANS_TAG_ENB); 3009 cts->sync_period = 2; 3010 cts->sync_offset = 32; 3011 cts->bus_width = MSG_EXT_WDTR_BUS_16_BIT; 3012 cts->valid = CCB_TRANS_SYNC_RATE_VALID | 3013 CCB_TRANS_SYNC_OFFSET_VALID | 3014 CCB_TRANS_BUS_WIDTH_VALID | 3015 CCB_TRANS_DISC_VALID | 3016 CCB_TRANS_TQ_VALID; 3017 } 3018 #endif 3019 pccb->ccb_h.status |= CAM_REQ_CMP; 3020 xpt_done(pccb); 3021 break; 3022 } 3023 case XPT_SET_TRAN_SETTINGS: { 3024 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 3025 xpt_done(pccb); 3026 break; 3027 } 3028 case XPT_CALC_GEOMETRY: 3029 if(pccb->ccb_h.target_id == 16) { 3030 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 3031 xpt_done(pccb); 3032 break; 3033 } 3034 #if __FreeBSD_version >= 500000 3035 cam_calc_geometry(&pccb->ccg, 1); 3036 #else 3037 { 3038 struct ccb_calc_geometry *ccg; 3039 u_int32_t size_mb; 3040 u_int32_t secs_per_cylinder; 3041 3042 ccg = &pccb->ccg; 3043 if (ccg->block_size == 0) { 3044 pccb->ccb_h.status = CAM_REQ_INVALID; 3045 xpt_done(pccb); 3046 break; 3047 } 3048 if(((1024L * 1024L)/ccg->block_size) < 0) { 3049 pccb->ccb_h.status = CAM_REQ_INVALID; 3050 xpt_done(pccb); 3051 break; 3052 } 3053 size_mb = ccg->volume_size/((1024L * 1024L)/ccg->block_size); 3054 if(size_mb > 1024 ) { 3055 ccg->heads = 255; 3056 ccg->secs_per_track = 63; 3057 } else { 3058 ccg->heads = 64; 3059 ccg->secs_per_track = 32; 3060 } 3061 secs_per_cylinder = ccg->heads * ccg->secs_per_track; 3062 ccg->cylinders = ccg->volume_size / secs_per_cylinder; 3063 pccb->ccb_h.status |= CAM_REQ_CMP; 3064 } 3065 #endif 3066 xpt_done(pccb); 3067 break; 3068 default: 3069 pccb->ccb_h.status |= CAM_REQ_INVALID; 3070 xpt_done(pccb); 3071 break; 3072 } 3073 } 3074 /* 3075 ********************************************************************** 3076 ********************************************************************** 3077 */ 3078 static void arcmsr_start_hba_bgrb(struct AdapterControlBlock *acb) 3079 { 3080 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3081 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3082 if(!arcmsr_hba_wait_msgint_ready(acb)) { 3083 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3084 } 3085 } 3086 /* 3087 ********************************************************************** 3088 ********************************************************************** 3089 */ 3090 static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb) 3091 { 3092 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3093 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_START_BGRB); 3094 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3095 printf( "arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3096 } 3097 } 3098 /* 3099 ********************************************************************** 3100 ********************************************************************** 3101 */ 3102 static void arcmsr_start_hbc_bgrb(struct AdapterControlBlock *acb) 3103 { 3104 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3105 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3106 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3107 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 3108 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3109 } 3110 } 3111 /* 3112 ********************************************************************** 3113 ********************************************************************** 3114 */ 3115 static void arcmsr_start_hbd_bgrb(struct AdapterControlBlock *acb) 3116 { 3117 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3118 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3119 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 3120 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3121 } 3122 } 3123 /* 3124 ********************************************************************** 3125 ********************************************************************** 3126 */ 3127 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb) 3128 { 3129 switch (acb->adapter_type) { 3130 case ACB_ADAPTER_TYPE_A: 3131 arcmsr_start_hba_bgrb(acb); 3132 break; 3133 case ACB_ADAPTER_TYPE_B: 3134 arcmsr_start_hbb_bgrb(acb); 3135 break; 3136 case ACB_ADAPTER_TYPE_C: 3137 arcmsr_start_hbc_bgrb(acb); 3138 break; 3139 case ACB_ADAPTER_TYPE_D: 3140 arcmsr_start_hbd_bgrb(acb); 3141 break; 3142 } 3143 } 3144 /* 3145 ********************************************************************** 3146 ** 3147 ********************************************************************** 3148 */ 3149 static void arcmsr_polling_hba_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3150 { 3151 struct CommandControlBlock *srb; 3152 u_int32_t flag_srb, outbound_intstatus, poll_srb_done=0, poll_count=0; 3153 u_int16_t error; 3154 3155 polling_ccb_retry: 3156 poll_count++; 3157 outbound_intstatus=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 3158 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus); /*clear interrupt*/ 3159 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3160 while(1) { 3161 if((flag_srb = CHIP_REG_READ32(HBA_MessageUnit, 3162 0, outbound_queueport)) == 0xFFFFFFFF) { 3163 if(poll_srb_done) { 3164 break;/*chip FIFO no ccb for completion already*/ 3165 } else { 3166 UDELAY(25000); 3167 if ((poll_count > 100) && (poll_srb != NULL)) { 3168 break; 3169 } 3170 goto polling_ccb_retry; 3171 } 3172 } 3173 /* check if command done with no error*/ 3174 srb = (struct CommandControlBlock *) 3175 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 3176 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 3177 poll_srb_done = (srb == poll_srb) ? 1:0; 3178 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3179 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3180 printf("arcmsr%d: scsi id=%d lun=%d srb='%p'" 3181 "poll command abort successfully \n" 3182 , acb->pci_unit 3183 , srb->pccb->ccb_h.target_id 3184 , srb->pccb->ccb_h.target_lun, srb); 3185 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3186 arcmsr_srb_complete(srb, 1); 3187 continue; 3188 } 3189 printf("arcmsr%d: polling get an illegal srb command done srb='%p'" 3190 "srboutstandingcount=%d \n" 3191 , acb->pci_unit 3192 , srb, acb->srboutstandingcount); 3193 continue; 3194 } 3195 arcmsr_report_srb_state(acb, srb, error); 3196 } /*drain reply FIFO*/ 3197 } 3198 /* 3199 ********************************************************************** 3200 ** 3201 ********************************************************************** 3202 */ 3203 static void arcmsr_polling_hbb_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3204 { 3205 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3206 struct CommandControlBlock *srb; 3207 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3208 int index; 3209 u_int16_t error; 3210 3211 polling_ccb_retry: 3212 poll_count++; 3213 CHIP_REG_WRITE32(HBB_DOORBELL, 3214 0, iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */ 3215 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3216 while(1) { 3217 index = phbbmu->doneq_index; 3218 if((flag_srb = phbbmu->done_qbuffer[index]) == 0) { 3219 if(poll_srb_done) { 3220 break;/*chip FIFO no ccb for completion already*/ 3221 } else { 3222 UDELAY(25000); 3223 if ((poll_count > 100) && (poll_srb != NULL)) { 3224 break; 3225 } 3226 goto polling_ccb_retry; 3227 } 3228 } 3229 phbbmu->done_qbuffer[index] = 0; 3230 index++; 3231 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 3232 phbbmu->doneq_index = index; 3233 /* check if command done with no error*/ 3234 srb = (struct CommandControlBlock *) 3235 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 3236 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 3237 poll_srb_done = (srb == poll_srb) ? 1:0; 3238 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3239 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3240 printf("arcmsr%d: scsi id=%d lun=%d srb='%p'" 3241 "poll command abort successfully \n" 3242 , acb->pci_unit 3243 , srb->pccb->ccb_h.target_id 3244 , srb->pccb->ccb_h.target_lun, srb); 3245 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3246 arcmsr_srb_complete(srb, 1); 3247 continue; 3248 } 3249 printf("arcmsr%d: polling get an illegal srb command done srb='%p'" 3250 "srboutstandingcount=%d \n" 3251 , acb->pci_unit 3252 , srb, acb->srboutstandingcount); 3253 continue; 3254 } 3255 arcmsr_report_srb_state(acb, srb, error); 3256 } /*drain reply FIFO*/ 3257 } 3258 /* 3259 ********************************************************************** 3260 ** 3261 ********************************************************************** 3262 */ 3263 static void arcmsr_polling_hbc_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3264 { 3265 struct CommandControlBlock *srb; 3266 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3267 u_int16_t error; 3268 3269 polling_ccb_retry: 3270 poll_count++; 3271 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3272 while(1) { 3273 if(!(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)) { 3274 if(poll_srb_done) { 3275 break;/*chip FIFO no ccb for completion already*/ 3276 } else { 3277 UDELAY(25000); 3278 if ((poll_count > 100) && (poll_srb != NULL)) { 3279 break; 3280 } 3281 if (acb->srboutstandingcount == 0) { 3282 break; 3283 } 3284 goto polling_ccb_retry; 3285 } 3286 } 3287 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 3288 /* check if command done with no error*/ 3289 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/ 3290 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE; 3291 if (poll_srb != NULL) 3292 poll_srb_done = (srb == poll_srb) ? 1:0; 3293 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3294 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3295 printf("arcmsr%d: scsi id=%d lun=%d srb='%p'poll command abort successfully \n" 3296 , acb->pci_unit, srb->pccb->ccb_h.target_id, srb->pccb->ccb_h.target_lun, srb); 3297 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3298 arcmsr_srb_complete(srb, 1); 3299 continue; 3300 } 3301 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 3302 , acb->pci_unit, srb, acb->srboutstandingcount); 3303 continue; 3304 } 3305 arcmsr_report_srb_state(acb, srb, error); 3306 } /*drain reply FIFO*/ 3307 } 3308 /* 3309 ********************************************************************** 3310 ** 3311 ********************************************************************** 3312 */ 3313 static void arcmsr_polling_hbd_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3314 { 3315 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 3316 struct CommandControlBlock *srb; 3317 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3318 u_int32_t outbound_write_pointer; 3319 u_int16_t error, doneq_index; 3320 3321 polling_ccb_retry: 3322 poll_count++; 3323 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3324 while(1) { 3325 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 3326 doneq_index = phbdmu->doneq_index; 3327 if ((outbound_write_pointer & 0xFF) == (doneq_index & 0xFF)) { 3328 if(poll_srb_done) { 3329 break;/*chip FIFO no ccb for completion already*/ 3330 } else { 3331 UDELAY(25000); 3332 if ((poll_count > 100) && (poll_srb != NULL)) { 3333 break; 3334 } 3335 if (acb->srboutstandingcount == 0) { 3336 break; 3337 } 3338 goto polling_ccb_retry; 3339 } 3340 } 3341 doneq_index = arcmsr_get_doneq_index(phbdmu); 3342 flag_srb = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow; 3343 /* check if command done with no error*/ 3344 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/ 3345 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 3346 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index); 3347 if (poll_srb != NULL) 3348 poll_srb_done = (srb == poll_srb) ? 1:0; 3349 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3350 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3351 printf("arcmsr%d: scsi id=%d lun=%d srb='%p'poll command abort successfully \n" 3352 , acb->pci_unit, srb->pccb->ccb_h.target_id, srb->pccb->ccb_h.target_lun, srb); 3353 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3354 arcmsr_srb_complete(srb, 1); 3355 continue; 3356 } 3357 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 3358 , acb->pci_unit, srb, acb->srboutstandingcount); 3359 continue; 3360 } 3361 arcmsr_report_srb_state(acb, srb, error); 3362 } /*drain reply FIFO*/ 3363 } 3364 /* 3365 ********************************************************************** 3366 ********************************************************************** 3367 */ 3368 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3369 { 3370 switch (acb->adapter_type) { 3371 case ACB_ADAPTER_TYPE_A: { 3372 arcmsr_polling_hba_srbdone(acb, poll_srb); 3373 } 3374 break; 3375 case ACB_ADAPTER_TYPE_B: { 3376 arcmsr_polling_hbb_srbdone(acb, poll_srb); 3377 } 3378 break; 3379 case ACB_ADAPTER_TYPE_C: { 3380 arcmsr_polling_hbc_srbdone(acb, poll_srb); 3381 } 3382 break; 3383 case ACB_ADAPTER_TYPE_D: { 3384 arcmsr_polling_hbd_srbdone(acb, poll_srb); 3385 } 3386 break; 3387 } 3388 } 3389 /* 3390 ********************************************************************** 3391 ********************************************************************** 3392 */ 3393 static void arcmsr_get_hba_config(struct AdapterControlBlock *acb) 3394 { 3395 char *acb_firm_model = acb->firm_model; 3396 char *acb_firm_version = acb->firm_version; 3397 char *acb_device_map = acb->device_map; 3398 size_t iop_firm_model = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3399 size_t iop_firm_version = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3400 size_t iop_device_map = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3401 int i; 3402 3403 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3404 if(!arcmsr_hba_wait_msgint_ready(acb)) { 3405 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3406 } 3407 i = 0; 3408 while(i < 8) { 3409 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3410 /* 8 bytes firm_model, 15, 60-67*/ 3411 acb_firm_model++; 3412 i++; 3413 } 3414 i=0; 3415 while(i < 16) { 3416 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3417 /* 16 bytes firm_version, 17, 68-83*/ 3418 acb_firm_version++; 3419 i++; 3420 } 3421 i=0; 3422 while(i < 16) { 3423 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3424 acb_device_map++; 3425 i++; 3426 } 3427 printf("ARECA RAID ADAPTER%d: %s \n", acb->pci_unit, ARCMSR_DRIVER_VERSION); 3428 printf("ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n", acb->pci_unit, acb->firm_version); 3429 acb->firm_request_len = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3430 acb->firm_numbers_queue = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3431 acb->firm_sdram_size = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3432 acb->firm_ide_channels = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3433 acb->firm_cfg_version = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3434 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 3435 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 3436 else 3437 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3438 } 3439 /* 3440 ********************************************************************** 3441 ********************************************************************** 3442 */ 3443 static void arcmsr_get_hbb_config(struct AdapterControlBlock *acb) 3444 { 3445 char *acb_firm_model = acb->firm_model; 3446 char *acb_firm_version = acb->firm_version; 3447 char *acb_device_map = acb->device_map; 3448 size_t iop_firm_model = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3449 size_t iop_firm_version = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3450 size_t iop_device_map = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3451 int i; 3452 3453 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG); 3454 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3455 printf( "arcmsr%d: wait" "'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3456 } 3457 i = 0; 3458 while(i < 8) { 3459 *acb_firm_model = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_model+i); 3460 /* 8 bytes firm_model, 15, 60-67*/ 3461 acb_firm_model++; 3462 i++; 3463 } 3464 i = 0; 3465 while(i < 16) { 3466 *acb_firm_version = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_version+i); 3467 /* 16 bytes firm_version, 17, 68-83*/ 3468 acb_firm_version++; 3469 i++; 3470 } 3471 i = 0; 3472 while(i < 16) { 3473 *acb_device_map = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_device_map+i); 3474 acb_device_map++; 3475 i++; 3476 } 3477 printf("ARECA RAID ADAPTER%d: %s \n", acb->pci_unit, ARCMSR_DRIVER_VERSION); 3478 printf("ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n", acb->pci_unit, acb->firm_version); 3479 acb->firm_request_len = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3480 acb->firm_numbers_queue = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3481 acb->firm_sdram_size = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3482 acb->firm_ide_channels = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3483 acb->firm_cfg_version = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3484 if(acb->firm_numbers_queue > ARCMSR_MAX_HBB_POSTQUEUE) 3485 acb->maxOutstanding = ARCMSR_MAX_HBB_POSTQUEUE - 1; 3486 else 3487 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3488 } 3489 /* 3490 ********************************************************************** 3491 ********************************************************************** 3492 */ 3493 static void arcmsr_get_hbc_config(struct AdapterControlBlock *acb) 3494 { 3495 char *acb_firm_model = acb->firm_model; 3496 char *acb_firm_version = acb->firm_version; 3497 char *acb_device_map = acb->device_map; 3498 size_t iop_firm_model = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3499 size_t iop_firm_version = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3500 size_t iop_device_map = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3501 int i; 3502 3503 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3504 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3505 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 3506 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3507 } 3508 i = 0; 3509 while(i < 8) { 3510 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3511 /* 8 bytes firm_model, 15, 60-67*/ 3512 acb_firm_model++; 3513 i++; 3514 } 3515 i = 0; 3516 while(i < 16) { 3517 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3518 /* 16 bytes firm_version, 17, 68-83*/ 3519 acb_firm_version++; 3520 i++; 3521 } 3522 i = 0; 3523 while(i < 16) { 3524 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3525 acb_device_map++; 3526 i++; 3527 } 3528 printf("ARECA RAID ADAPTER%d: %s \n", acb->pci_unit, ARCMSR_DRIVER_VERSION); 3529 printf("ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n", acb->pci_unit, acb->firm_version); 3530 acb->firm_request_len = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3531 acb->firm_numbers_queue = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3532 acb->firm_sdram_size = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3533 acb->firm_ide_channels = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3534 acb->firm_cfg_version = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3535 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 3536 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 3537 else 3538 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3539 } 3540 /* 3541 ********************************************************************** 3542 ********************************************************************** 3543 */ 3544 static void arcmsr_get_hbd_config(struct AdapterControlBlock *acb) 3545 { 3546 char *acb_firm_model = acb->firm_model; 3547 char *acb_firm_version = acb->firm_version; 3548 char *acb_device_map = acb->device_map; 3549 size_t iop_firm_model = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3550 size_t iop_firm_version = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3551 size_t iop_device_map = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3552 int i; 3553 3554 if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) 3555 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR); 3556 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3557 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 3558 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3559 } 3560 i = 0; 3561 while(i < 8) { 3562 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3563 /* 8 bytes firm_model, 15, 60-67*/ 3564 acb_firm_model++; 3565 i++; 3566 } 3567 i = 0; 3568 while(i < 16) { 3569 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3570 /* 16 bytes firm_version, 17, 68-83*/ 3571 acb_firm_version++; 3572 i++; 3573 } 3574 i = 0; 3575 while(i < 16) { 3576 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3577 acb_device_map++; 3578 i++; 3579 } 3580 printf("ARECA RAID ADAPTER%d: %s \n", acb->pci_unit, ARCMSR_DRIVER_VERSION); 3581 printf("ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n", acb->pci_unit, acb->firm_version); 3582 acb->firm_request_len = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_request_len, 1, 04-07*/ 3583 acb->firm_numbers_queue = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_numbers_queue, 2, 08-11*/ 3584 acb->firm_sdram_size = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_sdram_size, 3, 12-15*/ 3585 acb->firm_ide_channels = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[5]); /*firm_ide_channels, 4, 16-19*/ 3586 acb->firm_cfg_version = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3587 if(acb->firm_numbers_queue > ARCMSR_MAX_HBD_POSTQUEUE) 3588 acb->maxOutstanding = ARCMSR_MAX_HBD_POSTQUEUE - 1; 3589 else 3590 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3591 } 3592 /* 3593 ********************************************************************** 3594 ********************************************************************** 3595 */ 3596 static void arcmsr_get_firmware_spec(struct AdapterControlBlock *acb) 3597 { 3598 switch (acb->adapter_type) { 3599 case ACB_ADAPTER_TYPE_A: { 3600 arcmsr_get_hba_config(acb); 3601 } 3602 break; 3603 case ACB_ADAPTER_TYPE_B: { 3604 arcmsr_get_hbb_config(acb); 3605 } 3606 break; 3607 case ACB_ADAPTER_TYPE_C: { 3608 arcmsr_get_hbc_config(acb); 3609 } 3610 break; 3611 case ACB_ADAPTER_TYPE_D: { 3612 arcmsr_get_hbd_config(acb); 3613 } 3614 break; 3615 } 3616 } 3617 /* 3618 ********************************************************************** 3619 ********************************************************************** 3620 */ 3621 static void arcmsr_wait_firmware_ready( struct AdapterControlBlock *acb) 3622 { 3623 int timeout=0; 3624 3625 switch (acb->adapter_type) { 3626 case ACB_ADAPTER_TYPE_A: { 3627 while ((CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0) 3628 { 3629 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 3630 { 3631 printf( "arcmsr%d:timed out waiting for firmware \n", acb->pci_unit); 3632 return; 3633 } 3634 UDELAY(15000); /* wait 15 milli-seconds */ 3635 } 3636 } 3637 break; 3638 case ACB_ADAPTER_TYPE_B: { 3639 while ((CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & ARCMSR_MESSAGE_FIRMWARE_OK) == 0) 3640 { 3641 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 3642 { 3643 printf( "arcmsr%d: timed out waiting for firmware \n", acb->pci_unit); 3644 return; 3645 } 3646 UDELAY(15000); /* wait 15 milli-seconds */ 3647 } 3648 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 3649 } 3650 break; 3651 case ACB_ADAPTER_TYPE_C: { 3652 while ((CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0) 3653 { 3654 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 3655 { 3656 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 3657 return; 3658 } 3659 UDELAY(15000); /* wait 15 milli-seconds */ 3660 } 3661 } 3662 break; 3663 case ACB_ADAPTER_TYPE_D: { 3664 while ((CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK) == 0) 3665 { 3666 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 3667 { 3668 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 3669 return; 3670 } 3671 UDELAY(15000); /* wait 15 milli-seconds */ 3672 } 3673 } 3674 break; 3675 } 3676 } 3677 /* 3678 ********************************************************************** 3679 ********************************************************************** 3680 */ 3681 static void arcmsr_clear_doorbell_queue_buffer( struct AdapterControlBlock *acb) 3682 { 3683 u_int32_t outbound_doorbell; 3684 3685 switch (acb->adapter_type) { 3686 case ACB_ADAPTER_TYPE_A: { 3687 /* empty doorbell Qbuffer if door bell ringed */ 3688 outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell); 3689 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */ 3690 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK); 3691 3692 } 3693 break; 3694 case ACB_ADAPTER_TYPE_B: { 3695 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt and message state*/ 3696 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK); 3697 /* let IOP know data has been read */ 3698 } 3699 break; 3700 case ACB_ADAPTER_TYPE_C: { 3701 /* empty doorbell Qbuffer if door bell ringed */ 3702 outbound_doorbell = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell); 3703 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell); /*clear doorbell interrupt */ 3704 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK); 3705 CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell_clear); /* Dummy read to force pci flush */ 3706 CHIP_REG_READ32(HBC_MessageUnit, 0, inbound_doorbell); /* Dummy read to force pci flush */ 3707 } 3708 break; 3709 case ACB_ADAPTER_TYPE_D: { 3710 /* empty doorbell Qbuffer if door bell ringed */ 3711 outbound_doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell); 3712 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */ 3713 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ); 3714 3715 } 3716 break; 3717 } 3718 } 3719 /* 3720 ************************************************************************ 3721 ************************************************************************ 3722 */ 3723 static u_int32_t arcmsr_iop_confirm(struct AdapterControlBlock *acb) 3724 { 3725 unsigned long srb_phyaddr; 3726 u_int32_t srb_phyaddr_hi32; 3727 u_int32_t srb_phyaddr_lo32; 3728 3729 /* 3730 ******************************************************************** 3731 ** here we need to tell iop 331 our freesrb.HighPart 3732 ** if freesrb.HighPart is not zero 3733 ******************************************************************** 3734 */ 3735 srb_phyaddr = (unsigned long) acb->srb_phyaddr.phyaddr; 3736 srb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high; 3737 srb_phyaddr_lo32 = acb->srb_phyaddr.B.phyadd_low; 3738 switch (acb->adapter_type) { 3739 case ACB_ADAPTER_TYPE_A: { 3740 if(srb_phyaddr_hi32 != 0) { 3741 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 3742 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 3743 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 3744 if(!arcmsr_hba_wait_msgint_ready(acb)) { 3745 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 3746 return FALSE; 3747 } 3748 } 3749 } 3750 break; 3751 /* 3752 *********************************************************************** 3753 ** if adapter type B, set window of "post command Q" 3754 *********************************************************************** 3755 */ 3756 case ACB_ADAPTER_TYPE_B: { 3757 u_int32_t post_queue_phyaddr; 3758 struct HBB_MessageUnit *phbbmu; 3759 3760 phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3761 phbbmu->postq_index = 0; 3762 phbbmu->doneq_index = 0; 3763 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_SET_POST_WINDOW); 3764 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3765 printf( "arcmsr%d: 'set window of post command Q' timeout\n", acb->pci_unit); 3766 return FALSE; 3767 } 3768 post_queue_phyaddr = srb_phyaddr + ARCMSR_SRBS_POOL_SIZE 3769 + offsetof(struct HBB_MessageUnit, post_qbuffer); 3770 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */ 3771 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1], srb_phyaddr_hi32); /* normal should be zero */ 3772 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ size (256+8)*4 */ 3773 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3], post_queue_phyaddr+1056); /* doneQ size (256+8)*4 */ 3774 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4], 1056); /* srb maxQ size must be --> [(256+8)*4] */ 3775 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_SET_CONFIG); 3776 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3777 printf( "arcmsr%d: 'set command Q window' timeout \n", acb->pci_unit); 3778 return FALSE; 3779 } 3780 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_START_DRIVER_MODE); 3781 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3782 printf( "arcmsr%d: 'start diver mode' timeout \n", acb->pci_unit); 3783 return FALSE; 3784 } 3785 } 3786 break; 3787 case ACB_ADAPTER_TYPE_C: { 3788 if(srb_phyaddr_hi32 != 0) { 3789 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 3790 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 3791 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 3792 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3793 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 3794 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 3795 return FALSE; 3796 } 3797 } 3798 } 3799 break; 3800 case ACB_ADAPTER_TYPE_D: { 3801 u_int32_t post_queue_phyaddr, done_queue_phyaddr; 3802 struct HBD_MessageUnit0 *phbdmu; 3803 3804 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 3805 phbdmu->postq_index = 0; 3806 phbdmu->doneq_index = 0x40FF; 3807 post_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE 3808 + offsetof(struct HBD_MessageUnit0, post_qbuffer); 3809 done_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE 3810 + offsetof(struct HBD_MessageUnit0, done_qbuffer); 3811 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */ 3812 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 3813 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ base */ 3814 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[3], done_queue_phyaddr); /* doneQ base */ 3815 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[4], 0x100); 3816 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 3817 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 3818 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 3819 return FALSE; 3820 } 3821 } 3822 break; 3823 } 3824 return (TRUE); 3825 } 3826 /* 3827 ************************************************************************ 3828 ************************************************************************ 3829 */ 3830 static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb) 3831 { 3832 switch (acb->adapter_type) 3833 { 3834 case ACB_ADAPTER_TYPE_A: 3835 case ACB_ADAPTER_TYPE_C: 3836 case ACB_ADAPTER_TYPE_D: 3837 break; 3838 case ACB_ADAPTER_TYPE_B: { 3839 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell,ARCMSR_MESSAGE_ACTIVE_EOI_MODE); 3840 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3841 printf( "arcmsr%d: 'iop enable eoi mode' timeout \n", acb->pci_unit); 3842 return; 3843 } 3844 } 3845 break; 3846 } 3847 } 3848 /* 3849 ********************************************************************** 3850 ********************************************************************** 3851 */ 3852 static void arcmsr_iop_init(struct AdapterControlBlock *acb) 3853 { 3854 u_int32_t intmask_org; 3855 3856 /* disable all outbound interrupt */ 3857 intmask_org = arcmsr_disable_allintr(acb); 3858 arcmsr_wait_firmware_ready(acb); 3859 arcmsr_iop_confirm(acb); 3860 arcmsr_get_firmware_spec(acb); 3861 /*start background rebuild*/ 3862 arcmsr_start_adapter_bgrb(acb); 3863 /* empty doorbell Qbuffer if door bell ringed */ 3864 arcmsr_clear_doorbell_queue_buffer(acb); 3865 arcmsr_enable_eoi_mode(acb); 3866 /* enable outbound Post Queue, outbound doorbell Interrupt */ 3867 arcmsr_enable_allintr(acb, intmask_org); 3868 acb->acb_flags |= ACB_F_IOP_INITED; 3869 } 3870 /* 3871 ********************************************************************** 3872 ********************************************************************** 3873 */ 3874 static void arcmsr_map_free_srb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3875 { 3876 struct AdapterControlBlock *acb = arg; 3877 struct CommandControlBlock *srb_tmp; 3878 u_int32_t i; 3879 unsigned long srb_phyaddr = (unsigned long)segs->ds_addr; 3880 3881 acb->srb_phyaddr.phyaddr = srb_phyaddr; 3882 srb_tmp = (struct CommandControlBlock *)acb->uncacheptr; 3883 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 3884 if(bus_dmamap_create(acb->dm_segs_dmat, 3885 /*flags*/0, &srb_tmp->dm_segs_dmamap) != 0) { 3886 acb->acb_flags |= ACB_F_MAPFREESRB_FAILD; 3887 printf("arcmsr%d:" 3888 " srb dmamap bus_dmamap_create error\n", acb->pci_unit); 3889 return; 3890 } 3891 if((acb->adapter_type == ACB_ADAPTER_TYPE_C) || (acb->adapter_type == ACB_ADAPTER_TYPE_D)) 3892 { 3893 srb_tmp->cdb_phyaddr_low = srb_phyaddr; 3894 srb_tmp->cdb_phyaddr_high = (u_int32_t)((srb_phyaddr >> 16) >> 16); 3895 } 3896 else 3897 srb_tmp->cdb_phyaddr_low = srb_phyaddr >> 5; 3898 srb_tmp->acb = acb; 3899 acb->srbworkingQ[i] = acb->psrb_pool[i] = srb_tmp; 3900 srb_phyaddr = srb_phyaddr + SRB_SIZE; 3901 srb_tmp = (struct CommandControlBlock *)((unsigned long)srb_tmp + SRB_SIZE); 3902 } 3903 acb->vir2phy_offset = (unsigned long)srb_tmp - (unsigned long)srb_phyaddr; 3904 } 3905 /* 3906 ************************************************************************ 3907 ************************************************************************ 3908 */ 3909 static void arcmsr_free_resource(struct AdapterControlBlock *acb) 3910 { 3911 /* remove the control device */ 3912 if(acb->ioctl_dev != NULL) { 3913 destroy_dev(acb->ioctl_dev); 3914 } 3915 bus_dmamap_unload(acb->srb_dmat, acb->srb_dmamap); 3916 bus_dmamap_destroy(acb->srb_dmat, acb->srb_dmamap); 3917 bus_dma_tag_destroy(acb->srb_dmat); 3918 bus_dma_tag_destroy(acb->dm_segs_dmat); 3919 bus_dma_tag_destroy(acb->parent_dmat); 3920 } 3921 /* 3922 ************************************************************************ 3923 ************************************************************************ 3924 */ 3925 static void arcmsr_mutex_init(struct AdapterControlBlock *acb) 3926 { 3927 ARCMSR_LOCK_INIT(&acb->isr_lock, "arcmsr isr lock"); 3928 ARCMSR_LOCK_INIT(&acb->srb_lock, "arcmsr srb lock"); 3929 ARCMSR_LOCK_INIT(&acb->postDone_lock, "arcmsr postQ lock"); 3930 ARCMSR_LOCK_INIT(&acb->qbuffer_lock, "arcmsr RW buffer lock"); 3931 } 3932 /* 3933 ************************************************************************ 3934 ************************************************************************ 3935 */ 3936 static void arcmsr_mutex_destroy(struct AdapterControlBlock *acb) 3937 { 3938 ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock); 3939 ARCMSR_LOCK_DESTROY(&acb->postDone_lock); 3940 ARCMSR_LOCK_DESTROY(&acb->srb_lock); 3941 ARCMSR_LOCK_DESTROY(&acb->isr_lock); 3942 } 3943 /* 3944 ************************************************************************ 3945 ************************************************************************ 3946 */ 3947 static u_int32_t arcmsr_initialize(device_t dev) 3948 { 3949 struct AdapterControlBlock *acb = device_get_softc(dev); 3950 u_int16_t pci_command; 3951 int i, j,max_coherent_size; 3952 u_int32_t vendor_dev_id; 3953 3954 vendor_dev_id = pci_get_devid(dev); 3955 acb->vendor_device_id = vendor_dev_id; 3956 switch (vendor_dev_id) { 3957 case PCIDevVenIDARC1880: 3958 case PCIDevVenIDARC1882: 3959 case PCIDevVenIDARC1213: 3960 case PCIDevVenIDARC1223: { 3961 acb->adapter_type = ACB_ADAPTER_TYPE_C; 3962 acb->adapter_bus_speed = ACB_BUS_SPEED_6G; 3963 max_coherent_size = ARCMSR_SRBS_POOL_SIZE; 3964 } 3965 break; 3966 case PCIDevVenIDARC1214: { 3967 acb->adapter_type = ACB_ADAPTER_TYPE_D; 3968 acb->adapter_bus_speed = ACB_BUS_SPEED_6G; 3969 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBD_MessageUnit0)); 3970 } 3971 break; 3972 case PCIDevVenIDARC1200: 3973 case PCIDevVenIDARC1201: { 3974 acb->adapter_type = ACB_ADAPTER_TYPE_B; 3975 acb->adapter_bus_speed = ACB_BUS_SPEED_3G; 3976 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit)); 3977 } 3978 break; 3979 case PCIDevVenIDARC1110: 3980 case PCIDevVenIDARC1120: 3981 case PCIDevVenIDARC1130: 3982 case PCIDevVenIDARC1160: 3983 case PCIDevVenIDARC1170: 3984 case PCIDevVenIDARC1210: 3985 case PCIDevVenIDARC1220: 3986 case PCIDevVenIDARC1230: 3987 case PCIDevVenIDARC1231: 3988 case PCIDevVenIDARC1260: 3989 case PCIDevVenIDARC1261: 3990 case PCIDevVenIDARC1270: 3991 case PCIDevVenIDARC1280: 3992 case PCIDevVenIDARC1212: 3993 case PCIDevVenIDARC1222: 3994 case PCIDevVenIDARC1380: 3995 case PCIDevVenIDARC1381: 3996 case PCIDevVenIDARC1680: 3997 case PCIDevVenIDARC1681: { 3998 acb->adapter_type = ACB_ADAPTER_TYPE_A; 3999 acb->adapter_bus_speed = ACB_BUS_SPEED_3G; 4000 max_coherent_size = ARCMSR_SRBS_POOL_SIZE; 4001 } 4002 break; 4003 default: { 4004 printf("arcmsr%d:" 4005 " unknown RAID adapter type \n", device_get_unit(dev)); 4006 return ENOMEM; 4007 } 4008 } 4009 #if __FreeBSD_version >= 700000 4010 if(bus_dma_tag_create( /*PCI parent*/ bus_get_dma_tag(dev), 4011 #else 4012 if(bus_dma_tag_create( /*PCI parent*/ NULL, 4013 #endif 4014 /*alignemnt*/ 1, 4015 /*boundary*/ 0, 4016 /*lowaddr*/ BUS_SPACE_MAXADDR, 4017 /*highaddr*/ BUS_SPACE_MAXADDR, 4018 /*filter*/ NULL, 4019 /*filterarg*/ NULL, 4020 /*maxsize*/ BUS_SPACE_MAXSIZE_32BIT, 4021 /*nsegments*/ BUS_SPACE_UNRESTRICTED, 4022 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4023 /*flags*/ 0, 4024 #if __FreeBSD_version >= 501102 4025 /*lockfunc*/ NULL, 4026 /*lockarg*/ NULL, 4027 #endif 4028 &acb->parent_dmat) != 0) 4029 { 4030 printf("arcmsr%d: parent_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4031 return ENOMEM; 4032 } 4033 4034 /* Create a single tag describing a region large enough to hold all of the s/g lists we will need. */ 4035 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat, 4036 /*alignment*/ 1, 4037 /*boundary*/ 0, 4038 #ifdef PAE 4039 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 4040 #else 4041 /*lowaddr*/ BUS_SPACE_MAXADDR, 4042 #endif 4043 /*highaddr*/ BUS_SPACE_MAXADDR, 4044 /*filter*/ NULL, 4045 /*filterarg*/ NULL, 4046 /*maxsize*/ ARCMSR_MAX_SG_ENTRIES * PAGE_SIZE * ARCMSR_MAX_FREESRB_NUM, 4047 /*nsegments*/ ARCMSR_MAX_SG_ENTRIES, 4048 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4049 /*flags*/ 0, 4050 #if __FreeBSD_version >= 501102 4051 /*lockfunc*/ busdma_lock_mutex, 4052 /*lockarg*/ &acb->isr_lock, 4053 #endif 4054 &acb->dm_segs_dmat) != 0) 4055 { 4056 bus_dma_tag_destroy(acb->parent_dmat); 4057 printf("arcmsr%d: dm_segs_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4058 return ENOMEM; 4059 } 4060 4061 /* DMA tag for our srb structures.... Allocate the freesrb memory */ 4062 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat, 4063 /*alignment*/ 0x20, 4064 /*boundary*/ 0, 4065 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 4066 /*highaddr*/ BUS_SPACE_MAXADDR, 4067 /*filter*/ NULL, 4068 /*filterarg*/ NULL, 4069 /*maxsize*/ max_coherent_size, 4070 /*nsegments*/ 1, 4071 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4072 /*flags*/ 0, 4073 #if __FreeBSD_version >= 501102 4074 /*lockfunc*/ NULL, 4075 /*lockarg*/ NULL, 4076 #endif 4077 &acb->srb_dmat) != 0) 4078 { 4079 bus_dma_tag_destroy(acb->dm_segs_dmat); 4080 bus_dma_tag_destroy(acb->parent_dmat); 4081 printf("arcmsr%d: srb_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4082 return ENXIO; 4083 } 4084 /* Allocation for our srbs */ 4085 if(bus_dmamem_alloc(acb->srb_dmat, (void **)&acb->uncacheptr, BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, &acb->srb_dmamap) != 0) { 4086 bus_dma_tag_destroy(acb->srb_dmat); 4087 bus_dma_tag_destroy(acb->dm_segs_dmat); 4088 bus_dma_tag_destroy(acb->parent_dmat); 4089 printf("arcmsr%d: srb_dmat bus_dmamem_alloc failure!\n", device_get_unit(dev)); 4090 return ENXIO; 4091 } 4092 /* And permanently map them */ 4093 if(bus_dmamap_load(acb->srb_dmat, acb->srb_dmamap, acb->uncacheptr, max_coherent_size, arcmsr_map_free_srb, acb, /*flags*/0)) { 4094 bus_dma_tag_destroy(acb->srb_dmat); 4095 bus_dma_tag_destroy(acb->dm_segs_dmat); 4096 bus_dma_tag_destroy(acb->parent_dmat); 4097 printf("arcmsr%d: srb_dmat bus_dmamap_load failure!\n", device_get_unit(dev)); 4098 return ENXIO; 4099 } 4100 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 4101 pci_command |= PCIM_CMD_BUSMASTEREN; 4102 pci_command |= PCIM_CMD_PERRESPEN; 4103 pci_command |= PCIM_CMD_MWRICEN; 4104 /* Enable Busmaster */ 4105 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 4106 switch(acb->adapter_type) { 4107 case ACB_ADAPTER_TYPE_A: { 4108 u_int32_t rid0 = PCIR_BAR(0); 4109 vm_offset_t mem_base0; 4110 4111 acb->sys_res_arcmsr[0] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, 0x1000, RF_ACTIVE); 4112 if(acb->sys_res_arcmsr[0] == NULL) { 4113 arcmsr_free_resource(acb); 4114 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4115 return ENOMEM; 4116 } 4117 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4118 arcmsr_free_resource(acb); 4119 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4120 return ENXIO; 4121 } 4122 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4123 if(mem_base0 == 0) { 4124 arcmsr_free_resource(acb); 4125 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4126 return ENXIO; 4127 } 4128 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4129 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4130 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4131 } 4132 break; 4133 case ACB_ADAPTER_TYPE_B: { 4134 struct HBB_MessageUnit *phbbmu; 4135 struct CommandControlBlock *freesrb; 4136 u_int32_t rid[]={ PCIR_BAR(0), PCIR_BAR(2) }; 4137 vm_offset_t mem_base[]={0,0}; 4138 for(i=0; i < 2; i++) { 4139 if(i == 0) { 4140 acb->sys_res_arcmsr[i] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid[i], 4141 0ul, ~0ul, sizeof(struct HBB_DOORBELL), RF_ACTIVE); 4142 } else { 4143 acb->sys_res_arcmsr[i] = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid[i], 4144 0ul, ~0ul, sizeof(struct HBB_RWBUFFER), RF_ACTIVE); 4145 } 4146 if(acb->sys_res_arcmsr[i] == NULL) { 4147 arcmsr_free_resource(acb); 4148 printf("arcmsr%d: bus_alloc_resource %d failure!\n", device_get_unit(dev), i); 4149 return ENOMEM; 4150 } 4151 if(rman_get_start(acb->sys_res_arcmsr[i]) <= 0) { 4152 arcmsr_free_resource(acb); 4153 printf("arcmsr%d: rman_get_start %d failure!\n", device_get_unit(dev), i); 4154 return ENXIO; 4155 } 4156 mem_base[i] = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[i]); 4157 if(mem_base[i] == 0) { 4158 arcmsr_free_resource(acb); 4159 printf("arcmsr%d: rman_get_virtual %d failure!\n", device_get_unit(dev), i); 4160 return ENXIO; 4161 } 4162 acb->btag[i] = rman_get_bustag(acb->sys_res_arcmsr[i]); 4163 acb->bhandle[i] = rman_get_bushandle(acb->sys_res_arcmsr[i]); 4164 } 4165 freesrb = (struct CommandControlBlock *)acb->uncacheptr; 4166 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)freesrb+ARCMSR_SRBS_POOL_SIZE); 4167 phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4168 phbbmu->hbb_doorbell = (struct HBB_DOORBELL *)mem_base[0]; 4169 phbbmu->hbb_rwbuffer = (struct HBB_RWBUFFER *)mem_base[1]; 4170 } 4171 break; 4172 case ACB_ADAPTER_TYPE_C: { 4173 u_int32_t rid0 = PCIR_BAR(1); 4174 vm_offset_t mem_base0; 4175 4176 acb->sys_res_arcmsr[0] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, sizeof(struct HBC_MessageUnit), RF_ACTIVE); 4177 if(acb->sys_res_arcmsr[0] == NULL) { 4178 arcmsr_free_resource(acb); 4179 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4180 return ENOMEM; 4181 } 4182 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4183 arcmsr_free_resource(acb); 4184 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4185 return ENXIO; 4186 } 4187 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4188 if(mem_base0 == 0) { 4189 arcmsr_free_resource(acb); 4190 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4191 return ENXIO; 4192 } 4193 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4194 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4195 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4196 } 4197 break; 4198 case ACB_ADAPTER_TYPE_D: { 4199 struct HBD_MessageUnit0 *phbdmu; 4200 u_int32_t rid0 = PCIR_BAR(0); 4201 vm_offset_t mem_base0; 4202 4203 acb->sys_res_arcmsr[0] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, sizeof(struct HBD_MessageUnit), RF_ACTIVE); 4204 if(acb->sys_res_arcmsr[0] == NULL) { 4205 arcmsr_free_resource(acb); 4206 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4207 return ENOMEM; 4208 } 4209 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4210 arcmsr_free_resource(acb); 4211 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4212 return ENXIO; 4213 } 4214 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4215 if(mem_base0 == 0) { 4216 arcmsr_free_resource(acb); 4217 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4218 return ENXIO; 4219 } 4220 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4221 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4222 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)acb->uncacheptr+ARCMSR_SRBS_POOL_SIZE); 4223 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 4224 phbdmu->phbdmu = (struct HBD_MessageUnit *)mem_base0; 4225 } 4226 break; 4227 } 4228 if(acb->acb_flags & ACB_F_MAPFREESRB_FAILD) { 4229 arcmsr_free_resource(acb); 4230 printf("arcmsr%d: map free srb failure!\n", device_get_unit(dev)); 4231 return ENXIO; 4232 } 4233 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_RQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ); 4234 acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER; 4235 /* 4236 ******************************************************************** 4237 ** init raid volume state 4238 ******************************************************************** 4239 */ 4240 for(i=0; i < ARCMSR_MAX_TARGETID; i++) { 4241 for(j=0; j < ARCMSR_MAX_TARGETLUN; j++) { 4242 acb->devstate[i][j] = ARECA_RAID_GONE; 4243 } 4244 } 4245 arcmsr_iop_init(acb); 4246 return(0); 4247 } 4248 /* 4249 ************************************************************************ 4250 ************************************************************************ 4251 */ 4252 static int arcmsr_attach(device_t dev) 4253 { 4254 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 4255 u_int32_t unit=device_get_unit(dev); 4256 struct ccb_setasync csa; 4257 struct cam_devq *devq; /* Device Queue to use for this SIM */ 4258 struct resource *irqres; 4259 int rid; 4260 4261 if(acb == NULL) { 4262 printf("arcmsr%d: cannot allocate softc\n", unit); 4263 return (ENOMEM); 4264 } 4265 arcmsr_mutex_init(acb); 4266 if(arcmsr_initialize(dev)) { 4267 printf("arcmsr%d: initialize failure!\n", unit); 4268 arcmsr_mutex_destroy(acb); 4269 return ENXIO; 4270 } 4271 /* After setting up the adapter, map our interrupt */ 4272 rid = 0; 4273 irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1, RF_SHAREABLE | RF_ACTIVE); 4274 if(irqres == NULL || 4275 #if __FreeBSD_version >= 700025 4276 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, NULL, arcmsr_intr_handler, acb, &acb->ih)) { 4277 #else 4278 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, arcmsr_intr_handler, acb, &acb->ih)) { 4279 #endif 4280 arcmsr_free_resource(acb); 4281 arcmsr_mutex_destroy(acb); 4282 printf("arcmsr%d: unable to register interrupt handler!\n", unit); 4283 return ENXIO; 4284 } 4285 acb->irqres = irqres; 4286 acb->pci_dev = dev; 4287 acb->pci_unit = unit; 4288 /* 4289 * Now let the CAM generic SCSI layer find the SCSI devices on 4290 * the bus * start queue to reset to the idle loop. * 4291 * Create device queue of SIM(s) * (MAX_START_JOB - 1) : 4292 * max_sim_transactions 4293 */ 4294 devq = cam_simq_alloc(ARCMSR_MAX_START_JOB); 4295 if(devq == NULL) { 4296 arcmsr_free_resource(acb); 4297 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres); 4298 arcmsr_mutex_destroy(acb); 4299 printf("arcmsr%d: cam_simq_alloc failure!\n", unit); 4300 return ENXIO; 4301 } 4302 #if __FreeBSD_version >= 700025 4303 acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, &acb->isr_lock, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq); 4304 #else 4305 acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq); 4306 #endif 4307 if(acb->psim == NULL) { 4308 arcmsr_free_resource(acb); 4309 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres); 4310 cam_simq_free(devq); 4311 arcmsr_mutex_destroy(acb); 4312 printf("arcmsr%d: cam_sim_alloc failure!\n", unit); 4313 return ENXIO; 4314 } 4315 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 4316 #if __FreeBSD_version >= 700044 4317 if(xpt_bus_register(acb->psim, dev, 0) != CAM_SUCCESS) { 4318 #else 4319 if(xpt_bus_register(acb->psim, 0) != CAM_SUCCESS) { 4320 #endif 4321 arcmsr_free_resource(acb); 4322 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres); 4323 cam_sim_free(acb->psim, /*free_devq*/TRUE); 4324 arcmsr_mutex_destroy(acb); 4325 printf("arcmsr%d: xpt_bus_register failure!\n", unit); 4326 return ENXIO; 4327 } 4328 if(xpt_create_path(&acb->ppath, /* periph */ NULL, cam_sim_path(acb->psim), CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 4329 arcmsr_free_resource(acb); 4330 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres); 4331 xpt_bus_deregister(cam_sim_path(acb->psim)); 4332 cam_sim_free(acb->psim, /* free_simq */ TRUE); 4333 arcmsr_mutex_destroy(acb); 4334 printf("arcmsr%d: xpt_create_path failure!\n", unit); 4335 return ENXIO; 4336 } 4337 /* 4338 **************************************************** 4339 */ 4340 xpt_setup_ccb(&csa.ccb_h, acb->ppath, /*priority*/5); 4341 csa.ccb_h.func_code = XPT_SASYNC_CB; 4342 csa.event_enable = AC_FOUND_DEVICE|AC_LOST_DEVICE; 4343 csa.callback = arcmsr_async; 4344 csa.callback_arg = acb->psim; 4345 xpt_action((union ccb *)&csa); 4346 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 4347 /* Create the control device. */ 4348 acb->ioctl_dev = make_dev(&arcmsr_cdevsw, unit, UID_ROOT, GID_WHEEL /* GID_OPERATOR */, S_IRUSR | S_IWUSR, "arcmsr%d", unit); 4349 4350 #if __FreeBSD_version < 503000 4351 acb->ioctl_dev->si_drv1 = acb; 4352 #endif 4353 #if __FreeBSD_version > 500005 4354 (void)make_dev_alias(acb->ioctl_dev, "arc%d", unit); 4355 #endif 4356 arcmsr_callout_init(&acb->devmap_callout); 4357 callout_reset(&acb->devmap_callout, 60 * hz, arcmsr_polling_devmap, acb); 4358 return (0); 4359 } 4360 4361 /* 4362 ************************************************************************ 4363 ************************************************************************ 4364 */ 4365 static int arcmsr_probe(device_t dev) 4366 { 4367 u_int32_t id; 4368 static char buf[256]; 4369 char x_type[]={"X-TYPE"}; 4370 char *type; 4371 int raid6 = 1; 4372 4373 if (pci_get_vendor(dev) != PCI_VENDOR_ID_ARECA) { 4374 return (ENXIO); 4375 } 4376 switch(id = pci_get_devid(dev)) { 4377 case PCIDevVenIDARC1110: 4378 case PCIDevVenIDARC1200: 4379 case PCIDevVenIDARC1201: 4380 case PCIDevVenIDARC1210: 4381 raid6 = 0; 4382 /*FALLTHRU*/ 4383 case PCIDevVenIDARC1120: 4384 case PCIDevVenIDARC1130: 4385 case PCIDevVenIDARC1160: 4386 case PCIDevVenIDARC1170: 4387 case PCIDevVenIDARC1220: 4388 case PCIDevVenIDARC1230: 4389 case PCIDevVenIDARC1231: 4390 case PCIDevVenIDARC1260: 4391 case PCIDevVenIDARC1261: 4392 case PCIDevVenIDARC1270: 4393 case PCIDevVenIDARC1280: 4394 type = "SATA 3G"; 4395 break; 4396 case PCIDevVenIDARC1212: 4397 case PCIDevVenIDARC1222: 4398 case PCIDevVenIDARC1380: 4399 case PCIDevVenIDARC1381: 4400 case PCIDevVenIDARC1680: 4401 case PCIDevVenIDARC1681: 4402 type = "SAS 3G"; 4403 break; 4404 case PCIDevVenIDARC1880: 4405 case PCIDevVenIDARC1882: 4406 case PCIDevVenIDARC1213: 4407 case PCIDevVenIDARC1223: 4408 type = "SAS 6G"; 4409 break; 4410 case PCIDevVenIDARC1214: 4411 type = "SATA 6G"; 4412 break; 4413 default: 4414 type = x_type; 4415 break; 4416 } 4417 if(type == x_type) 4418 return(ENXIO); 4419 sprintf(buf, "Areca %s Host Adapter RAID Controller %s\n", type, raid6 ? "(RAID6 capable)" : ""); 4420 device_set_desc_copy(dev, buf); 4421 return (BUS_PROBE_DEFAULT); 4422 } 4423 /* 4424 ************************************************************************ 4425 ************************************************************************ 4426 */ 4427 static int arcmsr_shutdown(device_t dev) 4428 { 4429 u_int32_t i; 4430 u_int32_t intmask_org; 4431 struct CommandControlBlock *srb; 4432 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 4433 4434 /* stop adapter background rebuild */ 4435 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 4436 /* disable all outbound interrupt */ 4437 intmask_org = arcmsr_disable_allintr(acb); 4438 arcmsr_stop_adapter_bgrb(acb); 4439 arcmsr_flush_adapter_cache(acb); 4440 /* abort all outstanding command */ 4441 acb->acb_flags |= ACB_F_SCSISTOPADAPTER; 4442 acb->acb_flags &= ~ACB_F_IOP_INITED; 4443 if(acb->srboutstandingcount != 0) { 4444 /*clear and abort all outbound posted Q*/ 4445 arcmsr_done4abort_postqueue(acb); 4446 /* talk to iop 331 outstanding command aborted*/ 4447 arcmsr_abort_allcmd(acb); 4448 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 4449 srb = acb->psrb_pool[i]; 4450 if(srb->srb_state == ARCMSR_SRB_START) { 4451 srb->srb_state = ARCMSR_SRB_ABORTED; 4452 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 4453 arcmsr_srb_complete(srb, 1); 4454 } 4455 } 4456 } 4457 acb->srboutstandingcount = 0; 4458 acb->workingsrb_doneindex = 0; 4459 acb->workingsrb_startindex = 0; 4460 acb->pktRequestCount = 0; 4461 acb->pktReturnCount = 0; 4462 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 4463 return (0); 4464 } 4465 /* 4466 ************************************************************************ 4467 ************************************************************************ 4468 */ 4469 static int arcmsr_detach(device_t dev) 4470 { 4471 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 4472 int i; 4473 4474 callout_stop(&acb->devmap_callout); 4475 bus_teardown_intr(dev, acb->irqres, acb->ih); 4476 arcmsr_shutdown(dev); 4477 arcmsr_free_resource(acb); 4478 for(i=0; (acb->sys_res_arcmsr[i]!=NULL) && (i<2); i++) { 4479 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(i), acb->sys_res_arcmsr[i]); 4480 } 4481 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres); 4482 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 4483 xpt_async(AC_LOST_DEVICE, acb->ppath, NULL); 4484 xpt_free_path(acb->ppath); 4485 xpt_bus_deregister(cam_sim_path(acb->psim)); 4486 cam_sim_free(acb->psim, TRUE); 4487 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 4488 arcmsr_mutex_destroy(acb); 4489 return (0); 4490 } 4491 4492 #ifdef ARCMSR_DEBUG1 4493 static void arcmsr_dump_data(struct AdapterControlBlock *acb) 4494 { 4495 if((acb->pktRequestCount - acb->pktReturnCount) == 0) 4496 return; 4497 printf("Command Request Count =0x%x\n",acb->pktRequestCount); 4498 printf("Command Return Count =0x%x\n",acb->pktReturnCount); 4499 printf("Command (Req-Rtn) Count =0x%x\n",(acb->pktRequestCount - acb->pktReturnCount)); 4500 printf("Queued Command Count =0x%x\n",acb->srboutstandingcount); 4501 } 4502 #endif 4503 4504