1 /* 2 ******************************************************************************** 3 ** OS : FreeBSD 4 ** FILE NAME : arcmsr.c 5 ** BY : Erich Chen, Ching Huang 6 ** Description: SCSI RAID Device Driver for 7 ** ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x) 8 ** SATA/SAS RAID HOST Adapter 9 ******************************************************************************** 10 ******************************************************************************** 11 ** 12 ** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved. 13 ** 14 ** Redistribution and use in source and binary forms, with or without 15 ** modification, are permitted provided that the following conditions 16 ** are met: 17 ** 1. Redistributions of source code must retain the above copyright 18 ** notice, this list of conditions and the following disclaimer. 19 ** 2. Redistributions in binary form must reproduce the above copyright 20 ** notice, this list of conditions and the following disclaimer in the 21 ** documentation and/or other materials provided with the distribution. 22 ** 3. The name of the author may not be used to endorse or promote products 23 ** derived from this software without specific prior written permission. 24 ** 25 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 26 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 27 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 28 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 29 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT 30 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 31 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY 32 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 33 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF 34 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 35 ******************************************************************************** 36 ** History 37 ** 38 ** REV# DATE NAME DESCRIPTION 39 ** 1.00.00.00 03/31/2004 Erich Chen First release 40 ** 1.20.00.02 11/29/2004 Erich Chen bug fix with arcmsr_bus_reset when PHY error 41 ** 1.20.00.03 04/19/2005 Erich Chen add SATA 24 Ports adapter type support 42 ** clean unused function 43 ** 1.20.00.12 09/12/2005 Erich Chen bug fix with abort command handling, 44 ** firmware version check 45 ** and firmware update notify for hardware bug fix 46 ** handling if none zero high part physical address 47 ** of srb resource 48 ** 1.20.00.13 08/18/2006 Erich Chen remove pending srb and report busy 49 ** add iop message xfer 50 ** with scsi pass-through command 51 ** add new device id of sas raid adapters 52 ** code fit for SPARC64 & PPC 53 ** 1.20.00.14 02/05/2007 Erich Chen bug fix for incorrect ccb_h.status report 54 ** and cause g_vfs_done() read write error 55 ** 1.20.00.15 10/10/2007 Erich Chen support new RAID adapter type ARC120x 56 ** 1.20.00.16 10/10/2009 Erich Chen Bug fix for RAID adapter type ARC120x 57 ** bus_dmamem_alloc() with BUS_DMA_ZERO 58 ** 1.20.00.17 07/15/2010 Ching Huang Added support ARC1880 59 ** report CAM_DEV_NOT_THERE instead of CAM_SEL_TIMEOUT when device failed, 60 ** prevent cam_periph_error removing all LUN devices of one Target id 61 ** for any one LUN device failed 62 ** 1.20.00.18 10/14/2010 Ching Huang Fixed "inquiry data fails comparion at DV1 step" 63 ** 10/25/2010 Ching Huang Fixed bad range input in bus_alloc_resource for ADAPTER_TYPE_B 64 ** 1.20.00.19 11/11/2010 Ching Huang Fixed arcmsr driver prevent arcsas support for Areca SAS HBA ARC13x0 65 ** 1.20.00.20 12/08/2010 Ching Huang Avoid calling atomic_set_int function 66 ** 1.20.00.21 02/08/2011 Ching Huang Implement I/O request timeout 67 ** 02/14/2011 Ching Huang Modified pktRequestCount 68 ** 1.20.00.21 03/03/2011 Ching Huang if a command timeout, then wait its ccb back before free it 69 ** 1.20.00.22 07/04/2011 Ching Huang Fixed multiple MTX panic 70 ** 1.20.00.23 10/28/2011 Ching Huang Added TIMEOUT_DELAY in case of too many HDDs need to start 71 ** 1.20.00.23 11/08/2011 Ching Huang Added report device transfer speed 72 ** 1.20.00.23 01/30/2012 Ching Huang Fixed Request requeued and Retrying command 73 ** 1.20.00.24 06/11/2012 Ching Huang Fixed return sense data condition 74 ** 1.20.00.25 08/17/2012 Ching Huang Fixed hotplug device no function on type A adapter 75 ** 1.20.00.26 12/14/2012 Ching Huang Added support ARC1214,1224,1264,1284 76 ** 1.20.00.27 05/06/2013 Ching Huang Fixed out standing cmd full on ARC-12x4 77 ** 1.20.00.28 09/13/2013 Ching Huang Removed recursive mutex in arcmsr_abort_dr_ccbs 78 ** 1.20.00.29 12/18/2013 Ching Huang Change simq allocation number, support ARC1883 79 ****************************************************************************************** 80 */ 81 82 #include <sys/cdefs.h> 83 __FBSDID("$FreeBSD$"); 84 85 #if 0 86 #define ARCMSR_DEBUG1 1 87 #endif 88 #include <sys/param.h> 89 #include <sys/systm.h> 90 #include <sys/malloc.h> 91 #include <sys/kernel.h> 92 #include <sys/bus.h> 93 #include <sys/queue.h> 94 #include <sys/stat.h> 95 #include <sys/devicestat.h> 96 #include <sys/kthread.h> 97 #include <sys/module.h> 98 #include <sys/proc.h> 99 #include <sys/lock.h> 100 #include <sys/sysctl.h> 101 #include <sys/poll.h> 102 #include <sys/ioccom.h> 103 #include <vm/vm.h> 104 #include <vm/vm_param.h> 105 #include <vm/pmap.h> 106 107 #include <isa/rtc.h> 108 109 #include <machine/bus.h> 110 #include <machine/resource.h> 111 #include <machine/atomic.h> 112 #include <sys/conf.h> 113 #include <sys/rman.h> 114 115 #include <cam/cam.h> 116 #include <cam/cam_ccb.h> 117 #include <cam/cam_sim.h> 118 #include <cam/cam_periph.h> 119 #include <cam/cam_xpt_periph.h> 120 #include <cam/cam_xpt_sim.h> 121 #include <cam/cam_debug.h> 122 #include <cam/scsi/scsi_all.h> 123 #include <cam/scsi/scsi_message.h> 124 /* 125 ************************************************************************** 126 ************************************************************************** 127 */ 128 #if __FreeBSD_version >= 500005 129 #include <sys/selinfo.h> 130 #include <sys/mutex.h> 131 #include <sys/endian.h> 132 #include <dev/pci/pcivar.h> 133 #include <dev/pci/pcireg.h> 134 #else 135 #include <sys/select.h> 136 #include <pci/pcivar.h> 137 #include <pci/pcireg.h> 138 #endif 139 140 #if !defined(CAM_NEW_TRAN_CODE) && __FreeBSD_version >= 700025 141 #define CAM_NEW_TRAN_CODE 1 142 #endif 143 144 #if __FreeBSD_version > 500000 145 #define arcmsr_callout_init(a) callout_init(a, /*mpsafe*/1); 146 #else 147 #define arcmsr_callout_init(a) callout_init(a); 148 #endif 149 150 #define ARCMSR_DRIVER_VERSION "arcmsr version 1.20.00.29 2013-12-18" 151 #include <dev/arcmsr/arcmsr.h> 152 /* 153 ************************************************************************** 154 ************************************************************************** 155 */ 156 static void arcmsr_free_srb(struct CommandControlBlock *srb); 157 static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb); 158 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb); 159 static int arcmsr_probe(device_t dev); 160 static int arcmsr_attach(device_t dev); 161 static int arcmsr_detach(device_t dev); 162 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg); 163 static void arcmsr_iop_parking(struct AdapterControlBlock *acb); 164 static int arcmsr_shutdown(device_t dev); 165 static void arcmsr_interrupt(struct AdapterControlBlock *acb); 166 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb); 167 static void arcmsr_free_resource(struct AdapterControlBlock *acb); 168 static void arcmsr_bus_reset(struct AdapterControlBlock *acb); 169 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb); 170 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb); 171 static void arcmsr_iop_init(struct AdapterControlBlock *acb); 172 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb); 173 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, struct QBUFFER *prbuffer); 174 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb); 175 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb); 176 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag); 177 static void arcmsr_iop_reset(struct AdapterControlBlock *acb); 178 static void arcmsr_report_sense_info(struct CommandControlBlock *srb); 179 static void arcmsr_build_srb(struct CommandControlBlock *srb, bus_dma_segment_t *dm_segs, u_int32_t nseg); 180 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb); 181 static int arcmsr_resume(device_t dev); 182 static int arcmsr_suspend(device_t dev); 183 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb); 184 static void arcmsr_polling_devmap(void *arg); 185 static void arcmsr_srb_timeout(void *arg); 186 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb); 187 #ifdef ARCMSR_DEBUG1 188 static void arcmsr_dump_data(struct AdapterControlBlock *acb); 189 #endif 190 /* 191 ************************************************************************** 192 ************************************************************************** 193 */ 194 static void UDELAY(u_int32_t us) { DELAY(us); } 195 /* 196 ************************************************************************** 197 ************************************************************************** 198 */ 199 static bus_dmamap_callback_t arcmsr_map_free_srb; 200 static bus_dmamap_callback_t arcmsr_execute_srb; 201 /* 202 ************************************************************************** 203 ************************************************************************** 204 */ 205 static d_open_t arcmsr_open; 206 static d_close_t arcmsr_close; 207 static d_ioctl_t arcmsr_ioctl; 208 209 static device_method_t arcmsr_methods[]={ 210 DEVMETHOD(device_probe, arcmsr_probe), 211 DEVMETHOD(device_attach, arcmsr_attach), 212 DEVMETHOD(device_detach, arcmsr_detach), 213 DEVMETHOD(device_shutdown, arcmsr_shutdown), 214 DEVMETHOD(device_suspend, arcmsr_suspend), 215 DEVMETHOD(device_resume, arcmsr_resume), 216 217 #if __FreeBSD_version >= 803000 218 DEVMETHOD_END 219 #else 220 { 0, 0 } 221 #endif 222 }; 223 224 static driver_t arcmsr_driver={ 225 "arcmsr", arcmsr_methods, sizeof(struct AdapterControlBlock) 226 }; 227 228 static devclass_t arcmsr_devclass; 229 DRIVER_MODULE(arcmsr, pci, arcmsr_driver, arcmsr_devclass, 0, 0); 230 MODULE_DEPEND(arcmsr, pci, 1, 1, 1); 231 MODULE_DEPEND(arcmsr, cam, 1, 1, 1); 232 #ifndef BUS_DMA_COHERENT 233 #define BUS_DMA_COHERENT 0x04 /* hint: map memory in a coherent way */ 234 #endif 235 #if __FreeBSD_version >= 501000 236 static struct cdevsw arcmsr_cdevsw={ 237 #if __FreeBSD_version >= 503000 238 .d_version = D_VERSION, 239 #endif 240 #if (__FreeBSD_version>=503000 && __FreeBSD_version<600034) 241 .d_flags = D_NEEDGIANT, 242 #endif 243 .d_open = arcmsr_open, /* open */ 244 .d_close = arcmsr_close, /* close */ 245 .d_ioctl = arcmsr_ioctl, /* ioctl */ 246 .d_name = "arcmsr", /* name */ 247 }; 248 #else 249 #define ARCMSR_CDEV_MAJOR 180 250 251 static struct cdevsw arcmsr_cdevsw = { 252 arcmsr_open, /* open */ 253 arcmsr_close, /* close */ 254 noread, /* read */ 255 nowrite, /* write */ 256 arcmsr_ioctl, /* ioctl */ 257 nopoll, /* poll */ 258 nommap, /* mmap */ 259 nostrategy, /* strategy */ 260 "arcmsr", /* name */ 261 ARCMSR_CDEV_MAJOR, /* major */ 262 nodump, /* dump */ 263 nopsize, /* psize */ 264 0 /* flags */ 265 }; 266 #endif 267 /* 268 ************************************************************************** 269 ************************************************************************** 270 */ 271 #if __FreeBSD_version < 500005 272 static int arcmsr_open(dev_t dev, int flags, int fmt, struct proc *proc) 273 #else 274 #if __FreeBSD_version < 503000 275 static int arcmsr_open(dev_t dev, int flags, int fmt, struct thread *proc) 276 #else 277 static int arcmsr_open(struct cdev *dev, int flags, int fmt, struct thread *proc) 278 #endif 279 #endif 280 { 281 #if __FreeBSD_version < 503000 282 struct AdapterControlBlock *acb = dev->si_drv1; 283 #else 284 int unit = dev2unit(dev); 285 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit); 286 #endif 287 if(acb == NULL) { 288 return ENXIO; 289 } 290 return (0); 291 } 292 /* 293 ************************************************************************** 294 ************************************************************************** 295 */ 296 #if __FreeBSD_version < 500005 297 static int arcmsr_close(dev_t dev, int flags, int fmt, struct proc *proc) 298 #else 299 #if __FreeBSD_version < 503000 300 static int arcmsr_close(dev_t dev, int flags, int fmt, struct thread *proc) 301 #else 302 static int arcmsr_close(struct cdev *dev, int flags, int fmt, struct thread *proc) 303 #endif 304 #endif 305 { 306 #if __FreeBSD_version < 503000 307 struct AdapterControlBlock *acb = dev->si_drv1; 308 #else 309 int unit = dev2unit(dev); 310 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit); 311 #endif 312 if(acb == NULL) { 313 return ENXIO; 314 } 315 return 0; 316 } 317 /* 318 ************************************************************************** 319 ************************************************************************** 320 */ 321 #if __FreeBSD_version < 500005 322 static int arcmsr_ioctl(dev_t dev, u_long ioctl_cmd, caddr_t arg, int flags, struct proc *proc) 323 #else 324 #if __FreeBSD_version < 503000 325 static int arcmsr_ioctl(dev_t dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc) 326 #else 327 static int arcmsr_ioctl(struct cdev *dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc) 328 #endif 329 #endif 330 { 331 #if __FreeBSD_version < 503000 332 struct AdapterControlBlock *acb = dev->si_drv1; 333 #else 334 int unit = dev2unit(dev); 335 struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit); 336 #endif 337 338 if(acb == NULL) { 339 return ENXIO; 340 } 341 return (arcmsr_iop_ioctlcmd(acb, ioctl_cmd, arg)); 342 } 343 /* 344 ********************************************************************** 345 ********************************************************************** 346 */ 347 static u_int32_t arcmsr_disable_allintr( struct AdapterControlBlock *acb) 348 { 349 u_int32_t intmask_org = 0; 350 351 switch (acb->adapter_type) { 352 case ACB_ADAPTER_TYPE_A: { 353 /* disable all outbound interrupt */ 354 intmask_org = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intmask); /* disable outbound message0 int */ 355 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE); 356 } 357 break; 358 case ACB_ADAPTER_TYPE_B: { 359 /* disable all outbound interrupt */ 360 intmask_org = CHIP_REG_READ32(HBB_DOORBELL, 361 0, iop2drv_doorbell_mask) & (~ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); /* disable outbound message0 int */ 362 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell_mask, 0); /* disable all interrupt */ 363 } 364 break; 365 case ACB_ADAPTER_TYPE_C: { 366 /* disable all outbound interrupt */ 367 intmask_org = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask) ; /* disable outbound message0 int */ 368 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE); 369 } 370 break; 371 case ACB_ADAPTER_TYPE_D: { 372 /* disable all outbound interrupt */ 373 intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable) ; /* disable outbound message0 int */ 374 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE); 375 } 376 break; 377 } 378 return (intmask_org); 379 } 380 /* 381 ********************************************************************** 382 ********************************************************************** 383 */ 384 static void arcmsr_enable_allintr( struct AdapterControlBlock *acb, u_int32_t intmask_org) 385 { 386 u_int32_t mask; 387 388 switch (acb->adapter_type) { 389 case ACB_ADAPTER_TYPE_A: { 390 /* enable outbound Post Queue, outbound doorbell Interrupt */ 391 mask = ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE|ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE); 392 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org & mask); 393 acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff; 394 } 395 break; 396 case ACB_ADAPTER_TYPE_B: { 397 /* enable ARCMSR_IOP2DRV_MESSAGE_CMD_DONE */ 398 mask = (ARCMSR_IOP2DRV_DATA_WRITE_OK|ARCMSR_IOP2DRV_DATA_READ_OK|ARCMSR_IOP2DRV_CDB_DONE|ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); 399 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell_mask, intmask_org | mask); /*1=interrupt enable, 0=interrupt disable*/ 400 acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f; 401 } 402 break; 403 case ACB_ADAPTER_TYPE_C: { 404 /* enable outbound Post Queue, outbound doorbell Interrupt */ 405 mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK); 406 CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org & mask); 407 acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f; 408 } 409 break; 410 case ACB_ADAPTER_TYPE_D: { 411 /* enable outbound Post Queue, outbound doorbell Interrupt */ 412 mask = ARCMSR_HBDMU_ALL_INT_ENABLE; 413 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | mask); 414 CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); 415 acb->outbound_int_enable = mask; 416 } 417 break; 418 } 419 } 420 /* 421 ********************************************************************** 422 ********************************************************************** 423 */ 424 static u_int8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb) 425 { 426 u_int32_t Index; 427 u_int8_t Retries = 0x00; 428 429 do { 430 for(Index=0; Index < 100; Index++) { 431 if(CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { 432 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);/*clear interrupt*/ 433 return TRUE; 434 } 435 UDELAY(10000); 436 }/*max 1 seconds*/ 437 }while(Retries++ < 20);/*max 20 sec*/ 438 return (FALSE); 439 } 440 /* 441 ********************************************************************** 442 ********************************************************************** 443 */ 444 static u_int8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb) 445 { 446 u_int32_t Index; 447 u_int8_t Retries = 0x00; 448 449 do { 450 for(Index=0; Index < 100; Index++) { 451 if(CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) { 452 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt*/ 453 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 454 return TRUE; 455 } 456 UDELAY(10000); 457 }/*max 1 seconds*/ 458 }while(Retries++ < 20);/*max 20 sec*/ 459 return (FALSE); 460 } 461 /* 462 ********************************************************************** 463 ********************************************************************** 464 */ 465 static u_int8_t arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock *acb) 466 { 467 u_int32_t Index; 468 u_int8_t Retries = 0x00; 469 470 do { 471 for(Index=0; Index < 100; Index++) { 472 if(CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 473 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);/*clear interrupt*/ 474 return TRUE; 475 } 476 UDELAY(10000); 477 }/*max 1 seconds*/ 478 }while(Retries++ < 20);/*max 20 sec*/ 479 return (FALSE); 480 } 481 /* 482 ********************************************************************** 483 ********************************************************************** 484 */ 485 static u_int8_t arcmsr_hbd_wait_msgint_ready(struct AdapterControlBlock *acb) 486 { 487 u_int32_t Index; 488 u_int8_t Retries = 0x00; 489 490 do { 491 for(Index=0; Index < 100; Index++) { 492 if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) { 493 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);/*clear interrupt*/ 494 return TRUE; 495 } 496 UDELAY(10000); 497 }/*max 1 seconds*/ 498 }while(Retries++ < 20);/*max 20 sec*/ 499 return (FALSE); 500 } 501 /* 502 ************************************************************************ 503 ************************************************************************ 504 */ 505 static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb) 506 { 507 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 508 509 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 510 do { 511 if(arcmsr_hba_wait_msgint_ready(acb)) { 512 break; 513 } else { 514 retry_count--; 515 } 516 }while(retry_count != 0); 517 } 518 /* 519 ************************************************************************ 520 ************************************************************************ 521 */ 522 static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb) 523 { 524 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 525 526 CHIP_REG_WRITE32(HBB_DOORBELL, 527 0, drv2iop_doorbell, ARCMSR_MESSAGE_FLUSH_CACHE); 528 do { 529 if(arcmsr_hbb_wait_msgint_ready(acb)) { 530 break; 531 } else { 532 retry_count--; 533 } 534 }while(retry_count != 0); 535 } 536 /* 537 ************************************************************************ 538 ************************************************************************ 539 */ 540 static void arcmsr_flush_hbc_cache(struct AdapterControlBlock *acb) 541 { 542 int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */ 543 544 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 545 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 546 do { 547 if(arcmsr_hbc_wait_msgint_ready(acb)) { 548 break; 549 } else { 550 retry_count--; 551 } 552 }while(retry_count != 0); 553 } 554 /* 555 ************************************************************************ 556 ************************************************************************ 557 */ 558 static void arcmsr_flush_hbd_cache(struct AdapterControlBlock *acb) 559 { 560 int retry_count = 30; /* enlarge wait flush adapter cache time: 10 minute */ 561 562 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE); 563 do { 564 if(arcmsr_hbd_wait_msgint_ready(acb)) { 565 break; 566 } else { 567 retry_count--; 568 } 569 }while(retry_count != 0); 570 } 571 /* 572 ************************************************************************ 573 ************************************************************************ 574 */ 575 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb) 576 { 577 switch (acb->adapter_type) { 578 case ACB_ADAPTER_TYPE_A: { 579 arcmsr_flush_hba_cache(acb); 580 } 581 break; 582 case ACB_ADAPTER_TYPE_B: { 583 arcmsr_flush_hbb_cache(acb); 584 } 585 break; 586 case ACB_ADAPTER_TYPE_C: { 587 arcmsr_flush_hbc_cache(acb); 588 } 589 break; 590 case ACB_ADAPTER_TYPE_D: { 591 arcmsr_flush_hbd_cache(acb); 592 } 593 break; 594 } 595 } 596 /* 597 ******************************************************************************* 598 ******************************************************************************* 599 */ 600 static int arcmsr_suspend(device_t dev) 601 { 602 struct AdapterControlBlock *acb = device_get_softc(dev); 603 604 /* flush controller */ 605 arcmsr_iop_parking(acb); 606 /* disable all outbound interrupt */ 607 arcmsr_disable_allintr(acb); 608 return(0); 609 } 610 /* 611 ******************************************************************************* 612 ******************************************************************************* 613 */ 614 static int arcmsr_resume(device_t dev) 615 { 616 struct AdapterControlBlock *acb = device_get_softc(dev); 617 618 arcmsr_iop_init(acb); 619 return(0); 620 } 621 /* 622 ********************************************************************************* 623 ********************************************************************************* 624 */ 625 static void arcmsr_async(void *cb_arg, u_int32_t code, struct cam_path *path, void *arg) 626 { 627 struct AdapterControlBlock *acb; 628 u_int8_t target_id, target_lun; 629 struct cam_sim *sim; 630 631 sim = (struct cam_sim *) cb_arg; 632 acb =(struct AdapterControlBlock *) cam_sim_softc(sim); 633 switch (code) { 634 case AC_LOST_DEVICE: 635 target_id = xpt_path_target_id(path); 636 target_lun = xpt_path_lun_id(path); 637 if((target_id > ARCMSR_MAX_TARGETID) || (target_lun > ARCMSR_MAX_TARGETLUN)) { 638 break; 639 } 640 // printf("%s:scsi id=%d lun=%d device lost \n", device_get_name(acb->pci_dev), target_id, target_lun); 641 break; 642 default: 643 break; 644 } 645 } 646 /* 647 ********************************************************************** 648 ********************************************************************** 649 */ 650 static void arcmsr_report_sense_info(struct CommandControlBlock *srb) 651 { 652 union ccb *pccb = srb->pccb; 653 654 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 655 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 656 if(pccb->csio.sense_len) { 657 memset(&pccb->csio.sense_data, 0, sizeof(pccb->csio.sense_data)); 658 memcpy(&pccb->csio.sense_data, srb->arcmsr_cdb.SenseData, 659 get_min(sizeof(struct SENSE_DATA), sizeof(pccb->csio.sense_data))); 660 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); /* Valid,ErrorCode */ 661 pccb->ccb_h.status |= CAM_AUTOSNS_VALID; 662 } 663 } 664 /* 665 ********************************************************************* 666 ********************************************************************* 667 */ 668 static void arcmsr_abort_hba_allcmd(struct AdapterControlBlock *acb) 669 { 670 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 671 if(!arcmsr_hba_wait_msgint_ready(acb)) { 672 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 673 } 674 } 675 /* 676 ********************************************************************* 677 ********************************************************************* 678 */ 679 static void arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb) 680 { 681 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_ABORT_CMD); 682 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 683 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 684 } 685 } 686 /* 687 ********************************************************************* 688 ********************************************************************* 689 */ 690 static void arcmsr_abort_hbc_allcmd(struct AdapterControlBlock *acb) 691 { 692 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 693 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 694 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 695 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 696 } 697 } 698 /* 699 ********************************************************************* 700 ********************************************************************* 701 */ 702 static void arcmsr_abort_hbd_allcmd(struct AdapterControlBlock *acb) 703 { 704 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD); 705 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 706 printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit); 707 } 708 } 709 /* 710 ********************************************************************* 711 ********************************************************************* 712 */ 713 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb) 714 { 715 switch (acb->adapter_type) { 716 case ACB_ADAPTER_TYPE_A: { 717 arcmsr_abort_hba_allcmd(acb); 718 } 719 break; 720 case ACB_ADAPTER_TYPE_B: { 721 arcmsr_abort_hbb_allcmd(acb); 722 } 723 break; 724 case ACB_ADAPTER_TYPE_C: { 725 arcmsr_abort_hbc_allcmd(acb); 726 } 727 break; 728 case ACB_ADAPTER_TYPE_D: { 729 arcmsr_abort_hbd_allcmd(acb); 730 } 731 break; 732 } 733 } 734 /* 735 ********************************************************************** 736 ********************************************************************** 737 */ 738 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag) 739 { 740 struct AdapterControlBlock *acb = srb->acb; 741 union ccb *pccb = srb->pccb; 742 743 if(srb->srb_flags & SRB_FLAG_TIMER_START) 744 callout_stop(&srb->ccb_callout); 745 if((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) { 746 bus_dmasync_op_t op; 747 748 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 749 op = BUS_DMASYNC_POSTREAD; 750 } else { 751 op = BUS_DMASYNC_POSTWRITE; 752 } 753 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op); 754 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap); 755 } 756 if(stand_flag == 1) { 757 atomic_subtract_int(&acb->srboutstandingcount, 1); 758 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) && ( 759 acb->srboutstandingcount < (acb->maxOutstanding -10))) { 760 acb->acb_flags &= ~ACB_F_CAM_DEV_QFRZN; 761 pccb->ccb_h.status |= CAM_RELEASE_SIMQ; 762 } 763 } 764 if(srb->srb_state != ARCMSR_SRB_TIMEOUT) 765 arcmsr_free_srb(srb); 766 acb->pktReturnCount++; 767 xpt_done(pccb); 768 } 769 /* 770 ************************************************************************** 771 ************************************************************************** 772 */ 773 static void arcmsr_report_srb_state(struct AdapterControlBlock *acb, struct CommandControlBlock *srb, u_int16_t error) 774 { 775 int target, lun; 776 777 target = srb->pccb->ccb_h.target_id; 778 lun = srb->pccb->ccb_h.target_lun; 779 if(error == FALSE) { 780 if(acb->devstate[target][lun] == ARECA_RAID_GONE) { 781 acb->devstate[target][lun] = ARECA_RAID_GOOD; 782 } 783 srb->pccb->ccb_h.status |= CAM_REQ_CMP; 784 arcmsr_srb_complete(srb, 1); 785 } else { 786 switch(srb->arcmsr_cdb.DeviceStatus) { 787 case ARCMSR_DEV_SELECT_TIMEOUT: { 788 if(acb->devstate[target][lun] == ARECA_RAID_GOOD) { 789 printf( "arcmsr%d: Target=%x, Lun=%x, selection timeout, raid volume was lost\n", acb->pci_unit, target, lun); 790 } 791 acb->devstate[target][lun] = ARECA_RAID_GONE; 792 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 793 arcmsr_srb_complete(srb, 1); 794 } 795 break; 796 case ARCMSR_DEV_ABORTED: 797 case ARCMSR_DEV_INIT_FAIL: { 798 acb->devstate[target][lun] = ARECA_RAID_GONE; 799 srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 800 arcmsr_srb_complete(srb, 1); 801 } 802 break; 803 case SCSISTAT_CHECK_CONDITION: { 804 acb->devstate[target][lun] = ARECA_RAID_GOOD; 805 arcmsr_report_sense_info(srb); 806 arcmsr_srb_complete(srb, 1); 807 } 808 break; 809 default: 810 printf("arcmsr%d: scsi id=%d lun=%d isr got command error done,but got unknown DeviceStatus=0x%x \n" 811 , acb->pci_unit, target, lun ,srb->arcmsr_cdb.DeviceStatus); 812 acb->devstate[target][lun] = ARECA_RAID_GONE; 813 srb->pccb->ccb_h.status |= CAM_UNCOR_PARITY; 814 /*unknown error or crc error just for retry*/ 815 arcmsr_srb_complete(srb, 1); 816 break; 817 } 818 } 819 } 820 /* 821 ************************************************************************** 822 ************************************************************************** 823 */ 824 static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, u_int32_t flag_srb, u_int16_t error) 825 { 826 struct CommandControlBlock *srb; 827 828 /* check if command done with no error*/ 829 switch (acb->adapter_type) { 830 case ACB_ADAPTER_TYPE_C: 831 case ACB_ADAPTER_TYPE_D: 832 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0)); /*frame must be 32 bytes aligned*/ 833 break; 834 case ACB_ADAPTER_TYPE_A: 835 case ACB_ADAPTER_TYPE_B: 836 default: 837 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 838 break; 839 } 840 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 841 if(srb->srb_state == ARCMSR_SRB_TIMEOUT) { 842 arcmsr_free_srb(srb); 843 printf("arcmsr%d: srb='%p' return srb has been timeouted\n", acb->pci_unit, srb); 844 return; 845 } 846 printf("arcmsr%d: return srb has been completed\n" 847 "srb='%p' srb_state=0x%x outstanding srb count=%d \n", 848 acb->pci_unit, srb, srb->srb_state, acb->srboutstandingcount); 849 return; 850 } 851 arcmsr_report_srb_state(acb, srb, error); 852 } 853 /* 854 ************************************************************************** 855 ************************************************************************** 856 */ 857 static void arcmsr_srb_timeout(void *arg) 858 { 859 struct CommandControlBlock *srb = (struct CommandControlBlock *)arg; 860 struct AdapterControlBlock *acb; 861 int target, lun; 862 u_int8_t cmd; 863 864 target = srb->pccb->ccb_h.target_id; 865 lun = srb->pccb->ccb_h.target_lun; 866 acb = srb->acb; 867 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 868 if(srb->srb_state == ARCMSR_SRB_START) 869 { 870 cmd = srb->pccb->csio.cdb_io.cdb_bytes[0]; 871 srb->srb_state = ARCMSR_SRB_TIMEOUT; 872 srb->pccb->ccb_h.status |= CAM_CMD_TIMEOUT; 873 arcmsr_srb_complete(srb, 1); 874 printf("arcmsr%d: scsi id %d lun %d cmd=0x%x srb='%p' ccb command time out!\n", 875 acb->pci_unit, target, lun, cmd, srb); 876 } 877 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 878 #ifdef ARCMSR_DEBUG1 879 arcmsr_dump_data(acb); 880 #endif 881 } 882 883 /* 884 ********************************************************************** 885 ********************************************************************** 886 */ 887 static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb) 888 { 889 int i=0; 890 u_int32_t flag_srb; 891 u_int16_t error; 892 893 switch (acb->adapter_type) { 894 case ACB_ADAPTER_TYPE_A: { 895 u_int32_t outbound_intstatus; 896 897 /*clear and abort all outbound posted Q*/ 898 outbound_intstatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 899 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);/*clear interrupt*/ 900 while(((flag_srb=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_queueport)) != 0xFFFFFFFF) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) { 901 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 902 arcmsr_drain_donequeue(acb, flag_srb, error); 903 } 904 } 905 break; 906 case ACB_ADAPTER_TYPE_B: { 907 struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu; 908 909 /*clear all outbound posted Q*/ 910 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */ 911 for(i=0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) { 912 if((flag_srb = phbbmu->done_qbuffer[i]) != 0) { 913 phbbmu->done_qbuffer[i] = 0; 914 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 915 arcmsr_drain_donequeue(acb, flag_srb, error); 916 } 917 phbbmu->post_qbuffer[i] = 0; 918 }/*drain reply FIFO*/ 919 phbbmu->doneq_index = 0; 920 phbbmu->postq_index = 0; 921 } 922 break; 923 case ACB_ADAPTER_TYPE_C: { 924 925 while((CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) { 926 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 927 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 928 arcmsr_drain_donequeue(acb, flag_srb, error); 929 } 930 } 931 break; 932 case ACB_ADAPTER_TYPE_D: { 933 arcmsr_hbd_postqueue_isr(acb); 934 } 935 break; 936 } 937 } 938 /* 939 **************************************************************************** 940 **************************************************************************** 941 */ 942 static void arcmsr_iop_reset(struct AdapterControlBlock *acb) 943 { 944 struct CommandControlBlock *srb; 945 u_int32_t intmask_org; 946 u_int32_t i=0; 947 948 if(acb->srboutstandingcount>0) { 949 /* disable all outbound interrupt */ 950 intmask_org = arcmsr_disable_allintr(acb); 951 /*clear and abort all outbound posted Q*/ 952 arcmsr_done4abort_postqueue(acb); 953 /* talk to iop 331 outstanding command aborted*/ 954 arcmsr_abort_allcmd(acb); 955 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 956 srb = acb->psrb_pool[i]; 957 if(srb->srb_state == ARCMSR_SRB_START) { 958 srb->srb_state = ARCMSR_SRB_ABORTED; 959 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 960 arcmsr_srb_complete(srb, 1); 961 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p' aborted\n" 962 , acb->pci_unit, srb->pccb->ccb_h.target_id 963 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 964 } 965 } 966 /* enable all outbound interrupt */ 967 arcmsr_enable_allintr(acb, intmask_org); 968 } 969 acb->srboutstandingcount = 0; 970 acb->workingsrb_doneindex = 0; 971 acb->workingsrb_startindex = 0; 972 acb->pktRequestCount = 0; 973 acb->pktReturnCount = 0; 974 } 975 /* 976 ********************************************************************** 977 ********************************************************************** 978 */ 979 static void arcmsr_build_srb(struct CommandControlBlock *srb, 980 bus_dma_segment_t *dm_segs, u_int32_t nseg) 981 { 982 struct ARCMSR_CDB *arcmsr_cdb = &srb->arcmsr_cdb; 983 u_int8_t *psge = (u_int8_t *)&arcmsr_cdb->u; 984 u_int32_t address_lo, address_hi; 985 union ccb *pccb = srb->pccb; 986 struct ccb_scsiio *pcsio = &pccb->csio; 987 u_int32_t arccdbsize = 0x30; 988 989 memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB)); 990 arcmsr_cdb->Bus = 0; 991 arcmsr_cdb->TargetID = pccb->ccb_h.target_id; 992 arcmsr_cdb->LUN = pccb->ccb_h.target_lun; 993 arcmsr_cdb->Function = 1; 994 arcmsr_cdb->CdbLength = (u_int8_t)pcsio->cdb_len; 995 bcopy(pcsio->cdb_io.cdb_bytes, arcmsr_cdb->Cdb, pcsio->cdb_len); 996 if(nseg != 0) { 997 struct AdapterControlBlock *acb = srb->acb; 998 bus_dmasync_op_t op; 999 u_int32_t length, i, cdb_sgcount = 0; 1000 1001 if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) { 1002 op = BUS_DMASYNC_PREREAD; 1003 } else { 1004 op = BUS_DMASYNC_PREWRITE; 1005 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE; 1006 srb->srb_flags |= SRB_FLAG_WRITE; 1007 } 1008 bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op); 1009 for(i=0; i < nseg; i++) { 1010 /* Get the physical address of the current data pointer */ 1011 length = arcmsr_htole32(dm_segs[i].ds_len); 1012 address_lo = arcmsr_htole32(dma_addr_lo32(dm_segs[i].ds_addr)); 1013 address_hi = arcmsr_htole32(dma_addr_hi32(dm_segs[i].ds_addr)); 1014 if(address_hi == 0) { 1015 struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge; 1016 pdma_sg->address = address_lo; 1017 pdma_sg->length = length; 1018 psge += sizeof(struct SG32ENTRY); 1019 arccdbsize += sizeof(struct SG32ENTRY); 1020 } else { 1021 u_int32_t sg64s_size = 0, tmplength = length; 1022 1023 while(1) { 1024 u_int64_t span4G, length0; 1025 struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge; 1026 1027 span4G = (u_int64_t)address_lo + tmplength; 1028 pdma_sg->addresshigh = address_hi; 1029 pdma_sg->address = address_lo; 1030 if(span4G > 0x100000000) { 1031 /*see if cross 4G boundary*/ 1032 length0 = 0x100000000-address_lo; 1033 pdma_sg->length = (u_int32_t)length0 | IS_SG64_ADDR; 1034 address_hi = address_hi+1; 1035 address_lo = 0; 1036 tmplength = tmplength - (u_int32_t)length0; 1037 sg64s_size += sizeof(struct SG64ENTRY); 1038 psge += sizeof(struct SG64ENTRY); 1039 cdb_sgcount++; 1040 } else { 1041 pdma_sg->length = tmplength | IS_SG64_ADDR; 1042 sg64s_size += sizeof(struct SG64ENTRY); 1043 psge += sizeof(struct SG64ENTRY); 1044 break; 1045 } 1046 } 1047 arccdbsize += sg64s_size; 1048 } 1049 cdb_sgcount++; 1050 } 1051 arcmsr_cdb->sgcount = (u_int8_t)cdb_sgcount; 1052 arcmsr_cdb->DataLength = pcsio->dxfer_len; 1053 if( arccdbsize > 256) { 1054 arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE; 1055 } 1056 } else { 1057 arcmsr_cdb->DataLength = 0; 1058 } 1059 srb->arc_cdb_size = arccdbsize; 1060 arcmsr_cdb->msgPages = (arccdbsize/256) + ((arccdbsize % 256) ? 1 : 0); 1061 } 1062 /* 1063 ************************************************************************** 1064 ************************************************************************** 1065 */ 1066 static void arcmsr_post_srb(struct AdapterControlBlock *acb, struct CommandControlBlock *srb) 1067 { 1068 u_int32_t cdb_phyaddr_low = (u_int32_t) srb->cdb_phyaddr_low; 1069 struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&srb->arcmsr_cdb; 1070 1071 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, (srb->srb_flags & SRB_FLAG_WRITE) ? BUS_DMASYNC_POSTWRITE:BUS_DMASYNC_POSTREAD); 1072 atomic_add_int(&acb->srboutstandingcount, 1); 1073 srb->srb_state = ARCMSR_SRB_START; 1074 1075 switch (acb->adapter_type) { 1076 case ACB_ADAPTER_TYPE_A: { 1077 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { 1078 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low|ARCMSR_SRBPOST_FLAG_SGL_BSIZE); 1079 } else { 1080 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low); 1081 } 1082 } 1083 break; 1084 case ACB_ADAPTER_TYPE_B: { 1085 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1086 int ending_index, index; 1087 1088 index = phbbmu->postq_index; 1089 ending_index = ((index+1) % ARCMSR_MAX_HBB_POSTQUEUE); 1090 phbbmu->post_qbuffer[ending_index] = 0; 1091 if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) { 1092 phbbmu->post_qbuffer[index] = cdb_phyaddr_low | ARCMSR_SRBPOST_FLAG_SGL_BSIZE; 1093 } else { 1094 phbbmu->post_qbuffer[index] = cdb_phyaddr_low; 1095 } 1096 index++; 1097 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 1098 phbbmu->postq_index = index; 1099 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_CDB_POSTED); 1100 } 1101 break; 1102 case ACB_ADAPTER_TYPE_C: { 1103 u_int32_t ccb_post_stamp, arc_cdb_size, cdb_phyaddr_hi32; 1104 1105 arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size; 1106 ccb_post_stamp = (cdb_phyaddr_low | ((arc_cdb_size-1) >> 6) | 1); 1107 cdb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high; 1108 if(cdb_phyaddr_hi32) 1109 { 1110 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_high, cdb_phyaddr_hi32); 1111 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp); 1112 } 1113 else 1114 { 1115 CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp); 1116 } 1117 } 1118 break; 1119 case ACB_ADAPTER_TYPE_D: { 1120 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1121 u_int16_t index_stripped; 1122 u_int16_t postq_index; 1123 struct InBound_SRB *pinbound_srb; 1124 1125 ARCMSR_LOCK_ACQUIRE(&acb->postDone_lock); 1126 postq_index = phbdmu->postq_index; 1127 pinbound_srb = (struct InBound_SRB *)&phbdmu->post_qbuffer[postq_index & 0xFF]; 1128 pinbound_srb->addressHigh = srb->cdb_phyaddr_high; 1129 pinbound_srb->addressLow = srb->cdb_phyaddr_low; 1130 pinbound_srb->length = srb->arc_cdb_size >> 2; 1131 arcmsr_cdb->Context = srb->cdb_phyaddr_low; 1132 if (postq_index & 0x4000) { 1133 index_stripped = postq_index & 0xFF; 1134 index_stripped += 1; 1135 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1136 phbdmu->postq_index = index_stripped ? (index_stripped | 0x4000) : index_stripped; 1137 } else { 1138 index_stripped = postq_index; 1139 index_stripped += 1; 1140 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1141 phbdmu->postq_index = index_stripped ? index_stripped : (index_stripped | 0x4000); 1142 } 1143 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inboundlist_write_pointer, postq_index); 1144 ARCMSR_LOCK_RELEASE(&acb->postDone_lock); 1145 } 1146 break; 1147 } 1148 } 1149 /* 1150 ************************************************************************ 1151 ************************************************************************ 1152 */ 1153 static struct QBUFFER *arcmsr_get_iop_rqbuffer( struct AdapterControlBlock *acb) 1154 { 1155 struct QBUFFER *qbuffer=NULL; 1156 1157 switch (acb->adapter_type) { 1158 case ACB_ADAPTER_TYPE_A: { 1159 struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu; 1160 1161 qbuffer = (struct QBUFFER *)&phbamu->message_rbuffer; 1162 } 1163 break; 1164 case ACB_ADAPTER_TYPE_B: { 1165 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1166 1167 qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_rbuffer; 1168 } 1169 break; 1170 case ACB_ADAPTER_TYPE_C: { 1171 struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu; 1172 1173 qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer; 1174 } 1175 break; 1176 case ACB_ADAPTER_TYPE_D: { 1177 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1178 1179 qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_rbuffer; 1180 } 1181 break; 1182 } 1183 return(qbuffer); 1184 } 1185 /* 1186 ************************************************************************ 1187 ************************************************************************ 1188 */ 1189 static struct QBUFFER *arcmsr_get_iop_wqbuffer( struct AdapterControlBlock *acb) 1190 { 1191 struct QBUFFER *qbuffer = NULL; 1192 1193 switch (acb->adapter_type) { 1194 case ACB_ADAPTER_TYPE_A: { 1195 struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu; 1196 1197 qbuffer = (struct QBUFFER *)&phbamu->message_wbuffer; 1198 } 1199 break; 1200 case ACB_ADAPTER_TYPE_B: { 1201 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1202 1203 qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_wbuffer; 1204 } 1205 break; 1206 case ACB_ADAPTER_TYPE_C: { 1207 struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu; 1208 1209 qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer; 1210 } 1211 break; 1212 case ACB_ADAPTER_TYPE_D: { 1213 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1214 1215 qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_wbuffer; 1216 } 1217 break; 1218 } 1219 return(qbuffer); 1220 } 1221 /* 1222 ************************************************************************** 1223 ************************************************************************** 1224 */ 1225 static void arcmsr_iop_message_read(struct AdapterControlBlock *acb) 1226 { 1227 switch (acb->adapter_type) { 1228 case ACB_ADAPTER_TYPE_A: { 1229 /* let IOP know data has been read */ 1230 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK); 1231 } 1232 break; 1233 case ACB_ADAPTER_TYPE_B: { 1234 /* let IOP know data has been read */ 1235 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK); 1236 } 1237 break; 1238 case ACB_ADAPTER_TYPE_C: { 1239 /* let IOP know data has been read */ 1240 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK); 1241 } 1242 break; 1243 case ACB_ADAPTER_TYPE_D: { 1244 /* let IOP know data has been read */ 1245 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ); 1246 } 1247 break; 1248 } 1249 } 1250 /* 1251 ************************************************************************** 1252 ************************************************************************** 1253 */ 1254 static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb) 1255 { 1256 switch (acb->adapter_type) { 1257 case ACB_ADAPTER_TYPE_A: { 1258 /* 1259 ** push inbound doorbell tell iop, driver data write ok 1260 ** and wait reply on next hwinterrupt for next Qbuffer post 1261 */ 1262 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK); 1263 } 1264 break; 1265 case ACB_ADAPTER_TYPE_B: { 1266 /* 1267 ** push inbound doorbell tell iop, driver data write ok 1268 ** and wait reply on next hwinterrupt for next Qbuffer post 1269 */ 1270 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_WRITE_OK); 1271 } 1272 break; 1273 case ACB_ADAPTER_TYPE_C: { 1274 /* 1275 ** push inbound doorbell tell iop, driver data write ok 1276 ** and wait reply on next hwinterrupt for next Qbuffer post 1277 */ 1278 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK); 1279 } 1280 break; 1281 case ACB_ADAPTER_TYPE_D: { 1282 /* 1283 ** push inbound doorbell tell iop, driver data write ok 1284 ** and wait reply on next hwinterrupt for next Qbuffer post 1285 */ 1286 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY); 1287 } 1288 break; 1289 } 1290 } 1291 /* 1292 ************************************************************************ 1293 ************************************************************************ 1294 */ 1295 static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb) 1296 { 1297 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1298 CHIP_REG_WRITE32(HBA_MessageUnit, 1299 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1300 if(!arcmsr_hba_wait_msgint_ready(acb)) { 1301 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n" 1302 , acb->pci_unit); 1303 } 1304 } 1305 /* 1306 ************************************************************************ 1307 ************************************************************************ 1308 */ 1309 static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb) 1310 { 1311 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1312 CHIP_REG_WRITE32(HBB_DOORBELL, 1313 0, drv2iop_doorbell, ARCMSR_MESSAGE_STOP_BGRB); 1314 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 1315 printf( "arcmsr%d: wait 'stop adapter background rebulid' timeout \n" 1316 , acb->pci_unit); 1317 } 1318 } 1319 /* 1320 ************************************************************************ 1321 ************************************************************************ 1322 */ 1323 static void arcmsr_stop_hbc_bgrb(struct AdapterControlBlock *acb) 1324 { 1325 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1326 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1327 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 1328 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 1329 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1330 } 1331 } 1332 /* 1333 ************************************************************************ 1334 ************************************************************************ 1335 */ 1336 static void arcmsr_stop_hbd_bgrb(struct AdapterControlBlock *acb) 1337 { 1338 acb->acb_flags &= ~ACB_F_MSG_START_BGRB; 1339 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB); 1340 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 1341 printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit); 1342 } 1343 } 1344 /* 1345 ************************************************************************ 1346 ************************************************************************ 1347 */ 1348 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb) 1349 { 1350 switch (acb->adapter_type) { 1351 case ACB_ADAPTER_TYPE_A: { 1352 arcmsr_stop_hba_bgrb(acb); 1353 } 1354 break; 1355 case ACB_ADAPTER_TYPE_B: { 1356 arcmsr_stop_hbb_bgrb(acb); 1357 } 1358 break; 1359 case ACB_ADAPTER_TYPE_C: { 1360 arcmsr_stop_hbc_bgrb(acb); 1361 } 1362 break; 1363 case ACB_ADAPTER_TYPE_D: { 1364 arcmsr_stop_hbd_bgrb(acb); 1365 } 1366 break; 1367 } 1368 } 1369 /* 1370 ************************************************************************ 1371 ************************************************************************ 1372 */ 1373 static void arcmsr_poll(struct cam_sim *psim) 1374 { 1375 struct AdapterControlBlock *acb; 1376 int mutex; 1377 1378 acb = (struct AdapterControlBlock *)cam_sim_softc(psim); 1379 mutex = mtx_owned(&acb->isr_lock); 1380 if( mutex == 0 ) 1381 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 1382 arcmsr_interrupt(acb); 1383 if( mutex == 0 ) 1384 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 1385 } 1386 /* 1387 ************************************************************************** 1388 ************************************************************************** 1389 */ 1390 static u_int32_t arcmsr_Read_iop_rqbuffer_data_D(struct AdapterControlBlock *acb, 1391 struct QBUFFER *prbuffer) { 1392 1393 u_int8_t *pQbuffer; 1394 u_int8_t *buf1 = 0; 1395 u_int32_t *iop_data, *buf2 = 0; 1396 u_int32_t iop_len, data_len; 1397 1398 iop_data = (u_int32_t *)prbuffer->data; 1399 iop_len = (u_int32_t)prbuffer->data_len; 1400 if ( iop_len > 0 ) 1401 { 1402 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO); 1403 buf2 = (u_int32_t *)buf1; 1404 if( buf1 == NULL) 1405 return (0); 1406 data_len = iop_len; 1407 while(data_len >= 4) 1408 { 1409 *buf2++ = *iop_data++; 1410 data_len -= 4; 1411 } 1412 if(data_len) 1413 *buf2 = *iop_data; 1414 buf2 = (u_int32_t *)buf1; 1415 } 1416 while (iop_len > 0) { 1417 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex]; 1418 *pQbuffer = *buf1; 1419 acb->rqbuf_lastindex++; 1420 /* if last, index number set it to 0 */ 1421 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 1422 buf1++; 1423 iop_len--; 1424 } 1425 if(buf2) 1426 free( (u_int8_t *)buf2, M_DEVBUF); 1427 /* let IOP know data has been read */ 1428 arcmsr_iop_message_read(acb); 1429 return (1); 1430 } 1431 /* 1432 ************************************************************************** 1433 ************************************************************************** 1434 */ 1435 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, 1436 struct QBUFFER *prbuffer) { 1437 1438 u_int8_t *pQbuffer; 1439 u_int8_t *iop_data; 1440 u_int32_t iop_len; 1441 1442 if(acb->adapter_type & (ACB_ADAPTER_TYPE_C | ACB_ADAPTER_TYPE_D)) { 1443 return(arcmsr_Read_iop_rqbuffer_data_D(acb, prbuffer)); 1444 } 1445 iop_data = (u_int8_t *)prbuffer->data; 1446 iop_len = (u_int32_t)prbuffer->data_len; 1447 while (iop_len > 0) { 1448 pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex]; 1449 *pQbuffer = *iop_data; 1450 acb->rqbuf_lastindex++; 1451 /* if last, index number set it to 0 */ 1452 acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 1453 iop_data++; 1454 iop_len--; 1455 } 1456 /* let IOP know data has been read */ 1457 arcmsr_iop_message_read(acb); 1458 return (1); 1459 } 1460 /* 1461 ************************************************************************** 1462 ************************************************************************** 1463 */ 1464 static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb) 1465 { 1466 struct QBUFFER *prbuffer; 1467 int my_empty_len; 1468 1469 /*check this iop data if overflow my rqbuffer*/ 1470 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 1471 prbuffer = arcmsr_get_iop_rqbuffer(acb); 1472 my_empty_len = (acb->rqbuf_lastindex - acb->rqbuf_firstindex - 1) & 1473 (ARCMSR_MAX_QBUFFER-1); 1474 if(my_empty_len >= prbuffer->data_len) { 1475 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 1476 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 1477 } else { 1478 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 1479 } 1480 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 1481 } 1482 /* 1483 ********************************************************************** 1484 ********************************************************************** 1485 */ 1486 static void arcmsr_Write_data_2iop_wqbuffer_D(struct AdapterControlBlock *acb) 1487 { 1488 u_int8_t *pQbuffer; 1489 struct QBUFFER *pwbuffer; 1490 u_int8_t *buf1 = 0; 1491 u_int32_t *iop_data, *buf2 = 0; 1492 u_int32_t allxfer_len = 0, data_len; 1493 1494 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) { 1495 buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO); 1496 buf2 = (u_int32_t *)buf1; 1497 if( buf1 == NULL) 1498 return; 1499 1500 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ); 1501 pwbuffer = arcmsr_get_iop_wqbuffer(acb); 1502 iop_data = (u_int32_t *)pwbuffer->data; 1503 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex) 1504 && (allxfer_len < 124)) { 1505 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex]; 1506 *buf1 = *pQbuffer; 1507 acb->wqbuf_firstindex++; 1508 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 1509 buf1++; 1510 allxfer_len++; 1511 } 1512 pwbuffer->data_len = allxfer_len; 1513 data_len = allxfer_len; 1514 buf1 = (u_int8_t *)buf2; 1515 while(data_len >= 4) 1516 { 1517 *iop_data++ = *buf2++; 1518 data_len -= 4; 1519 } 1520 if(data_len) 1521 *iop_data = *buf2; 1522 free( buf1, M_DEVBUF); 1523 arcmsr_iop_message_wrote(acb); 1524 } 1525 } 1526 /* 1527 ********************************************************************** 1528 ********************************************************************** 1529 */ 1530 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb) 1531 { 1532 u_int8_t *pQbuffer; 1533 struct QBUFFER *pwbuffer; 1534 u_int8_t *iop_data; 1535 int32_t allxfer_len=0; 1536 1537 if(acb->adapter_type & (ACB_ADAPTER_TYPE_C | ACB_ADAPTER_TYPE_D)) { 1538 arcmsr_Write_data_2iop_wqbuffer_D(acb); 1539 return; 1540 } 1541 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) { 1542 acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ); 1543 pwbuffer = arcmsr_get_iop_wqbuffer(acb); 1544 iop_data = (u_int8_t *)pwbuffer->data; 1545 while((acb->wqbuf_firstindex != acb->wqbuf_lastindex) 1546 && (allxfer_len < 124)) { 1547 pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex]; 1548 *iop_data = *pQbuffer; 1549 acb->wqbuf_firstindex++; 1550 acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 1551 iop_data++; 1552 allxfer_len++; 1553 } 1554 pwbuffer->data_len = allxfer_len; 1555 arcmsr_iop_message_wrote(acb); 1556 } 1557 } 1558 /* 1559 ************************************************************************** 1560 ************************************************************************** 1561 */ 1562 static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb) 1563 { 1564 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 1565 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READ; 1566 /* 1567 ***************************************************************** 1568 ** check if there are any mail packages from user space program 1569 ** in my post bag, now is the time to send them into Areca's firmware 1570 ***************************************************************** 1571 */ 1572 if(acb->wqbuf_firstindex != acb->wqbuf_lastindex) { 1573 arcmsr_Write_data_2iop_wqbuffer(acb); 1574 } 1575 if(acb->wqbuf_firstindex == acb->wqbuf_lastindex) { 1576 acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED; 1577 } 1578 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 1579 } 1580 /* 1581 ************************************************************************** 1582 ************************************************************************** 1583 */ 1584 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb) 1585 { 1586 /* 1587 if (ccb->ccb_h.status != CAM_REQ_CMP) 1588 printf("arcmsr_rescanLun_cb: Rescan Target=%x, lun=%x," 1589 "failure status=%x\n", ccb->ccb_h.target_id, 1590 ccb->ccb_h.target_lun, ccb->ccb_h.status); 1591 else 1592 printf("arcmsr_rescanLun_cb: Rescan lun successfully!\n"); 1593 */ 1594 xpt_free_path(ccb->ccb_h.path); 1595 xpt_free_ccb(ccb); 1596 } 1597 1598 static void arcmsr_rescan_lun(struct AdapterControlBlock *acb, int target, int lun) 1599 { 1600 struct cam_path *path; 1601 union ccb *ccb; 1602 1603 if ((ccb = (union ccb *)xpt_alloc_ccb_nowait()) == NULL) 1604 return; 1605 if (xpt_create_path(&path, NULL, cam_sim_path(acb->psim), target, lun) != CAM_REQ_CMP) 1606 { 1607 xpt_free_ccb(ccb); 1608 return; 1609 } 1610 /* printf("arcmsr_rescan_lun: Rescan Target=%x, Lun=%x\n", target, lun); */ 1611 bzero(ccb, sizeof(union ccb)); 1612 xpt_setup_ccb(&ccb->ccb_h, path, 5); 1613 ccb->ccb_h.func_code = XPT_SCAN_LUN; 1614 ccb->ccb_h.cbfcnp = arcmsr_rescanLun_cb; 1615 ccb->crcn.flags = CAM_FLAG_NONE; 1616 xpt_action(ccb); 1617 } 1618 1619 1620 static void arcmsr_abort_dr_ccbs(struct AdapterControlBlock *acb, int target, int lun) 1621 { 1622 struct CommandControlBlock *srb; 1623 u_int32_t intmask_org; 1624 int i; 1625 1626 /* disable all outbound interrupts */ 1627 intmask_org = arcmsr_disable_allintr(acb); 1628 for (i = 0; i < ARCMSR_MAX_FREESRB_NUM; i++) 1629 { 1630 srb = acb->psrb_pool[i]; 1631 if (srb->srb_state == ARCMSR_SRB_START) 1632 { 1633 if((target == srb->pccb->ccb_h.target_id) && (lun == srb->pccb->ccb_h.target_lun)) 1634 { 1635 srb->srb_state = ARCMSR_SRB_ABORTED; 1636 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 1637 arcmsr_srb_complete(srb, 1); 1638 printf("arcmsr%d: abort scsi id %d lun %d srb=%p \n", acb->pci_unit, target, lun, srb); 1639 } 1640 } 1641 } 1642 /* enable outbound Post Queue, outbound doorbell Interrupt */ 1643 arcmsr_enable_allintr(acb, intmask_org); 1644 } 1645 /* 1646 ************************************************************************** 1647 ************************************************************************** 1648 */ 1649 static void arcmsr_dr_handle(struct AdapterControlBlock *acb) { 1650 u_int32_t devicemap; 1651 u_int32_t target, lun; 1652 u_int32_t deviceMapCurrent[4]={0}; 1653 u_int8_t *pDevMap; 1654 1655 switch (acb->adapter_type) { 1656 case ACB_ADAPTER_TYPE_A: 1657 devicemap = offsetof(struct HBA_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1658 for (target = 0; target < 4; target++) 1659 { 1660 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1661 devicemap += 4; 1662 } 1663 break; 1664 1665 case ACB_ADAPTER_TYPE_B: 1666 devicemap = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1667 for (target = 0; target < 4; target++) 1668 { 1669 deviceMapCurrent[target]=bus_space_read_4(acb->btag[1], acb->bhandle[1], devicemap); 1670 devicemap += 4; 1671 } 1672 break; 1673 1674 case ACB_ADAPTER_TYPE_C: 1675 devicemap = offsetof(struct HBC_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1676 for (target = 0; target < 4; target++) 1677 { 1678 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1679 devicemap += 4; 1680 } 1681 break; 1682 case ACB_ADAPTER_TYPE_D: 1683 devicemap = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 1684 for (target = 0; target < 4; target++) 1685 { 1686 deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0], devicemap); 1687 devicemap += 4; 1688 } 1689 break; 1690 } 1691 1692 if(acb->acb_flags & ACB_F_BUS_HANG_ON) 1693 { 1694 acb->acb_flags &= ~ACB_F_BUS_HANG_ON; 1695 } 1696 /* 1697 ** adapter posted CONFIG message 1698 ** copy the new map, note if there are differences with the current map 1699 */ 1700 pDevMap = (u_int8_t *)&deviceMapCurrent[0]; 1701 for (target = 0; target < ARCMSR_MAX_TARGETID - 1; target++) 1702 { 1703 if (*pDevMap != acb->device_map[target]) 1704 { 1705 u_int8_t difference, bit_check; 1706 1707 difference = *pDevMap ^ acb->device_map[target]; 1708 for(lun=0; lun < ARCMSR_MAX_TARGETLUN; lun++) 1709 { 1710 bit_check = (1 << lun); /*check bit from 0....31*/ 1711 if(difference & bit_check) 1712 { 1713 if(acb->device_map[target] & bit_check) 1714 {/* unit departed */ 1715 printf("arcmsr_dr_handle: Target=%x, lun=%x, GONE!!!\n",target,lun); 1716 arcmsr_abort_dr_ccbs(acb, target, lun); 1717 arcmsr_rescan_lun(acb, target, lun); 1718 acb->devstate[target][lun] = ARECA_RAID_GONE; 1719 } 1720 else 1721 {/* unit arrived */ 1722 printf("arcmsr_dr_handle: Target=%x, lun=%x, Plug-IN!!!\n",target,lun); 1723 arcmsr_rescan_lun(acb, target, lun); 1724 acb->devstate[target][lun] = ARECA_RAID_GOOD; 1725 } 1726 } 1727 } 1728 /* printf("arcmsr_dr_handle: acb->device_map[%x]=0x%x, deviceMapCurrent[%x]=%x\n",target,acb->device_map[target],target,*pDevMap); */ 1729 acb->device_map[target] = *pDevMap; 1730 } 1731 pDevMap++; 1732 } 1733 } 1734 /* 1735 ************************************************************************** 1736 ************************************************************************** 1737 */ 1738 static void arcmsr_hba_message_isr(struct AdapterControlBlock *acb) { 1739 u_int32_t outbound_message; 1740 1741 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT); 1742 outbound_message = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[0]); 1743 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1744 arcmsr_dr_handle( acb ); 1745 } 1746 /* 1747 ************************************************************************** 1748 ************************************************************************** 1749 */ 1750 static void arcmsr_hbb_message_isr(struct AdapterControlBlock *acb) { 1751 u_int32_t outbound_message; 1752 1753 /* clear interrupts */ 1754 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN); 1755 outbound_message = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0]); 1756 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1757 arcmsr_dr_handle( acb ); 1758 } 1759 /* 1760 ************************************************************************** 1761 ************************************************************************** 1762 */ 1763 static void arcmsr_hbc_message_isr(struct AdapterControlBlock *acb) { 1764 u_int32_t outbound_message; 1765 1766 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR); 1767 outbound_message = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[0]); 1768 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1769 arcmsr_dr_handle( acb ); 1770 } 1771 /* 1772 ************************************************************************** 1773 ************************************************************************** 1774 */ 1775 static void arcmsr_hbd_message_isr(struct AdapterControlBlock *acb) { 1776 u_int32_t outbound_message; 1777 1778 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR); 1779 outbound_message = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[0]); 1780 if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG) 1781 arcmsr_dr_handle( acb ); 1782 } 1783 /* 1784 ************************************************************************** 1785 ************************************************************************** 1786 */ 1787 static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb) 1788 { 1789 u_int32_t doorbell_status; 1790 1791 /* 1792 ******************************************************************* 1793 ** Maybe here we need to check wrqbuffer_lock is lock or not 1794 ** DOORBELL: din! don! 1795 ** check if there are any mail need to pack from firmware 1796 ******************************************************************* 1797 */ 1798 doorbell_status = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell); 1799 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */ 1800 if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) { 1801 arcmsr_iop2drv_data_wrote_handle(acb); 1802 } 1803 if(doorbell_status & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) { 1804 arcmsr_iop2drv_data_read_handle(acb); 1805 } 1806 } 1807 /* 1808 ************************************************************************** 1809 ************************************************************************** 1810 */ 1811 static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *acb) 1812 { 1813 u_int32_t doorbell_status; 1814 1815 /* 1816 ******************************************************************* 1817 ** Maybe here we need to check wrqbuffer_lock is lock or not 1818 ** DOORBELL: din! don! 1819 ** check if there are any mail need to pack from firmware 1820 ******************************************************************* 1821 */ 1822 doorbell_status = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell); 1823 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, doorbell_status); /* clear doorbell interrupt */ 1824 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) { 1825 arcmsr_iop2drv_data_wrote_handle(acb); 1826 } 1827 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) { 1828 arcmsr_iop2drv_data_read_handle(acb); 1829 } 1830 if(doorbell_status & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) { 1831 arcmsr_hbc_message_isr(acb); /* messenger of "driver to iop commands" */ 1832 } 1833 } 1834 /* 1835 ************************************************************************** 1836 ************************************************************************** 1837 */ 1838 static void arcmsr_hbd_doorbell_isr(struct AdapterControlBlock *acb) 1839 { 1840 u_int32_t doorbell_status; 1841 1842 /* 1843 ******************************************************************* 1844 ** Maybe here we need to check wrqbuffer_lock is lock or not 1845 ** DOORBELL: din! don! 1846 ** check if there are any mail need to pack from firmware 1847 ******************************************************************* 1848 */ 1849 doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE; 1850 if(doorbell_status) 1851 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */ 1852 while( doorbell_status & ARCMSR_HBDMU_F0_DOORBELL_CAUSE ) { 1853 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK) { 1854 arcmsr_iop2drv_data_wrote_handle(acb); 1855 } 1856 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK) { 1857 arcmsr_iop2drv_data_read_handle(acb); 1858 } 1859 if(doorbell_status & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) { 1860 arcmsr_hbd_message_isr(acb); /* messenger of "driver to iop commands" */ 1861 } 1862 doorbell_status = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE; 1863 if(doorbell_status) 1864 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, doorbell_status); /* clear doorbell interrupt */ 1865 } 1866 } 1867 /* 1868 ************************************************************************** 1869 ************************************************************************** 1870 */ 1871 static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb) 1872 { 1873 u_int32_t flag_srb; 1874 u_int16_t error; 1875 1876 /* 1877 ***************************************************************************** 1878 ** areca cdb command done 1879 ***************************************************************************** 1880 */ 1881 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 1882 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1883 while((flag_srb = CHIP_REG_READ32(HBA_MessageUnit, 1884 0, outbound_queueport)) != 0xFFFFFFFF) { 1885 /* check if command done with no error*/ 1886 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0) ? TRUE : FALSE; 1887 arcmsr_drain_donequeue(acb, flag_srb, error); 1888 } /*drain reply FIFO*/ 1889 } 1890 /* 1891 ************************************************************************** 1892 ************************************************************************** 1893 */ 1894 static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb) 1895 { 1896 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 1897 u_int32_t flag_srb; 1898 int index; 1899 u_int16_t error; 1900 1901 /* 1902 ***************************************************************************** 1903 ** areca cdb command done 1904 ***************************************************************************** 1905 */ 1906 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 1907 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1908 index = phbbmu->doneq_index; 1909 while((flag_srb = phbbmu->done_qbuffer[index]) != 0) { 1910 phbbmu->done_qbuffer[index] = 0; 1911 index++; 1912 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 1913 phbbmu->doneq_index = index; 1914 /* check if command done with no error*/ 1915 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 1916 arcmsr_drain_donequeue(acb, flag_srb, error); 1917 } /*drain reply FIFO*/ 1918 } 1919 /* 1920 ************************************************************************** 1921 ************************************************************************** 1922 */ 1923 static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb) 1924 { 1925 u_int32_t flag_srb,throttling = 0; 1926 u_int16_t error; 1927 1928 /* 1929 ***************************************************************************** 1930 ** areca cdb command done 1931 ***************************************************************************** 1932 */ 1933 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1934 do { 1935 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 1936 /* check if command done with no error*/ 1937 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE; 1938 arcmsr_drain_donequeue(acb, flag_srb, error); 1939 throttling++; 1940 if(throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) { 1941 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING); 1942 throttling = 0; 1943 } 1944 } while(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR); 1945 } 1946 /* 1947 ********************************************************************** 1948 ** 1949 ********************************************************************** 1950 */ 1951 static uint16_t arcmsr_get_doneq_index(struct HBD_MessageUnit0 *phbdmu) 1952 { 1953 uint16_t doneq_index, index_stripped; 1954 1955 doneq_index = phbdmu->doneq_index; 1956 if (doneq_index & 0x4000) { 1957 index_stripped = doneq_index & 0xFF; 1958 index_stripped += 1; 1959 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1960 phbdmu->doneq_index = index_stripped ? 1961 (index_stripped | 0x4000) : index_stripped; 1962 } else { 1963 index_stripped = doneq_index; 1964 index_stripped += 1; 1965 index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE; 1966 phbdmu->doneq_index = index_stripped ? 1967 index_stripped : (index_stripped | 0x4000); 1968 } 1969 return (phbdmu->doneq_index); 1970 } 1971 /* 1972 ************************************************************************** 1973 ************************************************************************** 1974 */ 1975 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb) 1976 { 1977 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 1978 u_int32_t outbound_write_pointer; 1979 u_int32_t addressLow; 1980 uint16_t doneq_index; 1981 u_int16_t error; 1982 /* 1983 ***************************************************************************** 1984 ** areca cdb command done 1985 ***************************************************************************** 1986 */ 1987 if((CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause) & 1988 ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT) == 0) 1989 return; 1990 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, 1991 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1992 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 1993 doneq_index = phbdmu->doneq_index; 1994 while ((doneq_index & 0xFF) != (outbound_write_pointer & 0xFF)) { 1995 doneq_index = arcmsr_get_doneq_index(phbdmu); 1996 addressLow = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow; 1997 error = (addressLow & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 1998 arcmsr_drain_donequeue(acb, addressLow, error); /*Check if command done with no error */ 1999 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index); 2000 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 2001 } 2002 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_interrupt_cause, ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR); 2003 CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause); /*Dummy ioread32 to force pci flush */ 2004 } 2005 /* 2006 ********************************************************************** 2007 ********************************************************************** 2008 */ 2009 static void arcmsr_handle_hba_isr( struct AdapterControlBlock *acb) 2010 { 2011 u_int32_t outbound_intStatus; 2012 /* 2013 ********************************************* 2014 ** check outbound intstatus 2015 ********************************************* 2016 */ 2017 outbound_intStatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 2018 if(!outbound_intStatus) { 2019 /*it must be share irq*/ 2020 return; 2021 } 2022 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intStatus); /*clear interrupt*/ 2023 /* MU doorbell interrupts*/ 2024 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) { 2025 arcmsr_hba_doorbell_isr(acb); 2026 } 2027 /* MU post queue interrupts*/ 2028 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) { 2029 arcmsr_hba_postqueue_isr(acb); 2030 } 2031 if(outbound_intStatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) { 2032 arcmsr_hba_message_isr(acb); 2033 } 2034 } 2035 /* 2036 ********************************************************************** 2037 ********************************************************************** 2038 */ 2039 static void arcmsr_handle_hbb_isr( struct AdapterControlBlock *acb) 2040 { 2041 u_int32_t outbound_doorbell; 2042 /* 2043 ********************************************* 2044 ** check outbound intstatus 2045 ********************************************* 2046 */ 2047 outbound_doorbell = CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & acb->outbound_int_enable; 2048 if(!outbound_doorbell) { 2049 /*it must be share irq*/ 2050 return; 2051 } 2052 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ~outbound_doorbell); /* clear doorbell interrupt */ 2053 CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell); 2054 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 2055 /* MU ioctl transfer doorbell interrupts*/ 2056 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) { 2057 arcmsr_iop2drv_data_wrote_handle(acb); 2058 } 2059 if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) { 2060 arcmsr_iop2drv_data_read_handle(acb); 2061 } 2062 /* MU post queue interrupts*/ 2063 if(outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) { 2064 arcmsr_hbb_postqueue_isr(acb); 2065 } 2066 if(outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) { 2067 arcmsr_hbb_message_isr(acb); 2068 } 2069 } 2070 /* 2071 ********************************************************************** 2072 ********************************************************************** 2073 */ 2074 static void arcmsr_handle_hbc_isr( struct AdapterControlBlock *acb) 2075 { 2076 u_int32_t host_interrupt_status; 2077 /* 2078 ********************************************* 2079 ** check outbound intstatus 2080 ********************************************* 2081 */ 2082 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & 2083 (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | 2084 ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR); 2085 if(!host_interrupt_status) { 2086 /*it must be share irq*/ 2087 return; 2088 } 2089 do { 2090 /* MU doorbell interrupts*/ 2091 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) { 2092 arcmsr_hbc_doorbell_isr(acb); 2093 } 2094 /* MU post queue interrupts*/ 2095 if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) { 2096 arcmsr_hbc_postqueue_isr(acb); 2097 } 2098 host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status); 2099 } while (host_interrupt_status & (ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR)); 2100 } 2101 /* 2102 ********************************************************************** 2103 ********************************************************************** 2104 */ 2105 static void arcmsr_handle_hbd_isr( struct AdapterControlBlock *acb) 2106 { 2107 u_int32_t host_interrupt_status; 2108 u_int32_t intmask_org; 2109 /* 2110 ********************************************* 2111 ** check outbound intstatus 2112 ********************************************* 2113 */ 2114 host_interrupt_status = CHIP_REG_READ32(HBD_MessageUnit, 0, host_int_status) & acb->outbound_int_enable; 2115 if(!(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_INT)) { 2116 /*it must be share irq*/ 2117 return; 2118 } 2119 /* disable outbound interrupt */ 2120 intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable) ; /* disable outbound message0 int */ 2121 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE); 2122 /* MU doorbell interrupts*/ 2123 if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT) { 2124 arcmsr_hbd_doorbell_isr(acb); 2125 } 2126 /* MU post queue interrupts*/ 2127 if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT) { 2128 arcmsr_hbd_postqueue_isr(acb); 2129 } 2130 /* enable all outbound interrupt */ 2131 CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | ARCMSR_HBDMU_ALL_INT_ENABLE); 2132 // CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable); 2133 } 2134 /* 2135 ****************************************************************************** 2136 ****************************************************************************** 2137 */ 2138 static void arcmsr_interrupt(struct AdapterControlBlock *acb) 2139 { 2140 switch (acb->adapter_type) { 2141 case ACB_ADAPTER_TYPE_A: 2142 arcmsr_handle_hba_isr(acb); 2143 break; 2144 case ACB_ADAPTER_TYPE_B: 2145 arcmsr_handle_hbb_isr(acb); 2146 break; 2147 case ACB_ADAPTER_TYPE_C: 2148 arcmsr_handle_hbc_isr(acb); 2149 break; 2150 case ACB_ADAPTER_TYPE_D: 2151 arcmsr_handle_hbd_isr(acb); 2152 break; 2153 default: 2154 printf("arcmsr%d: interrupt service," 2155 " unknown adapter type =%d\n", acb->pci_unit, acb->adapter_type); 2156 break; 2157 } 2158 } 2159 /* 2160 ********************************************************************** 2161 ********************************************************************** 2162 */ 2163 static void arcmsr_intr_handler(void *arg) 2164 { 2165 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg; 2166 2167 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 2168 arcmsr_interrupt(acb); 2169 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 2170 } 2171 /* 2172 ****************************************************************************** 2173 ****************************************************************************** 2174 */ 2175 static void arcmsr_polling_devmap(void *arg) 2176 { 2177 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg; 2178 switch (acb->adapter_type) { 2179 case ACB_ADAPTER_TYPE_A: 2180 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2181 break; 2182 2183 case ACB_ADAPTER_TYPE_B: 2184 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG); 2185 break; 2186 2187 case ACB_ADAPTER_TYPE_C: 2188 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2189 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 2190 break; 2191 2192 case ACB_ADAPTER_TYPE_D: 2193 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 2194 break; 2195 } 2196 2197 if((acb->acb_flags & ACB_F_SCSISTOPADAPTER) == 0) 2198 { 2199 callout_reset(&acb->devmap_callout, 5 * hz, arcmsr_polling_devmap, acb); /* polling per 5 seconds */ 2200 } 2201 } 2202 2203 /* 2204 ******************************************************************************* 2205 ** 2206 ******************************************************************************* 2207 */ 2208 static void arcmsr_iop_parking(struct AdapterControlBlock *acb) 2209 { 2210 u_int32_t intmask_org; 2211 2212 if(acb != NULL) { 2213 /* stop adapter background rebuild */ 2214 if(acb->acb_flags & ACB_F_MSG_START_BGRB) { 2215 intmask_org = arcmsr_disable_allintr(acb); 2216 arcmsr_stop_adapter_bgrb(acb); 2217 arcmsr_flush_adapter_cache(acb); 2218 arcmsr_enable_allintr(acb, intmask_org); 2219 } 2220 } 2221 } 2222 /* 2223 *********************************************************************** 2224 ** 2225 ************************************************************************ 2226 */ 2227 u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg) 2228 { 2229 struct CMD_MESSAGE_FIELD *pcmdmessagefld; 2230 u_int32_t retvalue = EINVAL; 2231 2232 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) arg; 2233 if(memcmp(pcmdmessagefld->cmdmessage.Signature, "ARCMSR", 6)!=0) { 2234 return retvalue; 2235 } 2236 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2237 switch(ioctl_cmd) { 2238 case ARCMSR_MESSAGE_READ_RQBUFFER: { 2239 u_int8_t *pQbuffer; 2240 u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer; 2241 u_int32_t allxfer_len=0; 2242 2243 while((acb->rqbuf_firstindex != acb->rqbuf_lastindex) 2244 && (allxfer_len < 1031)) { 2245 /*copy READ QBUFFER to srb*/ 2246 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex]; 2247 *ptmpQbuffer = *pQbuffer; 2248 acb->rqbuf_firstindex++; 2249 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 2250 /*if last index number set it to 0 */ 2251 ptmpQbuffer++; 2252 allxfer_len++; 2253 } 2254 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2255 struct QBUFFER *prbuffer; 2256 2257 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2258 prbuffer = arcmsr_get_iop_rqbuffer(acb); 2259 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 2260 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 2261 } 2262 pcmdmessagefld->cmdmessage.Length = allxfer_len; 2263 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2264 retvalue = ARCMSR_MESSAGE_SUCCESS; 2265 } 2266 break; 2267 case ARCMSR_MESSAGE_WRITE_WQBUFFER: { 2268 u_int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex; 2269 u_int8_t *pQbuffer; 2270 u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer; 2271 2272 user_len = pcmdmessagefld->cmdmessage.Length; 2273 /*check if data xfer length of this request will overflow my array qbuffer */ 2274 wqbuf_lastindex = acb->wqbuf_lastindex; 2275 wqbuf_firstindex = acb->wqbuf_firstindex; 2276 if(wqbuf_lastindex != wqbuf_firstindex) { 2277 arcmsr_Write_data_2iop_wqbuffer(acb); 2278 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2279 } else { 2280 my_empty_len = (wqbuf_firstindex - wqbuf_lastindex - 1) & 2281 (ARCMSR_MAX_QBUFFER - 1); 2282 if(my_empty_len >= user_len) { 2283 while(user_len > 0) { 2284 /*copy srb data to wqbuffer*/ 2285 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex]; 2286 *pQbuffer = *ptmpuserbuffer; 2287 acb->wqbuf_lastindex++; 2288 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 2289 /*if last index number set it to 0 */ 2290 ptmpuserbuffer++; 2291 user_len--; 2292 } 2293 /*post fist Qbuffer*/ 2294 if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) { 2295 acb->acb_flags &= ~ACB_F_MESSAGE_WQBUFFER_CLEARED; 2296 arcmsr_Write_data_2iop_wqbuffer(acb); 2297 } 2298 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2299 } else { 2300 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2301 } 2302 } 2303 retvalue = ARCMSR_MESSAGE_SUCCESS; 2304 } 2305 break; 2306 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: { 2307 u_int8_t *pQbuffer = acb->rqbuffer; 2308 2309 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2310 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2311 arcmsr_iop_message_read(acb); 2312 /*signature, let IOP know data has been readed */ 2313 } 2314 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 2315 acb->rqbuf_firstindex = 0; 2316 acb->rqbuf_lastindex = 0; 2317 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2318 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2319 retvalue = ARCMSR_MESSAGE_SUCCESS; 2320 } 2321 break; 2322 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: 2323 { 2324 u_int8_t *pQbuffer = acb->wqbuffer; 2325 2326 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2327 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2328 arcmsr_iop_message_read(acb); 2329 /*signature, let IOP know data has been readed */ 2330 } 2331 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ); 2332 acb->wqbuf_firstindex = 0; 2333 acb->wqbuf_lastindex = 0; 2334 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2335 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2336 retvalue = ARCMSR_MESSAGE_SUCCESS; 2337 } 2338 break; 2339 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: { 2340 u_int8_t *pQbuffer; 2341 2342 if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2343 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2344 arcmsr_iop_message_read(acb); 2345 /*signature, let IOP know data has been readed */ 2346 } 2347 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED 2348 |ACB_F_MESSAGE_RQBUFFER_CLEARED 2349 |ACB_F_MESSAGE_WQBUFFER_READ); 2350 acb->rqbuf_firstindex = 0; 2351 acb->rqbuf_lastindex = 0; 2352 acb->wqbuf_firstindex = 0; 2353 acb->wqbuf_lastindex = 0; 2354 pQbuffer = acb->rqbuffer; 2355 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 2356 pQbuffer = acb->wqbuffer; 2357 memset(pQbuffer, 0, sizeof(struct QBUFFER)); 2358 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2359 retvalue = ARCMSR_MESSAGE_SUCCESS; 2360 } 2361 break; 2362 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: { 2363 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F; 2364 retvalue = ARCMSR_MESSAGE_SUCCESS; 2365 } 2366 break; 2367 case ARCMSR_MESSAGE_SAY_HELLO: { 2368 u_int8_t *hello_string = "Hello! I am ARCMSR"; 2369 u_int8_t *puserbuffer = (u_int8_t *)pcmdmessagefld->messagedatabuffer; 2370 2371 if(memcpy(puserbuffer, hello_string, (int16_t)strlen(hello_string))) { 2372 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR; 2373 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2374 return ENOIOCTL; 2375 } 2376 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2377 retvalue = ARCMSR_MESSAGE_SUCCESS; 2378 } 2379 break; 2380 case ARCMSR_MESSAGE_SAY_GOODBYE: { 2381 arcmsr_iop_parking(acb); 2382 retvalue = ARCMSR_MESSAGE_SUCCESS; 2383 } 2384 break; 2385 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: { 2386 arcmsr_flush_adapter_cache(acb); 2387 retvalue = ARCMSR_MESSAGE_SUCCESS; 2388 } 2389 break; 2390 } 2391 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2392 return (retvalue); 2393 } 2394 /* 2395 ************************************************************************** 2396 ************************************************************************** 2397 */ 2398 static void arcmsr_free_srb(struct CommandControlBlock *srb) 2399 { 2400 struct AdapterControlBlock *acb; 2401 2402 acb = srb->acb; 2403 ARCMSR_LOCK_ACQUIRE(&acb->srb_lock); 2404 srb->srb_state = ARCMSR_SRB_DONE; 2405 srb->srb_flags = 0; 2406 acb->srbworkingQ[acb->workingsrb_doneindex] = srb; 2407 acb->workingsrb_doneindex++; 2408 acb->workingsrb_doneindex %= ARCMSR_MAX_FREESRB_NUM; 2409 ARCMSR_LOCK_RELEASE(&acb->srb_lock); 2410 } 2411 /* 2412 ************************************************************************** 2413 ************************************************************************** 2414 */ 2415 struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb) 2416 { 2417 struct CommandControlBlock *srb = NULL; 2418 u_int32_t workingsrb_startindex, workingsrb_doneindex; 2419 2420 ARCMSR_LOCK_ACQUIRE(&acb->srb_lock); 2421 workingsrb_doneindex = acb->workingsrb_doneindex; 2422 workingsrb_startindex = acb->workingsrb_startindex; 2423 srb = acb->srbworkingQ[workingsrb_startindex]; 2424 workingsrb_startindex++; 2425 workingsrb_startindex %= ARCMSR_MAX_FREESRB_NUM; 2426 if(workingsrb_doneindex != workingsrb_startindex) { 2427 acb->workingsrb_startindex = workingsrb_startindex; 2428 } else { 2429 srb = NULL; 2430 } 2431 ARCMSR_LOCK_RELEASE(&acb->srb_lock); 2432 return(srb); 2433 } 2434 /* 2435 ************************************************************************** 2436 ************************************************************************** 2437 */ 2438 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb) 2439 { 2440 struct CMD_MESSAGE_FIELD *pcmdmessagefld; 2441 int retvalue = 0, transfer_len = 0; 2442 char *buffer; 2443 u_int32_t controlcode = (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[5] << 24 | 2444 (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[6] << 16 | 2445 (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[7] << 8 | 2446 (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[8]; 2447 /* 4 bytes: Areca io control code */ 2448 if ((pccb->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_VADDR) { 2449 buffer = pccb->csio.data_ptr; 2450 transfer_len = pccb->csio.dxfer_len; 2451 } else { 2452 retvalue = ARCMSR_MESSAGE_FAIL; 2453 goto message_out; 2454 } 2455 if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) { 2456 retvalue = ARCMSR_MESSAGE_FAIL; 2457 goto message_out; 2458 } 2459 pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) buffer; 2460 switch(controlcode) { 2461 case ARCMSR_MESSAGE_READ_RQBUFFER: { 2462 u_int8_t *pQbuffer; 2463 u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer; 2464 int32_t allxfer_len = 0; 2465 2466 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2467 while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex) 2468 && (allxfer_len < 1031)) { 2469 pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex]; 2470 *ptmpQbuffer = *pQbuffer; 2471 acb->rqbuf_firstindex++; 2472 acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER; 2473 ptmpQbuffer++; 2474 allxfer_len++; 2475 } 2476 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2477 struct QBUFFER *prbuffer; 2478 2479 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2480 prbuffer = arcmsr_get_iop_rqbuffer(acb); 2481 if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0) 2482 acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW; 2483 } 2484 pcmdmessagefld->cmdmessage.Length = allxfer_len; 2485 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2486 retvalue = ARCMSR_MESSAGE_SUCCESS; 2487 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2488 } 2489 break; 2490 case ARCMSR_MESSAGE_WRITE_WQBUFFER: { 2491 int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex; 2492 u_int8_t *pQbuffer; 2493 u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer; 2494 2495 user_len = pcmdmessagefld->cmdmessage.Length; 2496 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2497 wqbuf_lastindex = acb->wqbuf_lastindex; 2498 wqbuf_firstindex = acb->wqbuf_firstindex; 2499 if (wqbuf_lastindex != wqbuf_firstindex) { 2500 arcmsr_Write_data_2iop_wqbuffer(acb); 2501 /* has error report sensedata */ 2502 if(pccb->csio.sense_len) { 2503 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); 2504 /* Valid,ErrorCode */ 2505 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05; 2506 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */ 2507 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A; 2508 /* AdditionalSenseLength */ 2509 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20; 2510 /* AdditionalSenseCode */ 2511 } 2512 retvalue = ARCMSR_MESSAGE_FAIL; 2513 } else { 2514 my_empty_len = (wqbuf_firstindex-wqbuf_lastindex - 1) 2515 &(ARCMSR_MAX_QBUFFER - 1); 2516 if (my_empty_len >= user_len) { 2517 while (user_len > 0) { 2518 pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex]; 2519 *pQbuffer = *ptmpuserbuffer; 2520 acb->wqbuf_lastindex++; 2521 acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER; 2522 ptmpuserbuffer++; 2523 user_len--; 2524 } 2525 if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) { 2526 acb->acb_flags &= 2527 ~ACB_F_MESSAGE_WQBUFFER_CLEARED; 2528 arcmsr_Write_data_2iop_wqbuffer(acb); 2529 } 2530 } else { 2531 /* has error report sensedata */ 2532 if(pccb->csio.sense_len) { 2533 ((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); 2534 /* Valid,ErrorCode */ 2535 ((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05; 2536 /* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */ 2537 ((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A; 2538 /* AdditionalSenseLength */ 2539 ((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20; 2540 /* AdditionalSenseCode */ 2541 } 2542 retvalue = ARCMSR_MESSAGE_FAIL; 2543 } 2544 } 2545 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2546 } 2547 break; 2548 case ARCMSR_MESSAGE_CLEAR_RQBUFFER: { 2549 u_int8_t *pQbuffer = acb->rqbuffer; 2550 2551 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2552 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2553 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2554 arcmsr_iop_message_read(acb); 2555 } 2556 acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED; 2557 acb->rqbuf_firstindex = 0; 2558 acb->rqbuf_lastindex = 0; 2559 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2560 pcmdmessagefld->cmdmessage.ReturnCode = 2561 ARCMSR_MESSAGE_RETURNCODE_OK; 2562 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2563 } 2564 break; 2565 case ARCMSR_MESSAGE_CLEAR_WQBUFFER: { 2566 u_int8_t *pQbuffer = acb->wqbuffer; 2567 2568 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2569 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2570 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2571 arcmsr_iop_message_read(acb); 2572 } 2573 acb->acb_flags |= 2574 (ACB_F_MESSAGE_WQBUFFER_CLEARED | 2575 ACB_F_MESSAGE_WQBUFFER_READ); 2576 acb->wqbuf_firstindex = 0; 2577 acb->wqbuf_lastindex = 0; 2578 memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER); 2579 pcmdmessagefld->cmdmessage.ReturnCode = 2580 ARCMSR_MESSAGE_RETURNCODE_OK; 2581 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2582 } 2583 break; 2584 case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: { 2585 u_int8_t *pQbuffer; 2586 2587 ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock); 2588 if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) { 2589 acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW; 2590 arcmsr_iop_message_read(acb); 2591 } 2592 acb->acb_flags |= 2593 (ACB_F_MESSAGE_WQBUFFER_CLEARED 2594 | ACB_F_MESSAGE_RQBUFFER_CLEARED 2595 | ACB_F_MESSAGE_WQBUFFER_READ); 2596 acb->rqbuf_firstindex = 0; 2597 acb->rqbuf_lastindex = 0; 2598 acb->wqbuf_firstindex = 0; 2599 acb->wqbuf_lastindex = 0; 2600 pQbuffer = acb->rqbuffer; 2601 memset(pQbuffer, 0, sizeof (struct QBUFFER)); 2602 pQbuffer = acb->wqbuffer; 2603 memset(pQbuffer, 0, sizeof (struct QBUFFER)); 2604 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2605 ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock); 2606 } 2607 break; 2608 case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: { 2609 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F; 2610 } 2611 break; 2612 case ARCMSR_MESSAGE_SAY_HELLO: { 2613 int8_t *hello_string = "Hello! I am ARCMSR"; 2614 2615 memcpy(pcmdmessagefld->messagedatabuffer, hello_string 2616 , (int16_t)strlen(hello_string)); 2617 pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK; 2618 } 2619 break; 2620 case ARCMSR_MESSAGE_SAY_GOODBYE: 2621 arcmsr_iop_parking(acb); 2622 break; 2623 case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: 2624 arcmsr_flush_adapter_cache(acb); 2625 break; 2626 default: 2627 retvalue = ARCMSR_MESSAGE_FAIL; 2628 } 2629 message_out: 2630 return (retvalue); 2631 } 2632 /* 2633 ********************************************************************* 2634 ********************************************************************* 2635 */ 2636 static void arcmsr_execute_srb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error) 2637 { 2638 struct CommandControlBlock *srb = (struct CommandControlBlock *)arg; 2639 struct AdapterControlBlock *acb = (struct AdapterControlBlock *)srb->acb; 2640 union ccb *pccb; 2641 int target, lun; 2642 2643 pccb = srb->pccb; 2644 target = pccb->ccb_h.target_id; 2645 lun = pccb->ccb_h.target_lun; 2646 acb->pktRequestCount++; 2647 if(error != 0) { 2648 if(error != EFBIG) { 2649 printf("arcmsr%d: unexpected error %x" 2650 " returned from 'bus_dmamap_load' \n" 2651 , acb->pci_unit, error); 2652 } 2653 if((pccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_INPROG) { 2654 pccb->ccb_h.status |= CAM_REQ_TOO_BIG; 2655 } 2656 arcmsr_srb_complete(srb, 0); 2657 return; 2658 } 2659 if(nseg > ARCMSR_MAX_SG_ENTRIES) { 2660 pccb->ccb_h.status |= CAM_REQ_TOO_BIG; 2661 arcmsr_srb_complete(srb, 0); 2662 return; 2663 } 2664 if(acb->acb_flags & ACB_F_BUS_RESET) { 2665 printf("arcmsr%d: bus reset and return busy \n", acb->pci_unit); 2666 pccb->ccb_h.status |= CAM_SCSI_BUS_RESET; 2667 arcmsr_srb_complete(srb, 0); 2668 return; 2669 } 2670 if(acb->devstate[target][lun] == ARECA_RAID_GONE) { 2671 u_int8_t block_cmd, cmd; 2672 2673 cmd = pccb->csio.cdb_io.cdb_bytes[0]; 2674 block_cmd = cmd & 0x0f; 2675 if(block_cmd == 0x08 || block_cmd == 0x0a) { 2676 printf("arcmsr%d:block 'read/write' command " 2677 "with gone raid volume Cmd=0x%2x, TargetId=%d, Lun=%d \n" 2678 , acb->pci_unit, cmd, target, lun); 2679 pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 2680 arcmsr_srb_complete(srb, 0); 2681 return; 2682 } 2683 } 2684 if((pccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_INPROG) { 2685 if(nseg != 0) { 2686 bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap); 2687 } 2688 arcmsr_srb_complete(srb, 0); 2689 return; 2690 } 2691 if(acb->srboutstandingcount >= acb->maxOutstanding) { 2692 if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) == 0) 2693 { 2694 xpt_freeze_simq(acb->psim, 1); 2695 acb->acb_flags |= ACB_F_CAM_DEV_QFRZN; 2696 } 2697 pccb->ccb_h.status &= ~CAM_SIM_QUEUED; 2698 pccb->ccb_h.status |= CAM_REQUEUE_REQ; 2699 arcmsr_srb_complete(srb, 0); 2700 return; 2701 } 2702 pccb->ccb_h.status |= CAM_SIM_QUEUED; 2703 arcmsr_build_srb(srb, dm_segs, nseg); 2704 arcmsr_post_srb(acb, srb); 2705 if (pccb->ccb_h.timeout != CAM_TIME_INFINITY) 2706 { 2707 arcmsr_callout_init(&srb->ccb_callout); 2708 callout_reset(&srb->ccb_callout, ((pccb->ccb_h.timeout + (ARCMSR_TIMEOUT_DELAY * 1000)) * hz) / 1000, arcmsr_srb_timeout, srb); 2709 srb->srb_flags |= SRB_FLAG_TIMER_START; 2710 } 2711 } 2712 /* 2713 ***************************************************************************************** 2714 ***************************************************************************************** 2715 */ 2716 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb) 2717 { 2718 struct CommandControlBlock *srb; 2719 struct AdapterControlBlock *acb = (struct AdapterControlBlock *) abortccb->ccb_h.arcmsr_ccbacb_ptr; 2720 u_int32_t intmask_org; 2721 int i = 0; 2722 2723 acb->num_aborts++; 2724 /* 2725 *************************************************************************** 2726 ** It is the upper layer do abort command this lock just prior to calling us. 2727 ** First determine if we currently own this command. 2728 ** Start by searching the device queue. If not found 2729 ** at all, and the system wanted us to just abort the 2730 ** command return success. 2731 *************************************************************************** 2732 */ 2733 if(acb->srboutstandingcount != 0) { 2734 /* disable all outbound interrupt */ 2735 intmask_org = arcmsr_disable_allintr(acb); 2736 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 2737 srb = acb->psrb_pool[i]; 2738 if(srb->srb_state == ARCMSR_SRB_START) { 2739 if(srb->pccb == abortccb) { 2740 srb->srb_state = ARCMSR_SRB_ABORTED; 2741 printf("arcmsr%d:scsi id=%d lun=%jx abort srb '%p'" 2742 "outstanding command \n" 2743 , acb->pci_unit, abortccb->ccb_h.target_id 2744 , (uintmax_t)abortccb->ccb_h.target_lun, srb); 2745 arcmsr_polling_srbdone(acb, srb); 2746 /* enable outbound Post Queue, outbound doorbell Interrupt */ 2747 arcmsr_enable_allintr(acb, intmask_org); 2748 return (TRUE); 2749 } 2750 } 2751 } 2752 /* enable outbound Post Queue, outbound doorbell Interrupt */ 2753 arcmsr_enable_allintr(acb, intmask_org); 2754 } 2755 return(FALSE); 2756 } 2757 /* 2758 **************************************************************************** 2759 **************************************************************************** 2760 */ 2761 static void arcmsr_bus_reset(struct AdapterControlBlock *acb) 2762 { 2763 int retry = 0; 2764 2765 acb->num_resets++; 2766 acb->acb_flags |= ACB_F_BUS_RESET; 2767 while(acb->srboutstandingcount != 0 && retry < 400) { 2768 arcmsr_interrupt(acb); 2769 UDELAY(25000); 2770 retry++; 2771 } 2772 arcmsr_iop_reset(acb); 2773 acb->acb_flags &= ~ACB_F_BUS_RESET; 2774 } 2775 /* 2776 ************************************************************************** 2777 ************************************************************************** 2778 */ 2779 static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb, 2780 union ccb *pccb) 2781 { 2782 if (pccb->ccb_h.target_lun) { 2783 pccb->ccb_h.status |= CAM_DEV_NOT_THERE; 2784 xpt_done(pccb); 2785 return; 2786 } 2787 pccb->ccb_h.status |= CAM_REQ_CMP; 2788 switch (pccb->csio.cdb_io.cdb_bytes[0]) { 2789 case INQUIRY: { 2790 unsigned char inqdata[36]; 2791 char *buffer = pccb->csio.data_ptr; 2792 2793 inqdata[0] = T_PROCESSOR; /* Periph Qualifier & Periph Dev Type */ 2794 inqdata[1] = 0; /* rem media bit & Dev Type Modifier */ 2795 inqdata[2] = 0; /* ISO, ECMA, & ANSI versions */ 2796 inqdata[3] = 0; 2797 inqdata[4] = 31; /* length of additional data */ 2798 inqdata[5] = 0; 2799 inqdata[6] = 0; 2800 inqdata[7] = 0; 2801 strncpy(&inqdata[8], "Areca ", 8); /* Vendor Identification */ 2802 strncpy(&inqdata[16], "RAID controller ", 16); /* Product Identification */ 2803 strncpy(&inqdata[32], "R001", 4); /* Product Revision */ 2804 memcpy(buffer, inqdata, sizeof(inqdata)); 2805 xpt_done(pccb); 2806 } 2807 break; 2808 case WRITE_BUFFER: 2809 case READ_BUFFER: { 2810 if (arcmsr_iop_message_xfer(acb, pccb)) { 2811 pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR; 2812 pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND; 2813 } 2814 xpt_done(pccb); 2815 } 2816 break; 2817 default: 2818 xpt_done(pccb); 2819 } 2820 } 2821 /* 2822 ********************************************************************* 2823 ********************************************************************* 2824 */ 2825 static void arcmsr_action(struct cam_sim *psim, union ccb *pccb) 2826 { 2827 struct AdapterControlBlock *acb; 2828 2829 acb = (struct AdapterControlBlock *) cam_sim_softc(psim); 2830 if(acb == NULL) { 2831 pccb->ccb_h.status |= CAM_REQ_INVALID; 2832 xpt_done(pccb); 2833 return; 2834 } 2835 switch (pccb->ccb_h.func_code) { 2836 case XPT_SCSI_IO: { 2837 struct CommandControlBlock *srb; 2838 int target = pccb->ccb_h.target_id; 2839 int error; 2840 2841 if(target == 16) { 2842 /* virtual device for iop message transfer */ 2843 arcmsr_handle_virtual_command(acb, pccb); 2844 return; 2845 } 2846 if((srb = arcmsr_get_freesrb(acb)) == NULL) { 2847 pccb->ccb_h.status |= CAM_RESRC_UNAVAIL; 2848 xpt_done(pccb); 2849 return; 2850 } 2851 pccb->ccb_h.arcmsr_ccbsrb_ptr = srb; 2852 pccb->ccb_h.arcmsr_ccbacb_ptr = acb; 2853 srb->pccb = pccb; 2854 error = bus_dmamap_load_ccb(acb->dm_segs_dmat 2855 , srb->dm_segs_dmamap 2856 , pccb 2857 , arcmsr_execute_srb, srb, /*flags*/0); 2858 if(error == EINPROGRESS) { 2859 xpt_freeze_simq(acb->psim, 1); 2860 pccb->ccb_h.status |= CAM_RELEASE_SIMQ; 2861 } 2862 break; 2863 } 2864 case XPT_TARGET_IO: { 2865 /* target mode not yet support vendor specific commands. */ 2866 pccb->ccb_h.status |= CAM_REQ_CMP; 2867 xpt_done(pccb); 2868 break; 2869 } 2870 case XPT_PATH_INQ: { 2871 struct ccb_pathinq *cpi = &pccb->cpi; 2872 2873 cpi->version_num = 1; 2874 cpi->hba_inquiry = PI_SDTR_ABLE | PI_TAG_ABLE; 2875 cpi->target_sprt = 0; 2876 cpi->hba_misc = 0; 2877 cpi->hba_eng_cnt = 0; 2878 cpi->max_target = ARCMSR_MAX_TARGETID; /* 0-16 */ 2879 cpi->max_lun = ARCMSR_MAX_TARGETLUN; /* 0-7 */ 2880 cpi->initiator_id = ARCMSR_SCSI_INITIATOR_ID; /* 255 */ 2881 cpi->bus_id = cam_sim_bus(psim); 2882 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN); 2883 strncpy(cpi->hba_vid, "ARCMSR", HBA_IDLEN); 2884 strncpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN); 2885 cpi->unit_number = cam_sim_unit(psim); 2886 #ifdef CAM_NEW_TRAN_CODE 2887 if(acb->adapter_bus_speed == ACB_BUS_SPEED_12G) 2888 cpi->base_transfer_speed = 1200000; 2889 else if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G) 2890 cpi->base_transfer_speed = 600000; 2891 else 2892 cpi->base_transfer_speed = 300000; 2893 if((acb->vendor_device_id == PCIDevVenIDARC1880) || 2894 (acb->vendor_device_id == PCIDevVenIDARC1680) || 2895 (acb->vendor_device_id == PCIDevVenIDARC1214)) 2896 { 2897 cpi->transport = XPORT_SAS; 2898 cpi->transport_version = 0; 2899 cpi->protocol_version = SCSI_REV_SPC2; 2900 } 2901 else 2902 { 2903 cpi->transport = XPORT_SPI; 2904 cpi->transport_version = 2; 2905 cpi->protocol_version = SCSI_REV_2; 2906 } 2907 cpi->protocol = PROTO_SCSI; 2908 #endif 2909 cpi->ccb_h.status |= CAM_REQ_CMP; 2910 xpt_done(pccb); 2911 break; 2912 } 2913 case XPT_ABORT: { 2914 union ccb *pabort_ccb; 2915 2916 pabort_ccb = pccb->cab.abort_ccb; 2917 switch (pabort_ccb->ccb_h.func_code) { 2918 case XPT_ACCEPT_TARGET_IO: 2919 case XPT_IMMED_NOTIFY: 2920 case XPT_CONT_TARGET_IO: 2921 if(arcmsr_seek_cmd2abort(pabort_ccb)==TRUE) { 2922 pabort_ccb->ccb_h.status |= CAM_REQ_ABORTED; 2923 xpt_done(pabort_ccb); 2924 pccb->ccb_h.status |= CAM_REQ_CMP; 2925 } else { 2926 xpt_print_path(pabort_ccb->ccb_h.path); 2927 printf("Not found\n"); 2928 pccb->ccb_h.status |= CAM_PATH_INVALID; 2929 } 2930 break; 2931 case XPT_SCSI_IO: 2932 pccb->ccb_h.status |= CAM_UA_ABORT; 2933 break; 2934 default: 2935 pccb->ccb_h.status |= CAM_REQ_INVALID; 2936 break; 2937 } 2938 xpt_done(pccb); 2939 break; 2940 } 2941 case XPT_RESET_BUS: 2942 case XPT_RESET_DEV: { 2943 u_int32_t i; 2944 2945 arcmsr_bus_reset(acb); 2946 for (i=0; i < 500; i++) { 2947 DELAY(1000); 2948 } 2949 pccb->ccb_h.status |= CAM_REQ_CMP; 2950 xpt_done(pccb); 2951 break; 2952 } 2953 case XPT_TERM_IO: { 2954 pccb->ccb_h.status |= CAM_REQ_INVALID; 2955 xpt_done(pccb); 2956 break; 2957 } 2958 case XPT_GET_TRAN_SETTINGS: { 2959 struct ccb_trans_settings *cts; 2960 2961 if(pccb->ccb_h.target_id == 16) { 2962 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 2963 xpt_done(pccb); 2964 break; 2965 } 2966 cts = &pccb->cts; 2967 #ifdef CAM_NEW_TRAN_CODE 2968 { 2969 struct ccb_trans_settings_scsi *scsi; 2970 struct ccb_trans_settings_spi *spi; 2971 struct ccb_trans_settings_sas *sas; 2972 2973 scsi = &cts->proto_specific.scsi; 2974 scsi->flags = CTS_SCSI_FLAGS_TAG_ENB; 2975 scsi->valid = CTS_SCSI_VALID_TQ; 2976 cts->protocol = PROTO_SCSI; 2977 2978 if((acb->vendor_device_id == PCIDevVenIDARC1880) || 2979 (acb->vendor_device_id == PCIDevVenIDARC1680) || 2980 (acb->vendor_device_id == PCIDevVenIDARC1214)) 2981 { 2982 cts->protocol_version = SCSI_REV_SPC2; 2983 cts->transport_version = 0; 2984 cts->transport = XPORT_SAS; 2985 sas = &cts->xport_specific.sas; 2986 sas->valid = CTS_SAS_VALID_SPEED; 2987 if (acb->sub_device_id == ARECA_SUB_DEV_ID_1883) 2988 sas->bitrate = 1200000; 2989 else if((acb->vendor_device_id == PCIDevVenIDARC1880) || 2990 (acb->vendor_device_id == PCIDevVenIDARC1214)) 2991 sas->bitrate = 600000; 2992 else if(acb->vendor_device_id == PCIDevVenIDARC1680) 2993 sas->bitrate = 300000; 2994 } 2995 else 2996 { 2997 cts->protocol_version = SCSI_REV_2; 2998 cts->transport_version = 2; 2999 cts->transport = XPORT_SPI; 3000 spi = &cts->xport_specific.spi; 3001 spi->flags = CTS_SPI_FLAGS_DISC_ENB; 3002 spi->sync_period = 2; 3003 spi->sync_offset = 32; 3004 spi->bus_width = MSG_EXT_WDTR_BUS_16_BIT; 3005 spi->valid = CTS_SPI_VALID_DISC 3006 | CTS_SPI_VALID_SYNC_RATE 3007 | CTS_SPI_VALID_SYNC_OFFSET 3008 | CTS_SPI_VALID_BUS_WIDTH; 3009 } 3010 } 3011 #else 3012 { 3013 cts->flags = (CCB_TRANS_DISC_ENB | CCB_TRANS_TAG_ENB); 3014 cts->sync_period = 2; 3015 cts->sync_offset = 32; 3016 cts->bus_width = MSG_EXT_WDTR_BUS_16_BIT; 3017 cts->valid = CCB_TRANS_SYNC_RATE_VALID | 3018 CCB_TRANS_SYNC_OFFSET_VALID | 3019 CCB_TRANS_BUS_WIDTH_VALID | 3020 CCB_TRANS_DISC_VALID | 3021 CCB_TRANS_TQ_VALID; 3022 } 3023 #endif 3024 pccb->ccb_h.status |= CAM_REQ_CMP; 3025 xpt_done(pccb); 3026 break; 3027 } 3028 case XPT_SET_TRAN_SETTINGS: { 3029 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 3030 xpt_done(pccb); 3031 break; 3032 } 3033 case XPT_CALC_GEOMETRY: 3034 if(pccb->ccb_h.target_id == 16) { 3035 pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL; 3036 xpt_done(pccb); 3037 break; 3038 } 3039 #if __FreeBSD_version >= 500000 3040 cam_calc_geometry(&pccb->ccg, 1); 3041 #else 3042 { 3043 struct ccb_calc_geometry *ccg; 3044 u_int32_t size_mb; 3045 u_int32_t secs_per_cylinder; 3046 3047 ccg = &pccb->ccg; 3048 if (ccg->block_size == 0) { 3049 pccb->ccb_h.status = CAM_REQ_INVALID; 3050 xpt_done(pccb); 3051 break; 3052 } 3053 if(((1024L * 1024L)/ccg->block_size) < 0) { 3054 pccb->ccb_h.status = CAM_REQ_INVALID; 3055 xpt_done(pccb); 3056 break; 3057 } 3058 size_mb = ccg->volume_size/((1024L * 1024L)/ccg->block_size); 3059 if(size_mb > 1024 ) { 3060 ccg->heads = 255; 3061 ccg->secs_per_track = 63; 3062 } else { 3063 ccg->heads = 64; 3064 ccg->secs_per_track = 32; 3065 } 3066 secs_per_cylinder = ccg->heads * ccg->secs_per_track; 3067 ccg->cylinders = ccg->volume_size / secs_per_cylinder; 3068 pccb->ccb_h.status |= CAM_REQ_CMP; 3069 } 3070 #endif 3071 xpt_done(pccb); 3072 break; 3073 default: 3074 pccb->ccb_h.status |= CAM_REQ_INVALID; 3075 xpt_done(pccb); 3076 break; 3077 } 3078 } 3079 /* 3080 ********************************************************************** 3081 ********************************************************************** 3082 */ 3083 static void arcmsr_start_hba_bgrb(struct AdapterControlBlock *acb) 3084 { 3085 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3086 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3087 if(!arcmsr_hba_wait_msgint_ready(acb)) { 3088 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3089 } 3090 } 3091 /* 3092 ********************************************************************** 3093 ********************************************************************** 3094 */ 3095 static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb) 3096 { 3097 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3098 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_START_BGRB); 3099 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3100 printf( "arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3101 } 3102 } 3103 /* 3104 ********************************************************************** 3105 ********************************************************************** 3106 */ 3107 static void arcmsr_start_hbc_bgrb(struct AdapterControlBlock *acb) 3108 { 3109 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3110 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3111 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3112 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 3113 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3114 } 3115 } 3116 /* 3117 ********************************************************************** 3118 ********************************************************************** 3119 */ 3120 static void arcmsr_start_hbd_bgrb(struct AdapterControlBlock *acb) 3121 { 3122 acb->acb_flags |= ACB_F_MSG_START_BGRB; 3123 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB); 3124 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 3125 printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit); 3126 } 3127 } 3128 /* 3129 ********************************************************************** 3130 ********************************************************************** 3131 */ 3132 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb) 3133 { 3134 switch (acb->adapter_type) { 3135 case ACB_ADAPTER_TYPE_A: 3136 arcmsr_start_hba_bgrb(acb); 3137 break; 3138 case ACB_ADAPTER_TYPE_B: 3139 arcmsr_start_hbb_bgrb(acb); 3140 break; 3141 case ACB_ADAPTER_TYPE_C: 3142 arcmsr_start_hbc_bgrb(acb); 3143 break; 3144 case ACB_ADAPTER_TYPE_D: 3145 arcmsr_start_hbd_bgrb(acb); 3146 break; 3147 } 3148 } 3149 /* 3150 ********************************************************************** 3151 ** 3152 ********************************************************************** 3153 */ 3154 static void arcmsr_polling_hba_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3155 { 3156 struct CommandControlBlock *srb; 3157 u_int32_t flag_srb, outbound_intstatus, poll_srb_done=0, poll_count=0; 3158 u_int16_t error; 3159 3160 polling_ccb_retry: 3161 poll_count++; 3162 outbound_intstatus=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable; 3163 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus); /*clear interrupt*/ 3164 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3165 while(1) { 3166 if((flag_srb = CHIP_REG_READ32(HBA_MessageUnit, 3167 0, outbound_queueport)) == 0xFFFFFFFF) { 3168 if(poll_srb_done) { 3169 break;/*chip FIFO no ccb for completion already*/ 3170 } else { 3171 UDELAY(25000); 3172 if ((poll_count > 100) && (poll_srb != NULL)) { 3173 break; 3174 } 3175 goto polling_ccb_retry; 3176 } 3177 } 3178 /* check if command done with no error*/ 3179 srb = (struct CommandControlBlock *) 3180 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 3181 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 3182 poll_srb_done = (srb == poll_srb) ? 1:0; 3183 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3184 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3185 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'" 3186 "poll command abort successfully \n" 3187 , acb->pci_unit 3188 , srb->pccb->ccb_h.target_id 3189 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3190 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3191 arcmsr_srb_complete(srb, 1); 3192 continue; 3193 } 3194 printf("arcmsr%d: polling get an illegal srb command done srb='%p'" 3195 "srboutstandingcount=%d \n" 3196 , acb->pci_unit 3197 , srb, acb->srboutstandingcount); 3198 continue; 3199 } 3200 arcmsr_report_srb_state(acb, srb, error); 3201 } /*drain reply FIFO*/ 3202 } 3203 /* 3204 ********************************************************************** 3205 ** 3206 ********************************************************************** 3207 */ 3208 static void arcmsr_polling_hbb_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3209 { 3210 struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3211 struct CommandControlBlock *srb; 3212 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3213 int index; 3214 u_int16_t error; 3215 3216 polling_ccb_retry: 3217 poll_count++; 3218 CHIP_REG_WRITE32(HBB_DOORBELL, 3219 0, iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */ 3220 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3221 while(1) { 3222 index = phbbmu->doneq_index; 3223 if((flag_srb = phbbmu->done_qbuffer[index]) == 0) { 3224 if(poll_srb_done) { 3225 break;/*chip FIFO no ccb for completion already*/ 3226 } else { 3227 UDELAY(25000); 3228 if ((poll_count > 100) && (poll_srb != NULL)) { 3229 break; 3230 } 3231 goto polling_ccb_retry; 3232 } 3233 } 3234 phbbmu->done_qbuffer[index] = 0; 3235 index++; 3236 index %= ARCMSR_MAX_HBB_POSTQUEUE; /*if last index number set it to 0 */ 3237 phbbmu->doneq_index = index; 3238 /* check if command done with no error*/ 3239 srb = (struct CommandControlBlock *) 3240 (acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/ 3241 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE; 3242 poll_srb_done = (srb == poll_srb) ? 1:0; 3243 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3244 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3245 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'" 3246 "poll command abort successfully \n" 3247 , acb->pci_unit 3248 , srb->pccb->ccb_h.target_id 3249 , (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3250 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3251 arcmsr_srb_complete(srb, 1); 3252 continue; 3253 } 3254 printf("arcmsr%d: polling get an illegal srb command done srb='%p'" 3255 "srboutstandingcount=%d \n" 3256 , acb->pci_unit 3257 , srb, acb->srboutstandingcount); 3258 continue; 3259 } 3260 arcmsr_report_srb_state(acb, srb, error); 3261 } /*drain reply FIFO*/ 3262 } 3263 /* 3264 ********************************************************************** 3265 ** 3266 ********************************************************************** 3267 */ 3268 static void arcmsr_polling_hbc_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3269 { 3270 struct CommandControlBlock *srb; 3271 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3272 u_int16_t error; 3273 3274 polling_ccb_retry: 3275 poll_count++; 3276 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3277 while(1) { 3278 if(!(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)) { 3279 if(poll_srb_done) { 3280 break;/*chip FIFO no ccb for completion already*/ 3281 } else { 3282 UDELAY(25000); 3283 if ((poll_count > 100) && (poll_srb != NULL)) { 3284 break; 3285 } 3286 if (acb->srboutstandingcount == 0) { 3287 break; 3288 } 3289 goto polling_ccb_retry; 3290 } 3291 } 3292 flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low); 3293 /* check if command done with no error*/ 3294 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/ 3295 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE; 3296 if (poll_srb != NULL) 3297 poll_srb_done = (srb == poll_srb) ? 1:0; 3298 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3299 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3300 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n" 3301 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3302 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3303 arcmsr_srb_complete(srb, 1); 3304 continue; 3305 } 3306 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 3307 , acb->pci_unit, srb, acb->srboutstandingcount); 3308 continue; 3309 } 3310 arcmsr_report_srb_state(acb, srb, error); 3311 } /*drain reply FIFO*/ 3312 } 3313 /* 3314 ********************************************************************** 3315 ** 3316 ********************************************************************** 3317 */ 3318 static void arcmsr_polling_hbd_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3319 { 3320 struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 3321 struct CommandControlBlock *srb; 3322 u_int32_t flag_srb, poll_srb_done=0, poll_count=0; 3323 u_int32_t outbound_write_pointer; 3324 u_int16_t error, doneq_index; 3325 3326 polling_ccb_retry: 3327 poll_count++; 3328 bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 3329 while(1) { 3330 outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow; 3331 doneq_index = phbdmu->doneq_index; 3332 if ((outbound_write_pointer & 0xFF) == (doneq_index & 0xFF)) { 3333 if(poll_srb_done) { 3334 break;/*chip FIFO no ccb for completion already*/ 3335 } else { 3336 UDELAY(25000); 3337 if ((poll_count > 100) && (poll_srb != NULL)) { 3338 break; 3339 } 3340 if (acb->srboutstandingcount == 0) { 3341 break; 3342 } 3343 goto polling_ccb_retry; 3344 } 3345 } 3346 doneq_index = arcmsr_get_doneq_index(phbdmu); 3347 flag_srb = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow; 3348 /* check if command done with no error*/ 3349 srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/ 3350 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE; 3351 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index); 3352 if (poll_srb != NULL) 3353 poll_srb_done = (srb == poll_srb) ? 1:0; 3354 if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) { 3355 if(srb->srb_state == ARCMSR_SRB_ABORTED) { 3356 printf("arcmsr%d: scsi id=%d lun=%jx srb='%p'poll command abort successfully \n" 3357 , acb->pci_unit, srb->pccb->ccb_h.target_id, (uintmax_t)srb->pccb->ccb_h.target_lun, srb); 3358 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 3359 arcmsr_srb_complete(srb, 1); 3360 continue; 3361 } 3362 printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n" 3363 , acb->pci_unit, srb, acb->srboutstandingcount); 3364 continue; 3365 } 3366 arcmsr_report_srb_state(acb, srb, error); 3367 } /*drain reply FIFO*/ 3368 } 3369 /* 3370 ********************************************************************** 3371 ********************************************************************** 3372 */ 3373 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb) 3374 { 3375 switch (acb->adapter_type) { 3376 case ACB_ADAPTER_TYPE_A: { 3377 arcmsr_polling_hba_srbdone(acb, poll_srb); 3378 } 3379 break; 3380 case ACB_ADAPTER_TYPE_B: { 3381 arcmsr_polling_hbb_srbdone(acb, poll_srb); 3382 } 3383 break; 3384 case ACB_ADAPTER_TYPE_C: { 3385 arcmsr_polling_hbc_srbdone(acb, poll_srb); 3386 } 3387 break; 3388 case ACB_ADAPTER_TYPE_D: { 3389 arcmsr_polling_hbd_srbdone(acb, poll_srb); 3390 } 3391 break; 3392 } 3393 } 3394 /* 3395 ********************************************************************** 3396 ********************************************************************** 3397 */ 3398 static void arcmsr_get_hba_config(struct AdapterControlBlock *acb) 3399 { 3400 char *acb_firm_model = acb->firm_model; 3401 char *acb_firm_version = acb->firm_version; 3402 char *acb_device_map = acb->device_map; 3403 size_t iop_firm_model = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3404 size_t iop_firm_version = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3405 size_t iop_device_map = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3406 int i; 3407 3408 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3409 if(!arcmsr_hba_wait_msgint_ready(acb)) { 3410 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3411 } 3412 i = 0; 3413 while(i < 8) { 3414 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3415 /* 8 bytes firm_model, 15, 60-67*/ 3416 acb_firm_model++; 3417 i++; 3418 } 3419 i=0; 3420 while(i < 16) { 3421 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3422 /* 16 bytes firm_version, 17, 68-83*/ 3423 acb_firm_version++; 3424 i++; 3425 } 3426 i=0; 3427 while(i < 16) { 3428 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3429 acb_device_map++; 3430 i++; 3431 } 3432 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3433 acb->firm_request_len = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3434 acb->firm_numbers_queue = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3435 acb->firm_sdram_size = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3436 acb->firm_ide_channels = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3437 acb->firm_cfg_version = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3438 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 3439 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 3440 else 3441 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3442 } 3443 /* 3444 ********************************************************************** 3445 ********************************************************************** 3446 */ 3447 static void arcmsr_get_hbb_config(struct AdapterControlBlock *acb) 3448 { 3449 char *acb_firm_model = acb->firm_model; 3450 char *acb_firm_version = acb->firm_version; 3451 char *acb_device_map = acb->device_map; 3452 size_t iop_firm_model = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3453 size_t iop_firm_version = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3454 size_t iop_device_map = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3455 int i; 3456 3457 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG); 3458 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3459 printf( "arcmsr%d: wait" "'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3460 } 3461 i = 0; 3462 while(i < 8) { 3463 *acb_firm_model = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_model+i); 3464 /* 8 bytes firm_model, 15, 60-67*/ 3465 acb_firm_model++; 3466 i++; 3467 } 3468 i = 0; 3469 while(i < 16) { 3470 *acb_firm_version = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_version+i); 3471 /* 16 bytes firm_version, 17, 68-83*/ 3472 acb_firm_version++; 3473 i++; 3474 } 3475 i = 0; 3476 while(i < 16) { 3477 *acb_device_map = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_device_map+i); 3478 acb_device_map++; 3479 i++; 3480 } 3481 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3482 acb->firm_request_len = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3483 acb->firm_numbers_queue = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3484 acb->firm_sdram_size = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3485 acb->firm_ide_channels = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3486 acb->firm_cfg_version = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3487 if(acb->firm_numbers_queue > ARCMSR_MAX_HBB_POSTQUEUE) 3488 acb->maxOutstanding = ARCMSR_MAX_HBB_POSTQUEUE - 1; 3489 else 3490 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3491 } 3492 /* 3493 ********************************************************************** 3494 ********************************************************************** 3495 */ 3496 static void arcmsr_get_hbc_config(struct AdapterControlBlock *acb) 3497 { 3498 char *acb_firm_model = acb->firm_model; 3499 char *acb_firm_version = acb->firm_version; 3500 char *acb_device_map = acb->device_map; 3501 size_t iop_firm_model = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3502 size_t iop_firm_version = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3503 size_t iop_device_map = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3504 int i; 3505 3506 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3507 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3508 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 3509 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3510 } 3511 i = 0; 3512 while(i < 8) { 3513 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3514 /* 8 bytes firm_model, 15, 60-67*/ 3515 acb_firm_model++; 3516 i++; 3517 } 3518 i = 0; 3519 while(i < 16) { 3520 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3521 /* 16 bytes firm_version, 17, 68-83*/ 3522 acb_firm_version++; 3523 i++; 3524 } 3525 i = 0; 3526 while(i < 16) { 3527 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3528 acb_device_map++; 3529 i++; 3530 } 3531 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3532 acb->firm_request_len = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[1]); /*firm_request_len, 1, 04-07*/ 3533 acb->firm_numbers_queue = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/ 3534 acb->firm_sdram_size = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_sdram_size, 3, 12-15*/ 3535 acb->firm_ide_channels = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_ide_channels, 4, 16-19*/ 3536 acb->firm_cfg_version = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3537 if(acb->firm_numbers_queue > ARCMSR_MAX_OUTSTANDING_CMD) 3538 acb->maxOutstanding = ARCMSR_MAX_OUTSTANDING_CMD - 1; 3539 else 3540 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3541 } 3542 /* 3543 ********************************************************************** 3544 ********************************************************************** 3545 */ 3546 static void arcmsr_get_hbd_config(struct AdapterControlBlock *acb) 3547 { 3548 char *acb_firm_model = acb->firm_model; 3549 char *acb_firm_version = acb->firm_version; 3550 char *acb_device_map = acb->device_map; 3551 size_t iop_firm_model = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]); /*firm_model,15,60-67*/ 3552 size_t iop_firm_version = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/ 3553 size_t iop_device_map = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]); 3554 int i; 3555 3556 if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) 3557 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR); 3558 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG); 3559 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 3560 printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit); 3561 } 3562 i = 0; 3563 while(i < 8) { 3564 *acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i); 3565 /* 8 bytes firm_model, 15, 60-67*/ 3566 acb_firm_model++; 3567 i++; 3568 } 3569 i = 0; 3570 while(i < 16) { 3571 *acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i); 3572 /* 16 bytes firm_version, 17, 68-83*/ 3573 acb_firm_version++; 3574 i++; 3575 } 3576 i = 0; 3577 while(i < 16) { 3578 *acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i); 3579 acb_device_map++; 3580 i++; 3581 } 3582 printf("Areca RAID adapter%d: %s F/W version %s \n", acb->pci_unit, acb->firm_model, acb->firm_version); 3583 acb->firm_request_len = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_request_len, 1, 04-07*/ 3584 acb->firm_numbers_queue = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[3]); /*firm_numbers_queue, 2, 08-11*/ 3585 acb->firm_sdram_size = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[4]); /*firm_sdram_size, 3, 12-15*/ 3586 acb->firm_ide_channels = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[5]); /*firm_ide_channels, 4, 16-19*/ 3587 acb->firm_cfg_version = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]); /*firm_cfg_version, 25, */ 3588 if(acb->firm_numbers_queue > ARCMSR_MAX_HBD_POSTQUEUE) 3589 acb->maxOutstanding = ARCMSR_MAX_HBD_POSTQUEUE - 1; 3590 else 3591 acb->maxOutstanding = acb->firm_numbers_queue - 1; 3592 } 3593 /* 3594 ********************************************************************** 3595 ********************************************************************** 3596 */ 3597 static void arcmsr_get_firmware_spec(struct AdapterControlBlock *acb) 3598 { 3599 switch (acb->adapter_type) { 3600 case ACB_ADAPTER_TYPE_A: { 3601 arcmsr_get_hba_config(acb); 3602 } 3603 break; 3604 case ACB_ADAPTER_TYPE_B: { 3605 arcmsr_get_hbb_config(acb); 3606 } 3607 break; 3608 case ACB_ADAPTER_TYPE_C: { 3609 arcmsr_get_hbc_config(acb); 3610 } 3611 break; 3612 case ACB_ADAPTER_TYPE_D: { 3613 arcmsr_get_hbd_config(acb); 3614 } 3615 break; 3616 } 3617 } 3618 /* 3619 ********************************************************************** 3620 ********************************************************************** 3621 */ 3622 static void arcmsr_wait_firmware_ready( struct AdapterControlBlock *acb) 3623 { 3624 int timeout=0; 3625 3626 switch (acb->adapter_type) { 3627 case ACB_ADAPTER_TYPE_A: { 3628 while ((CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0) 3629 { 3630 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 3631 { 3632 printf( "arcmsr%d:timed out waiting for firmware \n", acb->pci_unit); 3633 return; 3634 } 3635 UDELAY(15000); /* wait 15 milli-seconds */ 3636 } 3637 } 3638 break; 3639 case ACB_ADAPTER_TYPE_B: { 3640 while ((CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & ARCMSR_MESSAGE_FIRMWARE_OK) == 0) 3641 { 3642 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 3643 { 3644 printf( "arcmsr%d: timed out waiting for firmware \n", acb->pci_unit); 3645 return; 3646 } 3647 UDELAY(15000); /* wait 15 milli-seconds */ 3648 } 3649 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT); 3650 } 3651 break; 3652 case ACB_ADAPTER_TYPE_C: { 3653 while ((CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0) 3654 { 3655 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 3656 { 3657 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 3658 return; 3659 } 3660 UDELAY(15000); /* wait 15 milli-seconds */ 3661 } 3662 } 3663 break; 3664 case ACB_ADAPTER_TYPE_D: { 3665 while ((CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK) == 0) 3666 { 3667 if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */ 3668 { 3669 printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit); 3670 return; 3671 } 3672 UDELAY(15000); /* wait 15 milli-seconds */ 3673 } 3674 } 3675 break; 3676 } 3677 } 3678 /* 3679 ********************************************************************** 3680 ********************************************************************** 3681 */ 3682 static void arcmsr_clear_doorbell_queue_buffer( struct AdapterControlBlock *acb) 3683 { 3684 u_int32_t outbound_doorbell; 3685 3686 switch (acb->adapter_type) { 3687 case ACB_ADAPTER_TYPE_A: { 3688 /* empty doorbell Qbuffer if door bell ringed */ 3689 outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell); 3690 CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */ 3691 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK); 3692 3693 } 3694 break; 3695 case ACB_ADAPTER_TYPE_B: { 3696 CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt and message state*/ 3697 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK); 3698 /* let IOP know data has been read */ 3699 } 3700 break; 3701 case ACB_ADAPTER_TYPE_C: { 3702 /* empty doorbell Qbuffer if door bell ringed */ 3703 outbound_doorbell = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell); 3704 CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell); /*clear doorbell interrupt */ 3705 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK); 3706 CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell_clear); /* Dummy read to force pci flush */ 3707 CHIP_REG_READ32(HBC_MessageUnit, 0, inbound_doorbell); /* Dummy read to force pci flush */ 3708 } 3709 break; 3710 case ACB_ADAPTER_TYPE_D: { 3711 /* empty doorbell Qbuffer if door bell ringed */ 3712 outbound_doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell); 3713 CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_doorbell); /*clear doorbell interrupt */ 3714 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ); 3715 3716 } 3717 break; 3718 } 3719 } 3720 /* 3721 ************************************************************************ 3722 ************************************************************************ 3723 */ 3724 static u_int32_t arcmsr_iop_confirm(struct AdapterControlBlock *acb) 3725 { 3726 unsigned long srb_phyaddr; 3727 u_int32_t srb_phyaddr_hi32; 3728 u_int32_t srb_phyaddr_lo32; 3729 3730 /* 3731 ******************************************************************** 3732 ** here we need to tell iop 331 our freesrb.HighPart 3733 ** if freesrb.HighPart is not zero 3734 ******************************************************************** 3735 */ 3736 srb_phyaddr = (unsigned long) acb->srb_phyaddr.phyaddr; 3737 srb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high; 3738 srb_phyaddr_lo32 = acb->srb_phyaddr.B.phyadd_low; 3739 switch (acb->adapter_type) { 3740 case ACB_ADAPTER_TYPE_A: { 3741 if(srb_phyaddr_hi32 != 0) { 3742 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 3743 CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 3744 CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 3745 if(!arcmsr_hba_wait_msgint_ready(acb)) { 3746 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 3747 return FALSE; 3748 } 3749 } 3750 } 3751 break; 3752 /* 3753 *********************************************************************** 3754 ** if adapter type B, set window of "post command Q" 3755 *********************************************************************** 3756 */ 3757 case ACB_ADAPTER_TYPE_B: { 3758 u_int32_t post_queue_phyaddr; 3759 struct HBB_MessageUnit *phbbmu; 3760 3761 phbbmu = (struct HBB_MessageUnit *)acb->pmu; 3762 phbbmu->postq_index = 0; 3763 phbbmu->doneq_index = 0; 3764 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_SET_POST_WINDOW); 3765 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3766 printf( "arcmsr%d: 'set window of post command Q' timeout\n", acb->pci_unit); 3767 return FALSE; 3768 } 3769 post_queue_phyaddr = srb_phyaddr + ARCMSR_SRBS_POOL_SIZE 3770 + offsetof(struct HBB_MessageUnit, post_qbuffer); 3771 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */ 3772 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1], srb_phyaddr_hi32); /* normal should be zero */ 3773 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ size (256+8)*4 */ 3774 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3], post_queue_phyaddr+1056); /* doneQ size (256+8)*4 */ 3775 CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4], 1056); /* srb maxQ size must be --> [(256+8)*4] */ 3776 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_SET_CONFIG); 3777 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3778 printf( "arcmsr%d: 'set command Q window' timeout \n", acb->pci_unit); 3779 return FALSE; 3780 } 3781 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_START_DRIVER_MODE); 3782 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3783 printf( "arcmsr%d: 'start diver mode' timeout \n", acb->pci_unit); 3784 return FALSE; 3785 } 3786 } 3787 break; 3788 case ACB_ADAPTER_TYPE_C: { 3789 if(srb_phyaddr_hi32 != 0) { 3790 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); 3791 CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 3792 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 3793 CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE); 3794 if(!arcmsr_hbc_wait_msgint_ready(acb)) { 3795 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 3796 return FALSE; 3797 } 3798 } 3799 } 3800 break; 3801 case ACB_ADAPTER_TYPE_D: { 3802 u_int32_t post_queue_phyaddr, done_queue_phyaddr; 3803 struct HBD_MessageUnit0 *phbdmu; 3804 3805 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 3806 phbdmu->postq_index = 0; 3807 phbdmu->doneq_index = 0x40FF; 3808 post_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE 3809 + offsetof(struct HBD_MessageUnit0, post_qbuffer); 3810 done_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE 3811 + offsetof(struct HBD_MessageUnit0, done_qbuffer); 3812 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */ 3813 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32); 3814 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ base */ 3815 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[3], done_queue_phyaddr); /* doneQ base */ 3816 CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[4], 0x100); 3817 CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG); 3818 if(!arcmsr_hbd_wait_msgint_ready(acb)) { 3819 printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit); 3820 return FALSE; 3821 } 3822 } 3823 break; 3824 } 3825 return (TRUE); 3826 } 3827 /* 3828 ************************************************************************ 3829 ************************************************************************ 3830 */ 3831 static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb) 3832 { 3833 switch (acb->adapter_type) 3834 { 3835 case ACB_ADAPTER_TYPE_A: 3836 case ACB_ADAPTER_TYPE_C: 3837 case ACB_ADAPTER_TYPE_D: 3838 break; 3839 case ACB_ADAPTER_TYPE_B: { 3840 CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell,ARCMSR_MESSAGE_ACTIVE_EOI_MODE); 3841 if(!arcmsr_hbb_wait_msgint_ready(acb)) { 3842 printf( "arcmsr%d: 'iop enable eoi mode' timeout \n", acb->pci_unit); 3843 return; 3844 } 3845 } 3846 break; 3847 } 3848 } 3849 /* 3850 ********************************************************************** 3851 ********************************************************************** 3852 */ 3853 static void arcmsr_iop_init(struct AdapterControlBlock *acb) 3854 { 3855 u_int32_t intmask_org; 3856 3857 /* disable all outbound interrupt */ 3858 intmask_org = arcmsr_disable_allintr(acb); 3859 arcmsr_wait_firmware_ready(acb); 3860 arcmsr_iop_confirm(acb); 3861 arcmsr_get_firmware_spec(acb); 3862 /*start background rebuild*/ 3863 arcmsr_start_adapter_bgrb(acb); 3864 /* empty doorbell Qbuffer if door bell ringed */ 3865 arcmsr_clear_doorbell_queue_buffer(acb); 3866 arcmsr_enable_eoi_mode(acb); 3867 /* enable outbound Post Queue, outbound doorbell Interrupt */ 3868 arcmsr_enable_allintr(acb, intmask_org); 3869 acb->acb_flags |= ACB_F_IOP_INITED; 3870 } 3871 /* 3872 ********************************************************************** 3873 ********************************************************************** 3874 */ 3875 static void arcmsr_map_free_srb(void *arg, bus_dma_segment_t *segs, int nseg, int error) 3876 { 3877 struct AdapterControlBlock *acb = arg; 3878 struct CommandControlBlock *srb_tmp; 3879 u_int32_t i; 3880 unsigned long srb_phyaddr = (unsigned long)segs->ds_addr; 3881 3882 acb->srb_phyaddr.phyaddr = srb_phyaddr; 3883 srb_tmp = (struct CommandControlBlock *)acb->uncacheptr; 3884 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 3885 if(bus_dmamap_create(acb->dm_segs_dmat, 3886 /*flags*/0, &srb_tmp->dm_segs_dmamap) != 0) { 3887 acb->acb_flags |= ACB_F_MAPFREESRB_FAILD; 3888 printf("arcmsr%d:" 3889 " srb dmamap bus_dmamap_create error\n", acb->pci_unit); 3890 return; 3891 } 3892 if((acb->adapter_type == ACB_ADAPTER_TYPE_C) || (acb->adapter_type == ACB_ADAPTER_TYPE_D)) 3893 { 3894 srb_tmp->cdb_phyaddr_low = srb_phyaddr; 3895 srb_tmp->cdb_phyaddr_high = (u_int32_t)((srb_phyaddr >> 16) >> 16); 3896 } 3897 else 3898 srb_tmp->cdb_phyaddr_low = srb_phyaddr >> 5; 3899 srb_tmp->acb = acb; 3900 acb->srbworkingQ[i] = acb->psrb_pool[i] = srb_tmp; 3901 srb_phyaddr = srb_phyaddr + SRB_SIZE; 3902 srb_tmp = (struct CommandControlBlock *)((unsigned long)srb_tmp + SRB_SIZE); 3903 } 3904 acb->vir2phy_offset = (unsigned long)srb_tmp - (unsigned long)srb_phyaddr; 3905 } 3906 /* 3907 ************************************************************************ 3908 ************************************************************************ 3909 */ 3910 static void arcmsr_free_resource(struct AdapterControlBlock *acb) 3911 { 3912 /* remove the control device */ 3913 if(acb->ioctl_dev != NULL) { 3914 destroy_dev(acb->ioctl_dev); 3915 } 3916 bus_dmamap_unload(acb->srb_dmat, acb->srb_dmamap); 3917 bus_dmamap_destroy(acb->srb_dmat, acb->srb_dmamap); 3918 bus_dma_tag_destroy(acb->srb_dmat); 3919 bus_dma_tag_destroy(acb->dm_segs_dmat); 3920 bus_dma_tag_destroy(acb->parent_dmat); 3921 } 3922 /* 3923 ************************************************************************ 3924 ************************************************************************ 3925 */ 3926 static void arcmsr_mutex_init(struct AdapterControlBlock *acb) 3927 { 3928 ARCMSR_LOCK_INIT(&acb->isr_lock, "arcmsr isr lock"); 3929 ARCMSR_LOCK_INIT(&acb->srb_lock, "arcmsr srb lock"); 3930 ARCMSR_LOCK_INIT(&acb->postDone_lock, "arcmsr postQ lock"); 3931 ARCMSR_LOCK_INIT(&acb->qbuffer_lock, "arcmsr RW buffer lock"); 3932 } 3933 /* 3934 ************************************************************************ 3935 ************************************************************************ 3936 */ 3937 static void arcmsr_mutex_destroy(struct AdapterControlBlock *acb) 3938 { 3939 ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock); 3940 ARCMSR_LOCK_DESTROY(&acb->postDone_lock); 3941 ARCMSR_LOCK_DESTROY(&acb->srb_lock); 3942 ARCMSR_LOCK_DESTROY(&acb->isr_lock); 3943 } 3944 /* 3945 ************************************************************************ 3946 ************************************************************************ 3947 */ 3948 static u_int32_t arcmsr_initialize(device_t dev) 3949 { 3950 struct AdapterControlBlock *acb = device_get_softc(dev); 3951 u_int16_t pci_command; 3952 int i, j,max_coherent_size; 3953 u_int32_t vendor_dev_id; 3954 3955 vendor_dev_id = pci_get_devid(dev); 3956 acb->vendor_device_id = vendor_dev_id; 3957 acb->sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); 3958 switch (vendor_dev_id) { 3959 case PCIDevVenIDARC1880: 3960 case PCIDevVenIDARC1882: 3961 case PCIDevVenIDARC1213: 3962 case PCIDevVenIDARC1223: { 3963 acb->adapter_type = ACB_ADAPTER_TYPE_C; 3964 if (acb->sub_device_id == ARECA_SUB_DEV_ID_1883) 3965 acb->adapter_bus_speed = ACB_BUS_SPEED_12G; 3966 else 3967 acb->adapter_bus_speed = ACB_BUS_SPEED_6G; 3968 max_coherent_size = ARCMSR_SRBS_POOL_SIZE; 3969 } 3970 break; 3971 case PCIDevVenIDARC1214: { 3972 acb->adapter_type = ACB_ADAPTER_TYPE_D; 3973 acb->adapter_bus_speed = ACB_BUS_SPEED_6G; 3974 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBD_MessageUnit0)); 3975 } 3976 break; 3977 case PCIDevVenIDARC1200: 3978 case PCIDevVenIDARC1201: { 3979 acb->adapter_type = ACB_ADAPTER_TYPE_B; 3980 acb->adapter_bus_speed = ACB_BUS_SPEED_3G; 3981 max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit)); 3982 } 3983 break; 3984 case PCIDevVenIDARC1110: 3985 case PCIDevVenIDARC1120: 3986 case PCIDevVenIDARC1130: 3987 case PCIDevVenIDARC1160: 3988 case PCIDevVenIDARC1170: 3989 case PCIDevVenIDARC1210: 3990 case PCIDevVenIDARC1220: 3991 case PCIDevVenIDARC1230: 3992 case PCIDevVenIDARC1231: 3993 case PCIDevVenIDARC1260: 3994 case PCIDevVenIDARC1261: 3995 case PCIDevVenIDARC1270: 3996 case PCIDevVenIDARC1280: 3997 case PCIDevVenIDARC1212: 3998 case PCIDevVenIDARC1222: 3999 case PCIDevVenIDARC1380: 4000 case PCIDevVenIDARC1381: 4001 case PCIDevVenIDARC1680: 4002 case PCIDevVenIDARC1681: { 4003 acb->adapter_type = ACB_ADAPTER_TYPE_A; 4004 acb->adapter_bus_speed = ACB_BUS_SPEED_3G; 4005 max_coherent_size = ARCMSR_SRBS_POOL_SIZE; 4006 } 4007 break; 4008 default: { 4009 printf("arcmsr%d:" 4010 " unknown RAID adapter type \n", device_get_unit(dev)); 4011 return ENOMEM; 4012 } 4013 } 4014 #if __FreeBSD_version >= 700000 4015 if(bus_dma_tag_create( /*PCI parent*/ bus_get_dma_tag(dev), 4016 #else 4017 if(bus_dma_tag_create( /*PCI parent*/ NULL, 4018 #endif 4019 /*alignemnt*/ 1, 4020 /*boundary*/ 0, 4021 /*lowaddr*/ BUS_SPACE_MAXADDR, 4022 /*highaddr*/ BUS_SPACE_MAXADDR, 4023 /*filter*/ NULL, 4024 /*filterarg*/ NULL, 4025 /*maxsize*/ BUS_SPACE_MAXSIZE_32BIT, 4026 /*nsegments*/ BUS_SPACE_UNRESTRICTED, 4027 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4028 /*flags*/ 0, 4029 #if __FreeBSD_version >= 501102 4030 /*lockfunc*/ NULL, 4031 /*lockarg*/ NULL, 4032 #endif 4033 &acb->parent_dmat) != 0) 4034 { 4035 printf("arcmsr%d: parent_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4036 return ENOMEM; 4037 } 4038 4039 /* Create a single tag describing a region large enough to hold all of the s/g lists we will need. */ 4040 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat, 4041 /*alignment*/ 1, 4042 /*boundary*/ 0, 4043 #ifdef PAE 4044 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 4045 #else 4046 /*lowaddr*/ BUS_SPACE_MAXADDR, 4047 #endif 4048 /*highaddr*/ BUS_SPACE_MAXADDR, 4049 /*filter*/ NULL, 4050 /*filterarg*/ NULL, 4051 /*maxsize*/ ARCMSR_MAX_SG_ENTRIES * PAGE_SIZE * ARCMSR_MAX_FREESRB_NUM, 4052 /*nsegments*/ ARCMSR_MAX_SG_ENTRIES, 4053 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4054 /*flags*/ 0, 4055 #if __FreeBSD_version >= 501102 4056 /*lockfunc*/ busdma_lock_mutex, 4057 /*lockarg*/ &acb->isr_lock, 4058 #endif 4059 &acb->dm_segs_dmat) != 0) 4060 { 4061 bus_dma_tag_destroy(acb->parent_dmat); 4062 printf("arcmsr%d: dm_segs_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4063 return ENOMEM; 4064 } 4065 4066 /* DMA tag for our srb structures.... Allocate the freesrb memory */ 4067 if(bus_dma_tag_create( /*parent_dmat*/ acb->parent_dmat, 4068 /*alignment*/ 0x20, 4069 /*boundary*/ 0, 4070 /*lowaddr*/ BUS_SPACE_MAXADDR_32BIT, 4071 /*highaddr*/ BUS_SPACE_MAXADDR, 4072 /*filter*/ NULL, 4073 /*filterarg*/ NULL, 4074 /*maxsize*/ max_coherent_size, 4075 /*nsegments*/ 1, 4076 /*maxsegsz*/ BUS_SPACE_MAXSIZE_32BIT, 4077 /*flags*/ 0, 4078 #if __FreeBSD_version >= 501102 4079 /*lockfunc*/ NULL, 4080 /*lockarg*/ NULL, 4081 #endif 4082 &acb->srb_dmat) != 0) 4083 { 4084 bus_dma_tag_destroy(acb->dm_segs_dmat); 4085 bus_dma_tag_destroy(acb->parent_dmat); 4086 printf("arcmsr%d: srb_dmat bus_dma_tag_create failure!\n", device_get_unit(dev)); 4087 return ENXIO; 4088 } 4089 /* Allocation for our srbs */ 4090 if(bus_dmamem_alloc(acb->srb_dmat, (void **)&acb->uncacheptr, BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, &acb->srb_dmamap) != 0) { 4091 bus_dma_tag_destroy(acb->srb_dmat); 4092 bus_dma_tag_destroy(acb->dm_segs_dmat); 4093 bus_dma_tag_destroy(acb->parent_dmat); 4094 printf("arcmsr%d: srb_dmat bus_dmamem_alloc failure!\n", device_get_unit(dev)); 4095 return ENXIO; 4096 } 4097 /* And permanently map them */ 4098 if(bus_dmamap_load(acb->srb_dmat, acb->srb_dmamap, acb->uncacheptr, max_coherent_size, arcmsr_map_free_srb, acb, /*flags*/0)) { 4099 bus_dma_tag_destroy(acb->srb_dmat); 4100 bus_dma_tag_destroy(acb->dm_segs_dmat); 4101 bus_dma_tag_destroy(acb->parent_dmat); 4102 printf("arcmsr%d: srb_dmat bus_dmamap_load failure!\n", device_get_unit(dev)); 4103 return ENXIO; 4104 } 4105 pci_command = pci_read_config(dev, PCIR_COMMAND, 2); 4106 pci_command |= PCIM_CMD_BUSMASTEREN; 4107 pci_command |= PCIM_CMD_PERRESPEN; 4108 pci_command |= PCIM_CMD_MWRICEN; 4109 /* Enable Busmaster */ 4110 pci_write_config(dev, PCIR_COMMAND, pci_command, 2); 4111 switch(acb->adapter_type) { 4112 case ACB_ADAPTER_TYPE_A: { 4113 u_int32_t rid0 = PCIR_BAR(0); 4114 vm_offset_t mem_base0; 4115 4116 acb->sys_res_arcmsr[0] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, 0x1000, RF_ACTIVE); 4117 if(acb->sys_res_arcmsr[0] == NULL) { 4118 arcmsr_free_resource(acb); 4119 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4120 return ENOMEM; 4121 } 4122 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4123 arcmsr_free_resource(acb); 4124 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4125 return ENXIO; 4126 } 4127 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4128 if(mem_base0 == 0) { 4129 arcmsr_free_resource(acb); 4130 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4131 return ENXIO; 4132 } 4133 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4134 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4135 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4136 } 4137 break; 4138 case ACB_ADAPTER_TYPE_B: { 4139 struct HBB_MessageUnit *phbbmu; 4140 struct CommandControlBlock *freesrb; 4141 u_int32_t rid[]={ PCIR_BAR(0), PCIR_BAR(2) }; 4142 vm_offset_t mem_base[]={0,0}; 4143 for(i=0; i < 2; i++) { 4144 if(i == 0) { 4145 acb->sys_res_arcmsr[i] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid[i], 4146 0ul, ~0ul, sizeof(struct HBB_DOORBELL), RF_ACTIVE); 4147 } else { 4148 acb->sys_res_arcmsr[i] = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid[i], 4149 0ul, ~0ul, sizeof(struct HBB_RWBUFFER), RF_ACTIVE); 4150 } 4151 if(acb->sys_res_arcmsr[i] == NULL) { 4152 arcmsr_free_resource(acb); 4153 printf("arcmsr%d: bus_alloc_resource %d failure!\n", device_get_unit(dev), i); 4154 return ENOMEM; 4155 } 4156 if(rman_get_start(acb->sys_res_arcmsr[i]) <= 0) { 4157 arcmsr_free_resource(acb); 4158 printf("arcmsr%d: rman_get_start %d failure!\n", device_get_unit(dev), i); 4159 return ENXIO; 4160 } 4161 mem_base[i] = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[i]); 4162 if(mem_base[i] == 0) { 4163 arcmsr_free_resource(acb); 4164 printf("arcmsr%d: rman_get_virtual %d failure!\n", device_get_unit(dev), i); 4165 return ENXIO; 4166 } 4167 acb->btag[i] = rman_get_bustag(acb->sys_res_arcmsr[i]); 4168 acb->bhandle[i] = rman_get_bushandle(acb->sys_res_arcmsr[i]); 4169 } 4170 freesrb = (struct CommandControlBlock *)acb->uncacheptr; 4171 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)freesrb+ARCMSR_SRBS_POOL_SIZE); 4172 phbbmu = (struct HBB_MessageUnit *)acb->pmu; 4173 phbbmu->hbb_doorbell = (struct HBB_DOORBELL *)mem_base[0]; 4174 phbbmu->hbb_rwbuffer = (struct HBB_RWBUFFER *)mem_base[1]; 4175 } 4176 break; 4177 case ACB_ADAPTER_TYPE_C: { 4178 u_int32_t rid0 = PCIR_BAR(1); 4179 vm_offset_t mem_base0; 4180 4181 acb->sys_res_arcmsr[0] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, sizeof(struct HBC_MessageUnit), RF_ACTIVE); 4182 if(acb->sys_res_arcmsr[0] == NULL) { 4183 arcmsr_free_resource(acb); 4184 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4185 return ENOMEM; 4186 } 4187 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4188 arcmsr_free_resource(acb); 4189 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4190 return ENXIO; 4191 } 4192 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4193 if(mem_base0 == 0) { 4194 arcmsr_free_resource(acb); 4195 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4196 return ENXIO; 4197 } 4198 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4199 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4200 acb->pmu = (struct MessageUnit_UNION *)mem_base0; 4201 } 4202 break; 4203 case ACB_ADAPTER_TYPE_D: { 4204 struct HBD_MessageUnit0 *phbdmu; 4205 u_int32_t rid0 = PCIR_BAR(0); 4206 vm_offset_t mem_base0; 4207 4208 acb->sys_res_arcmsr[0] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, sizeof(struct HBD_MessageUnit), RF_ACTIVE); 4209 if(acb->sys_res_arcmsr[0] == NULL) { 4210 arcmsr_free_resource(acb); 4211 printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev)); 4212 return ENOMEM; 4213 } 4214 if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) { 4215 arcmsr_free_resource(acb); 4216 printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev)); 4217 return ENXIO; 4218 } 4219 mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]); 4220 if(mem_base0 == 0) { 4221 arcmsr_free_resource(acb); 4222 printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev)); 4223 return ENXIO; 4224 } 4225 acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]); 4226 acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]); 4227 acb->pmu = (struct MessageUnit_UNION *)((unsigned long)acb->uncacheptr+ARCMSR_SRBS_POOL_SIZE); 4228 phbdmu = (struct HBD_MessageUnit0 *)acb->pmu; 4229 phbdmu->phbdmu = (struct HBD_MessageUnit *)mem_base0; 4230 } 4231 break; 4232 } 4233 if(acb->acb_flags & ACB_F_MAPFREESRB_FAILD) { 4234 arcmsr_free_resource(acb); 4235 printf("arcmsr%d: map free srb failure!\n", device_get_unit(dev)); 4236 return ENXIO; 4237 } 4238 acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_RQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ); 4239 acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER; 4240 /* 4241 ******************************************************************** 4242 ** init raid volume state 4243 ******************************************************************** 4244 */ 4245 for(i=0; i < ARCMSR_MAX_TARGETID; i++) { 4246 for(j=0; j < ARCMSR_MAX_TARGETLUN; j++) { 4247 acb->devstate[i][j] = ARECA_RAID_GONE; 4248 } 4249 } 4250 arcmsr_iop_init(acb); 4251 return(0); 4252 } 4253 /* 4254 ************************************************************************ 4255 ************************************************************************ 4256 */ 4257 static int arcmsr_attach(device_t dev) 4258 { 4259 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 4260 u_int32_t unit=device_get_unit(dev); 4261 struct ccb_setasync csa; 4262 struct cam_devq *devq; /* Device Queue to use for this SIM */ 4263 struct resource *irqres; 4264 int rid; 4265 4266 if(acb == NULL) { 4267 printf("arcmsr%d: cannot allocate softc\n", unit); 4268 return (ENOMEM); 4269 } 4270 arcmsr_mutex_init(acb); 4271 acb->pci_dev = dev; 4272 acb->pci_unit = unit; 4273 if(arcmsr_initialize(dev)) { 4274 printf("arcmsr%d: initialize failure!\n", unit); 4275 arcmsr_mutex_destroy(acb); 4276 return ENXIO; 4277 } 4278 /* After setting up the adapter, map our interrupt */ 4279 rid = 0; 4280 irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1, RF_SHAREABLE | RF_ACTIVE); 4281 if(irqres == NULL || 4282 #if __FreeBSD_version >= 700025 4283 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, NULL, arcmsr_intr_handler, acb, &acb->ih)) { 4284 #else 4285 bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, arcmsr_intr_handler, acb, &acb->ih)) { 4286 #endif 4287 arcmsr_free_resource(acb); 4288 arcmsr_mutex_destroy(acb); 4289 printf("arcmsr%d: unable to register interrupt handler!\n", unit); 4290 return ENXIO; 4291 } 4292 acb->irqres = irqres; 4293 /* 4294 * Now let the CAM generic SCSI layer find the SCSI devices on 4295 * the bus * start queue to reset to the idle loop. * 4296 * Create device queue of SIM(s) * (MAX_START_JOB - 1) : 4297 * max_sim_transactions 4298 */ 4299 devq = cam_simq_alloc(acb->maxOutstanding); 4300 if(devq == NULL) { 4301 arcmsr_free_resource(acb); 4302 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres); 4303 arcmsr_mutex_destroy(acb); 4304 printf("arcmsr%d: cam_simq_alloc failure!\n", unit); 4305 return ENXIO; 4306 } 4307 #if __FreeBSD_version >= 700025 4308 acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, &acb->isr_lock, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq); 4309 #else 4310 acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq); 4311 #endif 4312 if(acb->psim == NULL) { 4313 arcmsr_free_resource(acb); 4314 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres); 4315 cam_simq_free(devq); 4316 arcmsr_mutex_destroy(acb); 4317 printf("arcmsr%d: cam_sim_alloc failure!\n", unit); 4318 return ENXIO; 4319 } 4320 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 4321 #if __FreeBSD_version >= 700044 4322 if(xpt_bus_register(acb->psim, dev, 0) != CAM_SUCCESS) { 4323 #else 4324 if(xpt_bus_register(acb->psim, 0) != CAM_SUCCESS) { 4325 #endif 4326 arcmsr_free_resource(acb); 4327 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres); 4328 cam_sim_free(acb->psim, /*free_devq*/TRUE); 4329 arcmsr_mutex_destroy(acb); 4330 printf("arcmsr%d: xpt_bus_register failure!\n", unit); 4331 return ENXIO; 4332 } 4333 if(xpt_create_path(&acb->ppath, /* periph */ NULL, cam_sim_path(acb->psim), CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) { 4334 arcmsr_free_resource(acb); 4335 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres); 4336 xpt_bus_deregister(cam_sim_path(acb->psim)); 4337 cam_sim_free(acb->psim, /* free_simq */ TRUE); 4338 arcmsr_mutex_destroy(acb); 4339 printf("arcmsr%d: xpt_create_path failure!\n", unit); 4340 return ENXIO; 4341 } 4342 /* 4343 **************************************************** 4344 */ 4345 xpt_setup_ccb(&csa.ccb_h, acb->ppath, /*priority*/5); 4346 csa.ccb_h.func_code = XPT_SASYNC_CB; 4347 csa.event_enable = AC_FOUND_DEVICE|AC_LOST_DEVICE; 4348 csa.callback = arcmsr_async; 4349 csa.callback_arg = acb->psim; 4350 xpt_action((union ccb *)&csa); 4351 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 4352 /* Create the control device. */ 4353 acb->ioctl_dev = make_dev(&arcmsr_cdevsw, unit, UID_ROOT, GID_WHEEL /* GID_OPERATOR */, S_IRUSR | S_IWUSR, "arcmsr%d", unit); 4354 4355 #if __FreeBSD_version < 503000 4356 acb->ioctl_dev->si_drv1 = acb; 4357 #endif 4358 #if __FreeBSD_version > 500005 4359 (void)make_dev_alias(acb->ioctl_dev, "arc%d", unit); 4360 #endif 4361 arcmsr_callout_init(&acb->devmap_callout); 4362 callout_reset(&acb->devmap_callout, 60 * hz, arcmsr_polling_devmap, acb); 4363 return (0); 4364 } 4365 4366 /* 4367 ************************************************************************ 4368 ************************************************************************ 4369 */ 4370 static int arcmsr_probe(device_t dev) 4371 { 4372 u_int32_t id; 4373 u_int16_t sub_device_id; 4374 static char buf[256]; 4375 char x_type[]={"unknown"}; 4376 char *type; 4377 int raid6 = 1; 4378 4379 if (pci_get_vendor(dev) != PCI_VENDOR_ID_ARECA) { 4380 return (ENXIO); 4381 } 4382 sub_device_id = pci_read_config(dev, PCIR_SUBDEV_0, 2); 4383 switch(id = pci_get_devid(dev)) { 4384 case PCIDevVenIDARC1110: 4385 case PCIDevVenIDARC1200: 4386 case PCIDevVenIDARC1201: 4387 case PCIDevVenIDARC1210: 4388 raid6 = 0; 4389 /*FALLTHRU*/ 4390 case PCIDevVenIDARC1120: 4391 case PCIDevVenIDARC1130: 4392 case PCIDevVenIDARC1160: 4393 case PCIDevVenIDARC1170: 4394 case PCIDevVenIDARC1220: 4395 case PCIDevVenIDARC1230: 4396 case PCIDevVenIDARC1231: 4397 case PCIDevVenIDARC1260: 4398 case PCIDevVenIDARC1261: 4399 case PCIDevVenIDARC1270: 4400 case PCIDevVenIDARC1280: 4401 type = "SATA 3G"; 4402 break; 4403 case PCIDevVenIDARC1212: 4404 case PCIDevVenIDARC1222: 4405 case PCIDevVenIDARC1380: 4406 case PCIDevVenIDARC1381: 4407 case PCIDevVenIDARC1680: 4408 case PCIDevVenIDARC1681: 4409 type = "SAS 3G"; 4410 break; 4411 case PCIDevVenIDARC1880: 4412 case PCIDevVenIDARC1882: 4413 case PCIDevVenIDARC1213: 4414 case PCIDevVenIDARC1223: 4415 if (sub_device_id == ARECA_SUB_DEV_ID_1883) 4416 type = "SAS 12G"; 4417 else 4418 type = "SAS 6G"; 4419 break; 4420 case PCIDevVenIDARC1214: 4421 type = "SATA 6G"; 4422 break; 4423 default: 4424 type = x_type; 4425 raid6 = 0; 4426 break; 4427 } 4428 if(type == x_type) 4429 return(ENXIO); 4430 sprintf(buf, "Areca %s Host Adapter RAID Controller %s\n%s\n", 4431 type, raid6 ? "(RAID6 capable)" : "", ARCMSR_DRIVER_VERSION); 4432 device_set_desc_copy(dev, buf); 4433 return (BUS_PROBE_DEFAULT); 4434 } 4435 /* 4436 ************************************************************************ 4437 ************************************************************************ 4438 */ 4439 static int arcmsr_shutdown(device_t dev) 4440 { 4441 u_int32_t i; 4442 u_int32_t intmask_org; 4443 struct CommandControlBlock *srb; 4444 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 4445 4446 /* stop adapter background rebuild */ 4447 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 4448 /* disable all outbound interrupt */ 4449 intmask_org = arcmsr_disable_allintr(acb); 4450 arcmsr_stop_adapter_bgrb(acb); 4451 arcmsr_flush_adapter_cache(acb); 4452 /* abort all outstanding command */ 4453 acb->acb_flags |= ACB_F_SCSISTOPADAPTER; 4454 acb->acb_flags &= ~ACB_F_IOP_INITED; 4455 if(acb->srboutstandingcount != 0) { 4456 /*clear and abort all outbound posted Q*/ 4457 arcmsr_done4abort_postqueue(acb); 4458 /* talk to iop 331 outstanding command aborted*/ 4459 arcmsr_abort_allcmd(acb); 4460 for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) { 4461 srb = acb->psrb_pool[i]; 4462 if(srb->srb_state == ARCMSR_SRB_START) { 4463 srb->srb_state = ARCMSR_SRB_ABORTED; 4464 srb->pccb->ccb_h.status |= CAM_REQ_ABORTED; 4465 arcmsr_srb_complete(srb, 1); 4466 } 4467 } 4468 } 4469 acb->srboutstandingcount = 0; 4470 acb->workingsrb_doneindex = 0; 4471 acb->workingsrb_startindex = 0; 4472 acb->pktRequestCount = 0; 4473 acb->pktReturnCount = 0; 4474 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 4475 return (0); 4476 } 4477 /* 4478 ************************************************************************ 4479 ************************************************************************ 4480 */ 4481 static int arcmsr_detach(device_t dev) 4482 { 4483 struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev); 4484 int i; 4485 4486 callout_stop(&acb->devmap_callout); 4487 bus_teardown_intr(dev, acb->irqres, acb->ih); 4488 arcmsr_shutdown(dev); 4489 arcmsr_free_resource(acb); 4490 for(i=0; (acb->sys_res_arcmsr[i]!=NULL) && (i<2); i++) { 4491 bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(i), acb->sys_res_arcmsr[i]); 4492 } 4493 bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres); 4494 ARCMSR_LOCK_ACQUIRE(&acb->isr_lock); 4495 xpt_async(AC_LOST_DEVICE, acb->ppath, NULL); 4496 xpt_free_path(acb->ppath); 4497 xpt_bus_deregister(cam_sim_path(acb->psim)); 4498 cam_sim_free(acb->psim, TRUE); 4499 ARCMSR_LOCK_RELEASE(&acb->isr_lock); 4500 arcmsr_mutex_destroy(acb); 4501 return (0); 4502 } 4503 4504 #ifdef ARCMSR_DEBUG1 4505 static void arcmsr_dump_data(struct AdapterControlBlock *acb) 4506 { 4507 if((acb->pktRequestCount - acb->pktReturnCount) == 0) 4508 return; 4509 printf("Command Request Count =0x%x\n",acb->pktRequestCount); 4510 printf("Command Return Count =0x%x\n",acb->pktReturnCount); 4511 printf("Command (Req-Rtn) Count =0x%x\n",(acb->pktRequestCount - acb->pktReturnCount)); 4512 printf("Queued Command Count =0x%x\n",acb->srboutstandingcount); 4513 } 4514 #endif 4515 4516