xref: /freebsd/sys/dev/arcmsr/arcmsr.c (revision 35689395b3d5478b3fab05080c71b13a7d57ca54)
1 /*
2 ********************************************************************************
3 **        OS    : FreeBSD
4 **   FILE NAME  : arcmsr.c
5 **        BY    : Erich Chen, Ching Huang
6 **   Description: SCSI RAID Device Driver for
7 **                ARECA (ARC11XX/ARC12XX/ARC13XX/ARC16XX/ARC188x)
8 **                SATA/SAS RAID HOST Adapter
9 ********************************************************************************
10 ********************************************************************************
11 **
12 ** Copyright (C) 2002 - 2012, Areca Technology Corporation All rights reserved.
13 **
14 ** Redistribution and use in source and binary forms, with or without
15 ** modification, are permitted provided that the following conditions
16 ** are met:
17 ** 1. Redistributions of source code must retain the above copyright
18 **    notice, this list of conditions and the following disclaimer.
19 ** 2. Redistributions in binary form must reproduce the above copyright
20 **    notice, this list of conditions and the following disclaimer in the
21 **    documentation and/or other materials provided with the distribution.
22 ** 3. The name of the author may not be used to endorse or promote products
23 **    derived from this software without specific prior written permission.
24 **
25 ** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
26 ** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
27 ** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
28 ** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
29 ** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT
30 ** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31 ** DATA, OR PROFITS; OR BUSINESS INTERRUPTION)HOWEVER CAUSED AND ON ANY
32 ** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33 **(INCLUDING NEGLIGENCE OR OTHERWISE)ARISING IN ANY WAY OUT OF THE USE OF
34 ** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35 ********************************************************************************
36 ** History
37 **
38 **        REV#         DATE             NAME             DESCRIPTION
39 **     1.00.00.00   03/31/2004      Erich Chen           First release
40 **     1.20.00.02   11/29/2004      Erich Chen           bug fix with arcmsr_bus_reset when PHY error
41 **     1.20.00.03   04/19/2005      Erich Chen           add SATA 24 Ports adapter type support
42 **                                                       clean unused function
43 **     1.20.00.12   09/12/2005      Erich Chen           bug fix with abort command handling,
44 **                                                       firmware version check
45 **                                                       and firmware update notify for hardware bug fix
46 **                                                       handling if none zero high part physical address
47 **                                                       of srb resource
48 **     1.20.00.13   08/18/2006      Erich Chen           remove pending srb and report busy
49 **                                                       add iop message xfer
50 **                                                       with scsi pass-through command
51 **                                                       add new device id of sas raid adapters
52 **                                                       code fit for SPARC64 & PPC
53 **     1.20.00.14   02/05/2007      Erich Chen           bug fix for incorrect ccb_h.status report
54 **                                                       and cause g_vfs_done() read write error
55 **     1.20.00.15   10/10/2007      Erich Chen           support new RAID adapter type ARC120x
56 **     1.20.00.16   10/10/2009      Erich Chen           Bug fix for RAID adapter type ARC120x
57 **                                                       bus_dmamem_alloc() with BUS_DMA_ZERO
58 **     1.20.00.17   07/15/2010      Ching Huang          Added support ARC1880
59 **                                                       report CAM_DEV_NOT_THERE instead of CAM_SEL_TIMEOUT when device failed,
60 **                                                       prevent cam_periph_error removing all LUN devices of one Target id
61 **                                                       for any one LUN device failed
62 **     1.20.00.18   10/14/2010      Ching Huang          Fixed "inquiry data fails comparion at DV1 step"
63 **                  10/25/2010      Ching Huang          Fixed bad range input in bus_alloc_resource for ADAPTER_TYPE_B
64 **     1.20.00.19   11/11/2010      Ching Huang          Fixed arcmsr driver prevent arcsas support for Areca SAS HBA ARC13x0
65 **     1.20.00.20   12/08/2010      Ching Huang          Avoid calling atomic_set_int function
66 **     1.20.00.21   02/08/2011      Ching Huang          Implement I/O request timeout
67 **                  02/14/2011      Ching Huang          Modified pktRequestCount
68 **     1.20.00.21   03/03/2011      Ching Huang          if a command timeout, then wait its ccb back before free it
69 **     1.20.00.22   07/04/2011      Ching Huang          Fixed multiple MTX panic
70 **     1.20.00.23   10/28/2011      Ching Huang          Added TIMEOUT_DELAY in case of too many HDDs need to start
71 **     1.20.00.23   11/08/2011      Ching Huang          Added report device transfer speed
72 **     1.20.00.23   01/30/2012      Ching Huang          Fixed Request requeued and Retrying command
73 **     1.20.00.24   06/11/2012      Ching Huang          Fixed return sense data condition
74 **     1.20.00.25   08/17/2012      Ching Huang          Fixed hotplug device no function on type A adapter
75 **     1.20.00.26   12/14/2012      Ching Huang          Added support ARC1214,1224
76 ******************************************************************************************
77 */
78 
79 #include <sys/cdefs.h>
80 __FBSDID("$FreeBSD$");
81 
82 #if 0
83 #define ARCMSR_DEBUG1			1
84 #endif
85 #include <sys/param.h>
86 #include <sys/systm.h>
87 #include <sys/malloc.h>
88 #include <sys/kernel.h>
89 #include <sys/bus.h>
90 #include <sys/queue.h>
91 #include <sys/stat.h>
92 #include <sys/devicestat.h>
93 #include <sys/kthread.h>
94 #include <sys/module.h>
95 #include <sys/proc.h>
96 #include <sys/lock.h>
97 #include <sys/sysctl.h>
98 #include <sys/poll.h>
99 #include <sys/ioccom.h>
100 #include <vm/vm.h>
101 #include <vm/vm_param.h>
102 #include <vm/pmap.h>
103 
104 #include <isa/rtc.h>
105 
106 #include <machine/bus.h>
107 #include <machine/resource.h>
108 #include <machine/atomic.h>
109 #include <sys/conf.h>
110 #include <sys/rman.h>
111 
112 #include <cam/cam.h>
113 #include <cam/cam_ccb.h>
114 #include <cam/cam_sim.h>
115 #include <cam/cam_periph.h>
116 #include <cam/cam_xpt_periph.h>
117 #include <cam/cam_xpt_sim.h>
118 #include <cam/cam_debug.h>
119 #include <cam/scsi/scsi_all.h>
120 #include <cam/scsi/scsi_message.h>
121 /*
122 **************************************************************************
123 **************************************************************************
124 */
125 #if __FreeBSD_version >= 500005
126     #include <sys/selinfo.h>
127     #include <sys/mutex.h>
128     #include <sys/endian.h>
129     #include <dev/pci/pcivar.h>
130     #include <dev/pci/pcireg.h>
131 #else
132     #include <sys/select.h>
133     #include <pci/pcivar.h>
134     #include <pci/pcireg.h>
135 #endif
136 
137 #if !defined(CAM_NEW_TRAN_CODE) && __FreeBSD_version >= 700025
138 #define	CAM_NEW_TRAN_CODE	1
139 #endif
140 
141 #if __FreeBSD_version > 500000
142 #define arcmsr_callout_init(a)	callout_init(a, /*mpsafe*/1);
143 #else
144 #define arcmsr_callout_init(a)	callout_init(a);
145 #endif
146 
147 #define ARCMSR_DRIVER_VERSION	"Driver Version 1.20.00.26 2013-01-08"
148 #include <dev/arcmsr/arcmsr.h>
149 /*
150 **************************************************************************
151 **************************************************************************
152 */
153 static void arcmsr_free_srb(struct CommandControlBlock *srb);
154 static struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb);
155 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb);
156 static int arcmsr_probe(device_t dev);
157 static int arcmsr_attach(device_t dev);
158 static int arcmsr_detach(device_t dev);
159 static u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg);
160 static void arcmsr_iop_parking(struct AdapterControlBlock *acb);
161 static int arcmsr_shutdown(device_t dev);
162 static void arcmsr_interrupt(struct AdapterControlBlock *acb);
163 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb);
164 static void arcmsr_free_resource(struct AdapterControlBlock *acb);
165 static void arcmsr_bus_reset(struct AdapterControlBlock *acb);
166 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb);
167 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb);
168 static void arcmsr_iop_init(struct AdapterControlBlock *acb);
169 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb);
170 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb, struct QBUFFER *prbuffer);
171 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb);
172 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb);
173 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag);
174 static void arcmsr_iop_reset(struct AdapterControlBlock *acb);
175 static void arcmsr_report_sense_info(struct CommandControlBlock *srb);
176 static void arcmsr_build_srb(struct CommandControlBlock *srb, bus_dma_segment_t *dm_segs, u_int32_t nseg);
177 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb);
178 static int arcmsr_resume(device_t dev);
179 static int arcmsr_suspend(device_t dev);
180 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb);
181 static void	arcmsr_polling_devmap(void *arg);
182 static void	arcmsr_srb_timeout(void *arg);
183 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb);
184 #ifdef ARCMSR_DEBUG1
185 static void arcmsr_dump_data(struct AdapterControlBlock *acb);
186 #endif
187 /*
188 **************************************************************************
189 **************************************************************************
190 */
191 static void UDELAY(u_int32_t us) { DELAY(us); }
192 /*
193 **************************************************************************
194 **************************************************************************
195 */
196 static bus_dmamap_callback_t arcmsr_map_free_srb;
197 static bus_dmamap_callback_t arcmsr_execute_srb;
198 /*
199 **************************************************************************
200 **************************************************************************
201 */
202 static d_open_t	arcmsr_open;
203 static d_close_t arcmsr_close;
204 static d_ioctl_t arcmsr_ioctl;
205 
206 static device_method_t arcmsr_methods[]={
207 	DEVMETHOD(device_probe,		arcmsr_probe),
208 	DEVMETHOD(device_attach,	arcmsr_attach),
209 	DEVMETHOD(device_detach,	arcmsr_detach),
210 	DEVMETHOD(device_shutdown,	arcmsr_shutdown),
211 	DEVMETHOD(device_suspend,	arcmsr_suspend),
212 	DEVMETHOD(device_resume,	arcmsr_resume),
213 
214 #if __FreeBSD_version >= 803000
215 	DEVMETHOD_END
216 #else
217 	{ 0, 0 }
218 #endif
219 };
220 
221 static driver_t arcmsr_driver={
222 	"arcmsr", arcmsr_methods, sizeof(struct AdapterControlBlock)
223 };
224 
225 static devclass_t arcmsr_devclass;
226 DRIVER_MODULE(arcmsr, pci, arcmsr_driver, arcmsr_devclass, 0, 0);
227 MODULE_DEPEND(arcmsr, pci, 1, 1, 1);
228 MODULE_DEPEND(arcmsr, cam, 1, 1, 1);
229 #ifndef BUS_DMA_COHERENT
230 	#define	BUS_DMA_COHERENT	0x04	/* hint: map memory in a coherent way */
231 #endif
232 #if __FreeBSD_version >= 501000
233 static struct cdevsw arcmsr_cdevsw={
234 	#if __FreeBSD_version >= 503000
235 		.d_version = D_VERSION,
236 	#endif
237 	#if (__FreeBSD_version>=503000 && __FreeBSD_version<600034)
238 		.d_flags   = D_NEEDGIANT,
239 	#endif
240 		.d_open    = arcmsr_open, 	/* open     */
241 		.d_close   = arcmsr_close, 	/* close    */
242 		.d_ioctl   = arcmsr_ioctl, 	/* ioctl    */
243 		.d_name    = "arcmsr", 		/* name     */
244 	};
245 #else
246 	#define ARCMSR_CDEV_MAJOR	180
247 
248 static struct cdevsw arcmsr_cdevsw = {
249 		arcmsr_open,				/* open     */
250 		arcmsr_close,				/* close    */
251 		noread,						/* read     */
252 		nowrite,					/* write    */
253 		arcmsr_ioctl,				/* ioctl    */
254 		nopoll,						/* poll     */
255 		nommap,						/* mmap     */
256 		nostrategy,					/* strategy */
257 		"arcmsr",					/* name     */
258 		ARCMSR_CDEV_MAJOR,			/* major    */
259 		nodump,						/* dump     */
260 		nopsize,					/* psize    */
261 		0							/* flags    */
262 	};
263 #endif
264 /*
265 **************************************************************************
266 **************************************************************************
267 */
268 #if __FreeBSD_version < 500005
269 	static int arcmsr_open(dev_t dev, int flags, int fmt, struct proc *proc)
270 #else
271 	#if __FreeBSD_version < 503000
272 	static int arcmsr_open(dev_t dev, int flags, int fmt, struct thread *proc)
273 	#else
274 	static int arcmsr_open(struct cdev *dev, int flags, int fmt, struct thread *proc)
275 	#endif
276 #endif
277 {
278 	#if __FreeBSD_version < 503000
279 		struct AdapterControlBlock *acb = dev->si_drv1;
280 	#else
281 		int	unit = dev2unit(dev);
282 		struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit);
283 	#endif
284 	if(acb == NULL) {
285 		return ENXIO;
286 	}
287 	return (0);
288 }
289 /*
290 **************************************************************************
291 **************************************************************************
292 */
293 #if __FreeBSD_version < 500005
294 	static int arcmsr_close(dev_t dev, int flags, int fmt, struct proc *proc)
295 #else
296 	#if __FreeBSD_version < 503000
297 	static int arcmsr_close(dev_t dev, int flags, int fmt, struct thread *proc)
298 	#else
299 	static int arcmsr_close(struct cdev *dev, int flags, int fmt, struct thread *proc)
300 	#endif
301 #endif
302 {
303 	#if __FreeBSD_version < 503000
304 		struct AdapterControlBlock *acb = dev->si_drv1;
305 	#else
306 		int	unit = dev2unit(dev);
307 		struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit);
308 	#endif
309 	if(acb == NULL) {
310 		return ENXIO;
311 	}
312 	return 0;
313 }
314 /*
315 **************************************************************************
316 **************************************************************************
317 */
318 #if __FreeBSD_version < 500005
319 	static int arcmsr_ioctl(dev_t dev, u_long ioctl_cmd, caddr_t arg, int flags, struct proc *proc)
320 #else
321 	#if __FreeBSD_version < 503000
322 	static int arcmsr_ioctl(dev_t dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc)
323 	#else
324 	static int arcmsr_ioctl(struct cdev *dev, u_long ioctl_cmd, caddr_t arg, int flags, struct thread *proc)
325 	#endif
326 #endif
327 {
328 	#if __FreeBSD_version < 503000
329 		struct AdapterControlBlock *acb = dev->si_drv1;
330 	#else
331 		int	unit = dev2unit(dev);
332 		struct AdapterControlBlock *acb = devclass_get_softc(arcmsr_devclass, unit);
333 	#endif
334 
335 	if(acb == NULL) {
336 		return ENXIO;
337 	}
338 	return (arcmsr_iop_ioctlcmd(acb, ioctl_cmd, arg));
339 }
340 /*
341 **********************************************************************
342 **********************************************************************
343 */
344 static u_int32_t arcmsr_disable_allintr( struct AdapterControlBlock *acb)
345 {
346 	u_int32_t intmask_org = 0;
347 
348 	switch (acb->adapter_type) {
349 	case ACB_ADAPTER_TYPE_A: {
350 			/* disable all outbound interrupt */
351 			intmask_org = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intmask); /* disable outbound message0 int */
352 			CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org|ARCMSR_MU_OUTBOUND_ALL_INTMASKENABLE);
353 		}
354 		break;
355 	case ACB_ADAPTER_TYPE_B: {
356 			/* disable all outbound interrupt */
357 			intmask_org = CHIP_REG_READ32(HBB_DOORBELL,
358 						0, iop2drv_doorbell_mask) & (~ARCMSR_IOP2DRV_MESSAGE_CMD_DONE); /* disable outbound message0 int */
359 			CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell_mask, 0); /* disable all interrupt */
360 		}
361 		break;
362 	case ACB_ADAPTER_TYPE_C: {
363 			/* disable all outbound interrupt */
364 			intmask_org = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_mask)	; /* disable outbound message0 int */
365 			CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org|ARCMSR_HBCMU_ALL_INTMASKENABLE);
366 		}
367 		break;
368 	case ACB_ADAPTER_TYPE_D: {
369 			/* disable all outbound interrupt */
370 			intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable)	; /* disable outbound message0 int */
371 			CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE);
372 		}
373 		break;
374 	}
375 	return (intmask_org);
376 }
377 /*
378 **********************************************************************
379 **********************************************************************
380 */
381 static void arcmsr_enable_allintr( struct AdapterControlBlock *acb, u_int32_t intmask_org)
382 {
383 	u_int32_t mask;
384 
385 	switch (acb->adapter_type) {
386 	case ACB_ADAPTER_TYPE_A: {
387 			/* enable outbound Post Queue, outbound doorbell Interrupt */
388 			mask = ~(ARCMSR_MU_OUTBOUND_POSTQUEUE_INTMASKENABLE|ARCMSR_MU_OUTBOUND_DOORBELL_INTMASKENABLE|ARCMSR_MU_OUTBOUND_MESSAGE0_INTMASKENABLE);
389 			CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intmask, intmask_org & mask);
390 			acb->outbound_int_enable = ~(intmask_org & mask) & 0x000000ff;
391 		}
392 		break;
393 	case ACB_ADAPTER_TYPE_B: {
394 			/* enable ARCMSR_IOP2DRV_MESSAGE_CMD_DONE */
395 			mask = (ARCMSR_IOP2DRV_DATA_WRITE_OK|ARCMSR_IOP2DRV_DATA_READ_OK|ARCMSR_IOP2DRV_CDB_DONE|ARCMSR_IOP2DRV_MESSAGE_CMD_DONE);
396 			CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell_mask, intmask_org | mask); /*1=interrupt enable, 0=interrupt disable*/
397 			acb->outbound_int_enable = (intmask_org | mask) & 0x0000000f;
398 		}
399 		break;
400 	case ACB_ADAPTER_TYPE_C: {
401 			/* enable outbound Post Queue, outbound doorbell Interrupt */
402 			mask = ~(ARCMSR_HBCMU_UTILITY_A_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR_MASK | ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR_MASK);
403 			CHIP_REG_WRITE32(HBC_MessageUnit, 0, host_int_mask, intmask_org & mask);
404 			acb->outbound_int_enable = ~(intmask_org & mask) & 0x0000000f;
405 		}
406 		break;
407 	case ACB_ADAPTER_TYPE_D: {
408 			/* enable outbound Post Queue, outbound doorbell Interrupt */
409 			mask = ARCMSR_HBDMU_ALL_INT_ENABLE;
410 			CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | mask);
411 			CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable);
412 			acb->outbound_int_enable = mask;
413 		}
414 		break;
415 	}
416 }
417 /*
418 **********************************************************************
419 **********************************************************************
420 */
421 static u_int8_t arcmsr_hba_wait_msgint_ready(struct AdapterControlBlock *acb)
422 {
423 	u_int32_t Index;
424 	u_int8_t Retries = 0x00;
425 
426 	do {
427 		for(Index=0; Index < 100; Index++) {
428 			if(CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
429 				CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);/*clear interrupt*/
430 				return TRUE;
431 			}
432 			UDELAY(10000);
433 		}/*max 1 seconds*/
434 	}while(Retries++ < 20);/*max 20 sec*/
435 	return (FALSE);
436 }
437 /*
438 **********************************************************************
439 **********************************************************************
440 */
441 static u_int8_t arcmsr_hbb_wait_msgint_ready(struct AdapterControlBlock *acb)
442 {
443 	u_int32_t Index;
444 	u_int8_t Retries = 0x00;
445 
446 	do {
447 		for(Index=0; Index < 100; Index++) {
448 			if(CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
449 				CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt*/
450 				CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
451 				return TRUE;
452 			}
453 			UDELAY(10000);
454 		}/*max 1 seconds*/
455 	}while(Retries++ < 20);/*max 20 sec*/
456 	return (FALSE);
457 }
458 /*
459 **********************************************************************
460 **********************************************************************
461 */
462 static u_int8_t arcmsr_hbc_wait_msgint_ready(struct AdapterControlBlock *acb)
463 {
464 	u_int32_t Index;
465 	u_int8_t Retries = 0x00;
466 
467 	do {
468 		for(Index=0; Index < 100; Index++) {
469 			if(CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
470 				CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);/*clear interrupt*/
471 				return TRUE;
472 			}
473 			UDELAY(10000);
474 		}/*max 1 seconds*/
475 	}while(Retries++ < 20);/*max 20 sec*/
476 	return (FALSE);
477 }
478 /*
479 **********************************************************************
480 **********************************************************************
481 */
482 static u_int8_t arcmsr_hbd_wait_msgint_ready(struct AdapterControlBlock *acb)
483 {
484 	u_int32_t Index;
485 	u_int8_t Retries = 0x00;
486 
487 	do {
488 		for(Index=0; Index < 100; Index++) {
489 			if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) {
490 				CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);/*clear interrupt*/
491 				return TRUE;
492 			}
493 			UDELAY(10000);
494 		}/*max 1 seconds*/
495 	}while(Retries++ < 20);/*max 20 sec*/
496 	return (FALSE);
497 }
498 /*
499 ************************************************************************
500 ************************************************************************
501 */
502 static void arcmsr_flush_hba_cache(struct AdapterControlBlock *acb)
503 {
504 	int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
505 
506 	CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
507 	do {
508 		if(arcmsr_hba_wait_msgint_ready(acb)) {
509 			break;
510 		} else {
511 			retry_count--;
512 		}
513 	}while(retry_count != 0);
514 }
515 /*
516 ************************************************************************
517 ************************************************************************
518 */
519 static void arcmsr_flush_hbb_cache(struct AdapterControlBlock *acb)
520 {
521 	int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
522 
523 	CHIP_REG_WRITE32(HBB_DOORBELL,
524 	0, drv2iop_doorbell, ARCMSR_MESSAGE_FLUSH_CACHE);
525 	do {
526 		if(arcmsr_hbb_wait_msgint_ready(acb)) {
527 			break;
528 		} else {
529 			retry_count--;
530 		}
531 	}while(retry_count != 0);
532 }
533 /*
534 ************************************************************************
535 ************************************************************************
536 */
537 static void arcmsr_flush_hbc_cache(struct AdapterControlBlock *acb)
538 {
539 	int retry_count = 30;/* enlarge wait flush adapter cache time: 10 minute */
540 
541 	CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
542 	CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
543 	do {
544 		if(arcmsr_hbc_wait_msgint_ready(acb)) {
545 			break;
546 		} else {
547 			retry_count--;
548 		}
549 	}while(retry_count != 0);
550 }
551 /*
552 ************************************************************************
553 ************************************************************************
554 */
555 static void arcmsr_flush_hbd_cache(struct AdapterControlBlock *acb)
556 {
557 	int retry_count = 30; /* enlarge wait flush adapter cache time: 10 minute */
558 
559 	CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_FLUSH_CACHE);
560 	do {
561 		if(arcmsr_hbd_wait_msgint_ready(acb)) {
562 			break;
563 		} else {
564 			retry_count--;
565 		}
566 	}while(retry_count != 0);
567 }
568 /*
569 ************************************************************************
570 ************************************************************************
571 */
572 static void arcmsr_flush_adapter_cache(struct AdapterControlBlock *acb)
573 {
574 	switch (acb->adapter_type) {
575 	case ACB_ADAPTER_TYPE_A: {
576 			arcmsr_flush_hba_cache(acb);
577 		}
578 		break;
579 	case ACB_ADAPTER_TYPE_B: {
580 			arcmsr_flush_hbb_cache(acb);
581 		}
582 		break;
583 	case ACB_ADAPTER_TYPE_C: {
584 			arcmsr_flush_hbc_cache(acb);
585 		}
586 		break;
587 	case ACB_ADAPTER_TYPE_D: {
588 			arcmsr_flush_hbd_cache(acb);
589 		}
590 		break;
591 	}
592 }
593 /*
594 *******************************************************************************
595 *******************************************************************************
596 */
597 static int arcmsr_suspend(device_t dev)
598 {
599 	struct AdapterControlBlock	*acb = device_get_softc(dev);
600 
601 	/* flush controller */
602 	arcmsr_iop_parking(acb);
603 	/* disable all outbound interrupt */
604 	arcmsr_disable_allintr(acb);
605 	return(0);
606 }
607 /*
608 *******************************************************************************
609 *******************************************************************************
610 */
611 static int arcmsr_resume(device_t dev)
612 {
613 	struct AdapterControlBlock	*acb = device_get_softc(dev);
614 
615 	arcmsr_iop_init(acb);
616 	return(0);
617 }
618 /*
619 *********************************************************************************
620 *********************************************************************************
621 */
622 static void arcmsr_async(void *cb_arg, u_int32_t code, struct cam_path *path, void *arg)
623 {
624 	struct AdapterControlBlock *acb;
625 	u_int8_t target_id, target_lun;
626 	struct cam_sim *sim;
627 
628 	sim = (struct cam_sim *) cb_arg;
629 	acb =(struct AdapterControlBlock *) cam_sim_softc(sim);
630 	switch (code) {
631 	case AC_LOST_DEVICE:
632 		target_id = xpt_path_target_id(path);
633 		target_lun = xpt_path_lun_id(path);
634 		if((target_id > ARCMSR_MAX_TARGETID) || (target_lun > ARCMSR_MAX_TARGETLUN)) {
635 			break;
636 		}
637 	//	printf("%s:scsi id=%d lun=%d device lost \n", device_get_name(acb->pci_dev), target_id, target_lun);
638 		break;
639 	default:
640 		break;
641 	}
642 }
643 /*
644 **********************************************************************
645 **********************************************************************
646 */
647 static void arcmsr_report_sense_info(struct CommandControlBlock *srb)
648 {
649 	union ccb *pccb = srb->pccb;
650 
651 	pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
652 	pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
653 	if(pccb->csio.sense_len) {
654 		memset(&pccb->csio.sense_data, 0, sizeof(pccb->csio.sense_data));
655 		memcpy(&pccb->csio.sense_data, srb->arcmsr_cdb.SenseData,
656 		get_min(sizeof(struct SENSE_DATA), sizeof(pccb->csio.sense_data)));
657 		((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70); /* Valid,ErrorCode */
658 		pccb->ccb_h.status |= CAM_AUTOSNS_VALID;
659 	}
660 }
661 /*
662 *********************************************************************
663 *********************************************************************
664 */
665 static void arcmsr_abort_hba_allcmd(struct AdapterControlBlock *acb)
666 {
667 	CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
668 	if(!arcmsr_hba_wait_msgint_ready(acb)) {
669 		printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
670 	}
671 }
672 /*
673 *********************************************************************
674 *********************************************************************
675 */
676 static void arcmsr_abort_hbb_allcmd(struct AdapterControlBlock *acb)
677 {
678 	CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_ABORT_CMD);
679 	if(!arcmsr_hbb_wait_msgint_ready(acb)) {
680 		printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
681 	}
682 }
683 /*
684 *********************************************************************
685 *********************************************************************
686 */
687 static void arcmsr_abort_hbc_allcmd(struct AdapterControlBlock *acb)
688 {
689 	CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
690 	CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
691 	if(!arcmsr_hbc_wait_msgint_ready(acb)) {
692 		printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
693 	}
694 }
695 /*
696 *********************************************************************
697 *********************************************************************
698 */
699 static void arcmsr_abort_hbd_allcmd(struct AdapterControlBlock *acb)
700 {
701 	CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_ABORT_CMD);
702 	if(!arcmsr_hbd_wait_msgint_ready(acb)) {
703 		printf("arcmsr%d: wait 'abort all outstanding command' timeout \n", acb->pci_unit);
704 	}
705 }
706 /*
707 *********************************************************************
708 *********************************************************************
709 */
710 static void arcmsr_abort_allcmd(struct AdapterControlBlock *acb)
711 {
712 	switch (acb->adapter_type) {
713 	case ACB_ADAPTER_TYPE_A: {
714 			arcmsr_abort_hba_allcmd(acb);
715 		}
716 		break;
717 	case ACB_ADAPTER_TYPE_B: {
718 			arcmsr_abort_hbb_allcmd(acb);
719 		}
720 		break;
721 	case ACB_ADAPTER_TYPE_C: {
722 			arcmsr_abort_hbc_allcmd(acb);
723 		}
724 		break;
725 	case ACB_ADAPTER_TYPE_D: {
726 			arcmsr_abort_hbd_allcmd(acb);
727 		}
728 		break;
729 	}
730 }
731 /*
732 **********************************************************************
733 **********************************************************************
734 */
735 static void arcmsr_srb_complete(struct CommandControlBlock *srb, int stand_flag)
736 {
737 	struct AdapterControlBlock *acb = srb->acb;
738 	union ccb *pccb = srb->pccb;
739 
740 	if(srb->srb_flags & SRB_FLAG_TIMER_START)
741 		callout_stop(&srb->ccb_callout);
742 	if((pccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
743 		bus_dmasync_op_t op;
744 
745 		if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
746 			op = BUS_DMASYNC_POSTREAD;
747 		} else {
748 			op = BUS_DMASYNC_POSTWRITE;
749 		}
750 		bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op);
751 		bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap);
752 	}
753 	if(stand_flag == 1) {
754 		atomic_subtract_int(&acb->srboutstandingcount, 1);
755 		if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) && (
756 		acb->srboutstandingcount < (acb->firm_numbers_queue -10))) {
757 			acb->acb_flags &= ~ACB_F_CAM_DEV_QFRZN;
758 			pccb->ccb_h.status |= CAM_RELEASE_SIMQ;
759 		}
760 	}
761 	if(srb->srb_state != ARCMSR_SRB_TIMEOUT)
762 		arcmsr_free_srb(srb);
763 	acb->pktReturnCount++;
764 	xpt_done(pccb);
765 }
766 /*
767 **************************************************************************
768 **************************************************************************
769 */
770 static void arcmsr_report_srb_state(struct AdapterControlBlock *acb, struct CommandControlBlock *srb, u_int16_t error)
771 {
772 	int target, lun;
773 
774 	target = srb->pccb->ccb_h.target_id;
775 	lun = srb->pccb->ccb_h.target_lun;
776 	if(error == FALSE) {
777 		if(acb->devstate[target][lun] == ARECA_RAID_GONE) {
778 			acb->devstate[target][lun] = ARECA_RAID_GOOD;
779 		}
780 		srb->pccb->ccb_h.status |= CAM_REQ_CMP;
781 		arcmsr_srb_complete(srb, 1);
782 	} else {
783 		switch(srb->arcmsr_cdb.DeviceStatus) {
784 		case ARCMSR_DEV_SELECT_TIMEOUT: {
785 				if(acb->devstate[target][lun] == ARECA_RAID_GOOD) {
786 					printf( "arcmsr%d: Target=%x, Lun=%x, selection timeout, raid volume was lost\n", acb->pci_unit, target, lun);
787 				}
788 				acb->devstate[target][lun] = ARECA_RAID_GONE;
789 				srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
790 				arcmsr_srb_complete(srb, 1);
791 			}
792 			break;
793 		case ARCMSR_DEV_ABORTED:
794 		case ARCMSR_DEV_INIT_FAIL: {
795 				acb->devstate[target][lun] = ARECA_RAID_GONE;
796 				srb->pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
797 				arcmsr_srb_complete(srb, 1);
798 			}
799 			break;
800 		case SCSISTAT_CHECK_CONDITION: {
801 				acb->devstate[target][lun] = ARECA_RAID_GOOD;
802 				arcmsr_report_sense_info(srb);
803 				arcmsr_srb_complete(srb, 1);
804 			}
805 			break;
806 		default:
807 			printf("arcmsr%d: scsi id=%d lun=%d isr got command error done,but got unknown DeviceStatus=0x%x \n"
808 					, acb->pci_unit, target, lun ,srb->arcmsr_cdb.DeviceStatus);
809 			acb->devstate[target][lun] = ARECA_RAID_GONE;
810 			srb->pccb->ccb_h.status |= CAM_UNCOR_PARITY;
811 			/*unknown error or crc error just for retry*/
812 			arcmsr_srb_complete(srb, 1);
813 			break;
814 		}
815 	}
816 }
817 /*
818 **************************************************************************
819 **************************************************************************
820 */
821 static void arcmsr_drain_donequeue(struct AdapterControlBlock *acb, u_int32_t flag_srb, u_int16_t error)
822 {
823 	struct CommandControlBlock *srb;
824 
825 	/* check if command done with no error*/
826 	switch (acb->adapter_type) {
827 	case ACB_ADAPTER_TYPE_C:
828 	case ACB_ADAPTER_TYPE_D:
829 		srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0)); /*frame must be 32 bytes aligned*/
830 		break;
831 	case ACB_ADAPTER_TYPE_A:
832 	case ACB_ADAPTER_TYPE_B:
833 	default:
834 		srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
835 		break;
836 	}
837 	if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
838 		if(srb->srb_state == ARCMSR_SRB_TIMEOUT) {
839 			arcmsr_free_srb(srb);
840 			printf("arcmsr%d: srb='%p' return srb has been timeouted\n", acb->pci_unit, srb);
841 			return;
842 		}
843 		printf("arcmsr%d: return srb has been completed\n"
844 			"srb='%p' srb_state=0x%x outstanding srb count=%d \n",
845 			acb->pci_unit, srb, srb->srb_state, acb->srboutstandingcount);
846 		return;
847 	}
848 	arcmsr_report_srb_state(acb, srb, error);
849 }
850 /*
851 **************************************************************************
852 **************************************************************************
853 */
854 static void	arcmsr_srb_timeout(void *arg)
855 {
856 	struct CommandControlBlock *srb = (struct CommandControlBlock *)arg;
857 	struct AdapterControlBlock *acb;
858 	int target, lun;
859 	u_int8_t cmd;
860 
861 	target = srb->pccb->ccb_h.target_id;
862 	lun = srb->pccb->ccb_h.target_lun;
863 	acb = srb->acb;
864 	ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
865 	if(srb->srb_state == ARCMSR_SRB_START)
866 	{
867 		cmd = srb->pccb->csio.cdb_io.cdb_bytes[0];
868 		srb->srb_state = ARCMSR_SRB_TIMEOUT;
869 		srb->pccb->ccb_h.status |= CAM_CMD_TIMEOUT;
870 		arcmsr_srb_complete(srb, 1);
871 		printf("arcmsr%d: scsi id %d lun %d cmd=0x%x srb='%p' ccb command time out!\n",
872 				 acb->pci_unit, target, lun, cmd, srb);
873 	}
874 	ARCMSR_LOCK_RELEASE(&acb->isr_lock);
875 #ifdef ARCMSR_DEBUG1
876     	arcmsr_dump_data(acb);
877 #endif
878 }
879 
880 /*
881 **********************************************************************
882 **********************************************************************
883 */
884 static void arcmsr_done4abort_postqueue(struct AdapterControlBlock *acb)
885 {
886 	int i=0;
887 	u_int32_t flag_srb;
888 	u_int16_t error;
889 
890 	switch (acb->adapter_type) {
891 	case ACB_ADAPTER_TYPE_A: {
892 			u_int32_t outbound_intstatus;
893 
894 			/*clear and abort all outbound posted Q*/
895 			outbound_intstatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
896 			CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);/*clear interrupt*/
897 			while(((flag_srb=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_queueport)) != 0xFFFFFFFF) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
898                 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
899 				arcmsr_drain_donequeue(acb, flag_srb, error);
900 			}
901 		}
902 		break;
903 	case ACB_ADAPTER_TYPE_B: {
904 			struct HBB_MessageUnit *phbbmu=(struct HBB_MessageUnit *)acb->pmu;
905 
906 			/*clear all outbound posted Q*/
907 			CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */
908 			for(i=0; i < ARCMSR_MAX_HBB_POSTQUEUE; i++) {
909 				if((flag_srb = phbbmu->done_qbuffer[i]) != 0) {
910 					phbbmu->done_qbuffer[i] = 0;
911                 	error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
912 					arcmsr_drain_donequeue(acb, flag_srb, error);
913 				}
914 				phbbmu->post_qbuffer[i] = 0;
915 			}/*drain reply FIFO*/
916 			phbbmu->doneq_index = 0;
917 			phbbmu->postq_index = 0;
918 		}
919 		break;
920 	case ACB_ADAPTER_TYPE_C: {
921 
922 			while((CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) && (i++ < ARCMSR_MAX_OUTSTANDING_CMD)) {
923 				flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
924                 error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
925 				arcmsr_drain_donequeue(acb, flag_srb, error);
926 			}
927 		}
928 		break;
929 	case ACB_ADAPTER_TYPE_D: {
930 			arcmsr_hbd_postqueue_isr(acb);
931 		}
932 		break;
933 	}
934 }
935 /*
936 ****************************************************************************
937 ****************************************************************************
938 */
939 static void arcmsr_iop_reset(struct AdapterControlBlock *acb)
940 {
941 	struct CommandControlBlock *srb;
942 	u_int32_t intmask_org;
943 	u_int32_t i=0;
944 
945 	if(acb->srboutstandingcount>0) {
946 		/* disable all outbound interrupt */
947 		intmask_org = arcmsr_disable_allintr(acb);
948 		/*clear and abort all outbound posted Q*/
949 		arcmsr_done4abort_postqueue(acb);
950 		/* talk to iop 331 outstanding command aborted*/
951 		arcmsr_abort_allcmd(acb);
952 		for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
953 			srb = acb->psrb_pool[i];
954 			if(srb->srb_state == ARCMSR_SRB_START) {
955 				srb->srb_state = ARCMSR_SRB_ABORTED;
956 				srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
957 				arcmsr_srb_complete(srb, 1);
958 				printf("arcmsr%d: scsi id=%d lun=%d srb='%p' aborted\n"
959 						, acb->pci_unit, srb->pccb->ccb_h.target_id
960 						, srb->pccb->ccb_h.target_lun, srb);
961 			}
962 		}
963 		/* enable all outbound interrupt */
964 		arcmsr_enable_allintr(acb, intmask_org);
965 	}
966 	acb->srboutstandingcount = 0;
967 	acb->workingsrb_doneindex = 0;
968 	acb->workingsrb_startindex = 0;
969 	acb->pktRequestCount = 0;
970 	acb->pktReturnCount = 0;
971 }
972 /*
973 **********************************************************************
974 **********************************************************************
975 */
976 static void arcmsr_build_srb(struct CommandControlBlock *srb,
977 		bus_dma_segment_t *dm_segs, u_int32_t nseg)
978 {
979 	struct ARCMSR_CDB *arcmsr_cdb = &srb->arcmsr_cdb;
980 	u_int8_t *psge = (u_int8_t *)&arcmsr_cdb->u;
981 	u_int32_t address_lo, address_hi;
982 	union ccb *pccb = srb->pccb;
983 	struct ccb_scsiio *pcsio = &pccb->csio;
984 	u_int32_t arccdbsize = 0x30;
985 
986 	memset(arcmsr_cdb, 0, sizeof(struct ARCMSR_CDB));
987 	arcmsr_cdb->Bus = 0;
988 	arcmsr_cdb->TargetID = pccb->ccb_h.target_id;
989 	arcmsr_cdb->LUN = pccb->ccb_h.target_lun;
990 	arcmsr_cdb->Function = 1;
991 	arcmsr_cdb->CdbLength = (u_int8_t)pcsio->cdb_len;
992 	bcopy(pcsio->cdb_io.cdb_bytes, arcmsr_cdb->Cdb, pcsio->cdb_len);
993 	if(nseg != 0) {
994 		struct AdapterControlBlock *acb = srb->acb;
995 		bus_dmasync_op_t op;
996 		u_int32_t length, i, cdb_sgcount = 0;
997 
998 		if((pccb->ccb_h.flags & CAM_DIR_MASK) == CAM_DIR_IN) {
999 			op = BUS_DMASYNC_PREREAD;
1000 		} else {
1001 			op = BUS_DMASYNC_PREWRITE;
1002 			arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_WRITE;
1003 			srb->srb_flags |= SRB_FLAG_WRITE;
1004 		}
1005 		bus_dmamap_sync(acb->dm_segs_dmat, srb->dm_segs_dmamap, op);
1006 		for(i=0; i < nseg; i++) {
1007 			/* Get the physical address of the current data pointer */
1008 			length = arcmsr_htole32(dm_segs[i].ds_len);
1009 			address_lo = arcmsr_htole32(dma_addr_lo32(dm_segs[i].ds_addr));
1010 			address_hi = arcmsr_htole32(dma_addr_hi32(dm_segs[i].ds_addr));
1011 			if(address_hi == 0) {
1012 				struct SG32ENTRY *pdma_sg = (struct SG32ENTRY *)psge;
1013 				pdma_sg->address = address_lo;
1014 				pdma_sg->length = length;
1015 				psge += sizeof(struct SG32ENTRY);
1016 				arccdbsize += sizeof(struct SG32ENTRY);
1017 			} else {
1018 				u_int32_t sg64s_size = 0, tmplength = length;
1019 
1020 				while(1) {
1021 					u_int64_t span4G, length0;
1022 					struct SG64ENTRY *pdma_sg = (struct SG64ENTRY *)psge;
1023 
1024 					span4G = (u_int64_t)address_lo + tmplength;
1025 					pdma_sg->addresshigh = address_hi;
1026 					pdma_sg->address = address_lo;
1027 					if(span4G > 0x100000000) {
1028 						/*see if cross 4G boundary*/
1029 						length0 = 0x100000000-address_lo;
1030 						pdma_sg->length = (u_int32_t)length0 | IS_SG64_ADDR;
1031 						address_hi = address_hi+1;
1032 						address_lo = 0;
1033 						tmplength = tmplength - (u_int32_t)length0;
1034 						sg64s_size += sizeof(struct SG64ENTRY);
1035 						psge += sizeof(struct SG64ENTRY);
1036 						cdb_sgcount++;
1037 					} else {
1038 						pdma_sg->length = tmplength | IS_SG64_ADDR;
1039 						sg64s_size += sizeof(struct SG64ENTRY);
1040 						psge += sizeof(struct SG64ENTRY);
1041 						break;
1042 					}
1043 				}
1044 				arccdbsize += sg64s_size;
1045 			}
1046 			cdb_sgcount++;
1047 		}
1048 		arcmsr_cdb->sgcount = (u_int8_t)cdb_sgcount;
1049 		arcmsr_cdb->DataLength = pcsio->dxfer_len;
1050 		if( arccdbsize > 256) {
1051 			arcmsr_cdb->Flags |= ARCMSR_CDB_FLAG_SGL_BSIZE;
1052 		}
1053 	} else {
1054 		arcmsr_cdb->DataLength = 0;
1055 	}
1056     srb->arc_cdb_size = arccdbsize;
1057     arcmsr_cdb->msgPages = (arccdbsize/256) + ((arccdbsize % 256) ? 1 : 0);
1058 }
1059 /*
1060 **************************************************************************
1061 **************************************************************************
1062 */
1063 static void arcmsr_post_srb(struct AdapterControlBlock *acb, struct CommandControlBlock *srb)
1064 {
1065 	u_int32_t cdb_phyaddr_low = (u_int32_t) srb->cdb_phyaddr_low;
1066 	struct ARCMSR_CDB *arcmsr_cdb = (struct ARCMSR_CDB *)&srb->arcmsr_cdb;
1067 
1068 	bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, (srb->srb_flags & SRB_FLAG_WRITE) ? BUS_DMASYNC_POSTWRITE:BUS_DMASYNC_POSTREAD);
1069 	atomic_add_int(&acb->srboutstandingcount, 1);
1070 	srb->srb_state = ARCMSR_SRB_START;
1071 
1072 	switch (acb->adapter_type) {
1073 	case ACB_ADAPTER_TYPE_A: {
1074 			if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
1075 				CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low|ARCMSR_SRBPOST_FLAG_SGL_BSIZE);
1076 			} else {
1077 				CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_queueport, cdb_phyaddr_low);
1078 			}
1079 		}
1080 		break;
1081 	case ACB_ADAPTER_TYPE_B: {
1082 			struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1083 			int ending_index, index;
1084 
1085 			index = phbbmu->postq_index;
1086 			ending_index = ((index+1) % ARCMSR_MAX_HBB_POSTQUEUE);
1087 			phbbmu->post_qbuffer[ending_index] = 0;
1088 			if(arcmsr_cdb->Flags & ARCMSR_CDB_FLAG_SGL_BSIZE) {
1089 				phbbmu->post_qbuffer[index] = cdb_phyaddr_low | ARCMSR_SRBPOST_FLAG_SGL_BSIZE;
1090 			} else {
1091 				phbbmu->post_qbuffer[index] = cdb_phyaddr_low;
1092 			}
1093 			index++;
1094 			index %= ARCMSR_MAX_HBB_POSTQUEUE;     /*if last index number set it to 0 */
1095 			phbbmu->postq_index = index;
1096 			CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_CDB_POSTED);
1097 		}
1098 		break;
1099     case ACB_ADAPTER_TYPE_C: {
1100             u_int32_t ccb_post_stamp, arc_cdb_size, cdb_phyaddr_hi32;
1101 
1102             arc_cdb_size = (srb->arc_cdb_size > 0x300) ? 0x300 : srb->arc_cdb_size;
1103             ccb_post_stamp = (cdb_phyaddr_low | ((arc_cdb_size-1) >> 6) | 1);
1104 			cdb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high;
1105             if(cdb_phyaddr_hi32)
1106             {
1107 			    CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_high, cdb_phyaddr_hi32);
1108 			    CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp);
1109             }
1110             else
1111             {
1112 			    CHIP_REG_WRITE32(HBC_MessageUnit,0,inbound_queueport_low, ccb_post_stamp);
1113             }
1114         }
1115         break;
1116 	case ACB_ADAPTER_TYPE_D: {
1117 			struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1118 			u_int16_t index_stripped;
1119 			u_int16_t postq_index;
1120 			struct InBound_SRB *pinbound_srb;
1121 
1122 			ARCMSR_LOCK_ACQUIRE(&acb->postDone_lock);
1123 			postq_index = phbdmu->postq_index;
1124 			pinbound_srb = (struct InBound_SRB *)&phbdmu->post_qbuffer[postq_index & 0xFF];
1125 			pinbound_srb->addressHigh = srb->cdb_phyaddr_high;
1126 			pinbound_srb->addressLow = srb->cdb_phyaddr_low;
1127 			pinbound_srb->length = srb->arc_cdb_size >> 2;
1128 			arcmsr_cdb->Context = srb->cdb_phyaddr_low;
1129 			if (postq_index & 0x4000) {
1130 				index_stripped = postq_index & 0xFF;
1131 				index_stripped += 1;
1132 				index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
1133 				phbdmu->postq_index = index_stripped ? (index_stripped | 0x4000) : index_stripped;
1134 			} else {
1135 				index_stripped = postq_index;
1136 				index_stripped += 1;
1137 				index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
1138 				phbdmu->postq_index = index_stripped ? index_stripped : (index_stripped | 0x4000);
1139 			}
1140 			CHIP_REG_WRITE32(HBD_MessageUnit, 0, inboundlist_write_pointer, postq_index);
1141 			ARCMSR_LOCK_RELEASE(&acb->postDone_lock);
1142 		}
1143 		break;
1144 	}
1145 }
1146 /*
1147 ************************************************************************
1148 ************************************************************************
1149 */
1150 static struct QBUFFER *arcmsr_get_iop_rqbuffer( struct AdapterControlBlock *acb)
1151 {
1152 	struct QBUFFER *qbuffer=NULL;
1153 
1154 	switch (acb->adapter_type) {
1155 	case ACB_ADAPTER_TYPE_A: {
1156 			struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu;
1157 
1158 			qbuffer = (struct QBUFFER *)&phbamu->message_rbuffer;
1159 		}
1160 		break;
1161 	case ACB_ADAPTER_TYPE_B: {
1162 			struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1163 
1164 			qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_rbuffer;
1165 		}
1166 		break;
1167 	case ACB_ADAPTER_TYPE_C: {
1168 			struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu;
1169 
1170 			qbuffer = (struct QBUFFER *)&phbcmu->message_rbuffer;
1171 		}
1172 		break;
1173 	case ACB_ADAPTER_TYPE_D: {
1174 			struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1175 
1176 			qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_rbuffer;
1177 		}
1178 		break;
1179 	}
1180 	return(qbuffer);
1181 }
1182 /*
1183 ************************************************************************
1184 ************************************************************************
1185 */
1186 static struct QBUFFER *arcmsr_get_iop_wqbuffer( struct AdapterControlBlock *acb)
1187 {
1188 	struct QBUFFER *qbuffer = NULL;
1189 
1190 	switch (acb->adapter_type) {
1191 	case ACB_ADAPTER_TYPE_A: {
1192 			struct HBA_MessageUnit *phbamu = (struct HBA_MessageUnit *)acb->pmu;
1193 
1194 			qbuffer = (struct QBUFFER *)&phbamu->message_wbuffer;
1195 		}
1196 		break;
1197 	case ACB_ADAPTER_TYPE_B: {
1198 			struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1199 
1200 			qbuffer = (struct QBUFFER *)&phbbmu->hbb_rwbuffer->message_wbuffer;
1201 		}
1202 		break;
1203 	case ACB_ADAPTER_TYPE_C: {
1204 			struct HBC_MessageUnit *phbcmu = (struct HBC_MessageUnit *)acb->pmu;
1205 
1206 			qbuffer = (struct QBUFFER *)&phbcmu->message_wbuffer;
1207 		}
1208 		break;
1209 	case ACB_ADAPTER_TYPE_D: {
1210 			struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1211 
1212 			qbuffer = (struct QBUFFER *)&phbdmu->phbdmu->message_wbuffer;
1213 		}
1214 		break;
1215 	}
1216 	return(qbuffer);
1217 }
1218 /*
1219 **************************************************************************
1220 **************************************************************************
1221 */
1222 static void arcmsr_iop_message_read(struct AdapterControlBlock *acb)
1223 {
1224 	switch (acb->adapter_type) {
1225 	case ACB_ADAPTER_TYPE_A: {
1226 			/* let IOP know data has been read */
1227 			CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK);
1228 		}
1229 		break;
1230 	case ACB_ADAPTER_TYPE_B: {
1231 			/* let IOP know data has been read */
1232 			CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK);
1233 		}
1234 		break;
1235 	case ACB_ADAPTER_TYPE_C: {
1236 			/* let IOP know data has been read */
1237 			CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK);
1238 		}
1239 		break;
1240 	case ACB_ADAPTER_TYPE_D: {
1241 			/* let IOP know data has been read */
1242 			CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ);
1243 		}
1244 		break;
1245 	}
1246 }
1247 /*
1248 **************************************************************************
1249 **************************************************************************
1250 */
1251 static void arcmsr_iop_message_wrote(struct AdapterControlBlock *acb)
1252 {
1253 	switch (acb->adapter_type) {
1254 	case ACB_ADAPTER_TYPE_A: {
1255 			/*
1256 			** push inbound doorbell tell iop, driver data write ok
1257 			** and wait reply on next hwinterrupt for next Qbuffer post
1258 			*/
1259 			CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_WRITE_OK);
1260 		}
1261 		break;
1262 	case ACB_ADAPTER_TYPE_B: {
1263 			/*
1264 			** push inbound doorbell tell iop, driver data write ok
1265 			** and wait reply on next hwinterrupt for next Qbuffer post
1266 			*/
1267 			CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_WRITE_OK);
1268 		}
1269 		break;
1270 	case ACB_ADAPTER_TYPE_C: {
1271 			/*
1272 			** push inbound doorbell tell iop, driver data write ok
1273 			** and wait reply on next hwinterrupt for next Qbuffer post
1274 			*/
1275 			CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_WRITE_OK);
1276 		}
1277 		break;
1278 	case ACB_ADAPTER_TYPE_D: {
1279 			/*
1280 			** push inbound doorbell tell iop, driver data write ok
1281 			** and wait reply on next hwinterrupt for next Qbuffer post
1282 			*/
1283 			CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_IN_READY);
1284 		}
1285 		break;
1286 	}
1287 }
1288 /*
1289 ************************************************************************
1290 ************************************************************************
1291 */
1292 static void arcmsr_stop_hba_bgrb(struct AdapterControlBlock *acb)
1293 {
1294 	acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1295 	CHIP_REG_WRITE32(HBA_MessageUnit,
1296 	0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1297 	if(!arcmsr_hba_wait_msgint_ready(acb)) {
1298 		printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
1299 			, acb->pci_unit);
1300 	}
1301 }
1302 /*
1303 ************************************************************************
1304 ************************************************************************
1305 */
1306 static void arcmsr_stop_hbb_bgrb(struct AdapterControlBlock *acb)
1307 {
1308 	acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1309 	CHIP_REG_WRITE32(HBB_DOORBELL,
1310 	0, drv2iop_doorbell, ARCMSR_MESSAGE_STOP_BGRB);
1311 	if(!arcmsr_hbb_wait_msgint_ready(acb)) {
1312 		printf( "arcmsr%d: wait 'stop adapter background rebulid' timeout \n"
1313 			, acb->pci_unit);
1314 	}
1315 }
1316 /*
1317 ************************************************************************
1318 ************************************************************************
1319 */
1320 static void arcmsr_stop_hbc_bgrb(struct AdapterControlBlock *acb)
1321 {
1322 	acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1323 	CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1324 	CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
1325 	if(!arcmsr_hbc_wait_msgint_ready(acb)) {
1326 		printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit);
1327 	}
1328 }
1329 /*
1330 ************************************************************************
1331 ************************************************************************
1332 */
1333 static void arcmsr_stop_hbd_bgrb(struct AdapterControlBlock *acb)
1334 {
1335 	acb->acb_flags &= ~ACB_F_MSG_START_BGRB;
1336 	CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_STOP_BGRB);
1337 	if(!arcmsr_hbd_wait_msgint_ready(acb)) {
1338 		printf("arcmsr%d: wait 'stop adapter background rebulid' timeout \n", acb->pci_unit);
1339 	}
1340 }
1341 /*
1342 ************************************************************************
1343 ************************************************************************
1344 */
1345 static void arcmsr_stop_adapter_bgrb(struct AdapterControlBlock *acb)
1346 {
1347 	switch (acb->adapter_type) {
1348 	case ACB_ADAPTER_TYPE_A: {
1349 			arcmsr_stop_hba_bgrb(acb);
1350 		}
1351 		break;
1352 	case ACB_ADAPTER_TYPE_B: {
1353 			arcmsr_stop_hbb_bgrb(acb);
1354 		}
1355 		break;
1356 	case ACB_ADAPTER_TYPE_C: {
1357 			arcmsr_stop_hbc_bgrb(acb);
1358 		}
1359 		break;
1360 	case ACB_ADAPTER_TYPE_D: {
1361 			arcmsr_stop_hbd_bgrb(acb);
1362 		}
1363 		break;
1364 	}
1365 }
1366 /*
1367 ************************************************************************
1368 ************************************************************************
1369 */
1370 static void arcmsr_poll(struct cam_sim *psim)
1371 {
1372 	struct AdapterControlBlock *acb;
1373 	int	mutex;
1374 
1375 	acb = (struct AdapterControlBlock *)cam_sim_softc(psim);
1376 	mutex = mtx_owned(&acb->isr_lock);
1377 	if( mutex == 0 )
1378 		ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
1379 	arcmsr_interrupt(acb);
1380 	if( mutex == 0 )
1381 		ARCMSR_LOCK_RELEASE(&acb->isr_lock);
1382 }
1383 /*
1384 **************************************************************************
1385 **************************************************************************
1386 */
1387 static u_int32_t arcmsr_Read_iop_rqbuffer_data_D(struct AdapterControlBlock *acb,
1388     struct QBUFFER *prbuffer) {
1389 
1390 	u_int8_t *pQbuffer;
1391 	u_int8_t *buf1 = 0;
1392 	u_int32_t *iop_data, *buf2 = 0;
1393 	u_int32_t iop_len, data_len;
1394 
1395 	iop_data = (u_int32_t *)prbuffer->data;
1396 	iop_len = (u_int32_t)prbuffer->data_len;
1397 	if ( iop_len > 0 )
1398 	{
1399 		buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO);
1400 		buf2 = (u_int32_t *)buf1;
1401 		if( buf1 == NULL)
1402 			return (0);
1403 		data_len = iop_len;
1404 		while(data_len >= 4)
1405 		{
1406 			*buf2++ = *iop_data++;
1407 			data_len -= 4;
1408 		}
1409 		if(data_len)
1410 			*buf2 = *iop_data;
1411 		buf2 = (u_int32_t *)buf1;
1412 	}
1413 	while (iop_len > 0) {
1414 		pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex];
1415 		*pQbuffer = *buf1;
1416 		acb->rqbuf_lastindex++;
1417 		/* if last, index number set it to 0 */
1418 		acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
1419 		buf1++;
1420 		iop_len--;
1421 	}
1422 	if(buf2)
1423 		free( (u_int8_t *)buf2, M_DEVBUF);
1424 	/* let IOP know data has been read */
1425 	arcmsr_iop_message_read(acb);
1426 	return (1);
1427 }
1428 /*
1429 **************************************************************************
1430 **************************************************************************
1431 */
1432 static u_int32_t arcmsr_Read_iop_rqbuffer_data(struct AdapterControlBlock *acb,
1433     struct QBUFFER *prbuffer) {
1434 
1435 	u_int8_t *pQbuffer;
1436 	u_int8_t *iop_data;
1437 	u_int32_t iop_len;
1438 
1439 	if(acb->adapter_type == ACB_ADAPTER_TYPE_D) {
1440 		return(arcmsr_Read_iop_rqbuffer_data_D(acb, prbuffer));
1441 	}
1442 	iop_data = (u_int8_t *)prbuffer->data;
1443 	iop_len = (u_int32_t)prbuffer->data_len;
1444 	while (iop_len > 0) {
1445 		pQbuffer = &acb->rqbuffer[acb->rqbuf_lastindex];
1446 		*pQbuffer = *iop_data;
1447 		acb->rqbuf_lastindex++;
1448 		/* if last, index number set it to 0 */
1449 		acb->rqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
1450 		iop_data++;
1451 		iop_len--;
1452 	}
1453 	/* let IOP know data has been read */
1454 	arcmsr_iop_message_read(acb);
1455 	return (1);
1456 }
1457 /*
1458 **************************************************************************
1459 **************************************************************************
1460 */
1461 static void arcmsr_iop2drv_data_wrote_handle(struct AdapterControlBlock *acb)
1462 {
1463 	struct QBUFFER *prbuffer;
1464 	int my_empty_len;
1465 
1466 	/*check this iop data if overflow my rqbuffer*/
1467 	ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
1468 	prbuffer = arcmsr_get_iop_rqbuffer(acb);
1469 	my_empty_len = (acb->rqbuf_lastindex - acb->rqbuf_firstindex - 1) &
1470 	    (ARCMSR_MAX_QBUFFER-1);
1471 	if(my_empty_len >= prbuffer->data_len) {
1472 		if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
1473 			acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
1474 	} else {
1475 		acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
1476 	}
1477 	ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
1478 }
1479 /*
1480 **********************************************************************
1481 **********************************************************************
1482 */
1483 static void arcmsr_Write_data_2iop_wqbuffer_D(struct AdapterControlBlock *acb)
1484 {
1485 	u_int8_t *pQbuffer;
1486 	struct QBUFFER *pwbuffer;
1487 	u_int8_t *buf1 = 0;
1488 	u_int32_t *iop_data, *buf2 = 0;
1489 	u_int32_t allxfer_len = 0, data_len;
1490 
1491 	if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) {
1492 		buf1 = malloc(128, M_DEVBUF, M_NOWAIT | M_ZERO);
1493 		buf2 = (u_int32_t *)buf1;
1494 		if( buf1 == NULL)
1495 			return;
1496 
1497 		acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ);
1498 		pwbuffer = arcmsr_get_iop_wqbuffer(acb);
1499 		iop_data = (u_int32_t *)pwbuffer->data;
1500 		while((acb->wqbuf_firstindex != acb->wqbuf_lastindex)
1501 			&& (allxfer_len < 124)) {
1502 			pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex];
1503 			*buf1 = *pQbuffer;
1504 			acb->wqbuf_firstindex++;
1505 			acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
1506 			buf1++;
1507 			allxfer_len++;
1508 		}
1509 		pwbuffer->data_len = allxfer_len;
1510 		data_len = allxfer_len;
1511 		buf1 = (u_int8_t *)buf2;
1512 		while(data_len >= 4)
1513 		{
1514 			*iop_data++ = *buf2++;
1515 			data_len -= 4;
1516 		}
1517 		if(data_len)
1518 			*iop_data = *buf2;
1519 		free( buf1, M_DEVBUF);
1520 		arcmsr_iop_message_wrote(acb);
1521 	}
1522 }
1523 /*
1524 **********************************************************************
1525 **********************************************************************
1526 */
1527 static void arcmsr_Write_data_2iop_wqbuffer(struct AdapterControlBlock *acb)
1528 {
1529 	u_int8_t *pQbuffer;
1530 	struct QBUFFER *pwbuffer;
1531 	u_int8_t *iop_data;
1532 	int32_t allxfer_len=0;
1533 
1534 	if(acb->adapter_type == ACB_ADAPTER_TYPE_D) {
1535 		arcmsr_Write_data_2iop_wqbuffer_D(acb);
1536 		return;
1537 	}
1538 	if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_READ) {
1539 		acb->acb_flags &= (~ACB_F_MESSAGE_WQBUFFER_READ);
1540 		pwbuffer = arcmsr_get_iop_wqbuffer(acb);
1541 		iop_data = (u_int8_t *)pwbuffer->data;
1542 		while((acb->wqbuf_firstindex != acb->wqbuf_lastindex)
1543 			&& (allxfer_len < 124)) {
1544 			pQbuffer = &acb->wqbuffer[acb->wqbuf_firstindex];
1545 			*iop_data = *pQbuffer;
1546 			acb->wqbuf_firstindex++;
1547 			acb->wqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
1548 			iop_data++;
1549 			allxfer_len++;
1550 		}
1551 		pwbuffer->data_len = allxfer_len;
1552 		arcmsr_iop_message_wrote(acb);
1553 	}
1554 }
1555 /*
1556 **************************************************************************
1557 **************************************************************************
1558 */
1559 static void arcmsr_iop2drv_data_read_handle(struct AdapterControlBlock *acb)
1560 {
1561 	ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
1562 	acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_READ;
1563 	/*
1564 	*****************************************************************
1565 	**   check if there are any mail packages from user space program
1566 	**   in my post bag, now is the time to send them into Areca's firmware
1567 	*****************************************************************
1568 	*/
1569 	if(acb->wqbuf_firstindex != acb->wqbuf_lastindex) {
1570 		arcmsr_Write_data_2iop_wqbuffer(acb);
1571 	}
1572 	if(acb->wqbuf_firstindex == acb->wqbuf_lastindex) {
1573 		acb->acb_flags |= ACB_F_MESSAGE_WQBUFFER_CLEARED;
1574 	}
1575 	ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
1576 }
1577 /*
1578 **************************************************************************
1579 **************************************************************************
1580 */
1581 static void arcmsr_rescanLun_cb(struct cam_periph *periph, union ccb *ccb)
1582 {
1583 /*
1584 	if (ccb->ccb_h.status != CAM_REQ_CMP)
1585 		printf("arcmsr_rescanLun_cb: Rescan Target=%x, lun=%x,"
1586 		    "failure status=%x\n", ccb->ccb_h.target_id,
1587 		    ccb->ccb_h.target_lun, ccb->ccb_h.status);
1588 	else
1589 		printf("arcmsr_rescanLun_cb: Rescan lun successfully!\n");
1590 */
1591 	xpt_free_path(ccb->ccb_h.path);
1592 	xpt_free_ccb(ccb);
1593 }
1594 
1595 static void	arcmsr_rescan_lun(struct AdapterControlBlock *acb, int target, int lun)
1596 {
1597 	struct cam_path     *path;
1598 	union ccb           *ccb;
1599 
1600 	if ((ccb = (union ccb *)xpt_alloc_ccb_nowait()) == NULL)
1601  		return;
1602 	if (xpt_create_path(&path, xpt_periph, cam_sim_path(acb->psim), target, lun) != CAM_REQ_CMP)
1603 	{
1604 		xpt_free_ccb(ccb);
1605 		return;
1606 	}
1607 /*	printf("arcmsr_rescan_lun: Rescan Target=%x, Lun=%x\n", target, lun); */
1608 	bzero(ccb, sizeof(union ccb));
1609 	xpt_setup_ccb(&ccb->ccb_h, path, 5);
1610 	ccb->ccb_h.func_code = XPT_SCAN_LUN;
1611 	ccb->ccb_h.cbfcnp = arcmsr_rescanLun_cb;
1612 	ccb->crcn.flags = CAM_FLAG_NONE;
1613 	xpt_action(ccb);
1614 }
1615 
1616 
1617 static void arcmsr_abort_dr_ccbs(struct AdapterControlBlock *acb, int target, int lun)
1618 {
1619    	struct CommandControlBlock *srb;
1620 	u_int32_t intmask_org;
1621    	int i;
1622 
1623 	ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
1624 	/* disable all outbound interrupts */
1625 	intmask_org = arcmsr_disable_allintr(acb);
1626 	for (i = 0; i < ARCMSR_MAX_FREESRB_NUM; i++)
1627 	{
1628 		srb = acb->psrb_pool[i];
1629 		if (srb->srb_state == ARCMSR_SRB_START)
1630 		{
1631            	if((target == srb->pccb->ccb_h.target_id) && (lun == srb->pccb->ccb_h.target_lun))
1632             {
1633 		    	srb->srb_state = ARCMSR_SRB_ABORTED;
1634 				srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
1635 		    	arcmsr_srb_complete(srb, 1);
1636 				printf("arcmsr%d: abort scsi id %d lun %d srb=%p \n", acb->pci_unit, target, lun, srb);
1637        		}
1638 		}
1639 	}
1640 	/* enable outbound Post Queue, outbound doorbell Interrupt */
1641 	arcmsr_enable_allintr(acb, intmask_org);
1642 	ARCMSR_LOCK_RELEASE(&acb->isr_lock);
1643 }
1644 /*
1645 **************************************************************************
1646 **************************************************************************
1647 */
1648 static void arcmsr_dr_handle(struct AdapterControlBlock *acb) {
1649 	u_int32_t	devicemap;
1650 	u_int32_t	target, lun;
1651     u_int32_t	deviceMapCurrent[4]={0};
1652     u_int8_t	*pDevMap;
1653 
1654 	switch (acb->adapter_type) {
1655 	case ACB_ADAPTER_TYPE_A:
1656 			devicemap = offsetof(struct HBA_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1657 			for (target = 0; target < 4; target++)
1658 			{
1659             	deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0],  devicemap);
1660             	devicemap += 4;
1661 			}
1662 			break;
1663 
1664 	case ACB_ADAPTER_TYPE_B:
1665 			devicemap = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1666 			for (target = 0; target < 4; target++)
1667 			{
1668             	deviceMapCurrent[target]=bus_space_read_4(acb->btag[1], acb->bhandle[1],  devicemap);
1669             	devicemap += 4;
1670 			}
1671 			break;
1672 
1673 	case ACB_ADAPTER_TYPE_C:
1674 			devicemap = offsetof(struct HBC_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1675 			for (target = 0; target < 4; target++)
1676 			{
1677             	deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0],  devicemap);
1678             	devicemap += 4;
1679 			}
1680 			break;
1681 	case ACB_ADAPTER_TYPE_D:
1682 			devicemap = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
1683 			for (target = 0; target < 4; target++)
1684 			{
1685             	deviceMapCurrent[target]=bus_space_read_4(acb->btag[0], acb->bhandle[0],  devicemap);
1686             	devicemap += 4;
1687 			}
1688 			break;
1689 	}
1690 
1691 		if(acb->acb_flags & ACB_F_BUS_HANG_ON)
1692 		{
1693 			acb->acb_flags &= ~ACB_F_BUS_HANG_ON;
1694 		}
1695 		/*
1696 		** adapter posted CONFIG message
1697 		** copy the new map, note if there are differences with the current map
1698 		*/
1699 		pDevMap = (u_int8_t	*)&deviceMapCurrent[0];
1700 		for (target = 0; target < ARCMSR_MAX_TARGETID - 1; target++)
1701 		{
1702 			if (*pDevMap != acb->device_map[target])
1703 			{
1704                 u_int8_t difference, bit_check;
1705 
1706                 difference = *pDevMap ^ acb->device_map[target];
1707                 for(lun=0; lun < ARCMSR_MAX_TARGETLUN; lun++)
1708                 {
1709                     bit_check = (1 << lun);						/*check bit from 0....31*/
1710                     if(difference & bit_check)
1711                     {
1712                         if(acb->device_map[target] & bit_check)
1713                         {/* unit departed */
1714 							printf("arcmsr_dr_handle: Target=%x, lun=%x, GONE!!!\n",target,lun);
1715  							arcmsr_abort_dr_ccbs(acb, target, lun);
1716                         	arcmsr_rescan_lun(acb, target, lun);
1717         					acb->devstate[target][lun] = ARECA_RAID_GONE;
1718                         }
1719                         else
1720                         {/* unit arrived */
1721 							printf("arcmsr_dr_handle: Target=%x, lun=%x, Plug-IN!!!\n",target,lun);
1722                         	arcmsr_rescan_lun(acb, target, lun);
1723         					acb->devstate[target][lun] = ARECA_RAID_GOOD;
1724                         }
1725                     }
1726                 }
1727 /*				printf("arcmsr_dr_handle: acb->device_map[%x]=0x%x, deviceMapCurrent[%x]=%x\n",target,acb->device_map[target],target,*pDevMap); */
1728 				acb->device_map[target] = *pDevMap;
1729 			}
1730 			pDevMap++;
1731 		}
1732 }
1733 /*
1734 **************************************************************************
1735 **************************************************************************
1736 */
1737 static void arcmsr_hba_message_isr(struct AdapterControlBlock *acb) {
1738 	u_int32_t outbound_message;
1739 
1740 	CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, ARCMSR_MU_OUTBOUND_MESSAGE0_INT);
1741 	outbound_message = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[0]);
1742 	if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1743 		arcmsr_dr_handle( acb );
1744 }
1745 /*
1746 **************************************************************************
1747 **************************************************************************
1748 */
1749 static void arcmsr_hbb_message_isr(struct AdapterControlBlock *acb) {
1750 	u_int32_t outbound_message;
1751 
1752 	/* clear interrupts */
1753 	CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);
1754 	outbound_message = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0]);
1755 	if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1756 		arcmsr_dr_handle( acb );
1757 }
1758 /*
1759 **************************************************************************
1760 **************************************************************************
1761 */
1762 static void arcmsr_hbc_message_isr(struct AdapterControlBlock *acb) {
1763 	u_int32_t outbound_message;
1764 
1765 	CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE_DOORBELL_CLEAR);
1766 	outbound_message = CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[0]);
1767 	if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1768 		arcmsr_dr_handle( acb );
1769 }
1770 /*
1771 **************************************************************************
1772 **************************************************************************
1773 */
1774 static void arcmsr_hbd_message_isr(struct AdapterControlBlock *acb) {
1775 	u_int32_t outbound_message;
1776 
1777 	CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);
1778 	outbound_message = CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[0]);
1779 	if (outbound_message == ARCMSR_SIGNATURE_GET_CONFIG)
1780 		arcmsr_dr_handle( acb );
1781 }
1782 /*
1783 **************************************************************************
1784 **************************************************************************
1785 */
1786 static void arcmsr_hba_doorbell_isr(struct AdapterControlBlock *acb)
1787 {
1788 	u_int32_t outbound_doorbell;
1789 
1790 	/*
1791 	*******************************************************************
1792 	**  Maybe here we need to check wrqbuffer_lock is lock or not
1793 	**  DOORBELL: din! don!
1794 	**  check if there are any mail need to pack from firmware
1795 	*******************************************************************
1796 	*/
1797 	outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit,
1798 	0, outbound_doorbell);
1799 	CHIP_REG_WRITE32(HBA_MessageUnit,
1800 	0, outbound_doorbell, outbound_doorbell); /* clear doorbell interrupt */
1801 	if(outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_WRITE_OK) {
1802 		arcmsr_iop2drv_data_wrote_handle(acb);
1803 	}
1804 	if(outbound_doorbell & ARCMSR_OUTBOUND_IOP331_DATA_READ_OK) {
1805 		arcmsr_iop2drv_data_read_handle(acb);
1806 	}
1807 }
1808 /*
1809 **************************************************************************
1810 **************************************************************************
1811 */
1812 static void arcmsr_hbc_doorbell_isr(struct AdapterControlBlock *acb)
1813 {
1814 	u_int32_t outbound_doorbell;
1815 
1816 	/*
1817 	*******************************************************************
1818 	**  Maybe here we need to check wrqbuffer_lock is lock or not
1819 	**  DOORBELL: din! don!
1820 	**  check if there are any mail need to pack from firmware
1821 	*******************************************************************
1822 	*/
1823 	outbound_doorbell = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell);
1824 	CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell); /* clear doorbell interrupt */
1825 	if(outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_WRITE_OK) {
1826 		arcmsr_iop2drv_data_wrote_handle(acb);
1827 	}
1828 	if(outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_DATA_READ_OK) {
1829 		arcmsr_iop2drv_data_read_handle(acb);
1830 	}
1831 	if(outbound_doorbell & ARCMSR_HBCMU_IOP2DRV_MESSAGE_CMD_DONE) {
1832 		arcmsr_hbc_message_isr(acb);    /* messenger of "driver to iop commands" */
1833 	}
1834 }
1835 /*
1836 **************************************************************************
1837 **************************************************************************
1838 */
1839 static void arcmsr_hbd_doorbell_isr(struct AdapterControlBlock *acb)
1840 {
1841 	u_int32_t outbound_Doorbell;
1842 
1843 	/*
1844 	*******************************************************************
1845 	**  Maybe here we need to check wrqbuffer_lock is lock or not
1846 	**  DOORBELL: din! don!
1847 	**  check if there are any mail need to pack from firmware
1848 	*******************************************************************
1849 	*/
1850 	outbound_Doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE;
1851 	if(outbound_Doorbell)
1852 		CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_Doorbell); /* clear doorbell interrupt */
1853 	while( outbound_Doorbell & ARCMSR_HBDMU_F0_DOORBELL_CAUSE ) {
1854 		if(outbound_Doorbell & ARCMSR_HBDMU_IOP2DRV_DATA_WRITE_OK) {
1855 			arcmsr_iop2drv_data_wrote_handle(acb);
1856 		}
1857 		if(outbound_Doorbell & ARCMSR_HBDMU_IOP2DRV_DATA_READ_OK) {
1858 			arcmsr_iop2drv_data_read_handle(acb);
1859 		}
1860 		if(outbound_Doorbell & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE) {
1861 			arcmsr_hbd_message_isr(acb);    /* messenger of "driver to iop commands" */
1862 		}
1863 		outbound_Doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_F0_DOORBELL_CAUSE;
1864 		if(outbound_Doorbell)
1865 			CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_Doorbell); /* clear doorbell interrupt */
1866 	}
1867 }
1868 /*
1869 **************************************************************************
1870 **************************************************************************
1871 */
1872 static void arcmsr_hba_postqueue_isr(struct AdapterControlBlock *acb)
1873 {
1874 	u_int32_t flag_srb;
1875 	u_int16_t error;
1876 
1877 	/*
1878 	*****************************************************************************
1879 	**               areca cdb command done
1880 	*****************************************************************************
1881 	*/
1882 	bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
1883 		BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1884 	while((flag_srb = CHIP_REG_READ32(HBA_MessageUnit,
1885 		0, outbound_queueport)) != 0xFFFFFFFF) {
1886 		/* check if command done with no error*/
1887         error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0) ? TRUE : FALSE;
1888 		arcmsr_drain_donequeue(acb, flag_srb, error);
1889 	}	/*drain reply FIFO*/
1890 }
1891 /*
1892 **************************************************************************
1893 **************************************************************************
1894 */
1895 static void arcmsr_hbb_postqueue_isr(struct AdapterControlBlock *acb)
1896 {
1897 	struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
1898 	u_int32_t flag_srb;
1899 	int index;
1900 	u_int16_t error;
1901 
1902 	/*
1903 	*****************************************************************************
1904 	**               areca cdb command done
1905 	*****************************************************************************
1906 	*/
1907 	bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
1908 		BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1909 	index = phbbmu->doneq_index;
1910 	while((flag_srb = phbbmu->done_qbuffer[index]) != 0) {
1911 		phbbmu->done_qbuffer[index] = 0;
1912 		index++;
1913 		index %= ARCMSR_MAX_HBB_POSTQUEUE;     /*if last index number set it to 0 */
1914 		phbbmu->doneq_index = index;
1915 		/* check if command done with no error*/
1916         error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
1917 		arcmsr_drain_donequeue(acb, flag_srb, error);
1918 	}	/*drain reply FIFO*/
1919 }
1920 /*
1921 **************************************************************************
1922 **************************************************************************
1923 */
1924 static void arcmsr_hbc_postqueue_isr(struct AdapterControlBlock *acb)
1925 {
1926 	u_int32_t flag_srb,throttling = 0;
1927 	u_int16_t error;
1928 
1929 	/*
1930 	*****************************************************************************
1931 	**               areca cdb command done
1932 	*****************************************************************************
1933 	*/
1934 	bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
1935 
1936 	while(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) {
1937 
1938 		flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
1939 		/* check if command done with no error*/
1940         error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;
1941 		arcmsr_drain_donequeue(acb, flag_srb, error);
1942         if(throttling == ARCMSR_HBC_ISR_THROTTLING_LEVEL) {
1943             CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_POSTQUEUE_THROTTLING);
1944             break;
1945         }
1946         throttling++;
1947 	}	/*drain reply FIFO*/
1948 }
1949 /*
1950 **********************************************************************
1951 **
1952 **********************************************************************
1953 */
1954 static uint16_t arcmsr_get_doneq_index(struct HBD_MessageUnit0 *phbdmu)
1955 {
1956 	uint16_t doneq_index, index_stripped;
1957 
1958 	doneq_index = phbdmu->doneq_index;
1959 	if (doneq_index & 0x4000) {
1960 		index_stripped = doneq_index & 0xFF;
1961 		index_stripped += 1;
1962 		index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
1963 		phbdmu->doneq_index = index_stripped ?
1964 		    (index_stripped | 0x4000) : index_stripped;
1965 	} else {
1966 		index_stripped = doneq_index;
1967 		index_stripped += 1;
1968 		index_stripped %= ARCMSR_MAX_HBD_POSTQUEUE;
1969 		phbdmu->doneq_index = index_stripped ?
1970 		    index_stripped : (index_stripped | 0x4000);
1971 	}
1972 	return (phbdmu->doneq_index);
1973 }
1974 /*
1975 **************************************************************************
1976 **************************************************************************
1977 */
1978 static void arcmsr_hbd_postqueue_isr(struct AdapterControlBlock *acb)
1979 {
1980 	struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
1981 	u_int32_t outbound_write_pointer;
1982 	u_int32_t addressLow;
1983 	uint16_t doneq_index;
1984 	u_int16_t error;
1985 	/*
1986 	*****************************************************************************
1987 	**               areca cdb command done
1988 	*****************************************************************************
1989 	*/
1990 	if((CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause) &
1991 	    ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT) == 0)
1992 	    return;
1993 	bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap,
1994 		BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
1995 	outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow;
1996 	doneq_index = phbdmu->doneq_index;
1997 	while ((doneq_index & 0xFF) != (outbound_write_pointer & 0xFF)) {
1998 		doneq_index = arcmsr_get_doneq_index(phbdmu);
1999 		addressLow = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow;
2000 		error = (addressLow & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
2001 		arcmsr_drain_donequeue(acb, addressLow, error); /*Check if command done with no error */
2002 		CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index);
2003 		outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow;
2004 	}
2005 	CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_interrupt_cause, ARCMSR_HBDMU_OUTBOUND_LIST_INTERRUPT_CLEAR);
2006 	CHIP_REG_READ32(HBD_MessageUnit, 0, outboundlist_interrupt_cause); /*Dummy ioread32 to force pci flush */
2007 }
2008 /*
2009 **********************************************************************
2010 **********************************************************************
2011 */
2012 static void arcmsr_handle_hba_isr( struct AdapterControlBlock *acb)
2013 {
2014 	u_int32_t outbound_intStatus;
2015 	/*
2016 	*********************************************
2017 	**   check outbound intstatus
2018 	*********************************************
2019 	*/
2020 	outbound_intStatus = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
2021 	if(!outbound_intStatus) {
2022 		/*it must be share irq*/
2023 		return;
2024 	}
2025 	CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intStatus); /*clear interrupt*/
2026 	/* MU doorbell interrupts*/
2027 	if(outbound_intStatus & ARCMSR_MU_OUTBOUND_DOORBELL_INT) {
2028 		arcmsr_hba_doorbell_isr(acb);
2029 	}
2030 	/* MU post queue interrupts*/
2031 	if(outbound_intStatus & ARCMSR_MU_OUTBOUND_POSTQUEUE_INT) {
2032 		arcmsr_hba_postqueue_isr(acb);
2033 	}
2034 	if(outbound_intStatus & ARCMSR_MU_OUTBOUND_MESSAGE0_INT) {
2035 		arcmsr_hba_message_isr(acb);
2036 	}
2037 }
2038 /*
2039 **********************************************************************
2040 **********************************************************************
2041 */
2042 static void arcmsr_handle_hbb_isr( struct AdapterControlBlock *acb)
2043 {
2044 	u_int32_t outbound_doorbell;
2045 	/*
2046 	*********************************************
2047 	**   check outbound intstatus
2048 	*********************************************
2049 	*/
2050 	outbound_doorbell = CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & acb->outbound_int_enable;
2051 	if(!outbound_doorbell) {
2052 		/*it must be share irq*/
2053 		return;
2054 	}
2055 	CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ~outbound_doorbell); /* clear doorbell interrupt */
2056 	CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell);
2057 	CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
2058 	/* MU ioctl transfer doorbell interrupts*/
2059 	if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_WRITE_OK) {
2060 		arcmsr_iop2drv_data_wrote_handle(acb);
2061 	}
2062 	if(outbound_doorbell & ARCMSR_IOP2DRV_DATA_READ_OK) {
2063 		arcmsr_iop2drv_data_read_handle(acb);
2064 	}
2065 	/* MU post queue interrupts*/
2066 	if(outbound_doorbell & ARCMSR_IOP2DRV_CDB_DONE) {
2067 		arcmsr_hbb_postqueue_isr(acb);
2068 	}
2069 	if(outbound_doorbell & ARCMSR_IOP2DRV_MESSAGE_CMD_DONE) {
2070 		arcmsr_hbb_message_isr(acb);
2071 	}
2072 }
2073 /*
2074 **********************************************************************
2075 **********************************************************************
2076 */
2077 static void arcmsr_handle_hbc_isr( struct AdapterControlBlock *acb)
2078 {
2079 	u_int32_t host_interrupt_status;
2080 	/*
2081 	*********************************************
2082 	**   check outbound intstatus
2083 	*********************************************
2084 	*/
2085 	host_interrupt_status = CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status);
2086 	if(!host_interrupt_status) {
2087 		/*it must be share irq*/
2088 		return;
2089 	}
2090 	/* MU doorbell interrupts*/
2091 	if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_DOORBELL_ISR) {
2092 		arcmsr_hbc_doorbell_isr(acb);
2093 	}
2094 	/* MU post queue interrupts*/
2095 	if(host_interrupt_status & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR) {
2096 		arcmsr_hbc_postqueue_isr(acb);
2097 	}
2098 }
2099 /*
2100 **********************************************************************
2101 **********************************************************************
2102 */
2103 static void arcmsr_handle_hbd_isr( struct AdapterControlBlock *acb)
2104 {
2105 	u_int32_t host_interrupt_status;
2106 	u_int32_t intmask_org;
2107 	/*
2108 	*********************************************
2109 	**   check outbound intstatus
2110 	*********************************************
2111 	*/
2112 	host_interrupt_status = CHIP_REG_READ32(HBD_MessageUnit, 0, host_int_status) & acb->outbound_int_enable;
2113 	if(!(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_INT)) {
2114 		/*it must be share irq*/
2115 		return;
2116 	}
2117 	/* disable outbound interrupt */
2118 	intmask_org = CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable)	; /* disable outbound message0 int */
2119 	CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, ARCMSR_HBDMU_ALL_INT_DISABLE);
2120 	/* MU doorbell interrupts*/
2121 	if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_DOORBELL_INT) {
2122 		arcmsr_hbd_doorbell_isr(acb);
2123 	}
2124 	/* MU post queue interrupts*/
2125 	if(host_interrupt_status & ARCMSR_HBDMU_OUTBOUND_POSTQUEUE_INT) {
2126 		arcmsr_hbd_postqueue_isr(acb);
2127 	}
2128 	/* enable all outbound interrupt */
2129 	CHIP_REG_WRITE32(HBD_MessageUnit, 0, pcief0_int_enable, intmask_org | ARCMSR_HBDMU_ALL_INT_ENABLE);
2130 //	CHIP_REG_READ32(HBD_MessageUnit, 0, pcief0_int_enable);
2131 }
2132 /*
2133 ******************************************************************************
2134 ******************************************************************************
2135 */
2136 static void arcmsr_interrupt(struct AdapterControlBlock *acb)
2137 {
2138 	switch (acb->adapter_type) {
2139 	case ACB_ADAPTER_TYPE_A:
2140 		arcmsr_handle_hba_isr(acb);
2141 		break;
2142 	case ACB_ADAPTER_TYPE_B:
2143 		arcmsr_handle_hbb_isr(acb);
2144 		break;
2145 	case ACB_ADAPTER_TYPE_C:
2146 		arcmsr_handle_hbc_isr(acb);
2147 		break;
2148 	case ACB_ADAPTER_TYPE_D:
2149 		arcmsr_handle_hbd_isr(acb);
2150 		break;
2151 	default:
2152 		printf("arcmsr%d: interrupt service,"
2153 		" unknown adapter type =%d\n", acb->pci_unit, acb->adapter_type);
2154 		break;
2155 	}
2156 }
2157 /*
2158 **********************************************************************
2159 **********************************************************************
2160 */
2161 static void arcmsr_intr_handler(void *arg)
2162 {
2163 	struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg;
2164 
2165 	ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
2166 	arcmsr_interrupt(acb);
2167 	ARCMSR_LOCK_RELEASE(&acb->isr_lock);
2168 }
2169 /*
2170 ******************************************************************************
2171 ******************************************************************************
2172 */
2173 static void	arcmsr_polling_devmap(void *arg)
2174 {
2175 	struct AdapterControlBlock *acb = (struct AdapterControlBlock *)arg;
2176 	switch (acb->adapter_type) {
2177     	case ACB_ADAPTER_TYPE_A:
2178 			CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2179 	    	break;
2180 
2181     	case ACB_ADAPTER_TYPE_B:
2182 			CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG);
2183 	    	break;
2184 
2185     	case ACB_ADAPTER_TYPE_C:
2186 			CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2187 			CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
2188 	    	break;
2189 
2190     	case ACB_ADAPTER_TYPE_D:
2191 			CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
2192 	    	break;
2193 	}
2194 
2195 	if((acb->acb_flags & ACB_F_SCSISTOPADAPTER) == 0)
2196 	{
2197 		callout_reset(&acb->devmap_callout, 5 * hz, arcmsr_polling_devmap, acb);	/* polling per 5 seconds */
2198 	}
2199 }
2200 
2201 /*
2202 *******************************************************************************
2203 **
2204 *******************************************************************************
2205 */
2206 static void arcmsr_iop_parking(struct AdapterControlBlock *acb)
2207 {
2208 	u_int32_t intmask_org;
2209 
2210 	if(acb != NULL) {
2211 		/* stop adapter background rebuild */
2212 		if(acb->acb_flags & ACB_F_MSG_START_BGRB) {
2213 			intmask_org = arcmsr_disable_allintr(acb);
2214 			arcmsr_stop_adapter_bgrb(acb);
2215 			arcmsr_flush_adapter_cache(acb);
2216 			arcmsr_enable_allintr(acb, intmask_org);
2217 		}
2218 	}
2219 }
2220 /*
2221 ***********************************************************************
2222 **
2223 ************************************************************************
2224 */
2225 u_int32_t arcmsr_iop_ioctlcmd(struct AdapterControlBlock *acb, u_int32_t ioctl_cmd, caddr_t arg)
2226 {
2227 	struct CMD_MESSAGE_FIELD *pcmdmessagefld;
2228 	u_int32_t retvalue = EINVAL;
2229 
2230 	pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) arg;
2231 	if(memcmp(pcmdmessagefld->cmdmessage.Signature, "ARCMSR", 6)!=0) {
2232 		return retvalue;
2233 	}
2234 	ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2235 	switch(ioctl_cmd) {
2236 	case ARCMSR_MESSAGE_READ_RQBUFFER: {
2237 			u_int8_t *pQbuffer;
2238 			u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer;
2239 			u_int32_t allxfer_len=0;
2240 
2241 			while((acb->rqbuf_firstindex != acb->rqbuf_lastindex)
2242 				&& (allxfer_len < 1031)) {
2243 				/*copy READ QBUFFER to srb*/
2244 				pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex];
2245 				*ptmpQbuffer = *pQbuffer;
2246 				acb->rqbuf_firstindex++;
2247 				acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
2248 				/*if last index number set it to 0 */
2249 				ptmpQbuffer++;
2250 				allxfer_len++;
2251 			}
2252 			if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2253 				struct QBUFFER *prbuffer;
2254 
2255 				acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2256 				prbuffer = arcmsr_get_iop_rqbuffer(acb);
2257 				if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
2258 					acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
2259 			}
2260 			pcmdmessagefld->cmdmessage.Length = allxfer_len;
2261 			pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2262 			retvalue = ARCMSR_MESSAGE_SUCCESS;
2263 		}
2264 		break;
2265 	case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
2266 			u_int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
2267 			u_int8_t *pQbuffer;
2268 			u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer;
2269 
2270 			user_len = pcmdmessagefld->cmdmessage.Length;
2271 			/*check if data xfer length of this request will overflow my array qbuffer */
2272 			wqbuf_lastindex = acb->wqbuf_lastindex;
2273 			wqbuf_firstindex = acb->wqbuf_firstindex;
2274 			if(wqbuf_lastindex != wqbuf_firstindex) {
2275 				arcmsr_Write_data_2iop_wqbuffer(acb);
2276 				pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
2277 			} else {
2278 				my_empty_len = (wqbuf_firstindex - wqbuf_lastindex - 1) &
2279 				    (ARCMSR_MAX_QBUFFER - 1);
2280 				if(my_empty_len >= user_len) {
2281 					while(user_len > 0) {
2282 						/*copy srb data to wqbuffer*/
2283 						pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex];
2284 						*pQbuffer = *ptmpuserbuffer;
2285 						acb->wqbuf_lastindex++;
2286 						acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
2287 						/*if last index number set it to 0 */
2288 						ptmpuserbuffer++;
2289 						user_len--;
2290 					}
2291 					/*post fist Qbuffer*/
2292 					if(acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
2293 						acb->acb_flags &= ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
2294 						arcmsr_Write_data_2iop_wqbuffer(acb);
2295 					}
2296 					pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2297 				} else {
2298 					pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
2299 				}
2300 			}
2301 			retvalue = ARCMSR_MESSAGE_SUCCESS;
2302 		}
2303 		break;
2304 	case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
2305 			u_int8_t *pQbuffer = acb->rqbuffer;
2306 
2307 			if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2308 				acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2309 				arcmsr_iop_message_read(acb);
2310 				/*signature, let IOP know data has been readed */
2311 			}
2312 			acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
2313 			acb->rqbuf_firstindex = 0;
2314 			acb->rqbuf_lastindex = 0;
2315 			memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2316 			pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2317 			retvalue = ARCMSR_MESSAGE_SUCCESS;
2318 		}
2319 		break;
2320 	case ARCMSR_MESSAGE_CLEAR_WQBUFFER:
2321 		{
2322 			u_int8_t *pQbuffer = acb->wqbuffer;
2323 
2324 			if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2325 				acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2326                 arcmsr_iop_message_read(acb);
2327 				/*signature, let IOP know data has been readed */
2328 			}
2329 			acb->acb_flags |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ);
2330 			acb->wqbuf_firstindex = 0;
2331 			acb->wqbuf_lastindex = 0;
2332 			memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2333 			pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2334 			retvalue = ARCMSR_MESSAGE_SUCCESS;
2335 		}
2336 		break;
2337 	case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
2338 			u_int8_t *pQbuffer;
2339 
2340 			if(acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2341 				acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2342                 arcmsr_iop_message_read(acb);
2343 				/*signature, let IOP know data has been readed */
2344 			}
2345 			acb->acb_flags  |= (ACB_F_MESSAGE_WQBUFFER_CLEARED
2346 					|ACB_F_MESSAGE_RQBUFFER_CLEARED
2347 					|ACB_F_MESSAGE_WQBUFFER_READ);
2348 			acb->rqbuf_firstindex = 0;
2349 			acb->rqbuf_lastindex = 0;
2350 			acb->wqbuf_firstindex = 0;
2351 			acb->wqbuf_lastindex = 0;
2352 			pQbuffer = acb->rqbuffer;
2353 			memset(pQbuffer, 0, sizeof(struct QBUFFER));
2354 			pQbuffer = acb->wqbuffer;
2355 			memset(pQbuffer, 0, sizeof(struct QBUFFER));
2356 			pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2357 			retvalue = ARCMSR_MESSAGE_SUCCESS;
2358 		}
2359 		break;
2360 	case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: {
2361 			pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F;
2362 			retvalue = ARCMSR_MESSAGE_SUCCESS;
2363 		}
2364 		break;
2365 	case ARCMSR_MESSAGE_SAY_HELLO: {
2366 			u_int8_t *hello_string = "Hello! I am ARCMSR";
2367 			u_int8_t *puserbuffer = (u_int8_t *)pcmdmessagefld->messagedatabuffer;
2368 
2369 			if(memcpy(puserbuffer, hello_string, (int16_t)strlen(hello_string))) {
2370 				pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_ERROR;
2371 				ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2372 				return ENOIOCTL;
2373 			}
2374 			pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2375 			retvalue = ARCMSR_MESSAGE_SUCCESS;
2376 		}
2377 		break;
2378 	case ARCMSR_MESSAGE_SAY_GOODBYE: {
2379 			arcmsr_iop_parking(acb);
2380 			retvalue = ARCMSR_MESSAGE_SUCCESS;
2381 		}
2382 		break;
2383 	case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE: {
2384 			arcmsr_flush_adapter_cache(acb);
2385 			retvalue = ARCMSR_MESSAGE_SUCCESS;
2386 		}
2387 		break;
2388 	}
2389 	ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2390 	return (retvalue);
2391 }
2392 /*
2393 **************************************************************************
2394 **************************************************************************
2395 */
2396 static void arcmsr_free_srb(struct CommandControlBlock *srb)
2397 {
2398 	struct AdapterControlBlock	*acb;
2399 
2400 	acb = srb->acb;
2401 	ARCMSR_LOCK_ACQUIRE(&acb->srb_lock);
2402 	srb->srb_state = ARCMSR_SRB_DONE;
2403 	srb->srb_flags = 0;
2404 	acb->srbworkingQ[acb->workingsrb_doneindex] = srb;
2405 	acb->workingsrb_doneindex++;
2406 	acb->workingsrb_doneindex %= ARCMSR_MAX_FREESRB_NUM;
2407 	ARCMSR_LOCK_RELEASE(&acb->srb_lock);
2408 }
2409 /*
2410 **************************************************************************
2411 **************************************************************************
2412 */
2413 struct CommandControlBlock *arcmsr_get_freesrb(struct AdapterControlBlock *acb)
2414 {
2415 	struct CommandControlBlock *srb = NULL;
2416 	u_int32_t workingsrb_startindex, workingsrb_doneindex;
2417 
2418 	ARCMSR_LOCK_ACQUIRE(&acb->srb_lock);
2419 	workingsrb_doneindex = acb->workingsrb_doneindex;
2420 	workingsrb_startindex = acb->workingsrb_startindex;
2421 	srb = acb->srbworkingQ[workingsrb_startindex];
2422 	workingsrb_startindex++;
2423 	workingsrb_startindex %= ARCMSR_MAX_FREESRB_NUM;
2424 	if(workingsrb_doneindex != workingsrb_startindex) {
2425 		acb->workingsrb_startindex = workingsrb_startindex;
2426 	} else {
2427 		srb = NULL;
2428 	}
2429 	ARCMSR_LOCK_RELEASE(&acb->srb_lock);
2430 	return(srb);
2431 }
2432 /*
2433 **************************************************************************
2434 **************************************************************************
2435 */
2436 static int arcmsr_iop_message_xfer(struct AdapterControlBlock *acb, union ccb *pccb)
2437 {
2438 	struct CMD_MESSAGE_FIELD *pcmdmessagefld;
2439 	int retvalue = 0, transfer_len = 0;
2440 	char *buffer;
2441 	u_int32_t controlcode = (u_int32_t ) pccb->csio.cdb_io.cdb_bytes[5] << 24 |
2442 				(u_int32_t ) pccb->csio.cdb_io.cdb_bytes[6] << 16 |
2443 				(u_int32_t ) pccb->csio.cdb_io.cdb_bytes[7] << 8  |
2444 				(u_int32_t ) pccb->csio.cdb_io.cdb_bytes[8];
2445 					/* 4 bytes: Areca io control code */
2446 	if ((pccb->ccb_h.flags & CAM_DATA_MASK) == CAM_DATA_VADDR) {
2447 		buffer = pccb->csio.data_ptr;
2448 		transfer_len = pccb->csio.dxfer_len;
2449 	} else {
2450 		retvalue = ARCMSR_MESSAGE_FAIL;
2451 		goto message_out;
2452 	}
2453 	if (transfer_len > sizeof(struct CMD_MESSAGE_FIELD)) {
2454 		retvalue = ARCMSR_MESSAGE_FAIL;
2455 		goto message_out;
2456 	}
2457 	pcmdmessagefld = (struct CMD_MESSAGE_FIELD *) buffer;
2458 	switch(controlcode) {
2459 	case ARCMSR_MESSAGE_READ_RQBUFFER: {
2460 			u_int8_t *pQbuffer;
2461 			u_int8_t *ptmpQbuffer = pcmdmessagefld->messagedatabuffer;
2462 			int32_t allxfer_len = 0;
2463 
2464 			ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2465 			while ((acb->rqbuf_firstindex != acb->rqbuf_lastindex)
2466 				&& (allxfer_len < 1031)) {
2467 				pQbuffer = &acb->rqbuffer[acb->rqbuf_firstindex];
2468 				*ptmpQbuffer = *pQbuffer;
2469 				acb->rqbuf_firstindex++;
2470 				acb->rqbuf_firstindex %= ARCMSR_MAX_QBUFFER;
2471 				ptmpQbuffer++;
2472 				allxfer_len++;
2473 			}
2474 			if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2475 				struct QBUFFER  *prbuffer;
2476 
2477 				acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2478 				prbuffer = arcmsr_get_iop_rqbuffer(acb);
2479 				if(arcmsr_Read_iop_rqbuffer_data(acb, prbuffer) == 0)
2480 					acb->acb_flags |= ACB_F_IOPDATA_OVERFLOW;
2481 			}
2482 			pcmdmessagefld->cmdmessage.Length = allxfer_len;
2483 			pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2484 			retvalue = ARCMSR_MESSAGE_SUCCESS;
2485 			ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2486 		}
2487 		break;
2488 	case ARCMSR_MESSAGE_WRITE_WQBUFFER: {
2489 			int32_t my_empty_len, user_len, wqbuf_firstindex, wqbuf_lastindex;
2490 			u_int8_t *pQbuffer;
2491 			u_int8_t *ptmpuserbuffer = pcmdmessagefld->messagedatabuffer;
2492 
2493 			user_len = pcmdmessagefld->cmdmessage.Length;
2494 			ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2495 			wqbuf_lastindex = acb->wqbuf_lastindex;
2496 			wqbuf_firstindex = acb->wqbuf_firstindex;
2497 			if (wqbuf_lastindex != wqbuf_firstindex) {
2498 				arcmsr_Write_data_2iop_wqbuffer(acb);
2499 				/* has error report sensedata */
2500 			    if(pccb->csio.sense_len) {
2501 				((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70);
2502 				/* Valid,ErrorCode */
2503 				((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05;
2504 				/* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */
2505 				((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A;
2506 				/* AdditionalSenseLength */
2507 				((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20;
2508 				/* AdditionalSenseCode */
2509 				}
2510 				retvalue = ARCMSR_MESSAGE_FAIL;
2511 			} else {
2512 				my_empty_len = (wqbuf_firstindex-wqbuf_lastindex - 1)
2513 						&(ARCMSR_MAX_QBUFFER - 1);
2514 				if (my_empty_len >= user_len) {
2515 					while (user_len > 0) {
2516 						pQbuffer = &acb->wqbuffer[acb->wqbuf_lastindex];
2517 						*pQbuffer = *ptmpuserbuffer;
2518 						acb->wqbuf_lastindex++;
2519 						acb->wqbuf_lastindex %= ARCMSR_MAX_QBUFFER;
2520 						ptmpuserbuffer++;
2521 						user_len--;
2522 					}
2523 					if (acb->acb_flags & ACB_F_MESSAGE_WQBUFFER_CLEARED) {
2524 						acb->acb_flags &=
2525 						    ~ACB_F_MESSAGE_WQBUFFER_CLEARED;
2526 						arcmsr_Write_data_2iop_wqbuffer(acb);
2527 					}
2528 				} else {
2529 					/* has error report sensedata */
2530 					if(pccb->csio.sense_len) {
2531 					((u_int8_t *)&pccb->csio.sense_data)[0] = (0x1 << 7 | 0x70);
2532 					/* Valid,ErrorCode */
2533 					((u_int8_t *)&pccb->csio.sense_data)[2] = 0x05;
2534 					/* FileMark,EndOfMedia,IncorrectLength,Reserved,SenseKey */
2535 					((u_int8_t *)&pccb->csio.sense_data)[7] = 0x0A;
2536 					/* AdditionalSenseLength */
2537 					((u_int8_t *)&pccb->csio.sense_data)[12] = 0x20;
2538 					/* AdditionalSenseCode */
2539 					}
2540 					retvalue = ARCMSR_MESSAGE_FAIL;
2541 				}
2542 			}
2543 			ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2544 		}
2545 		break;
2546 	case ARCMSR_MESSAGE_CLEAR_RQBUFFER: {
2547 			u_int8_t *pQbuffer = acb->rqbuffer;
2548 
2549 			ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2550 			if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2551 				acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2552 				arcmsr_iop_message_read(acb);
2553 			}
2554 			acb->acb_flags |= ACB_F_MESSAGE_RQBUFFER_CLEARED;
2555 			acb->rqbuf_firstindex = 0;
2556 			acb->rqbuf_lastindex = 0;
2557 			memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2558 			pcmdmessagefld->cmdmessage.ReturnCode =
2559 			    ARCMSR_MESSAGE_RETURNCODE_OK;
2560 			ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2561 		}
2562 		break;
2563 	case ARCMSR_MESSAGE_CLEAR_WQBUFFER: {
2564 			u_int8_t *pQbuffer = acb->wqbuffer;
2565 
2566 			ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2567 			if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2568 				acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2569 				arcmsr_iop_message_read(acb);
2570 			}
2571 			acb->acb_flags |=
2572 				(ACB_F_MESSAGE_WQBUFFER_CLEARED |
2573 					ACB_F_MESSAGE_WQBUFFER_READ);
2574 			acb->wqbuf_firstindex = 0;
2575 			acb->wqbuf_lastindex = 0;
2576 			memset(pQbuffer, 0, ARCMSR_MAX_QBUFFER);
2577 			pcmdmessagefld->cmdmessage.ReturnCode =
2578 				ARCMSR_MESSAGE_RETURNCODE_OK;
2579 			ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2580 		}
2581 		break;
2582 	case ARCMSR_MESSAGE_CLEAR_ALLQBUFFER: {
2583 			u_int8_t *pQbuffer;
2584 
2585 			ARCMSR_LOCK_ACQUIRE(&acb->qbuffer_lock);
2586 			if (acb->acb_flags & ACB_F_IOPDATA_OVERFLOW) {
2587 				acb->acb_flags &= ~ACB_F_IOPDATA_OVERFLOW;
2588 				arcmsr_iop_message_read(acb);
2589 			}
2590 			acb->acb_flags |=
2591 				(ACB_F_MESSAGE_WQBUFFER_CLEARED
2592 				| ACB_F_MESSAGE_RQBUFFER_CLEARED
2593 				| ACB_F_MESSAGE_WQBUFFER_READ);
2594 			acb->rqbuf_firstindex = 0;
2595 			acb->rqbuf_lastindex = 0;
2596 			acb->wqbuf_firstindex = 0;
2597 			acb->wqbuf_lastindex = 0;
2598 			pQbuffer = acb->rqbuffer;
2599 			memset(pQbuffer, 0, sizeof (struct QBUFFER));
2600 			pQbuffer = acb->wqbuffer;
2601 			memset(pQbuffer, 0, sizeof (struct QBUFFER));
2602 			pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2603 			ARCMSR_LOCK_RELEASE(&acb->qbuffer_lock);
2604 		}
2605 		break;
2606 	case ARCMSR_MESSAGE_REQUEST_RETURNCODE_3F: {
2607 			pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_3F;
2608 		}
2609 		break;
2610 	case ARCMSR_MESSAGE_SAY_HELLO: {
2611 			int8_t *hello_string = "Hello! I am ARCMSR";
2612 
2613 			memcpy(pcmdmessagefld->messagedatabuffer, hello_string
2614 				, (int16_t)strlen(hello_string));
2615 			pcmdmessagefld->cmdmessage.ReturnCode = ARCMSR_MESSAGE_RETURNCODE_OK;
2616 		}
2617 		break;
2618 	case ARCMSR_MESSAGE_SAY_GOODBYE:
2619 		arcmsr_iop_parking(acb);
2620 		break;
2621 	case ARCMSR_MESSAGE_FLUSH_ADAPTER_CACHE:
2622 		arcmsr_flush_adapter_cache(acb);
2623 		break;
2624 	default:
2625 		retvalue = ARCMSR_MESSAGE_FAIL;
2626 	}
2627 message_out:
2628 	return (retvalue);
2629 }
2630 /*
2631 *********************************************************************
2632 *********************************************************************
2633 */
2634 static void arcmsr_execute_srb(void *arg, bus_dma_segment_t *dm_segs, int nseg, int error)
2635 {
2636 	struct CommandControlBlock *srb = (struct CommandControlBlock *)arg;
2637 	struct AdapterControlBlock *acb = (struct AdapterControlBlock *)srb->acb;
2638 	union ccb *pccb;
2639 	int target, lun;
2640 
2641 	pccb = srb->pccb;
2642 	target = pccb->ccb_h.target_id;
2643 	lun = pccb->ccb_h.target_lun;
2644 	acb->pktRequestCount++;
2645 	if(error != 0) {
2646 		if(error != EFBIG) {
2647 			printf("arcmsr%d: unexpected error %x"
2648 				" returned from 'bus_dmamap_load' \n"
2649 				, acb->pci_unit, error);
2650 		}
2651 		if((pccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_INPROG) {
2652 			pccb->ccb_h.status |= CAM_REQ_TOO_BIG;
2653 		}
2654 		arcmsr_srb_complete(srb, 0);
2655 		return;
2656 	}
2657 	if(nseg > ARCMSR_MAX_SG_ENTRIES) {
2658 		pccb->ccb_h.status |= CAM_REQ_TOO_BIG;
2659 		arcmsr_srb_complete(srb, 0);
2660 		return;
2661 	}
2662 	if(acb->acb_flags & ACB_F_BUS_RESET) {
2663 		printf("arcmsr%d: bus reset and return busy \n", acb->pci_unit);
2664 		pccb->ccb_h.status |= CAM_SCSI_BUS_RESET;
2665 		arcmsr_srb_complete(srb, 0);
2666 		return;
2667 	}
2668 	if(acb->devstate[target][lun] == ARECA_RAID_GONE) {
2669 		u_int8_t block_cmd, cmd;
2670 
2671 		cmd = pccb->csio.cdb_io.cdb_bytes[0];
2672 		block_cmd = cmd & 0x0f;
2673 		if(block_cmd == 0x08 || block_cmd == 0x0a) {
2674 			printf("arcmsr%d:block 'read/write' command "
2675 				"with gone raid volume Cmd=0x%2x, TargetId=%d, Lun=%d \n"
2676 				, acb->pci_unit, cmd, target, lun);
2677 			pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
2678 			arcmsr_srb_complete(srb, 0);
2679 			return;
2680 		}
2681 	}
2682 	if((pccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_INPROG) {
2683 		if(nseg != 0) {
2684 			bus_dmamap_unload(acb->dm_segs_dmat, srb->dm_segs_dmamap);
2685 		}
2686 		arcmsr_srb_complete(srb, 0);
2687 		return;
2688 	}
2689 	if(acb->srboutstandingcount >= acb->firm_numbers_queue) {
2690 		if((acb->acb_flags & ACB_F_CAM_DEV_QFRZN) == 0)
2691 		{
2692 			xpt_freeze_simq(acb->psim, 1);
2693 			acb->acb_flags |= ACB_F_CAM_DEV_QFRZN;
2694 		}
2695 		pccb->ccb_h.status &= ~CAM_SIM_QUEUED;
2696 		pccb->ccb_h.status |= CAM_REQUEUE_REQ;
2697 		arcmsr_srb_complete(srb, 0);
2698 		return;
2699 	}
2700 	pccb->ccb_h.status |= CAM_SIM_QUEUED;
2701 	arcmsr_build_srb(srb, dm_segs, nseg);
2702 	arcmsr_post_srb(acb, srb);
2703 	if (pccb->ccb_h.timeout != CAM_TIME_INFINITY)
2704 	{
2705 		arcmsr_callout_init(&srb->ccb_callout);
2706 		callout_reset(&srb->ccb_callout, ((pccb->ccb_h.timeout + (ARCMSR_TIMEOUT_DELAY * 1000)) * hz) / 1000, arcmsr_srb_timeout, srb);
2707 		srb->srb_flags |= SRB_FLAG_TIMER_START;
2708 	}
2709 }
2710 /*
2711 *****************************************************************************************
2712 *****************************************************************************************
2713 */
2714 static u_int8_t arcmsr_seek_cmd2abort(union ccb *abortccb)
2715 {
2716 	struct CommandControlBlock *srb;
2717 	struct AdapterControlBlock *acb = (struct AdapterControlBlock *) abortccb->ccb_h.arcmsr_ccbacb_ptr;
2718 	u_int32_t intmask_org;
2719 	int i = 0;
2720 
2721 	acb->num_aborts++;
2722 	/*
2723 	***************************************************************************
2724 	** It is the upper layer do abort command this lock just prior to calling us.
2725 	** First determine if we currently own this command.
2726 	** Start by searching the device queue. If not found
2727 	** at all, and the system wanted us to just abort the
2728 	** command return success.
2729 	***************************************************************************
2730 	*/
2731 	if(acb->srboutstandingcount != 0) {
2732 		/* disable all outbound interrupt */
2733 		intmask_org = arcmsr_disable_allintr(acb);
2734 		for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
2735 			srb = acb->psrb_pool[i];
2736 			if(srb->srb_state == ARCMSR_SRB_START) {
2737 				if(srb->pccb == abortccb) {
2738 					srb->srb_state = ARCMSR_SRB_ABORTED;
2739 					printf("arcmsr%d:scsi id=%d lun=%d abort srb '%p'"
2740 						"outstanding command \n"
2741 						, acb->pci_unit, abortccb->ccb_h.target_id
2742 						, abortccb->ccb_h.target_lun, srb);
2743 					arcmsr_polling_srbdone(acb, srb);
2744 					/* enable outbound Post Queue, outbound doorbell Interrupt */
2745 					arcmsr_enable_allintr(acb, intmask_org);
2746 					return (TRUE);
2747 				}
2748 			}
2749 		}
2750 		/* enable outbound Post Queue, outbound doorbell Interrupt */
2751 		arcmsr_enable_allintr(acb, intmask_org);
2752 	}
2753 	return(FALSE);
2754 }
2755 /*
2756 ****************************************************************************
2757 ****************************************************************************
2758 */
2759 static void arcmsr_bus_reset(struct AdapterControlBlock *acb)
2760 {
2761 	int retry = 0;
2762 
2763 	acb->num_resets++;
2764 	acb->acb_flags |= ACB_F_BUS_RESET;
2765 	while(acb->srboutstandingcount != 0 && retry < 400) {
2766 		arcmsr_interrupt(acb);
2767 		UDELAY(25000);
2768 		retry++;
2769 	}
2770 	arcmsr_iop_reset(acb);
2771 	acb->acb_flags &= ~ACB_F_BUS_RESET;
2772 }
2773 /*
2774 **************************************************************************
2775 **************************************************************************
2776 */
2777 static void arcmsr_handle_virtual_command(struct AdapterControlBlock *acb,
2778 		union ccb *pccb)
2779 {
2780 	if (pccb->ccb_h.target_lun) {
2781 		pccb->ccb_h.status |= CAM_DEV_NOT_THERE;
2782 		xpt_done(pccb);
2783 		return;
2784 	}
2785 	pccb->ccb_h.status |= CAM_REQ_CMP;
2786 	switch (pccb->csio.cdb_io.cdb_bytes[0]) {
2787 	case INQUIRY: {
2788 		unsigned char inqdata[36];
2789 		char *buffer = pccb->csio.data_ptr;
2790 
2791 		inqdata[0] = T_PROCESSOR;	/* Periph Qualifier & Periph Dev Type */
2792 		inqdata[1] = 0;				/* rem media bit & Dev Type Modifier */
2793 		inqdata[2] = 0;				/* ISO, ECMA, & ANSI versions */
2794 		inqdata[3] = 0;
2795 		inqdata[4] = 31;			/* length of additional data */
2796 		inqdata[5] = 0;
2797 		inqdata[6] = 0;
2798 		inqdata[7] = 0;
2799 		strncpy(&inqdata[8], "Areca   ", 8);	/* Vendor Identification */
2800 		strncpy(&inqdata[16], "RAID controller ", 16);	/* Product Identification */
2801 		strncpy(&inqdata[32], "R001", 4); /* Product Revision */
2802 		memcpy(buffer, inqdata, sizeof(inqdata));
2803 		xpt_done(pccb);
2804 	}
2805 	break;
2806 	case WRITE_BUFFER:
2807 	case READ_BUFFER: {
2808 		if (arcmsr_iop_message_xfer(acb, pccb)) {
2809 			pccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
2810 			pccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
2811 		}
2812 		xpt_done(pccb);
2813 	}
2814 	break;
2815 	default:
2816 		xpt_done(pccb);
2817 	}
2818 }
2819 /*
2820 *********************************************************************
2821 *********************************************************************
2822 */
2823 static void arcmsr_action(struct cam_sim *psim, union ccb *pccb)
2824 {
2825 	struct AdapterControlBlock *acb;
2826 
2827 	acb = (struct AdapterControlBlock *) cam_sim_softc(psim);
2828 	if(acb == NULL) {
2829 		pccb->ccb_h.status |= CAM_REQ_INVALID;
2830 		xpt_done(pccb);
2831 		return;
2832 	}
2833 	switch (pccb->ccb_h.func_code) {
2834 	case XPT_SCSI_IO: {
2835 			struct CommandControlBlock *srb;
2836 			int target = pccb->ccb_h.target_id;
2837 			int error;
2838 
2839 			if(target == 16) {
2840 				/* virtual device for iop message transfer */
2841 				arcmsr_handle_virtual_command(acb, pccb);
2842 				return;
2843 			}
2844 			if((srb = arcmsr_get_freesrb(acb)) == NULL) {
2845 				pccb->ccb_h.status |= CAM_RESRC_UNAVAIL;
2846 				xpt_done(pccb);
2847 				return;
2848 			}
2849 			pccb->ccb_h.arcmsr_ccbsrb_ptr = srb;
2850 			pccb->ccb_h.arcmsr_ccbacb_ptr = acb;
2851 			srb->pccb = pccb;
2852 			error =	bus_dmamap_load_ccb(acb->dm_segs_dmat
2853 				, srb->dm_segs_dmamap
2854 				, pccb
2855 				, arcmsr_execute_srb, srb, /*flags*/0);
2856 			if(error == EINPROGRESS) {
2857 				xpt_freeze_simq(acb->psim, 1);
2858 				pccb->ccb_h.status |= CAM_RELEASE_SIMQ;
2859 			}
2860 			break;
2861 		}
2862 	case XPT_TARGET_IO: {
2863 			/* target mode not yet support vendor specific commands. */
2864 			pccb->ccb_h.status |= CAM_REQ_CMP;
2865 			xpt_done(pccb);
2866 			break;
2867 		}
2868 	case XPT_PATH_INQ: {
2869 			struct ccb_pathinq *cpi = &pccb->cpi;
2870 
2871 			cpi->version_num = 1;
2872 			cpi->hba_inquiry = PI_SDTR_ABLE | PI_TAG_ABLE;
2873 			cpi->target_sprt = 0;
2874 			cpi->hba_misc = 0;
2875 			cpi->hba_eng_cnt = 0;
2876 			cpi->max_target = ARCMSR_MAX_TARGETID;        /* 0-16 */
2877 			cpi->max_lun = ARCMSR_MAX_TARGETLUN;	    /* 0-7 */
2878 			cpi->initiator_id = ARCMSR_SCSI_INITIATOR_ID; /* 255 */
2879 			cpi->bus_id = cam_sim_bus(psim);
2880 			strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
2881 			strncpy(cpi->hba_vid, "ARCMSR", HBA_IDLEN);
2882 			strncpy(cpi->dev_name, cam_sim_name(psim), DEV_IDLEN);
2883 			cpi->unit_number = cam_sim_unit(psim);
2884 		#ifdef	CAM_NEW_TRAN_CODE
2885 			if(acb->adapter_bus_speed == ACB_BUS_SPEED_6G)
2886 				cpi->base_transfer_speed = 600000;
2887 			else
2888 				cpi->base_transfer_speed = 300000;
2889 			if((acb->vendor_device_id == PCIDevVenIDARC1880) ||
2890 			   (acb->vendor_device_id == PCIDevVenIDARC1680) ||
2891 			   (acb->vendor_device_id == PCIDevVenIDARC1214))
2892 			{
2893 				cpi->transport = XPORT_SAS;
2894 				cpi->transport_version = 0;
2895 				cpi->protocol_version = SCSI_REV_SPC2;
2896 			}
2897 			else
2898 			{
2899 				cpi->transport = XPORT_SPI;
2900 				cpi->transport_version = 2;
2901 				cpi->protocol_version = SCSI_REV_2;
2902 			}
2903 			cpi->protocol = PROTO_SCSI;
2904 		#endif
2905 			cpi->ccb_h.status |= CAM_REQ_CMP;
2906 			xpt_done(pccb);
2907 			break;
2908 		}
2909 	case XPT_ABORT: {
2910 			union ccb *pabort_ccb;
2911 
2912 			pabort_ccb = pccb->cab.abort_ccb;
2913 			switch (pabort_ccb->ccb_h.func_code) {
2914 			case XPT_ACCEPT_TARGET_IO:
2915 			case XPT_IMMED_NOTIFY:
2916 			case XPT_CONT_TARGET_IO:
2917 				if(arcmsr_seek_cmd2abort(pabort_ccb)==TRUE) {
2918 					pabort_ccb->ccb_h.status |= CAM_REQ_ABORTED;
2919 					xpt_done(pabort_ccb);
2920 					pccb->ccb_h.status |= CAM_REQ_CMP;
2921 				} else {
2922 					xpt_print_path(pabort_ccb->ccb_h.path);
2923 					printf("Not found\n");
2924 					pccb->ccb_h.status |= CAM_PATH_INVALID;
2925 				}
2926 				break;
2927 			case XPT_SCSI_IO:
2928 				pccb->ccb_h.status |= CAM_UA_ABORT;
2929 				break;
2930 			default:
2931 				pccb->ccb_h.status |= CAM_REQ_INVALID;
2932 				break;
2933 			}
2934 			xpt_done(pccb);
2935 			break;
2936 		}
2937 	case XPT_RESET_BUS:
2938 	case XPT_RESET_DEV: {
2939 			u_int32_t     i;
2940 
2941 			arcmsr_bus_reset(acb);
2942 			for (i=0; i < 500; i++) {
2943 				DELAY(1000);
2944 			}
2945 			pccb->ccb_h.status |= CAM_REQ_CMP;
2946 			xpt_done(pccb);
2947 			break;
2948 		}
2949 	case XPT_TERM_IO: {
2950 			pccb->ccb_h.status |= CAM_REQ_INVALID;
2951 			xpt_done(pccb);
2952 			break;
2953 		}
2954 	case XPT_GET_TRAN_SETTINGS: {
2955 			struct ccb_trans_settings *cts;
2956 
2957 			if(pccb->ccb_h.target_id == 16) {
2958 				pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
2959 				xpt_done(pccb);
2960 				break;
2961 			}
2962 			cts = &pccb->cts;
2963 		#ifdef	CAM_NEW_TRAN_CODE
2964 			{
2965 				struct ccb_trans_settings_scsi *scsi;
2966 				struct ccb_trans_settings_spi *spi;
2967 				struct ccb_trans_settings_sas *sas;
2968 
2969 				scsi = &cts->proto_specific.scsi;
2970 				scsi->flags = CTS_SCSI_FLAGS_TAG_ENB;
2971 				scsi->valid = CTS_SCSI_VALID_TQ;
2972 				cts->protocol = PROTO_SCSI;
2973 
2974 				if((acb->vendor_device_id == PCIDevVenIDARC1880) ||
2975 				   (acb->vendor_device_id == PCIDevVenIDARC1680) ||
2976 				   (acb->vendor_device_id == PCIDevVenIDARC1214))
2977 				{
2978 					cts->protocol_version = SCSI_REV_SPC2;
2979 					cts->transport_version = 0;
2980 					cts->transport = XPORT_SAS;
2981 					sas = &cts->xport_specific.sas;
2982 					sas->valid = CTS_SAS_VALID_SPEED;
2983 					if((acb->vendor_device_id == PCIDevVenIDARC1880) ||
2984 					   (acb->vendor_device_id == PCIDevVenIDARC1214))
2985 						sas->bitrate = 600000;
2986 					else if(acb->vendor_device_id == PCIDevVenIDARC1680)
2987 						sas->bitrate = 300000;
2988 				}
2989 				else
2990 				{
2991 					cts->protocol_version = SCSI_REV_2;
2992 					cts->transport_version = 2;
2993 					cts->transport = XPORT_SPI;
2994 					spi = &cts->xport_specific.spi;
2995 					spi->flags = CTS_SPI_FLAGS_DISC_ENB;
2996 					spi->sync_period = 2;
2997 					spi->sync_offset = 32;
2998 					spi->bus_width = MSG_EXT_WDTR_BUS_16_BIT;
2999 					spi->valid = CTS_SPI_VALID_DISC
3000 						| CTS_SPI_VALID_SYNC_RATE
3001 						| CTS_SPI_VALID_SYNC_OFFSET
3002 						| CTS_SPI_VALID_BUS_WIDTH;
3003 				}
3004 			}
3005 		#else
3006 			{
3007 				cts->flags = (CCB_TRANS_DISC_ENB | CCB_TRANS_TAG_ENB);
3008 				cts->sync_period = 2;
3009 				cts->sync_offset = 32;
3010 				cts->bus_width = MSG_EXT_WDTR_BUS_16_BIT;
3011 				cts->valid = CCB_TRANS_SYNC_RATE_VALID |
3012 				CCB_TRANS_SYNC_OFFSET_VALID |
3013 				CCB_TRANS_BUS_WIDTH_VALID |
3014 				CCB_TRANS_DISC_VALID |
3015 				CCB_TRANS_TQ_VALID;
3016 			}
3017 		#endif
3018 			pccb->ccb_h.status |= CAM_REQ_CMP;
3019 			xpt_done(pccb);
3020 			break;
3021 		}
3022 	case XPT_SET_TRAN_SETTINGS: {
3023 			pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
3024 			xpt_done(pccb);
3025 			break;
3026 		}
3027 	case XPT_CALC_GEOMETRY:
3028 			if(pccb->ccb_h.target_id == 16) {
3029 				pccb->ccb_h.status |= CAM_FUNC_NOTAVAIL;
3030 				xpt_done(pccb);
3031 				break;
3032 			}
3033 #if __FreeBSD_version >= 500000
3034 			cam_calc_geometry(&pccb->ccg, 1);
3035 #else
3036 			{
3037 			struct ccb_calc_geometry *ccg;
3038 			u_int32_t size_mb;
3039 			u_int32_t secs_per_cylinder;
3040 
3041 			ccg = &pccb->ccg;
3042 			if (ccg->block_size == 0) {
3043 				pccb->ccb_h.status = CAM_REQ_INVALID;
3044 				xpt_done(pccb);
3045 				break;
3046 			}
3047 			if(((1024L * 1024L)/ccg->block_size) < 0) {
3048 				pccb->ccb_h.status = CAM_REQ_INVALID;
3049 				xpt_done(pccb);
3050 				break;
3051 			}
3052 			size_mb = ccg->volume_size/((1024L * 1024L)/ccg->block_size);
3053 			if(size_mb > 1024 ) {
3054 				ccg->heads = 255;
3055 				ccg->secs_per_track = 63;
3056 			} else {
3057 				ccg->heads = 64;
3058 				ccg->secs_per_track = 32;
3059 			}
3060 			secs_per_cylinder = ccg->heads * ccg->secs_per_track;
3061 			ccg->cylinders = ccg->volume_size / secs_per_cylinder;
3062 			pccb->ccb_h.status |= CAM_REQ_CMP;
3063 			}
3064 #endif
3065 			xpt_done(pccb);
3066 			break;
3067 	default:
3068 		pccb->ccb_h.status |= CAM_REQ_INVALID;
3069 		xpt_done(pccb);
3070 		break;
3071 	}
3072 }
3073 /*
3074 **********************************************************************
3075 **********************************************************************
3076 */
3077 static void arcmsr_start_hba_bgrb(struct AdapterControlBlock *acb)
3078 {
3079 	acb->acb_flags |= ACB_F_MSG_START_BGRB;
3080 	CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3081 	if(!arcmsr_hba_wait_msgint_ready(acb)) {
3082 		printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3083 	}
3084 }
3085 /*
3086 **********************************************************************
3087 **********************************************************************
3088 */
3089 static void arcmsr_start_hbb_bgrb(struct AdapterControlBlock *acb)
3090 {
3091 	acb->acb_flags |= ACB_F_MSG_START_BGRB;
3092 	CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell,  ARCMSR_MESSAGE_START_BGRB);
3093 	if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3094 		printf( "arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3095 	}
3096 }
3097 /*
3098 **********************************************************************
3099 **********************************************************************
3100 */
3101 static void arcmsr_start_hbc_bgrb(struct AdapterControlBlock *acb)
3102 {
3103 	acb->acb_flags |= ACB_F_MSG_START_BGRB;
3104 	CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3105 	CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
3106 	if(!arcmsr_hbc_wait_msgint_ready(acb)) {
3107 		printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3108 	}
3109 }
3110 /*
3111 **********************************************************************
3112 **********************************************************************
3113 */
3114 static void arcmsr_start_hbd_bgrb(struct AdapterControlBlock *acb)
3115 {
3116 	acb->acb_flags |= ACB_F_MSG_START_BGRB;
3117 	CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_START_BGRB);
3118 	if(!arcmsr_hbd_wait_msgint_ready(acb)) {
3119 		printf("arcmsr%d: wait 'start adapter background rebulid' timeout \n", acb->pci_unit);
3120 	}
3121 }
3122 /*
3123 **********************************************************************
3124 **********************************************************************
3125 */
3126 static void arcmsr_start_adapter_bgrb(struct AdapterControlBlock *acb)
3127 {
3128 	switch (acb->adapter_type) {
3129 	case ACB_ADAPTER_TYPE_A:
3130 		arcmsr_start_hba_bgrb(acb);
3131 		break;
3132 	case ACB_ADAPTER_TYPE_B:
3133 		arcmsr_start_hbb_bgrb(acb);
3134 		break;
3135 	case ACB_ADAPTER_TYPE_C:
3136 		arcmsr_start_hbc_bgrb(acb);
3137 		break;
3138 	case ACB_ADAPTER_TYPE_D:
3139 		arcmsr_start_hbd_bgrb(acb);
3140 		break;
3141 	}
3142 }
3143 /*
3144 **********************************************************************
3145 **
3146 **********************************************************************
3147 */
3148 static void arcmsr_polling_hba_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3149 {
3150 	struct CommandControlBlock *srb;
3151 	u_int32_t flag_srb, outbound_intstatus, poll_srb_done=0, poll_count=0;
3152 	u_int16_t	error;
3153 
3154 polling_ccb_retry:
3155 	poll_count++;
3156 	outbound_intstatus=CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_intstatus) & acb->outbound_int_enable;
3157 	CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_intstatus, outbound_intstatus);	/*clear interrupt*/
3158 	bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3159 	while(1) {
3160 		if((flag_srb = CHIP_REG_READ32(HBA_MessageUnit,
3161 			0, outbound_queueport)) == 0xFFFFFFFF) {
3162 			if(poll_srb_done) {
3163 				break;/*chip FIFO no ccb for completion already*/
3164 			} else {
3165 				UDELAY(25000);
3166 				if ((poll_count > 100) && (poll_srb != NULL)) {
3167 					break;
3168 				}
3169 				goto polling_ccb_retry;
3170 			}
3171 		}
3172 		/* check if command done with no error*/
3173 		srb = (struct CommandControlBlock *)
3174 			(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
3175         error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
3176 		poll_srb_done = (srb == poll_srb) ? 1:0;
3177 		if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3178 			if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3179 				printf("arcmsr%d: scsi id=%d lun=%d srb='%p'"
3180 					"poll command abort successfully \n"
3181 					, acb->pci_unit
3182 					, srb->pccb->ccb_h.target_id
3183 					, srb->pccb->ccb_h.target_lun, srb);
3184 				srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3185 				arcmsr_srb_complete(srb, 1);
3186 				continue;
3187 			}
3188 			printf("arcmsr%d: polling get an illegal srb command done srb='%p'"
3189 				"srboutstandingcount=%d \n"
3190 				, acb->pci_unit
3191 				, srb, acb->srboutstandingcount);
3192 			continue;
3193 		}
3194 		arcmsr_report_srb_state(acb, srb, error);
3195 	}	/*drain reply FIFO*/
3196 }
3197 /*
3198 **********************************************************************
3199 **
3200 **********************************************************************
3201 */
3202 static void arcmsr_polling_hbb_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3203 {
3204 	struct HBB_MessageUnit *phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3205 	struct CommandControlBlock *srb;
3206 	u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
3207 	int index;
3208 	u_int16_t	error;
3209 
3210 polling_ccb_retry:
3211 	poll_count++;
3212 	CHIP_REG_WRITE32(HBB_DOORBELL,
3213 	0, iop2drv_doorbell, ARCMSR_DOORBELL_INT_CLEAR_PATTERN); /* clear doorbell interrupt */
3214 	bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3215 	while(1) {
3216 		index = phbbmu->doneq_index;
3217 		if((flag_srb = phbbmu->done_qbuffer[index]) == 0) {
3218 			if(poll_srb_done) {
3219 				break;/*chip FIFO no ccb for completion already*/
3220 			} else {
3221 				UDELAY(25000);
3222 			    if ((poll_count > 100) && (poll_srb != NULL)) {
3223 					break;
3224 				}
3225 				goto polling_ccb_retry;
3226 			}
3227 		}
3228 		phbbmu->done_qbuffer[index] = 0;
3229 		index++;
3230 		index %= ARCMSR_MAX_HBB_POSTQUEUE;     /*if last index number set it to 0 */
3231 		phbbmu->doneq_index = index;
3232 		/* check if command done with no error*/
3233 		srb = (struct CommandControlBlock *)
3234 			(acb->vir2phy_offset+(flag_srb << 5));/*frame must be 32 bytes aligned*/
3235         error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE0)?TRUE:FALSE;
3236 		poll_srb_done = (srb == poll_srb) ? 1:0;
3237 		if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3238 			if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3239 				printf("arcmsr%d: scsi id=%d lun=%d srb='%p'"
3240 					"poll command abort successfully \n"
3241 					, acb->pci_unit
3242 					, srb->pccb->ccb_h.target_id
3243 					, srb->pccb->ccb_h.target_lun, srb);
3244 				srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3245 				arcmsr_srb_complete(srb, 1);
3246 				continue;
3247 			}
3248 			printf("arcmsr%d: polling get an illegal srb command done srb='%p'"
3249 				"srboutstandingcount=%d \n"
3250 				, acb->pci_unit
3251 				, srb, acb->srboutstandingcount);
3252 			continue;
3253 		}
3254 		arcmsr_report_srb_state(acb, srb, error);
3255 	}	/*drain reply FIFO*/
3256 }
3257 /*
3258 **********************************************************************
3259 **
3260 **********************************************************************
3261 */
3262 static void arcmsr_polling_hbc_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3263 {
3264 	struct CommandControlBlock *srb;
3265 	u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
3266 	u_int16_t	error;
3267 
3268 polling_ccb_retry:
3269 	poll_count++;
3270 	bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3271 	while(1) {
3272 		if(!(CHIP_REG_READ32(HBC_MessageUnit, 0, host_int_status) & ARCMSR_HBCMU_OUTBOUND_POSTQUEUE_ISR)) {
3273 			if(poll_srb_done) {
3274 				break;/*chip FIFO no ccb for completion already*/
3275 			} else {
3276 				UDELAY(25000);
3277 			    if ((poll_count > 100) && (poll_srb != NULL)) {
3278 					break;
3279 				}
3280 			    if (acb->srboutstandingcount == 0) {
3281 				    break;
3282 			    }
3283 				goto polling_ccb_retry;
3284 			}
3285 		}
3286 		flag_srb = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_queueport_low);
3287 		/* check if command done with no error*/
3288 		srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/
3289         error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1)?TRUE:FALSE;
3290 		if (poll_srb != NULL)
3291 			poll_srb_done = (srb == poll_srb) ? 1:0;
3292 		if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3293 			if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3294 				printf("arcmsr%d: scsi id=%d lun=%d srb='%p'poll command abort successfully \n"
3295 						, acb->pci_unit, srb->pccb->ccb_h.target_id, srb->pccb->ccb_h.target_lun, srb);
3296 				srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3297 				arcmsr_srb_complete(srb, 1);
3298 				continue;
3299 			}
3300 			printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n"
3301 					, acb->pci_unit, srb, acb->srboutstandingcount);
3302 			continue;
3303 		}
3304 		arcmsr_report_srb_state(acb, srb, error);
3305 	}	/*drain reply FIFO*/
3306 }
3307 /*
3308 **********************************************************************
3309 **
3310 **********************************************************************
3311 */
3312 static void arcmsr_polling_hbd_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3313 {
3314 	struct HBD_MessageUnit0 *phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
3315 	struct CommandControlBlock *srb;
3316 	u_int32_t flag_srb, poll_srb_done=0, poll_count=0;
3317 	u_int32_t outbound_write_pointer;
3318 	u_int16_t	error, doneq_index;
3319 
3320 polling_ccb_retry:
3321 	poll_count++;
3322 	bus_dmamap_sync(acb->srb_dmat, acb->srb_dmamap, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE);
3323 	while(1) {
3324 		outbound_write_pointer = phbdmu->done_qbuffer[0].addressLow;
3325 		doneq_index = phbdmu->doneq_index;
3326 		if ((outbound_write_pointer & 0xFF) == (doneq_index & 0xFF)) {
3327 			if(poll_srb_done) {
3328 				break;/*chip FIFO no ccb for completion already*/
3329 			} else {
3330 				UDELAY(25000);
3331 			    if ((poll_count > 100) && (poll_srb != NULL)) {
3332 					break;
3333 				}
3334 			    if (acb->srboutstandingcount == 0) {
3335 				    break;
3336 			    }
3337 				goto polling_ccb_retry;
3338 			}
3339 		}
3340 		doneq_index = arcmsr_get_doneq_index(phbdmu);
3341 		flag_srb = phbdmu->done_qbuffer[(doneq_index & 0xFF)+1].addressLow;
3342 		/* check if command done with no error*/
3343 		srb = (struct CommandControlBlock *)(acb->vir2phy_offset+(flag_srb & 0xFFFFFFE0));/*frame must be 32 bytes aligned*/
3344         error = (flag_srb & ARCMSR_SRBREPLY_FLAG_ERROR_MODE1) ? TRUE : FALSE;
3345 		CHIP_REG_WRITE32(HBD_MessageUnit, 0, outboundlist_read_pointer, doneq_index);
3346 		if (poll_srb != NULL)
3347 			poll_srb_done = (srb == poll_srb) ? 1:0;
3348 		if((srb->acb != acb) || (srb->srb_state != ARCMSR_SRB_START)) {
3349 			if(srb->srb_state == ARCMSR_SRB_ABORTED) {
3350 				printf("arcmsr%d: scsi id=%d lun=%d srb='%p'poll command abort successfully \n"
3351 						, acb->pci_unit, srb->pccb->ccb_h.target_id, srb->pccb->ccb_h.target_lun, srb);
3352 				srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
3353 				arcmsr_srb_complete(srb, 1);
3354 				continue;
3355 			}
3356 			printf("arcmsr%d: polling get an illegal srb command done srb='%p'srboutstandingcount=%d \n"
3357 					, acb->pci_unit, srb, acb->srboutstandingcount);
3358 			continue;
3359 		}
3360 		arcmsr_report_srb_state(acb, srb, error);
3361 	}	/*drain reply FIFO*/
3362 }
3363 /*
3364 **********************************************************************
3365 **********************************************************************
3366 */
3367 static void arcmsr_polling_srbdone(struct AdapterControlBlock *acb, struct CommandControlBlock *poll_srb)
3368 {
3369 	switch (acb->adapter_type) {
3370 	case ACB_ADAPTER_TYPE_A: {
3371 			arcmsr_polling_hba_srbdone(acb, poll_srb);
3372 		}
3373 		break;
3374 	case ACB_ADAPTER_TYPE_B: {
3375 			arcmsr_polling_hbb_srbdone(acb, poll_srb);
3376 		}
3377 		break;
3378 	case ACB_ADAPTER_TYPE_C: {
3379 			arcmsr_polling_hbc_srbdone(acb, poll_srb);
3380 		}
3381 		break;
3382 	case ACB_ADAPTER_TYPE_D: {
3383 			arcmsr_polling_hbd_srbdone(acb, poll_srb);
3384 		}
3385 		break;
3386 	}
3387 }
3388 /*
3389 **********************************************************************
3390 **********************************************************************
3391 */
3392 static void arcmsr_get_hba_config(struct AdapterControlBlock *acb)
3393 {
3394 	char *acb_firm_model = acb->firm_model;
3395 	char *acb_firm_version = acb->firm_version;
3396 	char *acb_device_map = acb->device_map;
3397 	size_t iop_firm_model = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);	/*firm_model,15,60-67*/
3398 	size_t iop_firm_version = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]);	/*firm_version,17,68-83*/
3399 	size_t iop_device_map = offsetof(struct HBA_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3400 	int i;
3401 
3402 	CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3403 	if(!arcmsr_hba_wait_msgint_ready(acb)) {
3404 		printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3405 	}
3406 	i = 0;
3407 	while(i < 8) {
3408 		*acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3409 		/* 8 bytes firm_model, 15, 60-67*/
3410 		acb_firm_model++;
3411 		i++;
3412 	}
3413 	i=0;
3414 	while(i < 16) {
3415 		*acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
3416 		/* 16 bytes firm_version, 17, 68-83*/
3417 		acb_firm_version++;
3418 		i++;
3419 	}
3420 	i=0;
3421 	while(i < 16) {
3422 		*acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
3423 		acb_device_map++;
3424 		i++;
3425 	}
3426 	printf("ARECA RAID ADAPTER%d: %s \n", acb->pci_unit, ARCMSR_DRIVER_VERSION);
3427 	printf("ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n", acb->pci_unit, acb->firm_version);
3428 	acb->firm_request_len = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[1]);   /*firm_request_len, 1, 04-07*/
3429 	acb->firm_numbers_queue = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
3430 	acb->firm_sdram_size = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[3]);    /*firm_sdram_size, 3, 12-15*/
3431 	acb->firm_ide_channels = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[4]);  /*firm_ide_channels, 4, 16-19*/
3432 	acb->firm_cfg_version = CHIP_REG_READ32(HBA_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]);	/*firm_cfg_version,  25, 	  */
3433 }
3434 /*
3435 **********************************************************************
3436 **********************************************************************
3437 */
3438 static void arcmsr_get_hbb_config(struct AdapterControlBlock *acb)
3439 {
3440 	char *acb_firm_model = acb->firm_model;
3441 	char *acb_firm_version = acb->firm_version;
3442 	char *acb_device_map = acb->device_map;
3443 	size_t iop_firm_model = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);	/*firm_model,15,60-67*/
3444 	size_t iop_firm_version = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]);	/*firm_version,17,68-83*/
3445 	size_t iop_device_map = offsetof(struct HBB_RWBUFFER, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3446 	int i;
3447 
3448 	CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_GET_CONFIG);
3449 	if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3450 		printf( "arcmsr%d: wait" "'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3451 	}
3452 	i = 0;
3453 	while(i < 8) {
3454 		*acb_firm_model = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_model+i);
3455 		/* 8 bytes firm_model, 15, 60-67*/
3456 		acb_firm_model++;
3457 		i++;
3458 	}
3459 	i = 0;
3460 	while(i < 16) {
3461 		*acb_firm_version = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_firm_version+i);
3462 		/* 16 bytes firm_version, 17, 68-83*/
3463 		acb_firm_version++;
3464 		i++;
3465 	}
3466 	i = 0;
3467 	while(i < 16) {
3468 		*acb_device_map = bus_space_read_1(acb->btag[1], acb->bhandle[1], iop_device_map+i);
3469 		acb_device_map++;
3470 		i++;
3471 	}
3472 	printf("ARECA RAID ADAPTER%d: %s \n", acb->pci_unit, ARCMSR_DRIVER_VERSION);
3473 	printf("ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n", acb->pci_unit, acb->firm_version);
3474 	acb->firm_request_len = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1]);   /*firm_request_len, 1, 04-07*/
3475 	acb->firm_numbers_queue = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2]); /*firm_numbers_queue, 2, 08-11*/
3476 	acb->firm_sdram_size = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3]);    /*firm_sdram_size, 3, 12-15*/
3477 	acb->firm_ide_channels = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4]);  /*firm_ide_channels, 4, 16-19*/
3478 	acb->firm_cfg_version = CHIP_REG_READ32(HBB_RWBUFFER, 1, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]);	/*firm_cfg_version,  25, 	  */
3479 }
3480 /*
3481 **********************************************************************
3482 **********************************************************************
3483 */
3484 static void arcmsr_get_hbc_config(struct AdapterControlBlock *acb)
3485 {
3486 	char *acb_firm_model = acb->firm_model;
3487 	char *acb_firm_version = acb->firm_version;
3488 	char *acb_device_map = acb->device_map;
3489 	size_t iop_firm_model = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);   /*firm_model,15,60-67*/
3490 	size_t iop_firm_version = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
3491 	size_t iop_device_map = offsetof(struct HBC_MessageUnit,msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3492 	int i;
3493 
3494 	CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3495 	CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
3496 	if(!arcmsr_hbc_wait_msgint_ready(acb)) {
3497 		printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3498 	}
3499 	i = 0;
3500 	while(i < 8) {
3501 		*acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3502 		/* 8 bytes firm_model, 15, 60-67*/
3503 		acb_firm_model++;
3504 		i++;
3505 	}
3506 	i = 0;
3507 	while(i < 16) {
3508 		*acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
3509 		/* 16 bytes firm_version, 17, 68-83*/
3510 		acb_firm_version++;
3511 		i++;
3512 	}
3513 	i = 0;
3514 	while(i < 16) {
3515 		*acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
3516 		acb_device_map++;
3517 		i++;
3518 	}
3519 	printf("ARECA RAID ADAPTER%d: %s \n", acb->pci_unit, ARCMSR_DRIVER_VERSION);
3520 	printf("ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n", acb->pci_unit, acb->firm_version);
3521 	acb->firm_request_len	= CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[1]);	/*firm_request_len,   1, 04-07*/
3522 	acb->firm_numbers_queue	= CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[2]);	/*firm_numbers_queue, 2, 08-11*/
3523 	acb->firm_sdram_size	= CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[3]);	/*firm_sdram_size,    3, 12-15*/
3524 	acb->firm_ide_channels	= CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[4]);	/*firm_ide_channels,  4, 16-19*/
3525 	acb->firm_cfg_version	= CHIP_REG_READ32(HBC_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]);	/*firm_cfg_version,  25, 	  */
3526 }
3527 /*
3528 **********************************************************************
3529 **********************************************************************
3530 */
3531 static void arcmsr_get_hbd_config(struct AdapterControlBlock *acb)
3532 {
3533 	char *acb_firm_model = acb->firm_model;
3534 	char *acb_firm_version = acb->firm_version;
3535 	char *acb_device_map = acb->device_map;
3536 	size_t iop_firm_model = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_MODEL_OFFSET]);   /*firm_model,15,60-67*/
3537 	size_t iop_firm_version = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_VERS_OFFSET]); /*firm_version,17,68-83*/
3538 	size_t iop_device_map = offsetof(struct HBD_MessageUnit, msgcode_rwbuffer[ARCMSR_FW_DEVMAP_OFFSET]);
3539 	int i;
3540 
3541 	if(CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell) & ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE)
3542 		CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, ARCMSR_HBDMU_IOP2DRV_MESSAGE_CMD_DONE_CLEAR);
3543 	CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_GET_CONFIG);
3544 	if(!arcmsr_hbd_wait_msgint_ready(acb)) {
3545 		printf("arcmsr%d: wait 'get adapter firmware miscellaneous data' timeout \n", acb->pci_unit);
3546 	}
3547 	i = 0;
3548 	while(i < 8) {
3549 		*acb_firm_model = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_model+i);
3550 		/* 8 bytes firm_model, 15, 60-67*/
3551 		acb_firm_model++;
3552 		i++;
3553 	}
3554 	i = 0;
3555 	while(i < 16) {
3556 		*acb_firm_version = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_firm_version+i);
3557 		/* 16 bytes firm_version, 17, 68-83*/
3558 		acb_firm_version++;
3559 		i++;
3560 	}
3561 	i = 0;
3562 	while(i < 16) {
3563 		*acb_device_map = bus_space_read_1(acb->btag[0], acb->bhandle[0], iop_device_map+i);
3564 		acb_device_map++;
3565 		i++;
3566 	}
3567 	printf("ARECA RAID ADAPTER%d: %s \n", acb->pci_unit, ARCMSR_DRIVER_VERSION);
3568 	printf("ARECA RAID ADAPTER%d: FIRMWARE VERSION %s \n", acb->pci_unit, acb->firm_version);
3569 	acb->firm_request_len	= CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[2]);	/*firm_request_len,   1, 04-07*/
3570 	acb->firm_numbers_queue	= CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[3]);	/*firm_numbers_queue, 2, 08-11*/
3571 	acb->firm_sdram_size	= CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[4]);	/*firm_sdram_size,    3, 12-15*/
3572 	acb->firm_ide_channels	= CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[5]);	/*firm_ide_channels,  4, 16-19*/
3573 	acb->firm_cfg_version	= CHIP_REG_READ32(HBD_MessageUnit, 0, msgcode_rwbuffer[ARCMSR_FW_CFGVER_OFFSET]);	/*firm_cfg_version,  25, 	  */
3574 }
3575 /*
3576 **********************************************************************
3577 **********************************************************************
3578 */
3579 static void arcmsr_get_firmware_spec(struct AdapterControlBlock *acb)
3580 {
3581 	switch (acb->adapter_type) {
3582 	case ACB_ADAPTER_TYPE_A: {
3583 			arcmsr_get_hba_config(acb);
3584 		}
3585 		break;
3586 	case ACB_ADAPTER_TYPE_B: {
3587 			arcmsr_get_hbb_config(acb);
3588 		}
3589 		break;
3590 	case ACB_ADAPTER_TYPE_C: {
3591 			arcmsr_get_hbc_config(acb);
3592 		}
3593 		break;
3594 	case ACB_ADAPTER_TYPE_D: {
3595 			arcmsr_get_hbd_config(acb);
3596 		}
3597 		break;
3598 	}
3599 }
3600 /*
3601 **********************************************************************
3602 **********************************************************************
3603 */
3604 static void arcmsr_wait_firmware_ready( struct AdapterControlBlock *acb)
3605 {
3606 	int	timeout=0;
3607 
3608 	switch (acb->adapter_type) {
3609 	case ACB_ADAPTER_TYPE_A: {
3610 			while ((CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_OUTBOUND_MESG1_FIRMWARE_OK) == 0)
3611 			{
3612 				if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
3613 				{
3614 					printf( "arcmsr%d:timed out waiting for firmware \n", acb->pci_unit);
3615 					return;
3616 				}
3617 				UDELAY(15000); /* wait 15 milli-seconds */
3618 			}
3619 		}
3620 		break;
3621 	case ACB_ADAPTER_TYPE_B: {
3622 			while ((CHIP_REG_READ32(HBB_DOORBELL, 0, iop2drv_doorbell) & ARCMSR_MESSAGE_FIRMWARE_OK) == 0)
3623 			{
3624 				if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
3625 				{
3626 					printf( "arcmsr%d: timed out waiting for firmware \n", acb->pci_unit);
3627 					return;
3628 				}
3629 				UDELAY(15000); /* wait 15 milli-seconds */
3630 			}
3631 			CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_END_OF_INTERRUPT);
3632 		}
3633 		break;
3634 	case ACB_ADAPTER_TYPE_C: {
3635 			while ((CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBCMU_MESSAGE_FIRMWARE_OK) == 0)
3636 			{
3637 				if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
3638 				{
3639 					printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit);
3640 					return;
3641 				}
3642 				UDELAY(15000); /* wait 15 milli-seconds */
3643 			}
3644 		}
3645 		break;
3646 	case ACB_ADAPTER_TYPE_D: {
3647 			while ((CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_msgaddr1) & ARCMSR_HBDMU_MESSAGE_FIRMWARE_OK) == 0)
3648 			{
3649 				if (timeout++ > 2000) /* (2000*15)/1000 = 30 sec */
3650 				{
3651 					printf( "arcmsr%d:timed out waiting for firmware ready\n", acb->pci_unit);
3652 					return;
3653 				}
3654 				UDELAY(15000); /* wait 15 milli-seconds */
3655 			}
3656 		}
3657 		break;
3658 	}
3659 }
3660 /*
3661 **********************************************************************
3662 **********************************************************************
3663 */
3664 static void arcmsr_clear_doorbell_queue_buffer( struct AdapterControlBlock *acb)
3665 {
3666 	u_int32_t outbound_doorbell;
3667 
3668 	switch (acb->adapter_type) {
3669 	case ACB_ADAPTER_TYPE_A: {
3670 			/* empty doorbell Qbuffer if door bell ringed */
3671 			outbound_doorbell = CHIP_REG_READ32(HBA_MessageUnit, 0, outbound_doorbell);
3672 			CHIP_REG_WRITE32(HBA_MessageUnit, 0, outbound_doorbell, outbound_doorbell);	/*clear doorbell interrupt */
3673 			CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_doorbell, ARCMSR_INBOUND_DRIVER_DATA_READ_OK);
3674 
3675 		}
3676 		break;
3677 	case ACB_ADAPTER_TYPE_B: {
3678 			CHIP_REG_WRITE32(HBB_DOORBELL, 0, iop2drv_doorbell, ARCMSR_MESSAGE_INT_CLEAR_PATTERN);/*clear interrupt and message state*/
3679 			CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_DRV2IOP_DATA_READ_OK);
3680 			/* let IOP know data has been read */
3681 		}
3682 		break;
3683 	case ACB_ADAPTER_TYPE_C: {
3684 			/* empty doorbell Qbuffer if door bell ringed */
3685 			outbound_doorbell = CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell);
3686 			CHIP_REG_WRITE32(HBC_MessageUnit, 0, outbound_doorbell_clear, outbound_doorbell);	/*clear doorbell interrupt */
3687 			CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell, ARCMSR_HBCMU_DRV2IOP_DATA_READ_OK);
3688 			CHIP_REG_READ32(HBC_MessageUnit, 0, outbound_doorbell_clear); /* Dummy read to force pci flush */
3689 			CHIP_REG_READ32(HBC_MessageUnit, 0, inbound_doorbell); /* Dummy read to force pci flush */
3690 		}
3691 		break;
3692 	case ACB_ADAPTER_TYPE_D: {
3693 			/* empty doorbell Qbuffer if door bell ringed */
3694 			outbound_doorbell = CHIP_REG_READ32(HBD_MessageUnit, 0, outbound_doorbell);
3695 			CHIP_REG_WRITE32(HBD_MessageUnit, 0, outbound_doorbell, outbound_doorbell);	/*clear doorbell interrupt */
3696 			CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_doorbell, ARCMSR_HBDMU_DRV2IOP_DATA_OUT_READ);
3697 
3698 		}
3699 		break;
3700 	}
3701 }
3702 /*
3703 ************************************************************************
3704 ************************************************************************
3705 */
3706 static u_int32_t arcmsr_iop_confirm(struct AdapterControlBlock *acb)
3707 {
3708 	unsigned long srb_phyaddr;
3709 	u_int32_t srb_phyaddr_hi32;
3710 	u_int32_t srb_phyaddr_lo32;
3711 
3712 	/*
3713 	********************************************************************
3714 	** here we need to tell iop 331 our freesrb.HighPart
3715 	** if freesrb.HighPart is not zero
3716 	********************************************************************
3717 	*/
3718 	srb_phyaddr = (unsigned long) acb->srb_phyaddr.phyaddr;
3719 	srb_phyaddr_hi32 = acb->srb_phyaddr.B.phyadd_high;
3720 	srb_phyaddr_lo32 = acb->srb_phyaddr.B.phyadd_low;
3721 	switch (acb->adapter_type) {
3722 	case ACB_ADAPTER_TYPE_A: {
3723 			if(srb_phyaddr_hi32 != 0) {
3724 				CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG);
3725 				CHIP_REG_WRITE32(HBA_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
3726 				CHIP_REG_WRITE32(HBA_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
3727 				if(!arcmsr_hba_wait_msgint_ready(acb)) {
3728 					printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
3729 					return FALSE;
3730 				}
3731 			}
3732 		}
3733 		break;
3734 		/*
3735 		***********************************************************************
3736 		**    if adapter type B, set window of "post command Q"
3737 		***********************************************************************
3738 		*/
3739 	case ACB_ADAPTER_TYPE_B: {
3740 			u_int32_t post_queue_phyaddr;
3741 			struct HBB_MessageUnit *phbbmu;
3742 
3743 			phbbmu = (struct HBB_MessageUnit *)acb->pmu;
3744 			phbbmu->postq_index = 0;
3745 			phbbmu->doneq_index = 0;
3746 			CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_SET_POST_WINDOW);
3747 			if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3748 				printf( "arcmsr%d: 'set window of post command Q' timeout\n", acb->pci_unit);
3749 				return FALSE;
3750 			}
3751 			post_queue_phyaddr = srb_phyaddr + ARCMSR_SRBS_POOL_SIZE
3752 								+ offsetof(struct HBB_MessageUnit, post_qbuffer);
3753 			CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */
3754 			CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[1], srb_phyaddr_hi32); /* normal should be zero */
3755 			CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ size (256+8)*4 */
3756 			CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[3], post_queue_phyaddr+1056); /* doneQ size (256+8)*4 */
3757 			CHIP_REG_WRITE32(HBB_RWBUFFER, 1, msgcode_rwbuffer[4], 1056); /* srb maxQ size must be --> [(256+8)*4] */
3758 			CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_SET_CONFIG);
3759 			if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3760 				printf( "arcmsr%d: 'set command Q window' timeout \n", acb->pci_unit);
3761 				return FALSE;
3762 			}
3763 			CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell, ARCMSR_MESSAGE_START_DRIVER_MODE);
3764 			if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3765 				printf( "arcmsr%d: 'start diver mode' timeout \n", acb->pci_unit);
3766 				return FALSE;
3767 			}
3768 		}
3769 		break;
3770 	case ACB_ADAPTER_TYPE_C: {
3771 			if(srb_phyaddr_hi32 != 0) {
3772 				CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG);
3773 				CHIP_REG_WRITE32(HBC_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
3774 				CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
3775 				CHIP_REG_WRITE32(HBC_MessageUnit, 0, inbound_doorbell,ARCMSR_HBCMU_DRV2IOP_MESSAGE_CMD_DONE);
3776 				if(!arcmsr_hbc_wait_msgint_ready(acb)) {
3777 					printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
3778 					return FALSE;
3779 				}
3780 			}
3781 		}
3782 		break;
3783 	case ACB_ADAPTER_TYPE_D: {
3784 			u_int32_t post_queue_phyaddr, done_queue_phyaddr;
3785 			struct HBD_MessageUnit0 *phbdmu;
3786 
3787 			phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
3788 			phbdmu->postq_index = 0;
3789 			phbdmu->doneq_index = 0x40FF;
3790 			post_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE
3791 								+ offsetof(struct HBD_MessageUnit0, post_qbuffer);
3792 			done_queue_phyaddr = srb_phyaddr_lo32 + ARCMSR_SRBS_POOL_SIZE
3793 								+ offsetof(struct HBD_MessageUnit0, done_qbuffer);
3794 			CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[0], ARCMSR_SIGNATURE_SET_CONFIG); /* driver "set config" signature */
3795 			CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[1], srb_phyaddr_hi32);
3796 			CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[2], post_queue_phyaddr); /* postQ base */
3797 			CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[3], done_queue_phyaddr); /* doneQ base */
3798 			CHIP_REG_WRITE32(HBD_MessageUnit, 0, msgcode_rwbuffer[4], 0x100);
3799 			CHIP_REG_WRITE32(HBD_MessageUnit, 0, inbound_msgaddr0, ARCMSR_INBOUND_MESG0_SET_CONFIG);
3800 			if(!arcmsr_hbd_wait_msgint_ready(acb)) {
3801 				printf( "arcmsr%d: 'set srb high part physical address' timeout \n", acb->pci_unit);
3802 				return FALSE;
3803 			}
3804 		}
3805 		break;
3806 	}
3807 	return (TRUE);
3808 }
3809 /*
3810 ************************************************************************
3811 ************************************************************************
3812 */
3813 static void arcmsr_enable_eoi_mode(struct AdapterControlBlock *acb)
3814 {
3815 	switch (acb->adapter_type)
3816 	{
3817 	case ACB_ADAPTER_TYPE_A:
3818 	case ACB_ADAPTER_TYPE_C:
3819 	case ACB_ADAPTER_TYPE_D:
3820 		break;
3821 	case ACB_ADAPTER_TYPE_B: {
3822 			CHIP_REG_WRITE32(HBB_DOORBELL, 0, drv2iop_doorbell,ARCMSR_MESSAGE_ACTIVE_EOI_MODE);
3823 			if(!arcmsr_hbb_wait_msgint_ready(acb)) {
3824 				printf( "arcmsr%d: 'iop enable eoi mode' timeout \n", acb->pci_unit);
3825 				return;
3826 			}
3827 		}
3828 		break;
3829 	}
3830 }
3831 /*
3832 **********************************************************************
3833 **********************************************************************
3834 */
3835 static void arcmsr_iop_init(struct AdapterControlBlock *acb)
3836 {
3837 	u_int32_t intmask_org;
3838 
3839 	/* disable all outbound interrupt */
3840 	intmask_org = arcmsr_disable_allintr(acb);
3841 	arcmsr_wait_firmware_ready(acb);
3842 	arcmsr_iop_confirm(acb);
3843 	arcmsr_get_firmware_spec(acb);
3844 	/*start background rebuild*/
3845 	arcmsr_start_adapter_bgrb(acb);
3846 	/* empty doorbell Qbuffer if door bell ringed */
3847 	arcmsr_clear_doorbell_queue_buffer(acb);
3848 	arcmsr_enable_eoi_mode(acb);
3849 	/* enable outbound Post Queue, outbound doorbell Interrupt */
3850 	arcmsr_enable_allintr(acb, intmask_org);
3851 	acb->acb_flags |= ACB_F_IOP_INITED;
3852 }
3853 /*
3854 **********************************************************************
3855 **********************************************************************
3856 */
3857 static void arcmsr_map_free_srb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
3858 {
3859 	struct AdapterControlBlock *acb = arg;
3860 	struct CommandControlBlock *srb_tmp;
3861 	u_int32_t i;
3862 	unsigned long srb_phyaddr = (unsigned long)segs->ds_addr;
3863 
3864 	acb->srb_phyaddr.phyaddr = srb_phyaddr;
3865 	srb_tmp = (struct CommandControlBlock *)acb->uncacheptr;
3866 	for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
3867 		if(bus_dmamap_create(acb->dm_segs_dmat,
3868 			 /*flags*/0, &srb_tmp->dm_segs_dmamap) != 0) {
3869 			acb->acb_flags |= ACB_F_MAPFREESRB_FAILD;
3870 			printf("arcmsr%d:"
3871 			" srb dmamap bus_dmamap_create error\n", acb->pci_unit);
3872 			return;
3873 		}
3874 		if((acb->adapter_type == ACB_ADAPTER_TYPE_C) || (acb->adapter_type == ACB_ADAPTER_TYPE_D))
3875 		{
3876 			srb_tmp->cdb_phyaddr_low = srb_phyaddr;
3877 			srb_tmp->cdb_phyaddr_high = (u_int32_t)((srb_phyaddr >> 16) >> 16);
3878 		}
3879 		else
3880 			srb_tmp->cdb_phyaddr_low = srb_phyaddr >> 5;
3881 		srb_tmp->acb = acb;
3882 		acb->srbworkingQ[i] = acb->psrb_pool[i] = srb_tmp;
3883 		srb_phyaddr = srb_phyaddr + SRB_SIZE;
3884 		srb_tmp = (struct CommandControlBlock *)((unsigned long)srb_tmp + SRB_SIZE);
3885 	}
3886 	acb->vir2phy_offset = (unsigned long)srb_tmp - (unsigned long)srb_phyaddr;
3887 }
3888 /*
3889 ************************************************************************
3890 ************************************************************************
3891 */
3892 static void arcmsr_free_resource(struct AdapterControlBlock *acb)
3893 {
3894 	/* remove the control device */
3895 	if(acb->ioctl_dev != NULL) {
3896 		destroy_dev(acb->ioctl_dev);
3897 	}
3898 	bus_dmamap_unload(acb->srb_dmat, acb->srb_dmamap);
3899 	bus_dmamap_destroy(acb->srb_dmat, acb->srb_dmamap);
3900 	bus_dma_tag_destroy(acb->srb_dmat);
3901 	bus_dma_tag_destroy(acb->dm_segs_dmat);
3902 	bus_dma_tag_destroy(acb->parent_dmat);
3903 }
3904 /*
3905 ************************************************************************
3906 ************************************************************************
3907 */
3908 static void arcmsr_mutex_init(struct AdapterControlBlock *acb)
3909 {
3910 	ARCMSR_LOCK_INIT(&acb->isr_lock, "arcmsr isr lock");
3911 	ARCMSR_LOCK_INIT(&acb->srb_lock, "arcmsr srb lock");
3912 	ARCMSR_LOCK_INIT(&acb->postDone_lock, "arcmsr postQ lock");
3913 	ARCMSR_LOCK_INIT(&acb->qbuffer_lock, "arcmsr RW buffer lock");
3914 }
3915 /*
3916 ************************************************************************
3917 ************************************************************************
3918 */
3919 static void arcmsr_mutex_destroy(struct AdapterControlBlock *acb)
3920 {
3921 	ARCMSR_LOCK_DESTROY(&acb->qbuffer_lock);
3922 	ARCMSR_LOCK_DESTROY(&acb->postDone_lock);
3923 	ARCMSR_LOCK_DESTROY(&acb->srb_lock);
3924 	ARCMSR_LOCK_DESTROY(&acb->isr_lock);
3925 }
3926 /*
3927 ************************************************************************
3928 ************************************************************************
3929 */
3930 static u_int32_t arcmsr_initialize(device_t dev)
3931 {
3932 	struct AdapterControlBlock *acb = device_get_softc(dev);
3933 	u_int16_t pci_command;
3934 	int i, j,max_coherent_size;
3935 	u_int32_t vendor_dev_id;
3936 
3937 	vendor_dev_id = pci_get_devid(dev);
3938 	acb->vendor_device_id = vendor_dev_id;
3939 	switch (vendor_dev_id) {
3940 	case PCIDevVenIDARC1880:
3941 	case PCIDevVenIDARC1882:
3942 	case PCIDevVenIDARC1213:
3943 	case PCIDevVenIDARC1223: {
3944 			acb->adapter_type = ACB_ADAPTER_TYPE_C;
3945 			acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
3946 			max_coherent_size = ARCMSR_SRBS_POOL_SIZE;
3947 		}
3948 		break;
3949 	case PCIDevVenIDARC1214: {
3950 			acb->adapter_type = ACB_ADAPTER_TYPE_D;
3951 			acb->adapter_bus_speed = ACB_BUS_SPEED_6G;
3952 			max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBD_MessageUnit0));
3953 		}
3954 		break;
3955 	case PCIDevVenIDARC1200:
3956 	case PCIDevVenIDARC1201: {
3957 			acb->adapter_type = ACB_ADAPTER_TYPE_B;
3958 			acb->adapter_bus_speed = ACB_BUS_SPEED_3G;
3959 			max_coherent_size = ARCMSR_SRBS_POOL_SIZE + (sizeof(struct HBB_MessageUnit));
3960 		}
3961 		break;
3962 	case PCIDevVenIDARC1110:
3963 	case PCIDevVenIDARC1120:
3964 	case PCIDevVenIDARC1130:
3965 	case PCIDevVenIDARC1160:
3966 	case PCIDevVenIDARC1170:
3967 	case PCIDevVenIDARC1210:
3968 	case PCIDevVenIDARC1220:
3969 	case PCIDevVenIDARC1230:
3970 	case PCIDevVenIDARC1231:
3971 	case PCIDevVenIDARC1260:
3972 	case PCIDevVenIDARC1261:
3973 	case PCIDevVenIDARC1270:
3974 	case PCIDevVenIDARC1280:
3975 	case PCIDevVenIDARC1212:
3976 	case PCIDevVenIDARC1222:
3977 	case PCIDevVenIDARC1380:
3978 	case PCIDevVenIDARC1381:
3979 	case PCIDevVenIDARC1680:
3980 	case PCIDevVenIDARC1681: {
3981 			acb->adapter_type = ACB_ADAPTER_TYPE_A;
3982 			acb->adapter_bus_speed = ACB_BUS_SPEED_3G;
3983 			max_coherent_size = ARCMSR_SRBS_POOL_SIZE;
3984 		}
3985 		break;
3986 	default: {
3987 			printf("arcmsr%d:"
3988 			" unknown RAID adapter type \n", device_get_unit(dev));
3989 			return ENOMEM;
3990 		}
3991 	}
3992 #if __FreeBSD_version >= 700000
3993 	if(bus_dma_tag_create(  /*PCI parent*/		bus_get_dma_tag(dev),
3994 #else
3995 	if(bus_dma_tag_create(  /*PCI parent*/		NULL,
3996 #endif
3997 							/*alignemnt*/	1,
3998 							/*boundary*/	0,
3999 							/*lowaddr*/		BUS_SPACE_MAXADDR,
4000 							/*highaddr*/	BUS_SPACE_MAXADDR,
4001 							/*filter*/		NULL,
4002 							/*filterarg*/	NULL,
4003 							/*maxsize*/		BUS_SPACE_MAXSIZE_32BIT,
4004 							/*nsegments*/	BUS_SPACE_UNRESTRICTED,
4005 							/*maxsegsz*/	BUS_SPACE_MAXSIZE_32BIT,
4006 							/*flags*/		0,
4007 #if __FreeBSD_version >= 501102
4008 							/*lockfunc*/	NULL,
4009 							/*lockarg*/		NULL,
4010 #endif
4011 						&acb->parent_dmat) != 0)
4012 	{
4013 		printf("arcmsr%d: parent_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
4014 		return ENOMEM;
4015 	}
4016 
4017 	/* Create a single tag describing a region large enough to hold all of the s/g lists we will need. */
4018 	if(bus_dma_tag_create(  /*parent_dmat*/	acb->parent_dmat,
4019 							/*alignment*/	1,
4020 							/*boundary*/	0,
4021 #ifdef PAE
4022 							/*lowaddr*/		BUS_SPACE_MAXADDR_32BIT,
4023 #else
4024 							/*lowaddr*/		BUS_SPACE_MAXADDR,
4025 #endif
4026 							/*highaddr*/	BUS_SPACE_MAXADDR,
4027 							/*filter*/		NULL,
4028 							/*filterarg*/	NULL,
4029 							/*maxsize*/		ARCMSR_MAX_SG_ENTRIES * PAGE_SIZE * ARCMSR_MAX_FREESRB_NUM,
4030 							/*nsegments*/	ARCMSR_MAX_SG_ENTRIES,
4031 							/*maxsegsz*/	BUS_SPACE_MAXSIZE_32BIT,
4032 							/*flags*/		0,
4033 #if __FreeBSD_version >= 501102
4034 							/*lockfunc*/	busdma_lock_mutex,
4035 							/*lockarg*/		&acb->isr_lock,
4036 #endif
4037 						&acb->dm_segs_dmat) != 0)
4038 	{
4039 		bus_dma_tag_destroy(acb->parent_dmat);
4040 		printf("arcmsr%d: dm_segs_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
4041 		return ENOMEM;
4042 	}
4043 
4044 	/* DMA tag for our srb structures.... Allocate the freesrb memory */
4045 	if(bus_dma_tag_create(  /*parent_dmat*/	acb->parent_dmat,
4046 							/*alignment*/	0x20,
4047 							/*boundary*/	0,
4048 							/*lowaddr*/		BUS_SPACE_MAXADDR_32BIT,
4049 							/*highaddr*/	BUS_SPACE_MAXADDR,
4050 							/*filter*/		NULL,
4051 							/*filterarg*/	NULL,
4052 							/*maxsize*/		max_coherent_size,
4053 							/*nsegments*/	1,
4054 							/*maxsegsz*/	BUS_SPACE_MAXSIZE_32BIT,
4055 							/*flags*/		0,
4056 #if __FreeBSD_version >= 501102
4057 							/*lockfunc*/	NULL,
4058 							/*lockarg*/		NULL,
4059 #endif
4060 						&acb->srb_dmat) != 0)
4061 	{
4062 		bus_dma_tag_destroy(acb->dm_segs_dmat);
4063 		bus_dma_tag_destroy(acb->parent_dmat);
4064 		printf("arcmsr%d: srb_dmat bus_dma_tag_create failure!\n", device_get_unit(dev));
4065 		return ENXIO;
4066 	}
4067 	/* Allocation for our srbs */
4068 	if(bus_dmamem_alloc(acb->srb_dmat, (void **)&acb->uncacheptr, BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, &acb->srb_dmamap) != 0) {
4069 		bus_dma_tag_destroy(acb->srb_dmat);
4070 		bus_dma_tag_destroy(acb->dm_segs_dmat);
4071 		bus_dma_tag_destroy(acb->parent_dmat);
4072 		printf("arcmsr%d: srb_dmat bus_dmamem_alloc failure!\n", device_get_unit(dev));
4073 		return ENXIO;
4074 	}
4075 	/* And permanently map them */
4076 	if(bus_dmamap_load(acb->srb_dmat, acb->srb_dmamap, acb->uncacheptr, max_coherent_size, arcmsr_map_free_srb, acb, /*flags*/0)) {
4077 		bus_dma_tag_destroy(acb->srb_dmat);
4078 		bus_dma_tag_destroy(acb->dm_segs_dmat);
4079 		bus_dma_tag_destroy(acb->parent_dmat);
4080 		printf("arcmsr%d: srb_dmat bus_dmamap_load failure!\n", device_get_unit(dev));
4081 		return ENXIO;
4082 	}
4083 	pci_command = pci_read_config(dev, PCIR_COMMAND, 2);
4084 	pci_command |= PCIM_CMD_BUSMASTEREN;
4085 	pci_command |= PCIM_CMD_PERRESPEN;
4086 	pci_command |= PCIM_CMD_MWRICEN;
4087 	/* Enable Busmaster/Mem */
4088 	pci_command |= PCIM_CMD_MEMEN;
4089 	pci_write_config(dev, PCIR_COMMAND, pci_command, 2);
4090 	switch(acb->adapter_type) {
4091 	case ACB_ADAPTER_TYPE_A: {
4092 			u_int32_t rid0 = PCIR_BAR(0);
4093 			vm_offset_t	mem_base0;
4094 
4095 			acb->sys_res_arcmsr[0] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, 0x1000, RF_ACTIVE);
4096 			if(acb->sys_res_arcmsr[0] == NULL) {
4097 				arcmsr_free_resource(acb);
4098 				printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4099 				return ENOMEM;
4100 			}
4101 			if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4102 				arcmsr_free_resource(acb);
4103 				printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4104 				return ENXIO;
4105 			}
4106 			mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4107 			if(mem_base0 == 0) {
4108 				arcmsr_free_resource(acb);
4109 				printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4110 				return ENXIO;
4111 			}
4112 			acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4113 			acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4114 			acb->pmu = (struct MessageUnit_UNION *)mem_base0;
4115 		}
4116 		break;
4117 	case ACB_ADAPTER_TYPE_B: {
4118 			struct HBB_MessageUnit *phbbmu;
4119 			struct CommandControlBlock *freesrb;
4120 			u_int32_t rid[]={ PCIR_BAR(0), PCIR_BAR(2) };
4121 			vm_offset_t	mem_base[]={0,0};
4122 			for(i=0; i < 2; i++) {
4123 				if(i == 0) {
4124 					acb->sys_res_arcmsr[i] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid[i],
4125 											0ul, ~0ul, sizeof(struct HBB_DOORBELL), RF_ACTIVE);
4126 				} else {
4127 					acb->sys_res_arcmsr[i] = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid[i],
4128 											0ul, ~0ul, sizeof(struct HBB_RWBUFFER), RF_ACTIVE);
4129 				}
4130 				if(acb->sys_res_arcmsr[i] == NULL) {
4131 					arcmsr_free_resource(acb);
4132 					printf("arcmsr%d: bus_alloc_resource %d failure!\n", device_get_unit(dev), i);
4133 					return ENOMEM;
4134 				}
4135 				if(rman_get_start(acb->sys_res_arcmsr[i]) <= 0) {
4136 					arcmsr_free_resource(acb);
4137 					printf("arcmsr%d: rman_get_start %d failure!\n", device_get_unit(dev), i);
4138 					return ENXIO;
4139 				}
4140 				mem_base[i] = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[i]);
4141 				if(mem_base[i] == 0) {
4142 					arcmsr_free_resource(acb);
4143 					printf("arcmsr%d: rman_get_virtual %d failure!\n", device_get_unit(dev), i);
4144 					return ENXIO;
4145 				}
4146 				acb->btag[i] = rman_get_bustag(acb->sys_res_arcmsr[i]);
4147 				acb->bhandle[i] = rman_get_bushandle(acb->sys_res_arcmsr[i]);
4148 			}
4149 			freesrb = (struct CommandControlBlock *)acb->uncacheptr;
4150 			acb->pmu = (struct MessageUnit_UNION *)((unsigned long)freesrb+ARCMSR_SRBS_POOL_SIZE);
4151 			phbbmu = (struct HBB_MessageUnit *)acb->pmu;
4152 			phbbmu->hbb_doorbell = (struct HBB_DOORBELL *)mem_base[0];
4153 			phbbmu->hbb_rwbuffer = (struct HBB_RWBUFFER *)mem_base[1];
4154 		}
4155 		break;
4156 	case ACB_ADAPTER_TYPE_C: {
4157 			u_int32_t rid0 = PCIR_BAR(1);
4158 			vm_offset_t	mem_base0;
4159 
4160 			acb->sys_res_arcmsr[0] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, sizeof(struct HBC_MessageUnit), RF_ACTIVE);
4161 			if(acb->sys_res_arcmsr[0] == NULL) {
4162 				arcmsr_free_resource(acb);
4163 				printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4164 				return ENOMEM;
4165 			}
4166 			if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4167 				arcmsr_free_resource(acb);
4168 				printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4169 				return ENXIO;
4170 			}
4171 			mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4172 			if(mem_base0 == 0) {
4173 				arcmsr_free_resource(acb);
4174 				printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4175 				return ENXIO;
4176 			}
4177 			acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4178 			acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4179 			acb->pmu = (struct MessageUnit_UNION *)mem_base0;
4180 		}
4181 		break;
4182 	case ACB_ADAPTER_TYPE_D: {
4183 			struct HBD_MessageUnit0 *phbdmu;
4184 			u_int32_t rid0 = PCIR_BAR(0);
4185 			vm_offset_t	mem_base0;
4186 
4187 			acb->sys_res_arcmsr[0] = bus_alloc_resource(dev,SYS_RES_MEMORY, &rid0, 0ul, ~0ul, sizeof(struct HBD_MessageUnit), RF_ACTIVE);
4188 			if(acb->sys_res_arcmsr[0] == NULL) {
4189 				arcmsr_free_resource(acb);
4190 				printf("arcmsr%d: bus_alloc_resource failure!\n", device_get_unit(dev));
4191 				return ENOMEM;
4192 			}
4193 			if(rman_get_start(acb->sys_res_arcmsr[0]) <= 0) {
4194 				arcmsr_free_resource(acb);
4195 				printf("arcmsr%d: rman_get_start failure!\n", device_get_unit(dev));
4196 				return ENXIO;
4197 			}
4198 			mem_base0 = (vm_offset_t) rman_get_virtual(acb->sys_res_arcmsr[0]);
4199 			if(mem_base0 == 0) {
4200 				arcmsr_free_resource(acb);
4201 				printf("arcmsr%d: rman_get_virtual failure!\n", device_get_unit(dev));
4202 				return ENXIO;
4203 			}
4204 			acb->btag[0] = rman_get_bustag(acb->sys_res_arcmsr[0]);
4205 			acb->bhandle[0] = rman_get_bushandle(acb->sys_res_arcmsr[0]);
4206 			acb->pmu = (struct MessageUnit_UNION *)((unsigned long)acb->uncacheptr+ARCMSR_SRBS_POOL_SIZE);
4207 			phbdmu = (struct HBD_MessageUnit0 *)acb->pmu;
4208 			phbdmu->phbdmu = (struct HBD_MessageUnit *)mem_base0;
4209 		}
4210 		break;
4211 	}
4212 	if(acb->acb_flags & ACB_F_MAPFREESRB_FAILD) {
4213 		arcmsr_free_resource(acb);
4214 		printf("arcmsr%d: map free srb failure!\n", device_get_unit(dev));
4215 		return ENXIO;
4216 	}
4217 	acb->acb_flags  |= (ACB_F_MESSAGE_WQBUFFER_CLEARED|ACB_F_MESSAGE_RQBUFFER_CLEARED|ACB_F_MESSAGE_WQBUFFER_READ);
4218 	acb->acb_flags &= ~ACB_F_SCSISTOPADAPTER;
4219 	/*
4220 	********************************************************************
4221 	** init raid volume state
4222 	********************************************************************
4223 	*/
4224 	for(i=0; i < ARCMSR_MAX_TARGETID; i++) {
4225 		for(j=0; j < ARCMSR_MAX_TARGETLUN; j++) {
4226 			acb->devstate[i][j] = ARECA_RAID_GONE;
4227 		}
4228 	}
4229 	arcmsr_iop_init(acb);
4230 	return(0);
4231 }
4232 /*
4233 ************************************************************************
4234 ************************************************************************
4235 */
4236 static int arcmsr_attach(device_t dev)
4237 {
4238 	struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
4239 	u_int32_t unit=device_get_unit(dev);
4240 	struct ccb_setasync csa;
4241 	struct cam_devq	*devq;	/* Device Queue to use for this SIM */
4242 	struct resource	*irqres;
4243 	int	rid;
4244 
4245 	if(acb == NULL) {
4246 		printf("arcmsr%d: cannot allocate softc\n", unit);
4247 		return (ENOMEM);
4248 	}
4249 	arcmsr_mutex_init(acb);
4250 	if(arcmsr_initialize(dev)) {
4251 		printf("arcmsr%d: initialize failure!\n", unit);
4252 		arcmsr_mutex_destroy(acb);
4253 		return ENXIO;
4254 	}
4255 	/* After setting up the adapter, map our interrupt */
4256 	rid = 0;
4257 	irqres = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0ul, ~0ul, 1, RF_SHAREABLE | RF_ACTIVE);
4258 	if(irqres == NULL ||
4259 #if __FreeBSD_version >= 700025
4260 		bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, NULL, arcmsr_intr_handler, acb, &acb->ih)) {
4261 #else
4262 		bus_setup_intr(dev, irqres, INTR_TYPE_CAM|INTR_ENTROPY|INTR_MPSAFE, arcmsr_intr_handler, acb, &acb->ih)) {
4263 #endif
4264 		arcmsr_free_resource(acb);
4265 		arcmsr_mutex_destroy(acb);
4266 		printf("arcmsr%d: unable to register interrupt handler!\n", unit);
4267 		return ENXIO;
4268 	}
4269 	acb->irqres = irqres;
4270 	acb->pci_dev = dev;
4271 	acb->pci_unit = unit;
4272 	/*
4273 	 * Now let the CAM generic SCSI layer find the SCSI devices on
4274 	 * the bus *  start queue to reset to the idle loop. *
4275 	 * Create device queue of SIM(s) *  (MAX_START_JOB - 1) :
4276 	 * max_sim_transactions
4277 	*/
4278 	devq = cam_simq_alloc(ARCMSR_MAX_START_JOB);
4279 	if(devq == NULL) {
4280 	    arcmsr_free_resource(acb);
4281 		bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
4282 		arcmsr_mutex_destroy(acb);
4283 		printf("arcmsr%d: cam_simq_alloc failure!\n", unit);
4284 		return ENXIO;
4285 	}
4286 #if __FreeBSD_version >= 700025
4287 	acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, &acb->isr_lock, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq);
4288 #else
4289 	acb->psim = cam_sim_alloc(arcmsr_action, arcmsr_poll, "arcmsr", acb, unit, 1, ARCMSR_MAX_OUTSTANDING_CMD, devq);
4290 #endif
4291 	if(acb->psim == NULL) {
4292 		arcmsr_free_resource(acb);
4293 		bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
4294 		cam_simq_free(devq);
4295 		arcmsr_mutex_destroy(acb);
4296 		printf("arcmsr%d: cam_sim_alloc failure!\n", unit);
4297 		return ENXIO;
4298 	}
4299 	ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
4300 #if __FreeBSD_version >= 700044
4301 	if(xpt_bus_register(acb->psim, dev, 0) != CAM_SUCCESS) {
4302 #else
4303 	if(xpt_bus_register(acb->psim, 0) != CAM_SUCCESS) {
4304 #endif
4305 		arcmsr_free_resource(acb);
4306 		bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
4307 		cam_sim_free(acb->psim, /*free_devq*/TRUE);
4308 		arcmsr_mutex_destroy(acb);
4309 		printf("arcmsr%d: xpt_bus_register failure!\n", unit);
4310 		return ENXIO;
4311 	}
4312 	if(xpt_create_path(&acb->ppath, /* periph */ NULL, cam_sim_path(acb->psim), CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
4313 		arcmsr_free_resource(acb);
4314 		bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
4315 		xpt_bus_deregister(cam_sim_path(acb->psim));
4316 		cam_sim_free(acb->psim, /* free_simq */ TRUE);
4317 		arcmsr_mutex_destroy(acb);
4318 		printf("arcmsr%d: xpt_create_path failure!\n", unit);
4319 		return ENXIO;
4320 	}
4321 	/*
4322 	****************************************************
4323 	*/
4324 	xpt_setup_ccb(&csa.ccb_h, acb->ppath, /*priority*/5);
4325 	csa.ccb_h.func_code = XPT_SASYNC_CB;
4326 	csa.event_enable = AC_FOUND_DEVICE|AC_LOST_DEVICE;
4327 	csa.callback = arcmsr_async;
4328 	csa.callback_arg = acb->psim;
4329 	xpt_action((union ccb *)&csa);
4330 	ARCMSR_LOCK_RELEASE(&acb->isr_lock);
4331 	/* Create the control device.  */
4332 	acb->ioctl_dev = make_dev(&arcmsr_cdevsw, unit, UID_ROOT, GID_WHEEL /* GID_OPERATOR */, S_IRUSR | S_IWUSR, "arcmsr%d", unit);
4333 
4334 #if __FreeBSD_version < 503000
4335 	acb->ioctl_dev->si_drv1 = acb;
4336 #endif
4337 #if __FreeBSD_version > 500005
4338 	(void)make_dev_alias(acb->ioctl_dev, "arc%d", unit);
4339 #endif
4340 	arcmsr_callout_init(&acb->devmap_callout);
4341 	callout_reset(&acb->devmap_callout, 60 * hz, arcmsr_polling_devmap, acb);
4342 	return (0);
4343 }
4344 
4345 /*
4346 ************************************************************************
4347 ************************************************************************
4348 */
4349 static int arcmsr_probe(device_t dev)
4350 {
4351 	u_int32_t id;
4352 	static char buf[256];
4353 	char x_type[]={"X-TYPE"};
4354 	char *type;
4355 	int raid6 = 1;
4356 
4357 	if (pci_get_vendor(dev) != PCI_VENDOR_ID_ARECA) {
4358 		return (ENXIO);
4359 	}
4360 	switch(id = pci_get_devid(dev)) {
4361 	case PCIDevVenIDARC1110:
4362 	case PCIDevVenIDARC1200:
4363 	case PCIDevVenIDARC1201:
4364 	case PCIDevVenIDARC1210:
4365 		raid6 = 0;
4366 		/*FALLTHRU*/
4367 	case PCIDevVenIDARC1120:
4368 	case PCIDevVenIDARC1130:
4369 	case PCIDevVenIDARC1160:
4370 	case PCIDevVenIDARC1170:
4371 	case PCIDevVenIDARC1220:
4372 	case PCIDevVenIDARC1230:
4373 	case PCIDevVenIDARC1231:
4374 	case PCIDevVenIDARC1260:
4375 	case PCIDevVenIDARC1261:
4376 	case PCIDevVenIDARC1270:
4377 	case PCIDevVenIDARC1280:
4378 		type = "SATA 3G";
4379 		break;
4380 	case PCIDevVenIDARC1212:
4381 	case PCIDevVenIDARC1222:
4382 	case PCIDevVenIDARC1380:
4383 	case PCIDevVenIDARC1381:
4384 	case PCIDevVenIDARC1680:
4385 	case PCIDevVenIDARC1681:
4386 		type = "SAS 3G";
4387 		break;
4388 	case PCIDevVenIDARC1880:
4389 	case PCIDevVenIDARC1882:
4390 	case PCIDevVenIDARC1213:
4391 	case PCIDevVenIDARC1223:
4392 		type = "SAS 6G";
4393 		break;
4394 	case PCIDevVenIDARC1214:
4395 		type = "SATA 6G";
4396 		break;
4397 	default:
4398 		type = x_type;
4399 		break;
4400 	}
4401 	if(type == x_type)
4402 		return(ENXIO);
4403 	sprintf(buf, "Areca %s Host Adapter RAID Controller %s\n", type, raid6 ? "(RAID6 capable)" : "");
4404 	device_set_desc_copy(dev, buf);
4405 	return (BUS_PROBE_DEFAULT);
4406 }
4407 /*
4408 ************************************************************************
4409 ************************************************************************
4410 */
4411 static int arcmsr_shutdown(device_t dev)
4412 {
4413 	u_int32_t  i;
4414 	u_int32_t intmask_org;
4415 	struct CommandControlBlock *srb;
4416 	struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
4417 
4418 	/* stop adapter background rebuild */
4419 	ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
4420 	/* disable all outbound interrupt */
4421 	intmask_org = arcmsr_disable_allintr(acb);
4422 	arcmsr_stop_adapter_bgrb(acb);
4423 	arcmsr_flush_adapter_cache(acb);
4424 	/* abort all outstanding command */
4425 	acb->acb_flags |= ACB_F_SCSISTOPADAPTER;
4426 	acb->acb_flags &= ~ACB_F_IOP_INITED;
4427 	if(acb->srboutstandingcount != 0) {
4428 		/*clear and abort all outbound posted Q*/
4429 		arcmsr_done4abort_postqueue(acb);
4430 		/* talk to iop 331 outstanding command aborted*/
4431 		arcmsr_abort_allcmd(acb);
4432 		for(i=0; i < ARCMSR_MAX_FREESRB_NUM; i++) {
4433 			srb = acb->psrb_pool[i];
4434 			if(srb->srb_state == ARCMSR_SRB_START) {
4435 				srb->srb_state = ARCMSR_SRB_ABORTED;
4436 				srb->pccb->ccb_h.status |= CAM_REQ_ABORTED;
4437 				arcmsr_srb_complete(srb, 1);
4438 			}
4439 		}
4440 	}
4441 	acb->srboutstandingcount = 0;
4442 	acb->workingsrb_doneindex = 0;
4443 	acb->workingsrb_startindex = 0;
4444 	acb->pktRequestCount = 0;
4445 	acb->pktReturnCount = 0;
4446 	ARCMSR_LOCK_RELEASE(&acb->isr_lock);
4447 	return (0);
4448 }
4449 /*
4450 ************************************************************************
4451 ************************************************************************
4452 */
4453 static int arcmsr_detach(device_t dev)
4454 {
4455 	struct AdapterControlBlock *acb=(struct AdapterControlBlock *)device_get_softc(dev);
4456 	int i;
4457 
4458 	callout_stop(&acb->devmap_callout);
4459 	bus_teardown_intr(dev, acb->irqres, acb->ih);
4460 	arcmsr_shutdown(dev);
4461 	arcmsr_free_resource(acb);
4462 	for(i=0; (acb->sys_res_arcmsr[i]!=NULL) && (i<2); i++) {
4463 		bus_release_resource(dev, SYS_RES_MEMORY, PCIR_BAR(i), acb->sys_res_arcmsr[i]);
4464 	}
4465 	bus_release_resource(dev, SYS_RES_IRQ, 0, acb->irqres);
4466 	ARCMSR_LOCK_ACQUIRE(&acb->isr_lock);
4467 	xpt_async(AC_LOST_DEVICE, acb->ppath, NULL);
4468 	xpt_free_path(acb->ppath);
4469 	xpt_bus_deregister(cam_sim_path(acb->psim));
4470 	cam_sim_free(acb->psim, TRUE);
4471 	ARCMSR_LOCK_RELEASE(&acb->isr_lock);
4472 	arcmsr_mutex_destroy(acb);
4473 	return (0);
4474 }
4475 
4476 #ifdef ARCMSR_DEBUG1
4477 static void arcmsr_dump_data(struct AdapterControlBlock *acb)
4478 {
4479 	if((acb->pktRequestCount - acb->pktReturnCount) == 0)
4480 		return;
4481 	printf("Command Request Count   =0x%x\n",acb->pktRequestCount);
4482 	printf("Command Return Count    =0x%x\n",acb->pktReturnCount);
4483 	printf("Command (Req-Rtn) Count =0x%x\n",(acb->pktRequestCount - acb->pktReturnCount));
4484 	printf("Queued Command Count    =0x%x\n",acb->srboutstandingcount);
4485 }
4486 #endif
4487 
4488