1*493d26c5SEd Maste /* 2*493d26c5SEd Maste * aQuantia Corporation Network Driver 3*493d26c5SEd Maste * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved 4*493d26c5SEd Maste * 5*493d26c5SEd Maste * Redistribution and use in source and binary forms, with or without 6*493d26c5SEd Maste * modification, are permitted provided that the following conditions 7*493d26c5SEd Maste * are met: 8*493d26c5SEd Maste * 9*493d26c5SEd Maste * (1) Redistributions of source code must retain the above 10*493d26c5SEd Maste * copyright notice, this list of conditions and the following 11*493d26c5SEd Maste * disclaimer. 12*493d26c5SEd Maste * 13*493d26c5SEd Maste * (2) Redistributions in binary form must reproduce the above 14*493d26c5SEd Maste * copyright notice, this list of conditions and the following 15*493d26c5SEd Maste * disclaimer in the documentation and/or other materials provided 16*493d26c5SEd Maste * with the distribution. 17*493d26c5SEd Maste * 18*493d26c5SEd Maste * (3)The name of the author may not be used to endorse or promote 19*493d26c5SEd Maste * products derived from this software without specific prior 20*493d26c5SEd Maste * written permission. 21*493d26c5SEd Maste * 22*493d26c5SEd Maste * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS 23*493d26c5SEd Maste * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24*493d26c5SEd Maste * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25*493d26c5SEd Maste * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 26*493d26c5SEd Maste * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27*493d26c5SEd Maste * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 28*493d26c5SEd Maste * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29*493d26c5SEd Maste * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30*493d26c5SEd Maste * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 31*493d26c5SEd Maste * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32*493d26c5SEd Maste * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33*493d26c5SEd Maste */ 34*493d26c5SEd Maste 35*493d26c5SEd Maste #ifndef _AQ_RING_H_ 36*493d26c5SEd Maste #define _AQ_RING_H_ 37*493d26c5SEd Maste 38*493d26c5SEd Maste #include "aq_hw.h" 39*493d26c5SEd Maste 40*493d26c5SEd Maste #define REFILL_THRESHOLD 128 41*493d26c5SEd Maste 42*493d26c5SEd Maste 43*493d26c5SEd Maste typedef volatile struct { 44*493d26c5SEd Maste u32 rss_type:4; 45*493d26c5SEd Maste u32 pkt_type:8; 46*493d26c5SEd Maste u32 rdm_err:1; 47*493d26c5SEd Maste u32 rsvd:6; 48*493d26c5SEd Maste u32 rx_cntl:2; 49*493d26c5SEd Maste u32 sph:1; 50*493d26c5SEd Maste u32 hdr_len:10; 51*493d26c5SEd Maste u32 rss_hash; 52*493d26c5SEd Maste u16 dd:1; 53*493d26c5SEd Maste u16 eop:1; 54*493d26c5SEd Maste u16 rx_stat:4; 55*493d26c5SEd Maste u16 rx_estat:6; 56*493d26c5SEd Maste u16 rsc_cnt:4; 57*493d26c5SEd Maste u16 pkt_len; 58*493d26c5SEd Maste u16 next_desp; 59*493d26c5SEd Maste u16 vlan; 60*493d26c5SEd Maste } __attribute__((__packed__)) aq_rx_wb_t; 61*493d26c5SEd Maste 62*493d26c5SEd Maste typedef volatile struct { 63*493d26c5SEd Maste union { 64*493d26c5SEd Maste /* HW RX descriptor */ 65*493d26c5SEd Maste struct __packed { 66*493d26c5SEd Maste u64 buf_addr; 67*493d26c5SEd Maste u64 hdr_addr; 68*493d26c5SEd Maste } read; 69*493d26c5SEd Maste 70*493d26c5SEd Maste /* HW RX descriptor writeback */ 71*493d26c5SEd Maste aq_rx_wb_t wb; 72*493d26c5SEd Maste }; 73*493d26c5SEd Maste } __attribute__((__packed__)) aq_rx_desc_t; 74*493d26c5SEd Maste 75*493d26c5SEd Maste /* Hardware tx descriptor */ 76*493d26c5SEd Maste typedef volatile struct { 77*493d26c5SEd Maste u64 buf_addr; 78*493d26c5SEd Maste 79*493d26c5SEd Maste union { 80*493d26c5SEd Maste struct { 81*493d26c5SEd Maste u32 type:3; 82*493d26c5SEd Maste u32 :1; 83*493d26c5SEd Maste u32 len:16; 84*493d26c5SEd Maste u32 dd:1; 85*493d26c5SEd Maste u32 eop:1; 86*493d26c5SEd Maste u32 cmd:8; 87*493d26c5SEd Maste u32 :14; 88*493d26c5SEd Maste u32 ct_idx:1; 89*493d26c5SEd Maste u32 ct_en:1; 90*493d26c5SEd Maste u32 pay_len:18; 91*493d26c5SEd Maste } __attribute__((__packed__)); 92*493d26c5SEd Maste u64 flags; 93*493d26c5SEd Maste }; 94*493d26c5SEd Maste } __attribute__((__packed__)) aq_tx_desc_t; 95*493d26c5SEd Maste 96*493d26c5SEd Maste enum aq_tx_desc_type { 97*493d26c5SEd Maste tx_desc_type_desc = 1, 98*493d26c5SEd Maste tx_desc_type_ctx = 2, 99*493d26c5SEd Maste }; 100*493d26c5SEd Maste 101*493d26c5SEd Maste enum aq_tx_desc_cmd { 102*493d26c5SEd Maste tx_desc_cmd_vlan = 1, 103*493d26c5SEd Maste tx_desc_cmd_fcs = 2, 104*493d26c5SEd Maste tx_desc_cmd_ipv4 = 4, 105*493d26c5SEd Maste tx_desc_cmd_l4cs = 8, 106*493d26c5SEd Maste tx_desc_cmd_lso = 0x10, 107*493d26c5SEd Maste tx_desc_cmd_wb = 0x20, 108*493d26c5SEd Maste }; 109*493d26c5SEd Maste 110*493d26c5SEd Maste /* Hardware tx context descriptor */ 111*493d26c5SEd Maste typedef volatile union { 112*493d26c5SEd Maste struct __packed { 113*493d26c5SEd Maste u64 flags1; 114*493d26c5SEd Maste u64 flags2; 115*493d26c5SEd Maste }; 116*493d26c5SEd Maste 117*493d26c5SEd Maste struct __packed { 118*493d26c5SEd Maste u64 :40; 119*493d26c5SEd Maste u32 tun_len:8; 120*493d26c5SEd Maste u32 out_len:16; 121*493d26c5SEd Maste u32 type:3; 122*493d26c5SEd Maste u32 idx:1; 123*493d26c5SEd Maste u32 vlan_tag:16; 124*493d26c5SEd Maste u32 cmd:4; 125*493d26c5SEd Maste u32 l2_len:7; 126*493d26c5SEd Maste u32 l3_len:9; 127*493d26c5SEd Maste u32 l4_len:8; 128*493d26c5SEd Maste u32 mss_len:16; 129*493d26c5SEd Maste }; 130*493d26c5SEd Maste } __attribute__((__packed__)) aq_txc_desc_t; 131*493d26c5SEd Maste 132*493d26c5SEd Maste struct aq_ring_stats { 133*493d26c5SEd Maste u64 rx_pkts; 134*493d26c5SEd Maste u64 rx_bytes; 135*493d26c5SEd Maste u64 jumbo_pkts; 136*493d26c5SEd Maste u64 rx_err; 137*493d26c5SEd Maste u64 irq; 138*493d26c5SEd Maste 139*493d26c5SEd Maste u64 tx_pkts; 140*493d26c5SEd Maste u64 tx_bytes; 141*493d26c5SEd Maste u64 tx_drops; 142*493d26c5SEd Maste u64 tx_queue_full; 143*493d26c5SEd Maste }; 144*493d26c5SEd Maste 145*493d26c5SEd Maste struct aq_dev; 146*493d26c5SEd Maste 147*493d26c5SEd Maste struct aq_ring { 148*493d26c5SEd Maste struct aq_dev *dev; 149*493d26c5SEd Maste int index; 150*493d26c5SEd Maste 151*493d26c5SEd Maste struct if_irq irq; 152*493d26c5SEd Maste int msix; 153*493d26c5SEd Maste /* RX */ 154*493d26c5SEd Maste qidx_t rx_size; 155*493d26c5SEd Maste int rx_max_frame_size; 156*493d26c5SEd Maste void *rx_desc_area_ptr; 157*493d26c5SEd Maste aq_rx_desc_t *rx_descs; 158*493d26c5SEd Maste uint64_t rx_descs_phys; 159*493d26c5SEd Maste 160*493d26c5SEd Maste /* TX */ 161*493d26c5SEd Maste int tx_head, tx_tail; 162*493d26c5SEd Maste qidx_t tx_size; 163*493d26c5SEd Maste void *tx_desc_area_ptr; 164*493d26c5SEd Maste aq_tx_desc_t *tx_descs; 165*493d26c5SEd Maste uint64_t tx_descs_phys; 166*493d26c5SEd Maste 167*493d26c5SEd Maste struct aq_ring_stats stats; 168*493d26c5SEd Maste }; 169*493d26c5SEd Maste 170*493d26c5SEd Maste int aq_ring_rx_init(struct aq_hw *hw, struct aq_ring *ring); 171*493d26c5SEd Maste int aq_ring_tx_init(struct aq_hw *hw, struct aq_ring *ring); 172*493d26c5SEd Maste 173*493d26c5SEd Maste int aq_ring_tx_start(struct aq_hw *hw, struct aq_ring *ring); 174*493d26c5SEd Maste int aq_ring_tx_stop(struct aq_hw *hw, struct aq_ring *ring); 175*493d26c5SEd Maste int aq_ring_rx_start(struct aq_hw *hw, struct aq_ring *ring); 176*493d26c5SEd Maste int aq_ring_rx_stop(struct aq_hw *hw, struct aq_ring *ring); 177*493d26c5SEd Maste 178*493d26c5SEd Maste int aq_ring_tx_tail_update(struct aq_hw *hw, struct aq_ring *ring, u32 tail); 179*493d26c5SEd Maste 180*493d26c5SEd Maste 181*493d26c5SEd Maste extern struct if_txrx aq_txrx; 182*493d26c5SEd Maste int aq_intr(void *arg); 183*493d26c5SEd Maste 184*493d26c5SEd Maste #endif /* _AQ_RING_H_ */ 185