1 /* 2 * aQuantia Corporation Network Driver 3 * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * (1) Redistributions of source code must retain the above 10 * copyright notice, this list of conditions and the following 11 * disclaimer. 12 * 13 * (2) Redistributions in binary form must reproduce the above 14 * copyright notice, this list of conditions and the following 15 * disclaimer in the documentation and/or other materials provided 16 * with the distribution. 17 * 18 * (3)The name of the author may not be used to endorse or promote 19 * products derived from this software without specific prior 20 * written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS 23 * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 24 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 26 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE 28 * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 30 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 31 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 32 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #ifndef _AQ_HW_H_ 36 #define _AQ_HW_H_ 37 38 #include <stdbool.h> 39 #include <sys/types.h> 40 #include <sys/cdefs.h> 41 #include <machine/cpufunc.h> 42 #include <sys/endian.h> 43 #include "aq_common.h" 44 45 #define AQ_WRITE_REG(hw, reg, value) writel(((hw)->hw_addr + (reg)), htole32(value)) 46 47 #define AQ_READ_REG(hw, reg) le32toh(readl((hw)->hw_addr + reg)) 48 49 50 #define AQ_WRITE_REG_BIT(hw, reg, msk, shift, value) do { \ 51 if (msk ^ ~0) { \ 52 u32 reg_old, reg_new = 0U; \ 53 reg_old = AQ_READ_REG(hw, reg); \ 54 reg_new = (reg_old & (~msk)) | (value << shift); \ 55 if (reg_old != reg_new) \ 56 AQ_WRITE_REG(hw, reg, reg_new); \ 57 } else { \ 58 AQ_WRITE_REG(hw, reg, value); \ 59 } } while(0) 60 61 62 #define AQ_READ_REG_BIT(a, reg, msk, shift) ( \ 63 ((AQ_READ_REG(a, reg) & msk) >> shift)) 64 65 #define AQ_HW_FLUSH() { (void)AQ_READ_REG(hw, 0x10); } 66 67 #define aq_hw_write_reg_bit AQ_WRITE_REG_BIT 68 69 #define aq_hw_write_reg AQ_WRITE_REG 70 71 /* Statistics */ 72 struct aq_hw_stats { 73 u64 crcerrs; 74 }; 75 76 struct aq_hw_stats_s { 77 u32 uprc; 78 u32 mprc; 79 u32 bprc; 80 u32 erpt; 81 u32 uptc; 82 u32 mptc; 83 u32 bptc; 84 u32 erpr; 85 u32 mbtc; 86 u32 bbtc; 87 u32 mbrc; 88 u32 bbrc; 89 u32 ubrc; 90 u32 ubtc; 91 u32 ptc; 92 u32 prc; 93 u32 dpc; 94 u32 cprc; 95 } __attribute__((__packed__)); 96 97 union ip_addr { 98 struct { 99 u8 addr[16]; 100 } v6; 101 struct { 102 u8 padding[12]; 103 u8 addr[4]; 104 } v4; 105 } __attribute__((__packed__)); 106 107 struct aq_hw_fw_mbox { 108 u32 version; 109 u32 transaction_id; 110 int error; 111 struct aq_hw_stats_s stats; 112 } __attribute__((__packed__)); 113 114 typedef struct aq_hw_fw_version { 115 union { 116 struct { 117 u16 build_number; 118 u8 minor_version; 119 u8 major_version; 120 }; 121 u32 raw; 122 }; 123 } aq_hw_fw_version; 124 125 enum aq_hw_irq_type { 126 aq_irq_invalid = 0, 127 aq_irq_legacy = 1, 128 aq_irq_msi = 2, 129 aq_irq_msix = 3, 130 }; 131 132 struct aq_hw_fc_info { 133 bool fc_rx; 134 bool fc_tx; 135 }; 136 137 struct aq_hw { 138 void *aq_dev; 139 u8 *hw_addr; 140 u32 regs_size; 141 142 u8 mac_addr[ETH_MAC_LEN]; 143 144 enum aq_hw_irq_type irq_type; 145 146 struct aq_hw_fc_info fc; 147 u16 link_rate; 148 149 u16 device_id; 150 u16 subsystem_vendor_id; 151 u16 subsystem_device_id; 152 u16 vendor_id; 153 u8 revision_id; 154 155 /* Interrupt Moderation value. */ 156 int itr; 157 158 /* Firmware-related stuff. */ 159 aq_hw_fw_version fw_version; 160 const struct aq_firmware_ops* fw_ops; 161 bool rbl_enabled; 162 bool fast_start_enabled; 163 bool flash_present; 164 u32 chip_features; 165 u64 fw_caps; 166 167 bool lro_enabled; 168 169 u32 mbox_addr; 170 struct aq_hw_fw_mbox mbox; 171 }; 172 173 #define aq_hw_s aq_hw 174 175 #define AQ_HW_MAC 0U 176 #define AQ_HW_MAC_MIN 1U 177 #define AQ_HW_MAC_MAX 33U 178 179 #define HW_ATL_B0_MIN_RXD 32U 180 #define HW_ATL_B0_MIN_TXD 32U 181 #define HW_ATL_B0_MAX_RXD 4096U /* in fact up to 8184, but closest to power of 2 */ 182 #define HW_ATL_B0_MAX_TXD 4096U /* in fact up to 8184, but closest to power of 2 */ 183 184 #define HW_ATL_B0_MTU_JUMBO 16352U 185 #define HW_ATL_B0_TSO_SIZE (160*1024) 186 #define HW_ATL_B0_RINGS_MAX 32U 187 #define HW_ATL_B0_LRO_RXD_MAX 16U 188 189 #define AQ_HW_FW_SM_RAM 0x2U 190 191 #define AQ_HW_MPI_STATE_MSK 0x00FFU 192 #define AQ_HW_MPI_STATE_SHIFT 0U 193 194 #define AQ_HW_MPI_CONTROL_ADR 0x0368U 195 #define AQ_HW_MPI_STATE_ADR 0x036CU 196 197 #define HW_ATL_RSS_INDIRECTION_TABLE_MAX 64U 198 #define HW_ATL_RSS_HASHKEY_SIZE 40U 199 200 /* PCI core control register */ 201 #define AQ_HW_PCI_REG_CONTROL_6_ADR 0x1014U 202 /* tx dma total request limit */ 203 #define AQ_HW_TX_DMA_TOTAL_REQ_LIMIT_ADR 0x00007b20U 204 205 #define AQ_HW_TXBUF_MAX 160U 206 #define AQ_HW_RXBUF_MAX 320U 207 208 #define L2_FILTER_ACTION_DISCARD (0x0) 209 #define L2_FILTER_ACTION_HOST (0x1) 210 211 #define AQ_HW_UCP_0X370_REG (0x370) 212 #define AQ_HW_CHIP_MIPS 0x00000001U 213 #define AQ_HW_CHIP_TPO2 0x00000002U 214 #define AQ_HW_CHIP_RPF2 0x00000004U 215 #define AQ_HW_CHIP_MPI_AQ 0x00000010U 216 #define AQ_HW_CHIP_REVISION_A0 0x01000000U 217 #define AQ_HW_CHIP_REVISION_B0 0x02000000U 218 #define AQ_HW_CHIP_REVISION_B1 0x04000000U 219 #define IS_CHIP_FEATURE(HW, _F_) (AQ_HW_CHIP_##_F_ & \ 220 (HW)->chip_features) 221 222 #define AQ_HW_FW_VER_EXPECTED 0x01050006U 223 224 #define AQ_RX_RSS_TYPE_NONE 0x0 225 #define AQ_RX_RSS_TYPE_IPV4 0x2 226 #define AQ_RX_RSS_TYPE_IPV6 0x3 227 #define AQ_RX_RSS_TYPE_IPV4_TCP 0x4 228 #define AQ_RX_RSS_TYPE_IPV6_TCP 0x5 229 #define AQ_RX_RSS_TYPE_IPV4_UDP 0x6 230 #define AQ_RX_RSS_TYPE_IPV6_UDP 0x7 231 232 enum hw_atl_rx_action_with_traffic { 233 HW_ATL_RX_DISCARD, 234 HW_ATL_RX_HOST, 235 HW_ATL_RX_MNGMNT, 236 HW_ATL_RX_HOST_AND_MNGMNT, 237 HW_ATL_RX_WOL 238 }; 239 240 struct aq_rx_filter_vlan { 241 u8 enable; 242 u8 location; 243 u16 vlan_id; 244 u8 queue; 245 }; 246 247 #define AQ_HW_VLAN_MAX_FILTERS 16U 248 #define AQ_HW_ETYPE_MAX_FILTERS 16U 249 250 struct aq_rx_filter_l2 { 251 u8 enable; 252 s8 queue; 253 u8 location; 254 u8 user_priority_en; 255 u8 user_priority; 256 u16 ethertype; 257 }; 258 259 enum hw_atl_rx_ctrl_registers_l2 { 260 HW_ATL_RX_ENABLE_UNICAST_MNGNT_QUEUE_L2 = BIT(19), 261 HW_ATL_RX_ENABLE_UNICAST_FLTR_L2 = BIT(31) 262 }; 263 264 struct aq_rx_filter_l3l4 { 265 u32 cmd; 266 u8 location; 267 u32 ip_dst[4]; 268 u32 ip_src[4]; 269 u16 p_dst; 270 u16 p_src; 271 bool is_ipv6; 272 }; 273 274 enum hw_atl_rx_protocol_value_l3l4 { 275 HW_ATL_RX_TCP, 276 HW_ATL_RX_UDP, 277 HW_ATL_RX_SCTP, 278 HW_ATL_RX_ICMP 279 }; 280 281 enum hw_atl_rx_ctrl_registers_l3l4 { 282 HW_ATL_RX_ENABLE_MNGMNT_QUEUE_L3L4 = BIT(22), 283 HW_ATL_RX_ENABLE_QUEUE_L3L4 = BIT(23), 284 HW_ATL_RX_ENABLE_ARP_FLTR_L3 = BIT(24), 285 HW_ATL_RX_ENABLE_CMP_PROT_L4 = BIT(25), 286 HW_ATL_RX_ENABLE_CMP_DEST_PORT_L4 = BIT(26), 287 HW_ATL_RX_ENABLE_CMP_SRC_PORT_L4 = BIT(27), 288 HW_ATL_RX_ENABLE_CMP_DEST_ADDR_L3 = BIT(28), 289 HW_ATL_RX_ENABLE_CMP_SRC_ADDR_L3 = BIT(29), 290 HW_ATL_RX_ENABLE_L3_IPv6 = BIT(30), 291 HW_ATL_RX_ENABLE_FLTR_L3L4 = BIT(31) 292 }; 293 294 #define HW_ATL_RX_BOFFSET_PROT_FL3L4 0U 295 #define HW_ATL_RX_BOFFSET_QUEUE_FL3L4 8U 296 #define HW_ATL_RX_BOFFSET_ACTION_FL3F4 16U 297 298 #define HW_ATL_RX_CNT_REG_ADDR_IPV6 4U 299 300 #define HW_ATL_GET_REG_LOCATION_FL3L4(location) \ 301 ((location) - AQ_RX_FIRST_LOC_FL3L4) 302 303 enum aq_hw_fw_mpi_state_e { 304 MPI_DEINIT = 0, 305 MPI_RESET = 1, 306 MPI_INIT = 2, 307 MPI_POWER = 4, 308 }; 309 310 int aq_hw_get_mac_permanent(struct aq_hw *hw, u8 *mac); 311 312 int aq_hw_mac_addr_set(struct aq_hw *hw, u8 *mac_addr, u8 index); 313 314 /* link speed in mbps. "0" - no link detected */ 315 int aq_hw_get_link_state(struct aq_hw *hw, u32 *link_speed, struct aq_hw_fc_info *fc_neg); 316 317 int aq_hw_set_link_speed(struct aq_hw *hw, u32 speed); 318 319 int aq_hw_fw_downld_dwords(struct aq_hw *hw, u32 a, u32 *p, u32 cnt); 320 321 int aq_hw_reset(struct aq_hw *hw); 322 323 int aq_hw_mpi_create(struct aq_hw *hw); 324 325 int aq_hw_mpi_read_stats(struct aq_hw *hw, struct aq_hw_fw_mbox *pmbox); 326 327 int aq_hw_init(struct aq_hw *hw, u8 *mac_addr, u8 adm_irq, bool msix); 328 329 int aq_hw_start(struct aq_hw *hw); 330 331 int aq_hw_interrupt_moderation_set(struct aq_hw *hw); 332 333 int aq_hw_get_fw_version(struct aq_hw *hw, u32 *fw_version); 334 335 int aq_hw_deinit(struct aq_hw *hw); 336 337 int aq_hw_ver_match(const aq_hw_fw_version* ver_expected, const aq_hw_fw_version* ver_actual); 338 339 void aq_hw_set_promisc(struct aq_hw_s *self, bool l2_promisc, bool vlan_promisc, bool mc_promisc); 340 341 int aq_hw_set_power(struct aq_hw *hw, unsigned int power_state); 342 343 int aq_hw_err_from_flags(struct aq_hw *hw); 344 345 int hw_atl_b0_hw_vlan_promisc_set(struct aq_hw_s *self, bool promisc); 346 347 int hw_atl_b0_hw_vlan_set(struct aq_hw_s *self, 348 struct aq_rx_filter_vlan *aq_vlans); 349 350 int aq_hw_rss_hash_set(struct aq_hw_s *self, u8 rss_key[HW_ATL_RSS_HASHKEY_SIZE]); 351 int aq_hw_rss_hash_get(struct aq_hw_s *self, u8 rss_key[HW_ATL_RSS_HASHKEY_SIZE]); 352 int aq_hw_rss_set(struct aq_hw_s *self, u8 rss_table[HW_ATL_RSS_INDIRECTION_TABLE_MAX]); 353 int aq_hw_udp_rss_enable(struct aq_hw_s *self, bool enable); 354 355 #endif //_AQ_HW_H_ 356 357