1*493d26c5SEd Maste /*
2*493d26c5SEd Maste * aQuantia Corporation Network Driver
3*493d26c5SEd Maste * Copyright (C) 2014-2017 aQuantia Corporation. All rights reserved
4*493d26c5SEd Maste *
5*493d26c5SEd Maste * Redistribution and use in source and binary forms, with or without
6*493d26c5SEd Maste * modification, are permitted provided that the following conditions
7*493d26c5SEd Maste * are met:
8*493d26c5SEd Maste *
9*493d26c5SEd Maste * (1) Redistributions of source code must retain the above
10*493d26c5SEd Maste * copyright notice, this list of conditions and the following
11*493d26c5SEd Maste * disclaimer.
12*493d26c5SEd Maste *
13*493d26c5SEd Maste * (2) Redistributions in binary form must reproduce the above
14*493d26c5SEd Maste * copyright notice, this list of conditions and the following
15*493d26c5SEd Maste * disclaimer in the documentation and/or other materials provided
16*493d26c5SEd Maste * with the distribution.
17*493d26c5SEd Maste *
18*493d26c5SEd Maste * (3) The name of the author may not be used to endorse or promote
19*493d26c5SEd Maste * products derived from this software without specific prior
20*493d26c5SEd Maste * written permission.
21*493d26c5SEd Maste *
22*493d26c5SEd Maste * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS
23*493d26c5SEd Maste * OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
24*493d26c5SEd Maste * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25*493d26c5SEd Maste * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
26*493d26c5SEd Maste * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27*493d26c5SEd Maste * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
28*493d26c5SEd Maste * GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
29*493d26c5SEd Maste * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
30*493d26c5SEd Maste * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
31*493d26c5SEd Maste * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
32*493d26c5SEd Maste * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
33*493d26c5SEd Maste *
34*493d26c5SEd Maste * @file aq_fw.c
35*493d26c5SEd Maste * Firmware-related functions implementation.
36*493d26c5SEd Maste * @date 2017.12.07 @author roman.agafonov@aquantia.com
37*493d26c5SEd Maste */
38*493d26c5SEd Maste
39*493d26c5SEd Maste #include <sys/cdefs.h>
40*493d26c5SEd Maste __FBSDID("$FreeBSD$");
41*493d26c5SEd Maste
42*493d26c5SEd Maste #include <errno.h>
43*493d26c5SEd Maste
44*493d26c5SEd Maste #include "aq_common.h"
45*493d26c5SEd Maste
46*493d26c5SEd Maste #include "aq_hw.h"
47*493d26c5SEd Maste #include "aq_hw_llh.h"
48*493d26c5SEd Maste #include "aq_hw_llh_internal.h"
49*493d26c5SEd Maste
50*493d26c5SEd Maste #include "aq_fw.h"
51*493d26c5SEd Maste #include "aq_common.h"
52*493d26c5SEd Maste
53*493d26c5SEd Maste #include "aq_dbg.h"
54*493d26c5SEd Maste
55*493d26c5SEd Maste
56*493d26c5SEd Maste typedef enum aq_fw_bootloader_mode
57*493d26c5SEd Maste {
58*493d26c5SEd Maste boot_mode_unknown = 0,
59*493d26c5SEd Maste boot_mode_flb,
60*493d26c5SEd Maste boot_mode_rbl_flash,
61*493d26c5SEd Maste boot_mode_rbl_host_bootload,
62*493d26c5SEd Maste } aq_fw_bootloader_mode;
63*493d26c5SEd Maste
64*493d26c5SEd Maste #define AQ_CFG_HOST_BOOT_DISABLE 0
65*493d26c5SEd Maste // Timeouts
66*493d26c5SEd Maste #define RBL_TIMEOUT_MS 10000
67*493d26c5SEd Maste #define MAC_FW_START_TIMEOUT_MS 10000
68*493d26c5SEd Maste #define FW_LOADER_START_TIMEOUT_MS 10000
69*493d26c5SEd Maste
70*493d26c5SEd Maste const u32 NO_RESET_SCRATCHPAD_ADDRESS = 0;
71*493d26c5SEd Maste const u32 NO_RESET_SCRATCHPAD_LEN_RES = 1;
72*493d26c5SEd Maste const u32 NO_RESET_SCRATCHPAD_RBL_STATUS = 2;
73*493d26c5SEd Maste const u32 NO_RESET_SCRATCHPAD_RBL_STATUS_2 = 3;
74*493d26c5SEd Maste const u32 WRITE_DATA_COMPLETE = 0x55555555;
75*493d26c5SEd Maste const u32 WRITE_DATA_CHUNK_DONE = 0xaaaaaaaa;
76*493d26c5SEd Maste const u32 WRITE_DATA_FAIL_WRONG_ADDRESS = 0x66666666;
77*493d26c5SEd Maste
78*493d26c5SEd Maste const u32 WAIT_WRITE_TIMEOUT = 1;
79*493d26c5SEd Maste const u32 WAIT_WRITE_TIMEOUT_COUNT = 1000;
80*493d26c5SEd Maste
81*493d26c5SEd Maste const u32 RBL_STATUS_SUCCESS = 0xabba;
82*493d26c5SEd Maste const u32 RBL_STATUS_FAILURE = 0xbad;
83*493d26c5SEd Maste const u32 RBL_STATUS_HOST_BOOT = 0xf1a7;
84*493d26c5SEd Maste
85*493d26c5SEd Maste const u32 SCRATCHPAD_FW_LOADER_STATUS = (0x40 / sizeof(u32));
86*493d26c5SEd Maste
87*493d26c5SEd Maste
88*493d26c5SEd Maste extern struct aq_firmware_ops aq_fw1x_ops;
89*493d26c5SEd Maste extern struct aq_firmware_ops aq_fw2x_ops;
90*493d26c5SEd Maste
91*493d26c5SEd Maste
92*493d26c5SEd Maste int mac_soft_reset_(struct aq_hw* hw, aq_fw_bootloader_mode* mode);
93*493d26c5SEd Maste int mac_soft_reset_flb_(struct aq_hw* hw);
94*493d26c5SEd Maste int mac_soft_reset_rbl_(struct aq_hw* hw, aq_fw_bootloader_mode* mode);
95*493d26c5SEd Maste int wait_init_mac_firmware_(struct aq_hw* hw);
96*493d26c5SEd Maste
97*493d26c5SEd Maste
aq_fw_reset(struct aq_hw * hw)98*493d26c5SEd Maste int aq_fw_reset(struct aq_hw* hw)
99*493d26c5SEd Maste {
100*493d26c5SEd Maste int ver = AQ_READ_REG(hw, 0x18);
101*493d26c5SEd Maste u32 bootExitCode = 0;
102*493d26c5SEd Maste int k;
103*493d26c5SEd Maste
104*493d26c5SEd Maste for (k = 0; k < 1000; ++k) {
105*493d26c5SEd Maste u32 flbStatus = reg_glb_daisy_chain_status1_get(hw);
106*493d26c5SEd Maste bootExitCode = AQ_READ_REG(hw, 0x388);
107*493d26c5SEd Maste if (flbStatus != 0x06000000 || bootExitCode != 0)
108*493d26c5SEd Maste break;
109*493d26c5SEd Maste }
110*493d26c5SEd Maste
111*493d26c5SEd Maste if (k == 1000) {
112*493d26c5SEd Maste aq_log_error("Neither RBL nor FLB started");
113*493d26c5SEd Maste return (-EBUSY);
114*493d26c5SEd Maste }
115*493d26c5SEd Maste
116*493d26c5SEd Maste hw->rbl_enabled = bootExitCode != 0;
117*493d26c5SEd Maste
118*493d26c5SEd Maste trace(dbg_init, "RBL enabled = %d", hw->rbl_enabled);
119*493d26c5SEd Maste
120*493d26c5SEd Maste /* Having FW version 0 is an indicator that cold start
121*493d26c5SEd Maste * is in progress. This means two things:
122*493d26c5SEd Maste * 1) Driver have to wait for FW/HW to finish boot (500ms giveup)
123*493d26c5SEd Maste * 2) Driver may skip reset sequence and save time.
124*493d26c5SEd Maste */
125*493d26c5SEd Maste if (hw->fast_start_enabled && !ver) {
126*493d26c5SEd Maste int err = wait_init_mac_firmware_(hw);
127*493d26c5SEd Maste /* Skip reset as it just completed */
128*493d26c5SEd Maste if (!err)
129*493d26c5SEd Maste return (0);
130*493d26c5SEd Maste }
131*493d26c5SEd Maste
132*493d26c5SEd Maste aq_fw_bootloader_mode mode = boot_mode_unknown;
133*493d26c5SEd Maste int err = mac_soft_reset_(hw, &mode);
134*493d26c5SEd Maste if (err < 0) {
135*493d26c5SEd Maste aq_log_error("MAC reset failed: %d", err);
136*493d26c5SEd Maste return (err);
137*493d26c5SEd Maste }
138*493d26c5SEd Maste
139*493d26c5SEd Maste switch (mode) {
140*493d26c5SEd Maste case boot_mode_flb:
141*493d26c5SEd Maste aq_log("FLB> F/W successfully loaded from flash.");
142*493d26c5SEd Maste hw->flash_present = true;
143*493d26c5SEd Maste return wait_init_mac_firmware_(hw);
144*493d26c5SEd Maste
145*493d26c5SEd Maste case boot_mode_rbl_flash:
146*493d26c5SEd Maste aq_log("RBL> F/W loaded from flash. Host Bootload disabled.");
147*493d26c5SEd Maste hw->flash_present = true;
148*493d26c5SEd Maste return wait_init_mac_firmware_(hw);
149*493d26c5SEd Maste
150*493d26c5SEd Maste case boot_mode_unknown:
151*493d26c5SEd Maste aq_log_error("F/W bootload error: unknown bootloader type");
152*493d26c5SEd Maste return (-ENOTSUP);
153*493d26c5SEd Maste
154*493d26c5SEd Maste case boot_mode_rbl_host_bootload:
155*493d26c5SEd Maste #if AQ_CFG_HOST_BOOT_DISABLE
156*493d26c5SEd Maste aq_log_error("RBL> Host Bootload mode: this driver does not support Host Boot");
157*493d26c5SEd Maste return (-ENOTSUP);
158*493d26c5SEd Maste #else
159*493d26c5SEd Maste trace(dbg_init, "RBL> Host Bootload mode");
160*493d26c5SEd Maste break;
161*493d26c5SEd Maste #endif // HOST_BOOT_DISABLE
162*493d26c5SEd Maste }
163*493d26c5SEd Maste
164*493d26c5SEd Maste /*
165*493d26c5SEd Maste * #todo: Host Boot
166*493d26c5SEd Maste */
167*493d26c5SEd Maste aq_log_error("RBL> F/W Host Bootload not implemented");
168*493d26c5SEd Maste
169*493d26c5SEd Maste return (-ENOTSUP);
170*493d26c5SEd Maste }
171*493d26c5SEd Maste
aq_fw_ops_init(struct aq_hw * hw)172*493d26c5SEd Maste int aq_fw_ops_init(struct aq_hw* hw)
173*493d26c5SEd Maste {
174*493d26c5SEd Maste if (hw->fw_version.raw == 0)
175*493d26c5SEd Maste hw->fw_version.raw = AQ_READ_REG(hw, 0x18);
176*493d26c5SEd Maste
177*493d26c5SEd Maste aq_log("MAC F/W version is %d.%d.%d",
178*493d26c5SEd Maste hw->fw_version.major_version, hw->fw_version.minor_version,
179*493d26c5SEd Maste hw->fw_version.build_number);
180*493d26c5SEd Maste
181*493d26c5SEd Maste if (hw->fw_version.major_version == 1) {
182*493d26c5SEd Maste trace(dbg_init, "using F/W ops v1.x");
183*493d26c5SEd Maste hw->fw_ops = &aq_fw1x_ops;
184*493d26c5SEd Maste return (EOK);
185*493d26c5SEd Maste } else if (hw->fw_version.major_version >= 2) {
186*493d26c5SEd Maste trace(dbg_init, "using F/W ops v2.x");
187*493d26c5SEd Maste hw->fw_ops = &aq_fw2x_ops;
188*493d26c5SEd Maste return (EOK);
189*493d26c5SEd Maste }
190*493d26c5SEd Maste
191*493d26c5SEd Maste aq_log_error("aq_fw_ops_init(): invalid F/W version %#x", hw->fw_version.raw);
192*493d26c5SEd Maste return (-ENOTSUP);
193*493d26c5SEd Maste }
194*493d26c5SEd Maste
195*493d26c5SEd Maste
mac_soft_reset_(struct aq_hw * hw,aq_fw_bootloader_mode * mode)196*493d26c5SEd Maste int mac_soft_reset_(struct aq_hw* hw, aq_fw_bootloader_mode* mode /*= nullptr*/)
197*493d26c5SEd Maste {
198*493d26c5SEd Maste if (hw->rbl_enabled) {
199*493d26c5SEd Maste return mac_soft_reset_rbl_(hw, mode);
200*493d26c5SEd Maste } else {
201*493d26c5SEd Maste if (mode)
202*493d26c5SEd Maste *mode = boot_mode_flb;
203*493d26c5SEd Maste
204*493d26c5SEd Maste return mac_soft_reset_flb_(hw);
205*493d26c5SEd Maste }
206*493d26c5SEd Maste }
207*493d26c5SEd Maste
mac_soft_reset_flb_(struct aq_hw * hw)208*493d26c5SEd Maste int mac_soft_reset_flb_(struct aq_hw* hw)
209*493d26c5SEd Maste {
210*493d26c5SEd Maste int k;
211*493d26c5SEd Maste
212*493d26c5SEd Maste reg_global_ctl2_set(hw, 0x40e1);
213*493d26c5SEd Maste // Let Felicity hardware to complete SMBUS transaction before Global software reset.
214*493d26c5SEd Maste msec_delay(50);
215*493d26c5SEd Maste
216*493d26c5SEd Maste /*
217*493d26c5SEd Maste * If SPI burst transaction was interrupted(before running the script), global software
218*493d26c5SEd Maste * reset may not clear SPI interface. Clean it up manually before global reset.
219*493d26c5SEd Maste */
220*493d26c5SEd Maste reg_glb_nvr_provisioning2_set(hw, 0xa0);
221*493d26c5SEd Maste reg_glb_nvr_interface1_set(hw, 0x9f);
222*493d26c5SEd Maste reg_glb_nvr_interface1_set(hw, 0x809f);
223*493d26c5SEd Maste msec_delay(50);
224*493d26c5SEd Maste
225*493d26c5SEd Maste reg_glb_standard_ctl1_set(hw, (reg_glb_standard_ctl1_get(hw) & ~glb_reg_res_dis_msk) | glb_soft_res_msk);
226*493d26c5SEd Maste
227*493d26c5SEd Maste // Kickstart.
228*493d26c5SEd Maste reg_global_ctl2_set(hw, 0x80e0);
229*493d26c5SEd Maste reg_mif_power_gating_enable_control_set(hw, 0);
230*493d26c5SEd Maste if (!hw->fast_start_enabled)
231*493d26c5SEd Maste reg_glb_general_provisioning9_set(hw, 1);
232*493d26c5SEd Maste
233*493d26c5SEd Maste /*
234*493d26c5SEd Maste * For the case SPI burst transaction was interrupted (by MCP reset above),
235*493d26c5SEd Maste * wait until it is completed by hardware.
236*493d26c5SEd Maste */
237*493d26c5SEd Maste msec_delay(50); // Sleep for 10 ms.
238*493d26c5SEd Maste
239*493d26c5SEd Maste /* MAC Kickstart */
240*493d26c5SEd Maste if (!hw->fast_start_enabled) {
241*493d26c5SEd Maste reg_global_ctl2_set(hw, 0x180e0);
242*493d26c5SEd Maste
243*493d26c5SEd Maste u32 flb_status = 0;
244*493d26c5SEd Maste int k;
245*493d26c5SEd Maste for (k = 0; k < 1000; ++k) {
246*493d26c5SEd Maste flb_status = reg_glb_daisy_chain_status1_get(hw) & 0x10;
247*493d26c5SEd Maste if (flb_status != 0)
248*493d26c5SEd Maste break;
249*493d26c5SEd Maste msec_delay(10); // Sleep for 10 ms.
250*493d26c5SEd Maste }
251*493d26c5SEd Maste
252*493d26c5SEd Maste if (flb_status == 0) {
253*493d26c5SEd Maste trace_error(dbg_init, "FLB> MAC kickstart failed: timed out");
254*493d26c5SEd Maste return (false);
255*493d26c5SEd Maste }
256*493d26c5SEd Maste
257*493d26c5SEd Maste trace(dbg_init, "FLB> MAC kickstart done, %d ms", k);
258*493d26c5SEd Maste /* FW reset */
259*493d26c5SEd Maste reg_global_ctl2_set(hw, 0x80e0);
260*493d26c5SEd Maste // Let Felicity hardware complete SMBUS transaction before Global software reset.
261*493d26c5SEd Maste msec_delay(50);
262*493d26c5SEd Maste }
263*493d26c5SEd Maste reg_glb_cpu_sem_set(hw, 1, 0);
264*493d26c5SEd Maste
265*493d26c5SEd Maste // PHY Kickstart: #undone
266*493d26c5SEd Maste
267*493d26c5SEd Maste // Global software reset
268*493d26c5SEd Maste rx_rx_reg_res_dis_set(hw, 0);
269*493d26c5SEd Maste tx_tx_reg_res_dis_set(hw, 0);
270*493d26c5SEd Maste mpi_tx_reg_res_dis_set(hw, 0);
271*493d26c5SEd Maste reg_glb_standard_ctl1_set(hw, (reg_glb_standard_ctl1_get(hw) & ~glb_reg_res_dis_msk) | glb_soft_res_msk);
272*493d26c5SEd Maste
273*493d26c5SEd Maste bool restart_completed = false;
274*493d26c5SEd Maste for (k = 0; k < 1000; ++k) {
275*493d26c5SEd Maste restart_completed = reg_glb_fw_image_id1_get(hw) != 0;
276*493d26c5SEd Maste if (restart_completed)
277*493d26c5SEd Maste break;
278*493d26c5SEd Maste msec_delay(10);
279*493d26c5SEd Maste }
280*493d26c5SEd Maste
281*493d26c5SEd Maste if (!restart_completed) {
282*493d26c5SEd Maste trace_error(dbg_init, "FLB> Global Soft Reset failed");
283*493d26c5SEd Maste return (false);
284*493d26c5SEd Maste }
285*493d26c5SEd Maste
286*493d26c5SEd Maste trace(dbg_init, "FLB> F/W restart: %d ms", k * 10);
287*493d26c5SEd Maste return (true);
288*493d26c5SEd Maste }
289*493d26c5SEd Maste
mac_soft_reset_rbl_(struct aq_hw * hw,aq_fw_bootloader_mode * mode)290*493d26c5SEd Maste int mac_soft_reset_rbl_(struct aq_hw* hw, aq_fw_bootloader_mode* mode)
291*493d26c5SEd Maste {
292*493d26c5SEd Maste trace(dbg_init, "RBL> MAC reset STARTED!");
293*493d26c5SEd Maste
294*493d26c5SEd Maste reg_global_ctl2_set(hw, 0x40e1);
295*493d26c5SEd Maste reg_glb_cpu_sem_set(hw, 1, 0);
296*493d26c5SEd Maste reg_mif_power_gating_enable_control_set(hw, 0);
297*493d26c5SEd Maste
298*493d26c5SEd Maste // MAC FW will reload PHY FW if 1E.1000.3 was cleaned - #undone
299*493d26c5SEd Maste
300*493d26c5SEd Maste reg_glb_cpu_no_reset_scratchpad_set(hw, 0xDEAD, NO_RESET_SCRATCHPAD_RBL_STATUS);
301*493d26c5SEd Maste
302*493d26c5SEd Maste // Global software reset
303*493d26c5SEd Maste rx_rx_reg_res_dis_set(hw, 0);
304*493d26c5SEd Maste tx_tx_reg_res_dis_set(hw, 0);
305*493d26c5SEd Maste mpi_tx_reg_res_dis_set(hw, 0);
306*493d26c5SEd Maste reg_glb_standard_ctl1_set(hw, (reg_glb_standard_ctl1_get(hw) & ~glb_reg_res_dis_msk) | glb_soft_res_msk);
307*493d26c5SEd Maste
308*493d26c5SEd Maste reg_global_ctl2_set(hw, 0x40e0);
309*493d26c5SEd Maste
310*493d26c5SEd Maste // Wait for RBL to finish boot process.
311*493d26c5SEd Maste u16 rbl_status = 0;
312*493d26c5SEd Maste for (int k = 0; k < RBL_TIMEOUT_MS; ++k) {
313*493d26c5SEd Maste rbl_status = LOWORD(reg_glb_cpu_no_reset_scratchpad_get(hw, NO_RESET_SCRATCHPAD_RBL_STATUS));
314*493d26c5SEd Maste if (rbl_status != 0 && rbl_status != 0xDEAD)
315*493d26c5SEd Maste break;
316*493d26c5SEd Maste
317*493d26c5SEd Maste msec_delay(1);
318*493d26c5SEd Maste }
319*493d26c5SEd Maste
320*493d26c5SEd Maste if (rbl_status == 0 || rbl_status == 0xDEAD) {
321*493d26c5SEd Maste trace_error(dbg_init, "RBL> RBL restart failed: timeout");
322*493d26c5SEd Maste return (-EBUSY);
323*493d26c5SEd Maste }
324*493d26c5SEd Maste
325*493d26c5SEd Maste if (rbl_status == RBL_STATUS_SUCCESS) {
326*493d26c5SEd Maste if (mode)
327*493d26c5SEd Maste *mode = boot_mode_rbl_flash;
328*493d26c5SEd Maste trace(dbg_init, "RBL> reset complete! [Flash]");
329*493d26c5SEd Maste } else if (rbl_status == RBL_STATUS_HOST_BOOT) {
330*493d26c5SEd Maste if (mode)
331*493d26c5SEd Maste *mode = boot_mode_rbl_host_bootload;
332*493d26c5SEd Maste trace(dbg_init, "RBL> reset complete! [Host Bootload]");
333*493d26c5SEd Maste } else {
334*493d26c5SEd Maste trace_error(dbg_init, "unknown RBL status 0x%x", rbl_status);
335*493d26c5SEd Maste return (-EBUSY);
336*493d26c5SEd Maste }
337*493d26c5SEd Maste
338*493d26c5SEd Maste return (EOK);
339*493d26c5SEd Maste }
340*493d26c5SEd Maste
wait_init_mac_firmware_(struct aq_hw * hw)341*493d26c5SEd Maste int wait_init_mac_firmware_(struct aq_hw* hw)
342*493d26c5SEd Maste {
343*493d26c5SEd Maste for (int i = 0; i < MAC_FW_START_TIMEOUT_MS; ++i) {
344*493d26c5SEd Maste if ((hw->fw_version.raw = AQ_READ_REG(hw, 0x18)) != 0)
345*493d26c5SEd Maste return (EOK);
346*493d26c5SEd Maste
347*493d26c5SEd Maste msec_delay(1);
348*493d26c5SEd Maste }
349*493d26c5SEd Maste
350*493d26c5SEd Maste trace_error(dbg_init, "timeout waiting for reg 0x18. MAC f/w NOT READY");
351*493d26c5SEd Maste return (-EBUSY);
352*493d26c5SEd Maste }
353