1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2008, 2009 Rui Paulo <rpaulo@FreeBSD.org> 5 * Copyright (c) 2009 Norikatsu Shigemura <nork@FreeBSD.org> 6 * Copyright (c) 2009-2012 Jung-uk Kim <jkim@FreeBSD.org> 7 * All rights reserved. 8 * Copyright (c) 2017-2020 Conrad Meyer <cem@FreeBSD.org>. All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Driver for the AMD CPU on-die thermal sensors. 34 * Initially based on the k8temp Linux driver. 35 */ 36 37 #include <sys/param.h> 38 #include <sys/bus.h> 39 #include <sys/conf.h> 40 #include <sys/kernel.h> 41 #include <sys/lock.h> 42 #include <sys/module.h> 43 #include <sys/mutex.h> 44 #include <sys/sysctl.h> 45 #include <sys/systm.h> 46 47 #include <machine/cpufunc.h> 48 #include <machine/md_var.h> 49 #include <machine/specialreg.h> 50 51 #include <dev/pci/pcivar.h> 52 #include <x86/pci_cfgreg.h> 53 54 #include <dev/amdsmn/amdsmn.h> 55 56 typedef enum { 57 CORE0_SENSOR0, 58 CORE0_SENSOR1, 59 CORE1_SENSOR0, 60 CORE1_SENSOR1, 61 CORE0, 62 CORE1, 63 CCD1, 64 CCD_BASE = CCD1, 65 CCD2, 66 CCD3, 67 CCD4, 68 CCD5, 69 CCD6, 70 CCD7, 71 CCD8, 72 CCD9, 73 CCD10, 74 CCD11, 75 CCD12, 76 CCD_MAX = CCD12, 77 NUM_CCDS = CCD_MAX - CCD_BASE + 1, 78 } amdsensor_t; 79 80 struct amdtemp_softc { 81 int sc_ncores; 82 int sc_ntemps; 83 int sc_flags; 84 #define AMDTEMP_FLAG_CS_SWAP 0x01 /* ThermSenseCoreSel is inverted. */ 85 #define AMDTEMP_FLAG_CT_10BIT 0x02 /* CurTmp is 10-bit wide. */ 86 #define AMDTEMP_FLAG_ALT_OFFSET 0x04 /* CurTmp starts at -28C. */ 87 int32_t sc_offset; 88 int32_t sc_temp_base; 89 int32_t (*sc_gettemp)(device_t, amdsensor_t); 90 struct sysctl_oid *sc_sysctl_cpu[MAXCPU]; 91 struct intr_config_hook sc_ich; 92 device_t sc_smn; 93 struct mtx sc_lock; 94 }; 95 96 /* 97 * N.B. The numbers in macro names below are significant and represent CPU 98 * family and model numbers. Do not make up fictitious family or model numbers 99 * when adding support for new devices. 100 */ 101 #define VENDORID_AMD 0x1022 102 #define DEVICEID_AMD_MISC0F 0x1103 103 #define DEVICEID_AMD_MISC10 0x1203 104 #define DEVICEID_AMD_MISC11 0x1303 105 #define DEVICEID_AMD_MISC14 0x1703 106 #define DEVICEID_AMD_MISC15 0x1603 107 #define DEVICEID_AMD_MISC15_M10H 0x1403 108 #define DEVICEID_AMD_MISC15_M30H 0x141d 109 #define DEVICEID_AMD_MISC15_M60H_ROOT 0x1576 110 #define DEVICEID_AMD_MISC16 0x1533 111 #define DEVICEID_AMD_MISC16_M30H 0x1583 112 #define DEVICEID_AMD_HOSTB17H_ROOT 0x1450 113 #define DEVICEID_AMD_HOSTB17H_M10H_ROOT 0x15d0 114 #define DEVICEID_AMD_HOSTB17H_M30H_ROOT 0x1480 /* Also M70H, F19H M00H/M20H */ 115 #define DEVICEID_AMD_HOSTB17H_M60H_ROOT 0x1630 116 #define DEVICEID_AMD_HOSTB19H_M10H_ROOT 0x14a4 117 #define DEVICEID_AMD_HOSTB19H_M60H_ROOT 0x14d8 118 #define DEVICEID_AMD_HOSTB19H_M70H_ROOT 0x14e8 119 120 static const struct amdtemp_product { 121 uint16_t amdtemp_vendorid; 122 uint16_t amdtemp_deviceid; 123 /* 124 * 0xFC register is only valid on the D18F3 PCI device; SMN temp 125 * drivers do not attach to that device. 126 */ 127 bool amdtemp_has_cpuid; 128 } amdtemp_products[] = { 129 { VENDORID_AMD, DEVICEID_AMD_MISC0F, true }, 130 { VENDORID_AMD, DEVICEID_AMD_MISC10, true }, 131 { VENDORID_AMD, DEVICEID_AMD_MISC11, true }, 132 { VENDORID_AMD, DEVICEID_AMD_MISC14, true }, 133 { VENDORID_AMD, DEVICEID_AMD_MISC15, true }, 134 { VENDORID_AMD, DEVICEID_AMD_MISC15_M10H, true }, 135 { VENDORID_AMD, DEVICEID_AMD_MISC15_M30H, true }, 136 { VENDORID_AMD, DEVICEID_AMD_MISC15_M60H_ROOT, false }, 137 { VENDORID_AMD, DEVICEID_AMD_MISC16, true }, 138 { VENDORID_AMD, DEVICEID_AMD_MISC16_M30H, true }, 139 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_ROOT, false }, 140 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M10H_ROOT, false }, 141 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M30H_ROOT, false }, 142 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M60H_ROOT, false }, 143 { VENDORID_AMD, DEVICEID_AMD_HOSTB19H_M10H_ROOT, false }, 144 { VENDORID_AMD, DEVICEID_AMD_HOSTB19H_M60H_ROOT, false }, 145 { VENDORID_AMD, DEVICEID_AMD_HOSTB19H_M70H_ROOT, false }, 146 }; 147 148 /* 149 * Reported Temperature Control Register, family 0Fh-15h (some models), 16h. 150 */ 151 #define AMDTEMP_REPTMP_CTRL 0xa4 152 153 #define AMDTEMP_REPTMP10H_CURTMP_MASK 0x7ff 154 #define AMDTEMP_REPTMP10H_CURTMP_SHIFT 21 155 #define AMDTEMP_REPTMP10H_TJSEL_MASK 0x3 156 #define AMDTEMP_REPTMP10H_TJSEL_SHIFT 16 157 158 /* 159 * Reported Temperature, Family 15h, M60+ 160 * 161 * Same register bit definitions as other Family 15h CPUs, but access is 162 * indirect via SMN, like Family 17h. 163 */ 164 #define AMDTEMP_15H_M60H_REPTMP_CTRL 0xd8200ca4 165 166 /* 167 * Reported Temperature, Family 17h 168 * 169 * According to AMD OSRR for 17H, section 4.2.1, bits 31-21 of this register 170 * provide the current temp. bit 19, when clear, means the temp is reported in 171 * a range 0.."225C" (probable typo for 255C), and when set changes the range 172 * to -49..206C. 173 */ 174 #define AMDTEMP_17H_CUR_TMP 0x59800 175 #define AMDTEMP_17H_CUR_TMP_RANGE_SEL (1u << 19) 176 /* 177 * Bits 16-17, when set, mean that CUR_TMP is read-write. When it is, the 178 * 49 degree offset should apply as well. This was revealed in a Linux 179 * patch from an AMD employee. 180 */ 181 #define AMDTEMP_17H_CUR_TMP_TJ_SEL ((1u << 17) | (1u << 16)) 182 /* 183 * The following register set was discovered experimentally by Ondrej Čerman 184 * and collaborators, but is not (yet) documented in a PPR/OSRR (other than 185 * the M70H PPR SMN memory map showing [0x59800, +0x314] as allocated to 186 * SMU::THM). It seems plausible and the Linux sensor folks have adopted it. 187 */ 188 #define AMDTEMP_17H_CCD_TMP_BASE 0x59954 189 #define AMDTEMP_17H_CCD_TMP_VALID (1u << 11) 190 191 #define AMDTEMP_ZEN4_10H_CCD_TMP_BASE 0x59b00 192 #define AMDTEMP_ZEN4_CCD_TMP_BASE 0x59b08 193 194 /* 195 * AMD temperature range adjustment, in deciKelvins (i.e., 49.0 Celsius). 196 */ 197 #define AMDTEMP_CURTMP_RANGE_ADJUST 490 198 199 /* 200 * Thermaltrip Status Register (Family 0Fh only) 201 */ 202 #define AMDTEMP_THERMTP_STAT 0xe4 203 #define AMDTEMP_TTSR_SELCORE 0x04 204 #define AMDTEMP_TTSR_SELSENSOR 0x40 205 206 /* 207 * DRAM Configuration High Register 208 */ 209 #define AMDTEMP_DRAM_CONF_HIGH 0x94 /* Function 2 */ 210 #define AMDTEMP_DRAM_MODE_DDR3 0x0100 211 212 /* 213 * CPU Family/Model Register 214 */ 215 #define AMDTEMP_CPUID 0xfc 216 217 /* 218 * Device methods. 219 */ 220 static void amdtemp_identify(driver_t *driver, device_t parent); 221 static int amdtemp_probe(device_t dev); 222 static int amdtemp_attach(device_t dev); 223 static void amdtemp_intrhook(void *arg); 224 static int amdtemp_detach(device_t dev); 225 static int32_t amdtemp_gettemp0f(device_t dev, amdsensor_t sensor); 226 static int32_t amdtemp_gettemp(device_t dev, amdsensor_t sensor); 227 static int32_t amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor); 228 static int32_t amdtemp_gettemp17h(device_t dev, amdsensor_t sensor); 229 static void amdtemp_probe_ccd_sensors17h(device_t dev, uint32_t model); 230 static void amdtemp_probe_ccd_sensors19h(device_t dev, uint32_t model); 231 static int amdtemp_sysctl(SYSCTL_HANDLER_ARGS); 232 233 static device_method_t amdtemp_methods[] = { 234 /* Device interface */ 235 DEVMETHOD(device_identify, amdtemp_identify), 236 DEVMETHOD(device_probe, amdtemp_probe), 237 DEVMETHOD(device_attach, amdtemp_attach), 238 DEVMETHOD(device_detach, amdtemp_detach), 239 240 DEVMETHOD_END 241 }; 242 243 static driver_t amdtemp_driver = { 244 "amdtemp", 245 amdtemp_methods, 246 sizeof(struct amdtemp_softc), 247 }; 248 249 DRIVER_MODULE(amdtemp, hostb, amdtemp_driver, NULL, NULL); 250 MODULE_VERSION(amdtemp, 1); 251 MODULE_DEPEND(amdtemp, amdsmn, 1, 1, 1); 252 MODULE_PNP_INFO("U16:vendor;U16:device", pci, amdtemp, amdtemp_products, 253 nitems(amdtemp_products)); 254 255 static bool 256 amdtemp_match(device_t dev, const struct amdtemp_product **product_out) 257 { 258 int i; 259 uint16_t vendor, devid; 260 261 vendor = pci_get_vendor(dev); 262 devid = pci_get_device(dev); 263 264 for (i = 0; i < nitems(amdtemp_products); i++) { 265 if (vendor == amdtemp_products[i].amdtemp_vendorid && 266 devid == amdtemp_products[i].amdtemp_deviceid) { 267 if (product_out != NULL) 268 *product_out = &amdtemp_products[i]; 269 return (true); 270 } 271 } 272 return (false); 273 } 274 275 static void 276 amdtemp_identify(driver_t *driver, device_t parent) 277 { 278 device_t child; 279 280 /* Make sure we're not being doubly invoked. */ 281 if (device_find_child(parent, "amdtemp", -1) != NULL) 282 return; 283 284 if (amdtemp_match(parent, NULL)) { 285 child = device_add_child(parent, "amdtemp", DEVICE_UNIT_ANY); 286 if (child == NULL) 287 device_printf(parent, "add amdtemp child failed\n"); 288 } 289 } 290 291 static int 292 amdtemp_probe(device_t dev) 293 { 294 uint32_t family, model; 295 296 if (resource_disabled("amdtemp", 0)) 297 return (ENXIO); 298 if (!amdtemp_match(device_get_parent(dev), NULL)) 299 return (ENXIO); 300 301 family = CPUID_TO_FAMILY(cpu_id); 302 model = CPUID_TO_MODEL(cpu_id); 303 304 switch (family) { 305 case 0x0f: 306 if ((model == 0x04 && (cpu_id & CPUID_STEPPING) == 0) || 307 (model == 0x05 && (cpu_id & CPUID_STEPPING) <= 1)) 308 return (ENXIO); 309 break; 310 case 0x10: 311 case 0x11: 312 case 0x12: 313 case 0x14: 314 case 0x15: 315 case 0x16: 316 case 0x17: 317 case 0x19: 318 break; 319 default: 320 return (ENXIO); 321 } 322 device_set_desc(dev, "AMD CPU On-Die Thermal Sensors"); 323 324 return (BUS_PROBE_GENERIC); 325 } 326 327 static int 328 amdtemp_attach(device_t dev) 329 { 330 char tn[32]; 331 u_int regs[4]; 332 const struct amdtemp_product *product; 333 struct amdtemp_softc *sc; 334 struct sysctl_ctx_list *sysctlctx; 335 struct sysctl_oid *sysctlnode; 336 uint32_t cpuid, family, model; 337 u_int bid; 338 int erratum319, unit; 339 bool needsmn; 340 341 sc = device_get_softc(dev); 342 erratum319 = 0; 343 needsmn = false; 344 345 if (!amdtemp_match(device_get_parent(dev), &product)) 346 return (ENXIO); 347 348 cpuid = cpu_id; 349 family = CPUID_TO_FAMILY(cpuid); 350 model = CPUID_TO_MODEL(cpuid); 351 352 /* 353 * This checks for the byzantine condition of running a heterogenous 354 * revision multi-socket system where the attach thread is potentially 355 * probing a remote socket's PCI device. 356 * 357 * Currently, such scenarios are unsupported on models using the SMN 358 * (because on those models, amdtemp(4) attaches to a different PCI 359 * device than the one that contains AMDTEMP_CPUID). 360 * 361 * The ancient 0x0F family of devices only supports this register from 362 * models 40h+. 363 */ 364 if (product->amdtemp_has_cpuid && (family > 0x0f || 365 (family == 0x0f && model >= 0x40))) { 366 cpuid = pci_read_config(device_get_parent(dev), AMDTEMP_CPUID, 367 4); 368 family = CPUID_TO_FAMILY(cpuid); 369 model = CPUID_TO_MODEL(cpuid); 370 } 371 372 switch (family) { 373 case 0x0f: 374 /* 375 * Thermaltrip Status Register 376 * 377 * - ThermSenseCoreSel 378 * 379 * Revision F & G: 0 - Core1, 1 - Core0 380 * Other: 0 - Core0, 1 - Core1 381 * 382 * - CurTmp 383 * 384 * Revision G: bits 23-14 385 * Other: bits 23-16 386 * 387 * XXX According to the BKDG, CurTmp, ThermSenseSel and 388 * ThermSenseCoreSel bits were introduced in Revision F 389 * but CurTmp seems working fine as early as Revision C. 390 * However, it is not clear whether ThermSenseSel and/or 391 * ThermSenseCoreSel work in undocumented cases as well. 392 * In fact, the Linux driver suggests it may not work but 393 * we just assume it does until we find otherwise. 394 * 395 * XXX According to Linux, CurTmp starts at -28C on 396 * Socket AM2 Revision G processors, which is not 397 * documented anywhere. 398 */ 399 if (model >= 0x40) 400 sc->sc_flags |= AMDTEMP_FLAG_CS_SWAP; 401 if (model >= 0x60 && model != 0xc1) { 402 do_cpuid(0x80000001, regs); 403 bid = (regs[1] >> 9) & 0x1f; 404 switch (model) { 405 case 0x68: /* Socket S1g1 */ 406 case 0x6c: 407 case 0x7c: 408 break; 409 case 0x6b: /* Socket AM2 and ASB1 (2 cores) */ 410 if (bid != 0x0b && bid != 0x0c) 411 sc->sc_flags |= 412 AMDTEMP_FLAG_ALT_OFFSET; 413 break; 414 case 0x6f: /* Socket AM2 and ASB1 (1 core) */ 415 case 0x7f: 416 if (bid != 0x07 && bid != 0x09 && 417 bid != 0x0c) 418 sc->sc_flags |= 419 AMDTEMP_FLAG_ALT_OFFSET; 420 break; 421 default: 422 sc->sc_flags |= AMDTEMP_FLAG_ALT_OFFSET; 423 } 424 sc->sc_flags |= AMDTEMP_FLAG_CT_10BIT; 425 } 426 427 /* 428 * There are two sensors per core. 429 */ 430 sc->sc_ntemps = 2; 431 432 sc->sc_gettemp = amdtemp_gettemp0f; 433 break; 434 case 0x10: 435 /* 436 * Erratum 319 Inaccurate Temperature Measurement 437 * 438 * http://support.amd.com/us/Processor_TechDocs/41322.pdf 439 */ 440 do_cpuid(0x80000001, regs); 441 switch ((regs[1] >> 28) & 0xf) { 442 case 0: /* Socket F */ 443 erratum319 = 1; 444 break; 445 case 1: /* Socket AM2+ or AM3 */ 446 if ((pci_cfgregread(pci_get_domain(dev), 447 pci_get_bus(dev), pci_get_slot(dev), 2, 448 AMDTEMP_DRAM_CONF_HIGH, 2) & 449 AMDTEMP_DRAM_MODE_DDR3) != 0 || model > 0x04 || 450 (model == 0x04 && (cpuid & CPUID_STEPPING) >= 3)) 451 break; 452 /* XXX 00100F42h (RB-C2) exists in both formats. */ 453 erratum319 = 1; 454 break; 455 } 456 /* FALLTHROUGH */ 457 case 0x11: 458 case 0x12: 459 case 0x14: 460 case 0x15: 461 case 0x16: 462 sc->sc_ntemps = 1; 463 /* 464 * Some later (60h+) models of family 15h use a similar SMN 465 * network as family 17h. (However, the register index differs 466 * from 17h and the decoding matches other 10h-15h models, 467 * which differ from 17h.) 468 */ 469 if (family == 0x15 && model >= 0x60) { 470 sc->sc_gettemp = amdtemp_gettemp15hm60h; 471 needsmn = true; 472 } else 473 sc->sc_gettemp = amdtemp_gettemp; 474 break; 475 case 0x17: 476 case 0x19: 477 sc->sc_ntemps = 1; 478 sc->sc_gettemp = amdtemp_gettemp17h; 479 needsmn = true; 480 break; 481 default: 482 device_printf(dev, "Bogus family 0x%x\n", family); 483 return (ENXIO); 484 } 485 486 if (needsmn) { 487 sc->sc_smn = device_find_child( 488 device_get_parent(dev), "amdsmn", -1); 489 if (sc->sc_smn == NULL) { 490 if (bootverbose) 491 device_printf(dev, "No SMN device found\n"); 492 return (ENXIO); 493 } 494 } 495 496 /* Find number of cores per package. */ 497 sc->sc_ncores = (amd_feature2 & AMDID2_CMP) != 0 ? 498 (cpu_procinfo2 & AMDID_CMP_CORES) + 1 : 1; 499 if (sc->sc_ncores > MAXCPU) 500 return (ENXIO); 501 502 mtx_init(&sc->sc_lock, "amdtemp", NULL, MTX_DEF); 503 if (erratum319) 504 device_printf(dev, 505 "Erratum 319: temperature measurement may be inaccurate\n"); 506 if (bootverbose) 507 device_printf(dev, "Found %d cores and %d sensors.\n", 508 sc->sc_ncores, 509 sc->sc_ntemps > 1 ? sc->sc_ntemps * sc->sc_ncores : 1); 510 511 /* 512 * dev.amdtemp.N tree. 513 */ 514 unit = device_get_unit(dev); 515 snprintf(tn, sizeof(tn), "dev.amdtemp.%d.sensor_offset", unit); 516 TUNABLE_INT_FETCH(tn, &sc->sc_offset); 517 518 sysctlctx = device_get_sysctl_ctx(dev); 519 SYSCTL_ADD_INT(sysctlctx, 520 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 521 "sensor_offset", CTLFLAG_RW, &sc->sc_offset, 0, 522 "Temperature sensor offset"); 523 sysctlnode = SYSCTL_ADD_NODE(sysctlctx, 524 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 525 "core0", CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "Core 0"); 526 527 SYSCTL_ADD_PROC(sysctlctx, 528 SYSCTL_CHILDREN(sysctlnode), 529 OID_AUTO, "sensor0", 530 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 531 dev, CORE0_SENSOR0, amdtemp_sysctl, "IK", 532 "Core 0 / Sensor 0 temperature"); 533 534 sc->sc_temp_base = AMDTEMP_17H_CCD_TMP_BASE; 535 536 if (family == 0x17) 537 amdtemp_probe_ccd_sensors17h(dev, model); 538 else if (family == 0x19) 539 amdtemp_probe_ccd_sensors19h(dev, model); 540 else if (sc->sc_ntemps > 1) { 541 SYSCTL_ADD_PROC(sysctlctx, 542 SYSCTL_CHILDREN(sysctlnode), 543 OID_AUTO, "sensor1", 544 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 545 dev, CORE0_SENSOR1, amdtemp_sysctl, "IK", 546 "Core 0 / Sensor 1 temperature"); 547 548 if (sc->sc_ncores > 1) { 549 sysctlnode = SYSCTL_ADD_NODE(sysctlctx, 550 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 551 OID_AUTO, "core1", CTLFLAG_RD | CTLFLAG_MPSAFE, 552 0, "Core 1"); 553 554 SYSCTL_ADD_PROC(sysctlctx, 555 SYSCTL_CHILDREN(sysctlnode), 556 OID_AUTO, "sensor0", 557 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 558 dev, CORE1_SENSOR0, amdtemp_sysctl, "IK", 559 "Core 1 / Sensor 0 temperature"); 560 561 SYSCTL_ADD_PROC(sysctlctx, 562 SYSCTL_CHILDREN(sysctlnode), 563 OID_AUTO, "sensor1", 564 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 565 dev, CORE1_SENSOR1, amdtemp_sysctl, "IK", 566 "Core 1 / Sensor 1 temperature"); 567 } 568 } 569 570 /* 571 * Try to create dev.cpu sysctl entries and setup intrhook function. 572 * This is needed because the cpu driver may be loaded late on boot, 573 * after us. 574 */ 575 amdtemp_intrhook(dev); 576 sc->sc_ich.ich_func = amdtemp_intrhook; 577 sc->sc_ich.ich_arg = dev; 578 if (config_intrhook_establish(&sc->sc_ich) != 0) { 579 device_printf(dev, "config_intrhook_establish failed!\n"); 580 return (ENXIO); 581 } 582 583 return (0); 584 } 585 586 void 587 amdtemp_intrhook(void *arg) 588 { 589 struct amdtemp_softc *sc; 590 struct sysctl_ctx_list *sysctlctx; 591 device_t dev = (device_t)arg; 592 device_t acpi, cpu, nexus; 593 amdsensor_t sensor; 594 int i; 595 596 sc = device_get_softc(dev); 597 598 /* 599 * dev.cpu.N.temperature. 600 */ 601 nexus = device_find_child(root_bus, "nexus", 0); 602 acpi = device_find_child(nexus, "acpi", 0); 603 604 for (i = 0; i < sc->sc_ncores; i++) { 605 if (sc->sc_sysctl_cpu[i] != NULL) 606 continue; 607 cpu = device_find_child(acpi, "cpu", 608 device_get_unit(dev) * sc->sc_ncores + i); 609 if (cpu != NULL) { 610 sysctlctx = device_get_sysctl_ctx(cpu); 611 612 sensor = sc->sc_ntemps > 1 ? 613 (i == 0 ? CORE0 : CORE1) : CORE0_SENSOR0; 614 sc->sc_sysctl_cpu[i] = SYSCTL_ADD_PROC(sysctlctx, 615 SYSCTL_CHILDREN(device_get_sysctl_tree(cpu)), 616 OID_AUTO, "temperature", 617 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 618 dev, sensor, amdtemp_sysctl, "IK", 619 "Current temparature"); 620 } 621 } 622 if (sc->sc_ich.ich_arg != NULL) 623 config_intrhook_disestablish(&sc->sc_ich); 624 } 625 626 int 627 amdtemp_detach(device_t dev) 628 { 629 struct amdtemp_softc *sc = device_get_softc(dev); 630 int i; 631 632 for (i = 0; i < sc->sc_ncores; i++) 633 if (sc->sc_sysctl_cpu[i] != NULL) 634 sysctl_remove_oid(sc->sc_sysctl_cpu[i], 1, 0); 635 636 /* NewBus removes the dev.amdtemp.N tree by itself. */ 637 638 mtx_destroy(&sc->sc_lock); 639 return (0); 640 } 641 642 static int 643 amdtemp_sysctl(SYSCTL_HANDLER_ARGS) 644 { 645 device_t dev = (device_t)arg1; 646 struct amdtemp_softc *sc = device_get_softc(dev); 647 amdsensor_t sensor = (amdsensor_t)arg2; 648 int32_t auxtemp[2], temp; 649 int error; 650 651 switch (sensor) { 652 case CORE0: 653 auxtemp[0] = sc->sc_gettemp(dev, CORE0_SENSOR0); 654 auxtemp[1] = sc->sc_gettemp(dev, CORE0_SENSOR1); 655 temp = imax(auxtemp[0], auxtemp[1]); 656 break; 657 case CORE1: 658 auxtemp[0] = sc->sc_gettemp(dev, CORE1_SENSOR0); 659 auxtemp[1] = sc->sc_gettemp(dev, CORE1_SENSOR1); 660 temp = imax(auxtemp[0], auxtemp[1]); 661 break; 662 default: 663 temp = sc->sc_gettemp(dev, sensor); 664 break; 665 } 666 error = sysctl_handle_int(oidp, &temp, 0, req); 667 668 return (error); 669 } 670 671 #define AMDTEMP_ZERO_C_TO_K 2731 672 673 static int32_t 674 amdtemp_gettemp0f(device_t dev, amdsensor_t sensor) 675 { 676 struct amdtemp_softc *sc = device_get_softc(dev); 677 uint32_t mask, offset, temp; 678 679 mtx_lock(&sc->sc_lock); 680 681 /* Set Sensor/Core selector. */ 682 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 1); 683 temp &= ~(AMDTEMP_TTSR_SELCORE | AMDTEMP_TTSR_SELSENSOR); 684 switch (sensor) { 685 case CORE0_SENSOR1: 686 temp |= AMDTEMP_TTSR_SELSENSOR; 687 /* FALLTHROUGH */ 688 case CORE0_SENSOR0: 689 case CORE0: 690 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) != 0) 691 temp |= AMDTEMP_TTSR_SELCORE; 692 break; 693 case CORE1_SENSOR1: 694 temp |= AMDTEMP_TTSR_SELSENSOR; 695 /* FALLTHROUGH */ 696 case CORE1_SENSOR0: 697 case CORE1: 698 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) == 0) 699 temp |= AMDTEMP_TTSR_SELCORE; 700 break; 701 default: 702 __assert_unreachable(); 703 } 704 pci_write_config(dev, AMDTEMP_THERMTP_STAT, temp, 1); 705 706 mask = (sc->sc_flags & AMDTEMP_FLAG_CT_10BIT) != 0 ? 0x3ff : 0x3fc; 707 offset = (sc->sc_flags & AMDTEMP_FLAG_ALT_OFFSET) != 0 ? 28 : 49; 708 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 4); 709 temp = ((temp >> 14) & mask) * 5 / 2; 710 temp += AMDTEMP_ZERO_C_TO_K + (sc->sc_offset - offset) * 10; 711 712 mtx_unlock(&sc->sc_lock); 713 return (temp); 714 } 715 716 static uint32_t 717 amdtemp_decode_fam10h_to_17h(int32_t sc_offset, uint32_t val, bool minus49) 718 { 719 uint32_t temp; 720 721 /* Convert raw register subfield units (0.125C) to units of 0.1C. */ 722 temp = (val & AMDTEMP_REPTMP10H_CURTMP_MASK) * 5 / 4; 723 724 if (minus49) 725 temp -= AMDTEMP_CURTMP_RANGE_ADJUST; 726 727 temp += AMDTEMP_ZERO_C_TO_K + sc_offset * 10; 728 return (temp); 729 } 730 731 static uint32_t 732 amdtemp_decode_fam10h_to_16h(int32_t sc_offset, uint32_t val) 733 { 734 bool minus49; 735 736 /* 737 * On Family 15h and higher, if CurTmpTjSel is 11b, the range is 738 * adjusted down by 49.0 degrees Celsius. (This adjustment is not 739 * documented in BKDGs prior to family 15h model 00h.) 740 */ 741 minus49 = (CPUID_TO_FAMILY(cpu_id) >= 0x15 && 742 ((val >> AMDTEMP_REPTMP10H_TJSEL_SHIFT) & 743 AMDTEMP_REPTMP10H_TJSEL_MASK) == 0x3); 744 745 return (amdtemp_decode_fam10h_to_17h(sc_offset, 746 val >> AMDTEMP_REPTMP10H_CURTMP_SHIFT, minus49)); 747 } 748 749 static uint32_t 750 amdtemp_decode_fam17h_tctl(int32_t sc_offset, uint32_t val) 751 { 752 bool minus49; 753 754 minus49 = ((val & AMDTEMP_17H_CUR_TMP_RANGE_SEL) != 0) 755 || ((val & AMDTEMP_17H_CUR_TMP_TJ_SEL) == AMDTEMP_17H_CUR_TMP_TJ_SEL); 756 return (amdtemp_decode_fam10h_to_17h(sc_offset, 757 val >> AMDTEMP_REPTMP10H_CURTMP_SHIFT, minus49)); 758 } 759 760 static int32_t 761 amdtemp_gettemp(device_t dev, amdsensor_t sensor) 762 { 763 struct amdtemp_softc *sc = device_get_softc(dev); 764 uint32_t temp; 765 766 temp = pci_read_config(dev, AMDTEMP_REPTMP_CTRL, 4); 767 return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, temp)); 768 } 769 770 static int32_t 771 amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor) 772 { 773 struct amdtemp_softc *sc = device_get_softc(dev); 774 uint32_t val; 775 int error __diagused; 776 777 error = amdsmn_read(sc->sc_smn, AMDTEMP_15H_M60H_REPTMP_CTRL, &val); 778 KASSERT(error == 0, ("amdsmn_read")); 779 return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, val)); 780 } 781 782 static int32_t 783 amdtemp_gettemp17h(device_t dev, amdsensor_t sensor) 784 { 785 struct amdtemp_softc *sc = device_get_softc(dev); 786 uint32_t val; 787 int error __diagused; 788 789 switch (sensor) { 790 case CORE0_SENSOR0: 791 /* Tctl */ 792 error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CUR_TMP, &val); 793 KASSERT(error == 0, ("amdsmn_read")); 794 return (amdtemp_decode_fam17h_tctl(sc->sc_offset, val)); 795 case CCD_BASE ... CCD_MAX: 796 /* Tccd<N> */ 797 error = amdsmn_read(sc->sc_smn, sc->sc_temp_base + 798 (((int)sensor - CCD_BASE) * sizeof(val)), &val); 799 KASSERT(error == 0, ("amdsmn_read2")); 800 KASSERT((val & AMDTEMP_17H_CCD_TMP_VALID) != 0, 801 ("sensor %d: not valid", (int)sensor)); 802 return (amdtemp_decode_fam10h_to_17h(sc->sc_offset, val, true)); 803 default: 804 __assert_unreachable(); 805 } 806 } 807 808 static void 809 amdtemp_probe_ccd_sensors(device_t dev, uint32_t maxreg) 810 { 811 char sensor_name[16], sensor_descr[32]; 812 struct amdtemp_softc *sc; 813 uint32_t i, val; 814 int error; 815 816 sc = device_get_softc(dev); 817 for (i = 0; i < maxreg; i++) { 818 error = amdsmn_read(sc->sc_smn, sc->sc_temp_base + 819 (i * sizeof(val)), &val); 820 if (error != 0) 821 continue; 822 if ((val & AMDTEMP_17H_CCD_TMP_VALID) == 0) 823 continue; 824 825 snprintf(sensor_name, sizeof(sensor_name), "ccd%u", i); 826 snprintf(sensor_descr, sizeof(sensor_descr), 827 "CCD %u temperature (Tccd%u)", i, i); 828 829 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 830 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 831 sensor_name, CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 832 dev, CCD_BASE + i, amdtemp_sysctl, "IK", sensor_descr); 833 } 834 } 835 836 static void 837 amdtemp_probe_ccd_sensors17h(device_t dev, uint32_t model) 838 { 839 uint32_t maxreg; 840 841 switch (model) { 842 case 0x00 ... 0x2f: /* Zen1, Zen+ */ 843 maxreg = 4; 844 break; 845 case 0x30 ... 0x3f: /* Zen2 TR (Castle Peak)/EPYC (Rome) */ 846 case 0x60 ... 0x7f: /* Zen2 Ryzen (Renoir APU, Matisse) */ 847 case 0x90 ... 0x9f: /* Zen2 Ryzen (Van Gogh APU) */ 848 maxreg = 8; 849 _Static_assert((int)NUM_CCDS >= 8, ""); 850 break; 851 default: 852 device_printf(dev, 853 "Unrecognized Family 17h Model: %02xh\n", model); 854 return; 855 } 856 857 amdtemp_probe_ccd_sensors(dev, maxreg); 858 } 859 860 static void 861 amdtemp_probe_ccd_sensors19h(device_t dev, uint32_t model) 862 { 863 struct amdtemp_softc *sc = device_get_softc(dev); 864 uint32_t maxreg; 865 866 switch (model) { 867 case 0x00 ... 0x0f: /* Zen3 EPYC "Milan" */ 868 case 0x20 ... 0x2f: /* Zen3 Ryzen "Vermeer" */ 869 maxreg = 8; 870 _Static_assert((int)NUM_CCDS >= 8, ""); 871 break; 872 case 0x10 ... 0x1f: 873 sc->sc_temp_base = AMDTEMP_ZEN4_10H_CCD_TMP_BASE; 874 maxreg = 12; 875 _Static_assert((int)NUM_CCDS >= 12, ""); 876 break; 877 case 0x60 ... 0x6f: /* Zen4 Ryzen "Raphael" */ 878 case 0x70 ... 0x7f: /* Zen4 Ryzen "Phoenix" */ 879 sc->sc_temp_base = AMDTEMP_ZEN4_CCD_TMP_BASE; 880 maxreg = 8; 881 _Static_assert((int)NUM_CCDS >= 8, ""); 882 break; 883 default: 884 device_printf(dev, 885 "Unrecognized Family 19h Model: %02xh\n", model); 886 return; 887 } 888 889 amdtemp_probe_ccd_sensors(dev, maxreg); 890 } 891