1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2008, 2009 Rui Paulo <rpaulo@FreeBSD.org> 5 * Copyright (c) 2009 Norikatsu Shigemura <nork@FreeBSD.org> 6 * Copyright (c) 2009-2012 Jung-uk Kim <jkim@FreeBSD.org> 7 * All rights reserved. 8 * Copyright (c) 2017-2020 Conrad Meyer <cem@FreeBSD.org>. All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Driver for the AMD CPU on-die thermal sensors. 34 * Initially based on the k8temp Linux driver. 35 */ 36 37 #include <sys/cdefs.h> 38 __FBSDID("$FreeBSD$"); 39 40 #include <sys/param.h> 41 #include <sys/bus.h> 42 #include <sys/conf.h> 43 #include <sys/kernel.h> 44 #include <sys/lock.h> 45 #include <sys/module.h> 46 #include <sys/mutex.h> 47 #include <sys/sysctl.h> 48 #include <sys/systm.h> 49 50 #include <machine/cpufunc.h> 51 #include <machine/md_var.h> 52 #include <machine/specialreg.h> 53 54 #include <dev/pci/pcivar.h> 55 #include <x86/pci_cfgreg.h> 56 57 #include <dev/amdsmn/amdsmn.h> 58 59 typedef enum { 60 CORE0_SENSOR0, 61 CORE0_SENSOR1, 62 CORE1_SENSOR0, 63 CORE1_SENSOR1, 64 CORE0, 65 CORE1, 66 CCD1, 67 CCD_BASE = CCD1, 68 CCD2, 69 CCD3, 70 CCD4, 71 CCD5, 72 CCD6, 73 CCD7, 74 CCD8, 75 CCD_MAX = CCD8, 76 NUM_CCDS = CCD_MAX - CCD_BASE + 1, 77 } amdsensor_t; 78 79 struct amdtemp_softc { 80 int sc_ncores; 81 int sc_ntemps; 82 int sc_flags; 83 #define AMDTEMP_FLAG_CS_SWAP 0x01 /* ThermSenseCoreSel is inverted. */ 84 #define AMDTEMP_FLAG_CT_10BIT 0x02 /* CurTmp is 10-bit wide. */ 85 #define AMDTEMP_FLAG_ALT_OFFSET 0x04 /* CurTmp starts at -28C. */ 86 int32_t sc_offset; 87 int32_t sc_temp_base; 88 int32_t (*sc_gettemp)(device_t, amdsensor_t); 89 struct sysctl_oid *sc_sysctl_cpu[MAXCPU]; 90 struct intr_config_hook sc_ich; 91 device_t sc_smn; 92 struct mtx sc_lock; 93 }; 94 95 /* 96 * N.B. The numbers in macro names below are significant and represent CPU 97 * family and model numbers. Do not make up fictitious family or model numbers 98 * when adding support for new devices. 99 */ 100 #define VENDORID_AMD 0x1022 101 #define DEVICEID_AMD_MISC0F 0x1103 102 #define DEVICEID_AMD_MISC10 0x1203 103 #define DEVICEID_AMD_MISC11 0x1303 104 #define DEVICEID_AMD_MISC14 0x1703 105 #define DEVICEID_AMD_MISC15 0x1603 106 #define DEVICEID_AMD_MISC15_M10H 0x1403 107 #define DEVICEID_AMD_MISC15_M30H 0x141d 108 #define DEVICEID_AMD_MISC15_M60H_ROOT 0x1576 109 #define DEVICEID_AMD_MISC16 0x1533 110 #define DEVICEID_AMD_MISC16_M30H 0x1583 111 #define DEVICEID_AMD_HOSTB17H_ROOT 0x1450 112 #define DEVICEID_AMD_HOSTB17H_M10H_ROOT 0x15d0 113 #define DEVICEID_AMD_HOSTB17H_M30H_ROOT 0x1480 /* Also M70H, F19H M00H/M20H */ 114 #define DEVICEID_AMD_HOSTB17H_M60H_ROOT 0x1630 115 #define DEVICEID_AMD_HOSTB19H_M60H_ROOT 0x14d8 116 117 static const struct amdtemp_product { 118 uint16_t amdtemp_vendorid; 119 uint16_t amdtemp_deviceid; 120 /* 121 * 0xFC register is only valid on the D18F3 PCI device; SMN temp 122 * drivers do not attach to that device. 123 */ 124 bool amdtemp_has_cpuid; 125 } amdtemp_products[] = { 126 { VENDORID_AMD, DEVICEID_AMD_MISC0F, true }, 127 { VENDORID_AMD, DEVICEID_AMD_MISC10, true }, 128 { VENDORID_AMD, DEVICEID_AMD_MISC11, true }, 129 { VENDORID_AMD, DEVICEID_AMD_MISC14, true }, 130 { VENDORID_AMD, DEVICEID_AMD_MISC15, true }, 131 { VENDORID_AMD, DEVICEID_AMD_MISC15_M10H, true }, 132 { VENDORID_AMD, DEVICEID_AMD_MISC15_M30H, true }, 133 { VENDORID_AMD, DEVICEID_AMD_MISC15_M60H_ROOT, false }, 134 { VENDORID_AMD, DEVICEID_AMD_MISC16, true }, 135 { VENDORID_AMD, DEVICEID_AMD_MISC16_M30H, true }, 136 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_ROOT, false }, 137 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M10H_ROOT, false }, 138 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M30H_ROOT, false }, 139 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M60H_ROOT, false }, 140 { VENDORID_AMD, DEVICEID_AMD_HOSTB19H_M60H_ROOT, false }, 141 }; 142 143 /* 144 * Reported Temperature Control Register, family 0Fh-15h (some models), 16h. 145 */ 146 #define AMDTEMP_REPTMP_CTRL 0xa4 147 148 #define AMDTEMP_REPTMP10H_CURTMP_MASK 0x7ff 149 #define AMDTEMP_REPTMP10H_CURTMP_SHIFT 21 150 #define AMDTEMP_REPTMP10H_TJSEL_MASK 0x3 151 #define AMDTEMP_REPTMP10H_TJSEL_SHIFT 16 152 153 /* 154 * Reported Temperature, Family 15h, M60+ 155 * 156 * Same register bit definitions as other Family 15h CPUs, but access is 157 * indirect via SMN, like Family 17h. 158 */ 159 #define AMDTEMP_15H_M60H_REPTMP_CTRL 0xd8200ca4 160 161 /* 162 * Reported Temperature, Family 17h 163 * 164 * According to AMD OSRR for 17H, section 4.2.1, bits 31-21 of this register 165 * provide the current temp. bit 19, when clear, means the temp is reported in 166 * a range 0.."225C" (probable typo for 255C), and when set changes the range 167 * to -49..206C. 168 */ 169 #define AMDTEMP_17H_CUR_TMP 0x59800 170 #define AMDTEMP_17H_CUR_TMP_RANGE_SEL (1u << 19) 171 /* 172 * Bits 16-17, when set, mean that CUR_TMP is read-write. When it is, the 173 * 49 degree offset should apply as well. This was revealed in a Linux 174 * patch from an AMD employee. 175 */ 176 #define AMDTEMP_17H_CUR_TMP_TJ_SEL ((1u << 17) | (1u << 16)) 177 /* 178 * The following register set was discovered experimentally by Ondrej Čerman 179 * and collaborators, but is not (yet) documented in a PPR/OSRR (other than 180 * the M70H PPR SMN memory map showing [0x59800, +0x314] as allocated to 181 * SMU::THM). It seems plausible and the Linux sensor folks have adopted it. 182 */ 183 #define AMDTEMP_17H_CCD_TMP_BASE 0x59954 184 #define AMDTEMP_17H_CCD_TMP_VALID (1u << 11) 185 186 #define AMDTEMP_ZEN4_CCD_TMP_BASE 0x59b08 187 188 /* 189 * AMD temperature range adjustment, in deciKelvins (i.e., 49.0 Celsius). 190 */ 191 #define AMDTEMP_CURTMP_RANGE_ADJUST 490 192 193 /* 194 * Thermaltrip Status Register (Family 0Fh only) 195 */ 196 #define AMDTEMP_THERMTP_STAT 0xe4 197 #define AMDTEMP_TTSR_SELCORE 0x04 198 #define AMDTEMP_TTSR_SELSENSOR 0x40 199 200 /* 201 * DRAM Configuration High Register 202 */ 203 #define AMDTEMP_DRAM_CONF_HIGH 0x94 /* Function 2 */ 204 #define AMDTEMP_DRAM_MODE_DDR3 0x0100 205 206 /* 207 * CPU Family/Model Register 208 */ 209 #define AMDTEMP_CPUID 0xfc 210 211 /* 212 * Device methods. 213 */ 214 static void amdtemp_identify(driver_t *driver, device_t parent); 215 static int amdtemp_probe(device_t dev); 216 static int amdtemp_attach(device_t dev); 217 static void amdtemp_intrhook(void *arg); 218 static int amdtemp_detach(device_t dev); 219 static int32_t amdtemp_gettemp0f(device_t dev, amdsensor_t sensor); 220 static int32_t amdtemp_gettemp(device_t dev, amdsensor_t sensor); 221 static int32_t amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor); 222 static int32_t amdtemp_gettemp17h(device_t dev, amdsensor_t sensor); 223 static void amdtemp_probe_ccd_sensors17h(device_t dev, uint32_t model); 224 static void amdtemp_probe_ccd_sensors19h(device_t dev, uint32_t model); 225 static int amdtemp_sysctl(SYSCTL_HANDLER_ARGS); 226 227 static device_method_t amdtemp_methods[] = { 228 /* Device interface */ 229 DEVMETHOD(device_identify, amdtemp_identify), 230 DEVMETHOD(device_probe, amdtemp_probe), 231 DEVMETHOD(device_attach, amdtemp_attach), 232 DEVMETHOD(device_detach, amdtemp_detach), 233 234 DEVMETHOD_END 235 }; 236 237 static driver_t amdtemp_driver = { 238 "amdtemp", 239 amdtemp_methods, 240 sizeof(struct amdtemp_softc), 241 }; 242 243 DRIVER_MODULE(amdtemp, hostb, amdtemp_driver, NULL, NULL); 244 MODULE_VERSION(amdtemp, 1); 245 MODULE_DEPEND(amdtemp, amdsmn, 1, 1, 1); 246 MODULE_PNP_INFO("U16:vendor;U16:device", pci, amdtemp, amdtemp_products, 247 nitems(amdtemp_products)); 248 249 static bool 250 amdtemp_match(device_t dev, const struct amdtemp_product **product_out) 251 { 252 int i; 253 uint16_t vendor, devid; 254 255 vendor = pci_get_vendor(dev); 256 devid = pci_get_device(dev); 257 258 for (i = 0; i < nitems(amdtemp_products); i++) { 259 if (vendor == amdtemp_products[i].amdtemp_vendorid && 260 devid == amdtemp_products[i].amdtemp_deviceid) { 261 if (product_out != NULL) 262 *product_out = &amdtemp_products[i]; 263 return (true); 264 } 265 } 266 return (false); 267 } 268 269 static void 270 amdtemp_identify(driver_t *driver, device_t parent) 271 { 272 device_t child; 273 274 /* Make sure we're not being doubly invoked. */ 275 if (device_find_child(parent, "amdtemp", -1) != NULL) 276 return; 277 278 if (amdtemp_match(parent, NULL)) { 279 child = device_add_child(parent, "amdtemp", -1); 280 if (child == NULL) 281 device_printf(parent, "add amdtemp child failed\n"); 282 } 283 } 284 285 static int 286 amdtemp_probe(device_t dev) 287 { 288 uint32_t family, model; 289 290 if (resource_disabled("amdtemp", 0)) 291 return (ENXIO); 292 if (!amdtemp_match(device_get_parent(dev), NULL)) 293 return (ENXIO); 294 295 family = CPUID_TO_FAMILY(cpu_id); 296 model = CPUID_TO_MODEL(cpu_id); 297 298 switch (family) { 299 case 0x0f: 300 if ((model == 0x04 && (cpu_id & CPUID_STEPPING) == 0) || 301 (model == 0x05 && (cpu_id & CPUID_STEPPING) <= 1)) 302 return (ENXIO); 303 break; 304 case 0x10: 305 case 0x11: 306 case 0x12: 307 case 0x14: 308 case 0x15: 309 case 0x16: 310 case 0x17: 311 case 0x19: 312 break; 313 default: 314 return (ENXIO); 315 } 316 device_set_desc(dev, "AMD CPU On-Die Thermal Sensors"); 317 318 return (BUS_PROBE_GENERIC); 319 } 320 321 static int 322 amdtemp_attach(device_t dev) 323 { 324 char tn[32]; 325 u_int regs[4]; 326 const struct amdtemp_product *product; 327 struct amdtemp_softc *sc; 328 struct sysctl_ctx_list *sysctlctx; 329 struct sysctl_oid *sysctlnode; 330 uint32_t cpuid, family, model; 331 u_int bid; 332 int erratum319, unit; 333 bool needsmn; 334 335 sc = device_get_softc(dev); 336 erratum319 = 0; 337 needsmn = false; 338 339 if (!amdtemp_match(device_get_parent(dev), &product)) 340 return (ENXIO); 341 342 cpuid = cpu_id; 343 family = CPUID_TO_FAMILY(cpuid); 344 model = CPUID_TO_MODEL(cpuid); 345 346 /* 347 * This checks for the byzantine condition of running a heterogenous 348 * revision multi-socket system where the attach thread is potentially 349 * probing a remote socket's PCI device. 350 * 351 * Currently, such scenarios are unsupported on models using the SMN 352 * (because on those models, amdtemp(4) attaches to a different PCI 353 * device than the one that contains AMDTEMP_CPUID). 354 * 355 * The ancient 0x0F family of devices only supports this register from 356 * models 40h+. 357 */ 358 if (product->amdtemp_has_cpuid && (family > 0x0f || 359 (family == 0x0f && model >= 0x40))) { 360 cpuid = pci_read_config(device_get_parent(dev), AMDTEMP_CPUID, 361 4); 362 family = CPUID_TO_FAMILY(cpuid); 363 model = CPUID_TO_MODEL(cpuid); 364 } 365 366 switch (family) { 367 case 0x0f: 368 /* 369 * Thermaltrip Status Register 370 * 371 * - ThermSenseCoreSel 372 * 373 * Revision F & G: 0 - Core1, 1 - Core0 374 * Other: 0 - Core0, 1 - Core1 375 * 376 * - CurTmp 377 * 378 * Revision G: bits 23-14 379 * Other: bits 23-16 380 * 381 * XXX According to the BKDG, CurTmp, ThermSenseSel and 382 * ThermSenseCoreSel bits were introduced in Revision F 383 * but CurTmp seems working fine as early as Revision C. 384 * However, it is not clear whether ThermSenseSel and/or 385 * ThermSenseCoreSel work in undocumented cases as well. 386 * In fact, the Linux driver suggests it may not work but 387 * we just assume it does until we find otherwise. 388 * 389 * XXX According to Linux, CurTmp starts at -28C on 390 * Socket AM2 Revision G processors, which is not 391 * documented anywhere. 392 */ 393 if (model >= 0x40) 394 sc->sc_flags |= AMDTEMP_FLAG_CS_SWAP; 395 if (model >= 0x60 && model != 0xc1) { 396 do_cpuid(0x80000001, regs); 397 bid = (regs[1] >> 9) & 0x1f; 398 switch (model) { 399 case 0x68: /* Socket S1g1 */ 400 case 0x6c: 401 case 0x7c: 402 break; 403 case 0x6b: /* Socket AM2 and ASB1 (2 cores) */ 404 if (bid != 0x0b && bid != 0x0c) 405 sc->sc_flags |= 406 AMDTEMP_FLAG_ALT_OFFSET; 407 break; 408 case 0x6f: /* Socket AM2 and ASB1 (1 core) */ 409 case 0x7f: 410 if (bid != 0x07 && bid != 0x09 && 411 bid != 0x0c) 412 sc->sc_flags |= 413 AMDTEMP_FLAG_ALT_OFFSET; 414 break; 415 default: 416 sc->sc_flags |= AMDTEMP_FLAG_ALT_OFFSET; 417 } 418 sc->sc_flags |= AMDTEMP_FLAG_CT_10BIT; 419 } 420 421 /* 422 * There are two sensors per core. 423 */ 424 sc->sc_ntemps = 2; 425 426 sc->sc_gettemp = amdtemp_gettemp0f; 427 break; 428 case 0x10: 429 /* 430 * Erratum 319 Inaccurate Temperature Measurement 431 * 432 * http://support.amd.com/us/Processor_TechDocs/41322.pdf 433 */ 434 do_cpuid(0x80000001, regs); 435 switch ((regs[1] >> 28) & 0xf) { 436 case 0: /* Socket F */ 437 erratum319 = 1; 438 break; 439 case 1: /* Socket AM2+ or AM3 */ 440 if ((pci_cfgregread(pci_get_bus(dev), 441 pci_get_slot(dev), 2, AMDTEMP_DRAM_CONF_HIGH, 2) & 442 AMDTEMP_DRAM_MODE_DDR3) != 0 || model > 0x04 || 443 (model == 0x04 && (cpuid & CPUID_STEPPING) >= 3)) 444 break; 445 /* XXX 00100F42h (RB-C2) exists in both formats. */ 446 erratum319 = 1; 447 break; 448 } 449 /* FALLTHROUGH */ 450 case 0x11: 451 case 0x12: 452 case 0x14: 453 case 0x15: 454 case 0x16: 455 sc->sc_ntemps = 1; 456 /* 457 * Some later (60h+) models of family 15h use a similar SMN 458 * network as family 17h. (However, the register index differs 459 * from 17h and the decoding matches other 10h-15h models, 460 * which differ from 17h.) 461 */ 462 if (family == 0x15 && model >= 0x60) { 463 sc->sc_gettemp = amdtemp_gettemp15hm60h; 464 needsmn = true; 465 } else 466 sc->sc_gettemp = amdtemp_gettemp; 467 break; 468 case 0x17: 469 case 0x19: 470 sc->sc_ntemps = 1; 471 sc->sc_gettemp = amdtemp_gettemp17h; 472 needsmn = true; 473 break; 474 default: 475 device_printf(dev, "Bogus family 0x%x\n", family); 476 return (ENXIO); 477 } 478 479 if (needsmn) { 480 sc->sc_smn = device_find_child( 481 device_get_parent(dev), "amdsmn", -1); 482 if (sc->sc_smn == NULL) { 483 if (bootverbose) 484 device_printf(dev, "No SMN device found\n"); 485 return (ENXIO); 486 } 487 } 488 489 /* Find number of cores per package. */ 490 sc->sc_ncores = (amd_feature2 & AMDID2_CMP) != 0 ? 491 (cpu_procinfo2 & AMDID_CMP_CORES) + 1 : 1; 492 if (sc->sc_ncores > MAXCPU) 493 return (ENXIO); 494 495 mtx_init(&sc->sc_lock, "amdtemp", NULL, MTX_DEF); 496 if (erratum319) 497 device_printf(dev, 498 "Erratum 319: temperature measurement may be inaccurate\n"); 499 if (bootverbose) 500 device_printf(dev, "Found %d cores and %d sensors.\n", 501 sc->sc_ncores, 502 sc->sc_ntemps > 1 ? sc->sc_ntemps * sc->sc_ncores : 1); 503 504 /* 505 * dev.amdtemp.N tree. 506 */ 507 unit = device_get_unit(dev); 508 snprintf(tn, sizeof(tn), "dev.amdtemp.%d.sensor_offset", unit); 509 TUNABLE_INT_FETCH(tn, &sc->sc_offset); 510 511 sysctlctx = device_get_sysctl_ctx(dev); 512 SYSCTL_ADD_INT(sysctlctx, 513 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 514 "sensor_offset", CTLFLAG_RW, &sc->sc_offset, 0, 515 "Temperature sensor offset"); 516 sysctlnode = SYSCTL_ADD_NODE(sysctlctx, 517 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 518 "core0", CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "Core 0"); 519 520 SYSCTL_ADD_PROC(sysctlctx, 521 SYSCTL_CHILDREN(sysctlnode), 522 OID_AUTO, "sensor0", 523 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 524 dev, CORE0_SENSOR0, amdtemp_sysctl, "IK", 525 "Core 0 / Sensor 0 temperature"); 526 527 sc->sc_temp_base = AMDTEMP_17H_CCD_TMP_BASE; 528 529 if (family == 0x17) 530 amdtemp_probe_ccd_sensors17h(dev, model); 531 else if (family == 0x19) 532 amdtemp_probe_ccd_sensors19h(dev, model); 533 else if (sc->sc_ntemps > 1) { 534 SYSCTL_ADD_PROC(sysctlctx, 535 SYSCTL_CHILDREN(sysctlnode), 536 OID_AUTO, "sensor1", 537 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 538 dev, CORE0_SENSOR1, amdtemp_sysctl, "IK", 539 "Core 0 / Sensor 1 temperature"); 540 541 if (sc->sc_ncores > 1) { 542 sysctlnode = SYSCTL_ADD_NODE(sysctlctx, 543 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 544 OID_AUTO, "core1", CTLFLAG_RD | CTLFLAG_MPSAFE, 545 0, "Core 1"); 546 547 SYSCTL_ADD_PROC(sysctlctx, 548 SYSCTL_CHILDREN(sysctlnode), 549 OID_AUTO, "sensor0", 550 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 551 dev, CORE1_SENSOR0, amdtemp_sysctl, "IK", 552 "Core 1 / Sensor 0 temperature"); 553 554 SYSCTL_ADD_PROC(sysctlctx, 555 SYSCTL_CHILDREN(sysctlnode), 556 OID_AUTO, "sensor1", 557 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 558 dev, CORE1_SENSOR1, amdtemp_sysctl, "IK", 559 "Core 1 / Sensor 1 temperature"); 560 } 561 } 562 563 /* 564 * Try to create dev.cpu sysctl entries and setup intrhook function. 565 * This is needed because the cpu driver may be loaded late on boot, 566 * after us. 567 */ 568 amdtemp_intrhook(dev); 569 sc->sc_ich.ich_func = amdtemp_intrhook; 570 sc->sc_ich.ich_arg = dev; 571 if (config_intrhook_establish(&sc->sc_ich) != 0) { 572 device_printf(dev, "config_intrhook_establish failed!\n"); 573 return (ENXIO); 574 } 575 576 return (0); 577 } 578 579 void 580 amdtemp_intrhook(void *arg) 581 { 582 struct amdtemp_softc *sc; 583 struct sysctl_ctx_list *sysctlctx; 584 device_t dev = (device_t)arg; 585 device_t acpi, cpu, nexus; 586 amdsensor_t sensor; 587 int i; 588 589 sc = device_get_softc(dev); 590 591 /* 592 * dev.cpu.N.temperature. 593 */ 594 nexus = device_find_child(root_bus, "nexus", 0); 595 acpi = device_find_child(nexus, "acpi", 0); 596 597 for (i = 0; i < sc->sc_ncores; i++) { 598 if (sc->sc_sysctl_cpu[i] != NULL) 599 continue; 600 cpu = device_find_child(acpi, "cpu", 601 device_get_unit(dev) * sc->sc_ncores + i); 602 if (cpu != NULL) { 603 sysctlctx = device_get_sysctl_ctx(cpu); 604 605 sensor = sc->sc_ntemps > 1 ? 606 (i == 0 ? CORE0 : CORE1) : CORE0_SENSOR0; 607 sc->sc_sysctl_cpu[i] = SYSCTL_ADD_PROC(sysctlctx, 608 SYSCTL_CHILDREN(device_get_sysctl_tree(cpu)), 609 OID_AUTO, "temperature", 610 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 611 dev, sensor, amdtemp_sysctl, "IK", 612 "Current temparature"); 613 } 614 } 615 if (sc->sc_ich.ich_arg != NULL) 616 config_intrhook_disestablish(&sc->sc_ich); 617 } 618 619 int 620 amdtemp_detach(device_t dev) 621 { 622 struct amdtemp_softc *sc = device_get_softc(dev); 623 int i; 624 625 for (i = 0; i < sc->sc_ncores; i++) 626 if (sc->sc_sysctl_cpu[i] != NULL) 627 sysctl_remove_oid(sc->sc_sysctl_cpu[i], 1, 0); 628 629 /* NewBus removes the dev.amdtemp.N tree by itself. */ 630 631 mtx_destroy(&sc->sc_lock); 632 return (0); 633 } 634 635 static int 636 amdtemp_sysctl(SYSCTL_HANDLER_ARGS) 637 { 638 device_t dev = (device_t)arg1; 639 struct amdtemp_softc *sc = device_get_softc(dev); 640 amdsensor_t sensor = (amdsensor_t)arg2; 641 int32_t auxtemp[2], temp; 642 int error; 643 644 switch (sensor) { 645 case CORE0: 646 auxtemp[0] = sc->sc_gettemp(dev, CORE0_SENSOR0); 647 auxtemp[1] = sc->sc_gettemp(dev, CORE0_SENSOR1); 648 temp = imax(auxtemp[0], auxtemp[1]); 649 break; 650 case CORE1: 651 auxtemp[0] = sc->sc_gettemp(dev, CORE1_SENSOR0); 652 auxtemp[1] = sc->sc_gettemp(dev, CORE1_SENSOR1); 653 temp = imax(auxtemp[0], auxtemp[1]); 654 break; 655 default: 656 temp = sc->sc_gettemp(dev, sensor); 657 break; 658 } 659 error = sysctl_handle_int(oidp, &temp, 0, req); 660 661 return (error); 662 } 663 664 #define AMDTEMP_ZERO_C_TO_K 2731 665 666 static int32_t 667 amdtemp_gettemp0f(device_t dev, amdsensor_t sensor) 668 { 669 struct amdtemp_softc *sc = device_get_softc(dev); 670 uint32_t mask, offset, temp; 671 672 mtx_lock(&sc->sc_lock); 673 674 /* Set Sensor/Core selector. */ 675 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 1); 676 temp &= ~(AMDTEMP_TTSR_SELCORE | AMDTEMP_TTSR_SELSENSOR); 677 switch (sensor) { 678 case CORE0_SENSOR1: 679 temp |= AMDTEMP_TTSR_SELSENSOR; 680 /* FALLTHROUGH */ 681 case CORE0_SENSOR0: 682 case CORE0: 683 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) != 0) 684 temp |= AMDTEMP_TTSR_SELCORE; 685 break; 686 case CORE1_SENSOR1: 687 temp |= AMDTEMP_TTSR_SELSENSOR; 688 /* FALLTHROUGH */ 689 case CORE1_SENSOR0: 690 case CORE1: 691 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) == 0) 692 temp |= AMDTEMP_TTSR_SELCORE; 693 break; 694 default: 695 __assert_unreachable(); 696 } 697 pci_write_config(dev, AMDTEMP_THERMTP_STAT, temp, 1); 698 699 mask = (sc->sc_flags & AMDTEMP_FLAG_CT_10BIT) != 0 ? 0x3ff : 0x3fc; 700 offset = (sc->sc_flags & AMDTEMP_FLAG_ALT_OFFSET) != 0 ? 28 : 49; 701 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 4); 702 temp = ((temp >> 14) & mask) * 5 / 2; 703 temp += AMDTEMP_ZERO_C_TO_K + (sc->sc_offset - offset) * 10; 704 705 mtx_unlock(&sc->sc_lock); 706 return (temp); 707 } 708 709 static uint32_t 710 amdtemp_decode_fam10h_to_17h(int32_t sc_offset, uint32_t val, bool minus49) 711 { 712 uint32_t temp; 713 714 /* Convert raw register subfield units (0.125C) to units of 0.1C. */ 715 temp = (val & AMDTEMP_REPTMP10H_CURTMP_MASK) * 5 / 4; 716 717 if (minus49) 718 temp -= AMDTEMP_CURTMP_RANGE_ADJUST; 719 720 temp += AMDTEMP_ZERO_C_TO_K + sc_offset * 10; 721 return (temp); 722 } 723 724 static uint32_t 725 amdtemp_decode_fam10h_to_16h(int32_t sc_offset, uint32_t val) 726 { 727 bool minus49; 728 729 /* 730 * On Family 15h and higher, if CurTmpTjSel is 11b, the range is 731 * adjusted down by 49.0 degrees Celsius. (This adjustment is not 732 * documented in BKDGs prior to family 15h model 00h.) 733 */ 734 minus49 = (CPUID_TO_FAMILY(cpu_id) >= 0x15 && 735 ((val >> AMDTEMP_REPTMP10H_TJSEL_SHIFT) & 736 AMDTEMP_REPTMP10H_TJSEL_MASK) == 0x3); 737 738 return (amdtemp_decode_fam10h_to_17h(sc_offset, 739 val >> AMDTEMP_REPTMP10H_CURTMP_SHIFT, minus49)); 740 } 741 742 static uint32_t 743 amdtemp_decode_fam17h_tctl(int32_t sc_offset, uint32_t val) 744 { 745 bool minus49; 746 747 minus49 = ((val & AMDTEMP_17H_CUR_TMP_RANGE_SEL) != 0) 748 || ((val & AMDTEMP_17H_CUR_TMP_TJ_SEL) == AMDTEMP_17H_CUR_TMP_TJ_SEL); 749 return (amdtemp_decode_fam10h_to_17h(sc_offset, 750 val >> AMDTEMP_REPTMP10H_CURTMP_SHIFT, minus49)); 751 } 752 753 static int32_t 754 amdtemp_gettemp(device_t dev, amdsensor_t sensor) 755 { 756 struct amdtemp_softc *sc = device_get_softc(dev); 757 uint32_t temp; 758 759 temp = pci_read_config(dev, AMDTEMP_REPTMP_CTRL, 4); 760 return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, temp)); 761 } 762 763 static int32_t 764 amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor) 765 { 766 struct amdtemp_softc *sc = device_get_softc(dev); 767 uint32_t val; 768 int error __diagused; 769 770 error = amdsmn_read(sc->sc_smn, AMDTEMP_15H_M60H_REPTMP_CTRL, &val); 771 KASSERT(error == 0, ("amdsmn_read")); 772 return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, val)); 773 } 774 775 static int32_t 776 amdtemp_gettemp17h(device_t dev, amdsensor_t sensor) 777 { 778 struct amdtemp_softc *sc = device_get_softc(dev); 779 uint32_t val; 780 int error __diagused; 781 782 switch (sensor) { 783 case CORE0_SENSOR0: 784 /* Tctl */ 785 error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CUR_TMP, &val); 786 KASSERT(error == 0, ("amdsmn_read")); 787 return (amdtemp_decode_fam17h_tctl(sc->sc_offset, val)); 788 case CCD_BASE ... CCD_MAX: 789 /* Tccd<N> */ 790 error = amdsmn_read(sc->sc_smn, sc->sc_temp_base + 791 (((int)sensor - CCD_BASE) * sizeof(val)), &val); 792 KASSERT(error == 0, ("amdsmn_read2")); 793 KASSERT((val & AMDTEMP_17H_CCD_TMP_VALID) != 0, 794 ("sensor %d: not valid", (int)sensor)); 795 return (amdtemp_decode_fam10h_to_17h(sc->sc_offset, val, true)); 796 default: 797 __assert_unreachable(); 798 } 799 } 800 801 static void 802 amdtemp_probe_ccd_sensors(device_t dev, uint32_t maxreg) 803 { 804 char sensor_name[16], sensor_descr[32]; 805 struct amdtemp_softc *sc; 806 uint32_t i, val; 807 int error; 808 809 sc = device_get_softc(dev); 810 for (i = 0; i < maxreg; i++) { 811 error = amdsmn_read(sc->sc_smn, sc->sc_temp_base + 812 (i * sizeof(val)), &val); 813 if (error != 0) 814 continue; 815 if ((val & AMDTEMP_17H_CCD_TMP_VALID) == 0) 816 continue; 817 818 snprintf(sensor_name, sizeof(sensor_name), "ccd%u", i); 819 snprintf(sensor_descr, sizeof(sensor_descr), 820 "CCD %u temperature (Tccd%u)", i, i); 821 822 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 823 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 824 sensor_name, CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 825 dev, CCD_BASE + i, amdtemp_sysctl, "IK", sensor_descr); 826 } 827 } 828 829 static void 830 amdtemp_probe_ccd_sensors17h(device_t dev, uint32_t model) 831 { 832 uint32_t maxreg; 833 834 switch (model) { 835 case 0x00 ... 0x2f: /* Zen1, Zen+ */ 836 maxreg = 4; 837 break; 838 case 0x30 ... 0x3f: /* Zen2 TR (Castle Peak)/EPYC (Rome) */ 839 case 0x60 ... 0x7f: /* Zen2 Ryzen (Renoir APU, Matisse) */ 840 case 0x90 ... 0x9f: /* Zen2 Ryzen (Van Gogh APU) */ 841 maxreg = 8; 842 _Static_assert((int)NUM_CCDS >= 8, ""); 843 break; 844 default: 845 device_printf(dev, 846 "Unrecognized Family 17h Model: %02xh\n", model); 847 return; 848 } 849 850 amdtemp_probe_ccd_sensors(dev, maxreg); 851 } 852 853 static void 854 amdtemp_probe_ccd_sensors19h(device_t dev, uint32_t model) 855 { 856 struct amdtemp_softc *sc = device_get_softc(dev); 857 uint32_t maxreg; 858 859 switch (model) { 860 case 0x00 ... 0x0f: /* Zen3 EPYC "Milan" */ 861 case 0x20 ... 0x2f: /* Zen3 Ryzen "Vermeer" */ 862 maxreg = 8; 863 _Static_assert((int)NUM_CCDS >= 8, ""); 864 break; 865 case 0x60 ... 0x6f: /* Zen4 Ryzen "Raphael" */ 866 sc->sc_temp_base = AMDTEMP_ZEN4_CCD_TMP_BASE; 867 maxreg = 8; 868 _Static_assert((int)NUM_CCDS >= 8, ""); 869 break; 870 default: 871 device_printf(dev, 872 "Unrecognized Family 19h Model: %02xh\n", model); 873 return; 874 } 875 876 amdtemp_probe_ccd_sensors(dev, maxreg); 877 } 878