1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008, 2009 Rui Paulo <rpaulo@FreeBSD.org> 5 * Copyright (c) 2009 Norikatsu Shigemura <nork@FreeBSD.org> 6 * Copyright (c) 2009-2012 Jung-uk Kim <jkim@FreeBSD.org> 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 20 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 22 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 26 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 27 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * Driver for the AMD CPU on-die thermal sensors. 33 * Initially based on the k8temp Linux driver. 34 */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 #include <sys/param.h> 40 #include <sys/bus.h> 41 #include <sys/conf.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/sysctl.h> 45 #include <sys/systm.h> 46 47 #include <machine/cpufunc.h> 48 #include <machine/md_var.h> 49 #include <machine/specialreg.h> 50 51 #include <dev/pci/pcivar.h> 52 #include <x86/pci_cfgreg.h> 53 54 #include <dev/amdsmn/amdsmn.h> 55 56 typedef enum { 57 CORE0_SENSOR0, 58 CORE0_SENSOR1, 59 CORE1_SENSOR0, 60 CORE1_SENSOR1, 61 CORE0, 62 CORE1 63 } amdsensor_t; 64 65 struct amdtemp_softc { 66 int sc_ncores; 67 int sc_ntemps; 68 int sc_flags; 69 #define AMDTEMP_FLAG_CS_SWAP 0x01 /* ThermSenseCoreSel is inverted. */ 70 #define AMDTEMP_FLAG_CT_10BIT 0x02 /* CurTmp is 10-bit wide. */ 71 #define AMDTEMP_FLAG_ALT_OFFSET 0x04 /* CurTmp starts at -28C. */ 72 int32_t sc_offset; 73 int32_t (*sc_gettemp)(device_t, amdsensor_t); 74 struct sysctl_oid *sc_sysctl_cpu[MAXCPU]; 75 struct intr_config_hook sc_ich; 76 device_t sc_smn; 77 }; 78 79 #define VENDORID_AMD 0x1022 80 #define DEVICEID_AMD_MISC0F 0x1103 81 #define DEVICEID_AMD_MISC10 0x1203 82 #define DEVICEID_AMD_MISC11 0x1303 83 #define DEVICEID_AMD_MISC12 0x1403 84 #define DEVICEID_AMD_MISC14 0x1703 85 #define DEVICEID_AMD_MISC15 0x1603 86 #define DEVICEID_AMD_MISC16 0x1533 87 #define DEVICEID_AMD_MISC16_M30H 0x1583 88 #define DEVICEID_AMD_MISC17 0x141d 89 #define DEVICEID_AMD_HOSTB17H_ROOT 0x1450 90 #define DEVICEID_AMD_HOSTB17H_DF_F3 0x1463 91 #define DEVICEID_AMD_HOSTB17H_M10H_ROOT 0x15d0 92 #define DEVICEID_AMD_HOSTB17H_M10H_DF_F3 0x15eb 93 94 static struct amdtemp_product { 95 uint16_t amdtemp_vendorid; 96 uint16_t amdtemp_deviceid; 97 } amdtemp_products[] = { 98 { VENDORID_AMD, DEVICEID_AMD_MISC0F }, 99 { VENDORID_AMD, DEVICEID_AMD_MISC10 }, 100 { VENDORID_AMD, DEVICEID_AMD_MISC11 }, 101 { VENDORID_AMD, DEVICEID_AMD_MISC12 }, 102 { VENDORID_AMD, DEVICEID_AMD_MISC14 }, 103 { VENDORID_AMD, DEVICEID_AMD_MISC15 }, 104 { VENDORID_AMD, DEVICEID_AMD_MISC16 }, 105 { VENDORID_AMD, DEVICEID_AMD_MISC16_M30H }, 106 { VENDORID_AMD, DEVICEID_AMD_MISC17 }, 107 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_ROOT }, 108 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M10H_ROOT }, 109 }; 110 111 /* 112 * Reported Temperature Control Register 113 */ 114 #define AMDTEMP_REPTMP_CTRL 0xa4 115 116 /* 117 * Reported Temperature, Family 17h 118 * 119 * According to AMD OSRR for 17H, section 4.2.1, bits 31-21 of this register 120 * provide the current temp. bit 19, when clear, means the temp is reported in 121 * a range 0.."225C" (probable typo for 255C), and when set changes the range 122 * to -49..206C. 123 */ 124 #define AMDTEMP_17H_CUR_TMP 0x59800 125 #define AMDTEMP_17H_CUR_TMP_RANGE_SEL (1 << 19) 126 #define AMDTEMP_17H_CUR_TMP_RANGE_OFF 490 127 128 /* 129 * Thermaltrip Status Register (Family 0Fh only) 130 */ 131 #define AMDTEMP_THERMTP_STAT 0xe4 132 #define AMDTEMP_TTSR_SELCORE 0x04 133 #define AMDTEMP_TTSR_SELSENSOR 0x40 134 135 /* 136 * DRAM Configuration High Register 137 */ 138 #define AMDTEMP_DRAM_CONF_HIGH 0x94 /* Function 2 */ 139 #define AMDTEMP_DRAM_MODE_DDR3 0x0100 140 141 /* 142 * CPU Family/Model Register 143 */ 144 #define AMDTEMP_CPUID 0xfc 145 146 /* 147 * Device methods. 148 */ 149 static void amdtemp_identify(driver_t *driver, device_t parent); 150 static int amdtemp_probe(device_t dev); 151 static int amdtemp_attach(device_t dev); 152 static void amdtemp_intrhook(void *arg); 153 static int amdtemp_detach(device_t dev); 154 static int amdtemp_match(device_t dev); 155 static int32_t amdtemp_gettemp0f(device_t dev, amdsensor_t sensor); 156 static int32_t amdtemp_gettemp(device_t dev, amdsensor_t sensor); 157 static int32_t amdtemp_gettemp17h(device_t dev, amdsensor_t sensor); 158 static int amdtemp_sysctl(SYSCTL_HANDLER_ARGS); 159 160 static device_method_t amdtemp_methods[] = { 161 /* Device interface */ 162 DEVMETHOD(device_identify, amdtemp_identify), 163 DEVMETHOD(device_probe, amdtemp_probe), 164 DEVMETHOD(device_attach, amdtemp_attach), 165 DEVMETHOD(device_detach, amdtemp_detach), 166 167 DEVMETHOD_END 168 }; 169 170 static driver_t amdtemp_driver = { 171 "amdtemp", 172 amdtemp_methods, 173 sizeof(struct amdtemp_softc), 174 }; 175 176 static devclass_t amdtemp_devclass; 177 DRIVER_MODULE(amdtemp, hostb, amdtemp_driver, amdtemp_devclass, NULL, NULL); 178 MODULE_VERSION(amdtemp, 1); 179 MODULE_DEPEND(amdtemp, amdsmn, 1, 1, 1); 180 MODULE_PNP_INFO("U16:vendor;U16:device", pci, amdtemp, amdtemp_products, 181 nitems(amdtemp_products)); 182 183 static int 184 amdtemp_match(device_t dev) 185 { 186 int i; 187 uint16_t vendor, devid; 188 189 vendor = pci_get_vendor(dev); 190 devid = pci_get_device(dev); 191 192 for (i = 0; i < nitems(amdtemp_products); i++) { 193 if (vendor == amdtemp_products[i].amdtemp_vendorid && 194 devid == amdtemp_products[i].amdtemp_deviceid) 195 return (1); 196 } 197 198 return (0); 199 } 200 201 static void 202 amdtemp_identify(driver_t *driver, device_t parent) 203 { 204 device_t child; 205 206 /* Make sure we're not being doubly invoked. */ 207 if (device_find_child(parent, "amdtemp", -1) != NULL) 208 return; 209 210 if (amdtemp_match(parent)) { 211 child = device_add_child(parent, "amdtemp", -1); 212 if (child == NULL) 213 device_printf(parent, "add amdtemp child failed\n"); 214 } 215 } 216 217 static int 218 amdtemp_probe(device_t dev) 219 { 220 uint32_t family, model; 221 222 if (resource_disabled("amdtemp", 0)) 223 return (ENXIO); 224 if (!amdtemp_match(device_get_parent(dev))) 225 return (ENXIO); 226 227 family = CPUID_TO_FAMILY(cpu_id); 228 model = CPUID_TO_MODEL(cpu_id); 229 230 switch (family) { 231 case 0x0f: 232 if ((model == 0x04 && (cpu_id & CPUID_STEPPING) == 0) || 233 (model == 0x05 && (cpu_id & CPUID_STEPPING) <= 1)) 234 return (ENXIO); 235 break; 236 case 0x10: 237 case 0x11: 238 case 0x12: 239 case 0x14: 240 case 0x15: 241 case 0x16: 242 case 0x17: 243 break; 244 default: 245 return (ENXIO); 246 } 247 device_set_desc(dev, "AMD CPU On-Die Thermal Sensors"); 248 249 return (BUS_PROBE_GENERIC); 250 } 251 252 static int 253 amdtemp_attach(device_t dev) 254 { 255 char tn[32]; 256 u_int regs[4]; 257 struct amdtemp_softc *sc = device_get_softc(dev); 258 struct sysctl_ctx_list *sysctlctx; 259 struct sysctl_oid *sysctlnode; 260 uint32_t cpuid, family, model; 261 u_int bid; 262 int erratum319, unit; 263 264 erratum319 = 0; 265 266 /* 267 * CPUID Register is available from Revision F. 268 */ 269 cpuid = cpu_id; 270 family = CPUID_TO_FAMILY(cpuid); 271 model = CPUID_TO_MODEL(cpuid); 272 if ((family != 0x0f || model >= 0x40) && family != 0x17) { 273 cpuid = pci_read_config(dev, AMDTEMP_CPUID, 4); 274 family = CPUID_TO_FAMILY(cpuid); 275 model = CPUID_TO_MODEL(cpuid); 276 } 277 278 switch (family) { 279 case 0x0f: 280 /* 281 * Thermaltrip Status Register 282 * 283 * - ThermSenseCoreSel 284 * 285 * Revision F & G: 0 - Core1, 1 - Core0 286 * Other: 0 - Core0, 1 - Core1 287 * 288 * - CurTmp 289 * 290 * Revision G: bits 23-14 291 * Other: bits 23-16 292 * 293 * XXX According to the BKDG, CurTmp, ThermSenseSel and 294 * ThermSenseCoreSel bits were introduced in Revision F 295 * but CurTmp seems working fine as early as Revision C. 296 * However, it is not clear whether ThermSenseSel and/or 297 * ThermSenseCoreSel work in undocumented cases as well. 298 * In fact, the Linux driver suggests it may not work but 299 * we just assume it does until we find otherwise. 300 * 301 * XXX According to Linux, CurTmp starts at -28C on 302 * Socket AM2 Revision G processors, which is not 303 * documented anywhere. 304 */ 305 if (model >= 0x40) 306 sc->sc_flags |= AMDTEMP_FLAG_CS_SWAP; 307 if (model >= 0x60 && model != 0xc1) { 308 do_cpuid(0x80000001, regs); 309 bid = (regs[1] >> 9) & 0x1f; 310 switch (model) { 311 case 0x68: /* Socket S1g1 */ 312 case 0x6c: 313 case 0x7c: 314 break; 315 case 0x6b: /* Socket AM2 and ASB1 (2 cores) */ 316 if (bid != 0x0b && bid != 0x0c) 317 sc->sc_flags |= 318 AMDTEMP_FLAG_ALT_OFFSET; 319 break; 320 case 0x6f: /* Socket AM2 and ASB1 (1 core) */ 321 case 0x7f: 322 if (bid != 0x07 && bid != 0x09 && 323 bid != 0x0c) 324 sc->sc_flags |= 325 AMDTEMP_FLAG_ALT_OFFSET; 326 break; 327 default: 328 sc->sc_flags |= AMDTEMP_FLAG_ALT_OFFSET; 329 } 330 sc->sc_flags |= AMDTEMP_FLAG_CT_10BIT; 331 } 332 333 /* 334 * There are two sensors per core. 335 */ 336 sc->sc_ntemps = 2; 337 338 sc->sc_gettemp = amdtemp_gettemp0f; 339 break; 340 case 0x10: 341 /* 342 * Erratum 319 Inaccurate Temperature Measurement 343 * 344 * http://support.amd.com/us/Processor_TechDocs/41322.pdf 345 */ 346 do_cpuid(0x80000001, regs); 347 switch ((regs[1] >> 28) & 0xf) { 348 case 0: /* Socket F */ 349 erratum319 = 1; 350 break; 351 case 1: /* Socket AM2+ or AM3 */ 352 if ((pci_cfgregread(pci_get_bus(dev), 353 pci_get_slot(dev), 2, AMDTEMP_DRAM_CONF_HIGH, 2) & 354 AMDTEMP_DRAM_MODE_DDR3) != 0 || model > 0x04 || 355 (model == 0x04 && (cpuid & CPUID_STEPPING) >= 3)) 356 break; 357 /* XXX 00100F42h (RB-C2) exists in both formats. */ 358 erratum319 = 1; 359 break; 360 } 361 /* FALLTHROUGH */ 362 case 0x11: 363 case 0x12: 364 case 0x14: 365 case 0x15: 366 case 0x16: 367 /* 368 * There is only one sensor per package. 369 */ 370 sc->sc_ntemps = 1; 371 372 sc->sc_gettemp = amdtemp_gettemp; 373 break; 374 case 0x17: 375 sc->sc_ntemps = 1; 376 sc->sc_gettemp = amdtemp_gettemp17h; 377 sc->sc_smn = device_find_child( 378 device_get_parent(dev), "amdsmn", -1); 379 if (sc->sc_smn == NULL) { 380 if (bootverbose) 381 device_printf(dev, "No SMN device found\n"); 382 return (ENXIO); 383 } 384 break; 385 } 386 387 /* Find number of cores per package. */ 388 sc->sc_ncores = (amd_feature2 & AMDID2_CMP) != 0 ? 389 (cpu_procinfo2 & AMDID_CMP_CORES) + 1 : 1; 390 if (sc->sc_ncores > MAXCPU) 391 return (ENXIO); 392 393 if (erratum319) 394 device_printf(dev, 395 "Erratum 319: temperature measurement may be inaccurate\n"); 396 if (bootverbose) 397 device_printf(dev, "Found %d cores and %d sensors.\n", 398 sc->sc_ncores, 399 sc->sc_ntemps > 1 ? sc->sc_ntemps * sc->sc_ncores : 1); 400 401 /* 402 * dev.amdtemp.N tree. 403 */ 404 unit = device_get_unit(dev); 405 snprintf(tn, sizeof(tn), "dev.amdtemp.%d.sensor_offset", unit); 406 TUNABLE_INT_FETCH(tn, &sc->sc_offset); 407 408 sysctlctx = device_get_sysctl_ctx(dev); 409 SYSCTL_ADD_INT(sysctlctx, 410 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 411 "sensor_offset", CTLFLAG_RW, &sc->sc_offset, 0, 412 "Temperature sensor offset"); 413 sysctlnode = SYSCTL_ADD_NODE(sysctlctx, 414 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 415 "core0", CTLFLAG_RD, 0, "Core 0"); 416 417 SYSCTL_ADD_PROC(sysctlctx, 418 SYSCTL_CHILDREN(sysctlnode), 419 OID_AUTO, "sensor0", CTLTYPE_INT | CTLFLAG_RD, 420 dev, CORE0_SENSOR0, amdtemp_sysctl, "IK", 421 "Core 0 / Sensor 0 temperature"); 422 423 if (sc->sc_ntemps > 1) { 424 SYSCTL_ADD_PROC(sysctlctx, 425 SYSCTL_CHILDREN(sysctlnode), 426 OID_AUTO, "sensor1", CTLTYPE_INT | CTLFLAG_RD, 427 dev, CORE0_SENSOR1, amdtemp_sysctl, "IK", 428 "Core 0 / Sensor 1 temperature"); 429 430 if (sc->sc_ncores > 1) { 431 sysctlnode = SYSCTL_ADD_NODE(sysctlctx, 432 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 433 OID_AUTO, "core1", CTLFLAG_RD, 0, "Core 1"); 434 435 SYSCTL_ADD_PROC(sysctlctx, 436 SYSCTL_CHILDREN(sysctlnode), 437 OID_AUTO, "sensor0", CTLTYPE_INT | CTLFLAG_RD, 438 dev, CORE1_SENSOR0, amdtemp_sysctl, "IK", 439 "Core 1 / Sensor 0 temperature"); 440 441 SYSCTL_ADD_PROC(sysctlctx, 442 SYSCTL_CHILDREN(sysctlnode), 443 OID_AUTO, "sensor1", CTLTYPE_INT | CTLFLAG_RD, 444 dev, CORE1_SENSOR1, amdtemp_sysctl, "IK", 445 "Core 1 / Sensor 1 temperature"); 446 } 447 } 448 449 /* 450 * Try to create dev.cpu sysctl entries and setup intrhook function. 451 * This is needed because the cpu driver may be loaded late on boot, 452 * after us. 453 */ 454 amdtemp_intrhook(dev); 455 sc->sc_ich.ich_func = amdtemp_intrhook; 456 sc->sc_ich.ich_arg = dev; 457 if (config_intrhook_establish(&sc->sc_ich) != 0) { 458 device_printf(dev, "config_intrhook_establish failed!\n"); 459 return (ENXIO); 460 } 461 462 return (0); 463 } 464 465 void 466 amdtemp_intrhook(void *arg) 467 { 468 struct amdtemp_softc *sc; 469 struct sysctl_ctx_list *sysctlctx; 470 device_t dev = (device_t)arg; 471 device_t acpi, cpu, nexus; 472 amdsensor_t sensor; 473 int i; 474 475 sc = device_get_softc(dev); 476 477 /* 478 * dev.cpu.N.temperature. 479 */ 480 nexus = device_find_child(root_bus, "nexus", 0); 481 acpi = device_find_child(nexus, "acpi", 0); 482 483 for (i = 0; i < sc->sc_ncores; i++) { 484 if (sc->sc_sysctl_cpu[i] != NULL) 485 continue; 486 cpu = device_find_child(acpi, "cpu", 487 device_get_unit(dev) * sc->sc_ncores + i); 488 if (cpu != NULL) { 489 sysctlctx = device_get_sysctl_ctx(cpu); 490 491 sensor = sc->sc_ntemps > 1 ? 492 (i == 0 ? CORE0 : CORE1) : CORE0_SENSOR0; 493 sc->sc_sysctl_cpu[i] = SYSCTL_ADD_PROC(sysctlctx, 494 SYSCTL_CHILDREN(device_get_sysctl_tree(cpu)), 495 OID_AUTO, "temperature", CTLTYPE_INT | CTLFLAG_RD, 496 dev, sensor, amdtemp_sysctl, "IK", 497 "Current temparature"); 498 } 499 } 500 if (sc->sc_ich.ich_arg != NULL) 501 config_intrhook_disestablish(&sc->sc_ich); 502 } 503 504 int 505 amdtemp_detach(device_t dev) 506 { 507 struct amdtemp_softc *sc = device_get_softc(dev); 508 int i; 509 510 for (i = 0; i < sc->sc_ncores; i++) 511 if (sc->sc_sysctl_cpu[i] != NULL) 512 sysctl_remove_oid(sc->sc_sysctl_cpu[i], 1, 0); 513 514 /* NewBus removes the dev.amdtemp.N tree by itself. */ 515 516 return (0); 517 } 518 519 static int 520 amdtemp_sysctl(SYSCTL_HANDLER_ARGS) 521 { 522 device_t dev = (device_t)arg1; 523 struct amdtemp_softc *sc = device_get_softc(dev); 524 amdsensor_t sensor = (amdsensor_t)arg2; 525 int32_t auxtemp[2], temp; 526 int error; 527 528 switch (sensor) { 529 case CORE0: 530 auxtemp[0] = sc->sc_gettemp(dev, CORE0_SENSOR0); 531 auxtemp[1] = sc->sc_gettemp(dev, CORE0_SENSOR1); 532 temp = imax(auxtemp[0], auxtemp[1]); 533 break; 534 case CORE1: 535 auxtemp[0] = sc->sc_gettemp(dev, CORE1_SENSOR0); 536 auxtemp[1] = sc->sc_gettemp(dev, CORE1_SENSOR1); 537 temp = imax(auxtemp[0], auxtemp[1]); 538 break; 539 default: 540 temp = sc->sc_gettemp(dev, sensor); 541 break; 542 } 543 error = sysctl_handle_int(oidp, &temp, 0, req); 544 545 return (error); 546 } 547 548 #define AMDTEMP_ZERO_C_TO_K 2731 549 550 static int32_t 551 amdtemp_gettemp0f(device_t dev, amdsensor_t sensor) 552 { 553 struct amdtemp_softc *sc = device_get_softc(dev); 554 uint32_t mask, offset, temp; 555 556 /* Set Sensor/Core selector. */ 557 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 1); 558 temp &= ~(AMDTEMP_TTSR_SELCORE | AMDTEMP_TTSR_SELSENSOR); 559 switch (sensor) { 560 case CORE0_SENSOR1: 561 temp |= AMDTEMP_TTSR_SELSENSOR; 562 /* FALLTHROUGH */ 563 case CORE0_SENSOR0: 564 case CORE0: 565 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) != 0) 566 temp |= AMDTEMP_TTSR_SELCORE; 567 break; 568 case CORE1_SENSOR1: 569 temp |= AMDTEMP_TTSR_SELSENSOR; 570 /* FALLTHROUGH */ 571 case CORE1_SENSOR0: 572 case CORE1: 573 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) == 0) 574 temp |= AMDTEMP_TTSR_SELCORE; 575 break; 576 } 577 pci_write_config(dev, AMDTEMP_THERMTP_STAT, temp, 1); 578 579 mask = (sc->sc_flags & AMDTEMP_FLAG_CT_10BIT) != 0 ? 0x3ff : 0x3fc; 580 offset = (sc->sc_flags & AMDTEMP_FLAG_ALT_OFFSET) != 0 ? 28 : 49; 581 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 4); 582 temp = ((temp >> 14) & mask) * 5 / 2; 583 temp += AMDTEMP_ZERO_C_TO_K + (sc->sc_offset - offset) * 10; 584 585 return (temp); 586 } 587 588 static int32_t 589 amdtemp_gettemp(device_t dev, amdsensor_t sensor) 590 { 591 struct amdtemp_softc *sc = device_get_softc(dev); 592 uint32_t temp; 593 594 temp = pci_read_config(dev, AMDTEMP_REPTMP_CTRL, 4); 595 temp = ((temp >> 21) & 0x7ff) * 5 / 4; 596 temp += AMDTEMP_ZERO_C_TO_K + sc->sc_offset * 10; 597 598 return (temp); 599 } 600 601 static int32_t 602 amdtemp_gettemp17h(device_t dev, amdsensor_t sensor) 603 { 604 struct amdtemp_softc *sc = device_get_softc(dev); 605 uint32_t temp, val; 606 int error; 607 608 error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CUR_TMP, &val); 609 KASSERT(error == 0, ("amdsmn_read")); 610 611 temp = ((val >> 21) & 0x7ff) * 5 / 4; 612 if ((val & AMDTEMP_17H_CUR_TMP_RANGE_SEL) != 0) 613 temp -= AMDTEMP_17H_CUR_TMP_RANGE_OFF; 614 temp += AMDTEMP_ZERO_C_TO_K + sc->sc_offset * 10; 615 616 return (temp); 617 } 618