1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008, 2009 Rui Paulo <rpaulo@FreeBSD.org> 5 * Copyright (c) 2009 Norikatsu Shigemura <nork@FreeBSD.org> 6 * Copyright (c) 2009-2012 Jung-uk Kim <jkim@FreeBSD.org> 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 20 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 21 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 22 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 23 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 24 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 26 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 27 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 28 * POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * Driver for the AMD CPU on-die thermal sensors. 33 * Initially based on the k8temp Linux driver. 34 */ 35 36 #include <sys/cdefs.h> 37 __FBSDID("$FreeBSD$"); 38 39 #include <sys/param.h> 40 #include <sys/bus.h> 41 #include <sys/conf.h> 42 #include <sys/kernel.h> 43 #include <sys/module.h> 44 #include <sys/sysctl.h> 45 #include <sys/systm.h> 46 47 #include <machine/cpufunc.h> 48 #include <machine/md_var.h> 49 #include <machine/specialreg.h> 50 51 #include <dev/pci/pcivar.h> 52 #include <x86/pci_cfgreg.h> 53 54 #include <dev/amdsmn/amdsmn.h> 55 56 typedef enum { 57 CORE0_SENSOR0, 58 CORE0_SENSOR1, 59 CORE1_SENSOR0, 60 CORE1_SENSOR1, 61 CORE0, 62 CORE1 63 } amdsensor_t; 64 65 struct amdtemp_softc { 66 int sc_ncores; 67 int sc_ntemps; 68 int sc_flags; 69 #define AMDTEMP_FLAG_CS_SWAP 0x01 /* ThermSenseCoreSel is inverted. */ 70 #define AMDTEMP_FLAG_CT_10BIT 0x02 /* CurTmp is 10-bit wide. */ 71 #define AMDTEMP_FLAG_ALT_OFFSET 0x04 /* CurTmp starts at -28C. */ 72 int32_t sc_offset; 73 int32_t (*sc_gettemp)(device_t, amdsensor_t); 74 struct sysctl_oid *sc_sysctl_cpu[MAXCPU]; 75 struct intr_config_hook sc_ich; 76 device_t sc_smn; 77 }; 78 79 #define VENDORID_AMD 0x1022 80 #define DEVICEID_AMD_MISC0F 0x1103 81 #define DEVICEID_AMD_MISC10 0x1203 82 #define DEVICEID_AMD_MISC11 0x1303 83 #define DEVICEID_AMD_MISC12 0x1403 84 #define DEVICEID_AMD_MISC14 0x1703 85 #define DEVICEID_AMD_MISC15 0x1603 86 #define DEVICEID_AMD_MISC16 0x1533 87 #define DEVICEID_AMD_MISC16_M30H 0x1583 88 #define DEVICEID_AMD_MISC17 0x141d 89 #define DEVICEID_AMD_HOSTB17H_ROOT 0x1450 90 #define DEVICEID_AMD_HOSTB17H_DF_F3 0x1463 91 #define DEVICEID_AMD_HOSTB17H_M10H_ROOT 0x15d0 92 #define DEVICEID_AMD_HOSTB17H_M10H_DF_F3 0x15eb 93 94 static struct amdtemp_product { 95 uint16_t amdtemp_vendorid; 96 uint16_t amdtemp_deviceid; 97 } amdtemp_products[] = { 98 { VENDORID_AMD, DEVICEID_AMD_MISC0F }, 99 { VENDORID_AMD, DEVICEID_AMD_MISC10 }, 100 { VENDORID_AMD, DEVICEID_AMD_MISC11 }, 101 { VENDORID_AMD, DEVICEID_AMD_MISC12 }, 102 { VENDORID_AMD, DEVICEID_AMD_MISC14 }, 103 { VENDORID_AMD, DEVICEID_AMD_MISC15 }, 104 { VENDORID_AMD, DEVICEID_AMD_MISC16 }, 105 { VENDORID_AMD, DEVICEID_AMD_MISC16_M30H }, 106 { VENDORID_AMD, DEVICEID_AMD_MISC17 }, 107 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_ROOT }, 108 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M10H_ROOT }, 109 }; 110 111 /* 112 * Reported Temperature Control Register 113 */ 114 #define AMDTEMP_REPTMP_CTRL 0xa4 115 116 /* 117 * Reported Temperature, Family 17h 118 */ 119 #define AMDTEMP_17H_CUR_TMP 0x59800 120 121 /* 122 * Thermaltrip Status Register (Family 0Fh only) 123 */ 124 #define AMDTEMP_THERMTP_STAT 0xe4 125 #define AMDTEMP_TTSR_SELCORE 0x04 126 #define AMDTEMP_TTSR_SELSENSOR 0x40 127 128 /* 129 * DRAM Configuration High Register 130 */ 131 #define AMDTEMP_DRAM_CONF_HIGH 0x94 /* Function 2 */ 132 #define AMDTEMP_DRAM_MODE_DDR3 0x0100 133 134 /* 135 * CPU Family/Model Register 136 */ 137 #define AMDTEMP_CPUID 0xfc 138 139 /* 140 * Device methods. 141 */ 142 static void amdtemp_identify(driver_t *driver, device_t parent); 143 static int amdtemp_probe(device_t dev); 144 static int amdtemp_attach(device_t dev); 145 static void amdtemp_intrhook(void *arg); 146 static int amdtemp_detach(device_t dev); 147 static int amdtemp_match(device_t dev); 148 static int32_t amdtemp_gettemp0f(device_t dev, amdsensor_t sensor); 149 static int32_t amdtemp_gettemp(device_t dev, amdsensor_t sensor); 150 static int32_t amdtemp_gettemp17h(device_t dev, amdsensor_t sensor); 151 static int amdtemp_sysctl(SYSCTL_HANDLER_ARGS); 152 153 static device_method_t amdtemp_methods[] = { 154 /* Device interface */ 155 DEVMETHOD(device_identify, amdtemp_identify), 156 DEVMETHOD(device_probe, amdtemp_probe), 157 DEVMETHOD(device_attach, amdtemp_attach), 158 DEVMETHOD(device_detach, amdtemp_detach), 159 160 DEVMETHOD_END 161 }; 162 163 static driver_t amdtemp_driver = { 164 "amdtemp", 165 amdtemp_methods, 166 sizeof(struct amdtemp_softc), 167 }; 168 169 static devclass_t amdtemp_devclass; 170 DRIVER_MODULE(amdtemp, hostb, amdtemp_driver, amdtemp_devclass, NULL, NULL); 171 MODULE_VERSION(amdtemp, 1); 172 MODULE_DEPEND(amdtemp, amdsmn, 1, 1, 1); 173 MODULE_PNP_INFO("U16:vendor;U16:device", pci, amdtemp, amdtemp_products, 174 nitems(amdtemp_products)); 175 176 static int 177 amdtemp_match(device_t dev) 178 { 179 int i; 180 uint16_t vendor, devid; 181 182 vendor = pci_get_vendor(dev); 183 devid = pci_get_device(dev); 184 185 for (i = 0; i < nitems(amdtemp_products); i++) { 186 if (vendor == amdtemp_products[i].amdtemp_vendorid && 187 devid == amdtemp_products[i].amdtemp_deviceid) 188 return (1); 189 } 190 191 return (0); 192 } 193 194 static void 195 amdtemp_identify(driver_t *driver, device_t parent) 196 { 197 device_t child; 198 199 /* Make sure we're not being doubly invoked. */ 200 if (device_find_child(parent, "amdtemp", -1) != NULL) 201 return; 202 203 if (amdtemp_match(parent)) { 204 child = device_add_child(parent, "amdtemp", -1); 205 if (child == NULL) 206 device_printf(parent, "add amdtemp child failed\n"); 207 } 208 } 209 210 static int 211 amdtemp_probe(device_t dev) 212 { 213 uint32_t family, model; 214 215 if (resource_disabled("amdtemp", 0)) 216 return (ENXIO); 217 if (!amdtemp_match(device_get_parent(dev))) 218 return (ENXIO); 219 220 family = CPUID_TO_FAMILY(cpu_id); 221 model = CPUID_TO_MODEL(cpu_id); 222 223 switch (family) { 224 case 0x0f: 225 if ((model == 0x04 && (cpu_id & CPUID_STEPPING) == 0) || 226 (model == 0x05 && (cpu_id & CPUID_STEPPING) <= 1)) 227 return (ENXIO); 228 break; 229 case 0x10: 230 case 0x11: 231 case 0x12: 232 case 0x14: 233 case 0x15: 234 case 0x16: 235 case 0x17: 236 break; 237 default: 238 return (ENXIO); 239 } 240 device_set_desc(dev, "AMD CPU On-Die Thermal Sensors"); 241 242 return (BUS_PROBE_GENERIC); 243 } 244 245 static int 246 amdtemp_attach(device_t dev) 247 { 248 char tn[32]; 249 u_int regs[4]; 250 struct amdtemp_softc *sc = device_get_softc(dev); 251 struct sysctl_ctx_list *sysctlctx; 252 struct sysctl_oid *sysctlnode; 253 uint32_t cpuid, family, model; 254 u_int bid; 255 int erratum319, unit; 256 257 erratum319 = 0; 258 259 /* 260 * CPUID Register is available from Revision F. 261 */ 262 cpuid = cpu_id; 263 family = CPUID_TO_FAMILY(cpuid); 264 model = CPUID_TO_MODEL(cpuid); 265 if ((family != 0x0f || model >= 0x40) && family != 0x17) { 266 cpuid = pci_read_config(dev, AMDTEMP_CPUID, 4); 267 family = CPUID_TO_FAMILY(cpuid); 268 model = CPUID_TO_MODEL(cpuid); 269 } 270 271 switch (family) { 272 case 0x0f: 273 /* 274 * Thermaltrip Status Register 275 * 276 * - ThermSenseCoreSel 277 * 278 * Revision F & G: 0 - Core1, 1 - Core0 279 * Other: 0 - Core0, 1 - Core1 280 * 281 * - CurTmp 282 * 283 * Revision G: bits 23-14 284 * Other: bits 23-16 285 * 286 * XXX According to the BKDG, CurTmp, ThermSenseSel and 287 * ThermSenseCoreSel bits were introduced in Revision F 288 * but CurTmp seems working fine as early as Revision C. 289 * However, it is not clear whether ThermSenseSel and/or 290 * ThermSenseCoreSel work in undocumented cases as well. 291 * In fact, the Linux driver suggests it may not work but 292 * we just assume it does until we find otherwise. 293 * 294 * XXX According to Linux, CurTmp starts at -28C on 295 * Socket AM2 Revision G processors, which is not 296 * documented anywhere. 297 */ 298 if (model >= 0x40) 299 sc->sc_flags |= AMDTEMP_FLAG_CS_SWAP; 300 if (model >= 0x60 && model != 0xc1) { 301 do_cpuid(0x80000001, regs); 302 bid = (regs[1] >> 9) & 0x1f; 303 switch (model) { 304 case 0x68: /* Socket S1g1 */ 305 case 0x6c: 306 case 0x7c: 307 break; 308 case 0x6b: /* Socket AM2 and ASB1 (2 cores) */ 309 if (bid != 0x0b && bid != 0x0c) 310 sc->sc_flags |= 311 AMDTEMP_FLAG_ALT_OFFSET; 312 break; 313 case 0x6f: /* Socket AM2 and ASB1 (1 core) */ 314 case 0x7f: 315 if (bid != 0x07 && bid != 0x09 && 316 bid != 0x0c) 317 sc->sc_flags |= 318 AMDTEMP_FLAG_ALT_OFFSET; 319 break; 320 default: 321 sc->sc_flags |= AMDTEMP_FLAG_ALT_OFFSET; 322 } 323 sc->sc_flags |= AMDTEMP_FLAG_CT_10BIT; 324 } 325 326 /* 327 * There are two sensors per core. 328 */ 329 sc->sc_ntemps = 2; 330 331 sc->sc_gettemp = amdtemp_gettemp0f; 332 break; 333 case 0x10: 334 /* 335 * Erratum 319 Inaccurate Temperature Measurement 336 * 337 * http://support.amd.com/us/Processor_TechDocs/41322.pdf 338 */ 339 do_cpuid(0x80000001, regs); 340 switch ((regs[1] >> 28) & 0xf) { 341 case 0: /* Socket F */ 342 erratum319 = 1; 343 break; 344 case 1: /* Socket AM2+ or AM3 */ 345 if ((pci_cfgregread(pci_get_bus(dev), 346 pci_get_slot(dev), 2, AMDTEMP_DRAM_CONF_HIGH, 2) & 347 AMDTEMP_DRAM_MODE_DDR3) != 0 || model > 0x04 || 348 (model == 0x04 && (cpuid & CPUID_STEPPING) >= 3)) 349 break; 350 /* XXX 00100F42h (RB-C2) exists in both formats. */ 351 erratum319 = 1; 352 break; 353 } 354 /* FALLTHROUGH */ 355 case 0x11: 356 case 0x12: 357 case 0x14: 358 case 0x15: 359 case 0x16: 360 /* 361 * There is only one sensor per package. 362 */ 363 sc->sc_ntemps = 1; 364 365 sc->sc_gettemp = amdtemp_gettemp; 366 break; 367 case 0x17: 368 sc->sc_ntemps = 1; 369 sc->sc_gettemp = amdtemp_gettemp17h; 370 sc->sc_smn = device_find_child( 371 device_get_parent(dev), "amdsmn", -1); 372 if (sc->sc_smn == NULL) { 373 if (bootverbose) 374 device_printf(dev, "No SMN device found\n"); 375 return (ENXIO); 376 } 377 break; 378 } 379 380 /* Find number of cores per package. */ 381 sc->sc_ncores = (amd_feature2 & AMDID2_CMP) != 0 ? 382 (cpu_procinfo2 & AMDID_CMP_CORES) + 1 : 1; 383 if (sc->sc_ncores > MAXCPU) 384 return (ENXIO); 385 386 if (erratum319) 387 device_printf(dev, 388 "Erratum 319: temperature measurement may be inaccurate\n"); 389 if (bootverbose) 390 device_printf(dev, "Found %d cores and %d sensors.\n", 391 sc->sc_ncores, 392 sc->sc_ntemps > 1 ? sc->sc_ntemps * sc->sc_ncores : 1); 393 394 /* 395 * dev.amdtemp.N tree. 396 */ 397 unit = device_get_unit(dev); 398 snprintf(tn, sizeof(tn), "dev.amdtemp.%d.sensor_offset", unit); 399 TUNABLE_INT_FETCH(tn, &sc->sc_offset); 400 401 sysctlctx = device_get_sysctl_ctx(dev); 402 SYSCTL_ADD_INT(sysctlctx, 403 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 404 "sensor_offset", CTLFLAG_RW, &sc->sc_offset, 0, 405 "Temperature sensor offset"); 406 sysctlnode = SYSCTL_ADD_NODE(sysctlctx, 407 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 408 "core0", CTLFLAG_RD, 0, "Core 0"); 409 410 SYSCTL_ADD_PROC(sysctlctx, 411 SYSCTL_CHILDREN(sysctlnode), 412 OID_AUTO, "sensor0", CTLTYPE_INT | CTLFLAG_RD, 413 dev, CORE0_SENSOR0, amdtemp_sysctl, "IK", 414 "Core 0 / Sensor 0 temperature"); 415 416 if (sc->sc_ntemps > 1) { 417 SYSCTL_ADD_PROC(sysctlctx, 418 SYSCTL_CHILDREN(sysctlnode), 419 OID_AUTO, "sensor1", CTLTYPE_INT | CTLFLAG_RD, 420 dev, CORE0_SENSOR1, amdtemp_sysctl, "IK", 421 "Core 0 / Sensor 1 temperature"); 422 423 if (sc->sc_ncores > 1) { 424 sysctlnode = SYSCTL_ADD_NODE(sysctlctx, 425 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 426 OID_AUTO, "core1", CTLFLAG_RD, 0, "Core 1"); 427 428 SYSCTL_ADD_PROC(sysctlctx, 429 SYSCTL_CHILDREN(sysctlnode), 430 OID_AUTO, "sensor0", CTLTYPE_INT | CTLFLAG_RD, 431 dev, CORE1_SENSOR0, amdtemp_sysctl, "IK", 432 "Core 1 / Sensor 0 temperature"); 433 434 SYSCTL_ADD_PROC(sysctlctx, 435 SYSCTL_CHILDREN(sysctlnode), 436 OID_AUTO, "sensor1", CTLTYPE_INT | CTLFLAG_RD, 437 dev, CORE1_SENSOR1, amdtemp_sysctl, "IK", 438 "Core 1 / Sensor 1 temperature"); 439 } 440 } 441 442 /* 443 * Try to create dev.cpu sysctl entries and setup intrhook function. 444 * This is needed because the cpu driver may be loaded late on boot, 445 * after us. 446 */ 447 amdtemp_intrhook(dev); 448 sc->sc_ich.ich_func = amdtemp_intrhook; 449 sc->sc_ich.ich_arg = dev; 450 if (config_intrhook_establish(&sc->sc_ich) != 0) { 451 device_printf(dev, "config_intrhook_establish failed!\n"); 452 return (ENXIO); 453 } 454 455 return (0); 456 } 457 458 void 459 amdtemp_intrhook(void *arg) 460 { 461 struct amdtemp_softc *sc; 462 struct sysctl_ctx_list *sysctlctx; 463 device_t dev = (device_t)arg; 464 device_t acpi, cpu, nexus; 465 amdsensor_t sensor; 466 int i; 467 468 sc = device_get_softc(dev); 469 470 /* 471 * dev.cpu.N.temperature. 472 */ 473 nexus = device_find_child(root_bus, "nexus", 0); 474 acpi = device_find_child(nexus, "acpi", 0); 475 476 for (i = 0; i < sc->sc_ncores; i++) { 477 if (sc->sc_sysctl_cpu[i] != NULL) 478 continue; 479 cpu = device_find_child(acpi, "cpu", 480 device_get_unit(dev) * sc->sc_ncores + i); 481 if (cpu != NULL) { 482 sysctlctx = device_get_sysctl_ctx(cpu); 483 484 sensor = sc->sc_ntemps > 1 ? 485 (i == 0 ? CORE0 : CORE1) : CORE0_SENSOR0; 486 sc->sc_sysctl_cpu[i] = SYSCTL_ADD_PROC(sysctlctx, 487 SYSCTL_CHILDREN(device_get_sysctl_tree(cpu)), 488 OID_AUTO, "temperature", CTLTYPE_INT | CTLFLAG_RD, 489 dev, sensor, amdtemp_sysctl, "IK", 490 "Current temparature"); 491 } 492 } 493 if (sc->sc_ich.ich_arg != NULL) 494 config_intrhook_disestablish(&sc->sc_ich); 495 } 496 497 int 498 amdtemp_detach(device_t dev) 499 { 500 struct amdtemp_softc *sc = device_get_softc(dev); 501 int i; 502 503 for (i = 0; i < sc->sc_ncores; i++) 504 if (sc->sc_sysctl_cpu[i] != NULL) 505 sysctl_remove_oid(sc->sc_sysctl_cpu[i], 1, 0); 506 507 /* NewBus removes the dev.amdtemp.N tree by itself. */ 508 509 return (0); 510 } 511 512 static int 513 amdtemp_sysctl(SYSCTL_HANDLER_ARGS) 514 { 515 device_t dev = (device_t)arg1; 516 struct amdtemp_softc *sc = device_get_softc(dev); 517 amdsensor_t sensor = (amdsensor_t)arg2; 518 int32_t auxtemp[2], temp; 519 int error; 520 521 switch (sensor) { 522 case CORE0: 523 auxtemp[0] = sc->sc_gettemp(dev, CORE0_SENSOR0); 524 auxtemp[1] = sc->sc_gettemp(dev, CORE0_SENSOR1); 525 temp = imax(auxtemp[0], auxtemp[1]); 526 break; 527 case CORE1: 528 auxtemp[0] = sc->sc_gettemp(dev, CORE1_SENSOR0); 529 auxtemp[1] = sc->sc_gettemp(dev, CORE1_SENSOR1); 530 temp = imax(auxtemp[0], auxtemp[1]); 531 break; 532 default: 533 temp = sc->sc_gettemp(dev, sensor); 534 break; 535 } 536 error = sysctl_handle_int(oidp, &temp, 0, req); 537 538 return (error); 539 } 540 541 #define AMDTEMP_ZERO_C_TO_K 2731 542 543 static int32_t 544 amdtemp_gettemp0f(device_t dev, amdsensor_t sensor) 545 { 546 struct amdtemp_softc *sc = device_get_softc(dev); 547 uint32_t mask, offset, temp; 548 549 /* Set Sensor/Core selector. */ 550 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 1); 551 temp &= ~(AMDTEMP_TTSR_SELCORE | AMDTEMP_TTSR_SELSENSOR); 552 switch (sensor) { 553 case CORE0_SENSOR1: 554 temp |= AMDTEMP_TTSR_SELSENSOR; 555 /* FALLTHROUGH */ 556 case CORE0_SENSOR0: 557 case CORE0: 558 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) != 0) 559 temp |= AMDTEMP_TTSR_SELCORE; 560 break; 561 case CORE1_SENSOR1: 562 temp |= AMDTEMP_TTSR_SELSENSOR; 563 /* FALLTHROUGH */ 564 case CORE1_SENSOR0: 565 case CORE1: 566 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) == 0) 567 temp |= AMDTEMP_TTSR_SELCORE; 568 break; 569 } 570 pci_write_config(dev, AMDTEMP_THERMTP_STAT, temp, 1); 571 572 mask = (sc->sc_flags & AMDTEMP_FLAG_CT_10BIT) != 0 ? 0x3ff : 0x3fc; 573 offset = (sc->sc_flags & AMDTEMP_FLAG_ALT_OFFSET) != 0 ? 28 : 49; 574 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 4); 575 temp = ((temp >> 14) & mask) * 5 / 2; 576 temp += AMDTEMP_ZERO_C_TO_K + (sc->sc_offset - offset) * 10; 577 578 return (temp); 579 } 580 581 static int32_t 582 amdtemp_gettemp(device_t dev, amdsensor_t sensor) 583 { 584 struct amdtemp_softc *sc = device_get_softc(dev); 585 uint32_t temp; 586 587 temp = pci_read_config(dev, AMDTEMP_REPTMP_CTRL, 4); 588 temp = ((temp >> 21) & 0x7ff) * 5 / 4; 589 temp += AMDTEMP_ZERO_C_TO_K + sc->sc_offset * 10; 590 591 return (temp); 592 } 593 594 static int32_t 595 amdtemp_gettemp17h(device_t dev, amdsensor_t sensor) 596 { 597 struct amdtemp_softc *sc = device_get_softc(dev); 598 uint32_t temp; 599 int error; 600 601 error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CUR_TMP, &temp); 602 KASSERT(error == 0, ("amdsmn_read")); 603 604 temp = ((temp >> 21) & 0x7ff) * 5 / 4; 605 temp += AMDTEMP_ZERO_C_TO_K + sc->sc_offset * 10; 606 607 return (temp); 608 } 609