xref: /freebsd/sys/dev/amdtemp/amdtemp.c (revision 681ce946f33e75c590e97c53076e86dff1fe8f4a)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 2008, 2009 Rui Paulo <rpaulo@FreeBSD.org>
5  * Copyright (c) 2009 Norikatsu Shigemura <nork@FreeBSD.org>
6  * Copyright (c) 2009-2012 Jung-uk Kim <jkim@FreeBSD.org>
7  * All rights reserved.
8  * Copyright (c) 2017-2020 Conrad Meyer <cem@FreeBSD.org>. All rights reserved.
9  *
10  * Redistribution and use in source and binary forms, with or without
11  * modification, are permitted provided that the following conditions
12  * are met:
13  * 1. Redistributions of source code must retain the above copyright
14  *    notice, this list of conditions and the following disclaimer.
15  * 2. Redistributions in binary form must reproduce the above copyright
16  *    notice, this list of conditions and the following disclaimer in the
17  *    documentation and/or other materials provided with the distribution.
18  *
19  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
20  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
21  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
23  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
25  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
27  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
28  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
29  * POSSIBILITY OF SUCH DAMAGE.
30  */
31 
32 /*
33  * Driver for the AMD CPU on-die thermal sensors.
34  * Initially based on the k8temp Linux driver.
35  */
36 
37 #include <sys/cdefs.h>
38 __FBSDID("$FreeBSD$");
39 
40 #include <sys/param.h>
41 #include <sys/bus.h>
42 #include <sys/conf.h>
43 #include <sys/kernel.h>
44 #include <sys/module.h>
45 #include <sys/sysctl.h>
46 #include <sys/systm.h>
47 
48 #include <machine/cpufunc.h>
49 #include <machine/md_var.h>
50 #include <machine/specialreg.h>
51 
52 #include <dev/pci/pcivar.h>
53 #include <x86/pci_cfgreg.h>
54 
55 #include <dev/amdsmn/amdsmn.h>
56 
57 typedef enum {
58 	CORE0_SENSOR0,
59 	CORE0_SENSOR1,
60 	CORE1_SENSOR0,
61 	CORE1_SENSOR1,
62 	CORE0,
63 	CORE1,
64 	CCD1,
65 	CCD_BASE = CCD1,
66 	CCD2,
67 	CCD3,
68 	CCD4,
69 	CCD5,
70 	CCD6,
71 	CCD7,
72 	CCD8,
73 	CCD_MAX = CCD8,
74 	NUM_CCDS = CCD_MAX - CCD_BASE + 1,
75 } amdsensor_t;
76 
77 struct amdtemp_softc {
78 	int		sc_ncores;
79 	int		sc_ntemps;
80 	int		sc_flags;
81 #define	AMDTEMP_FLAG_CS_SWAP	0x01	/* ThermSenseCoreSel is inverted. */
82 #define	AMDTEMP_FLAG_CT_10BIT	0x02	/* CurTmp is 10-bit wide. */
83 #define	AMDTEMP_FLAG_ALT_OFFSET	0x04	/* CurTmp starts at -28C. */
84 	int32_t		sc_offset;
85 	int32_t		(*sc_gettemp)(device_t, amdsensor_t);
86 	struct sysctl_oid *sc_sysctl_cpu[MAXCPU];
87 	struct intr_config_hook sc_ich;
88 	device_t	sc_smn;
89 };
90 
91 /*
92  * N.B. The numbers in macro names below are significant and represent CPU
93  * family and model numbers.  Do not make up fictitious family or model numbers
94  * when adding support for new devices.
95  */
96 #define	VENDORID_AMD		0x1022
97 #define	DEVICEID_AMD_MISC0F	0x1103
98 #define	DEVICEID_AMD_MISC10	0x1203
99 #define	DEVICEID_AMD_MISC11	0x1303
100 #define	DEVICEID_AMD_MISC14	0x1703
101 #define	DEVICEID_AMD_MISC15	0x1603
102 #define	DEVICEID_AMD_MISC15_M10H	0x1403
103 #define	DEVICEID_AMD_MISC15_M30H	0x141d
104 #define	DEVICEID_AMD_MISC15_M60H_ROOT	0x1576
105 #define	DEVICEID_AMD_MISC16	0x1533
106 #define	DEVICEID_AMD_MISC16_M30H	0x1583
107 #define	DEVICEID_AMD_HOSTB17H_ROOT	0x1450
108 #define	DEVICEID_AMD_HOSTB17H_M10H_ROOT	0x15d0
109 #define	DEVICEID_AMD_HOSTB17H_M30H_ROOT	0x1480	/* Also M70H, F19H M00H/M20H */
110 #define	DEVICEID_AMD_HOSTB17H_M60H_ROOT	0x1630
111 
112 static const struct amdtemp_product {
113 	uint16_t	amdtemp_vendorid;
114 	uint16_t	amdtemp_deviceid;
115 	/*
116 	 * 0xFC register is only valid on the D18F3 PCI device; SMN temp
117 	 * drivers do not attach to that device.
118 	 */
119 	bool		amdtemp_has_cpuid;
120 } amdtemp_products[] = {
121 	{ VENDORID_AMD,	DEVICEID_AMD_MISC0F, true },
122 	{ VENDORID_AMD,	DEVICEID_AMD_MISC10, true },
123 	{ VENDORID_AMD,	DEVICEID_AMD_MISC11, true },
124 	{ VENDORID_AMD,	DEVICEID_AMD_MISC14, true },
125 	{ VENDORID_AMD,	DEVICEID_AMD_MISC15, true },
126 	{ VENDORID_AMD,	DEVICEID_AMD_MISC15_M10H, true },
127 	{ VENDORID_AMD,	DEVICEID_AMD_MISC15_M30H, true },
128 	{ VENDORID_AMD,	DEVICEID_AMD_MISC15_M60H_ROOT, false },
129 	{ VENDORID_AMD,	DEVICEID_AMD_MISC16, true },
130 	{ VENDORID_AMD,	DEVICEID_AMD_MISC16_M30H, true },
131 	{ VENDORID_AMD,	DEVICEID_AMD_HOSTB17H_ROOT, false },
132 	{ VENDORID_AMD,	DEVICEID_AMD_HOSTB17H_M10H_ROOT, false },
133 	{ VENDORID_AMD,	DEVICEID_AMD_HOSTB17H_M30H_ROOT, false },
134 	{ VENDORID_AMD,	DEVICEID_AMD_HOSTB17H_M60H_ROOT, false },
135 };
136 
137 /*
138  * Reported Temperature Control Register, family 0Fh-15h (some models), 16h.
139  */
140 #define	AMDTEMP_REPTMP_CTRL	0xa4
141 
142 #define	AMDTEMP_REPTMP10H_CURTMP_MASK	0x7ff
143 #define	AMDTEMP_REPTMP10H_CURTMP_SHIFT	21
144 #define	AMDTEMP_REPTMP10H_TJSEL_MASK	0x3
145 #define	AMDTEMP_REPTMP10H_TJSEL_SHIFT	16
146 
147 /*
148  * Reported Temperature, Family 15h, M60+
149  *
150  * Same register bit definitions as other Family 15h CPUs, but access is
151  * indirect via SMN, like Family 17h.
152  */
153 #define	AMDTEMP_15H_M60H_REPTMP_CTRL	0xd8200ca4
154 
155 /*
156  * Reported Temperature, Family 17h
157  *
158  * According to AMD OSRR for 17H, section 4.2.1, bits 31-21 of this register
159  * provide the current temp.  bit 19, when clear, means the temp is reported in
160  * a range 0.."225C" (probable typo for 255C), and when set changes the range
161  * to -49..206C.
162  */
163 #define	AMDTEMP_17H_CUR_TMP		0x59800
164 #define	AMDTEMP_17H_CUR_TMP_RANGE_SEL	(1u << 19)
165 /*
166  * The following register set was discovered experimentally by Ondrej Čerman
167  * and collaborators, but is not (yet) documented in a PPR/OSRR (other than
168  * the M70H PPR SMN memory map showing [0x59800, +0x314] as allocated to
169  * SMU::THM).  It seems plausible and the Linux sensor folks have adopted it.
170  */
171 #define	AMDTEMP_17H_CCD_TMP_BASE	0x59954
172 #define	AMDTEMP_17H_CCD_TMP_VALID	(1u << 11)
173 
174 /*
175  * AMD temperature range adjustment, in deciKelvins (i.e., 49.0 Celsius).
176  */
177 #define	AMDTEMP_CURTMP_RANGE_ADJUST	490
178 
179 /*
180  * Thermaltrip Status Register (Family 0Fh only)
181  */
182 #define	AMDTEMP_THERMTP_STAT	0xe4
183 #define	AMDTEMP_TTSR_SELCORE	0x04
184 #define	AMDTEMP_TTSR_SELSENSOR	0x40
185 
186 /*
187  * DRAM Configuration High Register
188  */
189 #define	AMDTEMP_DRAM_CONF_HIGH	0x94	/* Function 2 */
190 #define	AMDTEMP_DRAM_MODE_DDR3	0x0100
191 
192 /*
193  * CPU Family/Model Register
194  */
195 #define	AMDTEMP_CPUID		0xfc
196 
197 /*
198  * Device methods.
199  */
200 static void 	amdtemp_identify(driver_t *driver, device_t parent);
201 static int	amdtemp_probe(device_t dev);
202 static int	amdtemp_attach(device_t dev);
203 static void	amdtemp_intrhook(void *arg);
204 static int	amdtemp_detach(device_t dev);
205 static int32_t	amdtemp_gettemp0f(device_t dev, amdsensor_t sensor);
206 static int32_t	amdtemp_gettemp(device_t dev, amdsensor_t sensor);
207 static int32_t	amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor);
208 static int32_t	amdtemp_gettemp17h(device_t dev, amdsensor_t sensor);
209 static void	amdtemp_probe_ccd_sensors17h(device_t dev, uint32_t model);
210 static void	amdtemp_probe_ccd_sensors19h(device_t dev, uint32_t model);
211 static int	amdtemp_sysctl(SYSCTL_HANDLER_ARGS);
212 
213 static device_method_t amdtemp_methods[] = {
214 	/* Device interface */
215 	DEVMETHOD(device_identify,	amdtemp_identify),
216 	DEVMETHOD(device_probe,		amdtemp_probe),
217 	DEVMETHOD(device_attach,	amdtemp_attach),
218 	DEVMETHOD(device_detach,	amdtemp_detach),
219 
220 	DEVMETHOD_END
221 };
222 
223 static driver_t amdtemp_driver = {
224 	"amdtemp",
225 	amdtemp_methods,
226 	sizeof(struct amdtemp_softc),
227 };
228 
229 static devclass_t amdtemp_devclass;
230 DRIVER_MODULE(amdtemp, hostb, amdtemp_driver, amdtemp_devclass, NULL, NULL);
231 MODULE_VERSION(amdtemp, 1);
232 MODULE_DEPEND(amdtemp, amdsmn, 1, 1, 1);
233 MODULE_PNP_INFO("U16:vendor;U16:device", pci, amdtemp, amdtemp_products,
234     nitems(amdtemp_products));
235 
236 static bool
237 amdtemp_match(device_t dev, const struct amdtemp_product **product_out)
238 {
239 	int i;
240 	uint16_t vendor, devid;
241 
242 	vendor = pci_get_vendor(dev);
243 	devid = pci_get_device(dev);
244 
245 	for (i = 0; i < nitems(amdtemp_products); i++) {
246 		if (vendor == amdtemp_products[i].amdtemp_vendorid &&
247 		    devid == amdtemp_products[i].amdtemp_deviceid) {
248 			if (product_out != NULL)
249 				*product_out = &amdtemp_products[i];
250 			return (true);
251 		}
252 	}
253 	return (false);
254 }
255 
256 static void
257 amdtemp_identify(driver_t *driver, device_t parent)
258 {
259 	device_t child;
260 
261 	/* Make sure we're not being doubly invoked. */
262 	if (device_find_child(parent, "amdtemp", -1) != NULL)
263 		return;
264 
265 	if (amdtemp_match(parent, NULL)) {
266 		child = device_add_child(parent, "amdtemp", -1);
267 		if (child == NULL)
268 			device_printf(parent, "add amdtemp child failed\n");
269 	}
270 }
271 
272 static int
273 amdtemp_probe(device_t dev)
274 {
275 	uint32_t family, model;
276 
277 	if (resource_disabled("amdtemp", 0))
278 		return (ENXIO);
279 	if (!amdtemp_match(device_get_parent(dev), NULL))
280 		return (ENXIO);
281 
282 	family = CPUID_TO_FAMILY(cpu_id);
283 	model = CPUID_TO_MODEL(cpu_id);
284 
285 	switch (family) {
286 	case 0x0f:
287 		if ((model == 0x04 && (cpu_id & CPUID_STEPPING) == 0) ||
288 		    (model == 0x05 && (cpu_id & CPUID_STEPPING) <= 1))
289 			return (ENXIO);
290 		break;
291 	case 0x10:
292 	case 0x11:
293 	case 0x12:
294 	case 0x14:
295 	case 0x15:
296 	case 0x16:
297 	case 0x17:
298 	case 0x19:
299 		break;
300 	default:
301 		return (ENXIO);
302 	}
303 	device_set_desc(dev, "AMD CPU On-Die Thermal Sensors");
304 
305 	return (BUS_PROBE_GENERIC);
306 }
307 
308 static int
309 amdtemp_attach(device_t dev)
310 {
311 	char tn[32];
312 	u_int regs[4];
313 	const struct amdtemp_product *product;
314 	struct amdtemp_softc *sc;
315 	struct sysctl_ctx_list *sysctlctx;
316 	struct sysctl_oid *sysctlnode;
317 	uint32_t cpuid, family, model;
318 	u_int bid;
319 	int erratum319, unit;
320 	bool needsmn;
321 
322 	sc = device_get_softc(dev);
323 	erratum319 = 0;
324 	needsmn = false;
325 
326 	if (!amdtemp_match(device_get_parent(dev), &product))
327 		return (ENXIO);
328 
329 	cpuid = cpu_id;
330 	family = CPUID_TO_FAMILY(cpuid);
331 	model = CPUID_TO_MODEL(cpuid);
332 
333 	/*
334 	 * This checks for the byzantine condition of running a heterogenous
335 	 * revision multi-socket system where the attach thread is potentially
336 	 * probing a remote socket's PCI device.
337 	 *
338 	 * Currently, such scenarios are unsupported on models using the SMN
339 	 * (because on those models, amdtemp(4) attaches to a different PCI
340 	 * device than the one that contains AMDTEMP_CPUID).
341 	 *
342 	 * The ancient 0x0F family of devices only supports this register from
343 	 * models 40h+.
344 	 */
345 	if (product->amdtemp_has_cpuid && (family > 0x0f ||
346 	    (family == 0x0f && model >= 0x40))) {
347 		cpuid = pci_read_config(device_get_parent(dev), AMDTEMP_CPUID,
348 		    4);
349 		family = CPUID_TO_FAMILY(cpuid);
350 		model = CPUID_TO_MODEL(cpuid);
351 	}
352 
353 	switch (family) {
354 	case 0x0f:
355 		/*
356 		 * Thermaltrip Status Register
357 		 *
358 		 * - ThermSenseCoreSel
359 		 *
360 		 * Revision F & G:	0 - Core1, 1 - Core0
361 		 * Other:		0 - Core0, 1 - Core1
362 		 *
363 		 * - CurTmp
364 		 *
365 		 * Revision G:		bits 23-14
366 		 * Other:		bits 23-16
367 		 *
368 		 * XXX According to the BKDG, CurTmp, ThermSenseSel and
369 		 * ThermSenseCoreSel bits were introduced in Revision F
370 		 * but CurTmp seems working fine as early as Revision C.
371 		 * However, it is not clear whether ThermSenseSel and/or
372 		 * ThermSenseCoreSel work in undocumented cases as well.
373 		 * In fact, the Linux driver suggests it may not work but
374 		 * we just assume it does until we find otherwise.
375 		 *
376 		 * XXX According to Linux, CurTmp starts at -28C on
377 		 * Socket AM2 Revision G processors, which is not
378 		 * documented anywhere.
379 		 */
380 		if (model >= 0x40)
381 			sc->sc_flags |= AMDTEMP_FLAG_CS_SWAP;
382 		if (model >= 0x60 && model != 0xc1) {
383 			do_cpuid(0x80000001, regs);
384 			bid = (regs[1] >> 9) & 0x1f;
385 			switch (model) {
386 			case 0x68: /* Socket S1g1 */
387 			case 0x6c:
388 			case 0x7c:
389 				break;
390 			case 0x6b: /* Socket AM2 and ASB1 (2 cores) */
391 				if (bid != 0x0b && bid != 0x0c)
392 					sc->sc_flags |=
393 					    AMDTEMP_FLAG_ALT_OFFSET;
394 				break;
395 			case 0x6f: /* Socket AM2 and ASB1 (1 core) */
396 			case 0x7f:
397 				if (bid != 0x07 && bid != 0x09 &&
398 				    bid != 0x0c)
399 					sc->sc_flags |=
400 					    AMDTEMP_FLAG_ALT_OFFSET;
401 				break;
402 			default:
403 				sc->sc_flags |= AMDTEMP_FLAG_ALT_OFFSET;
404 			}
405 			sc->sc_flags |= AMDTEMP_FLAG_CT_10BIT;
406 		}
407 
408 		/*
409 		 * There are two sensors per core.
410 		 */
411 		sc->sc_ntemps = 2;
412 
413 		sc->sc_gettemp = amdtemp_gettemp0f;
414 		break;
415 	case 0x10:
416 		/*
417 		 * Erratum 319 Inaccurate Temperature Measurement
418 		 *
419 		 * http://support.amd.com/us/Processor_TechDocs/41322.pdf
420 		 */
421 		do_cpuid(0x80000001, regs);
422 		switch ((regs[1] >> 28) & 0xf) {
423 		case 0:	/* Socket F */
424 			erratum319 = 1;
425 			break;
426 		case 1:	/* Socket AM2+ or AM3 */
427 			if ((pci_cfgregread(pci_get_bus(dev),
428 			    pci_get_slot(dev), 2, AMDTEMP_DRAM_CONF_HIGH, 2) &
429 			    AMDTEMP_DRAM_MODE_DDR3) != 0 || model > 0x04 ||
430 			    (model == 0x04 && (cpuid & CPUID_STEPPING) >= 3))
431 				break;
432 			/* XXX 00100F42h (RB-C2) exists in both formats. */
433 			erratum319 = 1;
434 			break;
435 		}
436 		/* FALLTHROUGH */
437 	case 0x11:
438 	case 0x12:
439 	case 0x14:
440 	case 0x15:
441 	case 0x16:
442 		sc->sc_ntemps = 1;
443 		/*
444 		 * Some later (60h+) models of family 15h use a similar SMN
445 		 * network as family 17h.  (However, the register index differs
446 		 * from 17h and the decoding matches other 10h-15h models,
447 		 * which differ from 17h.)
448 		 */
449 		if (family == 0x15 && model >= 0x60) {
450 			sc->sc_gettemp = amdtemp_gettemp15hm60h;
451 			needsmn = true;
452 		} else
453 			sc->sc_gettemp = amdtemp_gettemp;
454 		break;
455 	case 0x17:
456 	case 0x19:
457 		sc->sc_ntemps = 1;
458 		sc->sc_gettemp = amdtemp_gettemp17h;
459 		needsmn = true;
460 		break;
461 	default:
462 		device_printf(dev, "Bogus family 0x%x\n", family);
463 		return (ENXIO);
464 	}
465 
466 	if (needsmn) {
467 		sc->sc_smn = device_find_child(
468 		    device_get_parent(dev), "amdsmn", -1);
469 		if (sc->sc_smn == NULL) {
470 			if (bootverbose)
471 				device_printf(dev, "No SMN device found\n");
472 			return (ENXIO);
473 		}
474 	}
475 
476 	/* Find number of cores per package. */
477 	sc->sc_ncores = (amd_feature2 & AMDID2_CMP) != 0 ?
478 	    (cpu_procinfo2 & AMDID_CMP_CORES) + 1 : 1;
479 	if (sc->sc_ncores > MAXCPU)
480 		return (ENXIO);
481 
482 	if (erratum319)
483 		device_printf(dev,
484 		    "Erratum 319: temperature measurement may be inaccurate\n");
485 	if (bootverbose)
486 		device_printf(dev, "Found %d cores and %d sensors.\n",
487 		    sc->sc_ncores,
488 		    sc->sc_ntemps > 1 ? sc->sc_ntemps * sc->sc_ncores : 1);
489 
490 	/*
491 	 * dev.amdtemp.N tree.
492 	 */
493 	unit = device_get_unit(dev);
494 	snprintf(tn, sizeof(tn), "dev.amdtemp.%d.sensor_offset", unit);
495 	TUNABLE_INT_FETCH(tn, &sc->sc_offset);
496 
497 	sysctlctx = device_get_sysctl_ctx(dev);
498 	SYSCTL_ADD_INT(sysctlctx,
499 	    SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
500 	    "sensor_offset", CTLFLAG_RW, &sc->sc_offset, 0,
501 	    "Temperature sensor offset");
502 	sysctlnode = SYSCTL_ADD_NODE(sysctlctx,
503 	    SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
504 	    "core0", CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "Core 0");
505 
506 	SYSCTL_ADD_PROC(sysctlctx,
507 	    SYSCTL_CHILDREN(sysctlnode),
508 	    OID_AUTO, "sensor0",
509 	    CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
510 	    dev, CORE0_SENSOR0, amdtemp_sysctl, "IK",
511 	    "Core 0 / Sensor 0 temperature");
512 
513 	if (family == 0x17)
514 		amdtemp_probe_ccd_sensors17h(dev, model);
515 	else if (family == 0x19)
516 		amdtemp_probe_ccd_sensors19h(dev, model);
517 	else if (sc->sc_ntemps > 1) {
518 		SYSCTL_ADD_PROC(sysctlctx,
519 		    SYSCTL_CHILDREN(sysctlnode),
520 		    OID_AUTO, "sensor1",
521 		    CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
522 		    dev, CORE0_SENSOR1, amdtemp_sysctl, "IK",
523 		    "Core 0 / Sensor 1 temperature");
524 
525 		if (sc->sc_ncores > 1) {
526 			sysctlnode = SYSCTL_ADD_NODE(sysctlctx,
527 			    SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
528 			    OID_AUTO, "core1", CTLFLAG_RD | CTLFLAG_MPSAFE,
529 			    0, "Core 1");
530 
531 			SYSCTL_ADD_PROC(sysctlctx,
532 			    SYSCTL_CHILDREN(sysctlnode),
533 			    OID_AUTO, "sensor0",
534 			    CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
535 			    dev, CORE1_SENSOR0, amdtemp_sysctl, "IK",
536 			    "Core 1 / Sensor 0 temperature");
537 
538 			SYSCTL_ADD_PROC(sysctlctx,
539 			    SYSCTL_CHILDREN(sysctlnode),
540 			    OID_AUTO, "sensor1",
541 			    CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
542 			    dev, CORE1_SENSOR1, amdtemp_sysctl, "IK",
543 			    "Core 1 / Sensor 1 temperature");
544 		}
545 	}
546 
547 	/*
548 	 * Try to create dev.cpu sysctl entries and setup intrhook function.
549 	 * This is needed because the cpu driver may be loaded late on boot,
550 	 * after us.
551 	 */
552 	amdtemp_intrhook(dev);
553 	sc->sc_ich.ich_func = amdtemp_intrhook;
554 	sc->sc_ich.ich_arg = dev;
555 	if (config_intrhook_establish(&sc->sc_ich) != 0) {
556 		device_printf(dev, "config_intrhook_establish failed!\n");
557 		return (ENXIO);
558 	}
559 
560 	return (0);
561 }
562 
563 void
564 amdtemp_intrhook(void *arg)
565 {
566 	struct amdtemp_softc *sc;
567 	struct sysctl_ctx_list *sysctlctx;
568 	device_t dev = (device_t)arg;
569 	device_t acpi, cpu, nexus;
570 	amdsensor_t sensor;
571 	int i;
572 
573 	sc = device_get_softc(dev);
574 
575 	/*
576 	 * dev.cpu.N.temperature.
577 	 */
578 	nexus = device_find_child(root_bus, "nexus", 0);
579 	acpi = device_find_child(nexus, "acpi", 0);
580 
581 	for (i = 0; i < sc->sc_ncores; i++) {
582 		if (sc->sc_sysctl_cpu[i] != NULL)
583 			continue;
584 		cpu = device_find_child(acpi, "cpu",
585 		    device_get_unit(dev) * sc->sc_ncores + i);
586 		if (cpu != NULL) {
587 			sysctlctx = device_get_sysctl_ctx(cpu);
588 
589 			sensor = sc->sc_ntemps > 1 ?
590 			    (i == 0 ? CORE0 : CORE1) : CORE0_SENSOR0;
591 			sc->sc_sysctl_cpu[i] = SYSCTL_ADD_PROC(sysctlctx,
592 			    SYSCTL_CHILDREN(device_get_sysctl_tree(cpu)),
593 			    OID_AUTO, "temperature",
594 			    CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
595 			    dev, sensor, amdtemp_sysctl, "IK",
596 			    "Current temparature");
597 		}
598 	}
599 	if (sc->sc_ich.ich_arg != NULL)
600 		config_intrhook_disestablish(&sc->sc_ich);
601 }
602 
603 int
604 amdtemp_detach(device_t dev)
605 {
606 	struct amdtemp_softc *sc = device_get_softc(dev);
607 	int i;
608 
609 	for (i = 0; i < sc->sc_ncores; i++)
610 		if (sc->sc_sysctl_cpu[i] != NULL)
611 			sysctl_remove_oid(sc->sc_sysctl_cpu[i], 1, 0);
612 
613 	/* NewBus removes the dev.amdtemp.N tree by itself. */
614 
615 	return (0);
616 }
617 
618 static int
619 amdtemp_sysctl(SYSCTL_HANDLER_ARGS)
620 {
621 	device_t dev = (device_t)arg1;
622 	struct amdtemp_softc *sc = device_get_softc(dev);
623 	amdsensor_t sensor = (amdsensor_t)arg2;
624 	int32_t auxtemp[2], temp;
625 	int error;
626 
627 	switch (sensor) {
628 	case CORE0:
629 		auxtemp[0] = sc->sc_gettemp(dev, CORE0_SENSOR0);
630 		auxtemp[1] = sc->sc_gettemp(dev, CORE0_SENSOR1);
631 		temp = imax(auxtemp[0], auxtemp[1]);
632 		break;
633 	case CORE1:
634 		auxtemp[0] = sc->sc_gettemp(dev, CORE1_SENSOR0);
635 		auxtemp[1] = sc->sc_gettemp(dev, CORE1_SENSOR1);
636 		temp = imax(auxtemp[0], auxtemp[1]);
637 		break;
638 	default:
639 		temp = sc->sc_gettemp(dev, sensor);
640 		break;
641 	}
642 	error = sysctl_handle_int(oidp, &temp, 0, req);
643 
644 	return (error);
645 }
646 
647 #define	AMDTEMP_ZERO_C_TO_K	2731
648 
649 static int32_t
650 amdtemp_gettemp0f(device_t dev, amdsensor_t sensor)
651 {
652 	struct amdtemp_softc *sc = device_get_softc(dev);
653 	uint32_t mask, offset, temp;
654 
655 	/* Set Sensor/Core selector. */
656 	temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 1);
657 	temp &= ~(AMDTEMP_TTSR_SELCORE | AMDTEMP_TTSR_SELSENSOR);
658 	switch (sensor) {
659 	case CORE0_SENSOR1:
660 		temp |= AMDTEMP_TTSR_SELSENSOR;
661 		/* FALLTHROUGH */
662 	case CORE0_SENSOR0:
663 	case CORE0:
664 		if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) != 0)
665 			temp |= AMDTEMP_TTSR_SELCORE;
666 		break;
667 	case CORE1_SENSOR1:
668 		temp |= AMDTEMP_TTSR_SELSENSOR;
669 		/* FALLTHROUGH */
670 	case CORE1_SENSOR0:
671 	case CORE1:
672 		if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) == 0)
673 			temp |= AMDTEMP_TTSR_SELCORE;
674 		break;
675 	default:
676 		__assert_unreachable();
677 	}
678 	pci_write_config(dev, AMDTEMP_THERMTP_STAT, temp, 1);
679 
680 	mask = (sc->sc_flags & AMDTEMP_FLAG_CT_10BIT) != 0 ? 0x3ff : 0x3fc;
681 	offset = (sc->sc_flags & AMDTEMP_FLAG_ALT_OFFSET) != 0 ? 28 : 49;
682 	temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 4);
683 	temp = ((temp >> 14) & mask) * 5 / 2;
684 	temp += AMDTEMP_ZERO_C_TO_K + (sc->sc_offset - offset) * 10;
685 
686 	return (temp);
687 }
688 
689 static uint32_t
690 amdtemp_decode_fam10h_to_17h(int32_t sc_offset, uint32_t val, bool minus49)
691 {
692 	uint32_t temp;
693 
694 	/* Convert raw register subfield units (0.125C) to units of 0.1C. */
695 	temp = (val & AMDTEMP_REPTMP10H_CURTMP_MASK) * 5 / 4;
696 
697 	if (minus49)
698 		temp -= AMDTEMP_CURTMP_RANGE_ADJUST;
699 
700 	temp += AMDTEMP_ZERO_C_TO_K + sc_offset * 10;
701 	return (temp);
702 }
703 
704 static uint32_t
705 amdtemp_decode_fam10h_to_16h(int32_t sc_offset, uint32_t val)
706 {
707 	bool minus49;
708 
709 	/*
710 	 * On Family 15h and higher, if CurTmpTjSel is 11b, the range is
711 	 * adjusted down by 49.0 degrees Celsius.  (This adjustment is not
712 	 * documented in BKDGs prior to family 15h model 00h.)
713 	 */
714 	minus49 = (CPUID_TO_FAMILY(cpu_id) >= 0x15 &&
715 	    ((val >> AMDTEMP_REPTMP10H_TJSEL_SHIFT) &
716 	    AMDTEMP_REPTMP10H_TJSEL_MASK) == 0x3);
717 
718 	return (amdtemp_decode_fam10h_to_17h(sc_offset,
719 	    val >> AMDTEMP_REPTMP10H_CURTMP_SHIFT, minus49));
720 }
721 
722 static uint32_t
723 amdtemp_decode_fam17h_tctl(int32_t sc_offset, uint32_t val)
724 {
725 	bool minus49;
726 
727 	minus49 = ((val & AMDTEMP_17H_CUR_TMP_RANGE_SEL) != 0);
728 	return (amdtemp_decode_fam10h_to_17h(sc_offset,
729 	    val >> AMDTEMP_REPTMP10H_CURTMP_SHIFT, minus49));
730 }
731 
732 static int32_t
733 amdtemp_gettemp(device_t dev, amdsensor_t sensor)
734 {
735 	struct amdtemp_softc *sc = device_get_softc(dev);
736 	uint32_t temp;
737 
738 	temp = pci_read_config(dev, AMDTEMP_REPTMP_CTRL, 4);
739 	return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, temp));
740 }
741 
742 static int32_t
743 amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor)
744 {
745 	struct amdtemp_softc *sc = device_get_softc(dev);
746 	uint32_t val;
747 	int error __diagused;
748 
749 	error = amdsmn_read(sc->sc_smn, AMDTEMP_15H_M60H_REPTMP_CTRL, &val);
750 	KASSERT(error == 0, ("amdsmn_read"));
751 	return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, val));
752 }
753 
754 static int32_t
755 amdtemp_gettemp17h(device_t dev, amdsensor_t sensor)
756 {
757 	struct amdtemp_softc *sc = device_get_softc(dev);
758 	uint32_t val;
759 	int error __diagused;
760 
761 	switch (sensor) {
762 	case CORE0_SENSOR0:
763 		/* Tctl */
764 		error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CUR_TMP, &val);
765 		KASSERT(error == 0, ("amdsmn_read"));
766 		return (amdtemp_decode_fam17h_tctl(sc->sc_offset, val));
767 	case CCD_BASE ... CCD_MAX:
768 		/* Tccd<N> */
769 		error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CCD_TMP_BASE +
770 		    (((int)sensor - CCD_BASE) * sizeof(val)), &val);
771 		KASSERT(error == 0, ("amdsmn_read2"));
772 		KASSERT((val & AMDTEMP_17H_CCD_TMP_VALID) != 0,
773 		    ("sensor %d: not valid", (int)sensor));
774 		return (amdtemp_decode_fam10h_to_17h(sc->sc_offset, val, true));
775 	default:
776 		__assert_unreachable();
777 	}
778 }
779 
780 static void
781 amdtemp_probe_ccd_sensors(device_t dev, uint32_t maxreg)
782 {
783 	char sensor_name[16], sensor_descr[32];
784 	struct amdtemp_softc *sc;
785 	uint32_t i, val;
786 	int error;
787 
788 	sc = device_get_softc(dev);
789 	for (i = 0; i < maxreg; i++) {
790 		error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CCD_TMP_BASE +
791 		    (i * sizeof(val)), &val);
792 		if (error != 0)
793 			continue;
794 		if ((val & AMDTEMP_17H_CCD_TMP_VALID) == 0)
795 			continue;
796 
797 		snprintf(sensor_name, sizeof(sensor_name), "ccd%u", i);
798 		snprintf(sensor_descr, sizeof(sensor_descr),
799 		    "CCD %u temperature (Tccd%u)", i, i);
800 
801 		SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
802 		    SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO,
803 		    sensor_name, CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE,
804 		    dev, CCD_BASE + i, amdtemp_sysctl, "IK", sensor_descr);
805 	}
806 }
807 
808 static void
809 amdtemp_probe_ccd_sensors17h(device_t dev, uint32_t model)
810 {
811 	uint32_t maxreg;
812 
813 	switch (model) {
814 	case 0x00 ... 0x2f: /* Zen1, Zen+ */
815 		maxreg = 4;
816 		break;
817 	case 0x30 ... 0x3f: /* Zen2 TR (Castle Peak)/EPYC (Rome) */
818 	case 0x60 ... 0x7f: /* Zen2 Ryzen (Renoir APU, Matisse) */
819 	case 0x90 ... 0x9f: /* Zen2 Ryzen (Van Gogh APU) */
820 		maxreg = 8;
821 		_Static_assert((int)NUM_CCDS >= 8, "");
822 		break;
823 	default:
824 		device_printf(dev,
825 		    "Unrecognized Family 17h Model: %02xh\n", model);
826 		return;
827 	}
828 
829 	amdtemp_probe_ccd_sensors(dev, maxreg);
830 }
831 
832 static void
833 amdtemp_probe_ccd_sensors19h(device_t dev, uint32_t model)
834 {
835 	uint32_t maxreg;
836 
837 	switch (model) {
838 	case 0x00 ... 0x0f: /* Zen3 EPYC "Milan" */
839 	case 0x20 ... 0x2f: /* Zen3 Ryzen "Vermeer" */
840 		maxreg = 8;
841 		_Static_assert((int)NUM_CCDS >= 8, "");
842 		break;
843 	default:
844 		device_printf(dev,
845 		    "Unrecognized Family 19h Model: %02xh\n", model);
846 		return;
847 	}
848 
849 	amdtemp_probe_ccd_sensors(dev, maxreg);
850 }
851