1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008, 2009 Rui Paulo <rpaulo@FreeBSD.org> 5 * Copyright (c) 2009 Norikatsu Shigemura <nork@FreeBSD.org> 6 * Copyright (c) 2009-2012 Jung-uk Kim <jkim@FreeBSD.org> 7 * All rights reserved. 8 * Copyright (c) 2017-2020 Conrad Meyer <cem@FreeBSD.org>. All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Driver for the AMD CPU on-die thermal sensors. 34 * Initially based on the k8temp Linux driver. 35 */ 36 37 #include <sys/cdefs.h> 38 __FBSDID("$FreeBSD$"); 39 40 #include <sys/param.h> 41 #include <sys/bus.h> 42 #include <sys/conf.h> 43 #include <sys/kernel.h> 44 #include <sys/module.h> 45 #include <sys/sysctl.h> 46 #include <sys/systm.h> 47 48 #include <machine/cpufunc.h> 49 #include <machine/md_var.h> 50 #include <machine/specialreg.h> 51 52 #include <dev/pci/pcivar.h> 53 #include <x86/pci_cfgreg.h> 54 55 #include <dev/amdsmn/amdsmn.h> 56 57 typedef enum { 58 CORE0_SENSOR0, 59 CORE0_SENSOR1, 60 CORE1_SENSOR0, 61 CORE1_SENSOR1, 62 CORE0, 63 CORE1, 64 CCD1, 65 CCD_BASE = CCD1, 66 CCD2, 67 CCD3, 68 CCD4, 69 CCD5, 70 CCD6, 71 CCD7, 72 CCD8, 73 CCD_MAX = CCD8, 74 NUM_CCDS = CCD_MAX - CCD_BASE + 1, 75 } amdsensor_t; 76 77 struct amdtemp_softc { 78 int sc_ncores; 79 int sc_ntemps; 80 int sc_flags; 81 #define AMDTEMP_FLAG_CS_SWAP 0x01 /* ThermSenseCoreSel is inverted. */ 82 #define AMDTEMP_FLAG_CT_10BIT 0x02 /* CurTmp is 10-bit wide. */ 83 #define AMDTEMP_FLAG_ALT_OFFSET 0x04 /* CurTmp starts at -28C. */ 84 int32_t sc_offset; 85 int32_t (*sc_gettemp)(device_t, amdsensor_t); 86 struct sysctl_oid *sc_sysctl_cpu[MAXCPU]; 87 struct intr_config_hook sc_ich; 88 device_t sc_smn; 89 }; 90 91 /* 92 * N.B. The numbers in macro names below are significant and represent CPU 93 * family and model numbers. Do not make up fictitious family or model numbers 94 * when adding support for new devices. 95 */ 96 #define VENDORID_AMD 0x1022 97 #define DEVICEID_AMD_MISC0F 0x1103 98 #define DEVICEID_AMD_MISC10 0x1203 99 #define DEVICEID_AMD_MISC11 0x1303 100 #define DEVICEID_AMD_MISC14 0x1703 101 #define DEVICEID_AMD_MISC15 0x1603 102 #define DEVICEID_AMD_MISC15_M10H 0x1403 103 #define DEVICEID_AMD_MISC15_M30H 0x141d 104 #define DEVICEID_AMD_MISC15_M60H_ROOT 0x1576 105 #define DEVICEID_AMD_MISC16 0x1533 106 #define DEVICEID_AMD_MISC16_M30H 0x1583 107 #define DEVICEID_AMD_HOSTB17H_ROOT 0x1450 108 #define DEVICEID_AMD_HOSTB17H_M10H_ROOT 0x15d0 109 #define DEVICEID_AMD_HOSTB17H_M30H_ROOT 0x1480 /* Also M70h. */ 110 111 static const struct amdtemp_product { 112 uint16_t amdtemp_vendorid; 113 uint16_t amdtemp_deviceid; 114 /* 115 * 0xFC register is only valid on the D18F3 PCI device; SMN temp 116 * drivers do not attach to that device. 117 */ 118 bool amdtemp_has_cpuid; 119 } amdtemp_products[] = { 120 { VENDORID_AMD, DEVICEID_AMD_MISC0F, true }, 121 { VENDORID_AMD, DEVICEID_AMD_MISC10, true }, 122 { VENDORID_AMD, DEVICEID_AMD_MISC11, true }, 123 { VENDORID_AMD, DEVICEID_AMD_MISC14, true }, 124 { VENDORID_AMD, DEVICEID_AMD_MISC15, true }, 125 { VENDORID_AMD, DEVICEID_AMD_MISC15_M10H, true }, 126 { VENDORID_AMD, DEVICEID_AMD_MISC15_M30H, true }, 127 { VENDORID_AMD, DEVICEID_AMD_MISC15_M60H_ROOT, false }, 128 { VENDORID_AMD, DEVICEID_AMD_MISC16, true }, 129 { VENDORID_AMD, DEVICEID_AMD_MISC16_M30H, true }, 130 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_ROOT, false }, 131 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M10H_ROOT, false }, 132 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M30H_ROOT, false }, 133 }; 134 135 /* 136 * Reported Temperature Control Register, family 0Fh-15h (some models), 16h. 137 */ 138 #define AMDTEMP_REPTMP_CTRL 0xa4 139 140 #define AMDTEMP_REPTMP10H_CURTMP_MASK 0x7ff 141 #define AMDTEMP_REPTMP10H_CURTMP_SHIFT 21 142 #define AMDTEMP_REPTMP10H_TJSEL_MASK 0x3 143 #define AMDTEMP_REPTMP10H_TJSEL_SHIFT 16 144 145 /* 146 * Reported Temperature, Family 15h, M60+ 147 * 148 * Same register bit definitions as other Family 15h CPUs, but access is 149 * indirect via SMN, like Family 17h. 150 */ 151 #define AMDTEMP_15H_M60H_REPTMP_CTRL 0xd8200ca4 152 153 /* 154 * Reported Temperature, Family 17h 155 * 156 * According to AMD OSRR for 17H, section 4.2.1, bits 31-21 of this register 157 * provide the current temp. bit 19, when clear, means the temp is reported in 158 * a range 0.."225C" (probable typo for 255C), and when set changes the range 159 * to -49..206C. 160 */ 161 #define AMDTEMP_17H_CUR_TMP 0x59800 162 #define AMDTEMP_17H_CUR_TMP_RANGE_SEL (1u << 19) 163 /* 164 * The following register set was discovered experimentally by Ondrej Čerman 165 * and collaborators, but is not (yet) documented in a PPR/OSRR (other than 166 * the M70H PPR SMN memory map showing [0x59800, +0x314] as allocated to 167 * SMU::THM). It seems plausible and the Linux sensor folks have adopted it. 168 */ 169 #define AMDTEMP_17H_CCD_TMP_BASE 0x59954 170 #define AMDTEMP_17H_CCD_TMP_VALID (1u << 11) 171 172 /* 173 * AMD temperature range adjustment, in deciKelvins (i.e., 49.0 Celsius). 174 */ 175 #define AMDTEMP_CURTMP_RANGE_ADJUST 490 176 177 /* 178 * Thermaltrip Status Register (Family 0Fh only) 179 */ 180 #define AMDTEMP_THERMTP_STAT 0xe4 181 #define AMDTEMP_TTSR_SELCORE 0x04 182 #define AMDTEMP_TTSR_SELSENSOR 0x40 183 184 /* 185 * DRAM Configuration High Register 186 */ 187 #define AMDTEMP_DRAM_CONF_HIGH 0x94 /* Function 2 */ 188 #define AMDTEMP_DRAM_MODE_DDR3 0x0100 189 190 /* 191 * CPU Family/Model Register 192 */ 193 #define AMDTEMP_CPUID 0xfc 194 195 /* 196 * Device methods. 197 */ 198 static void amdtemp_identify(driver_t *driver, device_t parent); 199 static int amdtemp_probe(device_t dev); 200 static int amdtemp_attach(device_t dev); 201 static void amdtemp_intrhook(void *arg); 202 static int amdtemp_detach(device_t dev); 203 static int32_t amdtemp_gettemp0f(device_t dev, amdsensor_t sensor); 204 static int32_t amdtemp_gettemp(device_t dev, amdsensor_t sensor); 205 static int32_t amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor); 206 static int32_t amdtemp_gettemp17h(device_t dev, amdsensor_t sensor); 207 static void amdtemp_probe_ccd_sensors17h(device_t dev, uint32_t model); 208 static int amdtemp_sysctl(SYSCTL_HANDLER_ARGS); 209 210 static device_method_t amdtemp_methods[] = { 211 /* Device interface */ 212 DEVMETHOD(device_identify, amdtemp_identify), 213 DEVMETHOD(device_probe, amdtemp_probe), 214 DEVMETHOD(device_attach, amdtemp_attach), 215 DEVMETHOD(device_detach, amdtemp_detach), 216 217 DEVMETHOD_END 218 }; 219 220 static driver_t amdtemp_driver = { 221 "amdtemp", 222 amdtemp_methods, 223 sizeof(struct amdtemp_softc), 224 }; 225 226 static devclass_t amdtemp_devclass; 227 DRIVER_MODULE(amdtemp, hostb, amdtemp_driver, amdtemp_devclass, NULL, NULL); 228 MODULE_VERSION(amdtemp, 1); 229 MODULE_DEPEND(amdtemp, amdsmn, 1, 1, 1); 230 MODULE_PNP_INFO("U16:vendor;U16:device", pci, amdtemp, amdtemp_products, 231 nitems(amdtemp_products)); 232 233 static bool 234 amdtemp_match(device_t dev, const struct amdtemp_product **product_out) 235 { 236 int i; 237 uint16_t vendor, devid; 238 239 vendor = pci_get_vendor(dev); 240 devid = pci_get_device(dev); 241 242 for (i = 0; i < nitems(amdtemp_products); i++) { 243 if (vendor == amdtemp_products[i].amdtemp_vendorid && 244 devid == amdtemp_products[i].amdtemp_deviceid) { 245 if (product_out != NULL) 246 *product_out = &amdtemp_products[i]; 247 return (true); 248 } 249 } 250 return (false); 251 } 252 253 static void 254 amdtemp_identify(driver_t *driver, device_t parent) 255 { 256 device_t child; 257 258 /* Make sure we're not being doubly invoked. */ 259 if (device_find_child(parent, "amdtemp", -1) != NULL) 260 return; 261 262 if (amdtemp_match(parent, NULL)) { 263 child = device_add_child(parent, "amdtemp", -1); 264 if (child == NULL) 265 device_printf(parent, "add amdtemp child failed\n"); 266 } 267 } 268 269 static int 270 amdtemp_probe(device_t dev) 271 { 272 uint32_t family, model; 273 274 if (resource_disabled("amdtemp", 0)) 275 return (ENXIO); 276 if (!amdtemp_match(device_get_parent(dev), NULL)) 277 return (ENXIO); 278 279 family = CPUID_TO_FAMILY(cpu_id); 280 model = CPUID_TO_MODEL(cpu_id); 281 282 switch (family) { 283 case 0x0f: 284 if ((model == 0x04 && (cpu_id & CPUID_STEPPING) == 0) || 285 (model == 0x05 && (cpu_id & CPUID_STEPPING) <= 1)) 286 return (ENXIO); 287 break; 288 case 0x10: 289 case 0x11: 290 case 0x12: 291 case 0x14: 292 case 0x15: 293 case 0x16: 294 case 0x17: 295 break; 296 default: 297 return (ENXIO); 298 } 299 device_set_desc(dev, "AMD CPU On-Die Thermal Sensors"); 300 301 return (BUS_PROBE_GENERIC); 302 } 303 304 static int 305 amdtemp_attach(device_t dev) 306 { 307 char tn[32]; 308 u_int regs[4]; 309 const struct amdtemp_product *product; 310 struct amdtemp_softc *sc; 311 struct sysctl_ctx_list *sysctlctx; 312 struct sysctl_oid *sysctlnode; 313 uint32_t cpuid, family, model; 314 u_int bid; 315 int erratum319, unit; 316 bool needsmn; 317 318 sc = device_get_softc(dev); 319 erratum319 = 0; 320 needsmn = false; 321 322 if (!amdtemp_match(device_get_parent(dev), &product)) 323 return (ENXIO); 324 325 cpuid = cpu_id; 326 family = CPUID_TO_FAMILY(cpuid); 327 model = CPUID_TO_MODEL(cpuid); 328 329 /* 330 * This checks for the byzantine condition of running a heterogenous 331 * revision multi-socket system where the attach thread is potentially 332 * probing a remote socket's PCI device. 333 * 334 * Currently, such scenarios are unsupported on models using the SMN 335 * (because on those models, amdtemp(4) attaches to a different PCI 336 * device than the one that contains AMDTEMP_CPUID). 337 * 338 * The ancient 0x0F family of devices only supports this register from 339 * models 40h+. 340 */ 341 if (product->amdtemp_has_cpuid && (family > 0x0f || 342 (family == 0x0f && model >= 0x40))) { 343 cpuid = pci_read_config(device_get_parent(dev), AMDTEMP_CPUID, 344 4); 345 family = CPUID_TO_FAMILY(cpuid); 346 model = CPUID_TO_MODEL(cpuid); 347 } 348 349 switch (family) { 350 case 0x0f: 351 /* 352 * Thermaltrip Status Register 353 * 354 * - ThermSenseCoreSel 355 * 356 * Revision F & G: 0 - Core1, 1 - Core0 357 * Other: 0 - Core0, 1 - Core1 358 * 359 * - CurTmp 360 * 361 * Revision G: bits 23-14 362 * Other: bits 23-16 363 * 364 * XXX According to the BKDG, CurTmp, ThermSenseSel and 365 * ThermSenseCoreSel bits were introduced in Revision F 366 * but CurTmp seems working fine as early as Revision C. 367 * However, it is not clear whether ThermSenseSel and/or 368 * ThermSenseCoreSel work in undocumented cases as well. 369 * In fact, the Linux driver suggests it may not work but 370 * we just assume it does until we find otherwise. 371 * 372 * XXX According to Linux, CurTmp starts at -28C on 373 * Socket AM2 Revision G processors, which is not 374 * documented anywhere. 375 */ 376 if (model >= 0x40) 377 sc->sc_flags |= AMDTEMP_FLAG_CS_SWAP; 378 if (model >= 0x60 && model != 0xc1) { 379 do_cpuid(0x80000001, regs); 380 bid = (regs[1] >> 9) & 0x1f; 381 switch (model) { 382 case 0x68: /* Socket S1g1 */ 383 case 0x6c: 384 case 0x7c: 385 break; 386 case 0x6b: /* Socket AM2 and ASB1 (2 cores) */ 387 if (bid != 0x0b && bid != 0x0c) 388 sc->sc_flags |= 389 AMDTEMP_FLAG_ALT_OFFSET; 390 break; 391 case 0x6f: /* Socket AM2 and ASB1 (1 core) */ 392 case 0x7f: 393 if (bid != 0x07 && bid != 0x09 && 394 bid != 0x0c) 395 sc->sc_flags |= 396 AMDTEMP_FLAG_ALT_OFFSET; 397 break; 398 default: 399 sc->sc_flags |= AMDTEMP_FLAG_ALT_OFFSET; 400 } 401 sc->sc_flags |= AMDTEMP_FLAG_CT_10BIT; 402 } 403 404 /* 405 * There are two sensors per core. 406 */ 407 sc->sc_ntemps = 2; 408 409 sc->sc_gettemp = amdtemp_gettemp0f; 410 break; 411 case 0x10: 412 /* 413 * Erratum 319 Inaccurate Temperature Measurement 414 * 415 * http://support.amd.com/us/Processor_TechDocs/41322.pdf 416 */ 417 do_cpuid(0x80000001, regs); 418 switch ((regs[1] >> 28) & 0xf) { 419 case 0: /* Socket F */ 420 erratum319 = 1; 421 break; 422 case 1: /* Socket AM2+ or AM3 */ 423 if ((pci_cfgregread(pci_get_bus(dev), 424 pci_get_slot(dev), 2, AMDTEMP_DRAM_CONF_HIGH, 2) & 425 AMDTEMP_DRAM_MODE_DDR3) != 0 || model > 0x04 || 426 (model == 0x04 && (cpuid & CPUID_STEPPING) >= 3)) 427 break; 428 /* XXX 00100F42h (RB-C2) exists in both formats. */ 429 erratum319 = 1; 430 break; 431 } 432 /* FALLTHROUGH */ 433 case 0x11: 434 case 0x12: 435 case 0x14: 436 case 0x15: 437 case 0x16: 438 sc->sc_ntemps = 1; 439 /* 440 * Some later (60h+) models of family 15h use a similar SMN 441 * network as family 17h. (However, the register index differs 442 * from 17h and the decoding matches other 10h-15h models, 443 * which differ from 17h.) 444 */ 445 if (family == 0x15 && model >= 0x60) { 446 sc->sc_gettemp = amdtemp_gettemp15hm60h; 447 needsmn = true; 448 } else 449 sc->sc_gettemp = amdtemp_gettemp; 450 break; 451 case 0x17: 452 sc->sc_ntemps = 1; 453 sc->sc_gettemp = amdtemp_gettemp17h; 454 needsmn = true; 455 break; 456 default: 457 device_printf(dev, "Bogus family 0x%x\n", family); 458 return (ENXIO); 459 } 460 461 if (needsmn) { 462 sc->sc_smn = device_find_child( 463 device_get_parent(dev), "amdsmn", -1); 464 if (sc->sc_smn == NULL) { 465 if (bootverbose) 466 device_printf(dev, "No SMN device found\n"); 467 return (ENXIO); 468 } 469 } 470 471 /* Find number of cores per package. */ 472 sc->sc_ncores = (amd_feature2 & AMDID2_CMP) != 0 ? 473 (cpu_procinfo2 & AMDID_CMP_CORES) + 1 : 1; 474 if (sc->sc_ncores > MAXCPU) 475 return (ENXIO); 476 477 if (erratum319) 478 device_printf(dev, 479 "Erratum 319: temperature measurement may be inaccurate\n"); 480 if (bootverbose) 481 device_printf(dev, "Found %d cores and %d sensors.\n", 482 sc->sc_ncores, 483 sc->sc_ntemps > 1 ? sc->sc_ntemps * sc->sc_ncores : 1); 484 485 /* 486 * dev.amdtemp.N tree. 487 */ 488 unit = device_get_unit(dev); 489 snprintf(tn, sizeof(tn), "dev.amdtemp.%d.sensor_offset", unit); 490 TUNABLE_INT_FETCH(tn, &sc->sc_offset); 491 492 sysctlctx = device_get_sysctl_ctx(dev); 493 SYSCTL_ADD_INT(sysctlctx, 494 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 495 "sensor_offset", CTLFLAG_RW, &sc->sc_offset, 0, 496 "Temperature sensor offset"); 497 sysctlnode = SYSCTL_ADD_NODE(sysctlctx, 498 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 499 "core0", CTLFLAG_RD, 0, "Core 0"); 500 501 SYSCTL_ADD_PROC(sysctlctx, 502 SYSCTL_CHILDREN(sysctlnode), 503 OID_AUTO, "sensor0", CTLTYPE_INT | CTLFLAG_RD, 504 dev, CORE0_SENSOR0, amdtemp_sysctl, "IK", 505 "Core 0 / Sensor 0 temperature"); 506 507 if (family == 0x17) 508 amdtemp_probe_ccd_sensors17h(dev, model); 509 else if (sc->sc_ntemps > 1) { 510 SYSCTL_ADD_PROC(sysctlctx, 511 SYSCTL_CHILDREN(sysctlnode), 512 OID_AUTO, "sensor1", CTLTYPE_INT | CTLFLAG_RD, 513 dev, CORE0_SENSOR1, amdtemp_sysctl, "IK", 514 "Core 0 / Sensor 1 temperature"); 515 516 if (sc->sc_ncores > 1) { 517 sysctlnode = SYSCTL_ADD_NODE(sysctlctx, 518 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 519 OID_AUTO, "core1", CTLFLAG_RD, 0, "Core 1"); 520 521 SYSCTL_ADD_PROC(sysctlctx, 522 SYSCTL_CHILDREN(sysctlnode), 523 OID_AUTO, "sensor0", CTLTYPE_INT | CTLFLAG_RD, 524 dev, CORE1_SENSOR0, amdtemp_sysctl, "IK", 525 "Core 1 / Sensor 0 temperature"); 526 527 SYSCTL_ADD_PROC(sysctlctx, 528 SYSCTL_CHILDREN(sysctlnode), 529 OID_AUTO, "sensor1", CTLTYPE_INT | CTLFLAG_RD, 530 dev, CORE1_SENSOR1, amdtemp_sysctl, "IK", 531 "Core 1 / Sensor 1 temperature"); 532 } 533 } 534 535 /* 536 * Try to create dev.cpu sysctl entries and setup intrhook function. 537 * This is needed because the cpu driver may be loaded late on boot, 538 * after us. 539 */ 540 amdtemp_intrhook(dev); 541 sc->sc_ich.ich_func = amdtemp_intrhook; 542 sc->sc_ich.ich_arg = dev; 543 if (config_intrhook_establish(&sc->sc_ich) != 0) { 544 device_printf(dev, "config_intrhook_establish failed!\n"); 545 return (ENXIO); 546 } 547 548 return (0); 549 } 550 551 void 552 amdtemp_intrhook(void *arg) 553 { 554 struct amdtemp_softc *sc; 555 struct sysctl_ctx_list *sysctlctx; 556 device_t dev = (device_t)arg; 557 device_t acpi, cpu, nexus; 558 amdsensor_t sensor; 559 int i; 560 561 sc = device_get_softc(dev); 562 563 /* 564 * dev.cpu.N.temperature. 565 */ 566 nexus = device_find_child(root_bus, "nexus", 0); 567 acpi = device_find_child(nexus, "acpi", 0); 568 569 for (i = 0; i < sc->sc_ncores; i++) { 570 if (sc->sc_sysctl_cpu[i] != NULL) 571 continue; 572 cpu = device_find_child(acpi, "cpu", 573 device_get_unit(dev) * sc->sc_ncores + i); 574 if (cpu != NULL) { 575 sysctlctx = device_get_sysctl_ctx(cpu); 576 577 sensor = sc->sc_ntemps > 1 ? 578 (i == 0 ? CORE0 : CORE1) : CORE0_SENSOR0; 579 sc->sc_sysctl_cpu[i] = SYSCTL_ADD_PROC(sysctlctx, 580 SYSCTL_CHILDREN(device_get_sysctl_tree(cpu)), 581 OID_AUTO, "temperature", CTLTYPE_INT | CTLFLAG_RD, 582 dev, sensor, amdtemp_sysctl, "IK", 583 "Current temparature"); 584 } 585 } 586 if (sc->sc_ich.ich_arg != NULL) 587 config_intrhook_disestablish(&sc->sc_ich); 588 } 589 590 int 591 amdtemp_detach(device_t dev) 592 { 593 struct amdtemp_softc *sc = device_get_softc(dev); 594 int i; 595 596 for (i = 0; i < sc->sc_ncores; i++) 597 if (sc->sc_sysctl_cpu[i] != NULL) 598 sysctl_remove_oid(sc->sc_sysctl_cpu[i], 1, 0); 599 600 /* NewBus removes the dev.amdtemp.N tree by itself. */ 601 602 return (0); 603 } 604 605 static int 606 amdtemp_sysctl(SYSCTL_HANDLER_ARGS) 607 { 608 device_t dev = (device_t)arg1; 609 struct amdtemp_softc *sc = device_get_softc(dev); 610 amdsensor_t sensor = (amdsensor_t)arg2; 611 int32_t auxtemp[2], temp; 612 int error; 613 614 switch (sensor) { 615 case CORE0: 616 auxtemp[0] = sc->sc_gettemp(dev, CORE0_SENSOR0); 617 auxtemp[1] = sc->sc_gettemp(dev, CORE0_SENSOR1); 618 temp = imax(auxtemp[0], auxtemp[1]); 619 break; 620 case CORE1: 621 auxtemp[0] = sc->sc_gettemp(dev, CORE1_SENSOR0); 622 auxtemp[1] = sc->sc_gettemp(dev, CORE1_SENSOR1); 623 temp = imax(auxtemp[0], auxtemp[1]); 624 break; 625 default: 626 temp = sc->sc_gettemp(dev, sensor); 627 break; 628 } 629 error = sysctl_handle_int(oidp, &temp, 0, req); 630 631 return (error); 632 } 633 634 #define AMDTEMP_ZERO_C_TO_K 2731 635 636 static int32_t 637 amdtemp_gettemp0f(device_t dev, amdsensor_t sensor) 638 { 639 struct amdtemp_softc *sc = device_get_softc(dev); 640 uint32_t mask, offset, temp; 641 642 /* Set Sensor/Core selector. */ 643 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 1); 644 temp &= ~(AMDTEMP_TTSR_SELCORE | AMDTEMP_TTSR_SELSENSOR); 645 switch (sensor) { 646 case CORE0_SENSOR1: 647 temp |= AMDTEMP_TTSR_SELSENSOR; 648 /* FALLTHROUGH */ 649 case CORE0_SENSOR0: 650 case CORE0: 651 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) != 0) 652 temp |= AMDTEMP_TTSR_SELCORE; 653 break; 654 case CORE1_SENSOR1: 655 temp |= AMDTEMP_TTSR_SELSENSOR; 656 /* FALLTHROUGH */ 657 case CORE1_SENSOR0: 658 case CORE1: 659 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) == 0) 660 temp |= AMDTEMP_TTSR_SELCORE; 661 break; 662 default: 663 __unreachable(); 664 } 665 pci_write_config(dev, AMDTEMP_THERMTP_STAT, temp, 1); 666 667 mask = (sc->sc_flags & AMDTEMP_FLAG_CT_10BIT) != 0 ? 0x3ff : 0x3fc; 668 offset = (sc->sc_flags & AMDTEMP_FLAG_ALT_OFFSET) != 0 ? 28 : 49; 669 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 4); 670 temp = ((temp >> 14) & mask) * 5 / 2; 671 temp += AMDTEMP_ZERO_C_TO_K + (sc->sc_offset - offset) * 10; 672 673 return (temp); 674 } 675 676 static uint32_t 677 amdtemp_decode_fam10h_to_17h(int32_t sc_offset, uint32_t val, bool minus49) 678 { 679 uint32_t temp; 680 681 /* Convert raw register subfield units (0.125C) to units of 0.1C. */ 682 temp = (val & AMDTEMP_REPTMP10H_CURTMP_MASK) * 5 / 4; 683 684 if (minus49) 685 temp -= AMDTEMP_CURTMP_RANGE_ADJUST; 686 687 temp += AMDTEMP_ZERO_C_TO_K + sc_offset * 10; 688 return (temp); 689 } 690 691 static uint32_t 692 amdtemp_decode_fam10h_to_16h(int32_t sc_offset, uint32_t val) 693 { 694 bool minus49; 695 696 /* 697 * On Family 15h and higher, if CurTmpTjSel is 11b, the range is 698 * adjusted down by 49.0 degrees Celsius. (This adjustment is not 699 * documented in BKDGs prior to family 15h model 00h.) 700 */ 701 minus49 = (CPUID_TO_FAMILY(cpu_id) >= 0x15 && 702 ((val >> AMDTEMP_REPTMP10H_TJSEL_SHIFT) & 703 AMDTEMP_REPTMP10H_TJSEL_MASK) == 0x3); 704 705 return (amdtemp_decode_fam10h_to_17h(sc_offset, 706 val >> AMDTEMP_REPTMP10H_CURTMP_SHIFT, minus49)); 707 } 708 709 static uint32_t 710 amdtemp_decode_fam17h_tctl(int32_t sc_offset, uint32_t val) 711 { 712 bool minus49; 713 714 minus49 = ((val & AMDTEMP_17H_CUR_TMP_RANGE_SEL) != 0); 715 return (amdtemp_decode_fam10h_to_17h(sc_offset, 716 val >> AMDTEMP_REPTMP10H_CURTMP_SHIFT, minus49)); 717 } 718 719 static int32_t 720 amdtemp_gettemp(device_t dev, amdsensor_t sensor) 721 { 722 struct amdtemp_softc *sc = device_get_softc(dev); 723 uint32_t temp; 724 725 temp = pci_read_config(dev, AMDTEMP_REPTMP_CTRL, 4); 726 return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, temp)); 727 } 728 729 static int32_t 730 amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor) 731 { 732 struct amdtemp_softc *sc = device_get_softc(dev); 733 uint32_t val; 734 int error; 735 736 error = amdsmn_read(sc->sc_smn, AMDTEMP_15H_M60H_REPTMP_CTRL, &val); 737 KASSERT(error == 0, ("amdsmn_read")); 738 return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, val)); 739 } 740 741 static int32_t 742 amdtemp_gettemp17h(device_t dev, amdsensor_t sensor) 743 { 744 struct amdtemp_softc *sc = device_get_softc(dev); 745 uint32_t val; 746 int error; 747 748 switch (sensor) { 749 case CORE0_SENSOR0: 750 /* Tctl */ 751 error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CUR_TMP, &val); 752 KASSERT(error == 0, ("amdsmn_read")); 753 return (amdtemp_decode_fam17h_tctl(sc->sc_offset, val)); 754 case CCD_BASE ... CCD_MAX: 755 /* Tccd<N> */ 756 error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CCD_TMP_BASE + 757 (((int)sensor - CCD_BASE) * sizeof(val)), &val); 758 KASSERT(error == 0, ("amdsmn_read2")); 759 KASSERT((val & AMDTEMP_17H_CCD_TMP_VALID) != 0, 760 ("sensor %d: not valid", (int)sensor)); 761 return (amdtemp_decode_fam10h_to_17h(sc->sc_offset, val, true)); 762 default: 763 __unreachable(); 764 } 765 } 766 767 static void 768 amdtemp_probe_ccd_sensors17h(device_t dev, uint32_t model) 769 { 770 char sensor_name[16], sensor_descr[32]; 771 struct amdtemp_softc *sc; 772 uint32_t maxreg, i, val; 773 int error; 774 775 switch (model) { 776 case 0x00 ... 0x1f: /* Zen1, Zen+ */ 777 maxreg = 4; 778 break; 779 case 0x30 ... 0x3f: /* Zen2 TR/Epyc */ 780 case 0x70 ... 0x7f: /* Zen2 Ryzen */ 781 maxreg = 8; 782 _Static_assert((int)NUM_CCDS >= 8, ""); 783 break; 784 default: 785 device_printf(dev, 786 "Unrecognized Family 17h Model: %02xh\n", model); 787 return; 788 } 789 790 sc = device_get_softc(dev); 791 for (i = 0; i < maxreg; i++) { 792 error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CCD_TMP_BASE + 793 (i * sizeof(val)), &val); 794 if (error != 0) 795 continue; 796 if ((val & AMDTEMP_17H_CCD_TMP_VALID) == 0) 797 continue; 798 799 snprintf(sensor_name, sizeof(sensor_name), "ccd%u", i); 800 snprintf(sensor_descr, sizeof(sensor_descr), 801 "CCD %u temperature (Tccd%u)", i, i); 802 803 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 804 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 805 sensor_name, CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 806 dev, CCD_BASE + i, amdtemp_sysctl, "IK", sensor_descr); 807 } 808 } 809