1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008, 2009 Rui Paulo <rpaulo@FreeBSD.org> 5 * Copyright (c) 2009 Norikatsu Shigemura <nork@FreeBSD.org> 6 * Copyright (c) 2009-2012 Jung-uk Kim <jkim@FreeBSD.org> 7 * All rights reserved. 8 * Copyright (c) 2017-2020 Conrad Meyer <cem@FreeBSD.org>. All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Driver for the AMD CPU on-die thermal sensors. 34 * Initially based on the k8temp Linux driver. 35 */ 36 37 #include <sys/cdefs.h> 38 __FBSDID("$FreeBSD$"); 39 40 #include <sys/param.h> 41 #include <sys/bus.h> 42 #include <sys/conf.h> 43 #include <sys/kernel.h> 44 #include <sys/lock.h> 45 #include <sys/module.h> 46 #include <sys/mutex.h> 47 #include <sys/sysctl.h> 48 #include <sys/systm.h> 49 50 #include <machine/cpufunc.h> 51 #include <machine/md_var.h> 52 #include <machine/specialreg.h> 53 54 #include <dev/pci/pcivar.h> 55 #include <x86/pci_cfgreg.h> 56 57 #include <dev/amdsmn/amdsmn.h> 58 59 typedef enum { 60 CORE0_SENSOR0, 61 CORE0_SENSOR1, 62 CORE1_SENSOR0, 63 CORE1_SENSOR1, 64 CORE0, 65 CORE1, 66 CCD1, 67 CCD_BASE = CCD1, 68 CCD2, 69 CCD3, 70 CCD4, 71 CCD5, 72 CCD6, 73 CCD7, 74 CCD8, 75 CCD_MAX = CCD8, 76 NUM_CCDS = CCD_MAX - CCD_BASE + 1, 77 } amdsensor_t; 78 79 struct amdtemp_softc { 80 int sc_ncores; 81 int sc_ntemps; 82 int sc_flags; 83 #define AMDTEMP_FLAG_CS_SWAP 0x01 /* ThermSenseCoreSel is inverted. */ 84 #define AMDTEMP_FLAG_CT_10BIT 0x02 /* CurTmp is 10-bit wide. */ 85 #define AMDTEMP_FLAG_ALT_OFFSET 0x04 /* CurTmp starts at -28C. */ 86 int32_t sc_offset; 87 int32_t (*sc_gettemp)(device_t, amdsensor_t); 88 struct sysctl_oid *sc_sysctl_cpu[MAXCPU]; 89 struct intr_config_hook sc_ich; 90 device_t sc_smn; 91 struct mtx sc_lock; 92 }; 93 94 /* 95 * N.B. The numbers in macro names below are significant and represent CPU 96 * family and model numbers. Do not make up fictitious family or model numbers 97 * when adding support for new devices. 98 */ 99 #define VENDORID_AMD 0x1022 100 #define DEVICEID_AMD_MISC0F 0x1103 101 #define DEVICEID_AMD_MISC10 0x1203 102 #define DEVICEID_AMD_MISC11 0x1303 103 #define DEVICEID_AMD_MISC14 0x1703 104 #define DEVICEID_AMD_MISC15 0x1603 105 #define DEVICEID_AMD_MISC15_M10H 0x1403 106 #define DEVICEID_AMD_MISC15_M30H 0x141d 107 #define DEVICEID_AMD_MISC15_M60H_ROOT 0x1576 108 #define DEVICEID_AMD_MISC16 0x1533 109 #define DEVICEID_AMD_MISC16_M30H 0x1583 110 #define DEVICEID_AMD_HOSTB17H_ROOT 0x1450 111 #define DEVICEID_AMD_HOSTB17H_M10H_ROOT 0x15d0 112 #define DEVICEID_AMD_HOSTB17H_M30H_ROOT 0x1480 /* Also M70H, F19H M00H/M20H */ 113 #define DEVICEID_AMD_HOSTB17H_M60H_ROOT 0x1630 114 115 static const struct amdtemp_product { 116 uint16_t amdtemp_vendorid; 117 uint16_t amdtemp_deviceid; 118 /* 119 * 0xFC register is only valid on the D18F3 PCI device; SMN temp 120 * drivers do not attach to that device. 121 */ 122 bool amdtemp_has_cpuid; 123 } amdtemp_products[] = { 124 { VENDORID_AMD, DEVICEID_AMD_MISC0F, true }, 125 { VENDORID_AMD, DEVICEID_AMD_MISC10, true }, 126 { VENDORID_AMD, DEVICEID_AMD_MISC11, true }, 127 { VENDORID_AMD, DEVICEID_AMD_MISC14, true }, 128 { VENDORID_AMD, DEVICEID_AMD_MISC15, true }, 129 { VENDORID_AMD, DEVICEID_AMD_MISC15_M10H, true }, 130 { VENDORID_AMD, DEVICEID_AMD_MISC15_M30H, true }, 131 { VENDORID_AMD, DEVICEID_AMD_MISC15_M60H_ROOT, false }, 132 { VENDORID_AMD, DEVICEID_AMD_MISC16, true }, 133 { VENDORID_AMD, DEVICEID_AMD_MISC16_M30H, true }, 134 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_ROOT, false }, 135 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M10H_ROOT, false }, 136 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M30H_ROOT, false }, 137 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M60H_ROOT, false }, 138 }; 139 140 /* 141 * Reported Temperature Control Register, family 0Fh-15h (some models), 16h. 142 */ 143 #define AMDTEMP_REPTMP_CTRL 0xa4 144 145 #define AMDTEMP_REPTMP10H_CURTMP_MASK 0x7ff 146 #define AMDTEMP_REPTMP10H_CURTMP_SHIFT 21 147 #define AMDTEMP_REPTMP10H_TJSEL_MASK 0x3 148 #define AMDTEMP_REPTMP10H_TJSEL_SHIFT 16 149 150 /* 151 * Reported Temperature, Family 15h, M60+ 152 * 153 * Same register bit definitions as other Family 15h CPUs, but access is 154 * indirect via SMN, like Family 17h. 155 */ 156 #define AMDTEMP_15H_M60H_REPTMP_CTRL 0xd8200ca4 157 158 /* 159 * Reported Temperature, Family 17h 160 * 161 * According to AMD OSRR for 17H, section 4.2.1, bits 31-21 of this register 162 * provide the current temp. bit 19, when clear, means the temp is reported in 163 * a range 0.."225C" (probable typo for 255C), and when set changes the range 164 * to -49..206C. 165 */ 166 #define AMDTEMP_17H_CUR_TMP 0x59800 167 #define AMDTEMP_17H_CUR_TMP_RANGE_SEL (1u << 19) 168 /* 169 * The following register set was discovered experimentally by Ondrej Čerman 170 * and collaborators, but is not (yet) documented in a PPR/OSRR (other than 171 * the M70H PPR SMN memory map showing [0x59800, +0x314] as allocated to 172 * SMU::THM). It seems plausible and the Linux sensor folks have adopted it. 173 */ 174 #define AMDTEMP_17H_CCD_TMP_BASE 0x59954 175 #define AMDTEMP_17H_CCD_TMP_VALID (1u << 11) 176 177 /* 178 * AMD temperature range adjustment, in deciKelvins (i.e., 49.0 Celsius). 179 */ 180 #define AMDTEMP_CURTMP_RANGE_ADJUST 490 181 182 /* 183 * Thermaltrip Status Register (Family 0Fh only) 184 */ 185 #define AMDTEMP_THERMTP_STAT 0xe4 186 #define AMDTEMP_TTSR_SELCORE 0x04 187 #define AMDTEMP_TTSR_SELSENSOR 0x40 188 189 /* 190 * DRAM Configuration High Register 191 */ 192 #define AMDTEMP_DRAM_CONF_HIGH 0x94 /* Function 2 */ 193 #define AMDTEMP_DRAM_MODE_DDR3 0x0100 194 195 /* 196 * CPU Family/Model Register 197 */ 198 #define AMDTEMP_CPUID 0xfc 199 200 /* 201 * Device methods. 202 */ 203 static void amdtemp_identify(driver_t *driver, device_t parent); 204 static int amdtemp_probe(device_t dev); 205 static int amdtemp_attach(device_t dev); 206 static void amdtemp_intrhook(void *arg); 207 static int amdtemp_detach(device_t dev); 208 static int32_t amdtemp_gettemp0f(device_t dev, amdsensor_t sensor); 209 static int32_t amdtemp_gettemp(device_t dev, amdsensor_t sensor); 210 static int32_t amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor); 211 static int32_t amdtemp_gettemp17h(device_t dev, amdsensor_t sensor); 212 static void amdtemp_probe_ccd_sensors17h(device_t dev, uint32_t model); 213 static void amdtemp_probe_ccd_sensors19h(device_t dev, uint32_t model); 214 static int amdtemp_sysctl(SYSCTL_HANDLER_ARGS); 215 216 static device_method_t amdtemp_methods[] = { 217 /* Device interface */ 218 DEVMETHOD(device_identify, amdtemp_identify), 219 DEVMETHOD(device_probe, amdtemp_probe), 220 DEVMETHOD(device_attach, amdtemp_attach), 221 DEVMETHOD(device_detach, amdtemp_detach), 222 223 DEVMETHOD_END 224 }; 225 226 static driver_t amdtemp_driver = { 227 "amdtemp", 228 amdtemp_methods, 229 sizeof(struct amdtemp_softc), 230 }; 231 232 DRIVER_MODULE(amdtemp, hostb, amdtemp_driver, NULL, NULL); 233 MODULE_VERSION(amdtemp, 1); 234 MODULE_DEPEND(amdtemp, amdsmn, 1, 1, 1); 235 MODULE_PNP_INFO("U16:vendor;U16:device", pci, amdtemp, amdtemp_products, 236 nitems(amdtemp_products)); 237 238 static bool 239 amdtemp_match(device_t dev, const struct amdtemp_product **product_out) 240 { 241 int i; 242 uint16_t vendor, devid; 243 244 vendor = pci_get_vendor(dev); 245 devid = pci_get_device(dev); 246 247 for (i = 0; i < nitems(amdtemp_products); i++) { 248 if (vendor == amdtemp_products[i].amdtemp_vendorid && 249 devid == amdtemp_products[i].amdtemp_deviceid) { 250 if (product_out != NULL) 251 *product_out = &amdtemp_products[i]; 252 return (true); 253 } 254 } 255 return (false); 256 } 257 258 static void 259 amdtemp_identify(driver_t *driver, device_t parent) 260 { 261 device_t child; 262 263 /* Make sure we're not being doubly invoked. */ 264 if (device_find_child(parent, "amdtemp", -1) != NULL) 265 return; 266 267 if (amdtemp_match(parent, NULL)) { 268 child = device_add_child(parent, "amdtemp", -1); 269 if (child == NULL) 270 device_printf(parent, "add amdtemp child failed\n"); 271 } 272 } 273 274 static int 275 amdtemp_probe(device_t dev) 276 { 277 uint32_t family, model; 278 279 if (resource_disabled("amdtemp", 0)) 280 return (ENXIO); 281 if (!amdtemp_match(device_get_parent(dev), NULL)) 282 return (ENXIO); 283 284 family = CPUID_TO_FAMILY(cpu_id); 285 model = CPUID_TO_MODEL(cpu_id); 286 287 switch (family) { 288 case 0x0f: 289 if ((model == 0x04 && (cpu_id & CPUID_STEPPING) == 0) || 290 (model == 0x05 && (cpu_id & CPUID_STEPPING) <= 1)) 291 return (ENXIO); 292 break; 293 case 0x10: 294 case 0x11: 295 case 0x12: 296 case 0x14: 297 case 0x15: 298 case 0x16: 299 case 0x17: 300 case 0x19: 301 break; 302 default: 303 return (ENXIO); 304 } 305 device_set_desc(dev, "AMD CPU On-Die Thermal Sensors"); 306 307 return (BUS_PROBE_GENERIC); 308 } 309 310 static int 311 amdtemp_attach(device_t dev) 312 { 313 char tn[32]; 314 u_int regs[4]; 315 const struct amdtemp_product *product; 316 struct amdtemp_softc *sc; 317 struct sysctl_ctx_list *sysctlctx; 318 struct sysctl_oid *sysctlnode; 319 uint32_t cpuid, family, model; 320 u_int bid; 321 int erratum319, unit; 322 bool needsmn; 323 324 sc = device_get_softc(dev); 325 erratum319 = 0; 326 needsmn = false; 327 328 if (!amdtemp_match(device_get_parent(dev), &product)) 329 return (ENXIO); 330 331 cpuid = cpu_id; 332 family = CPUID_TO_FAMILY(cpuid); 333 model = CPUID_TO_MODEL(cpuid); 334 335 /* 336 * This checks for the byzantine condition of running a heterogenous 337 * revision multi-socket system where the attach thread is potentially 338 * probing a remote socket's PCI device. 339 * 340 * Currently, such scenarios are unsupported on models using the SMN 341 * (because on those models, amdtemp(4) attaches to a different PCI 342 * device than the one that contains AMDTEMP_CPUID). 343 * 344 * The ancient 0x0F family of devices only supports this register from 345 * models 40h+. 346 */ 347 if (product->amdtemp_has_cpuid && (family > 0x0f || 348 (family == 0x0f && model >= 0x40))) { 349 cpuid = pci_read_config(device_get_parent(dev), AMDTEMP_CPUID, 350 4); 351 family = CPUID_TO_FAMILY(cpuid); 352 model = CPUID_TO_MODEL(cpuid); 353 } 354 355 switch (family) { 356 case 0x0f: 357 /* 358 * Thermaltrip Status Register 359 * 360 * - ThermSenseCoreSel 361 * 362 * Revision F & G: 0 - Core1, 1 - Core0 363 * Other: 0 - Core0, 1 - Core1 364 * 365 * - CurTmp 366 * 367 * Revision G: bits 23-14 368 * Other: bits 23-16 369 * 370 * XXX According to the BKDG, CurTmp, ThermSenseSel and 371 * ThermSenseCoreSel bits were introduced in Revision F 372 * but CurTmp seems working fine as early as Revision C. 373 * However, it is not clear whether ThermSenseSel and/or 374 * ThermSenseCoreSel work in undocumented cases as well. 375 * In fact, the Linux driver suggests it may not work but 376 * we just assume it does until we find otherwise. 377 * 378 * XXX According to Linux, CurTmp starts at -28C on 379 * Socket AM2 Revision G processors, which is not 380 * documented anywhere. 381 */ 382 if (model >= 0x40) 383 sc->sc_flags |= AMDTEMP_FLAG_CS_SWAP; 384 if (model >= 0x60 && model != 0xc1) { 385 do_cpuid(0x80000001, regs); 386 bid = (regs[1] >> 9) & 0x1f; 387 switch (model) { 388 case 0x68: /* Socket S1g1 */ 389 case 0x6c: 390 case 0x7c: 391 break; 392 case 0x6b: /* Socket AM2 and ASB1 (2 cores) */ 393 if (bid != 0x0b && bid != 0x0c) 394 sc->sc_flags |= 395 AMDTEMP_FLAG_ALT_OFFSET; 396 break; 397 case 0x6f: /* Socket AM2 and ASB1 (1 core) */ 398 case 0x7f: 399 if (bid != 0x07 && bid != 0x09 && 400 bid != 0x0c) 401 sc->sc_flags |= 402 AMDTEMP_FLAG_ALT_OFFSET; 403 break; 404 default: 405 sc->sc_flags |= AMDTEMP_FLAG_ALT_OFFSET; 406 } 407 sc->sc_flags |= AMDTEMP_FLAG_CT_10BIT; 408 } 409 410 /* 411 * There are two sensors per core. 412 */ 413 sc->sc_ntemps = 2; 414 415 sc->sc_gettemp = amdtemp_gettemp0f; 416 break; 417 case 0x10: 418 /* 419 * Erratum 319 Inaccurate Temperature Measurement 420 * 421 * http://support.amd.com/us/Processor_TechDocs/41322.pdf 422 */ 423 do_cpuid(0x80000001, regs); 424 switch ((regs[1] >> 28) & 0xf) { 425 case 0: /* Socket F */ 426 erratum319 = 1; 427 break; 428 case 1: /* Socket AM2+ or AM3 */ 429 if ((pci_cfgregread(pci_get_bus(dev), 430 pci_get_slot(dev), 2, AMDTEMP_DRAM_CONF_HIGH, 2) & 431 AMDTEMP_DRAM_MODE_DDR3) != 0 || model > 0x04 || 432 (model == 0x04 && (cpuid & CPUID_STEPPING) >= 3)) 433 break; 434 /* XXX 00100F42h (RB-C2) exists in both formats. */ 435 erratum319 = 1; 436 break; 437 } 438 /* FALLTHROUGH */ 439 case 0x11: 440 case 0x12: 441 case 0x14: 442 case 0x15: 443 case 0x16: 444 sc->sc_ntemps = 1; 445 /* 446 * Some later (60h+) models of family 15h use a similar SMN 447 * network as family 17h. (However, the register index differs 448 * from 17h and the decoding matches other 10h-15h models, 449 * which differ from 17h.) 450 */ 451 if (family == 0x15 && model >= 0x60) { 452 sc->sc_gettemp = amdtemp_gettemp15hm60h; 453 needsmn = true; 454 } else 455 sc->sc_gettemp = amdtemp_gettemp; 456 break; 457 case 0x17: 458 case 0x19: 459 sc->sc_ntemps = 1; 460 sc->sc_gettemp = amdtemp_gettemp17h; 461 needsmn = true; 462 break; 463 default: 464 device_printf(dev, "Bogus family 0x%x\n", family); 465 return (ENXIO); 466 } 467 468 if (needsmn) { 469 sc->sc_smn = device_find_child( 470 device_get_parent(dev), "amdsmn", -1); 471 if (sc->sc_smn == NULL) { 472 if (bootverbose) 473 device_printf(dev, "No SMN device found\n"); 474 return (ENXIO); 475 } 476 } 477 478 /* Find number of cores per package. */ 479 sc->sc_ncores = (amd_feature2 & AMDID2_CMP) != 0 ? 480 (cpu_procinfo2 & AMDID_CMP_CORES) + 1 : 1; 481 if (sc->sc_ncores > MAXCPU) 482 return (ENXIO); 483 484 mtx_init(&sc->sc_lock, "amdtemp", NULL, MTX_DEF); 485 if (erratum319) 486 device_printf(dev, 487 "Erratum 319: temperature measurement may be inaccurate\n"); 488 if (bootverbose) 489 device_printf(dev, "Found %d cores and %d sensors.\n", 490 sc->sc_ncores, 491 sc->sc_ntemps > 1 ? sc->sc_ntemps * sc->sc_ncores : 1); 492 493 /* 494 * dev.amdtemp.N tree. 495 */ 496 unit = device_get_unit(dev); 497 snprintf(tn, sizeof(tn), "dev.amdtemp.%d.sensor_offset", unit); 498 TUNABLE_INT_FETCH(tn, &sc->sc_offset); 499 500 sysctlctx = device_get_sysctl_ctx(dev); 501 SYSCTL_ADD_INT(sysctlctx, 502 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 503 "sensor_offset", CTLFLAG_RW, &sc->sc_offset, 0, 504 "Temperature sensor offset"); 505 sysctlnode = SYSCTL_ADD_NODE(sysctlctx, 506 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 507 "core0", CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "Core 0"); 508 509 SYSCTL_ADD_PROC(sysctlctx, 510 SYSCTL_CHILDREN(sysctlnode), 511 OID_AUTO, "sensor0", 512 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 513 dev, CORE0_SENSOR0, amdtemp_sysctl, "IK", 514 "Core 0 / Sensor 0 temperature"); 515 516 if (family == 0x17) 517 amdtemp_probe_ccd_sensors17h(dev, model); 518 else if (family == 0x19) 519 amdtemp_probe_ccd_sensors19h(dev, model); 520 else if (sc->sc_ntemps > 1) { 521 SYSCTL_ADD_PROC(sysctlctx, 522 SYSCTL_CHILDREN(sysctlnode), 523 OID_AUTO, "sensor1", 524 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 525 dev, CORE0_SENSOR1, amdtemp_sysctl, "IK", 526 "Core 0 / Sensor 1 temperature"); 527 528 if (sc->sc_ncores > 1) { 529 sysctlnode = SYSCTL_ADD_NODE(sysctlctx, 530 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 531 OID_AUTO, "core1", CTLFLAG_RD | CTLFLAG_MPSAFE, 532 0, "Core 1"); 533 534 SYSCTL_ADD_PROC(sysctlctx, 535 SYSCTL_CHILDREN(sysctlnode), 536 OID_AUTO, "sensor0", 537 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 538 dev, CORE1_SENSOR0, amdtemp_sysctl, "IK", 539 "Core 1 / Sensor 0 temperature"); 540 541 SYSCTL_ADD_PROC(sysctlctx, 542 SYSCTL_CHILDREN(sysctlnode), 543 OID_AUTO, "sensor1", 544 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 545 dev, CORE1_SENSOR1, amdtemp_sysctl, "IK", 546 "Core 1 / Sensor 1 temperature"); 547 } 548 } 549 550 /* 551 * Try to create dev.cpu sysctl entries and setup intrhook function. 552 * This is needed because the cpu driver may be loaded late on boot, 553 * after us. 554 */ 555 amdtemp_intrhook(dev); 556 sc->sc_ich.ich_func = amdtemp_intrhook; 557 sc->sc_ich.ich_arg = dev; 558 if (config_intrhook_establish(&sc->sc_ich) != 0) { 559 device_printf(dev, "config_intrhook_establish failed!\n"); 560 return (ENXIO); 561 } 562 563 return (0); 564 } 565 566 void 567 amdtemp_intrhook(void *arg) 568 { 569 struct amdtemp_softc *sc; 570 struct sysctl_ctx_list *sysctlctx; 571 device_t dev = (device_t)arg; 572 device_t acpi, cpu, nexus; 573 amdsensor_t sensor; 574 int i; 575 576 sc = device_get_softc(dev); 577 578 /* 579 * dev.cpu.N.temperature. 580 */ 581 nexus = device_find_child(root_bus, "nexus", 0); 582 acpi = device_find_child(nexus, "acpi", 0); 583 584 for (i = 0; i < sc->sc_ncores; i++) { 585 if (sc->sc_sysctl_cpu[i] != NULL) 586 continue; 587 cpu = device_find_child(acpi, "cpu", 588 device_get_unit(dev) * sc->sc_ncores + i); 589 if (cpu != NULL) { 590 sysctlctx = device_get_sysctl_ctx(cpu); 591 592 sensor = sc->sc_ntemps > 1 ? 593 (i == 0 ? CORE0 : CORE1) : CORE0_SENSOR0; 594 sc->sc_sysctl_cpu[i] = SYSCTL_ADD_PROC(sysctlctx, 595 SYSCTL_CHILDREN(device_get_sysctl_tree(cpu)), 596 OID_AUTO, "temperature", 597 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 598 dev, sensor, amdtemp_sysctl, "IK", 599 "Current temparature"); 600 } 601 } 602 if (sc->sc_ich.ich_arg != NULL) 603 config_intrhook_disestablish(&sc->sc_ich); 604 } 605 606 int 607 amdtemp_detach(device_t dev) 608 { 609 struct amdtemp_softc *sc = device_get_softc(dev); 610 int i; 611 612 for (i = 0; i < sc->sc_ncores; i++) 613 if (sc->sc_sysctl_cpu[i] != NULL) 614 sysctl_remove_oid(sc->sc_sysctl_cpu[i], 1, 0); 615 616 /* NewBus removes the dev.amdtemp.N tree by itself. */ 617 618 mtx_destroy(&sc->sc_lock); 619 return (0); 620 } 621 622 static int 623 amdtemp_sysctl(SYSCTL_HANDLER_ARGS) 624 { 625 device_t dev = (device_t)arg1; 626 struct amdtemp_softc *sc = device_get_softc(dev); 627 amdsensor_t sensor = (amdsensor_t)arg2; 628 int32_t auxtemp[2], temp; 629 int error; 630 631 switch (sensor) { 632 case CORE0: 633 auxtemp[0] = sc->sc_gettemp(dev, CORE0_SENSOR0); 634 auxtemp[1] = sc->sc_gettemp(dev, CORE0_SENSOR1); 635 temp = imax(auxtemp[0], auxtemp[1]); 636 break; 637 case CORE1: 638 auxtemp[0] = sc->sc_gettemp(dev, CORE1_SENSOR0); 639 auxtemp[1] = sc->sc_gettemp(dev, CORE1_SENSOR1); 640 temp = imax(auxtemp[0], auxtemp[1]); 641 break; 642 default: 643 temp = sc->sc_gettemp(dev, sensor); 644 break; 645 } 646 error = sysctl_handle_int(oidp, &temp, 0, req); 647 648 return (error); 649 } 650 651 #define AMDTEMP_ZERO_C_TO_K 2731 652 653 static int32_t 654 amdtemp_gettemp0f(device_t dev, amdsensor_t sensor) 655 { 656 struct amdtemp_softc *sc = device_get_softc(dev); 657 uint32_t mask, offset, temp; 658 659 mtx_lock(&sc->sc_lock); 660 661 /* Set Sensor/Core selector. */ 662 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 1); 663 temp &= ~(AMDTEMP_TTSR_SELCORE | AMDTEMP_TTSR_SELSENSOR); 664 switch (sensor) { 665 case CORE0_SENSOR1: 666 temp |= AMDTEMP_TTSR_SELSENSOR; 667 /* FALLTHROUGH */ 668 case CORE0_SENSOR0: 669 case CORE0: 670 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) != 0) 671 temp |= AMDTEMP_TTSR_SELCORE; 672 break; 673 case CORE1_SENSOR1: 674 temp |= AMDTEMP_TTSR_SELSENSOR; 675 /* FALLTHROUGH */ 676 case CORE1_SENSOR0: 677 case CORE1: 678 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) == 0) 679 temp |= AMDTEMP_TTSR_SELCORE; 680 break; 681 default: 682 __assert_unreachable(); 683 } 684 pci_write_config(dev, AMDTEMP_THERMTP_STAT, temp, 1); 685 686 mask = (sc->sc_flags & AMDTEMP_FLAG_CT_10BIT) != 0 ? 0x3ff : 0x3fc; 687 offset = (sc->sc_flags & AMDTEMP_FLAG_ALT_OFFSET) != 0 ? 28 : 49; 688 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 4); 689 temp = ((temp >> 14) & mask) * 5 / 2; 690 temp += AMDTEMP_ZERO_C_TO_K + (sc->sc_offset - offset) * 10; 691 692 mtx_unlock(&sc->sc_lock); 693 return (temp); 694 } 695 696 static uint32_t 697 amdtemp_decode_fam10h_to_17h(int32_t sc_offset, uint32_t val, bool minus49) 698 { 699 uint32_t temp; 700 701 /* Convert raw register subfield units (0.125C) to units of 0.1C. */ 702 temp = (val & AMDTEMP_REPTMP10H_CURTMP_MASK) * 5 / 4; 703 704 if (minus49) 705 temp -= AMDTEMP_CURTMP_RANGE_ADJUST; 706 707 temp += AMDTEMP_ZERO_C_TO_K + sc_offset * 10; 708 return (temp); 709 } 710 711 static uint32_t 712 amdtemp_decode_fam10h_to_16h(int32_t sc_offset, uint32_t val) 713 { 714 bool minus49; 715 716 /* 717 * On Family 15h and higher, if CurTmpTjSel is 11b, the range is 718 * adjusted down by 49.0 degrees Celsius. (This adjustment is not 719 * documented in BKDGs prior to family 15h model 00h.) 720 */ 721 minus49 = (CPUID_TO_FAMILY(cpu_id) >= 0x15 && 722 ((val >> AMDTEMP_REPTMP10H_TJSEL_SHIFT) & 723 AMDTEMP_REPTMP10H_TJSEL_MASK) == 0x3); 724 725 return (amdtemp_decode_fam10h_to_17h(sc_offset, 726 val >> AMDTEMP_REPTMP10H_CURTMP_SHIFT, minus49)); 727 } 728 729 static uint32_t 730 amdtemp_decode_fam17h_tctl(int32_t sc_offset, uint32_t val) 731 { 732 bool minus49; 733 734 minus49 = ((val & AMDTEMP_17H_CUR_TMP_RANGE_SEL) != 0); 735 return (amdtemp_decode_fam10h_to_17h(sc_offset, 736 val >> AMDTEMP_REPTMP10H_CURTMP_SHIFT, minus49)); 737 } 738 739 static int32_t 740 amdtemp_gettemp(device_t dev, amdsensor_t sensor) 741 { 742 struct amdtemp_softc *sc = device_get_softc(dev); 743 uint32_t temp; 744 745 temp = pci_read_config(dev, AMDTEMP_REPTMP_CTRL, 4); 746 return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, temp)); 747 } 748 749 static int32_t 750 amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor) 751 { 752 struct amdtemp_softc *sc = device_get_softc(dev); 753 uint32_t val; 754 int error __diagused; 755 756 error = amdsmn_read(sc->sc_smn, AMDTEMP_15H_M60H_REPTMP_CTRL, &val); 757 KASSERT(error == 0, ("amdsmn_read")); 758 return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, val)); 759 } 760 761 static int32_t 762 amdtemp_gettemp17h(device_t dev, amdsensor_t sensor) 763 { 764 struct amdtemp_softc *sc = device_get_softc(dev); 765 uint32_t val; 766 int error __diagused; 767 768 switch (sensor) { 769 case CORE0_SENSOR0: 770 /* Tctl */ 771 error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CUR_TMP, &val); 772 KASSERT(error == 0, ("amdsmn_read")); 773 return (amdtemp_decode_fam17h_tctl(sc->sc_offset, val)); 774 case CCD_BASE ... CCD_MAX: 775 /* Tccd<N> */ 776 error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CCD_TMP_BASE + 777 (((int)sensor - CCD_BASE) * sizeof(val)), &val); 778 KASSERT(error == 0, ("amdsmn_read2")); 779 KASSERT((val & AMDTEMP_17H_CCD_TMP_VALID) != 0, 780 ("sensor %d: not valid", (int)sensor)); 781 return (amdtemp_decode_fam10h_to_17h(sc->sc_offset, val, true)); 782 default: 783 __assert_unreachable(); 784 } 785 } 786 787 static void 788 amdtemp_probe_ccd_sensors(device_t dev, uint32_t maxreg) 789 { 790 char sensor_name[16], sensor_descr[32]; 791 struct amdtemp_softc *sc; 792 uint32_t i, val; 793 int error; 794 795 sc = device_get_softc(dev); 796 for (i = 0; i < maxreg; i++) { 797 error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CCD_TMP_BASE + 798 (i * sizeof(val)), &val); 799 if (error != 0) 800 continue; 801 if ((val & AMDTEMP_17H_CCD_TMP_VALID) == 0) 802 continue; 803 804 snprintf(sensor_name, sizeof(sensor_name), "ccd%u", i); 805 snprintf(sensor_descr, sizeof(sensor_descr), 806 "CCD %u temperature (Tccd%u)", i, i); 807 808 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 809 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 810 sensor_name, CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 811 dev, CCD_BASE + i, amdtemp_sysctl, "IK", sensor_descr); 812 } 813 } 814 815 static void 816 amdtemp_probe_ccd_sensors17h(device_t dev, uint32_t model) 817 { 818 uint32_t maxreg; 819 820 switch (model) { 821 case 0x00 ... 0x2f: /* Zen1, Zen+ */ 822 maxreg = 4; 823 break; 824 case 0x30 ... 0x3f: /* Zen2 TR (Castle Peak)/EPYC (Rome) */ 825 case 0x60 ... 0x7f: /* Zen2 Ryzen (Renoir APU, Matisse) */ 826 case 0x90 ... 0x9f: /* Zen2 Ryzen (Van Gogh APU) */ 827 maxreg = 8; 828 _Static_assert((int)NUM_CCDS >= 8, ""); 829 break; 830 default: 831 device_printf(dev, 832 "Unrecognized Family 17h Model: %02xh\n", model); 833 return; 834 } 835 836 amdtemp_probe_ccd_sensors(dev, maxreg); 837 } 838 839 static void 840 amdtemp_probe_ccd_sensors19h(device_t dev, uint32_t model) 841 { 842 uint32_t maxreg; 843 844 switch (model) { 845 case 0x00 ... 0x0f: /* Zen3 EPYC "Milan" */ 846 case 0x20 ... 0x2f: /* Zen3 Ryzen "Vermeer" */ 847 maxreg = 8; 848 _Static_assert((int)NUM_CCDS >= 8, ""); 849 break; 850 default: 851 device_printf(dev, 852 "Unrecognized Family 19h Model: %02xh\n", model); 853 return; 854 } 855 856 amdtemp_probe_ccd_sensors(dev, maxreg); 857 } 858