1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008, 2009 Rui Paulo <rpaulo@FreeBSD.org> 5 * Copyright (c) 2009 Norikatsu Shigemura <nork@FreeBSD.org> 6 * Copyright (c) 2009-2012 Jung-uk Kim <jkim@FreeBSD.org> 7 * All rights reserved. 8 * Copyright (c) 2017-2020 Conrad Meyer <cem@FreeBSD.org>. All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Driver for the AMD CPU on-die thermal sensors. 34 * Initially based on the k8temp Linux driver. 35 */ 36 37 #include <sys/cdefs.h> 38 __FBSDID("$FreeBSD$"); 39 40 #include <sys/param.h> 41 #include <sys/bus.h> 42 #include <sys/conf.h> 43 #include <sys/kernel.h> 44 #include <sys/module.h> 45 #include <sys/sysctl.h> 46 #include <sys/systm.h> 47 48 #include <machine/cpufunc.h> 49 #include <machine/md_var.h> 50 #include <machine/specialreg.h> 51 52 #include <dev/pci/pcivar.h> 53 #include <x86/pci_cfgreg.h> 54 55 #include <dev/amdsmn/amdsmn.h> 56 57 typedef enum { 58 CORE0_SENSOR0, 59 CORE0_SENSOR1, 60 CORE1_SENSOR0, 61 CORE1_SENSOR1, 62 CORE0, 63 CORE1, 64 CCD1, 65 CCD_BASE = CCD1, 66 CCD2, 67 CCD3, 68 CCD4, 69 CCD5, 70 CCD6, 71 CCD7, 72 CCD8, 73 CCD_MAX = CCD8, 74 NUM_CCDS = CCD_MAX - CCD_BASE + 1, 75 } amdsensor_t; 76 77 struct amdtemp_softc { 78 int sc_ncores; 79 int sc_ntemps; 80 int sc_flags; 81 #define AMDTEMP_FLAG_CS_SWAP 0x01 /* ThermSenseCoreSel is inverted. */ 82 #define AMDTEMP_FLAG_CT_10BIT 0x02 /* CurTmp is 10-bit wide. */ 83 #define AMDTEMP_FLAG_ALT_OFFSET 0x04 /* CurTmp starts at -28C. */ 84 int32_t sc_offset; 85 int32_t (*sc_gettemp)(device_t, amdsensor_t); 86 struct sysctl_oid *sc_sysctl_cpu[MAXCPU]; 87 struct intr_config_hook sc_ich; 88 device_t sc_smn; 89 }; 90 91 /* 92 * N.B. The numbers in macro names below are significant and represent CPU 93 * family and model numbers. Do not make up fictitious family or model numbers 94 * when adding support for new devices. 95 */ 96 #define VENDORID_AMD 0x1022 97 #define DEVICEID_AMD_MISC0F 0x1103 98 #define DEVICEID_AMD_MISC10 0x1203 99 #define DEVICEID_AMD_MISC11 0x1303 100 #define DEVICEID_AMD_MISC14 0x1703 101 #define DEVICEID_AMD_MISC15 0x1603 102 #define DEVICEID_AMD_MISC15_M10H 0x1403 103 #define DEVICEID_AMD_MISC15_M30H 0x141d 104 #define DEVICEID_AMD_MISC15_M60H_ROOT 0x1576 105 #define DEVICEID_AMD_MISC16 0x1533 106 #define DEVICEID_AMD_MISC16_M30H 0x1583 107 #define DEVICEID_AMD_HOSTB17H_ROOT 0x1450 108 #define DEVICEID_AMD_HOSTB17H_M10H_ROOT 0x15d0 109 #define DEVICEID_AMD_HOSTB17H_M30H_ROOT 0x1480 /* Also M70H, F19H M00H/M20H */ 110 #define DEVICEID_AMD_HOSTB17H_M60H_ROOT 0x1630 111 112 static const struct amdtemp_product { 113 uint16_t amdtemp_vendorid; 114 uint16_t amdtemp_deviceid; 115 /* 116 * 0xFC register is only valid on the D18F3 PCI device; SMN temp 117 * drivers do not attach to that device. 118 */ 119 bool amdtemp_has_cpuid; 120 } amdtemp_products[] = { 121 { VENDORID_AMD, DEVICEID_AMD_MISC0F, true }, 122 { VENDORID_AMD, DEVICEID_AMD_MISC10, true }, 123 { VENDORID_AMD, DEVICEID_AMD_MISC11, true }, 124 { VENDORID_AMD, DEVICEID_AMD_MISC14, true }, 125 { VENDORID_AMD, DEVICEID_AMD_MISC15, true }, 126 { VENDORID_AMD, DEVICEID_AMD_MISC15_M10H, true }, 127 { VENDORID_AMD, DEVICEID_AMD_MISC15_M30H, true }, 128 { VENDORID_AMD, DEVICEID_AMD_MISC15_M60H_ROOT, false }, 129 { VENDORID_AMD, DEVICEID_AMD_MISC16, true }, 130 { VENDORID_AMD, DEVICEID_AMD_MISC16_M30H, true }, 131 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_ROOT, false }, 132 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M10H_ROOT, false }, 133 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M30H_ROOT, false }, 134 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M60H_ROOT, false }, 135 }; 136 137 /* 138 * Reported Temperature Control Register, family 0Fh-15h (some models), 16h. 139 */ 140 #define AMDTEMP_REPTMP_CTRL 0xa4 141 142 #define AMDTEMP_REPTMP10H_CURTMP_MASK 0x7ff 143 #define AMDTEMP_REPTMP10H_CURTMP_SHIFT 21 144 #define AMDTEMP_REPTMP10H_TJSEL_MASK 0x3 145 #define AMDTEMP_REPTMP10H_TJSEL_SHIFT 16 146 147 /* 148 * Reported Temperature, Family 15h, M60+ 149 * 150 * Same register bit definitions as other Family 15h CPUs, but access is 151 * indirect via SMN, like Family 17h. 152 */ 153 #define AMDTEMP_15H_M60H_REPTMP_CTRL 0xd8200ca4 154 155 /* 156 * Reported Temperature, Family 17h 157 * 158 * According to AMD OSRR for 17H, section 4.2.1, bits 31-21 of this register 159 * provide the current temp. bit 19, when clear, means the temp is reported in 160 * a range 0.."225C" (probable typo for 255C), and when set changes the range 161 * to -49..206C. 162 */ 163 #define AMDTEMP_17H_CUR_TMP 0x59800 164 #define AMDTEMP_17H_CUR_TMP_RANGE_SEL (1u << 19) 165 /* 166 * The following register set was discovered experimentally by Ondrej Čerman 167 * and collaborators, but is not (yet) documented in a PPR/OSRR (other than 168 * the M70H PPR SMN memory map showing [0x59800, +0x314] as allocated to 169 * SMU::THM). It seems plausible and the Linux sensor folks have adopted it. 170 */ 171 #define AMDTEMP_17H_CCD_TMP_BASE 0x59954 172 #define AMDTEMP_17H_CCD_TMP_VALID (1u << 11) 173 174 /* 175 * AMD temperature range adjustment, in deciKelvins (i.e., 49.0 Celsius). 176 */ 177 #define AMDTEMP_CURTMP_RANGE_ADJUST 490 178 179 /* 180 * Thermaltrip Status Register (Family 0Fh only) 181 */ 182 #define AMDTEMP_THERMTP_STAT 0xe4 183 #define AMDTEMP_TTSR_SELCORE 0x04 184 #define AMDTEMP_TTSR_SELSENSOR 0x40 185 186 /* 187 * DRAM Configuration High Register 188 */ 189 #define AMDTEMP_DRAM_CONF_HIGH 0x94 /* Function 2 */ 190 #define AMDTEMP_DRAM_MODE_DDR3 0x0100 191 192 /* 193 * CPU Family/Model Register 194 */ 195 #define AMDTEMP_CPUID 0xfc 196 197 /* 198 * Device methods. 199 */ 200 static void amdtemp_identify(driver_t *driver, device_t parent); 201 static int amdtemp_probe(device_t dev); 202 static int amdtemp_attach(device_t dev); 203 static void amdtemp_intrhook(void *arg); 204 static int amdtemp_detach(device_t dev); 205 static int32_t amdtemp_gettemp0f(device_t dev, amdsensor_t sensor); 206 static int32_t amdtemp_gettemp(device_t dev, amdsensor_t sensor); 207 static int32_t amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor); 208 static int32_t amdtemp_gettemp17h(device_t dev, amdsensor_t sensor); 209 static void amdtemp_probe_ccd_sensors17h(device_t dev, uint32_t model); 210 static void amdtemp_probe_ccd_sensors19h(device_t dev, uint32_t model); 211 static int amdtemp_sysctl(SYSCTL_HANDLER_ARGS); 212 213 static device_method_t amdtemp_methods[] = { 214 /* Device interface */ 215 DEVMETHOD(device_identify, amdtemp_identify), 216 DEVMETHOD(device_probe, amdtemp_probe), 217 DEVMETHOD(device_attach, amdtemp_attach), 218 DEVMETHOD(device_detach, amdtemp_detach), 219 220 DEVMETHOD_END 221 }; 222 223 static driver_t amdtemp_driver = { 224 "amdtemp", 225 amdtemp_methods, 226 sizeof(struct amdtemp_softc), 227 }; 228 229 static devclass_t amdtemp_devclass; 230 DRIVER_MODULE(amdtemp, hostb, amdtemp_driver, amdtemp_devclass, NULL, NULL); 231 MODULE_VERSION(amdtemp, 1); 232 MODULE_DEPEND(amdtemp, amdsmn, 1, 1, 1); 233 MODULE_PNP_INFO("U16:vendor;U16:device", pci, amdtemp, amdtemp_products, 234 nitems(amdtemp_products)); 235 236 static bool 237 amdtemp_match(device_t dev, const struct amdtemp_product **product_out) 238 { 239 int i; 240 uint16_t vendor, devid; 241 242 vendor = pci_get_vendor(dev); 243 devid = pci_get_device(dev); 244 245 for (i = 0; i < nitems(amdtemp_products); i++) { 246 if (vendor == amdtemp_products[i].amdtemp_vendorid && 247 devid == amdtemp_products[i].amdtemp_deviceid) { 248 if (product_out != NULL) 249 *product_out = &amdtemp_products[i]; 250 return (true); 251 } 252 } 253 return (false); 254 } 255 256 static void 257 amdtemp_identify(driver_t *driver, device_t parent) 258 { 259 device_t child; 260 261 /* Make sure we're not being doubly invoked. */ 262 if (device_find_child(parent, "amdtemp", -1) != NULL) 263 return; 264 265 if (amdtemp_match(parent, NULL)) { 266 child = device_add_child(parent, "amdtemp", 267 device_get_unit(parent)); 268 if (child == NULL) 269 device_printf(parent, "add amdtemp child failed\n"); 270 } 271 } 272 273 static int 274 amdtemp_probe(device_t dev) 275 { 276 uint32_t family, model; 277 278 if (resource_disabled("amdtemp", 0)) 279 return (ENXIO); 280 if (!amdtemp_match(device_get_parent(dev), NULL)) 281 return (ENXIO); 282 283 family = CPUID_TO_FAMILY(cpu_id); 284 model = CPUID_TO_MODEL(cpu_id); 285 286 switch (family) { 287 case 0x0f: 288 if ((model == 0x04 && (cpu_id & CPUID_STEPPING) == 0) || 289 (model == 0x05 && (cpu_id & CPUID_STEPPING) <= 1)) 290 return (ENXIO); 291 break; 292 case 0x10: 293 case 0x11: 294 case 0x12: 295 case 0x14: 296 case 0x15: 297 case 0x16: 298 case 0x17: 299 case 0x19: 300 break; 301 default: 302 return (ENXIO); 303 } 304 device_set_desc(dev, "AMD CPU On-Die Thermal Sensors"); 305 306 return (BUS_PROBE_GENERIC); 307 } 308 309 static int 310 amdtemp_attach(device_t dev) 311 { 312 char tn[32]; 313 u_int regs[4]; 314 const struct amdtemp_product *product; 315 struct amdtemp_softc *sc; 316 struct sysctl_ctx_list *sysctlctx; 317 struct sysctl_oid *sysctlnode; 318 uint32_t cpuid, family, model; 319 u_int bid; 320 int erratum319, unit; 321 bool needsmn; 322 323 sc = device_get_softc(dev); 324 erratum319 = 0; 325 needsmn = false; 326 327 if (!amdtemp_match(device_get_parent(dev), &product)) 328 return (ENXIO); 329 330 cpuid = cpu_id; 331 family = CPUID_TO_FAMILY(cpuid); 332 model = CPUID_TO_MODEL(cpuid); 333 334 /* 335 * This checks for the byzantine condition of running a heterogenous 336 * revision multi-socket system where the attach thread is potentially 337 * probing a remote socket's PCI device. 338 * 339 * Currently, such scenarios are unsupported on models using the SMN 340 * (because on those models, amdtemp(4) attaches to a different PCI 341 * device than the one that contains AMDTEMP_CPUID). 342 * 343 * The ancient 0x0F family of devices only supports this register from 344 * models 40h+. 345 */ 346 if (product->amdtemp_has_cpuid && (family > 0x0f || 347 (family == 0x0f && model >= 0x40))) { 348 cpuid = pci_read_config(device_get_parent(dev), AMDTEMP_CPUID, 349 4); 350 family = CPUID_TO_FAMILY(cpuid); 351 model = CPUID_TO_MODEL(cpuid); 352 } 353 354 switch (family) { 355 case 0x0f: 356 /* 357 * Thermaltrip Status Register 358 * 359 * - ThermSenseCoreSel 360 * 361 * Revision F & G: 0 - Core1, 1 - Core0 362 * Other: 0 - Core0, 1 - Core1 363 * 364 * - CurTmp 365 * 366 * Revision G: bits 23-14 367 * Other: bits 23-16 368 * 369 * XXX According to the BKDG, CurTmp, ThermSenseSel and 370 * ThermSenseCoreSel bits were introduced in Revision F 371 * but CurTmp seems working fine as early as Revision C. 372 * However, it is not clear whether ThermSenseSel and/or 373 * ThermSenseCoreSel work in undocumented cases as well. 374 * In fact, the Linux driver suggests it may not work but 375 * we just assume it does until we find otherwise. 376 * 377 * XXX According to Linux, CurTmp starts at -28C on 378 * Socket AM2 Revision G processors, which is not 379 * documented anywhere. 380 */ 381 if (model >= 0x40) 382 sc->sc_flags |= AMDTEMP_FLAG_CS_SWAP; 383 if (model >= 0x60 && model != 0xc1) { 384 do_cpuid(0x80000001, regs); 385 bid = (regs[1] >> 9) & 0x1f; 386 switch (model) { 387 case 0x68: /* Socket S1g1 */ 388 case 0x6c: 389 case 0x7c: 390 break; 391 case 0x6b: /* Socket AM2 and ASB1 (2 cores) */ 392 if (bid != 0x0b && bid != 0x0c) 393 sc->sc_flags |= 394 AMDTEMP_FLAG_ALT_OFFSET; 395 break; 396 case 0x6f: /* Socket AM2 and ASB1 (1 core) */ 397 case 0x7f: 398 if (bid != 0x07 && bid != 0x09 && 399 bid != 0x0c) 400 sc->sc_flags |= 401 AMDTEMP_FLAG_ALT_OFFSET; 402 break; 403 default: 404 sc->sc_flags |= AMDTEMP_FLAG_ALT_OFFSET; 405 } 406 sc->sc_flags |= AMDTEMP_FLAG_CT_10BIT; 407 } 408 409 /* 410 * There are two sensors per core. 411 */ 412 sc->sc_ntemps = 2; 413 414 sc->sc_gettemp = amdtemp_gettemp0f; 415 break; 416 case 0x10: 417 /* 418 * Erratum 319 Inaccurate Temperature Measurement 419 * 420 * http://support.amd.com/us/Processor_TechDocs/41322.pdf 421 */ 422 do_cpuid(0x80000001, regs); 423 switch ((regs[1] >> 28) & 0xf) { 424 case 0: /* Socket F */ 425 erratum319 = 1; 426 break; 427 case 1: /* Socket AM2+ or AM3 */ 428 if ((pci_cfgregread(pci_get_bus(dev), 429 pci_get_slot(dev), 2, AMDTEMP_DRAM_CONF_HIGH, 2) & 430 AMDTEMP_DRAM_MODE_DDR3) != 0 || model > 0x04 || 431 (model == 0x04 && (cpuid & CPUID_STEPPING) >= 3)) 432 break; 433 /* XXX 00100F42h (RB-C2) exists in both formats. */ 434 erratum319 = 1; 435 break; 436 } 437 /* FALLTHROUGH */ 438 case 0x11: 439 case 0x12: 440 case 0x14: 441 case 0x15: 442 case 0x16: 443 sc->sc_ntemps = 1; 444 /* 445 * Some later (60h+) models of family 15h use a similar SMN 446 * network as family 17h. (However, the register index differs 447 * from 17h and the decoding matches other 10h-15h models, 448 * which differ from 17h.) 449 */ 450 if (family == 0x15 && model >= 0x60) { 451 sc->sc_gettemp = amdtemp_gettemp15hm60h; 452 needsmn = true; 453 } else 454 sc->sc_gettemp = amdtemp_gettemp; 455 break; 456 case 0x17: 457 case 0x19: 458 sc->sc_ntemps = 1; 459 sc->sc_gettemp = amdtemp_gettemp17h; 460 needsmn = true; 461 break; 462 default: 463 device_printf(dev, "Bogus family 0x%x\n", family); 464 return (ENXIO); 465 } 466 467 if (needsmn) { 468 sc->sc_smn = device_find_child( 469 device_get_parent(dev), "amdsmn", -1); 470 if (sc->sc_smn == NULL) { 471 if (bootverbose) 472 device_printf(dev, "No SMN device found\n"); 473 return (ENXIO); 474 } 475 } 476 477 /* Find number of cores per package. */ 478 sc->sc_ncores = (amd_feature2 & AMDID2_CMP) != 0 ? 479 (cpu_procinfo2 & AMDID_CMP_CORES) + 1 : 1; 480 if (sc->sc_ncores > MAXCPU) 481 return (ENXIO); 482 483 if (erratum319) 484 device_printf(dev, 485 "Erratum 319: temperature measurement may be inaccurate\n"); 486 if (bootverbose) 487 device_printf(dev, "Found %d cores and %d sensors.\n", 488 sc->sc_ncores, 489 sc->sc_ntemps > 1 ? sc->sc_ntemps * sc->sc_ncores : 1); 490 491 /* 492 * dev.amdtemp.N tree. 493 */ 494 unit = device_get_unit(dev); 495 snprintf(tn, sizeof(tn), "dev.amdtemp.%d.sensor_offset", unit); 496 TUNABLE_INT_FETCH(tn, &sc->sc_offset); 497 498 sysctlctx = device_get_sysctl_ctx(dev); 499 SYSCTL_ADD_INT(sysctlctx, 500 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 501 "sensor_offset", CTLFLAG_RW, &sc->sc_offset, 0, 502 "Temperature sensor offset"); 503 sysctlnode = SYSCTL_ADD_NODE(sysctlctx, 504 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 505 "core0", CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "Core 0"); 506 507 SYSCTL_ADD_PROC(sysctlctx, 508 SYSCTL_CHILDREN(sysctlnode), 509 OID_AUTO, "sensor0", 510 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 511 dev, CORE0_SENSOR0, amdtemp_sysctl, "IK", 512 "Core 0 / Sensor 0 temperature"); 513 514 if (family == 0x17) 515 amdtemp_probe_ccd_sensors17h(dev, model); 516 else if (family == 0x19) 517 amdtemp_probe_ccd_sensors19h(dev, model); 518 else if (sc->sc_ntemps > 1) { 519 SYSCTL_ADD_PROC(sysctlctx, 520 SYSCTL_CHILDREN(sysctlnode), 521 OID_AUTO, "sensor1", 522 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 523 dev, CORE0_SENSOR1, amdtemp_sysctl, "IK", 524 "Core 0 / Sensor 1 temperature"); 525 526 if (sc->sc_ncores > 1) { 527 sysctlnode = SYSCTL_ADD_NODE(sysctlctx, 528 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 529 OID_AUTO, "core1", CTLFLAG_RD | CTLFLAG_MPSAFE, 530 0, "Core 1"); 531 532 SYSCTL_ADD_PROC(sysctlctx, 533 SYSCTL_CHILDREN(sysctlnode), 534 OID_AUTO, "sensor0", 535 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 536 dev, CORE1_SENSOR0, amdtemp_sysctl, "IK", 537 "Core 1 / Sensor 0 temperature"); 538 539 SYSCTL_ADD_PROC(sysctlctx, 540 SYSCTL_CHILDREN(sysctlnode), 541 OID_AUTO, "sensor1", 542 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 543 dev, CORE1_SENSOR1, amdtemp_sysctl, "IK", 544 "Core 1 / Sensor 1 temperature"); 545 } 546 } 547 548 /* 549 * Try to create dev.cpu sysctl entries and setup intrhook function. 550 * This is needed because the cpu driver may be loaded late on boot, 551 * after us. 552 */ 553 amdtemp_intrhook(dev); 554 sc->sc_ich.ich_func = amdtemp_intrhook; 555 sc->sc_ich.ich_arg = dev; 556 if (config_intrhook_establish(&sc->sc_ich) != 0) { 557 device_printf(dev, "config_intrhook_establish failed!\n"); 558 return (ENXIO); 559 } 560 561 return (0); 562 } 563 564 void 565 amdtemp_intrhook(void *arg) 566 { 567 struct amdtemp_softc *sc; 568 struct sysctl_ctx_list *sysctlctx; 569 device_t dev = (device_t)arg; 570 device_t acpi, cpu, nexus; 571 amdsensor_t sensor; 572 int i; 573 574 sc = device_get_softc(dev); 575 576 /* 577 * dev.cpu.N.temperature. 578 */ 579 nexus = device_find_child(root_bus, "nexus", 0); 580 acpi = device_find_child(nexus, "acpi", 0); 581 582 for (i = 0; i < sc->sc_ncores; i++) { 583 if (sc->sc_sysctl_cpu[i] != NULL) 584 continue; 585 cpu = device_find_child(acpi, "cpu", 586 device_get_unit(dev) * sc->sc_ncores + i); 587 if (cpu != NULL) { 588 sysctlctx = device_get_sysctl_ctx(cpu); 589 590 sensor = sc->sc_ntemps > 1 ? 591 (i == 0 ? CORE0 : CORE1) : CORE0_SENSOR0; 592 sc->sc_sysctl_cpu[i] = SYSCTL_ADD_PROC(sysctlctx, 593 SYSCTL_CHILDREN(device_get_sysctl_tree(cpu)), 594 OID_AUTO, "temperature", 595 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 596 dev, sensor, amdtemp_sysctl, "IK", 597 "Current temparature"); 598 } 599 } 600 if (sc->sc_ich.ich_arg != NULL) 601 config_intrhook_disestablish(&sc->sc_ich); 602 } 603 604 int 605 amdtemp_detach(device_t dev) 606 { 607 struct amdtemp_softc *sc = device_get_softc(dev); 608 int i; 609 610 for (i = 0; i < sc->sc_ncores; i++) 611 if (sc->sc_sysctl_cpu[i] != NULL) 612 sysctl_remove_oid(sc->sc_sysctl_cpu[i], 1, 0); 613 614 /* NewBus removes the dev.amdtemp.N tree by itself. */ 615 616 return (0); 617 } 618 619 static int 620 amdtemp_sysctl(SYSCTL_HANDLER_ARGS) 621 { 622 device_t dev = (device_t)arg1; 623 struct amdtemp_softc *sc = device_get_softc(dev); 624 amdsensor_t sensor = (amdsensor_t)arg2; 625 int32_t auxtemp[2], temp; 626 int error; 627 628 switch (sensor) { 629 case CORE0: 630 auxtemp[0] = sc->sc_gettemp(dev, CORE0_SENSOR0); 631 auxtemp[1] = sc->sc_gettemp(dev, CORE0_SENSOR1); 632 temp = imax(auxtemp[0], auxtemp[1]); 633 break; 634 case CORE1: 635 auxtemp[0] = sc->sc_gettemp(dev, CORE1_SENSOR0); 636 auxtemp[1] = sc->sc_gettemp(dev, CORE1_SENSOR1); 637 temp = imax(auxtemp[0], auxtemp[1]); 638 break; 639 default: 640 temp = sc->sc_gettemp(dev, sensor); 641 break; 642 } 643 error = sysctl_handle_int(oidp, &temp, 0, req); 644 645 return (error); 646 } 647 648 #define AMDTEMP_ZERO_C_TO_K 2731 649 650 static int32_t 651 amdtemp_gettemp0f(device_t dev, amdsensor_t sensor) 652 { 653 struct amdtemp_softc *sc = device_get_softc(dev); 654 uint32_t mask, offset, temp; 655 656 /* Set Sensor/Core selector. */ 657 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 1); 658 temp &= ~(AMDTEMP_TTSR_SELCORE | AMDTEMP_TTSR_SELSENSOR); 659 switch (sensor) { 660 case CORE0_SENSOR1: 661 temp |= AMDTEMP_TTSR_SELSENSOR; 662 /* FALLTHROUGH */ 663 case CORE0_SENSOR0: 664 case CORE0: 665 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) != 0) 666 temp |= AMDTEMP_TTSR_SELCORE; 667 break; 668 case CORE1_SENSOR1: 669 temp |= AMDTEMP_TTSR_SELSENSOR; 670 /* FALLTHROUGH */ 671 case CORE1_SENSOR0: 672 case CORE1: 673 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) == 0) 674 temp |= AMDTEMP_TTSR_SELCORE; 675 break; 676 default: 677 __assert_unreachable(); 678 } 679 pci_write_config(dev, AMDTEMP_THERMTP_STAT, temp, 1); 680 681 mask = (sc->sc_flags & AMDTEMP_FLAG_CT_10BIT) != 0 ? 0x3ff : 0x3fc; 682 offset = (sc->sc_flags & AMDTEMP_FLAG_ALT_OFFSET) != 0 ? 28 : 49; 683 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 4); 684 temp = ((temp >> 14) & mask) * 5 / 2; 685 temp += AMDTEMP_ZERO_C_TO_K + (sc->sc_offset - offset) * 10; 686 687 return (temp); 688 } 689 690 static uint32_t 691 amdtemp_decode_fam10h_to_17h(int32_t sc_offset, uint32_t val, bool minus49) 692 { 693 uint32_t temp; 694 695 /* Convert raw register subfield units (0.125C) to units of 0.1C. */ 696 temp = (val & AMDTEMP_REPTMP10H_CURTMP_MASK) * 5 / 4; 697 698 if (minus49) 699 temp -= AMDTEMP_CURTMP_RANGE_ADJUST; 700 701 temp += AMDTEMP_ZERO_C_TO_K + sc_offset * 10; 702 return (temp); 703 } 704 705 static uint32_t 706 amdtemp_decode_fam10h_to_16h(int32_t sc_offset, uint32_t val) 707 { 708 bool minus49; 709 710 /* 711 * On Family 15h and higher, if CurTmpTjSel is 11b, the range is 712 * adjusted down by 49.0 degrees Celsius. (This adjustment is not 713 * documented in BKDGs prior to family 15h model 00h.) 714 */ 715 minus49 = (CPUID_TO_FAMILY(cpu_id) >= 0x15 && 716 ((val >> AMDTEMP_REPTMP10H_TJSEL_SHIFT) & 717 AMDTEMP_REPTMP10H_TJSEL_MASK) == 0x3); 718 719 return (amdtemp_decode_fam10h_to_17h(sc_offset, 720 val >> AMDTEMP_REPTMP10H_CURTMP_SHIFT, minus49)); 721 } 722 723 static uint32_t 724 amdtemp_decode_fam17h_tctl(int32_t sc_offset, uint32_t val) 725 { 726 bool minus49; 727 728 minus49 = ((val & AMDTEMP_17H_CUR_TMP_RANGE_SEL) != 0); 729 return (amdtemp_decode_fam10h_to_17h(sc_offset, 730 val >> AMDTEMP_REPTMP10H_CURTMP_SHIFT, minus49)); 731 } 732 733 static int32_t 734 amdtemp_gettemp(device_t dev, amdsensor_t sensor) 735 { 736 struct amdtemp_softc *sc = device_get_softc(dev); 737 uint32_t temp; 738 739 temp = pci_read_config(dev, AMDTEMP_REPTMP_CTRL, 4); 740 return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, temp)); 741 } 742 743 static int32_t 744 amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor) 745 { 746 struct amdtemp_softc *sc = device_get_softc(dev); 747 uint32_t val; 748 int error; 749 750 error = amdsmn_read(sc->sc_smn, AMDTEMP_15H_M60H_REPTMP_CTRL, &val); 751 KASSERT(error == 0, ("amdsmn_read")); 752 return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, val)); 753 } 754 755 static int32_t 756 amdtemp_gettemp17h(device_t dev, amdsensor_t sensor) 757 { 758 struct amdtemp_softc *sc = device_get_softc(dev); 759 uint32_t val; 760 int error; 761 762 switch (sensor) { 763 case CORE0_SENSOR0: 764 /* Tctl */ 765 error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CUR_TMP, &val); 766 KASSERT(error == 0, ("amdsmn_read")); 767 return (amdtemp_decode_fam17h_tctl(sc->sc_offset, val)); 768 case CCD_BASE ... CCD_MAX: 769 /* Tccd<N> */ 770 error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CCD_TMP_BASE + 771 (((int)sensor - CCD_BASE) * sizeof(val)), &val); 772 KASSERT(error == 0, ("amdsmn_read2")); 773 KASSERT((val & AMDTEMP_17H_CCD_TMP_VALID) != 0, 774 ("sensor %d: not valid", (int)sensor)); 775 return (amdtemp_decode_fam10h_to_17h(sc->sc_offset, val, true)); 776 default: 777 __assert_unreachable(); 778 } 779 } 780 781 static void 782 amdtemp_probe_ccd_sensors(device_t dev, uint32_t maxreg) 783 { 784 char sensor_name[16], sensor_descr[32]; 785 struct amdtemp_softc *sc; 786 uint32_t i, val; 787 int error; 788 789 sc = device_get_softc(dev); 790 for (i = 0; i < maxreg; i++) { 791 error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CCD_TMP_BASE + 792 (i * sizeof(val)), &val); 793 if (error != 0) 794 continue; 795 if ((val & AMDTEMP_17H_CCD_TMP_VALID) == 0) 796 continue; 797 798 snprintf(sensor_name, sizeof(sensor_name), "ccd%u", i); 799 snprintf(sensor_descr, sizeof(sensor_descr), 800 "CCD %u temperature (Tccd%u)", i, i); 801 802 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 803 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 804 sensor_name, CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 805 dev, CCD_BASE + i, amdtemp_sysctl, "IK", sensor_descr); 806 } 807 } 808 809 static void 810 amdtemp_probe_ccd_sensors17h(device_t dev, uint32_t model) 811 { 812 uint32_t maxreg; 813 814 switch (model) { 815 case 0x00 ... 0x2f: /* Zen1, Zen+ */ 816 maxreg = 4; 817 break; 818 case 0x30 ... 0x3f: /* Zen2 TR (Castle Peak)/EPYC (Rome) */ 819 case 0x60 ... 0x7f: /* Zen2 Ryzen (Renoir APU, Matisse) */ 820 case 0x90 ... 0x9f: /* Zen2 Ryzen (Van Gogh APU) */ 821 maxreg = 8; 822 _Static_assert((int)NUM_CCDS >= 8, ""); 823 break; 824 default: 825 device_printf(dev, 826 "Unrecognized Family 17h Model: %02xh\n", model); 827 return; 828 } 829 830 amdtemp_probe_ccd_sensors(dev, maxreg); 831 } 832 833 static void 834 amdtemp_probe_ccd_sensors19h(device_t dev, uint32_t model) 835 { 836 uint32_t maxreg; 837 838 switch (model) { 839 case 0x00 ... 0x0f: /* Zen3 EPYC "Milan" */ 840 case 0x20 ... 0x2f: /* Zen3 Ryzen "Vermeer" */ 841 maxreg = 8; 842 _Static_assert((int)NUM_CCDS >= 8, ""); 843 break; 844 default: 845 device_printf(dev, 846 "Unrecognized Family 19h Model: %02xh\n", model); 847 return; 848 } 849 850 amdtemp_probe_ccd_sensors(dev, maxreg); 851 } 852