1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2008, 2009 Rui Paulo <rpaulo@FreeBSD.org> 5 * Copyright (c) 2009 Norikatsu Shigemura <nork@FreeBSD.org> 6 * Copyright (c) 2009-2012 Jung-uk Kim <jkim@FreeBSD.org> 7 * All rights reserved. 8 * Copyright (c) 2017-2020 Conrad Meyer <cem@FreeBSD.org>. All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Driver for the AMD CPU on-die thermal sensors. 34 * Initially based on the k8temp Linux driver. 35 */ 36 37 #include <sys/cdefs.h> 38 __FBSDID("$FreeBSD$"); 39 40 #include <sys/param.h> 41 #include <sys/bus.h> 42 #include <sys/conf.h> 43 #include <sys/kernel.h> 44 #include <sys/lock.h> 45 #include <sys/module.h> 46 #include <sys/mutex.h> 47 #include <sys/sysctl.h> 48 #include <sys/systm.h> 49 50 #include <machine/cpufunc.h> 51 #include <machine/md_var.h> 52 #include <machine/specialreg.h> 53 54 #include <dev/pci/pcivar.h> 55 #include <x86/pci_cfgreg.h> 56 57 #include <dev/amdsmn/amdsmn.h> 58 59 typedef enum { 60 CORE0_SENSOR0, 61 CORE0_SENSOR1, 62 CORE1_SENSOR0, 63 CORE1_SENSOR1, 64 CORE0, 65 CORE1, 66 CCD1, 67 CCD_BASE = CCD1, 68 CCD2, 69 CCD3, 70 CCD4, 71 CCD5, 72 CCD6, 73 CCD7, 74 CCD8, 75 CCD_MAX = CCD8, 76 NUM_CCDS = CCD_MAX - CCD_BASE + 1, 77 } amdsensor_t; 78 79 struct amdtemp_softc { 80 int sc_ncores; 81 int sc_ntemps; 82 int sc_flags; 83 #define AMDTEMP_FLAG_CS_SWAP 0x01 /* ThermSenseCoreSel is inverted. */ 84 #define AMDTEMP_FLAG_CT_10BIT 0x02 /* CurTmp is 10-bit wide. */ 85 #define AMDTEMP_FLAG_ALT_OFFSET 0x04 /* CurTmp starts at -28C. */ 86 int32_t sc_offset; 87 int32_t (*sc_gettemp)(device_t, amdsensor_t); 88 struct sysctl_oid *sc_sysctl_cpu[MAXCPU]; 89 struct intr_config_hook sc_ich; 90 device_t sc_smn; 91 struct mtx sc_lock; 92 }; 93 94 /* 95 * N.B. The numbers in macro names below are significant and represent CPU 96 * family and model numbers. Do not make up fictitious family or model numbers 97 * when adding support for new devices. 98 */ 99 #define VENDORID_AMD 0x1022 100 #define DEVICEID_AMD_MISC0F 0x1103 101 #define DEVICEID_AMD_MISC10 0x1203 102 #define DEVICEID_AMD_MISC11 0x1303 103 #define DEVICEID_AMD_MISC14 0x1703 104 #define DEVICEID_AMD_MISC15 0x1603 105 #define DEVICEID_AMD_MISC15_M10H 0x1403 106 #define DEVICEID_AMD_MISC15_M30H 0x141d 107 #define DEVICEID_AMD_MISC15_M60H_ROOT 0x1576 108 #define DEVICEID_AMD_MISC16 0x1533 109 #define DEVICEID_AMD_MISC16_M30H 0x1583 110 #define DEVICEID_AMD_HOSTB17H_ROOT 0x1450 111 #define DEVICEID_AMD_HOSTB17H_M10H_ROOT 0x15d0 112 #define DEVICEID_AMD_HOSTB17H_M30H_ROOT 0x1480 /* Also M70H, F19H M00H/M20H */ 113 #define DEVICEID_AMD_HOSTB17H_M60H_ROOT 0x1630 114 115 static const struct amdtemp_product { 116 uint16_t amdtemp_vendorid; 117 uint16_t amdtemp_deviceid; 118 /* 119 * 0xFC register is only valid on the D18F3 PCI device; SMN temp 120 * drivers do not attach to that device. 121 */ 122 bool amdtemp_has_cpuid; 123 } amdtemp_products[] = { 124 { VENDORID_AMD, DEVICEID_AMD_MISC0F, true }, 125 { VENDORID_AMD, DEVICEID_AMD_MISC10, true }, 126 { VENDORID_AMD, DEVICEID_AMD_MISC11, true }, 127 { VENDORID_AMD, DEVICEID_AMD_MISC14, true }, 128 { VENDORID_AMD, DEVICEID_AMD_MISC15, true }, 129 { VENDORID_AMD, DEVICEID_AMD_MISC15_M10H, true }, 130 { VENDORID_AMD, DEVICEID_AMD_MISC15_M30H, true }, 131 { VENDORID_AMD, DEVICEID_AMD_MISC15_M60H_ROOT, false }, 132 { VENDORID_AMD, DEVICEID_AMD_MISC16, true }, 133 { VENDORID_AMD, DEVICEID_AMD_MISC16_M30H, true }, 134 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_ROOT, false }, 135 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M10H_ROOT, false }, 136 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M30H_ROOT, false }, 137 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M60H_ROOT, false }, 138 }; 139 140 /* 141 * Reported Temperature Control Register, family 0Fh-15h (some models), 16h. 142 */ 143 #define AMDTEMP_REPTMP_CTRL 0xa4 144 145 #define AMDTEMP_REPTMP10H_CURTMP_MASK 0x7ff 146 #define AMDTEMP_REPTMP10H_CURTMP_SHIFT 21 147 #define AMDTEMP_REPTMP10H_TJSEL_MASK 0x3 148 #define AMDTEMP_REPTMP10H_TJSEL_SHIFT 16 149 150 /* 151 * Reported Temperature, Family 15h, M60+ 152 * 153 * Same register bit definitions as other Family 15h CPUs, but access is 154 * indirect via SMN, like Family 17h. 155 */ 156 #define AMDTEMP_15H_M60H_REPTMP_CTRL 0xd8200ca4 157 158 /* 159 * Reported Temperature, Family 17h 160 * 161 * According to AMD OSRR for 17H, section 4.2.1, bits 31-21 of this register 162 * provide the current temp. bit 19, when clear, means the temp is reported in 163 * a range 0.."225C" (probable typo for 255C), and when set changes the range 164 * to -49..206C. 165 */ 166 #define AMDTEMP_17H_CUR_TMP 0x59800 167 #define AMDTEMP_17H_CUR_TMP_RANGE_SEL (1u << 19) 168 /* 169 * Bits 16-17, when set, mean that CUR_TMP is read-write. When it is, the 170 * 49 degree offset should apply as well. This was revealed in a Linux 171 * patch from an AMD employee. 172 */ 173 #define AMDTEMP_17H_CUR_TMP_TJ_SEL ((1u << 17) | (1u << 16)) 174 /* 175 * The following register set was discovered experimentally by Ondrej Čerman 176 * and collaborators, but is not (yet) documented in a PPR/OSRR (other than 177 * the M70H PPR SMN memory map showing [0x59800, +0x314] as allocated to 178 * SMU::THM). It seems plausible and the Linux sensor folks have adopted it. 179 */ 180 #define AMDTEMP_17H_CCD_TMP_BASE 0x59954 181 #define AMDTEMP_17H_CCD_TMP_VALID (1u << 11) 182 183 /* 184 * AMD temperature range adjustment, in deciKelvins (i.e., 49.0 Celsius). 185 */ 186 #define AMDTEMP_CURTMP_RANGE_ADJUST 490 187 188 /* 189 * Thermaltrip Status Register (Family 0Fh only) 190 */ 191 #define AMDTEMP_THERMTP_STAT 0xe4 192 #define AMDTEMP_TTSR_SELCORE 0x04 193 #define AMDTEMP_TTSR_SELSENSOR 0x40 194 195 /* 196 * DRAM Configuration High Register 197 */ 198 #define AMDTEMP_DRAM_CONF_HIGH 0x94 /* Function 2 */ 199 #define AMDTEMP_DRAM_MODE_DDR3 0x0100 200 201 /* 202 * CPU Family/Model Register 203 */ 204 #define AMDTEMP_CPUID 0xfc 205 206 /* 207 * Device methods. 208 */ 209 static void amdtemp_identify(driver_t *driver, device_t parent); 210 static int amdtemp_probe(device_t dev); 211 static int amdtemp_attach(device_t dev); 212 static void amdtemp_intrhook(void *arg); 213 static int amdtemp_detach(device_t dev); 214 static int32_t amdtemp_gettemp0f(device_t dev, amdsensor_t sensor); 215 static int32_t amdtemp_gettemp(device_t dev, amdsensor_t sensor); 216 static int32_t amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor); 217 static int32_t amdtemp_gettemp17h(device_t dev, amdsensor_t sensor); 218 static void amdtemp_probe_ccd_sensors17h(device_t dev, uint32_t model); 219 static void amdtemp_probe_ccd_sensors19h(device_t dev, uint32_t model); 220 static int amdtemp_sysctl(SYSCTL_HANDLER_ARGS); 221 222 static device_method_t amdtemp_methods[] = { 223 /* Device interface */ 224 DEVMETHOD(device_identify, amdtemp_identify), 225 DEVMETHOD(device_probe, amdtemp_probe), 226 DEVMETHOD(device_attach, amdtemp_attach), 227 DEVMETHOD(device_detach, amdtemp_detach), 228 229 DEVMETHOD_END 230 }; 231 232 static driver_t amdtemp_driver = { 233 "amdtemp", 234 amdtemp_methods, 235 sizeof(struct amdtemp_softc), 236 }; 237 238 DRIVER_MODULE(amdtemp, hostb, amdtemp_driver, NULL, NULL); 239 MODULE_VERSION(amdtemp, 1); 240 MODULE_DEPEND(amdtemp, amdsmn, 1, 1, 1); 241 MODULE_PNP_INFO("U16:vendor;U16:device", pci, amdtemp, amdtemp_products, 242 nitems(amdtemp_products)); 243 244 static bool 245 amdtemp_match(device_t dev, const struct amdtemp_product **product_out) 246 { 247 int i; 248 uint16_t vendor, devid; 249 250 vendor = pci_get_vendor(dev); 251 devid = pci_get_device(dev); 252 253 for (i = 0; i < nitems(amdtemp_products); i++) { 254 if (vendor == amdtemp_products[i].amdtemp_vendorid && 255 devid == amdtemp_products[i].amdtemp_deviceid) { 256 if (product_out != NULL) 257 *product_out = &amdtemp_products[i]; 258 return (true); 259 } 260 } 261 return (false); 262 } 263 264 static void 265 amdtemp_identify(driver_t *driver, device_t parent) 266 { 267 device_t child; 268 269 /* Make sure we're not being doubly invoked. */ 270 if (device_find_child(parent, "amdtemp", -1) != NULL) 271 return; 272 273 if (amdtemp_match(parent, NULL)) { 274 child = device_add_child(parent, "amdtemp", -1); 275 if (child == NULL) 276 device_printf(parent, "add amdtemp child failed\n"); 277 } 278 } 279 280 static int 281 amdtemp_probe(device_t dev) 282 { 283 uint32_t family, model; 284 285 if (resource_disabled("amdtemp", 0)) 286 return (ENXIO); 287 if (!amdtemp_match(device_get_parent(dev), NULL)) 288 return (ENXIO); 289 290 family = CPUID_TO_FAMILY(cpu_id); 291 model = CPUID_TO_MODEL(cpu_id); 292 293 switch (family) { 294 case 0x0f: 295 if ((model == 0x04 && (cpu_id & CPUID_STEPPING) == 0) || 296 (model == 0x05 && (cpu_id & CPUID_STEPPING) <= 1)) 297 return (ENXIO); 298 break; 299 case 0x10: 300 case 0x11: 301 case 0x12: 302 case 0x14: 303 case 0x15: 304 case 0x16: 305 case 0x17: 306 case 0x19: 307 break; 308 default: 309 return (ENXIO); 310 } 311 device_set_desc(dev, "AMD CPU On-Die Thermal Sensors"); 312 313 return (BUS_PROBE_GENERIC); 314 } 315 316 static int 317 amdtemp_attach(device_t dev) 318 { 319 char tn[32]; 320 u_int regs[4]; 321 const struct amdtemp_product *product; 322 struct amdtemp_softc *sc; 323 struct sysctl_ctx_list *sysctlctx; 324 struct sysctl_oid *sysctlnode; 325 uint32_t cpuid, family, model; 326 u_int bid; 327 int erratum319, unit; 328 bool needsmn; 329 330 sc = device_get_softc(dev); 331 erratum319 = 0; 332 needsmn = false; 333 334 if (!amdtemp_match(device_get_parent(dev), &product)) 335 return (ENXIO); 336 337 cpuid = cpu_id; 338 family = CPUID_TO_FAMILY(cpuid); 339 model = CPUID_TO_MODEL(cpuid); 340 341 /* 342 * This checks for the byzantine condition of running a heterogenous 343 * revision multi-socket system where the attach thread is potentially 344 * probing a remote socket's PCI device. 345 * 346 * Currently, such scenarios are unsupported on models using the SMN 347 * (because on those models, amdtemp(4) attaches to a different PCI 348 * device than the one that contains AMDTEMP_CPUID). 349 * 350 * The ancient 0x0F family of devices only supports this register from 351 * models 40h+. 352 */ 353 if (product->amdtemp_has_cpuid && (family > 0x0f || 354 (family == 0x0f && model >= 0x40))) { 355 cpuid = pci_read_config(device_get_parent(dev), AMDTEMP_CPUID, 356 4); 357 family = CPUID_TO_FAMILY(cpuid); 358 model = CPUID_TO_MODEL(cpuid); 359 } 360 361 switch (family) { 362 case 0x0f: 363 /* 364 * Thermaltrip Status Register 365 * 366 * - ThermSenseCoreSel 367 * 368 * Revision F & G: 0 - Core1, 1 - Core0 369 * Other: 0 - Core0, 1 - Core1 370 * 371 * - CurTmp 372 * 373 * Revision G: bits 23-14 374 * Other: bits 23-16 375 * 376 * XXX According to the BKDG, CurTmp, ThermSenseSel and 377 * ThermSenseCoreSel bits were introduced in Revision F 378 * but CurTmp seems working fine as early as Revision C. 379 * However, it is not clear whether ThermSenseSel and/or 380 * ThermSenseCoreSel work in undocumented cases as well. 381 * In fact, the Linux driver suggests it may not work but 382 * we just assume it does until we find otherwise. 383 * 384 * XXX According to Linux, CurTmp starts at -28C on 385 * Socket AM2 Revision G processors, which is not 386 * documented anywhere. 387 */ 388 if (model >= 0x40) 389 sc->sc_flags |= AMDTEMP_FLAG_CS_SWAP; 390 if (model >= 0x60 && model != 0xc1) { 391 do_cpuid(0x80000001, regs); 392 bid = (regs[1] >> 9) & 0x1f; 393 switch (model) { 394 case 0x68: /* Socket S1g1 */ 395 case 0x6c: 396 case 0x7c: 397 break; 398 case 0x6b: /* Socket AM2 and ASB1 (2 cores) */ 399 if (bid != 0x0b && bid != 0x0c) 400 sc->sc_flags |= 401 AMDTEMP_FLAG_ALT_OFFSET; 402 break; 403 case 0x6f: /* Socket AM2 and ASB1 (1 core) */ 404 case 0x7f: 405 if (bid != 0x07 && bid != 0x09 && 406 bid != 0x0c) 407 sc->sc_flags |= 408 AMDTEMP_FLAG_ALT_OFFSET; 409 break; 410 default: 411 sc->sc_flags |= AMDTEMP_FLAG_ALT_OFFSET; 412 } 413 sc->sc_flags |= AMDTEMP_FLAG_CT_10BIT; 414 } 415 416 /* 417 * There are two sensors per core. 418 */ 419 sc->sc_ntemps = 2; 420 421 sc->sc_gettemp = amdtemp_gettemp0f; 422 break; 423 case 0x10: 424 /* 425 * Erratum 319 Inaccurate Temperature Measurement 426 * 427 * http://support.amd.com/us/Processor_TechDocs/41322.pdf 428 */ 429 do_cpuid(0x80000001, regs); 430 switch ((regs[1] >> 28) & 0xf) { 431 case 0: /* Socket F */ 432 erratum319 = 1; 433 break; 434 case 1: /* Socket AM2+ or AM3 */ 435 if ((pci_cfgregread(pci_get_bus(dev), 436 pci_get_slot(dev), 2, AMDTEMP_DRAM_CONF_HIGH, 2) & 437 AMDTEMP_DRAM_MODE_DDR3) != 0 || model > 0x04 || 438 (model == 0x04 && (cpuid & CPUID_STEPPING) >= 3)) 439 break; 440 /* XXX 00100F42h (RB-C2) exists in both formats. */ 441 erratum319 = 1; 442 break; 443 } 444 /* FALLTHROUGH */ 445 case 0x11: 446 case 0x12: 447 case 0x14: 448 case 0x15: 449 case 0x16: 450 sc->sc_ntemps = 1; 451 /* 452 * Some later (60h+) models of family 15h use a similar SMN 453 * network as family 17h. (However, the register index differs 454 * from 17h and the decoding matches other 10h-15h models, 455 * which differ from 17h.) 456 */ 457 if (family == 0x15 && model >= 0x60) { 458 sc->sc_gettemp = amdtemp_gettemp15hm60h; 459 needsmn = true; 460 } else 461 sc->sc_gettemp = amdtemp_gettemp; 462 break; 463 case 0x17: 464 case 0x19: 465 sc->sc_ntemps = 1; 466 sc->sc_gettemp = amdtemp_gettemp17h; 467 needsmn = true; 468 break; 469 default: 470 device_printf(dev, "Bogus family 0x%x\n", family); 471 return (ENXIO); 472 } 473 474 if (needsmn) { 475 sc->sc_smn = device_find_child( 476 device_get_parent(dev), "amdsmn", -1); 477 if (sc->sc_smn == NULL) { 478 if (bootverbose) 479 device_printf(dev, "No SMN device found\n"); 480 return (ENXIO); 481 } 482 } 483 484 /* Find number of cores per package. */ 485 sc->sc_ncores = (amd_feature2 & AMDID2_CMP) != 0 ? 486 (cpu_procinfo2 & AMDID_CMP_CORES) + 1 : 1; 487 if (sc->sc_ncores > MAXCPU) 488 return (ENXIO); 489 490 mtx_init(&sc->sc_lock, "amdtemp", NULL, MTX_DEF); 491 if (erratum319) 492 device_printf(dev, 493 "Erratum 319: temperature measurement may be inaccurate\n"); 494 if (bootverbose) 495 device_printf(dev, "Found %d cores and %d sensors.\n", 496 sc->sc_ncores, 497 sc->sc_ntemps > 1 ? sc->sc_ntemps * sc->sc_ncores : 1); 498 499 /* 500 * dev.amdtemp.N tree. 501 */ 502 unit = device_get_unit(dev); 503 snprintf(tn, sizeof(tn), "dev.amdtemp.%d.sensor_offset", unit); 504 TUNABLE_INT_FETCH(tn, &sc->sc_offset); 505 506 sysctlctx = device_get_sysctl_ctx(dev); 507 SYSCTL_ADD_INT(sysctlctx, 508 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 509 "sensor_offset", CTLFLAG_RW, &sc->sc_offset, 0, 510 "Temperature sensor offset"); 511 sysctlnode = SYSCTL_ADD_NODE(sysctlctx, 512 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 513 "core0", CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "Core 0"); 514 515 SYSCTL_ADD_PROC(sysctlctx, 516 SYSCTL_CHILDREN(sysctlnode), 517 OID_AUTO, "sensor0", 518 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 519 dev, CORE0_SENSOR0, amdtemp_sysctl, "IK", 520 "Core 0 / Sensor 0 temperature"); 521 522 if (family == 0x17) 523 amdtemp_probe_ccd_sensors17h(dev, model); 524 else if (family == 0x19) 525 amdtemp_probe_ccd_sensors19h(dev, model); 526 else if (sc->sc_ntemps > 1) { 527 SYSCTL_ADD_PROC(sysctlctx, 528 SYSCTL_CHILDREN(sysctlnode), 529 OID_AUTO, "sensor1", 530 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 531 dev, CORE0_SENSOR1, amdtemp_sysctl, "IK", 532 "Core 0 / Sensor 1 temperature"); 533 534 if (sc->sc_ncores > 1) { 535 sysctlnode = SYSCTL_ADD_NODE(sysctlctx, 536 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 537 OID_AUTO, "core1", CTLFLAG_RD | CTLFLAG_MPSAFE, 538 0, "Core 1"); 539 540 SYSCTL_ADD_PROC(sysctlctx, 541 SYSCTL_CHILDREN(sysctlnode), 542 OID_AUTO, "sensor0", 543 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 544 dev, CORE1_SENSOR0, amdtemp_sysctl, "IK", 545 "Core 1 / Sensor 0 temperature"); 546 547 SYSCTL_ADD_PROC(sysctlctx, 548 SYSCTL_CHILDREN(sysctlnode), 549 OID_AUTO, "sensor1", 550 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 551 dev, CORE1_SENSOR1, amdtemp_sysctl, "IK", 552 "Core 1 / Sensor 1 temperature"); 553 } 554 } 555 556 /* 557 * Try to create dev.cpu sysctl entries and setup intrhook function. 558 * This is needed because the cpu driver may be loaded late on boot, 559 * after us. 560 */ 561 amdtemp_intrhook(dev); 562 sc->sc_ich.ich_func = amdtemp_intrhook; 563 sc->sc_ich.ich_arg = dev; 564 if (config_intrhook_establish(&sc->sc_ich) != 0) { 565 device_printf(dev, "config_intrhook_establish failed!\n"); 566 return (ENXIO); 567 } 568 569 return (0); 570 } 571 572 void 573 amdtemp_intrhook(void *arg) 574 { 575 struct amdtemp_softc *sc; 576 struct sysctl_ctx_list *sysctlctx; 577 device_t dev = (device_t)arg; 578 device_t acpi, cpu, nexus; 579 amdsensor_t sensor; 580 int i; 581 582 sc = device_get_softc(dev); 583 584 /* 585 * dev.cpu.N.temperature. 586 */ 587 nexus = device_find_child(root_bus, "nexus", 0); 588 acpi = device_find_child(nexus, "acpi", 0); 589 590 for (i = 0; i < sc->sc_ncores; i++) { 591 if (sc->sc_sysctl_cpu[i] != NULL) 592 continue; 593 cpu = device_find_child(acpi, "cpu", 594 device_get_unit(dev) * sc->sc_ncores + i); 595 if (cpu != NULL) { 596 sysctlctx = device_get_sysctl_ctx(cpu); 597 598 sensor = sc->sc_ntemps > 1 ? 599 (i == 0 ? CORE0 : CORE1) : CORE0_SENSOR0; 600 sc->sc_sysctl_cpu[i] = SYSCTL_ADD_PROC(sysctlctx, 601 SYSCTL_CHILDREN(device_get_sysctl_tree(cpu)), 602 OID_AUTO, "temperature", 603 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 604 dev, sensor, amdtemp_sysctl, "IK", 605 "Current temparature"); 606 } 607 } 608 if (sc->sc_ich.ich_arg != NULL) 609 config_intrhook_disestablish(&sc->sc_ich); 610 } 611 612 int 613 amdtemp_detach(device_t dev) 614 { 615 struct amdtemp_softc *sc = device_get_softc(dev); 616 int i; 617 618 for (i = 0; i < sc->sc_ncores; i++) 619 if (sc->sc_sysctl_cpu[i] != NULL) 620 sysctl_remove_oid(sc->sc_sysctl_cpu[i], 1, 0); 621 622 /* NewBus removes the dev.amdtemp.N tree by itself. */ 623 624 mtx_destroy(&sc->sc_lock); 625 return (0); 626 } 627 628 static int 629 amdtemp_sysctl(SYSCTL_HANDLER_ARGS) 630 { 631 device_t dev = (device_t)arg1; 632 struct amdtemp_softc *sc = device_get_softc(dev); 633 amdsensor_t sensor = (amdsensor_t)arg2; 634 int32_t auxtemp[2], temp; 635 int error; 636 637 switch (sensor) { 638 case CORE0: 639 auxtemp[0] = sc->sc_gettemp(dev, CORE0_SENSOR0); 640 auxtemp[1] = sc->sc_gettemp(dev, CORE0_SENSOR1); 641 temp = imax(auxtemp[0], auxtemp[1]); 642 break; 643 case CORE1: 644 auxtemp[0] = sc->sc_gettemp(dev, CORE1_SENSOR0); 645 auxtemp[1] = sc->sc_gettemp(dev, CORE1_SENSOR1); 646 temp = imax(auxtemp[0], auxtemp[1]); 647 break; 648 default: 649 temp = sc->sc_gettemp(dev, sensor); 650 break; 651 } 652 error = sysctl_handle_int(oidp, &temp, 0, req); 653 654 return (error); 655 } 656 657 #define AMDTEMP_ZERO_C_TO_K 2731 658 659 static int32_t 660 amdtemp_gettemp0f(device_t dev, amdsensor_t sensor) 661 { 662 struct amdtemp_softc *sc = device_get_softc(dev); 663 uint32_t mask, offset, temp; 664 665 mtx_lock(&sc->sc_lock); 666 667 /* Set Sensor/Core selector. */ 668 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 1); 669 temp &= ~(AMDTEMP_TTSR_SELCORE | AMDTEMP_TTSR_SELSENSOR); 670 switch (sensor) { 671 case CORE0_SENSOR1: 672 temp |= AMDTEMP_TTSR_SELSENSOR; 673 /* FALLTHROUGH */ 674 case CORE0_SENSOR0: 675 case CORE0: 676 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) != 0) 677 temp |= AMDTEMP_TTSR_SELCORE; 678 break; 679 case CORE1_SENSOR1: 680 temp |= AMDTEMP_TTSR_SELSENSOR; 681 /* FALLTHROUGH */ 682 case CORE1_SENSOR0: 683 case CORE1: 684 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) == 0) 685 temp |= AMDTEMP_TTSR_SELCORE; 686 break; 687 default: 688 __assert_unreachable(); 689 } 690 pci_write_config(dev, AMDTEMP_THERMTP_STAT, temp, 1); 691 692 mask = (sc->sc_flags & AMDTEMP_FLAG_CT_10BIT) != 0 ? 0x3ff : 0x3fc; 693 offset = (sc->sc_flags & AMDTEMP_FLAG_ALT_OFFSET) != 0 ? 28 : 49; 694 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 4); 695 temp = ((temp >> 14) & mask) * 5 / 2; 696 temp += AMDTEMP_ZERO_C_TO_K + (sc->sc_offset - offset) * 10; 697 698 mtx_unlock(&sc->sc_lock); 699 return (temp); 700 } 701 702 static uint32_t 703 amdtemp_decode_fam10h_to_17h(int32_t sc_offset, uint32_t val, bool minus49) 704 { 705 uint32_t temp; 706 707 /* Convert raw register subfield units (0.125C) to units of 0.1C. */ 708 temp = (val & AMDTEMP_REPTMP10H_CURTMP_MASK) * 5 / 4; 709 710 if (minus49) 711 temp -= AMDTEMP_CURTMP_RANGE_ADJUST; 712 713 temp += AMDTEMP_ZERO_C_TO_K + sc_offset * 10; 714 return (temp); 715 } 716 717 static uint32_t 718 amdtemp_decode_fam10h_to_16h(int32_t sc_offset, uint32_t val) 719 { 720 bool minus49; 721 722 /* 723 * On Family 15h and higher, if CurTmpTjSel is 11b, the range is 724 * adjusted down by 49.0 degrees Celsius. (This adjustment is not 725 * documented in BKDGs prior to family 15h model 00h.) 726 */ 727 minus49 = (CPUID_TO_FAMILY(cpu_id) >= 0x15 && 728 ((val >> AMDTEMP_REPTMP10H_TJSEL_SHIFT) & 729 AMDTEMP_REPTMP10H_TJSEL_MASK) == 0x3); 730 731 return (amdtemp_decode_fam10h_to_17h(sc_offset, 732 val >> AMDTEMP_REPTMP10H_CURTMP_SHIFT, minus49)); 733 } 734 735 static uint32_t 736 amdtemp_decode_fam17h_tctl(int32_t sc_offset, uint32_t val) 737 { 738 bool minus49; 739 740 minus49 = ((val & AMDTEMP_17H_CUR_TMP_RANGE_SEL) != 0) 741 || ((val & AMDTEMP_17H_CUR_TMP_TJ_SEL) == AMDTEMP_17H_CUR_TMP_TJ_SEL); 742 return (amdtemp_decode_fam10h_to_17h(sc_offset, 743 val >> AMDTEMP_REPTMP10H_CURTMP_SHIFT, minus49)); 744 } 745 746 static int32_t 747 amdtemp_gettemp(device_t dev, amdsensor_t sensor) 748 { 749 struct amdtemp_softc *sc = device_get_softc(dev); 750 uint32_t temp; 751 752 temp = pci_read_config(dev, AMDTEMP_REPTMP_CTRL, 4); 753 return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, temp)); 754 } 755 756 static int32_t 757 amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor) 758 { 759 struct amdtemp_softc *sc = device_get_softc(dev); 760 uint32_t val; 761 int error __diagused; 762 763 error = amdsmn_read(sc->sc_smn, AMDTEMP_15H_M60H_REPTMP_CTRL, &val); 764 KASSERT(error == 0, ("amdsmn_read")); 765 return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, val)); 766 } 767 768 static int32_t 769 amdtemp_gettemp17h(device_t dev, amdsensor_t sensor) 770 { 771 struct amdtemp_softc *sc = device_get_softc(dev); 772 uint32_t val; 773 int error __diagused; 774 775 switch (sensor) { 776 case CORE0_SENSOR0: 777 /* Tctl */ 778 error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CUR_TMP, &val); 779 KASSERT(error == 0, ("amdsmn_read")); 780 return (amdtemp_decode_fam17h_tctl(sc->sc_offset, val)); 781 case CCD_BASE ... CCD_MAX: 782 /* Tccd<N> */ 783 error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CCD_TMP_BASE + 784 (((int)sensor - CCD_BASE) * sizeof(val)), &val); 785 KASSERT(error == 0, ("amdsmn_read2")); 786 KASSERT((val & AMDTEMP_17H_CCD_TMP_VALID) != 0, 787 ("sensor %d: not valid", (int)sensor)); 788 return (amdtemp_decode_fam10h_to_17h(sc->sc_offset, val, true)); 789 default: 790 __assert_unreachable(); 791 } 792 } 793 794 static void 795 amdtemp_probe_ccd_sensors(device_t dev, uint32_t maxreg) 796 { 797 char sensor_name[16], sensor_descr[32]; 798 struct amdtemp_softc *sc; 799 uint32_t i, val; 800 int error; 801 802 sc = device_get_softc(dev); 803 for (i = 0; i < maxreg; i++) { 804 error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CCD_TMP_BASE + 805 (i * sizeof(val)), &val); 806 if (error != 0) 807 continue; 808 if ((val & AMDTEMP_17H_CCD_TMP_VALID) == 0) 809 continue; 810 811 snprintf(sensor_name, sizeof(sensor_name), "ccd%u", i); 812 snprintf(sensor_descr, sizeof(sensor_descr), 813 "CCD %u temperature (Tccd%u)", i, i); 814 815 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 816 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 817 sensor_name, CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 818 dev, CCD_BASE + i, amdtemp_sysctl, "IK", sensor_descr); 819 } 820 } 821 822 static void 823 amdtemp_probe_ccd_sensors17h(device_t dev, uint32_t model) 824 { 825 uint32_t maxreg; 826 827 switch (model) { 828 case 0x00 ... 0x2f: /* Zen1, Zen+ */ 829 maxreg = 4; 830 break; 831 case 0x30 ... 0x3f: /* Zen2 TR (Castle Peak)/EPYC (Rome) */ 832 case 0x60 ... 0x7f: /* Zen2 Ryzen (Renoir APU, Matisse) */ 833 case 0x90 ... 0x9f: /* Zen2 Ryzen (Van Gogh APU) */ 834 maxreg = 8; 835 _Static_assert((int)NUM_CCDS >= 8, ""); 836 break; 837 default: 838 device_printf(dev, 839 "Unrecognized Family 17h Model: %02xh\n", model); 840 return; 841 } 842 843 amdtemp_probe_ccd_sensors(dev, maxreg); 844 } 845 846 static void 847 amdtemp_probe_ccd_sensors19h(device_t dev, uint32_t model) 848 { 849 uint32_t maxreg; 850 851 switch (model) { 852 case 0x00 ... 0x0f: /* Zen3 EPYC "Milan" */ 853 case 0x20 ... 0x2f: /* Zen3 Ryzen "Vermeer" */ 854 maxreg = 8; 855 _Static_assert((int)NUM_CCDS >= 8, ""); 856 break; 857 default: 858 device_printf(dev, 859 "Unrecognized Family 19h Model: %02xh\n", model); 860 return; 861 } 862 863 amdtemp_probe_ccd_sensors(dev, maxreg); 864 } 865