1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008, 2009 Rui Paulo <rpaulo@FreeBSD.org> 5 * Copyright (c) 2009 Norikatsu Shigemura <nork@FreeBSD.org> 6 * Copyright (c) 2009-2012 Jung-uk Kim <jkim@FreeBSD.org> 7 * All rights reserved. 8 * Copyright (c) 2017-2020 Conrad Meyer <cem@FreeBSD.org>. All rights reserved. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 22 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 23 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 26 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 27 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 28 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Driver for the AMD CPU on-die thermal sensors. 34 * Initially based on the k8temp Linux driver. 35 */ 36 37 #include <sys/cdefs.h> 38 __FBSDID("$FreeBSD$"); 39 40 #include <sys/param.h> 41 #include <sys/bus.h> 42 #include <sys/conf.h> 43 #include <sys/kernel.h> 44 #include <sys/module.h> 45 #include <sys/sysctl.h> 46 #include <sys/systm.h> 47 48 #include <machine/cpufunc.h> 49 #include <machine/md_var.h> 50 #include <machine/specialreg.h> 51 52 #include <dev/pci/pcivar.h> 53 #include <x86/pci_cfgreg.h> 54 55 #include <dev/amdsmn/amdsmn.h> 56 57 typedef enum { 58 CORE0_SENSOR0, 59 CORE0_SENSOR1, 60 CORE1_SENSOR0, 61 CORE1_SENSOR1, 62 CORE0, 63 CORE1, 64 CCD1, 65 CCD_BASE = CCD1, 66 CCD2, 67 CCD3, 68 CCD4, 69 CCD5, 70 CCD6, 71 CCD7, 72 CCD8, 73 CCD_MAX = CCD8, 74 NUM_CCDS = CCD_MAX - CCD_BASE + 1, 75 } amdsensor_t; 76 77 struct amdtemp_softc { 78 int sc_ncores; 79 int sc_ntemps; 80 int sc_flags; 81 #define AMDTEMP_FLAG_CS_SWAP 0x01 /* ThermSenseCoreSel is inverted. */ 82 #define AMDTEMP_FLAG_CT_10BIT 0x02 /* CurTmp is 10-bit wide. */ 83 #define AMDTEMP_FLAG_ALT_OFFSET 0x04 /* CurTmp starts at -28C. */ 84 int32_t sc_offset; 85 int32_t (*sc_gettemp)(device_t, amdsensor_t); 86 struct sysctl_oid *sc_sysctl_cpu[MAXCPU]; 87 struct intr_config_hook sc_ich; 88 device_t sc_smn; 89 }; 90 91 /* 92 * N.B. The numbers in macro names below are significant and represent CPU 93 * family and model numbers. Do not make up fictitious family or model numbers 94 * when adding support for new devices. 95 */ 96 #define VENDORID_AMD 0x1022 97 #define DEVICEID_AMD_MISC0F 0x1103 98 #define DEVICEID_AMD_MISC10 0x1203 99 #define DEVICEID_AMD_MISC11 0x1303 100 #define DEVICEID_AMD_MISC14 0x1703 101 #define DEVICEID_AMD_MISC15 0x1603 102 #define DEVICEID_AMD_MISC15_M10H 0x1403 103 #define DEVICEID_AMD_MISC15_M30H 0x141d 104 #define DEVICEID_AMD_MISC15_M60H_ROOT 0x1576 105 #define DEVICEID_AMD_MISC16 0x1533 106 #define DEVICEID_AMD_MISC16_M30H 0x1583 107 #define DEVICEID_AMD_HOSTB17H_ROOT 0x1450 108 #define DEVICEID_AMD_HOSTB17H_M10H_ROOT 0x15d0 109 #define DEVICEID_AMD_HOSTB17H_M30H_ROOT 0x1480 /* Also M70h. */ 110 #define DEVICEID_AMD_HOSTB17H_M60H_ROOT 0x1630 111 112 static const struct amdtemp_product { 113 uint16_t amdtemp_vendorid; 114 uint16_t amdtemp_deviceid; 115 /* 116 * 0xFC register is only valid on the D18F3 PCI device; SMN temp 117 * drivers do not attach to that device. 118 */ 119 bool amdtemp_has_cpuid; 120 } amdtemp_products[] = { 121 { VENDORID_AMD, DEVICEID_AMD_MISC0F, true }, 122 { VENDORID_AMD, DEVICEID_AMD_MISC10, true }, 123 { VENDORID_AMD, DEVICEID_AMD_MISC11, true }, 124 { VENDORID_AMD, DEVICEID_AMD_MISC14, true }, 125 { VENDORID_AMD, DEVICEID_AMD_MISC15, true }, 126 { VENDORID_AMD, DEVICEID_AMD_MISC15_M10H, true }, 127 { VENDORID_AMD, DEVICEID_AMD_MISC15_M30H, true }, 128 { VENDORID_AMD, DEVICEID_AMD_MISC15_M60H_ROOT, false }, 129 { VENDORID_AMD, DEVICEID_AMD_MISC16, true }, 130 { VENDORID_AMD, DEVICEID_AMD_MISC16_M30H, true }, 131 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_ROOT, false }, 132 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M10H_ROOT, false }, 133 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M30H_ROOT, false }, 134 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M60H_ROOT, false }, 135 }; 136 137 /* 138 * Reported Temperature Control Register, family 0Fh-15h (some models), 16h. 139 */ 140 #define AMDTEMP_REPTMP_CTRL 0xa4 141 142 #define AMDTEMP_REPTMP10H_CURTMP_MASK 0x7ff 143 #define AMDTEMP_REPTMP10H_CURTMP_SHIFT 21 144 #define AMDTEMP_REPTMP10H_TJSEL_MASK 0x3 145 #define AMDTEMP_REPTMP10H_TJSEL_SHIFT 16 146 147 /* 148 * Reported Temperature, Family 15h, M60+ 149 * 150 * Same register bit definitions as other Family 15h CPUs, but access is 151 * indirect via SMN, like Family 17h. 152 */ 153 #define AMDTEMP_15H_M60H_REPTMP_CTRL 0xd8200ca4 154 155 /* 156 * Reported Temperature, Family 17h 157 * 158 * According to AMD OSRR for 17H, section 4.2.1, bits 31-21 of this register 159 * provide the current temp. bit 19, when clear, means the temp is reported in 160 * a range 0.."225C" (probable typo for 255C), and when set changes the range 161 * to -49..206C. 162 */ 163 #define AMDTEMP_17H_CUR_TMP 0x59800 164 #define AMDTEMP_17H_CUR_TMP_RANGE_SEL (1u << 19) 165 /* 166 * The following register set was discovered experimentally by Ondrej Čerman 167 * and collaborators, but is not (yet) documented in a PPR/OSRR (other than 168 * the M70H PPR SMN memory map showing [0x59800, +0x314] as allocated to 169 * SMU::THM). It seems plausible and the Linux sensor folks have adopted it. 170 */ 171 #define AMDTEMP_17H_CCD_TMP_BASE 0x59954 172 #define AMDTEMP_17H_CCD_TMP_VALID (1u << 11) 173 174 /* 175 * AMD temperature range adjustment, in deciKelvins (i.e., 49.0 Celsius). 176 */ 177 #define AMDTEMP_CURTMP_RANGE_ADJUST 490 178 179 /* 180 * Thermaltrip Status Register (Family 0Fh only) 181 */ 182 #define AMDTEMP_THERMTP_STAT 0xe4 183 #define AMDTEMP_TTSR_SELCORE 0x04 184 #define AMDTEMP_TTSR_SELSENSOR 0x40 185 186 /* 187 * DRAM Configuration High Register 188 */ 189 #define AMDTEMP_DRAM_CONF_HIGH 0x94 /* Function 2 */ 190 #define AMDTEMP_DRAM_MODE_DDR3 0x0100 191 192 /* 193 * CPU Family/Model Register 194 */ 195 #define AMDTEMP_CPUID 0xfc 196 197 /* 198 * Device methods. 199 */ 200 static void amdtemp_identify(driver_t *driver, device_t parent); 201 static int amdtemp_probe(device_t dev); 202 static int amdtemp_attach(device_t dev); 203 static void amdtemp_intrhook(void *arg); 204 static int amdtemp_detach(device_t dev); 205 static int32_t amdtemp_gettemp0f(device_t dev, amdsensor_t sensor); 206 static int32_t amdtemp_gettemp(device_t dev, amdsensor_t sensor); 207 static int32_t amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor); 208 static int32_t amdtemp_gettemp17h(device_t dev, amdsensor_t sensor); 209 static void amdtemp_probe_ccd_sensors17h(device_t dev, uint32_t model); 210 static int amdtemp_sysctl(SYSCTL_HANDLER_ARGS); 211 212 static device_method_t amdtemp_methods[] = { 213 /* Device interface */ 214 DEVMETHOD(device_identify, amdtemp_identify), 215 DEVMETHOD(device_probe, amdtemp_probe), 216 DEVMETHOD(device_attach, amdtemp_attach), 217 DEVMETHOD(device_detach, amdtemp_detach), 218 219 DEVMETHOD_END 220 }; 221 222 static driver_t amdtemp_driver = { 223 "amdtemp", 224 amdtemp_methods, 225 sizeof(struct amdtemp_softc), 226 }; 227 228 static devclass_t amdtemp_devclass; 229 DRIVER_MODULE(amdtemp, hostb, amdtemp_driver, amdtemp_devclass, NULL, NULL); 230 MODULE_VERSION(amdtemp, 1); 231 MODULE_DEPEND(amdtemp, amdsmn, 1, 1, 1); 232 MODULE_PNP_INFO("U16:vendor;U16:device", pci, amdtemp, amdtemp_products, 233 nitems(amdtemp_products)); 234 235 static bool 236 amdtemp_match(device_t dev, const struct amdtemp_product **product_out) 237 { 238 int i; 239 uint16_t vendor, devid; 240 241 vendor = pci_get_vendor(dev); 242 devid = pci_get_device(dev); 243 244 for (i = 0; i < nitems(amdtemp_products); i++) { 245 if (vendor == amdtemp_products[i].amdtemp_vendorid && 246 devid == amdtemp_products[i].amdtemp_deviceid) { 247 if (product_out != NULL) 248 *product_out = &amdtemp_products[i]; 249 return (true); 250 } 251 } 252 return (false); 253 } 254 255 static void 256 amdtemp_identify(driver_t *driver, device_t parent) 257 { 258 device_t child; 259 260 /* Make sure we're not being doubly invoked. */ 261 if (device_find_child(parent, "amdtemp", -1) != NULL) 262 return; 263 264 if (amdtemp_match(parent, NULL)) { 265 child = device_add_child(parent, "amdtemp", -1); 266 if (child == NULL) 267 device_printf(parent, "add amdtemp child failed\n"); 268 } 269 } 270 271 static int 272 amdtemp_probe(device_t dev) 273 { 274 uint32_t family, model; 275 276 if (resource_disabled("amdtemp", 0)) 277 return (ENXIO); 278 if (!amdtemp_match(device_get_parent(dev), NULL)) 279 return (ENXIO); 280 281 family = CPUID_TO_FAMILY(cpu_id); 282 model = CPUID_TO_MODEL(cpu_id); 283 284 switch (family) { 285 case 0x0f: 286 if ((model == 0x04 && (cpu_id & CPUID_STEPPING) == 0) || 287 (model == 0x05 && (cpu_id & CPUID_STEPPING) <= 1)) 288 return (ENXIO); 289 break; 290 case 0x10: 291 case 0x11: 292 case 0x12: 293 case 0x14: 294 case 0x15: 295 case 0x16: 296 case 0x17: 297 break; 298 default: 299 return (ENXIO); 300 } 301 device_set_desc(dev, "AMD CPU On-Die Thermal Sensors"); 302 303 return (BUS_PROBE_GENERIC); 304 } 305 306 static int 307 amdtemp_attach(device_t dev) 308 { 309 char tn[32]; 310 u_int regs[4]; 311 const struct amdtemp_product *product; 312 struct amdtemp_softc *sc; 313 struct sysctl_ctx_list *sysctlctx; 314 struct sysctl_oid *sysctlnode; 315 uint32_t cpuid, family, model; 316 u_int bid; 317 int erratum319, unit; 318 bool needsmn; 319 320 sc = device_get_softc(dev); 321 erratum319 = 0; 322 needsmn = false; 323 324 if (!amdtemp_match(device_get_parent(dev), &product)) 325 return (ENXIO); 326 327 cpuid = cpu_id; 328 family = CPUID_TO_FAMILY(cpuid); 329 model = CPUID_TO_MODEL(cpuid); 330 331 /* 332 * This checks for the byzantine condition of running a heterogenous 333 * revision multi-socket system where the attach thread is potentially 334 * probing a remote socket's PCI device. 335 * 336 * Currently, such scenarios are unsupported on models using the SMN 337 * (because on those models, amdtemp(4) attaches to a different PCI 338 * device than the one that contains AMDTEMP_CPUID). 339 * 340 * The ancient 0x0F family of devices only supports this register from 341 * models 40h+. 342 */ 343 if (product->amdtemp_has_cpuid && (family > 0x0f || 344 (family == 0x0f && model >= 0x40))) { 345 cpuid = pci_read_config(device_get_parent(dev), AMDTEMP_CPUID, 346 4); 347 family = CPUID_TO_FAMILY(cpuid); 348 model = CPUID_TO_MODEL(cpuid); 349 } 350 351 switch (family) { 352 case 0x0f: 353 /* 354 * Thermaltrip Status Register 355 * 356 * - ThermSenseCoreSel 357 * 358 * Revision F & G: 0 - Core1, 1 - Core0 359 * Other: 0 - Core0, 1 - Core1 360 * 361 * - CurTmp 362 * 363 * Revision G: bits 23-14 364 * Other: bits 23-16 365 * 366 * XXX According to the BKDG, CurTmp, ThermSenseSel and 367 * ThermSenseCoreSel bits were introduced in Revision F 368 * but CurTmp seems working fine as early as Revision C. 369 * However, it is not clear whether ThermSenseSel and/or 370 * ThermSenseCoreSel work in undocumented cases as well. 371 * In fact, the Linux driver suggests it may not work but 372 * we just assume it does until we find otherwise. 373 * 374 * XXX According to Linux, CurTmp starts at -28C on 375 * Socket AM2 Revision G processors, which is not 376 * documented anywhere. 377 */ 378 if (model >= 0x40) 379 sc->sc_flags |= AMDTEMP_FLAG_CS_SWAP; 380 if (model >= 0x60 && model != 0xc1) { 381 do_cpuid(0x80000001, regs); 382 bid = (regs[1] >> 9) & 0x1f; 383 switch (model) { 384 case 0x68: /* Socket S1g1 */ 385 case 0x6c: 386 case 0x7c: 387 break; 388 case 0x6b: /* Socket AM2 and ASB1 (2 cores) */ 389 if (bid != 0x0b && bid != 0x0c) 390 sc->sc_flags |= 391 AMDTEMP_FLAG_ALT_OFFSET; 392 break; 393 case 0x6f: /* Socket AM2 and ASB1 (1 core) */ 394 case 0x7f: 395 if (bid != 0x07 && bid != 0x09 && 396 bid != 0x0c) 397 sc->sc_flags |= 398 AMDTEMP_FLAG_ALT_OFFSET; 399 break; 400 default: 401 sc->sc_flags |= AMDTEMP_FLAG_ALT_OFFSET; 402 } 403 sc->sc_flags |= AMDTEMP_FLAG_CT_10BIT; 404 } 405 406 /* 407 * There are two sensors per core. 408 */ 409 sc->sc_ntemps = 2; 410 411 sc->sc_gettemp = amdtemp_gettemp0f; 412 break; 413 case 0x10: 414 /* 415 * Erratum 319 Inaccurate Temperature Measurement 416 * 417 * http://support.amd.com/us/Processor_TechDocs/41322.pdf 418 */ 419 do_cpuid(0x80000001, regs); 420 switch ((regs[1] >> 28) & 0xf) { 421 case 0: /* Socket F */ 422 erratum319 = 1; 423 break; 424 case 1: /* Socket AM2+ or AM3 */ 425 if ((pci_cfgregread(pci_get_bus(dev), 426 pci_get_slot(dev), 2, AMDTEMP_DRAM_CONF_HIGH, 2) & 427 AMDTEMP_DRAM_MODE_DDR3) != 0 || model > 0x04 || 428 (model == 0x04 && (cpuid & CPUID_STEPPING) >= 3)) 429 break; 430 /* XXX 00100F42h (RB-C2) exists in both formats. */ 431 erratum319 = 1; 432 break; 433 } 434 /* FALLTHROUGH */ 435 case 0x11: 436 case 0x12: 437 case 0x14: 438 case 0x15: 439 case 0x16: 440 sc->sc_ntemps = 1; 441 /* 442 * Some later (60h+) models of family 15h use a similar SMN 443 * network as family 17h. (However, the register index differs 444 * from 17h and the decoding matches other 10h-15h models, 445 * which differ from 17h.) 446 */ 447 if (family == 0x15 && model >= 0x60) { 448 sc->sc_gettemp = amdtemp_gettemp15hm60h; 449 needsmn = true; 450 } else 451 sc->sc_gettemp = amdtemp_gettemp; 452 break; 453 case 0x17: 454 sc->sc_ntemps = 1; 455 sc->sc_gettemp = amdtemp_gettemp17h; 456 needsmn = true; 457 break; 458 default: 459 device_printf(dev, "Bogus family 0x%x\n", family); 460 return (ENXIO); 461 } 462 463 if (needsmn) { 464 sc->sc_smn = device_find_child( 465 device_get_parent(dev), "amdsmn", -1); 466 if (sc->sc_smn == NULL) { 467 if (bootverbose) 468 device_printf(dev, "No SMN device found\n"); 469 return (ENXIO); 470 } 471 } 472 473 /* Find number of cores per package. */ 474 sc->sc_ncores = (amd_feature2 & AMDID2_CMP) != 0 ? 475 (cpu_procinfo2 & AMDID_CMP_CORES) + 1 : 1; 476 if (sc->sc_ncores > MAXCPU) 477 return (ENXIO); 478 479 if (erratum319) 480 device_printf(dev, 481 "Erratum 319: temperature measurement may be inaccurate\n"); 482 if (bootverbose) 483 device_printf(dev, "Found %d cores and %d sensors.\n", 484 sc->sc_ncores, 485 sc->sc_ntemps > 1 ? sc->sc_ntemps * sc->sc_ncores : 1); 486 487 /* 488 * dev.amdtemp.N tree. 489 */ 490 unit = device_get_unit(dev); 491 snprintf(tn, sizeof(tn), "dev.amdtemp.%d.sensor_offset", unit); 492 TUNABLE_INT_FETCH(tn, &sc->sc_offset); 493 494 sysctlctx = device_get_sysctl_ctx(dev); 495 SYSCTL_ADD_INT(sysctlctx, 496 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 497 "sensor_offset", CTLFLAG_RW, &sc->sc_offset, 0, 498 "Temperature sensor offset"); 499 sysctlnode = SYSCTL_ADD_NODE(sysctlctx, 500 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 501 "core0", CTLFLAG_RD | CTLFLAG_MPSAFE, 0, "Core 0"); 502 503 SYSCTL_ADD_PROC(sysctlctx, 504 SYSCTL_CHILDREN(sysctlnode), 505 OID_AUTO, "sensor0", 506 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 507 dev, CORE0_SENSOR0, amdtemp_sysctl, "IK", 508 "Core 0 / Sensor 0 temperature"); 509 510 if (family == 0x17) 511 amdtemp_probe_ccd_sensors17h(dev, model); 512 else if (sc->sc_ntemps > 1) { 513 SYSCTL_ADD_PROC(sysctlctx, 514 SYSCTL_CHILDREN(sysctlnode), 515 OID_AUTO, "sensor1", 516 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 517 dev, CORE0_SENSOR1, amdtemp_sysctl, "IK", 518 "Core 0 / Sensor 1 temperature"); 519 520 if (sc->sc_ncores > 1) { 521 sysctlnode = SYSCTL_ADD_NODE(sysctlctx, 522 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 523 OID_AUTO, "core1", CTLFLAG_RD | CTLFLAG_MPSAFE, 524 0, "Core 1"); 525 526 SYSCTL_ADD_PROC(sysctlctx, 527 SYSCTL_CHILDREN(sysctlnode), 528 OID_AUTO, "sensor0", 529 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 530 dev, CORE1_SENSOR0, amdtemp_sysctl, "IK", 531 "Core 1 / Sensor 0 temperature"); 532 533 SYSCTL_ADD_PROC(sysctlctx, 534 SYSCTL_CHILDREN(sysctlnode), 535 OID_AUTO, "sensor1", 536 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 537 dev, CORE1_SENSOR1, amdtemp_sysctl, "IK", 538 "Core 1 / Sensor 1 temperature"); 539 } 540 } 541 542 /* 543 * Try to create dev.cpu sysctl entries and setup intrhook function. 544 * This is needed because the cpu driver may be loaded late on boot, 545 * after us. 546 */ 547 amdtemp_intrhook(dev); 548 sc->sc_ich.ich_func = amdtemp_intrhook; 549 sc->sc_ich.ich_arg = dev; 550 if (config_intrhook_establish(&sc->sc_ich) != 0) { 551 device_printf(dev, "config_intrhook_establish failed!\n"); 552 return (ENXIO); 553 } 554 555 return (0); 556 } 557 558 void 559 amdtemp_intrhook(void *arg) 560 { 561 struct amdtemp_softc *sc; 562 struct sysctl_ctx_list *sysctlctx; 563 device_t dev = (device_t)arg; 564 device_t acpi, cpu, nexus; 565 amdsensor_t sensor; 566 int i; 567 568 sc = device_get_softc(dev); 569 570 /* 571 * dev.cpu.N.temperature. 572 */ 573 nexus = device_find_child(root_bus, "nexus", 0); 574 acpi = device_find_child(nexus, "acpi", 0); 575 576 for (i = 0; i < sc->sc_ncores; i++) { 577 if (sc->sc_sysctl_cpu[i] != NULL) 578 continue; 579 cpu = device_find_child(acpi, "cpu", 580 device_get_unit(dev) * sc->sc_ncores + i); 581 if (cpu != NULL) { 582 sysctlctx = device_get_sysctl_ctx(cpu); 583 584 sensor = sc->sc_ntemps > 1 ? 585 (i == 0 ? CORE0 : CORE1) : CORE0_SENSOR0; 586 sc->sc_sysctl_cpu[i] = SYSCTL_ADD_PROC(sysctlctx, 587 SYSCTL_CHILDREN(device_get_sysctl_tree(cpu)), 588 OID_AUTO, "temperature", 589 CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT, 590 dev, sensor, amdtemp_sysctl, "IK", 591 "Current temparature"); 592 } 593 } 594 if (sc->sc_ich.ich_arg != NULL) 595 config_intrhook_disestablish(&sc->sc_ich); 596 } 597 598 int 599 amdtemp_detach(device_t dev) 600 { 601 struct amdtemp_softc *sc = device_get_softc(dev); 602 int i; 603 604 for (i = 0; i < sc->sc_ncores; i++) 605 if (sc->sc_sysctl_cpu[i] != NULL) 606 sysctl_remove_oid(sc->sc_sysctl_cpu[i], 1, 0); 607 608 /* NewBus removes the dev.amdtemp.N tree by itself. */ 609 610 return (0); 611 } 612 613 static int 614 amdtemp_sysctl(SYSCTL_HANDLER_ARGS) 615 { 616 device_t dev = (device_t)arg1; 617 struct amdtemp_softc *sc = device_get_softc(dev); 618 amdsensor_t sensor = (amdsensor_t)arg2; 619 int32_t auxtemp[2], temp; 620 int error; 621 622 switch (sensor) { 623 case CORE0: 624 auxtemp[0] = sc->sc_gettemp(dev, CORE0_SENSOR0); 625 auxtemp[1] = sc->sc_gettemp(dev, CORE0_SENSOR1); 626 temp = imax(auxtemp[0], auxtemp[1]); 627 break; 628 case CORE1: 629 auxtemp[0] = sc->sc_gettemp(dev, CORE1_SENSOR0); 630 auxtemp[1] = sc->sc_gettemp(dev, CORE1_SENSOR1); 631 temp = imax(auxtemp[0], auxtemp[1]); 632 break; 633 default: 634 temp = sc->sc_gettemp(dev, sensor); 635 break; 636 } 637 error = sysctl_handle_int(oidp, &temp, 0, req); 638 639 return (error); 640 } 641 642 #define AMDTEMP_ZERO_C_TO_K 2731 643 644 static int32_t 645 amdtemp_gettemp0f(device_t dev, amdsensor_t sensor) 646 { 647 struct amdtemp_softc *sc = device_get_softc(dev); 648 uint32_t mask, offset, temp; 649 650 /* Set Sensor/Core selector. */ 651 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 1); 652 temp &= ~(AMDTEMP_TTSR_SELCORE | AMDTEMP_TTSR_SELSENSOR); 653 switch (sensor) { 654 case CORE0_SENSOR1: 655 temp |= AMDTEMP_TTSR_SELSENSOR; 656 /* FALLTHROUGH */ 657 case CORE0_SENSOR0: 658 case CORE0: 659 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) != 0) 660 temp |= AMDTEMP_TTSR_SELCORE; 661 break; 662 case CORE1_SENSOR1: 663 temp |= AMDTEMP_TTSR_SELSENSOR; 664 /* FALLTHROUGH */ 665 case CORE1_SENSOR0: 666 case CORE1: 667 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) == 0) 668 temp |= AMDTEMP_TTSR_SELCORE; 669 break; 670 default: 671 __assert_unreachable(); 672 } 673 pci_write_config(dev, AMDTEMP_THERMTP_STAT, temp, 1); 674 675 mask = (sc->sc_flags & AMDTEMP_FLAG_CT_10BIT) != 0 ? 0x3ff : 0x3fc; 676 offset = (sc->sc_flags & AMDTEMP_FLAG_ALT_OFFSET) != 0 ? 28 : 49; 677 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 4); 678 temp = ((temp >> 14) & mask) * 5 / 2; 679 temp += AMDTEMP_ZERO_C_TO_K + (sc->sc_offset - offset) * 10; 680 681 return (temp); 682 } 683 684 static uint32_t 685 amdtemp_decode_fam10h_to_17h(int32_t sc_offset, uint32_t val, bool minus49) 686 { 687 uint32_t temp; 688 689 /* Convert raw register subfield units (0.125C) to units of 0.1C. */ 690 temp = (val & AMDTEMP_REPTMP10H_CURTMP_MASK) * 5 / 4; 691 692 if (minus49) 693 temp -= AMDTEMP_CURTMP_RANGE_ADJUST; 694 695 temp += AMDTEMP_ZERO_C_TO_K + sc_offset * 10; 696 return (temp); 697 } 698 699 static uint32_t 700 amdtemp_decode_fam10h_to_16h(int32_t sc_offset, uint32_t val) 701 { 702 bool minus49; 703 704 /* 705 * On Family 15h and higher, if CurTmpTjSel is 11b, the range is 706 * adjusted down by 49.0 degrees Celsius. (This adjustment is not 707 * documented in BKDGs prior to family 15h model 00h.) 708 */ 709 minus49 = (CPUID_TO_FAMILY(cpu_id) >= 0x15 && 710 ((val >> AMDTEMP_REPTMP10H_TJSEL_SHIFT) & 711 AMDTEMP_REPTMP10H_TJSEL_MASK) == 0x3); 712 713 return (amdtemp_decode_fam10h_to_17h(sc_offset, 714 val >> AMDTEMP_REPTMP10H_CURTMP_SHIFT, minus49)); 715 } 716 717 static uint32_t 718 amdtemp_decode_fam17h_tctl(int32_t sc_offset, uint32_t val) 719 { 720 bool minus49; 721 722 minus49 = ((val & AMDTEMP_17H_CUR_TMP_RANGE_SEL) != 0); 723 return (amdtemp_decode_fam10h_to_17h(sc_offset, 724 val >> AMDTEMP_REPTMP10H_CURTMP_SHIFT, minus49)); 725 } 726 727 static int32_t 728 amdtemp_gettemp(device_t dev, amdsensor_t sensor) 729 { 730 struct amdtemp_softc *sc = device_get_softc(dev); 731 uint32_t temp; 732 733 temp = pci_read_config(dev, AMDTEMP_REPTMP_CTRL, 4); 734 return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, temp)); 735 } 736 737 static int32_t 738 amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor) 739 { 740 struct amdtemp_softc *sc = device_get_softc(dev); 741 uint32_t val; 742 int error; 743 744 error = amdsmn_read(sc->sc_smn, AMDTEMP_15H_M60H_REPTMP_CTRL, &val); 745 KASSERT(error == 0, ("amdsmn_read")); 746 return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, val)); 747 } 748 749 static int32_t 750 amdtemp_gettemp17h(device_t dev, amdsensor_t sensor) 751 { 752 struct amdtemp_softc *sc = device_get_softc(dev); 753 uint32_t val; 754 int error; 755 756 switch (sensor) { 757 case CORE0_SENSOR0: 758 /* Tctl */ 759 error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CUR_TMP, &val); 760 KASSERT(error == 0, ("amdsmn_read")); 761 return (amdtemp_decode_fam17h_tctl(sc->sc_offset, val)); 762 case CCD_BASE ... CCD_MAX: 763 /* Tccd<N> */ 764 error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CCD_TMP_BASE + 765 (((int)sensor - CCD_BASE) * sizeof(val)), &val); 766 KASSERT(error == 0, ("amdsmn_read2")); 767 KASSERT((val & AMDTEMP_17H_CCD_TMP_VALID) != 0, 768 ("sensor %d: not valid", (int)sensor)); 769 return (amdtemp_decode_fam10h_to_17h(sc->sc_offset, val, true)); 770 default: 771 __assert_unreachable(); 772 } 773 } 774 775 static void 776 amdtemp_probe_ccd_sensors17h(device_t dev, uint32_t model) 777 { 778 char sensor_name[16], sensor_descr[32]; 779 struct amdtemp_softc *sc; 780 uint32_t maxreg, i, val; 781 int error; 782 783 switch (model) { 784 case 0x00 ... 0x1f: /* Zen1, Zen+ */ 785 maxreg = 4; 786 break; 787 case 0x30 ... 0x3f: /* Zen2 TR/Epyc */ 788 case 0x70 ... 0x7f: /* Zen2 Ryzen */ 789 maxreg = 8; 790 _Static_assert((int)NUM_CCDS >= 8, ""); 791 break; 792 default: 793 device_printf(dev, 794 "Unrecognized Family 17h Model: %02xh\n", model); 795 return; 796 } 797 798 sc = device_get_softc(dev); 799 for (i = 0; i < maxreg; i++) { 800 error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CCD_TMP_BASE + 801 (i * sizeof(val)), &val); 802 if (error != 0) 803 continue; 804 if ((val & AMDTEMP_17H_CCD_TMP_VALID) == 0) 805 continue; 806 807 snprintf(sensor_name, sizeof(sensor_name), "ccd%u", i); 808 snprintf(sensor_descr, sizeof(sensor_descr), 809 "CCD %u temperature (Tccd%u)", i, i); 810 811 SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev), 812 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 813 sensor_name, CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_MPSAFE, 814 dev, CCD_BASE + i, amdtemp_sysctl, "IK", sensor_descr); 815 } 816 } 817