1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008, 2009 Rui Paulo <rpaulo@FreeBSD.org> 5 * Copyright (c) 2009 Norikatsu Shigemura <nork@FreeBSD.org> 6 * Copyright (c) 2009-2012 Jung-uk Kim <jkim@FreeBSD.org> 7 * All rights reserved. 8 * Copyright (c) 2017-2019 Conrad Meyer <cem@FreeBSD.org> 9 * All rights reserved. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 23 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 24 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 25 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 26 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 27 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 28 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 29 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Driver for the AMD CPU on-die thermal sensors. 35 * Initially based on the k8temp Linux driver. 36 */ 37 38 #include <sys/cdefs.h> 39 __FBSDID("$FreeBSD$"); 40 41 #include <sys/param.h> 42 #include <sys/bus.h> 43 #include <sys/conf.h> 44 #include <sys/kernel.h> 45 #include <sys/module.h> 46 #include <sys/sysctl.h> 47 #include <sys/systm.h> 48 49 #include <machine/cpufunc.h> 50 #include <machine/md_var.h> 51 #include <machine/specialreg.h> 52 53 #include <dev/pci/pcivar.h> 54 #include <x86/pci_cfgreg.h> 55 56 #include <dev/amdsmn/amdsmn.h> 57 58 typedef enum { 59 CORE0_SENSOR0, 60 CORE0_SENSOR1, 61 CORE1_SENSOR0, 62 CORE1_SENSOR1, 63 CORE0, 64 CORE1 65 } amdsensor_t; 66 67 struct amdtemp_softc { 68 int sc_ncores; 69 int sc_ntemps; 70 int sc_flags; 71 #define AMDTEMP_FLAG_CS_SWAP 0x01 /* ThermSenseCoreSel is inverted. */ 72 #define AMDTEMP_FLAG_CT_10BIT 0x02 /* CurTmp is 10-bit wide. */ 73 #define AMDTEMP_FLAG_ALT_OFFSET 0x04 /* CurTmp starts at -28C. */ 74 int32_t sc_offset; 75 int32_t (*sc_gettemp)(device_t, amdsensor_t); 76 struct sysctl_oid *sc_sysctl_cpu[MAXCPU]; 77 struct intr_config_hook sc_ich; 78 device_t sc_smn; 79 }; 80 81 /* 82 * N.B. The numbers in macro names below are significant and represent CPU 83 * family and model numbers. Do not make up fictitious family or model numbers 84 * when adding support for new devices. 85 */ 86 #define VENDORID_AMD 0x1022 87 #define DEVICEID_AMD_MISC0F 0x1103 88 #define DEVICEID_AMD_MISC10 0x1203 89 #define DEVICEID_AMD_MISC11 0x1303 90 #define DEVICEID_AMD_MISC14 0x1703 91 #define DEVICEID_AMD_MISC15 0x1603 92 #define DEVICEID_AMD_MISC15_M10H 0x1403 93 #define DEVICEID_AMD_MISC15_M30H 0x141d 94 #define DEVICEID_AMD_MISC15_M60H_ROOT 0x1576 95 #define DEVICEID_AMD_MISC16 0x1533 96 #define DEVICEID_AMD_MISC16_M30H 0x1583 97 #define DEVICEID_AMD_HOSTB17H_ROOT 0x1450 98 #define DEVICEID_AMD_HOSTB17H_M10H_ROOT 0x15d0 99 100 static const struct amdtemp_product { 101 uint16_t amdtemp_vendorid; 102 uint16_t amdtemp_deviceid; 103 /* 104 * 0xFC register is only valid on the D18F3 PCI device; SMN temp 105 * drivers do not attach to that device. 106 */ 107 bool amdtemp_has_cpuid; 108 } amdtemp_products[] = { 109 { VENDORID_AMD, DEVICEID_AMD_MISC0F, true }, 110 { VENDORID_AMD, DEVICEID_AMD_MISC10, true }, 111 { VENDORID_AMD, DEVICEID_AMD_MISC11, true }, 112 { VENDORID_AMD, DEVICEID_AMD_MISC14, true }, 113 { VENDORID_AMD, DEVICEID_AMD_MISC15, true }, 114 { VENDORID_AMD, DEVICEID_AMD_MISC15_M10H, true }, 115 { VENDORID_AMD, DEVICEID_AMD_MISC15_M30H, true }, 116 { VENDORID_AMD, DEVICEID_AMD_MISC15_M60H_ROOT, false }, 117 { VENDORID_AMD, DEVICEID_AMD_MISC16, true }, 118 { VENDORID_AMD, DEVICEID_AMD_MISC16_M30H, true }, 119 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_ROOT, false }, 120 { VENDORID_AMD, DEVICEID_AMD_HOSTB17H_M10H_ROOT, false }, 121 }; 122 123 /* 124 * Reported Temperature Control Register, family 0Fh-15h (some models), 16h. 125 */ 126 #define AMDTEMP_REPTMP_CTRL 0xa4 127 128 #define AMDTEMP_REPTMP10H_CURTMP_MASK 0x7ff 129 #define AMDTEMP_REPTMP10H_CURTMP_SHIFT 21 130 #define AMDTEMP_REPTMP10H_TJSEL_MASK 0x3 131 #define AMDTEMP_REPTMP10H_TJSEL_SHIFT 16 132 133 /* 134 * Reported Temperature, Family 15h, M60+ 135 * 136 * Same register bit definitions as other Family 15h CPUs, but access is 137 * indirect via SMN, like Family 17h. 138 */ 139 #define AMDTEMP_15H_M60H_REPTMP_CTRL 0xd8200ca4 140 141 /* 142 * Reported Temperature, Family 17h 143 * 144 * According to AMD OSRR for 17H, section 4.2.1, bits 31-21 of this register 145 * provide the current temp. bit 19, when clear, means the temp is reported in 146 * a range 0.."225C" (probable typo for 255C), and when set changes the range 147 * to -49..206C. 148 */ 149 #define AMDTEMP_17H_CUR_TMP 0x59800 150 #define AMDTEMP_17H_CUR_TMP_RANGE_SEL (1 << 19) 151 152 /* 153 * AMD temperature range adjustment, in deciKelvins (i.e., 49.0 Celsius). 154 */ 155 #define AMDTEMP_CURTMP_RANGE_ADJUST 490 156 157 /* 158 * Thermaltrip Status Register (Family 0Fh only) 159 */ 160 #define AMDTEMP_THERMTP_STAT 0xe4 161 #define AMDTEMP_TTSR_SELCORE 0x04 162 #define AMDTEMP_TTSR_SELSENSOR 0x40 163 164 /* 165 * DRAM Configuration High Register 166 */ 167 #define AMDTEMP_DRAM_CONF_HIGH 0x94 /* Function 2 */ 168 #define AMDTEMP_DRAM_MODE_DDR3 0x0100 169 170 /* 171 * CPU Family/Model Register 172 */ 173 #define AMDTEMP_CPUID 0xfc 174 175 /* 176 * Device methods. 177 */ 178 static void amdtemp_identify(driver_t *driver, device_t parent); 179 static int amdtemp_probe(device_t dev); 180 static int amdtemp_attach(device_t dev); 181 static void amdtemp_intrhook(void *arg); 182 static int amdtemp_detach(device_t dev); 183 static int32_t amdtemp_gettemp0f(device_t dev, amdsensor_t sensor); 184 static int32_t amdtemp_gettemp(device_t dev, amdsensor_t sensor); 185 static int32_t amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor); 186 static int32_t amdtemp_gettemp17h(device_t dev, amdsensor_t sensor); 187 static int amdtemp_sysctl(SYSCTL_HANDLER_ARGS); 188 189 static device_method_t amdtemp_methods[] = { 190 /* Device interface */ 191 DEVMETHOD(device_identify, amdtemp_identify), 192 DEVMETHOD(device_probe, amdtemp_probe), 193 DEVMETHOD(device_attach, amdtemp_attach), 194 DEVMETHOD(device_detach, amdtemp_detach), 195 196 DEVMETHOD_END 197 }; 198 199 static driver_t amdtemp_driver = { 200 "amdtemp", 201 amdtemp_methods, 202 sizeof(struct amdtemp_softc), 203 }; 204 205 static devclass_t amdtemp_devclass; 206 DRIVER_MODULE(amdtemp, hostb, amdtemp_driver, amdtemp_devclass, NULL, NULL); 207 MODULE_VERSION(amdtemp, 1); 208 MODULE_DEPEND(amdtemp, amdsmn, 1, 1, 1); 209 MODULE_PNP_INFO("U16:vendor;U16:device", pci, amdtemp, amdtemp_products, 210 nitems(amdtemp_products)); 211 212 static bool 213 amdtemp_match(device_t dev, const struct amdtemp_product **product_out) 214 { 215 int i; 216 uint16_t vendor, devid; 217 218 vendor = pci_get_vendor(dev); 219 devid = pci_get_device(dev); 220 221 for (i = 0; i < nitems(amdtemp_products); i++) { 222 if (vendor == amdtemp_products[i].amdtemp_vendorid && 223 devid == amdtemp_products[i].amdtemp_deviceid) { 224 if (product_out != NULL) 225 *product_out = &amdtemp_products[i]; 226 return (true); 227 } 228 } 229 return (false); 230 } 231 232 static void 233 amdtemp_identify(driver_t *driver, device_t parent) 234 { 235 device_t child; 236 237 /* Make sure we're not being doubly invoked. */ 238 if (device_find_child(parent, "amdtemp", -1) != NULL) 239 return; 240 241 if (amdtemp_match(parent, NULL)) { 242 child = device_add_child(parent, "amdtemp", -1); 243 if (child == NULL) 244 device_printf(parent, "add amdtemp child failed\n"); 245 } 246 } 247 248 static int 249 amdtemp_probe(device_t dev) 250 { 251 uint32_t family, model; 252 253 if (resource_disabled("amdtemp", 0)) 254 return (ENXIO); 255 if (!amdtemp_match(device_get_parent(dev), NULL)) 256 return (ENXIO); 257 258 family = CPUID_TO_FAMILY(cpu_id); 259 model = CPUID_TO_MODEL(cpu_id); 260 261 switch (family) { 262 case 0x0f: 263 if ((model == 0x04 && (cpu_id & CPUID_STEPPING) == 0) || 264 (model == 0x05 && (cpu_id & CPUID_STEPPING) <= 1)) 265 return (ENXIO); 266 break; 267 case 0x10: 268 case 0x11: 269 case 0x12: 270 case 0x14: 271 case 0x15: 272 case 0x16: 273 case 0x17: 274 break; 275 default: 276 return (ENXIO); 277 } 278 device_set_desc(dev, "AMD CPU On-Die Thermal Sensors"); 279 280 return (BUS_PROBE_GENERIC); 281 } 282 283 static int 284 amdtemp_attach(device_t dev) 285 { 286 char tn[32]; 287 u_int regs[4]; 288 const struct amdtemp_product *product; 289 struct amdtemp_softc *sc; 290 struct sysctl_ctx_list *sysctlctx; 291 struct sysctl_oid *sysctlnode; 292 uint32_t cpuid, family, model; 293 u_int bid; 294 int erratum319, unit; 295 bool needsmn; 296 297 sc = device_get_softc(dev); 298 erratum319 = 0; 299 needsmn = false; 300 301 if (!amdtemp_match(device_get_parent(dev), &product)) 302 return (ENXIO); 303 304 cpuid = cpu_id; 305 family = CPUID_TO_FAMILY(cpuid); 306 model = CPUID_TO_MODEL(cpuid); 307 308 /* 309 * This checks for the byzantine condition of running a heterogenous 310 * revision multi-socket system where the attach thread is potentially 311 * probing a remote socket's PCI device. 312 * 313 * Currently, such scenarios are unsupported on models using the SMN 314 * (because on those models, amdtemp(4) attaches to a different PCI 315 * device than the one that contains AMDTEMP_CPUID). 316 * 317 * The ancient 0x0F family of devices only supports this register from 318 * models 40h+. 319 */ 320 if (product->amdtemp_has_cpuid && (family > 0x0f || 321 (family == 0x0f && model >= 0x40))) { 322 cpuid = pci_read_config(device_get_parent(dev), AMDTEMP_CPUID, 323 4); 324 family = CPUID_TO_FAMILY(cpuid); 325 model = CPUID_TO_MODEL(cpuid); 326 } 327 328 switch (family) { 329 case 0x0f: 330 /* 331 * Thermaltrip Status Register 332 * 333 * - ThermSenseCoreSel 334 * 335 * Revision F & G: 0 - Core1, 1 - Core0 336 * Other: 0 - Core0, 1 - Core1 337 * 338 * - CurTmp 339 * 340 * Revision G: bits 23-14 341 * Other: bits 23-16 342 * 343 * XXX According to the BKDG, CurTmp, ThermSenseSel and 344 * ThermSenseCoreSel bits were introduced in Revision F 345 * but CurTmp seems working fine as early as Revision C. 346 * However, it is not clear whether ThermSenseSel and/or 347 * ThermSenseCoreSel work in undocumented cases as well. 348 * In fact, the Linux driver suggests it may not work but 349 * we just assume it does until we find otherwise. 350 * 351 * XXX According to Linux, CurTmp starts at -28C on 352 * Socket AM2 Revision G processors, which is not 353 * documented anywhere. 354 */ 355 if (model >= 0x40) 356 sc->sc_flags |= AMDTEMP_FLAG_CS_SWAP; 357 if (model >= 0x60 && model != 0xc1) { 358 do_cpuid(0x80000001, regs); 359 bid = (regs[1] >> 9) & 0x1f; 360 switch (model) { 361 case 0x68: /* Socket S1g1 */ 362 case 0x6c: 363 case 0x7c: 364 break; 365 case 0x6b: /* Socket AM2 and ASB1 (2 cores) */ 366 if (bid != 0x0b && bid != 0x0c) 367 sc->sc_flags |= 368 AMDTEMP_FLAG_ALT_OFFSET; 369 break; 370 case 0x6f: /* Socket AM2 and ASB1 (1 core) */ 371 case 0x7f: 372 if (bid != 0x07 && bid != 0x09 && 373 bid != 0x0c) 374 sc->sc_flags |= 375 AMDTEMP_FLAG_ALT_OFFSET; 376 break; 377 default: 378 sc->sc_flags |= AMDTEMP_FLAG_ALT_OFFSET; 379 } 380 sc->sc_flags |= AMDTEMP_FLAG_CT_10BIT; 381 } 382 383 /* 384 * There are two sensors per core. 385 */ 386 sc->sc_ntemps = 2; 387 388 sc->sc_gettemp = amdtemp_gettemp0f; 389 break; 390 case 0x10: 391 /* 392 * Erratum 319 Inaccurate Temperature Measurement 393 * 394 * http://support.amd.com/us/Processor_TechDocs/41322.pdf 395 */ 396 do_cpuid(0x80000001, regs); 397 switch ((regs[1] >> 28) & 0xf) { 398 case 0: /* Socket F */ 399 erratum319 = 1; 400 break; 401 case 1: /* Socket AM2+ or AM3 */ 402 if ((pci_cfgregread(pci_get_bus(dev), 403 pci_get_slot(dev), 2, AMDTEMP_DRAM_CONF_HIGH, 2) & 404 AMDTEMP_DRAM_MODE_DDR3) != 0 || model > 0x04 || 405 (model == 0x04 && (cpuid & CPUID_STEPPING) >= 3)) 406 break; 407 /* XXX 00100F42h (RB-C2) exists in both formats. */ 408 erratum319 = 1; 409 break; 410 } 411 /* FALLTHROUGH */ 412 case 0x11: 413 case 0x12: 414 case 0x14: 415 case 0x15: 416 case 0x16: 417 sc->sc_ntemps = 1; 418 /* 419 * Some later (60h+) models of family 15h use a similar SMN 420 * network as family 17h. (However, the register index differs 421 * from 17h and the decoding matches other 10h-15h models, 422 * which differ from 17h.) 423 */ 424 if (family == 0x15 && model >= 0x60) { 425 sc->sc_gettemp = amdtemp_gettemp15hm60h; 426 needsmn = true; 427 } else 428 sc->sc_gettemp = amdtemp_gettemp; 429 break; 430 case 0x17: 431 sc->sc_ntemps = 1; 432 sc->sc_gettemp = amdtemp_gettemp17h; 433 needsmn = true; 434 break; 435 default: 436 device_printf(dev, "Bogus family 0x%x\n", family); 437 return (ENXIO); 438 } 439 440 if (needsmn) { 441 sc->sc_smn = device_find_child( 442 device_get_parent(dev), "amdsmn", -1); 443 if (sc->sc_smn == NULL) { 444 if (bootverbose) 445 device_printf(dev, "No SMN device found\n"); 446 return (ENXIO); 447 } 448 } 449 450 /* Find number of cores per package. */ 451 sc->sc_ncores = (amd_feature2 & AMDID2_CMP) != 0 ? 452 (cpu_procinfo2 & AMDID_CMP_CORES) + 1 : 1; 453 if (sc->sc_ncores > MAXCPU) 454 return (ENXIO); 455 456 if (erratum319) 457 device_printf(dev, 458 "Erratum 319: temperature measurement may be inaccurate\n"); 459 if (bootverbose) 460 device_printf(dev, "Found %d cores and %d sensors.\n", 461 sc->sc_ncores, 462 sc->sc_ntemps > 1 ? sc->sc_ntemps * sc->sc_ncores : 1); 463 464 /* 465 * dev.amdtemp.N tree. 466 */ 467 unit = device_get_unit(dev); 468 snprintf(tn, sizeof(tn), "dev.amdtemp.%d.sensor_offset", unit); 469 TUNABLE_INT_FETCH(tn, &sc->sc_offset); 470 471 sysctlctx = device_get_sysctl_ctx(dev); 472 SYSCTL_ADD_INT(sysctlctx, 473 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 474 "sensor_offset", CTLFLAG_RW, &sc->sc_offset, 0, 475 "Temperature sensor offset"); 476 sysctlnode = SYSCTL_ADD_NODE(sysctlctx, 477 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, 478 "core0", CTLFLAG_RD, 0, "Core 0"); 479 480 SYSCTL_ADD_PROC(sysctlctx, 481 SYSCTL_CHILDREN(sysctlnode), 482 OID_AUTO, "sensor0", CTLTYPE_INT | CTLFLAG_RD, 483 dev, CORE0_SENSOR0, amdtemp_sysctl, "IK", 484 "Core 0 / Sensor 0 temperature"); 485 486 if (sc->sc_ntemps > 1) { 487 SYSCTL_ADD_PROC(sysctlctx, 488 SYSCTL_CHILDREN(sysctlnode), 489 OID_AUTO, "sensor1", CTLTYPE_INT | CTLFLAG_RD, 490 dev, CORE0_SENSOR1, amdtemp_sysctl, "IK", 491 "Core 0 / Sensor 1 temperature"); 492 493 if (sc->sc_ncores > 1) { 494 sysctlnode = SYSCTL_ADD_NODE(sysctlctx, 495 SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), 496 OID_AUTO, "core1", CTLFLAG_RD, 0, "Core 1"); 497 498 SYSCTL_ADD_PROC(sysctlctx, 499 SYSCTL_CHILDREN(sysctlnode), 500 OID_AUTO, "sensor0", CTLTYPE_INT | CTLFLAG_RD, 501 dev, CORE1_SENSOR0, amdtemp_sysctl, "IK", 502 "Core 1 / Sensor 0 temperature"); 503 504 SYSCTL_ADD_PROC(sysctlctx, 505 SYSCTL_CHILDREN(sysctlnode), 506 OID_AUTO, "sensor1", CTLTYPE_INT | CTLFLAG_RD, 507 dev, CORE1_SENSOR1, amdtemp_sysctl, "IK", 508 "Core 1 / Sensor 1 temperature"); 509 } 510 } 511 512 /* 513 * Try to create dev.cpu sysctl entries and setup intrhook function. 514 * This is needed because the cpu driver may be loaded late on boot, 515 * after us. 516 */ 517 amdtemp_intrhook(dev); 518 sc->sc_ich.ich_func = amdtemp_intrhook; 519 sc->sc_ich.ich_arg = dev; 520 if (config_intrhook_establish(&sc->sc_ich) != 0) { 521 device_printf(dev, "config_intrhook_establish failed!\n"); 522 return (ENXIO); 523 } 524 525 return (0); 526 } 527 528 void 529 amdtemp_intrhook(void *arg) 530 { 531 struct amdtemp_softc *sc; 532 struct sysctl_ctx_list *sysctlctx; 533 device_t dev = (device_t)arg; 534 device_t acpi, cpu, nexus; 535 amdsensor_t sensor; 536 int i; 537 538 sc = device_get_softc(dev); 539 540 /* 541 * dev.cpu.N.temperature. 542 */ 543 nexus = device_find_child(root_bus, "nexus", 0); 544 acpi = device_find_child(nexus, "acpi", 0); 545 546 for (i = 0; i < sc->sc_ncores; i++) { 547 if (sc->sc_sysctl_cpu[i] != NULL) 548 continue; 549 cpu = device_find_child(acpi, "cpu", 550 device_get_unit(dev) * sc->sc_ncores + i); 551 if (cpu != NULL) { 552 sysctlctx = device_get_sysctl_ctx(cpu); 553 554 sensor = sc->sc_ntemps > 1 ? 555 (i == 0 ? CORE0 : CORE1) : CORE0_SENSOR0; 556 sc->sc_sysctl_cpu[i] = SYSCTL_ADD_PROC(sysctlctx, 557 SYSCTL_CHILDREN(device_get_sysctl_tree(cpu)), 558 OID_AUTO, "temperature", CTLTYPE_INT | CTLFLAG_RD, 559 dev, sensor, amdtemp_sysctl, "IK", 560 "Current temparature"); 561 } 562 } 563 if (sc->sc_ich.ich_arg != NULL) 564 config_intrhook_disestablish(&sc->sc_ich); 565 } 566 567 int 568 amdtemp_detach(device_t dev) 569 { 570 struct amdtemp_softc *sc = device_get_softc(dev); 571 int i; 572 573 for (i = 0; i < sc->sc_ncores; i++) 574 if (sc->sc_sysctl_cpu[i] != NULL) 575 sysctl_remove_oid(sc->sc_sysctl_cpu[i], 1, 0); 576 577 /* NewBus removes the dev.amdtemp.N tree by itself. */ 578 579 return (0); 580 } 581 582 static int 583 amdtemp_sysctl(SYSCTL_HANDLER_ARGS) 584 { 585 device_t dev = (device_t)arg1; 586 struct amdtemp_softc *sc = device_get_softc(dev); 587 amdsensor_t sensor = (amdsensor_t)arg2; 588 int32_t auxtemp[2], temp; 589 int error; 590 591 switch (sensor) { 592 case CORE0: 593 auxtemp[0] = sc->sc_gettemp(dev, CORE0_SENSOR0); 594 auxtemp[1] = sc->sc_gettemp(dev, CORE0_SENSOR1); 595 temp = imax(auxtemp[0], auxtemp[1]); 596 break; 597 case CORE1: 598 auxtemp[0] = sc->sc_gettemp(dev, CORE1_SENSOR0); 599 auxtemp[1] = sc->sc_gettemp(dev, CORE1_SENSOR1); 600 temp = imax(auxtemp[0], auxtemp[1]); 601 break; 602 default: 603 temp = sc->sc_gettemp(dev, sensor); 604 break; 605 } 606 error = sysctl_handle_int(oidp, &temp, 0, req); 607 608 return (error); 609 } 610 611 #define AMDTEMP_ZERO_C_TO_K 2731 612 613 static int32_t 614 amdtemp_gettemp0f(device_t dev, amdsensor_t sensor) 615 { 616 struct amdtemp_softc *sc = device_get_softc(dev); 617 uint32_t mask, offset, temp; 618 619 /* Set Sensor/Core selector. */ 620 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 1); 621 temp &= ~(AMDTEMP_TTSR_SELCORE | AMDTEMP_TTSR_SELSENSOR); 622 switch (sensor) { 623 case CORE0_SENSOR1: 624 temp |= AMDTEMP_TTSR_SELSENSOR; 625 /* FALLTHROUGH */ 626 case CORE0_SENSOR0: 627 case CORE0: 628 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) != 0) 629 temp |= AMDTEMP_TTSR_SELCORE; 630 break; 631 case CORE1_SENSOR1: 632 temp |= AMDTEMP_TTSR_SELSENSOR; 633 /* FALLTHROUGH */ 634 case CORE1_SENSOR0: 635 case CORE1: 636 if ((sc->sc_flags & AMDTEMP_FLAG_CS_SWAP) == 0) 637 temp |= AMDTEMP_TTSR_SELCORE; 638 break; 639 } 640 pci_write_config(dev, AMDTEMP_THERMTP_STAT, temp, 1); 641 642 mask = (sc->sc_flags & AMDTEMP_FLAG_CT_10BIT) != 0 ? 0x3ff : 0x3fc; 643 offset = (sc->sc_flags & AMDTEMP_FLAG_ALT_OFFSET) != 0 ? 28 : 49; 644 temp = pci_read_config(dev, AMDTEMP_THERMTP_STAT, 4); 645 temp = ((temp >> 14) & mask) * 5 / 2; 646 temp += AMDTEMP_ZERO_C_TO_K + (sc->sc_offset - offset) * 10; 647 648 return (temp); 649 } 650 651 static uint32_t 652 amdtemp_decode_fam10h_to_16h(int32_t sc_offset, uint32_t val) 653 { 654 uint32_t temp; 655 656 /* Convert raw register subfield units (0.125C) to units of 0.1C. */ 657 temp = ((val >> AMDTEMP_REPTMP10H_CURTMP_SHIFT) & 658 AMDTEMP_REPTMP10H_CURTMP_MASK) * 5 / 4; 659 660 /* 661 * On Family 15h and higher, if CurTmpTjSel is 11b, the range is 662 * adjusted down by 49.0 degrees Celsius. (This adjustment is not 663 * documented in BKDGs prior to family 15h model 00h.) 664 */ 665 if (CPUID_TO_FAMILY(cpu_id) >= 0x15 && 666 ((val >> AMDTEMP_REPTMP10H_TJSEL_SHIFT) & 667 AMDTEMP_REPTMP10H_TJSEL_MASK) == 0x3) 668 temp -= AMDTEMP_CURTMP_RANGE_ADJUST; 669 670 temp += AMDTEMP_ZERO_C_TO_K + sc_offset * 10; 671 return (temp); 672 } 673 674 static int32_t 675 amdtemp_gettemp(device_t dev, amdsensor_t sensor) 676 { 677 struct amdtemp_softc *sc = device_get_softc(dev); 678 uint32_t temp; 679 680 temp = pci_read_config(dev, AMDTEMP_REPTMP_CTRL, 4); 681 return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, temp)); 682 } 683 684 static int32_t 685 amdtemp_gettemp15hm60h(device_t dev, amdsensor_t sensor) 686 { 687 struct amdtemp_softc *sc = device_get_softc(dev); 688 uint32_t val; 689 int error; 690 691 error = amdsmn_read(sc->sc_smn, AMDTEMP_15H_M60H_REPTMP_CTRL, &val); 692 KASSERT(error == 0, ("amdsmn_read")); 693 return (amdtemp_decode_fam10h_to_16h(sc->sc_offset, val)); 694 } 695 696 static int32_t 697 amdtemp_gettemp17h(device_t dev, amdsensor_t sensor) 698 { 699 struct amdtemp_softc *sc = device_get_softc(dev); 700 uint32_t temp, val; 701 int error; 702 703 error = amdsmn_read(sc->sc_smn, AMDTEMP_17H_CUR_TMP, &val); 704 KASSERT(error == 0, ("amdsmn_read")); 705 706 temp = ((val >> 21) & 0x7ff) * 5 / 4; 707 if ((val & AMDTEMP_17H_CUR_TMP_RANGE_SEL) != 0) 708 temp -= AMDTEMP_CURTMP_RANGE_ADJUST; 709 temp += AMDTEMP_ZERO_C_TO_K + sc->sc_offset * 10; 710 711 return (temp); 712 } 713