1 /*- 2 * Copyright (c) 2017-2020 Conrad Meyer <cem@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 16 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 17 * DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, 18 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 19 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 20 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, 22 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN 23 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 24 * POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /* 28 * Driver for the AMD Family 15h and 17h CPU System Management Network. 29 */ 30 31 #include <sys/param.h> 32 #include <sys/bus.h> 33 #include <sys/conf.h> 34 #include <sys/lock.h> 35 #include <sys/kernel.h> 36 #include <sys/module.h> 37 #include <sys/mutex.h> 38 #include <sys/sysctl.h> 39 #include <sys/systm.h> 40 41 #include <machine/cpufunc.h> 42 #include <machine/cputypes.h> 43 #include <machine/md_var.h> 44 #include <machine/specialreg.h> 45 46 #include <dev/pci/pcivar.h> 47 #include <x86/pci_cfgreg.h> 48 49 #include <dev/amdsmn/amdsmn.h> 50 51 #define F15H_SMN_ADDR_REG 0xb8 52 #define F15H_SMN_DATA_REG 0xbc 53 #define F17H_SMN_ADDR_REG 0x60 54 #define F17H_SMN_DATA_REG 0x64 55 56 #define PCI_DEVICE_ID_AMD_15H_M60H_ROOT 0x1576 57 #define PCI_DEVICE_ID_AMD_17H_ROOT 0x1450 58 #define PCI_DEVICE_ID_AMD_17H_M10H_ROOT 0x15d0 59 #define PCI_DEVICE_ID_AMD_17H_M30H_ROOT 0x1480 /* Also M70H, F19H M00H/M20H */ 60 #define PCI_DEVICE_ID_AMD_17H_M60H_ROOT 0x1630 61 #define PCI_DEVICE_ID_AMD_19H_M10H_ROOT 0x14a4 62 #define PCI_DEVICE_ID_AMD_19H_M40H_ROOT 0x14b5 63 #define PCI_DEVICE_ID_AMD_19H_M60H_ROOT 0x14d8 64 #define PCI_DEVICE_ID_AMD_19H_M70H_ROOT 0x14e8 65 66 struct pciid; 67 struct amdsmn_softc { 68 struct mtx smn_lock; 69 const struct pciid *smn_pciid; 70 }; 71 72 static const struct pciid { 73 uint16_t amdsmn_vendorid; 74 uint16_t amdsmn_deviceid; 75 uint8_t amdsmn_addr_reg; 76 uint8_t amdsmn_data_reg; 77 } amdsmn_ids[] = { 78 { 79 .amdsmn_vendorid = CPU_VENDOR_AMD, 80 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_15H_M60H_ROOT, 81 .amdsmn_addr_reg = F15H_SMN_ADDR_REG, 82 .amdsmn_data_reg = F15H_SMN_DATA_REG, 83 }, 84 { 85 .amdsmn_vendorid = CPU_VENDOR_AMD, 86 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_17H_ROOT, 87 .amdsmn_addr_reg = F17H_SMN_ADDR_REG, 88 .amdsmn_data_reg = F17H_SMN_DATA_REG, 89 }, 90 { 91 .amdsmn_vendorid = CPU_VENDOR_AMD, 92 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_17H_M10H_ROOT, 93 .amdsmn_addr_reg = F17H_SMN_ADDR_REG, 94 .amdsmn_data_reg = F17H_SMN_DATA_REG, 95 }, 96 { 97 .amdsmn_vendorid = CPU_VENDOR_AMD, 98 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_17H_M30H_ROOT, 99 .amdsmn_addr_reg = F17H_SMN_ADDR_REG, 100 .amdsmn_data_reg = F17H_SMN_DATA_REG, 101 }, 102 { 103 .amdsmn_vendorid = CPU_VENDOR_AMD, 104 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_17H_M60H_ROOT, 105 .amdsmn_addr_reg = F17H_SMN_ADDR_REG, 106 .amdsmn_data_reg = F17H_SMN_DATA_REG, 107 }, 108 { 109 .amdsmn_vendorid = CPU_VENDOR_AMD, 110 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_19H_M10H_ROOT, 111 .amdsmn_addr_reg = F17H_SMN_ADDR_REG, 112 .amdsmn_data_reg = F17H_SMN_DATA_REG, 113 }, 114 { 115 .amdsmn_vendorid = CPU_VENDOR_AMD, 116 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_19H_M40H_ROOT, 117 .amdsmn_addr_reg = F17H_SMN_ADDR_REG, 118 .amdsmn_data_reg = F17H_SMN_DATA_REG, 119 }, 120 { 121 .amdsmn_vendorid = CPU_VENDOR_AMD, 122 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_19H_M60H_ROOT, 123 .amdsmn_addr_reg = F17H_SMN_ADDR_REG, 124 .amdsmn_data_reg = F17H_SMN_DATA_REG, 125 }, 126 { 127 .amdsmn_vendorid = CPU_VENDOR_AMD, 128 .amdsmn_deviceid = PCI_DEVICE_ID_AMD_19H_M70H_ROOT, 129 .amdsmn_addr_reg = F17H_SMN_ADDR_REG, 130 .amdsmn_data_reg = F17H_SMN_DATA_REG, 131 }, 132 }; 133 134 /* 135 * Device methods. 136 */ 137 static void amdsmn_identify(driver_t *driver, device_t parent); 138 static int amdsmn_probe(device_t dev); 139 static int amdsmn_attach(device_t dev); 140 static int amdsmn_detach(device_t dev); 141 142 static device_method_t amdsmn_methods[] = { 143 /* Device interface */ 144 DEVMETHOD(device_identify, amdsmn_identify), 145 DEVMETHOD(device_probe, amdsmn_probe), 146 DEVMETHOD(device_attach, amdsmn_attach), 147 DEVMETHOD(device_detach, amdsmn_detach), 148 DEVMETHOD_END 149 }; 150 151 static driver_t amdsmn_driver = { 152 "amdsmn", 153 amdsmn_methods, 154 sizeof(struct amdsmn_softc), 155 }; 156 157 DRIVER_MODULE(amdsmn, hostb, amdsmn_driver, NULL, NULL); 158 MODULE_VERSION(amdsmn, 1); 159 MODULE_PNP_INFO("U16:vendor;U16:device", pci, amdsmn, amdsmn_ids, 160 nitems(amdsmn_ids)); 161 162 static bool 163 amdsmn_match(device_t parent, const struct pciid **pciid_out) 164 { 165 uint16_t vendor, device; 166 size_t i; 167 168 vendor = pci_get_vendor(parent); 169 device = pci_get_device(parent); 170 171 for (i = 0; i < nitems(amdsmn_ids); i++) { 172 if (vendor == amdsmn_ids[i].amdsmn_vendorid && 173 device == amdsmn_ids[i].amdsmn_deviceid) { 174 if (pciid_out != NULL) 175 *pciid_out = &amdsmn_ids[i]; 176 return (true); 177 } 178 } 179 return (false); 180 } 181 182 static void 183 amdsmn_identify(driver_t *driver, device_t parent) 184 { 185 device_t child; 186 187 /* Make sure we're not being doubly invoked. */ 188 if (device_find_child(parent, "amdsmn", -1) != NULL) 189 return; 190 if (!amdsmn_match(parent, NULL)) 191 return; 192 193 child = device_add_child(parent, "amdsmn", DEVICE_UNIT_ANY); 194 if (child == NULL) 195 device_printf(parent, "add amdsmn child failed\n"); 196 } 197 198 static int 199 amdsmn_probe(device_t dev) 200 { 201 uint32_t family; 202 203 if (resource_disabled("amdsmn", 0)) 204 return (ENXIO); 205 if (!amdsmn_match(device_get_parent(dev), NULL)) 206 return (ENXIO); 207 208 family = CPUID_TO_FAMILY(cpu_id); 209 210 switch (family) { 211 case 0x15: 212 case 0x17: 213 case 0x19: 214 break; 215 default: 216 return (ENXIO); 217 } 218 device_set_descf(dev, "AMD Family %xh System Management Network", 219 family); 220 221 return (BUS_PROBE_GENERIC); 222 } 223 224 static int 225 amdsmn_attach(device_t dev) 226 { 227 struct amdsmn_softc *sc = device_get_softc(dev); 228 229 if (!amdsmn_match(device_get_parent(dev), &sc->smn_pciid)) 230 return (ENXIO); 231 232 mtx_init(&sc->smn_lock, "SMN mtx", "SMN", MTX_DEF); 233 return (0); 234 } 235 236 int 237 amdsmn_detach(device_t dev) 238 { 239 struct amdsmn_softc *sc = device_get_softc(dev); 240 241 mtx_destroy(&sc->smn_lock); 242 return (0); 243 } 244 245 int 246 amdsmn_read(device_t dev, uint32_t addr, uint32_t *value) 247 { 248 struct amdsmn_softc *sc = device_get_softc(dev); 249 device_t parent; 250 251 parent = device_get_parent(dev); 252 253 mtx_lock(&sc->smn_lock); 254 pci_write_config(parent, sc->smn_pciid->amdsmn_addr_reg, addr, 4); 255 *value = pci_read_config(parent, sc->smn_pciid->amdsmn_data_reg, 4); 256 mtx_unlock(&sc->smn_lock); 257 258 return (0); 259 } 260 261 int 262 amdsmn_write(device_t dev, uint32_t addr, uint32_t value) 263 { 264 struct amdsmn_softc *sc = device_get_softc(dev); 265 device_t parent; 266 267 parent = device_get_parent(dev); 268 269 mtx_lock(&sc->smn_lock); 270 pci_write_config(parent, sc->smn_pciid->amdsmn_addr_reg, addr, 4); 271 pci_write_config(parent, sc->smn_pciid->amdsmn_data_reg, value, 4); 272 mtx_unlock(&sc->smn_lock); 273 274 return (0); 275 } 276