1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2009 Andriy Gapon <avg@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * This is a driver for watchdog timer present in AMD SB600/SB7xx/SB8xx 31 * southbridges. 32 * Please see the following specifications for the descriptions of the 33 * registers and flags: 34 * - AMD SB600 Register Reference Guide, Public Version, Rev. 3.03 (SB600 RRG) 35 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/46155_sb600_rrg_pub_3.03.pdf 36 * - AMD SB700/710/750 Register Reference Guide (RRG) 37 * http://developer.amd.com/assets/43009_sb7xx_rrg_pub_1.00.pdf 38 * - AMD SB700/710/750 Register Programming Requirements (RPR) 39 * http://developer.amd.com/assets/42413_sb7xx_rpr_pub_1.00.pdf 40 * - AMD SB800-Series Southbridges Register Reference Guide (RRG) 41 * http://support.amd.com/us/Embedded_TechDocs/45482.pdf 42 * Please see the following for Watchdog Resource Table specification: 43 * - Watchdog Timer Hardware Requirements for Windows Server 2003 (WDRT) 44 * http://www.microsoft.com/whdc/system/sysinternals/watchdog.mspx 45 * AMD SB600/SB7xx/SB8xx watchdog hardware seems to conform to the above 46 * specifications, but the table hasn't been spotted in the wild yet. 47 */ 48 49 #include <sys/cdefs.h> 50 __FBSDID("$FreeBSD$"); 51 52 #include <sys/param.h> 53 #include <sys/kernel.h> 54 #include <sys/module.h> 55 #include <sys/systm.h> 56 #include <sys/sysctl.h> 57 #include <sys/bus.h> 58 #include <machine/bus.h> 59 #include <sys/rman.h> 60 #include <machine/resource.h> 61 #include <sys/watchdog.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/amdsbwd/amd_chipset.h> 65 #include <isa/isavar.h> 66 67 /* 68 * Registers in the Watchdog IO space. 69 * See SB7xx RRG 2.3.4, WDRT. 70 */ 71 #define AMDSB_WD_CTRL 0x00 72 #define AMDSB_WD_RUN 0x01 73 #define AMDSB_WD_FIRED 0x02 74 #define AMDSB_WD_SHUTDOWN 0x04 75 #define AMDSB_WD_DISABLE 0x08 76 #define AMDSB_WD_RESERVED 0x70 77 #define AMDSB_WD_RELOAD 0x80 78 #define AMDSB_WD_COUNT 0x04 79 #define AMDSB_WD_COUNT_MASK 0xffff 80 #define AMDSB_WDIO_REG_WIDTH 4 81 82 #define amdsbwd_verbose_printf(dev, ...) \ 83 do { \ 84 if (bootverbose) \ 85 device_printf(dev, __VA_ARGS__);\ 86 } while (0) 87 88 struct amdsbwd_softc { 89 device_t dev; 90 eventhandler_tag ev_tag; 91 struct resource *res_ctrl; 92 struct resource *res_count; 93 int rid_ctrl; 94 int rid_count; 95 int ms_per_tick; 96 int max_ticks; 97 int active; 98 unsigned int timeout; 99 }; 100 101 static void amdsbwd_identify(driver_t *driver, device_t parent); 102 static int amdsbwd_probe(device_t dev); 103 static int amdsbwd_attach(device_t dev); 104 static int amdsbwd_detach(device_t dev); 105 106 static device_method_t amdsbwd_methods[] = { 107 DEVMETHOD(device_identify, amdsbwd_identify), 108 DEVMETHOD(device_probe, amdsbwd_probe), 109 DEVMETHOD(device_attach, amdsbwd_attach), 110 DEVMETHOD(device_detach, amdsbwd_detach), 111 #if 0 112 DEVMETHOD(device_shutdown, amdsbwd_detach), 113 #endif 114 DEVMETHOD_END 115 }; 116 117 static devclass_t amdsbwd_devclass; 118 static driver_t amdsbwd_driver = { 119 "amdsbwd", 120 amdsbwd_methods, 121 sizeof(struct amdsbwd_softc) 122 }; 123 124 DRIVER_MODULE(amdsbwd, isa, amdsbwd_driver, amdsbwd_devclass, NULL, NULL); 125 126 127 static uint8_t 128 pmio_read(struct resource *res, uint8_t reg) 129 { 130 bus_write_1(res, 0, reg); /* Index */ 131 return (bus_read_1(res, 1)); /* Data */ 132 } 133 134 static void 135 pmio_write(struct resource *res, uint8_t reg, uint8_t val) 136 { 137 bus_write_1(res, 0, reg); /* Index */ 138 bus_write_1(res, 1, val); /* Data */ 139 } 140 141 static uint32_t 142 wdctrl_read(struct amdsbwd_softc *sc) 143 { 144 return (bus_read_4(sc->res_ctrl, 0)); 145 } 146 147 static void 148 wdctrl_write(struct amdsbwd_softc *sc, uint32_t val) 149 { 150 bus_write_4(sc->res_ctrl, 0, val); 151 } 152 153 static __unused uint32_t 154 wdcount_read(struct amdsbwd_softc *sc) 155 { 156 return (bus_read_4(sc->res_count, 0)); 157 } 158 159 static void 160 wdcount_write(struct amdsbwd_softc *sc, uint32_t val) 161 { 162 bus_write_4(sc->res_count, 0, val); 163 } 164 165 static void 166 amdsbwd_tmr_enable(struct amdsbwd_softc *sc) 167 { 168 uint32_t val; 169 170 val = wdctrl_read(sc); 171 val |= AMDSB_WD_RUN; 172 wdctrl_write(sc, val); 173 sc->active = 1; 174 amdsbwd_verbose_printf(sc->dev, "timer enabled\n"); 175 } 176 177 static void 178 amdsbwd_tmr_disable(struct amdsbwd_softc *sc) 179 { 180 uint32_t val; 181 182 val = wdctrl_read(sc); 183 val &= ~AMDSB_WD_RUN; 184 wdctrl_write(sc, val); 185 sc->active = 0; 186 amdsbwd_verbose_printf(sc->dev, "timer disabled\n"); 187 } 188 189 static void 190 amdsbwd_tmr_reload(struct amdsbwd_softc *sc) 191 { 192 uint32_t val; 193 194 val = wdctrl_read(sc); 195 val |= AMDSB_WD_RELOAD; 196 wdctrl_write(sc, val); 197 } 198 199 static void 200 amdsbwd_tmr_set(struct amdsbwd_softc *sc, uint16_t timeout) 201 { 202 203 timeout &= AMDSB_WD_COUNT_MASK; 204 wdcount_write(sc, timeout); 205 sc->timeout = timeout; 206 amdsbwd_verbose_printf(sc->dev, "timeout set to %u ticks\n", timeout); 207 } 208 209 static void 210 amdsbwd_event(void *arg, unsigned int cmd, int *error) 211 { 212 struct amdsbwd_softc *sc = arg; 213 uint64_t timeout; 214 215 if (cmd != 0) { 216 timeout = 0; 217 cmd &= WD_INTERVAL; 218 if (cmd >= WD_TO_1MS) { 219 timeout = (uint64_t)1 << (cmd - WD_TO_1MS); 220 timeout = timeout / sc->ms_per_tick; 221 } 222 /* For a too short timeout use 1 tick. */ 223 if (timeout == 0) 224 timeout = 1; 225 /* For a too long timeout stop the timer. */ 226 if (timeout > sc->max_ticks) 227 timeout = 0; 228 } else { 229 timeout = 0; 230 } 231 232 if (timeout != 0) { 233 if (timeout != sc->timeout) 234 amdsbwd_tmr_set(sc, timeout); 235 if (!sc->active) 236 amdsbwd_tmr_enable(sc); 237 amdsbwd_tmr_reload(sc); 238 *error = 0; 239 } else { 240 if (sc->active) 241 amdsbwd_tmr_disable(sc); 242 } 243 } 244 245 static void 246 amdsbwd_identify(driver_t *driver, device_t parent) 247 { 248 device_t child; 249 device_t smb_dev; 250 251 if (resource_disabled("amdsbwd", 0)) 252 return; 253 if (device_find_child(parent, "amdsbwd", -1) != NULL) 254 return; 255 256 /* 257 * Try to identify SB600/SB7xx by PCI Device ID of SMBus device 258 * that should be present at bus 0, device 20, function 0. 259 */ 260 smb_dev = pci_find_bsf(0, 20, 0); 261 if (smb_dev == NULL) 262 return; 263 if (pci_get_devid(smb_dev) != AMDSB_SMBUS_DEVID && 264 pci_get_devid(smb_dev) != AMDFCH_SMBUS_DEVID && 265 pci_get_devid(smb_dev) != AMDCZ_SMBUS_DEVID) 266 return; 267 268 child = BUS_ADD_CHILD(parent, ISA_ORDER_SPECULATIVE, "amdsbwd", -1); 269 if (child == NULL) 270 device_printf(parent, "add amdsbwd child failed\n"); 271 } 272 273 274 static void 275 amdsbwd_probe_sb7xx(device_t dev, struct resource *pmres, uint32_t *addr) 276 { 277 uint8_t val; 278 int i; 279 280 /* Report cause of previous reset for user's convenience. */ 281 val = pmio_read(pmres, AMDSB_PM_RESET_STATUS0); 282 if (val != 0) 283 amdsbwd_verbose_printf(dev, "ResetStatus0 = %#04x\n", val); 284 val = pmio_read(pmres, AMDSB_PM_RESET_STATUS1); 285 if (val != 0) 286 amdsbwd_verbose_printf(dev, "ResetStatus1 = %#04x\n", val); 287 if ((val & AMDSB_WD_RST_STS) != 0) 288 device_printf(dev, "Previous Reset was caused by Watchdog\n"); 289 290 /* Find base address of memory mapped WDT registers. */ 291 for (*addr = 0, i = 0; i < 4; i++) { 292 *addr <<= 8; 293 *addr |= pmio_read(pmres, AMDSB_PM_WDT_BASE_MSB - i); 294 } 295 *addr &= ~0x07u; 296 297 /* Set watchdog timer tick to 1s. */ 298 val = pmio_read(pmres, AMDSB_PM_WDT_CTRL); 299 val &= ~AMDSB_WDT_RES_MASK; 300 val |= AMDSB_WDT_RES_1S; 301 pmio_write(pmres, AMDSB_PM_WDT_CTRL, val); 302 303 /* Enable watchdog device (in stopped state). */ 304 val = pmio_read(pmres, AMDSB_PM_WDT_CTRL); 305 val &= ~AMDSB_WDT_DISABLE; 306 pmio_write(pmres, AMDSB_PM_WDT_CTRL, val); 307 308 /* 309 * XXX TODO: Ensure that watchdog decode is enabled 310 * (register 0x41, bit 3). 311 */ 312 device_set_desc(dev, "AMD SB600/SB7xx Watchdog Timer"); 313 } 314 315 static void 316 amdsbwd_probe_sb8xx(device_t dev, struct resource *pmres, uint32_t *addr) 317 { 318 uint8_t val; 319 int i; 320 321 /* Report cause of previous reset for user's convenience. */ 322 val = pmio_read(pmres, AMDSB8_PM_RESET_STATUS0); 323 if (val != 0) 324 amdsbwd_verbose_printf(dev, "ResetStatus0 = %#04x\n", val); 325 val = pmio_read(pmres, AMDSB8_PM_RESET_STATUS1); 326 if (val != 0) 327 amdsbwd_verbose_printf(dev, "ResetStatus1 = %#04x\n", val); 328 if ((val & AMDSB8_WD_RST_STS) != 0) 329 device_printf(dev, "Previous Reset was caused by Watchdog\n"); 330 331 /* Find base address of memory mapped WDT registers. */ 332 for (*addr = 0, i = 0; i < 4; i++) { 333 *addr <<= 8; 334 *addr |= pmio_read(pmres, AMDSB8_PM_WDT_EN + 3 - i); 335 } 336 *addr &= ~0x07u; 337 338 /* Set watchdog timer tick to 1s. */ 339 val = pmio_read(pmres, AMDSB8_PM_WDT_CTRL); 340 val &= ~AMDSB8_WDT_RES_MASK; 341 val |= AMDSB8_WDT_1HZ; 342 pmio_write(pmres, AMDSB8_PM_WDT_CTRL, val); 343 #ifdef AMDSBWD_DEBUG 344 val = pmio_read(pmres, AMDSB8_PM_WDT_CTRL); 345 amdsbwd_verbose_printf(dev, "AMDSB8_PM_WDT_CTRL value = %#04x\n", val); 346 #endif 347 348 /* 349 * Enable watchdog device (in stopped state) 350 * and decoding of its address. 351 */ 352 val = pmio_read(pmres, AMDSB8_PM_WDT_EN); 353 val &= ~AMDSB8_WDT_DISABLE; 354 val |= AMDSB8_WDT_DEC_EN; 355 pmio_write(pmres, AMDSB8_PM_WDT_EN, val); 356 #ifdef AMDSBWD_DEBUG 357 val = pmio_read(pmres, AMDSB8_PM_WDT_EN); 358 device_printf(dev, "AMDSB8_PM_WDT_EN value = %#04x\n", val); 359 #endif 360 device_set_desc(dev, "AMD SB8xx/SB9xx/Axx Watchdog Timer"); 361 } 362 363 static void 364 amdsbwd_probe_fch41(device_t dev, struct resource *pmres, uint32_t *addr) 365 { 366 uint8_t val; 367 368 val = pmio_read(pmres, AMDFCH41_PM_ISA_CTRL); 369 if ((val & AMDFCH41_MMIO_EN) != 0) { 370 /* Fixed offset for the watchdog within ACPI MMIO range. */ 371 amdsbwd_verbose_printf(dev, "ACPI MMIO range is enabled\n"); 372 *addr = AMDFCH41_MMIO_ADDR + AMDFCH41_MMIO_WDT_OFF; 373 } else { 374 /* 375 * Enable decoding of watchdog MMIO address. 376 */ 377 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN0); 378 val |= AMDFCH41_WDT_EN; 379 pmio_write(pmres, AMDFCH41_PM_DECODE_EN0, val); 380 #ifdef AMDSBWD_DEBUG 381 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN0); 382 device_printf(dev, "AMDFCH41_PM_DECODE_EN0 value = %#04x\n", 383 val); 384 #endif 385 386 /* Special fixed MMIO range for the watchdog. */ 387 *addr = AMDFCH41_WDT_FIXED_ADDR; 388 } 389 390 /* 391 * Set watchdog timer tick to 1s and 392 * enable the watchdog device (in stopped state). 393 */ 394 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN3); 395 val &= ~AMDFCH41_WDT_RES_MASK; 396 val |= AMDFCH41_WDT_RES_1S; 397 val &= ~AMDFCH41_WDT_EN_MASK; 398 val |= AMDFCH41_WDT_ENABLE; 399 pmio_write(pmres, AMDFCH41_PM_DECODE_EN3, val); 400 #ifdef AMDSBWD_DEBUG 401 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN3); 402 amdsbwd_verbose_printf(dev, "AMDFCH41_PM_DECODE_EN3 value = %#04x\n", 403 val); 404 #endif 405 device_set_desc(dev, "AMD FCH Rev 41h+ Watchdog Timer"); 406 } 407 408 static int 409 amdsbwd_probe(device_t dev) 410 { 411 struct resource *res; 412 device_t smb_dev; 413 uint32_t addr; 414 int rid; 415 int rc; 416 uint32_t devid; 417 uint8_t revid; 418 419 /* Do not claim some ISA PnP device by accident. */ 420 if (isa_get_logicalid(dev) != 0) 421 return (ENXIO); 422 423 rc = bus_set_resource(dev, SYS_RES_IOPORT, 0, AMDSB_PMIO_INDEX, 424 AMDSB_PMIO_WIDTH); 425 if (rc != 0) { 426 device_printf(dev, "bus_set_resource for IO failed\n"); 427 return (ENXIO); 428 } 429 rid = 0; 430 res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 431 RF_ACTIVE | RF_SHAREABLE); 432 if (res == NULL) { 433 device_printf(dev, "bus_alloc_resource for IO failed\n"); 434 return (ENXIO); 435 } 436 437 smb_dev = pci_find_bsf(0, 20, 0); 438 KASSERT(smb_dev != NULL, ("can't find SMBus PCI device\n")); 439 devid = pci_get_devid(smb_dev); 440 revid = pci_get_revid(smb_dev); 441 if (devid == AMDSB_SMBUS_DEVID && revid < AMDSB8_SMBUS_REVID) 442 amdsbwd_probe_sb7xx(dev, res, &addr); 443 else if (devid == AMDSB_SMBUS_DEVID || 444 (devid == AMDFCH_SMBUS_DEVID && revid < AMDFCH41_SMBUS_REVID) || 445 (devid == AMDCZ_SMBUS_DEVID && revid < AMDCZ49_SMBUS_REVID)) 446 amdsbwd_probe_sb8xx(dev, res, &addr); 447 else 448 amdsbwd_probe_fch41(dev, res, &addr); 449 450 bus_release_resource(dev, SYS_RES_IOPORT, rid, res); 451 bus_delete_resource(dev, SYS_RES_IOPORT, rid); 452 453 amdsbwd_verbose_printf(dev, "memory base address = %#010x\n", addr); 454 rc = bus_set_resource(dev, SYS_RES_MEMORY, 0, addr + AMDSB_WD_CTRL, 455 AMDSB_WDIO_REG_WIDTH); 456 if (rc != 0) { 457 device_printf(dev, "bus_set_resource for control failed\n"); 458 return (ENXIO); 459 } 460 rc = bus_set_resource(dev, SYS_RES_MEMORY, 1, addr + AMDSB_WD_COUNT, 461 AMDSB_WDIO_REG_WIDTH); 462 if (rc != 0) { 463 device_printf(dev, "bus_set_resource for count failed\n"); 464 return (ENXIO); 465 } 466 467 return (0); 468 } 469 470 static int 471 amdsbwd_attach_sb(device_t dev, struct amdsbwd_softc *sc) 472 { 473 474 sc->max_ticks = UINT16_MAX; 475 sc->rid_ctrl = 0; 476 sc->rid_count = 1; 477 478 sc->ms_per_tick = 1000; 479 480 sc->res_ctrl = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 481 &sc->rid_ctrl, RF_ACTIVE); 482 if (sc->res_ctrl == NULL) { 483 device_printf(dev, "bus_alloc_resource for ctrl failed\n"); 484 return (ENXIO); 485 } 486 sc->res_count = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 487 &sc->rid_count, RF_ACTIVE); 488 if (sc->res_count == NULL) { 489 device_printf(dev, "bus_alloc_resource for count failed\n"); 490 return (ENXIO); 491 } 492 return (0); 493 } 494 495 static int 496 amdsbwd_attach(device_t dev) 497 { 498 struct amdsbwd_softc *sc; 499 int rc; 500 501 sc = device_get_softc(dev); 502 sc->dev = dev; 503 504 rc = amdsbwd_attach_sb(dev, sc); 505 if (rc != 0) 506 goto fail; 507 508 #ifdef AMDSBWD_DEBUG 509 device_printf(dev, "wd ctrl = %#04x\n", wdctrl_read(sc)); 510 device_printf(dev, "wd count = %#04x\n", wdcount_read(sc)); 511 #endif 512 513 /* Setup initial state of Watchdog Control. */ 514 wdctrl_write(sc, AMDSB_WD_FIRED); 515 516 if (wdctrl_read(sc) & AMDSB_WD_DISABLE) { 517 device_printf(dev, "watchdog hardware is disabled\n"); 518 goto fail; 519 } 520 521 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, amdsbwd_event, sc, 522 EVENTHANDLER_PRI_ANY); 523 524 return (0); 525 526 fail: 527 amdsbwd_detach(dev); 528 return (ENXIO); 529 } 530 531 static int 532 amdsbwd_detach(device_t dev) 533 { 534 struct amdsbwd_softc *sc; 535 536 sc = device_get_softc(dev); 537 if (sc->ev_tag != NULL) 538 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag); 539 540 if (sc->active) 541 amdsbwd_tmr_disable(sc); 542 543 if (sc->res_ctrl != NULL) 544 bus_release_resource(dev, SYS_RES_MEMORY, sc->rid_ctrl, 545 sc->res_ctrl); 546 547 if (sc->res_count != NULL) 548 bus_release_resource(dev, SYS_RES_MEMORY, sc->rid_count, 549 sc->res_count); 550 551 return (0); 552 } 553 554