1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2009 Andriy Gapon <avg@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * This is a driver for watchdog timer present in AMD SB600/SB7xx/SB8xx 31 * southbridges. 32 * Please see the following specifications for the descriptions of the 33 * registers and flags: 34 * - AMD SB600 Register Reference Guide, Public Version, Rev. 3.03 (SB600 RRG) 35 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/46155_sb600_rrg_pub_3.03.pdf 36 * - AMD SB700/710/750 Register Reference Guide (RRG) 37 * http://developer.amd.com/assets/43009_sb7xx_rrg_pub_1.00.pdf 38 * - AMD SB700/710/750 Register Programming Requirements (RPR) 39 * http://developer.amd.com/assets/42413_sb7xx_rpr_pub_1.00.pdf 40 * - AMD SB800-Series Southbridges Register Reference Guide (RRG) 41 * http://support.amd.com/us/Embedded_TechDocs/45482.pdf 42 * Please see the following for Watchdog Resource Table specification: 43 * - Watchdog Timer Hardware Requirements for Windows Server 2003 (WDRT) 44 * http://www.microsoft.com/whdc/system/sysinternals/watchdog.mspx 45 * AMD SB600/SB7xx/SB8xx watchdog hardware seems to conform to the above 46 * specifications, but the table hasn't been spotted in the wild yet. 47 */ 48 49 #include <sys/cdefs.h> 50 __FBSDID("$FreeBSD$"); 51 52 #include <sys/param.h> 53 #include <sys/kernel.h> 54 #include <sys/module.h> 55 #include <sys/systm.h> 56 #include <sys/sysctl.h> 57 #include <sys/bus.h> 58 #include <machine/bus.h> 59 #include <sys/rman.h> 60 #include <machine/resource.h> 61 #include <sys/watchdog.h> 62 63 #include <dev/pci/pcivar.h> 64 #include <dev/amdsbwd/amd_chipset.h> 65 #include <isa/isavar.h> 66 67 /* 68 * Registers in the Watchdog IO space. 69 * See SB7xx RRG 2.3.4, WDRT. 70 */ 71 #define AMDSB_WD_CTRL 0x00 72 #define AMDSB_WD_RUN 0x01 73 #define AMDSB_WD_FIRED 0x02 74 #define AMDSB_WD_SHUTDOWN 0x04 75 #define AMDSB_WD_DISABLE 0x08 76 #define AMDSB_WD_RESERVED 0x70 77 #define AMDSB_WD_RELOAD 0x80 78 #define AMDSB_WD_COUNT 0x04 79 #define AMDSB_WD_COUNT_MASK 0xffff 80 #define AMDSB_WDIO_REG_WIDTH 4 81 82 #define amdsbwd_verbose_printf(dev, ...) \ 83 do { \ 84 if (bootverbose) \ 85 device_printf(dev, __VA_ARGS__);\ 86 } while (0) 87 88 struct amdsbwd_softc { 89 device_t dev; 90 eventhandler_tag ev_tag; 91 struct resource *res_ctrl; 92 struct resource *res_count; 93 int rid_ctrl; 94 int rid_count; 95 int ms_per_tick; 96 int max_ticks; 97 int active; 98 unsigned int timeout; 99 }; 100 101 static void amdsbwd_identify(driver_t *driver, device_t parent); 102 static int amdsbwd_probe(device_t dev); 103 static int amdsbwd_attach(device_t dev); 104 static int amdsbwd_detach(device_t dev); 105 106 static device_method_t amdsbwd_methods[] = { 107 DEVMETHOD(device_identify, amdsbwd_identify), 108 DEVMETHOD(device_probe, amdsbwd_probe), 109 DEVMETHOD(device_attach, amdsbwd_attach), 110 DEVMETHOD(device_detach, amdsbwd_detach), 111 #if 0 112 DEVMETHOD(device_shutdown, amdsbwd_detach), 113 #endif 114 DEVMETHOD_END 115 }; 116 117 static devclass_t amdsbwd_devclass; 118 static driver_t amdsbwd_driver = { 119 "amdsbwd", 120 amdsbwd_methods, 121 sizeof(struct amdsbwd_softc) 122 }; 123 124 DRIVER_MODULE(amdsbwd, isa, amdsbwd_driver, amdsbwd_devclass, NULL, NULL); 125 126 127 static uint8_t 128 pmio_read(struct resource *res, uint8_t reg) 129 { 130 bus_write_1(res, 0, reg); /* Index */ 131 return (bus_read_1(res, 1)); /* Data */ 132 } 133 134 static void 135 pmio_write(struct resource *res, uint8_t reg, uint8_t val) 136 { 137 bus_write_1(res, 0, reg); /* Index */ 138 bus_write_1(res, 1, val); /* Data */ 139 } 140 141 static uint32_t 142 wdctrl_read(struct amdsbwd_softc *sc) 143 { 144 return (bus_read_4(sc->res_ctrl, 0)); 145 } 146 147 static void 148 wdctrl_write(struct amdsbwd_softc *sc, uint32_t val) 149 { 150 bus_write_4(sc->res_ctrl, 0, val); 151 } 152 153 static __unused uint32_t 154 wdcount_read(struct amdsbwd_softc *sc) 155 { 156 return (bus_read_4(sc->res_count, 0)); 157 } 158 159 static void 160 wdcount_write(struct amdsbwd_softc *sc, uint32_t val) 161 { 162 bus_write_4(sc->res_count, 0, val); 163 } 164 165 static void 166 amdsbwd_tmr_enable(struct amdsbwd_softc *sc) 167 { 168 uint32_t val; 169 170 val = wdctrl_read(sc); 171 val |= AMDSB_WD_RUN; 172 wdctrl_write(sc, val); 173 sc->active = 1; 174 amdsbwd_verbose_printf(sc->dev, "timer enabled\n"); 175 } 176 177 static void 178 amdsbwd_tmr_disable(struct amdsbwd_softc *sc) 179 { 180 uint32_t val; 181 182 val = wdctrl_read(sc); 183 val &= ~AMDSB_WD_RUN; 184 wdctrl_write(sc, val); 185 sc->active = 0; 186 amdsbwd_verbose_printf(sc->dev, "timer disabled\n"); 187 } 188 189 static void 190 amdsbwd_tmr_reload(struct amdsbwd_softc *sc) 191 { 192 uint32_t val; 193 194 val = wdctrl_read(sc); 195 val |= AMDSB_WD_RELOAD; 196 wdctrl_write(sc, val); 197 } 198 199 static void 200 amdsbwd_tmr_set(struct amdsbwd_softc *sc, uint16_t timeout) 201 { 202 203 timeout &= AMDSB_WD_COUNT_MASK; 204 wdcount_write(sc, timeout); 205 sc->timeout = timeout; 206 amdsbwd_verbose_printf(sc->dev, "timeout set to %u ticks\n", timeout); 207 } 208 209 static void 210 amdsbwd_event(void *arg, unsigned int cmd, int *error) 211 { 212 struct amdsbwd_softc *sc = arg; 213 unsigned int timeout; 214 215 /* convert from power-of-two-ns to WDT ticks */ 216 cmd &= WD_INTERVAL; 217 if (cmd < WD_TO_1SEC) 218 cmd = 0; 219 if (cmd) { 220 timeout = ((uint64_t)1 << (cmd - WD_TO_1MS)) / sc->ms_per_tick; 221 if (timeout > sc->max_ticks) 222 timeout = sc->max_ticks; 223 if (timeout != sc->timeout) { 224 amdsbwd_tmr_set(sc, timeout); 225 if (!sc->active) 226 amdsbwd_tmr_enable(sc); 227 } 228 amdsbwd_tmr_reload(sc); 229 *error = 0; 230 } else { 231 if (sc->active) 232 amdsbwd_tmr_disable(sc); 233 } 234 } 235 236 static void 237 amdsbwd_identify(driver_t *driver, device_t parent) 238 { 239 device_t child; 240 device_t smb_dev; 241 242 if (resource_disabled("amdsbwd", 0)) 243 return; 244 if (device_find_child(parent, "amdsbwd", -1) != NULL) 245 return; 246 247 /* 248 * Try to identify SB600/SB7xx by PCI Device ID of SMBus device 249 * that should be present at bus 0, device 20, function 0. 250 */ 251 smb_dev = pci_find_bsf(0, 20, 0); 252 if (smb_dev == NULL) 253 return; 254 if (pci_get_devid(smb_dev) != AMDSB_SMBUS_DEVID && 255 pci_get_devid(smb_dev) != AMDFCH_SMBUS_DEVID && 256 pci_get_devid(smb_dev) != AMDCZ_SMBUS_DEVID) 257 return; 258 259 child = BUS_ADD_CHILD(parent, ISA_ORDER_SPECULATIVE, "amdsbwd", -1); 260 if (child == NULL) 261 device_printf(parent, "add amdsbwd child failed\n"); 262 } 263 264 265 static void 266 amdsbwd_probe_sb7xx(device_t dev, struct resource *pmres, uint32_t *addr) 267 { 268 uint8_t val; 269 int i; 270 271 /* Report cause of previous reset for user's convenience. */ 272 val = pmio_read(pmres, AMDSB_PM_RESET_STATUS0); 273 if (val != 0) 274 amdsbwd_verbose_printf(dev, "ResetStatus0 = %#04x\n", val); 275 val = pmio_read(pmres, AMDSB_PM_RESET_STATUS1); 276 if (val != 0) 277 amdsbwd_verbose_printf(dev, "ResetStatus1 = %#04x\n", val); 278 if ((val & AMDSB_WD_RST_STS) != 0) 279 device_printf(dev, "Previous Reset was caused by Watchdog\n"); 280 281 /* Find base address of memory mapped WDT registers. */ 282 for (*addr = 0, i = 0; i < 4; i++) { 283 *addr <<= 8; 284 *addr |= pmio_read(pmres, AMDSB_PM_WDT_BASE_MSB - i); 285 } 286 *addr &= ~0x07u; 287 288 /* Set watchdog timer tick to 1s. */ 289 val = pmio_read(pmres, AMDSB_PM_WDT_CTRL); 290 val &= ~AMDSB_WDT_RES_MASK; 291 val |= AMDSB_WDT_RES_1S; 292 pmio_write(pmres, AMDSB_PM_WDT_CTRL, val); 293 294 /* Enable watchdog device (in stopped state). */ 295 val = pmio_read(pmres, AMDSB_PM_WDT_CTRL); 296 val &= ~AMDSB_WDT_DISABLE; 297 pmio_write(pmres, AMDSB_PM_WDT_CTRL, val); 298 299 /* 300 * XXX TODO: Ensure that watchdog decode is enabled 301 * (register 0x41, bit 3). 302 */ 303 device_set_desc(dev, "AMD SB600/SB7xx Watchdog Timer"); 304 } 305 306 static void 307 amdsbwd_probe_sb8xx(device_t dev, struct resource *pmres, uint32_t *addr) 308 { 309 uint8_t val; 310 int i; 311 312 /* Report cause of previous reset for user's convenience. */ 313 val = pmio_read(pmres, AMDSB8_PM_RESET_STATUS0); 314 if (val != 0) 315 amdsbwd_verbose_printf(dev, "ResetStatus0 = %#04x\n", val); 316 val = pmio_read(pmres, AMDSB8_PM_RESET_STATUS1); 317 if (val != 0) 318 amdsbwd_verbose_printf(dev, "ResetStatus1 = %#04x\n", val); 319 if ((val & AMDSB8_WD_RST_STS) != 0) 320 device_printf(dev, "Previous Reset was caused by Watchdog\n"); 321 322 /* Find base address of memory mapped WDT registers. */ 323 for (*addr = 0, i = 0; i < 4; i++) { 324 *addr <<= 8; 325 *addr |= pmio_read(pmres, AMDSB8_PM_WDT_EN + 3 - i); 326 } 327 *addr &= ~0x07u; 328 329 /* Set watchdog timer tick to 1s. */ 330 val = pmio_read(pmres, AMDSB8_PM_WDT_CTRL); 331 val &= ~AMDSB8_WDT_RES_MASK; 332 val |= AMDSB8_WDT_1HZ; 333 pmio_write(pmres, AMDSB8_PM_WDT_CTRL, val); 334 #ifdef AMDSBWD_DEBUG 335 val = pmio_read(pmres, AMDSB8_PM_WDT_CTRL); 336 amdsbwd_verbose_printf(dev, "AMDSB8_PM_WDT_CTRL value = %#04x\n", val); 337 #endif 338 339 /* 340 * Enable watchdog device (in stopped state) 341 * and decoding of its address. 342 */ 343 val = pmio_read(pmres, AMDSB8_PM_WDT_EN); 344 val &= ~AMDSB8_WDT_DISABLE; 345 val |= AMDSB8_WDT_DEC_EN; 346 pmio_write(pmres, AMDSB8_PM_WDT_EN, val); 347 #ifdef AMDSBWD_DEBUG 348 val = pmio_read(pmres, AMDSB8_PM_WDT_EN); 349 device_printf(dev, "AMDSB8_PM_WDT_EN value = %#04x\n", val); 350 #endif 351 device_set_desc(dev, "AMD SB8xx/SB9xx/Axx Watchdog Timer"); 352 } 353 354 static void 355 amdsbwd_probe_fch41(device_t dev, struct resource *pmres, uint32_t *addr) 356 { 357 uint8_t val; 358 359 val = pmio_read(pmres, AMDFCH41_PM_ISA_CTRL); 360 if ((val & AMDFCH41_MMIO_EN) != 0) { 361 /* Fixed offset for the watchdog within ACPI MMIO range. */ 362 amdsbwd_verbose_printf(dev, "ACPI MMIO range is enabled\n"); 363 *addr = AMDFCH41_MMIO_ADDR + AMDFCH41_MMIO_WDT_OFF; 364 } else { 365 /* 366 * Enable decoding of watchdog MMIO address. 367 */ 368 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN0); 369 val |= AMDFCH41_WDT_EN; 370 pmio_write(pmres, AMDFCH41_PM_DECODE_EN0, val); 371 #ifdef AMDSBWD_DEBUG 372 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN0); 373 device_printf(dev, "AMDFCH41_PM_DECODE_EN0 value = %#04x\n", 374 val); 375 #endif 376 377 /* Special fixed MMIO range for the watchdog. */ 378 *addr = AMDFCH41_WDT_FIXED_ADDR; 379 } 380 381 /* 382 * Set watchdog timer tick to 1s and 383 * enable the watchdog device (in stopped state). 384 */ 385 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN3); 386 val &= ~AMDFCH41_WDT_RES_MASK; 387 val |= AMDFCH41_WDT_RES_1S; 388 val &= ~AMDFCH41_WDT_EN_MASK; 389 val |= AMDFCH41_WDT_ENABLE; 390 pmio_write(pmres, AMDFCH41_PM_DECODE_EN3, val); 391 #ifdef AMDSBWD_DEBUG 392 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN3); 393 amdsbwd_verbose_printf(dev, "AMDFCH41_PM_DECODE_EN3 value = %#04x\n", 394 val); 395 #endif 396 device_set_desc(dev, "AMD FCH Rev 41h+ Watchdog Timer"); 397 } 398 399 static int 400 amdsbwd_probe(device_t dev) 401 { 402 struct resource *res; 403 device_t smb_dev; 404 uint32_t addr; 405 int rid; 406 int rc; 407 uint32_t devid; 408 uint8_t revid; 409 410 /* Do not claim some ISA PnP device by accident. */ 411 if (isa_get_logicalid(dev) != 0) 412 return (ENXIO); 413 414 rc = bus_set_resource(dev, SYS_RES_IOPORT, 0, AMDSB_PMIO_INDEX, 415 AMDSB_PMIO_WIDTH); 416 if (rc != 0) { 417 device_printf(dev, "bus_set_resource for IO failed\n"); 418 return (ENXIO); 419 } 420 rid = 0; 421 res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 422 RF_ACTIVE | RF_SHAREABLE); 423 if (res == NULL) { 424 device_printf(dev, "bus_alloc_resource for IO failed\n"); 425 return (ENXIO); 426 } 427 428 smb_dev = pci_find_bsf(0, 20, 0); 429 KASSERT(smb_dev != NULL, ("can't find SMBus PCI device\n")); 430 devid = pci_get_devid(smb_dev); 431 revid = pci_get_revid(smb_dev); 432 if (devid == AMDSB_SMBUS_DEVID && revid < AMDSB8_SMBUS_REVID) 433 amdsbwd_probe_sb7xx(dev, res, &addr); 434 else if (devid == AMDSB_SMBUS_DEVID || 435 (devid == AMDFCH_SMBUS_DEVID && revid < AMDFCH41_SMBUS_REVID) || 436 (devid == AMDCZ_SMBUS_DEVID && revid < AMDCZ49_SMBUS_REVID)) 437 amdsbwd_probe_sb8xx(dev, res, &addr); 438 else 439 amdsbwd_probe_fch41(dev, res, &addr); 440 441 bus_release_resource(dev, SYS_RES_IOPORT, rid, res); 442 bus_delete_resource(dev, SYS_RES_IOPORT, rid); 443 444 amdsbwd_verbose_printf(dev, "memory base address = %#010x\n", addr); 445 rc = bus_set_resource(dev, SYS_RES_MEMORY, 0, addr + AMDSB_WD_CTRL, 446 AMDSB_WDIO_REG_WIDTH); 447 if (rc != 0) { 448 device_printf(dev, "bus_set_resource for control failed\n"); 449 return (ENXIO); 450 } 451 rc = bus_set_resource(dev, SYS_RES_MEMORY, 1, addr + AMDSB_WD_COUNT, 452 AMDSB_WDIO_REG_WIDTH); 453 if (rc != 0) { 454 device_printf(dev, "bus_set_resource for count failed\n"); 455 return (ENXIO); 456 } 457 458 return (0); 459 } 460 461 static int 462 amdsbwd_attach_sb(device_t dev, struct amdsbwd_softc *sc) 463 { 464 465 sc->max_ticks = UINT16_MAX; 466 sc->rid_ctrl = 0; 467 sc->rid_count = 1; 468 469 sc->ms_per_tick = 1000; 470 471 sc->res_ctrl = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 472 &sc->rid_ctrl, RF_ACTIVE); 473 if (sc->res_ctrl == NULL) { 474 device_printf(dev, "bus_alloc_resource for ctrl failed\n"); 475 return (ENXIO); 476 } 477 sc->res_count = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 478 &sc->rid_count, RF_ACTIVE); 479 if (sc->res_count == NULL) { 480 device_printf(dev, "bus_alloc_resource for count failed\n"); 481 return (ENXIO); 482 } 483 return (0); 484 } 485 486 static int 487 amdsbwd_attach(device_t dev) 488 { 489 struct amdsbwd_softc *sc; 490 int rc; 491 492 sc = device_get_softc(dev); 493 sc->dev = dev; 494 495 rc = amdsbwd_attach_sb(dev, sc); 496 if (rc != 0) 497 goto fail; 498 499 #ifdef AMDSBWD_DEBUG 500 device_printf(dev, "wd ctrl = %#04x\n", wdctrl_read(sc)); 501 device_printf(dev, "wd count = %#04x\n", wdcount_read(sc)); 502 #endif 503 504 /* Setup initial state of Watchdog Control. */ 505 wdctrl_write(sc, AMDSB_WD_FIRED); 506 507 if (wdctrl_read(sc) & AMDSB_WD_DISABLE) { 508 device_printf(dev, "watchdog hardware is disabled\n"); 509 goto fail; 510 } 511 512 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, amdsbwd_event, sc, 513 EVENTHANDLER_PRI_ANY); 514 515 return (0); 516 517 fail: 518 amdsbwd_detach(dev); 519 return (ENXIO); 520 } 521 522 static int 523 amdsbwd_detach(device_t dev) 524 { 525 struct amdsbwd_softc *sc; 526 527 sc = device_get_softc(dev); 528 if (sc->ev_tag != NULL) 529 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag); 530 531 if (sc->active) 532 amdsbwd_tmr_disable(sc); 533 534 if (sc->res_ctrl != NULL) 535 bus_release_resource(dev, SYS_RES_MEMORY, sc->rid_ctrl, 536 sc->res_ctrl); 537 538 if (sc->res_count != NULL) 539 bus_release_resource(dev, SYS_RES_MEMORY, sc->rid_count, 540 sc->res_count); 541 542 return (0); 543 } 544 545