1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2009 Andriy Gapon <avg@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * This is a driver for watchdog timer present in AMD SB600/SB7xx/SB8xx 31 * southbridges. 32 * Please see the following specifications for the descriptions of the 33 * registers and flags: 34 * - AMD SB600 Register Reference Guide, Public Version, Rev. 3.03 (SB600 RRG) 35 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/46155_sb600_rrg_pub_3.03.pdf 36 * - AMD SB700/710/750 Register Reference Guide (RRG) 37 * http://developer.amd.com/assets/43009_sb7xx_rrg_pub_1.00.pdf 38 * - AMD SB700/710/750 Register Programming Requirements (RPR) 39 * http://developer.amd.com/assets/42413_sb7xx_rpr_pub_1.00.pdf 40 * - AMD SB800-Series Southbridges Register Reference Guide (RRG) 41 * http://support.amd.com/us/Embedded_TechDocs/45482.pdf 42 * Please see the following for Watchdog Resource Table specification: 43 * - Watchdog Timer Hardware Requirements for Windows Server 2003 (WDRT) 44 * http://www.microsoft.com/whdc/system/sysinternals/watchdog.mspx 45 * AMD SB600/SB7xx/SB8xx watchdog hardware seems to conform to the above 46 * specifications, but the table hasn't been spotted in the wild yet. 47 */ 48 49 #include <sys/cdefs.h> 50 __FBSDID("$FreeBSD$"); 51 52 #include "opt_amdsbwd.h" 53 54 #include <sys/param.h> 55 #include <sys/eventhandler.h> 56 #include <sys/kernel.h> 57 #include <sys/module.h> 58 #include <sys/systm.h> 59 #include <sys/sysctl.h> 60 #include <sys/bus.h> 61 #include <machine/bus.h> 62 #include <sys/rman.h> 63 #include <machine/resource.h> 64 #include <sys/watchdog.h> 65 66 #include <dev/pci/pcivar.h> 67 #include <dev/amdsbwd/amd_chipset.h> 68 #include <isa/isavar.h> 69 70 /* 71 * Registers in the Watchdog IO space. 72 * See SB7xx RRG 2.3.4, WDRT. 73 */ 74 #define AMDSB_WD_CTRL 0x00 75 #define AMDSB_WD_RUN 0x01 76 #define AMDSB_WD_FIRED 0x02 77 #define AMDSB_WD_SHUTDOWN 0x04 78 #define AMDSB_WD_DISABLE 0x08 79 #define AMDSB_WD_RESERVED 0x70 80 #define AMDSB_WD_RELOAD 0x80 81 #define AMDSB_WD_COUNT 0x04 82 #define AMDSB_WD_COUNT_MASK 0xffff 83 #define AMDSB_WDIO_REG_WIDTH 4 84 85 #define amdsbwd_verbose_printf(dev, ...) \ 86 do { \ 87 if (bootverbose) \ 88 device_printf(dev, __VA_ARGS__);\ 89 } while (0) 90 91 struct amdsbwd_softc { 92 device_t dev; 93 eventhandler_tag ev_tag; 94 struct resource *res_ctrl; 95 struct resource *res_count; 96 int rid_ctrl; 97 int rid_count; 98 int ms_per_tick; 99 int max_ticks; 100 int active; 101 unsigned int timeout; 102 }; 103 104 static void amdsbwd_identify(driver_t *driver, device_t parent); 105 static int amdsbwd_probe(device_t dev); 106 static int amdsbwd_attach(device_t dev); 107 static int amdsbwd_detach(device_t dev); 108 static int amdsbwd_suspend(device_t dev); 109 static int amdsbwd_resume(device_t dev); 110 111 static device_method_t amdsbwd_methods[] = { 112 DEVMETHOD(device_identify, amdsbwd_identify), 113 DEVMETHOD(device_probe, amdsbwd_probe), 114 DEVMETHOD(device_attach, amdsbwd_attach), 115 DEVMETHOD(device_detach, amdsbwd_detach), 116 DEVMETHOD(device_suspend, amdsbwd_suspend), 117 DEVMETHOD(device_resume, amdsbwd_resume), 118 #if 0 119 DEVMETHOD(device_shutdown, amdsbwd_detach), 120 #endif 121 DEVMETHOD_END 122 }; 123 124 static devclass_t amdsbwd_devclass; 125 static driver_t amdsbwd_driver = { 126 "amdsbwd", 127 amdsbwd_methods, 128 sizeof(struct amdsbwd_softc) 129 }; 130 131 DRIVER_MODULE(amdsbwd, isa, amdsbwd_driver, amdsbwd_devclass, NULL, NULL); 132 133 134 static uint8_t 135 pmio_read(struct resource *res, uint8_t reg) 136 { 137 bus_write_1(res, 0, reg); /* Index */ 138 return (bus_read_1(res, 1)); /* Data */ 139 } 140 141 static void 142 pmio_write(struct resource *res, uint8_t reg, uint8_t val) 143 { 144 bus_write_1(res, 0, reg); /* Index */ 145 bus_write_1(res, 1, val); /* Data */ 146 } 147 148 static uint32_t 149 wdctrl_read(struct amdsbwd_softc *sc) 150 { 151 return (bus_read_4(sc->res_ctrl, 0)); 152 } 153 154 static void 155 wdctrl_write(struct amdsbwd_softc *sc, uint32_t val) 156 { 157 bus_write_4(sc->res_ctrl, 0, val); 158 } 159 160 static __unused uint32_t 161 wdcount_read(struct amdsbwd_softc *sc) 162 { 163 return (bus_read_4(sc->res_count, 0)); 164 } 165 166 static void 167 wdcount_write(struct amdsbwd_softc *sc, uint32_t val) 168 { 169 bus_write_4(sc->res_count, 0, val); 170 } 171 172 static void 173 amdsbwd_tmr_enable(struct amdsbwd_softc *sc) 174 { 175 uint32_t val; 176 177 val = wdctrl_read(sc); 178 val |= AMDSB_WD_RUN; 179 wdctrl_write(sc, val); 180 sc->active = 1; 181 amdsbwd_verbose_printf(sc->dev, "timer enabled\n"); 182 } 183 184 static void 185 amdsbwd_tmr_disable(struct amdsbwd_softc *sc) 186 { 187 uint32_t val; 188 189 val = wdctrl_read(sc); 190 val &= ~AMDSB_WD_RUN; 191 wdctrl_write(sc, val); 192 sc->active = 0; 193 amdsbwd_verbose_printf(sc->dev, "timer disabled\n"); 194 } 195 196 static void 197 amdsbwd_tmr_reload(struct amdsbwd_softc *sc) 198 { 199 uint32_t val; 200 201 val = wdctrl_read(sc); 202 val |= AMDSB_WD_RELOAD; 203 wdctrl_write(sc, val); 204 } 205 206 static void 207 amdsbwd_tmr_set(struct amdsbwd_softc *sc, uint16_t timeout) 208 { 209 210 timeout &= AMDSB_WD_COUNT_MASK; 211 wdcount_write(sc, timeout); 212 sc->timeout = timeout; 213 amdsbwd_verbose_printf(sc->dev, "timeout set to %u ticks\n", timeout); 214 } 215 216 static void 217 amdsbwd_event(void *arg, unsigned int cmd, int *error) 218 { 219 struct amdsbwd_softc *sc = arg; 220 uint64_t timeout; 221 222 if (cmd != 0) { 223 timeout = 0; 224 cmd &= WD_INTERVAL; 225 if (cmd >= WD_TO_1MS) { 226 timeout = (uint64_t)1 << (cmd - WD_TO_1MS); 227 timeout = timeout / sc->ms_per_tick; 228 } 229 /* For a too short timeout use 1 tick. */ 230 if (timeout == 0) 231 timeout = 1; 232 /* For a too long timeout stop the timer. */ 233 if (timeout > sc->max_ticks) 234 timeout = 0; 235 } else { 236 timeout = 0; 237 } 238 239 if (timeout != 0) { 240 if (timeout != sc->timeout) 241 amdsbwd_tmr_set(sc, timeout); 242 if (!sc->active) 243 amdsbwd_tmr_enable(sc); 244 amdsbwd_tmr_reload(sc); 245 *error = 0; 246 } else { 247 if (sc->active) 248 amdsbwd_tmr_disable(sc); 249 } 250 } 251 252 static void 253 amdsbwd_identify(driver_t *driver, device_t parent) 254 { 255 device_t child; 256 device_t smb_dev; 257 258 if (resource_disabled("amdsbwd", 0)) 259 return; 260 if (device_find_child(parent, "amdsbwd", -1) != NULL) 261 return; 262 263 /* 264 * Try to identify SB600/SB7xx by PCI Device ID of SMBus device 265 * that should be present at bus 0, device 20, function 0. 266 */ 267 smb_dev = pci_find_bsf(0, 20, 0); 268 if (smb_dev == NULL) 269 return; 270 if (pci_get_devid(smb_dev) != AMDSB_SMBUS_DEVID && 271 pci_get_devid(smb_dev) != AMDFCH_SMBUS_DEVID && 272 pci_get_devid(smb_dev) != AMDCZ_SMBUS_DEVID) 273 return; 274 275 child = BUS_ADD_CHILD(parent, ISA_ORDER_SPECULATIVE, "amdsbwd", -1); 276 if (child == NULL) 277 device_printf(parent, "add amdsbwd child failed\n"); 278 } 279 280 281 static void 282 amdsbwd_probe_sb7xx(device_t dev, struct resource *pmres, uint32_t *addr) 283 { 284 uint8_t val; 285 int i; 286 287 /* Report cause of previous reset for user's convenience. */ 288 val = pmio_read(pmres, AMDSB_PM_RESET_STATUS0); 289 if (val != 0) 290 amdsbwd_verbose_printf(dev, "ResetStatus0 = %#04x\n", val); 291 val = pmio_read(pmres, AMDSB_PM_RESET_STATUS1); 292 if (val != 0) 293 amdsbwd_verbose_printf(dev, "ResetStatus1 = %#04x\n", val); 294 if ((val & AMDSB_WD_RST_STS) != 0) 295 device_printf(dev, "Previous Reset was caused by Watchdog\n"); 296 297 /* Find base address of memory mapped WDT registers. */ 298 for (*addr = 0, i = 0; i < 4; i++) { 299 *addr <<= 8; 300 *addr |= pmio_read(pmres, AMDSB_PM_WDT_BASE_MSB - i); 301 } 302 *addr &= ~0x07u; 303 304 /* Set watchdog timer tick to 1s. */ 305 val = pmio_read(pmres, AMDSB_PM_WDT_CTRL); 306 val &= ~AMDSB_WDT_RES_MASK; 307 val |= AMDSB_WDT_RES_1S; 308 pmio_write(pmres, AMDSB_PM_WDT_CTRL, val); 309 310 /* Enable watchdog device (in stopped state). */ 311 val = pmio_read(pmres, AMDSB_PM_WDT_CTRL); 312 val &= ~AMDSB_WDT_DISABLE; 313 pmio_write(pmres, AMDSB_PM_WDT_CTRL, val); 314 315 /* 316 * XXX TODO: Ensure that watchdog decode is enabled 317 * (register 0x41, bit 3). 318 */ 319 device_set_desc(dev, "AMD SB600/SB7xx Watchdog Timer"); 320 } 321 322 static void 323 amdsbwd_probe_sb8xx(device_t dev, struct resource *pmres, uint32_t *addr) 324 { 325 uint32_t val; 326 int i; 327 328 /* Report cause of previous reset for user's convenience. */ 329 330 val = pmio_read(pmres, AMDSB8_PM_RESET_CTRL); 331 if ((val & AMDSB8_RST_STS_DIS) != 0) { 332 val &= ~AMDSB8_RST_STS_DIS; 333 pmio_write(pmres, AMDSB8_PM_RESET_CTRL, val); 334 } 335 val = 0; 336 for (i = 3; i >= 0; i--) { 337 val <<= 8; 338 val |= pmio_read(pmres, AMDSB8_PM_RESET_STATUS + i); 339 } 340 if (val != 0) 341 amdsbwd_verbose_printf(dev, "ResetStatus = 0x%08x\n", val); 342 if ((val & AMDSB8_WD_RST_STS) != 0) 343 device_printf(dev, "Previous Reset was caused by Watchdog\n"); 344 345 /* Find base address of memory mapped WDT registers. */ 346 for (*addr = 0, i = 0; i < 4; i++) { 347 *addr <<= 8; 348 *addr |= pmio_read(pmres, AMDSB8_PM_WDT_EN + 3 - i); 349 } 350 *addr &= ~0x07u; 351 352 /* Set watchdog timer tick to 1s. */ 353 val = pmio_read(pmres, AMDSB8_PM_WDT_CTRL); 354 val &= ~AMDSB8_WDT_RES_MASK; 355 val |= AMDSB8_WDT_1HZ; 356 pmio_write(pmres, AMDSB8_PM_WDT_CTRL, val); 357 #ifdef AMDSBWD_DEBUG 358 val = pmio_read(pmres, AMDSB8_PM_WDT_CTRL); 359 amdsbwd_verbose_printf(dev, "AMDSB8_PM_WDT_CTRL value = %#04x\n", val); 360 #endif 361 362 /* 363 * Enable watchdog device (in stopped state) 364 * and decoding of its address. 365 */ 366 val = pmio_read(pmres, AMDSB8_PM_WDT_EN); 367 val &= ~AMDSB8_WDT_DISABLE; 368 val |= AMDSB8_WDT_DEC_EN; 369 pmio_write(pmres, AMDSB8_PM_WDT_EN, val); 370 #ifdef AMDSBWD_DEBUG 371 val = pmio_read(pmres, AMDSB8_PM_WDT_EN); 372 device_printf(dev, "AMDSB8_PM_WDT_EN value = %#04x\n", val); 373 #endif 374 device_set_desc(dev, "AMD SB8xx/SB9xx/Axx Watchdog Timer"); 375 } 376 377 static void 378 amdsbwd_probe_fch41(device_t dev, struct resource *pmres, uint32_t *addr) 379 { 380 uint8_t val; 381 382 val = pmio_read(pmres, AMDFCH41_PM_ISA_CTRL); 383 if ((val & AMDFCH41_MMIO_EN) != 0) { 384 /* Fixed offset for the watchdog within ACPI MMIO range. */ 385 amdsbwd_verbose_printf(dev, "ACPI MMIO range is enabled\n"); 386 *addr = AMDFCH41_MMIO_ADDR + AMDFCH41_MMIO_WDT_OFF; 387 } else { 388 /* 389 * Enable decoding of watchdog MMIO address. 390 */ 391 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN0); 392 val |= AMDFCH41_WDT_EN; 393 pmio_write(pmres, AMDFCH41_PM_DECODE_EN0, val); 394 #ifdef AMDSBWD_DEBUG 395 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN0); 396 device_printf(dev, "AMDFCH41_PM_DECODE_EN0 value = %#04x\n", 397 val); 398 #endif 399 400 /* Special fixed MMIO range for the watchdog. */ 401 *addr = AMDFCH41_WDT_FIXED_ADDR; 402 } 403 404 /* 405 * Set watchdog timer tick to 1s and 406 * enable the watchdog device (in stopped state). 407 */ 408 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN3); 409 val &= ~AMDFCH41_WDT_RES_MASK; 410 val |= AMDFCH41_WDT_RES_1S; 411 val &= ~AMDFCH41_WDT_EN_MASK; 412 val |= AMDFCH41_WDT_ENABLE; 413 pmio_write(pmres, AMDFCH41_PM_DECODE_EN3, val); 414 #ifdef AMDSBWD_DEBUG 415 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN3); 416 amdsbwd_verbose_printf(dev, "AMDFCH41_PM_DECODE_EN3 value = %#04x\n", 417 val); 418 #endif 419 device_set_desc(dev, "AMD FCH Rev 41h+ Watchdog Timer"); 420 } 421 422 static int 423 amdsbwd_probe(device_t dev) 424 { 425 struct resource *res; 426 device_t smb_dev; 427 uint32_t addr; 428 int rid; 429 int rc; 430 uint32_t devid; 431 uint8_t revid; 432 433 /* Do not claim some ISA PnP device by accident. */ 434 if (isa_get_logicalid(dev) != 0) 435 return (ENXIO); 436 437 rc = bus_set_resource(dev, SYS_RES_IOPORT, 0, AMDSB_PMIO_INDEX, 438 AMDSB_PMIO_WIDTH); 439 if (rc != 0) { 440 device_printf(dev, "bus_set_resource for IO failed\n"); 441 return (ENXIO); 442 } 443 rid = 0; 444 res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 445 RF_ACTIVE | RF_SHAREABLE); 446 if (res == NULL) { 447 device_printf(dev, "bus_alloc_resource for IO failed\n"); 448 return (ENXIO); 449 } 450 451 smb_dev = pci_find_bsf(0, 20, 0); 452 KASSERT(smb_dev != NULL, ("can't find SMBus PCI device\n")); 453 devid = pci_get_devid(smb_dev); 454 revid = pci_get_revid(smb_dev); 455 if (devid == AMDSB_SMBUS_DEVID && revid < AMDSB8_SMBUS_REVID) 456 amdsbwd_probe_sb7xx(dev, res, &addr); 457 else if (devid == AMDSB_SMBUS_DEVID || 458 (devid == AMDFCH_SMBUS_DEVID && revid < AMDFCH41_SMBUS_REVID) || 459 (devid == AMDCZ_SMBUS_DEVID && revid < AMDCZ49_SMBUS_REVID)) 460 amdsbwd_probe_sb8xx(dev, res, &addr); 461 else 462 amdsbwd_probe_fch41(dev, res, &addr); 463 464 bus_release_resource(dev, SYS_RES_IOPORT, rid, res); 465 bus_delete_resource(dev, SYS_RES_IOPORT, rid); 466 467 amdsbwd_verbose_printf(dev, "memory base address = %#010x\n", addr); 468 rc = bus_set_resource(dev, SYS_RES_MEMORY, 0, addr + AMDSB_WD_CTRL, 469 AMDSB_WDIO_REG_WIDTH); 470 if (rc != 0) { 471 device_printf(dev, "bus_set_resource for control failed\n"); 472 return (ENXIO); 473 } 474 rc = bus_set_resource(dev, SYS_RES_MEMORY, 1, addr + AMDSB_WD_COUNT, 475 AMDSB_WDIO_REG_WIDTH); 476 if (rc != 0) { 477 device_printf(dev, "bus_set_resource for count failed\n"); 478 return (ENXIO); 479 } 480 481 return (0); 482 } 483 484 static int 485 amdsbwd_attach_sb(device_t dev, struct amdsbwd_softc *sc) 486 { 487 488 sc->max_ticks = UINT16_MAX; 489 sc->rid_ctrl = 0; 490 sc->rid_count = 1; 491 492 sc->ms_per_tick = 1000; 493 494 sc->res_ctrl = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 495 &sc->rid_ctrl, RF_ACTIVE); 496 if (sc->res_ctrl == NULL) { 497 device_printf(dev, "bus_alloc_resource for ctrl failed\n"); 498 return (ENXIO); 499 } 500 sc->res_count = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 501 &sc->rid_count, RF_ACTIVE); 502 if (sc->res_count == NULL) { 503 device_printf(dev, "bus_alloc_resource for count failed\n"); 504 return (ENXIO); 505 } 506 return (0); 507 } 508 509 static int 510 amdsbwd_attach(device_t dev) 511 { 512 struct amdsbwd_softc *sc; 513 int rc; 514 515 sc = device_get_softc(dev); 516 sc->dev = dev; 517 518 rc = amdsbwd_attach_sb(dev, sc); 519 if (rc != 0) 520 goto fail; 521 522 #ifdef AMDSBWD_DEBUG 523 device_printf(dev, "wd ctrl = %#04x\n", wdctrl_read(sc)); 524 device_printf(dev, "wd count = %#04x\n", wdcount_read(sc)); 525 #endif 526 527 /* Setup initial state of Watchdog Control. */ 528 wdctrl_write(sc, AMDSB_WD_FIRED); 529 530 if (wdctrl_read(sc) & AMDSB_WD_DISABLE) { 531 device_printf(dev, "watchdog hardware is disabled\n"); 532 goto fail; 533 } 534 535 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, amdsbwd_event, sc, 536 EVENTHANDLER_PRI_ANY); 537 538 return (0); 539 540 fail: 541 amdsbwd_detach(dev); 542 return (ENXIO); 543 } 544 545 static int 546 amdsbwd_detach(device_t dev) 547 { 548 struct amdsbwd_softc *sc; 549 550 sc = device_get_softc(dev); 551 if (sc->ev_tag != NULL) 552 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag); 553 554 if (sc->active) 555 amdsbwd_tmr_disable(sc); 556 557 if (sc->res_ctrl != NULL) 558 bus_release_resource(dev, SYS_RES_MEMORY, sc->rid_ctrl, 559 sc->res_ctrl); 560 561 if (sc->res_count != NULL) 562 bus_release_resource(dev, SYS_RES_MEMORY, sc->rid_count, 563 sc->res_count); 564 565 return (0); 566 } 567 568 static int 569 amdsbwd_suspend(device_t dev) 570 { 571 struct amdsbwd_softc *sc; 572 uint32_t val; 573 574 sc = device_get_softc(dev); 575 val = wdctrl_read(sc); 576 val &= ~AMDSB_WD_RUN; 577 wdctrl_write(sc, val); 578 return (0); 579 } 580 581 static int 582 amdsbwd_resume(device_t dev) 583 { 584 struct amdsbwd_softc *sc; 585 586 sc = device_get_softc(dev); 587 wdctrl_write(sc, AMDSB_WD_FIRED); 588 if (sc->active) { 589 amdsbwd_tmr_set(sc, sc->timeout); 590 amdsbwd_tmr_enable(sc); 591 amdsbwd_tmr_reload(sc); 592 } 593 return (0); 594 } 595