1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2009 Andriy Gapon <avg@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29 /* 30 * This is a driver for watchdog timer present in AMD SB600/SB7xx/SB8xx 31 * southbridges. 32 * Please see the following specifications for the descriptions of the 33 * registers and flags: 34 * - AMD SB600 Register Reference Guide, Public Version, Rev. 3.03 (SB600 RRG) 35 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/46155_sb600_rrg_pub_3.03.pdf 36 * - AMD SB700/710/750 Register Reference Guide (RRG) 37 * http://developer.amd.com/assets/43009_sb7xx_rrg_pub_1.00.pdf 38 * - AMD SB700/710/750 Register Programming Requirements (RPR) 39 * http://developer.amd.com/assets/42413_sb7xx_rpr_pub_1.00.pdf 40 * - AMD SB800-Series Southbridges Register Reference Guide (RRG) 41 * http://support.amd.com/us/Embedded_TechDocs/45482.pdf 42 * Please see the following for Watchdog Resource Table specification: 43 * - Watchdog Timer Hardware Requirements for Windows Server 2003 (WDRT) 44 * http://www.microsoft.com/whdc/system/sysinternals/watchdog.mspx 45 * AMD SB600/SB7xx/SB8xx watchdog hardware seems to conform to the above 46 * specifications, but the table hasn't been spotted in the wild yet. 47 */ 48 49 #include <sys/cdefs.h> 50 __FBSDID("$FreeBSD$"); 51 52 #include "opt_amdsbwd.h" 53 54 #include <sys/param.h> 55 #include <sys/eventhandler.h> 56 #include <sys/kernel.h> 57 #include <sys/module.h> 58 #include <sys/systm.h> 59 #include <sys/sysctl.h> 60 #include <sys/bus.h> 61 #include <machine/bus.h> 62 #include <sys/rman.h> 63 #include <machine/cputypes.h> 64 #include <machine/md_var.h> 65 #include <machine/resource.h> 66 #include <sys/watchdog.h> 67 68 #include <dev/pci/pcivar.h> 69 #include <dev/amdsbwd/amd_chipset.h> 70 #include <isa/isavar.h> 71 72 /* 73 * Registers in the Watchdog IO space. 74 * See SB7xx RRG 2.3.4, WDRT. 75 */ 76 #define AMDSB_WD_CTRL 0x00 77 #define AMDSB_WD_RUN 0x01 78 #define AMDSB_WD_FIRED 0x02 79 #define AMDSB_WD_SHUTDOWN 0x04 80 #define AMDSB_WD_DISABLE 0x08 81 #define AMDSB_WD_RESERVED 0x70 82 #define AMDSB_WD_RELOAD 0x80 83 #define AMDSB_WD_COUNT 0x04 84 #define AMDSB_WD_COUNT_MASK 0xffff 85 #define AMDSB_WDIO_REG_WIDTH 4 86 87 #define amdsbwd_verbose_printf(dev, ...) \ 88 do { \ 89 if (bootverbose) \ 90 device_printf(dev, __VA_ARGS__);\ 91 } while (0) 92 93 struct amdsbwd_softc { 94 device_t dev; 95 eventhandler_tag ev_tag; 96 struct resource *res_ctrl; 97 struct resource *res_count; 98 int rid_ctrl; 99 int rid_count; 100 int ms_per_tick; 101 int max_ticks; 102 int active; 103 unsigned int timeout; 104 }; 105 106 static void amdsbwd_identify(driver_t *driver, device_t parent); 107 static int amdsbwd_probe(device_t dev); 108 static int amdsbwd_attach(device_t dev); 109 static int amdsbwd_detach(device_t dev); 110 static int amdsbwd_suspend(device_t dev); 111 static int amdsbwd_resume(device_t dev); 112 113 static device_method_t amdsbwd_methods[] = { 114 DEVMETHOD(device_identify, amdsbwd_identify), 115 DEVMETHOD(device_probe, amdsbwd_probe), 116 DEVMETHOD(device_attach, amdsbwd_attach), 117 DEVMETHOD(device_detach, amdsbwd_detach), 118 DEVMETHOD(device_suspend, amdsbwd_suspend), 119 DEVMETHOD(device_resume, amdsbwd_resume), 120 #if 0 121 DEVMETHOD(device_shutdown, amdsbwd_detach), 122 #endif 123 DEVMETHOD_END 124 }; 125 126 static driver_t amdsbwd_driver = { 127 "amdsbwd", 128 amdsbwd_methods, 129 sizeof(struct amdsbwd_softc) 130 }; 131 132 DRIVER_MODULE(amdsbwd, isa, amdsbwd_driver, NULL, NULL); 133 134 static uint8_t 135 pmio_read(struct resource *res, uint8_t reg) 136 { 137 bus_write_1(res, 0, reg); /* Index */ 138 return (bus_read_1(res, 1)); /* Data */ 139 } 140 141 static void 142 pmio_write(struct resource *res, uint8_t reg, uint8_t val) 143 { 144 bus_write_1(res, 0, reg); /* Index */ 145 bus_write_1(res, 1, val); /* Data */ 146 } 147 148 static uint32_t 149 wdctrl_read(struct amdsbwd_softc *sc) 150 { 151 return (bus_read_4(sc->res_ctrl, 0)); 152 } 153 154 static void 155 wdctrl_write(struct amdsbwd_softc *sc, uint32_t val) 156 { 157 bus_write_4(sc->res_ctrl, 0, val); 158 } 159 160 static __unused uint32_t 161 wdcount_read(struct amdsbwd_softc *sc) 162 { 163 return (bus_read_4(sc->res_count, 0)); 164 } 165 166 static void 167 wdcount_write(struct amdsbwd_softc *sc, uint32_t val) 168 { 169 bus_write_4(sc->res_count, 0, val); 170 } 171 172 static void 173 amdsbwd_tmr_enable(struct amdsbwd_softc *sc) 174 { 175 uint32_t val; 176 177 val = wdctrl_read(sc); 178 val |= AMDSB_WD_RUN; 179 wdctrl_write(sc, val); 180 sc->active = 1; 181 amdsbwd_verbose_printf(sc->dev, "timer enabled\n"); 182 } 183 184 static void 185 amdsbwd_tmr_disable(struct amdsbwd_softc *sc) 186 { 187 uint32_t val; 188 189 val = wdctrl_read(sc); 190 val &= ~AMDSB_WD_RUN; 191 wdctrl_write(sc, val); 192 sc->active = 0; 193 amdsbwd_verbose_printf(sc->dev, "timer disabled\n"); 194 } 195 196 static void 197 amdsbwd_tmr_reload(struct amdsbwd_softc *sc) 198 { 199 uint32_t val; 200 201 val = wdctrl_read(sc); 202 val |= AMDSB_WD_RELOAD; 203 wdctrl_write(sc, val); 204 } 205 206 static void 207 amdsbwd_tmr_set(struct amdsbwd_softc *sc, uint16_t timeout) 208 { 209 210 timeout &= AMDSB_WD_COUNT_MASK; 211 wdcount_write(sc, timeout); 212 sc->timeout = timeout; 213 amdsbwd_verbose_printf(sc->dev, "timeout set to %u ticks\n", timeout); 214 } 215 216 static void 217 amdsbwd_event(void *arg, unsigned int cmd, int *error) 218 { 219 struct amdsbwd_softc *sc = arg; 220 uint64_t timeout; 221 222 if (cmd != 0) { 223 timeout = 0; 224 cmd &= WD_INTERVAL; 225 if (cmd >= WD_TO_1MS) { 226 timeout = (uint64_t)1 << (cmd - WD_TO_1MS); 227 timeout = timeout / sc->ms_per_tick; 228 } 229 /* For a too short timeout use 1 tick. */ 230 if (timeout == 0) 231 timeout = 1; 232 /* For a too long timeout stop the timer. */ 233 if (timeout > sc->max_ticks) 234 timeout = 0; 235 } else { 236 timeout = 0; 237 } 238 239 if (timeout != 0) { 240 if (timeout != sc->timeout) 241 amdsbwd_tmr_set(sc, timeout); 242 if (!sc->active) 243 amdsbwd_tmr_enable(sc); 244 amdsbwd_tmr_reload(sc); 245 *error = 0; 246 } else { 247 if (sc->active) 248 amdsbwd_tmr_disable(sc); 249 } 250 } 251 252 static void 253 amdsbwd_identify(driver_t *driver, device_t parent) 254 { 255 device_t child; 256 device_t smb_dev; 257 258 if (resource_disabled("amdsbwd", 0)) 259 return; 260 if (device_find_child(parent, "amdsbwd", -1) != NULL) 261 return; 262 263 /* 264 * Try to identify SB600/SB7xx by PCI Device ID of SMBus device 265 * that should be present at bus 0, device 20, function 0. 266 */ 267 smb_dev = pci_find_bsf(0, 20, 0); 268 if (smb_dev == NULL) 269 return; 270 if (pci_get_devid(smb_dev) != AMDSB_SMBUS_DEVID && 271 pci_get_devid(smb_dev) != AMDFCH_SMBUS_DEVID && 272 pci_get_devid(smb_dev) != AMDCZ_SMBUS_DEVID && 273 pci_get_devid(smb_dev) != HYGONCZ_SMBUS_DEVID) 274 return; 275 276 child = BUS_ADD_CHILD(parent, ISA_ORDER_SPECULATIVE, "amdsbwd", -1); 277 if (child == NULL) 278 device_printf(parent, "add amdsbwd child failed\n"); 279 } 280 281 static void 282 amdsbwd_probe_sb7xx(device_t dev, struct resource *pmres, uint32_t *addr) 283 { 284 uint8_t val; 285 int i; 286 287 /* Report cause of previous reset for user's convenience. */ 288 val = pmio_read(pmres, AMDSB_PM_RESET_STATUS0); 289 if (val != 0) 290 amdsbwd_verbose_printf(dev, "ResetStatus0 = %#04x\n", val); 291 val = pmio_read(pmres, AMDSB_PM_RESET_STATUS1); 292 if (val != 0) 293 amdsbwd_verbose_printf(dev, "ResetStatus1 = %#04x\n", val); 294 if ((val & AMDSB_WD_RST_STS) != 0) 295 device_printf(dev, "Previous Reset was caused by Watchdog\n"); 296 297 /* Find base address of memory mapped WDT registers. */ 298 for (*addr = 0, i = 0; i < 4; i++) { 299 *addr <<= 8; 300 *addr |= pmio_read(pmres, AMDSB_PM_WDT_BASE_MSB - i); 301 } 302 *addr &= ~0x07u; 303 304 /* Set watchdog timer tick to 1s. */ 305 val = pmio_read(pmres, AMDSB_PM_WDT_CTRL); 306 val &= ~AMDSB_WDT_RES_MASK; 307 val |= AMDSB_WDT_RES_1S; 308 pmio_write(pmres, AMDSB_PM_WDT_CTRL, val); 309 310 /* Enable watchdog device (in stopped state). */ 311 val = pmio_read(pmres, AMDSB_PM_WDT_CTRL); 312 val &= ~AMDSB_WDT_DISABLE; 313 pmio_write(pmres, AMDSB_PM_WDT_CTRL, val); 314 315 /* 316 * XXX TODO: Ensure that watchdog decode is enabled 317 * (register 0x41, bit 3). 318 */ 319 device_set_desc(dev, "AMD SB600/SB7xx Watchdog Timer"); 320 } 321 322 static void 323 amdsbwd_probe_sb8xx(device_t dev, struct resource *pmres, uint32_t *addr) 324 { 325 uint32_t val; 326 int i; 327 328 /* Report cause of previous reset for user's convenience. */ 329 330 val = pmio_read(pmres, AMDSB8_PM_RESET_CTRL); 331 if ((val & AMDSB8_RST_STS_DIS) != 0) { 332 val &= ~AMDSB8_RST_STS_DIS; 333 pmio_write(pmres, AMDSB8_PM_RESET_CTRL, val); 334 } 335 val = 0; 336 for (i = 3; i >= 0; i--) { 337 val <<= 8; 338 val |= pmio_read(pmres, AMDSB8_PM_RESET_STATUS + i); 339 } 340 if (val != 0) 341 amdsbwd_verbose_printf(dev, "ResetStatus = 0x%08x\n", val); 342 if ((val & AMDSB8_WD_RST_STS) != 0) 343 device_printf(dev, "Previous Reset was caused by Watchdog\n"); 344 345 /* Find base address of memory mapped WDT registers. */ 346 for (*addr = 0, i = 0; i < 4; i++) { 347 *addr <<= 8; 348 *addr |= pmio_read(pmres, AMDSB8_PM_WDT_EN + 3 - i); 349 } 350 *addr &= ~0x07u; 351 352 /* Set watchdog timer tick to 1s. */ 353 val = pmio_read(pmres, AMDSB8_PM_WDT_CTRL); 354 val &= ~AMDSB8_WDT_RES_MASK; 355 val |= AMDSB8_WDT_1HZ; 356 pmio_write(pmres, AMDSB8_PM_WDT_CTRL, val); 357 #ifdef AMDSBWD_DEBUG 358 val = pmio_read(pmres, AMDSB8_PM_WDT_CTRL); 359 amdsbwd_verbose_printf(dev, "AMDSB8_PM_WDT_CTRL value = %#04x\n", val); 360 #endif 361 362 /* 363 * Enable watchdog device (in stopped state) 364 * and decoding of its address. 365 */ 366 val = pmio_read(pmres, AMDSB8_PM_WDT_EN); 367 val &= ~AMDSB8_WDT_DISABLE; 368 val |= AMDSB8_WDT_DEC_EN; 369 pmio_write(pmres, AMDSB8_PM_WDT_EN, val); 370 #ifdef AMDSBWD_DEBUG 371 val = pmio_read(pmres, AMDSB8_PM_WDT_EN); 372 device_printf(dev, "AMDSB8_PM_WDT_EN value = %#04x\n", val); 373 #endif 374 device_set_desc(dev, "AMD SB8xx/SB9xx/Axx Watchdog Timer"); 375 } 376 377 static void 378 amdsbwd_probe_fch41(device_t dev, struct resource *pmres, uint32_t *addr) 379 { 380 uint8_t val; 381 char buf[36]; 382 383 /* 384 * Enable decoding of watchdog MMIO address. 385 */ 386 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN0); 387 val |= AMDFCH41_WDT_EN; 388 pmio_write(pmres, AMDFCH41_PM_DECODE_EN0, val); 389 #ifdef AMDSBWD_DEBUG 390 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN0); 391 device_printf(dev, "AMDFCH41_PM_DECODE_EN0 value = %#04x\n", val); 392 #endif 393 394 val = pmio_read(pmres, AMDFCH41_PM_ISA_CTRL); 395 if ((val & AMDFCH41_MMIO_EN) != 0) { 396 /* Fixed offset for the watchdog within ACPI MMIO range. */ 397 amdsbwd_verbose_printf(dev, "ACPI MMIO range is enabled\n"); 398 *addr = AMDFCH41_MMIO_ADDR + AMDFCH41_MMIO_WDT_OFF; 399 } else { 400 /* Special fixed MMIO range for the watchdog. */ 401 *addr = AMDFCH41_WDT_FIXED_ADDR; 402 } 403 404 /* 405 * Set watchdog timer tick to 1s and 406 * enable the watchdog device (in stopped state). 407 */ 408 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN3); 409 val &= ~AMDFCH41_WDT_RES_MASK; 410 val |= AMDFCH41_WDT_RES_1S; 411 val &= ~AMDFCH41_WDT_EN_MASK; 412 val |= AMDFCH41_WDT_ENABLE; 413 pmio_write(pmres, AMDFCH41_PM_DECODE_EN3, val); 414 #ifdef AMDSBWD_DEBUG 415 val = pmio_read(pmres, AMDFCH41_PM_DECODE_EN3); 416 amdsbwd_verbose_printf(dev, "AMDFCH41_PM_DECODE_EN3 value = %#04x\n", 417 val); 418 #endif 419 snprintf(buf, sizeof(buf), "%s FCH Rev 41h+ Watchdog Timer", 420 cpu_vendor_id == CPU_VENDOR_HYGON ? "Hygon" : "AMD"); 421 device_set_desc_copy(dev, buf); 422 } 423 424 static int 425 amdsbwd_probe(device_t dev) 426 { 427 struct resource *res; 428 device_t smb_dev; 429 uint32_t addr; 430 int rid; 431 int rc; 432 uint32_t devid; 433 uint8_t revid; 434 435 /* Do not claim some ISA PnP device by accident. */ 436 if (isa_get_logicalid(dev) != 0) 437 return (ENXIO); 438 439 rc = bus_set_resource(dev, SYS_RES_IOPORT, 0, AMDSB_PMIO_INDEX, 440 AMDSB_PMIO_WIDTH); 441 if (rc != 0) { 442 device_printf(dev, "bus_set_resource for IO failed\n"); 443 return (ENXIO); 444 } 445 rid = 0; 446 res = bus_alloc_resource_any(dev, SYS_RES_IOPORT, &rid, 447 RF_ACTIVE | RF_SHAREABLE); 448 if (res == NULL) { 449 device_printf(dev, "bus_alloc_resource for IO failed\n"); 450 return (ENXIO); 451 } 452 453 smb_dev = pci_find_bsf(0, 20, 0); 454 KASSERT(smb_dev != NULL, ("can't find SMBus PCI device\n")); 455 devid = pci_get_devid(smb_dev); 456 revid = pci_get_revid(smb_dev); 457 if (devid == AMDSB_SMBUS_DEVID && revid < AMDSB8_SMBUS_REVID) 458 amdsbwd_probe_sb7xx(dev, res, &addr); 459 else if (devid == AMDSB_SMBUS_DEVID || 460 (devid == AMDFCH_SMBUS_DEVID && revid < AMDFCH41_SMBUS_REVID) || 461 (devid == AMDCZ_SMBUS_DEVID && revid < AMDCZ49_SMBUS_REVID)) 462 amdsbwd_probe_sb8xx(dev, res, &addr); 463 else 464 amdsbwd_probe_fch41(dev, res, &addr); 465 466 bus_release_resource(dev, SYS_RES_IOPORT, rid, res); 467 bus_delete_resource(dev, SYS_RES_IOPORT, rid); 468 469 amdsbwd_verbose_printf(dev, "memory base address = %#010x\n", addr); 470 rc = bus_set_resource(dev, SYS_RES_MEMORY, 0, addr + AMDSB_WD_CTRL, 471 AMDSB_WDIO_REG_WIDTH); 472 if (rc != 0) { 473 device_printf(dev, "bus_set_resource for control failed\n"); 474 return (ENXIO); 475 } 476 rc = bus_set_resource(dev, SYS_RES_MEMORY, 1, addr + AMDSB_WD_COUNT, 477 AMDSB_WDIO_REG_WIDTH); 478 if (rc != 0) { 479 device_printf(dev, "bus_set_resource for count failed\n"); 480 return (ENXIO); 481 } 482 483 return (0); 484 } 485 486 static int 487 amdsbwd_attach_sb(device_t dev, struct amdsbwd_softc *sc) 488 { 489 490 sc->max_ticks = UINT16_MAX; 491 sc->rid_ctrl = 0; 492 sc->rid_count = 1; 493 494 sc->ms_per_tick = 1000; 495 496 sc->res_ctrl = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 497 &sc->rid_ctrl, RF_ACTIVE); 498 if (sc->res_ctrl == NULL) { 499 device_printf(dev, "bus_alloc_resource for ctrl failed\n"); 500 return (ENXIO); 501 } 502 sc->res_count = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 503 &sc->rid_count, RF_ACTIVE); 504 if (sc->res_count == NULL) { 505 device_printf(dev, "bus_alloc_resource for count failed\n"); 506 return (ENXIO); 507 } 508 return (0); 509 } 510 511 static int 512 amdsbwd_attach(device_t dev) 513 { 514 struct amdsbwd_softc *sc; 515 int rc; 516 517 sc = device_get_softc(dev); 518 sc->dev = dev; 519 520 rc = amdsbwd_attach_sb(dev, sc); 521 if (rc != 0) 522 goto fail; 523 524 #ifdef AMDSBWD_DEBUG 525 device_printf(dev, "wd ctrl = %#04x\n", wdctrl_read(sc)); 526 device_printf(dev, "wd count = %#04x\n", wdcount_read(sc)); 527 #endif 528 529 /* Setup initial state of Watchdog Control. */ 530 wdctrl_write(sc, AMDSB_WD_FIRED); 531 532 if (wdctrl_read(sc) & AMDSB_WD_DISABLE) { 533 device_printf(dev, "watchdog hardware is disabled\n"); 534 goto fail; 535 } 536 537 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, amdsbwd_event, sc, 538 EVENTHANDLER_PRI_ANY); 539 540 return (0); 541 542 fail: 543 amdsbwd_detach(dev); 544 return (ENXIO); 545 } 546 547 static int 548 amdsbwd_detach(device_t dev) 549 { 550 struct amdsbwd_softc *sc; 551 552 sc = device_get_softc(dev); 553 if (sc->ev_tag != NULL) 554 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag); 555 556 if (sc->active) 557 amdsbwd_tmr_disable(sc); 558 559 if (sc->res_ctrl != NULL) 560 bus_release_resource(dev, SYS_RES_MEMORY, sc->rid_ctrl, 561 sc->res_ctrl); 562 563 if (sc->res_count != NULL) 564 bus_release_resource(dev, SYS_RES_MEMORY, sc->rid_count, 565 sc->res_count); 566 567 return (0); 568 } 569 570 static int 571 amdsbwd_suspend(device_t dev) 572 { 573 struct amdsbwd_softc *sc; 574 uint32_t val; 575 576 sc = device_get_softc(dev); 577 val = wdctrl_read(sc); 578 val &= ~AMDSB_WD_RUN; 579 wdctrl_write(sc, val); 580 return (0); 581 } 582 583 static int 584 amdsbwd_resume(device_t dev) 585 { 586 struct amdsbwd_softc *sc; 587 588 sc = device_get_softc(dev); 589 wdctrl_write(sc, AMDSB_WD_FIRED); 590 if (sc->active) { 591 amdsbwd_tmr_set(sc, sc->timeout); 592 amdsbwd_tmr_enable(sc); 593 amdsbwd_tmr_reload(sc); 594 } 595 return (0); 596 } 597