1 /*- 2 * Copyright (c) 2009 Andriy Gapon <avg@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27 /* 28 * This is a driver for watchdog timer present in AMD SB600/SB7xx/SB8xx 29 * southbridges. 30 * Please see the following specifications for the descriptions of the 31 * registers and flags: 32 * - AMD SB600 Register Reference Guide, Public Version, Rev. 3.03 (SB600 RRG) 33 * http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/46155_sb600_rrg_pub_3.03.pdf 34 * - AMD SB700/710/750 Register Reference Guide (RRG) 35 * http://developer.amd.com/assets/43009_sb7xx_rrg_pub_1.00.pdf 36 * - AMD SB700/710/750 Register Programming Requirements (RPR) 37 * http://developer.amd.com/assets/42413_sb7xx_rpr_pub_1.00.pdf 38 * - AMD SB800-Series Southbridges Register Reference Guide (RRG) 39 * http://support.amd.com/us/Embedded_TechDocs/45482.pdf 40 * Please see the following for Watchdog Resource Table specification: 41 * - Watchdog Timer Hardware Requirements for Windows Server 2003 (WDRT) 42 * http://www.microsoft.com/whdc/system/sysinternals/watchdog.mspx 43 * AMD SB600/SB7xx/SB8xx watchdog hardware seems to conform to the above 44 * specifications, but the table hasn't been spotted in the wild yet. 45 */ 46 47 #include <sys/cdefs.h> 48 __FBSDID("$FreeBSD$"); 49 50 #include <sys/param.h> 51 #include <sys/kernel.h> 52 #include <sys/module.h> 53 #include <sys/systm.h> 54 #include <sys/sysctl.h> 55 #include <sys/bus.h> 56 #include <machine/bus.h> 57 #include <sys/rman.h> 58 #include <machine/resource.h> 59 #include <sys/watchdog.h> 60 61 #include <dev/pci/pcivar.h> 62 #include <isa/isavar.h> 63 64 /* SB7xx RRG 2.3.3.1.1. */ 65 #define AMDSB_PMIO_INDEX 0xcd6 66 #define AMDSB_PMIO_DATA (PMIO_INDEX + 1) 67 #define AMDSB_PMIO_WIDTH 2 68 /* SB7xx RRG 2.3.3.2. */ 69 #define AMDSB_PM_RESET_STATUS0 0x44 70 #define AMDSB_PM_RESET_STATUS1 0x45 71 #define AMDSB_WD_RST_STS 0x02 72 /* SB7xx RRG 2.3.3.2, RPR 2.36. */ 73 #define AMDSB_PM_WDT_CTRL 0x69 74 #define AMDSB_WDT_DISABLE 0x01 75 #define AMDSB_WDT_RES_MASK (0x02 | 0x04) 76 #define AMDSB_WDT_RES_32US 0x00 77 #define AMDSB_WDT_RES_10MS 0x02 78 #define AMDSB_WDT_RES_100MS 0x04 79 #define AMDSB_WDT_RES_1S 0x06 80 #define AMDSB_PM_WDT_BASE_LSB 0x6c 81 #define AMDSB_PM_WDT_BASE_MSB 0x6f 82 /* SB8xx RRG 2.3.3. */ 83 #define AMDSB8_PM_WDT_EN 0x48 84 #define AMDSB8_WDT_DEC_EN 0x01 85 #define AMDSB8_WDT_DISABLE 0x02 86 #define AMDSB8_PM_WDT_CTRL 0x4c 87 #define AMDSB8_WDT_32KHZ 0x00 88 #define AMDSB8_WDT_1HZ 0x03 89 #define AMDSB8_WDT_RES_MASK 0x03 90 #define AMDSB8_PM_RESET_STATUS0 0xC0 91 #define AMDSB8_PM_RESET_STATUS1 0xC1 92 #define AMDSB8_WD_RST_STS 0x20 93 /* SB7xx RRG 2.3.4, WDRT. */ 94 #define AMDSB_WD_CTRL 0x00 95 #define AMDSB_WD_RUN 0x01 96 #define AMDSB_WD_FIRED 0x02 97 #define AMDSB_WD_SHUTDOWN 0x04 98 #define AMDSB_WD_DISABLE 0x08 99 #define AMDSB_WD_RESERVED 0x70 100 #define AMDSB_WD_RELOAD 0x80 101 #define AMDSB_WD_COUNT 0x04 102 #define AMDSB_WD_COUNT_MASK 0xffff 103 #define AMDSB_WDIO_REG_WIDTH 4 104 /* WDRT */ 105 #define MAXCOUNT_MIN_VALUE 511 106 /* SB7xx RRG 2.3.1.1, SB600 RRG 2.3.1.1, SB8xx RRG 2.3.1. */ 107 #define AMDSB_SMBUS_DEVID 0x43851002 108 #define AMDSB8_SMBUS_REVID 0x40 109 110 #define amdsbwd_verbose_printf(dev, ...) \ 111 do { \ 112 if (bootverbose) \ 113 device_printf(dev, __VA_ARGS__);\ 114 } while (0) 115 116 struct amdsbwd_softc { 117 device_t dev; 118 eventhandler_tag ev_tag; 119 struct resource *res_ctrl; 120 struct resource *res_count; 121 int rid_ctrl; 122 int rid_count; 123 int ms_per_tick; 124 int max_ticks; 125 int active; 126 unsigned int timeout; 127 }; 128 129 static void amdsbwd_identify(driver_t *driver, device_t parent); 130 static int amdsbwd_probe(device_t dev); 131 static int amdsbwd_attach(device_t dev); 132 static int amdsbwd_detach(device_t dev); 133 134 static device_method_t amdsbwd_methods[] = { 135 DEVMETHOD(device_identify, amdsbwd_identify), 136 DEVMETHOD(device_probe, amdsbwd_probe), 137 DEVMETHOD(device_attach, amdsbwd_attach), 138 DEVMETHOD(device_detach, amdsbwd_detach), 139 #if 0 140 DEVMETHOD(device_shutdown, amdsbwd_detach), 141 #endif 142 DEVMETHOD_END 143 }; 144 145 static devclass_t amdsbwd_devclass; 146 static driver_t amdsbwd_driver = { 147 "amdsbwd", 148 amdsbwd_methods, 149 sizeof(struct amdsbwd_softc) 150 }; 151 152 DRIVER_MODULE(amdsbwd, isa, amdsbwd_driver, amdsbwd_devclass, NULL, NULL); 153 154 155 static uint8_t 156 pmio_read(struct resource *res, uint8_t reg) 157 { 158 bus_write_1(res, 0, reg); /* Index */ 159 return (bus_read_1(res, 1)); /* Data */ 160 } 161 162 static void 163 pmio_write(struct resource *res, uint8_t reg, uint8_t val) 164 { 165 bus_write_1(res, 0, reg); /* Index */ 166 bus_write_1(res, 1, val); /* Data */ 167 } 168 169 static uint32_t 170 wdctrl_read(struct amdsbwd_softc *sc) 171 { 172 return (bus_read_4(sc->res_ctrl, 0)); 173 } 174 175 static void 176 wdctrl_write(struct amdsbwd_softc *sc, uint32_t val) 177 { 178 bus_write_4(sc->res_ctrl, 0, val); 179 } 180 181 static __unused uint32_t 182 wdcount_read(struct amdsbwd_softc *sc) 183 { 184 return (bus_read_4(sc->res_count, 0)); 185 } 186 187 static void 188 wdcount_write(struct amdsbwd_softc *sc, uint32_t val) 189 { 190 bus_write_4(sc->res_count, 0, val); 191 } 192 193 static void 194 amdsbwd_tmr_enable(struct amdsbwd_softc *sc) 195 { 196 uint32_t val; 197 198 val = wdctrl_read(sc); 199 val |= AMDSB_WD_RUN; 200 wdctrl_write(sc, val); 201 sc->active = 1; 202 amdsbwd_verbose_printf(sc->dev, "timer enabled\n"); 203 } 204 205 static void 206 amdsbwd_tmr_disable(struct amdsbwd_softc *sc) 207 { 208 uint32_t val; 209 210 val = wdctrl_read(sc); 211 val &= ~AMDSB_WD_RUN; 212 wdctrl_write(sc, val); 213 sc->active = 0; 214 amdsbwd_verbose_printf(sc->dev, "timer disabled\n"); 215 } 216 217 static void 218 amdsbwd_tmr_reload(struct amdsbwd_softc *sc) 219 { 220 uint32_t val; 221 222 val = wdctrl_read(sc); 223 val |= AMDSB_WD_RELOAD; 224 wdctrl_write(sc, val); 225 } 226 227 static void 228 amdsbwd_tmr_set(struct amdsbwd_softc *sc, uint16_t timeout) 229 { 230 231 timeout &= AMDSB_WD_COUNT_MASK; 232 wdcount_write(sc, timeout); 233 sc->timeout = timeout; 234 amdsbwd_verbose_printf(sc->dev, "timeout set to %u ticks\n", timeout); 235 } 236 237 static void 238 amdsbwd_event(void *arg, unsigned int cmd, int *error) 239 { 240 struct amdsbwd_softc *sc = arg; 241 unsigned int timeout; 242 243 /* convert from power-of-two-ns to WDT ticks */ 244 cmd &= WD_INTERVAL; 245 if (cmd < WD_TO_1SEC) 246 cmd = 0; 247 if (cmd) { 248 timeout = ((uint64_t)1 << (cmd - WD_TO_1MS)) / sc->ms_per_tick; 249 if (timeout > sc->max_ticks) 250 timeout = sc->max_ticks; 251 if (timeout != sc->timeout) { 252 amdsbwd_tmr_set(sc, timeout); 253 if (!sc->active) 254 amdsbwd_tmr_enable(sc); 255 } 256 amdsbwd_tmr_reload(sc); 257 *error = 0; 258 } else { 259 if (sc->active) 260 amdsbwd_tmr_disable(sc); 261 } 262 } 263 264 static void 265 amdsbwd_identify(driver_t *driver, device_t parent) 266 { 267 device_t child; 268 device_t smb_dev; 269 270 if (resource_disabled("amdsbwd", 0)) 271 return; 272 if (device_find_child(parent, "amdsbwd", -1) != NULL) 273 return; 274 275 /* 276 * Try to identify SB600/SB7xx by PCI Device ID of SMBus device 277 * that should be present at bus 0, device 20, function 0. 278 */ 279 smb_dev = pci_find_bsf(0, 20, 0); 280 if (smb_dev == NULL) 281 return; 282 if (pci_get_devid(smb_dev) != AMDSB_SMBUS_DEVID) 283 return; 284 285 child = BUS_ADD_CHILD(parent, ISA_ORDER_SPECULATIVE, "amdsbwd", -1); 286 if (child == NULL) 287 device_printf(parent, "add amdsbwd child failed\n"); 288 } 289 290 291 static void 292 amdsbwd_probe_sb7xx(device_t dev, struct resource *pmres, uint32_t *addr) 293 { 294 uint32_t val; 295 int i; 296 297 /* Report cause of previous reset for user's convenience. */ 298 val = pmio_read(pmres, AMDSB_PM_RESET_STATUS0); 299 if (val != 0) 300 amdsbwd_verbose_printf(dev, "ResetStatus0 = %#04x\n", val); 301 val = pmio_read(pmres, AMDSB_PM_RESET_STATUS1); 302 if (val != 0) 303 amdsbwd_verbose_printf(dev, "ResetStatus1 = %#04x\n", val); 304 if ((val & AMDSB_WD_RST_STS) != 0) 305 device_printf(dev, "Previous Reset was caused by Watchdog\n"); 306 307 /* Find base address of memory mapped WDT registers. */ 308 for (*addr = 0, i = 0; i < 4; i++) { 309 *addr <<= 8; 310 *addr |= pmio_read(pmres, AMDSB_PM_WDT_BASE_MSB - i); 311 } 312 /* Set watchdog timer tick to 1s. */ 313 val = pmio_read(pmres, AMDSB_PM_WDT_CTRL); 314 val &= ~AMDSB_WDT_RES_MASK; 315 val |= AMDSB_WDT_RES_10MS; 316 pmio_write(pmres, AMDSB_PM_WDT_CTRL, val); 317 318 /* Enable watchdog device (in stopped state). */ 319 val = pmio_read(pmres, AMDSB_PM_WDT_CTRL); 320 val &= ~AMDSB_WDT_DISABLE; 321 pmio_write(pmres, AMDSB_PM_WDT_CTRL, val); 322 323 /* 324 * XXX TODO: Ensure that watchdog decode is enabled 325 * (register 0x41, bit 3). 326 */ 327 device_set_desc(dev, "AMD SB600/SB7xx Watchdog Timer"); 328 } 329 330 static void 331 amdsbwd_probe_sb8xx(device_t dev, struct resource *pmres, uint32_t *addr) 332 { 333 uint32_t val; 334 int i; 335 336 /* Report cause of previous reset for user's convenience. */ 337 val = pmio_read(pmres, AMDSB8_PM_RESET_STATUS0); 338 if (val != 0) 339 amdsbwd_verbose_printf(dev, "ResetStatus0 = %#04x\n", val); 340 val = pmio_read(pmres, AMDSB8_PM_RESET_STATUS1); 341 if (val != 0) 342 amdsbwd_verbose_printf(dev, "ResetStatus1 = %#04x\n", val); 343 if ((val & AMDSB8_WD_RST_STS) != 0) 344 device_printf(dev, "Previous Reset was caused by Watchdog\n"); 345 346 /* Find base address of memory mapped WDT registers. */ 347 for (*addr = 0, i = 0; i < 4; i++) { 348 *addr <<= 8; 349 *addr |= pmio_read(pmres, AMDSB8_PM_WDT_EN + 3 - i); 350 } 351 *addr &= ~0x07u; 352 353 /* Set watchdog timer tick to 1s. */ 354 val = pmio_read(pmres, AMDSB8_PM_WDT_CTRL); 355 val &= ~AMDSB8_WDT_RES_MASK; 356 val |= AMDSB8_WDT_1HZ; 357 pmio_write(pmres, AMDSB8_PM_WDT_CTRL, val); 358 #ifdef AMDSBWD_DEBUG 359 val = pmio_read(pmres, AMDSB8_PM_WDT_CTRL); 360 amdsbwd_verbose_printf(dev, "AMDSB8_PM_WDT_CTRL value = %#02x\n", val); 361 #endif 362 363 /* 364 * Enable watchdog device (in stopped state) 365 * and decoding of its address. 366 */ 367 val = pmio_read(pmres, AMDSB8_PM_WDT_EN); 368 val &= ~AMDSB8_WDT_DISABLE; 369 val |= AMDSB8_WDT_DEC_EN; 370 pmio_write(pmres, AMDSB8_PM_WDT_EN, val); 371 #ifdef AMDSBWD_DEBUG 372 val = pmio_read(pmres, AMDSB8_PM_WDT_EN); 373 device_printf(dev, "AMDSB8_PM_WDT_EN value = %#02x\n", val); 374 #endif 375 device_set_desc(dev, "AMD SB8xx Watchdog Timer"); 376 } 377 378 static int 379 amdsbwd_probe(device_t dev) 380 { 381 struct resource *res; 382 device_t smb_dev; 383 uint32_t addr; 384 int rid; 385 int rc; 386 387 /* Do not claim some ISA PnP device by accident. */ 388 if (isa_get_logicalid(dev) != 0) 389 return (ENXIO); 390 391 rc = bus_set_resource(dev, SYS_RES_IOPORT, 0, AMDSB_PMIO_INDEX, 392 AMDSB_PMIO_WIDTH); 393 if (rc != 0) { 394 device_printf(dev, "bus_set_resource for IO failed\n"); 395 return (ENXIO); 396 } 397 rid = 0; 398 res = bus_alloc_resource(dev, SYS_RES_IOPORT, &rid, 0ul, ~0ul, 399 AMDSB_PMIO_WIDTH, RF_ACTIVE | RF_SHAREABLE); 400 if (res == NULL) { 401 device_printf(dev, "bus_alloc_resource for IO failed\n"); 402 return (ENXIO); 403 } 404 405 smb_dev = pci_find_bsf(0, 20, 0); 406 KASSERT(smb_dev != NULL, ("can't find SMBus PCI device\n")); 407 if (pci_get_revid(smb_dev) < AMDSB8_SMBUS_REVID) 408 amdsbwd_probe_sb7xx(dev, res, &addr); 409 else 410 amdsbwd_probe_sb8xx(dev, res, &addr); 411 412 bus_release_resource(dev, SYS_RES_IOPORT, rid, res); 413 bus_delete_resource(dev, SYS_RES_IOPORT, rid); 414 415 amdsbwd_verbose_printf(dev, "memory base address = %#010x\n", addr); 416 rc = bus_set_resource(dev, SYS_RES_MEMORY, 0, addr + AMDSB_WD_CTRL, 417 AMDSB_WDIO_REG_WIDTH); 418 if (rc != 0) { 419 device_printf(dev, "bus_set_resource for control failed\n"); 420 return (ENXIO); 421 } 422 rc = bus_set_resource(dev, SYS_RES_MEMORY, 1, addr + AMDSB_WD_COUNT, 423 AMDSB_WDIO_REG_WIDTH); 424 if (rc != 0) { 425 device_printf(dev, "bus_set_resource for count failed\n"); 426 return (ENXIO); 427 } 428 429 return (0); 430 } 431 432 static int 433 amdsbwd_attach_sb(device_t dev, struct amdsbwd_softc *sc) 434 { 435 device_t smb_dev; 436 437 sc->max_ticks = UINT16_MAX; 438 sc->rid_ctrl = 0; 439 sc->rid_count = 1; 440 441 smb_dev = pci_find_bsf(0, 20, 0); 442 KASSERT(smb_dev != NULL, ("can't find SMBus PCI device\n")); 443 if (pci_get_revid(smb_dev) < AMDSB8_SMBUS_REVID) 444 sc->ms_per_tick = 10; 445 else 446 sc->ms_per_tick = 1000; 447 448 sc->res_ctrl = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 449 &sc->rid_ctrl, RF_ACTIVE); 450 if (sc->res_ctrl == NULL) { 451 device_printf(dev, "bus_alloc_resource for ctrl failed\n"); 452 return (ENXIO); 453 } 454 sc->res_count = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 455 &sc->rid_count, RF_ACTIVE); 456 if (sc->res_count == NULL) { 457 device_printf(dev, "bus_alloc_resource for count failed\n"); 458 return (ENXIO); 459 } 460 return (0); 461 } 462 463 static int 464 amdsbwd_attach(device_t dev) 465 { 466 struct amdsbwd_softc *sc; 467 int rc; 468 469 sc = device_get_softc(dev); 470 sc->dev = dev; 471 472 rc = amdsbwd_attach_sb(dev, sc); 473 if (rc != 0) 474 goto fail; 475 476 #ifdef AMDSBWD_DEBUG 477 device_printf(dev, "wd ctrl = %#04x\n", wdctrl_read(sc)); 478 device_printf(dev, "wd count = %#04x\n", wdcount_read(sc)); 479 #endif 480 481 /* Setup initial state of Watchdog Control. */ 482 wdctrl_write(sc, AMDSB_WD_FIRED); 483 484 if (wdctrl_read(sc) & AMDSB_WD_DISABLE) { 485 device_printf(dev, "watchdog hardware is disabled\n"); 486 goto fail; 487 } 488 489 sc->ev_tag = EVENTHANDLER_REGISTER(watchdog_list, amdsbwd_event, sc, 490 EVENTHANDLER_PRI_ANY); 491 492 return (0); 493 494 fail: 495 amdsbwd_detach(dev); 496 return (ENXIO); 497 } 498 499 static int 500 amdsbwd_detach(device_t dev) 501 { 502 struct amdsbwd_softc *sc; 503 504 sc = device_get_softc(dev); 505 if (sc->ev_tag != NULL) 506 EVENTHANDLER_DEREGISTER(watchdog_list, sc->ev_tag); 507 508 if (sc->active) 509 amdsbwd_tmr_disable(sc); 510 511 if (sc->res_ctrl != NULL) 512 bus_release_resource(dev, SYS_RES_MEMORY, sc->rid_ctrl, 513 sc->res_ctrl); 514 515 if (sc->res_count != NULL) 516 bus_release_resource(dev, SYS_RES_MEMORY, sc->rid_count, 517 sc->res_count); 518 519 return (0); 520 } 521 522