1 /*- 2 * Copyright (c) 2016 Andriy Gapon <avg@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29 /* 30 * The following registers, bits and magic values are defined in Register 31 * Reference Guide documents for SB600, SB7x0, SB8x0, SB9x0 southbridges and 32 * various versions of Fusion Controller Hubs (FCHs). FCHs integrated into 33 * CPUs are documented in BIOS and Kernel Development Guide documents for 34 * the corresponding processor families. 35 * 36 * At present there are three classes of supported chipsets: 37 * - SB600 and S7x0 southbridges where the SMBus controller device has 38 * a PCI Device ID of 0x43851002 and a revision less than 0x40 39 * - SB8x0, SB9x0 southbridges and FCHs where the SMBus controller device has 40 * a PCI Device ID of 0x43851002 and a revision greater than or equal to 0x40 41 * or the controller has an ID of 0x780b1022 and a revision less than 0x41 42 * - FCHs where the SMBus controller device has a PCI Device ID of 0x780b1022 43 * and a revision greater than or equal to 0x41 44 * The register definitions are compatible within the classes and may be 45 * incompatible accross them. 46 * So far there is no public documentation for "KERNCZ" FCH where the SMBus 47 * controller has a PCI ID of 0x790b1022. Based on some code in Linux it is 48 * assumed that revisions less than 0x49 are compatible with the SB8x0 class 49 * and revisions greater than or equal to 0x49 are compatible with the class 50 * of FCHs with 0x41+ revisions. 51 */ 52 53 /* 54 * IO registers for accessing the PMIO space. 55 * See SB7xx RRG 2.3.3.1.1, for instance. 56 */ 57 #define AMDSB_PMIO_INDEX 0xcd6 58 #define AMDSB_PMIO_DATA (PMIO_INDEX + 1) 59 #define AMDSB_PMIO_WIDTH 2 60 61 /* 62 * SB7x0 and compatible registers in the PMIO space. 63 * See SB7xx RRG 2.3.3.2. 64 */ 65 #define AMDSB_PM_RESET_STATUS0 0x44 66 #define AMDSB_PM_RESET_STATUS1 0x45 67 #define AMDSB_WD_RST_STS 0x02 68 #define AMDSB_PM_WDT_CTRL 0x69 69 #define AMDSB_WDT_DISABLE 0x01 70 #define AMDSB_WDT_RES_MASK (0x02 | 0x04) 71 #define AMDSB_WDT_RES_32US 0x00 72 #define AMDSB_WDT_RES_10MS 0x02 73 #define AMDSB_WDT_RES_100MS 0x04 74 #define AMDSB_WDT_RES_1S 0x06 75 #define AMDSB_PM_WDT_BASE_LSB 0x6c 76 #define AMDSB_PM_WDT_BASE_MSB 0x6f 77 78 /* 79 * SB8x0 and compatible registers in the PMIO space. 80 * See SB8xx RRG 2.3.3, for instance. 81 */ 82 #define AMDSB8_PM_SMBUS_EN 0x2c 83 #define AMDSB8_SMBUS_EN 0x01 84 #define AMDSB8_SMBUS_ADDR_MASK 0xffe0u 85 #define AMDSB8_PM_WDT_EN 0x48 86 #define AMDSB8_WDT_DEC_EN 0x01 87 #define AMDSB8_WDT_DISABLE 0x02 88 #define AMDSB8_PM_WDT_CTRL 0x4c 89 #define AMDSB8_WDT_32KHZ 0x00 90 #define AMDSB8_WDT_1HZ 0x03 91 #define AMDSB8_WDT_RES_MASK 0x03 92 #define AMDSB8_PM_RESET_STATUS0 0xc0 93 #define AMDSB8_PM_RESET_STATUS1 0xc1 94 #define AMDSB8_WD_RST_STS 0x20 95 96 /* 97 * Newer FCH registers in the PMIO space. 98 * See BKDG for Family 16h Models 30h-3Fh 3.26.13 PMx00 and PMx04. 99 */ 100 #define AMDFCH41_PM_DECODE_EN0 0x00 101 #define AMDFCH41_SMBUS_EN 0x10 102 #define AMDFCH41_WDT_EN 0x80 103 #define AMDFCH41_PM_DECODE_EN1 0x01 104 #define AMDFCH41_PM_DECODE_EN3 0x03 105 #define AMDFCH41_WDT_RES_MASK 0x03 106 #define AMDFCH41_WDT_RES_32US 0x00 107 #define AMDFCH41_WDT_RES_10MS 0x01 108 #define AMDFCH41_WDT_RES_100MS 0x02 109 #define AMDFCH41_WDT_RES_1S 0x03 110 #define AMDFCH41_WDT_EN_MASK 0x0c 111 #define AMDFCH41_WDT_ENABLE 0x00 112 #define AMDFCH41_PM_ISA_CTRL 0x04 113 #define AMDFCH41_MMIO_EN 0x02 114 115 /* 116 * Fixed MMIO addresses for accessing Watchdog and SMBus registers. 117 * See BKDG for Family 16h Models 30h-3Fh 3.26.13 PMx00 and PMx04. 118 */ 119 #define AMDFCH41_WDT_FIXED_ADDR 0xfeb00000u 120 #define AMDFCH41_MMIO_ADDR 0xfed80000u 121 #define AMDFCH41_MMIO_SMBUS_OFF 0x0a00 122 #define AMDFCH41_MMIO_WDT_OFF 0x0b00 123 124 /* 125 * PCI Device IDs and revisions. 126 * SB600 RRG 2.3.1.1, 127 * SB7xx RRG 2.3.1.1, 128 * SB8xx RRG 2.3.1, 129 * BKDG for Family 16h Models 00h-0Fh 3.26.7.1, 130 * BKDG for Family 16h Models 30h-3Fh 3.26.7.1. 131 * Also, see i2c-piix4 aka piix4_smbus Linux driver. 132 */ 133 #define AMDSB_SMBUS_DEVID 0x43851002 134 #define AMDSB8_SMBUS_REVID 0x40 135 #define AMDFCH_SMBUS_DEVID 0x780b1022 136 #define AMDFCH41_SMBUS_REVID 0x41 137 #define AMDCZ_SMBUS_DEVID 0x790b1022 138 #define AMDCZ49_SMBUS_REVID 0x49 139 140