1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 3 * 4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 * 29 * $FreeBSD$ 30 */ 31 32 #ifndef _IF_ALEREG_H 33 #define _IF_ALEREG_H 34 35 /* 36 * Atheros Communucations, Inc. PCI vendor ID 37 */ 38 #define VENDORID_ATHEROS 0x1969 39 40 /* 41 * Atheros AR8121/AR8113/AR8114 device ID 42 */ 43 #define DEVICEID_ATHEROS_AR81XX 0x1026 44 45 #define ALE_SPI_CTRL 0x200 46 #define SPI_VPD_ENB 0x00002000 47 48 #define ALE_SPI_ADDR 0x204 /* 16bits */ 49 50 #define ALE_SPI_DATA 0x208 51 52 #define ALE_SPI_CONFIG 0x20C 53 54 #define ALE_SPI_OP_PROGRAM 0x210 /* 8bits */ 55 56 #define ALE_SPI_OP_SC_ERASE 0x211 /* 8bits */ 57 58 #define ALE_SPI_OP_CHIP_ERASE 0x212 /* 8bits */ 59 60 #define ALE_SPI_OP_RDID 0x213 /* 8bits */ 61 62 #define ALE_SPI_OP_WREN 0x214 /* 8bits */ 63 64 #define ALE_SPI_OP_RDSR 0x215 /* 8bits */ 65 66 #define ALE_SPI_OP_WRSR 0x216 /* 8bits */ 67 68 #define ALE_SPI_OP_READ 0x217 /* 8bits */ 69 70 #define ALE_TWSI_CTRL 0x218 71 #define TWSI_CTRL_SW_LD_START 0x00000800 72 #define TWSI_CTRL_HW_LD_START 0x00001000 73 #define TWSI_CTRL_LD_EXIST 0x00400000 74 75 #define ALE_DEV_MISC_CTRL 0x21C 76 77 #define ALE_PCIE_PHYMISC 0x1000 78 #define PCIE_PHYMISC_FORCE_RCV_DET 0x00000004 79 80 #define ALE_MASTER_CFG 0x1400 81 #define MASTER_RESET 0x00000001 82 #define MASTER_MTIMER_ENB 0x00000002 83 #define MASTER_IM_TX_TIMER_ENB 0x00000004 84 #define MASTER_MANUAL_INT_ENB 0x00000008 85 #define MASTER_IM_RX_TIMER_ENB 0x00000020 86 #define MASTER_INT_RDCLR 0x00000040 87 #define MASTER_LED_MODE 0x00000200 88 #define MASTER_CHIP_REV_MASK 0x00FF0000 89 #define MASTER_CHIP_ID_MASK 0xFF000000 90 #define MASTER_CHIP_REV_SHIFT 16 91 #define MASTER_CHIP_ID_SHIFT 24 92 93 /* Number of ticks per usec for AR81xx. */ 94 #define ALE_TICK_USECS 2 95 #define ALE_USECS(x) ((x) / ALE_TICK_USECS) 96 97 #define ALE_MANUAL_TIMER 0x1404 98 99 #define ALE_IM_TIMER 0x1408 100 #define IM_TIMER_TX_MASK 0x0000FFFF 101 #define IM_TIMER_RX_MASK 0xFFFF0000 102 #define IM_TIMER_TX_SHIFT 0 103 #define IM_TIMER_RX_SHIFT 16 104 #define ALE_IM_TIMER_MIN 0 105 #define ALE_IM_TIMER_MAX 130000 /* 130ms */ 106 #define ALE_IM_RX_TIMER_DEFAULT 30 107 #define ALE_IM_TX_TIMER_DEFAULT 1000 108 109 #define ALE_GPHY_CTRL 0x140C /* 16bits */ 110 #define GPHY_CTRL_EXT_RESET 0x0001 111 #define GPHY_CTRL_PIPE_MOD 0x0002 112 #define GPHY_CTRL_BERT_START 0x0010 113 #define GPHY_CTRL_GALE_25M_ENB 0x0020 114 #define GPHY_CTRL_LPW_EXIT 0x0040 115 #define GPHY_CTRL_PHY_IDDQ 0x0080 116 #define GPHY_CTRL_PHY_IDDQ_DIS 0x0100 117 #define GPHY_CTRL_PCLK_SEL_DIS 0x0200 118 #define GPHY_CTRL_HIB_EN 0x0400 119 #define GPHY_CTRL_HIB_PULSE 0x0800 120 #define GPHY_CTRL_SEL_ANA_RESET 0x1000 121 #define GPHY_CTRL_PHY_PLL_ON 0x2000 122 #define GPHY_CTRL_PWDOWN_HW 0x4000 123 124 #define ALE_INTR_CLR_TIMER 0x140E /* 16bits */ 125 126 #define ALE_IDLE_STATUS 0x1410 127 #define IDLE_STATUS_RXMAC 0x00000001 128 #define IDLE_STATUS_TXMAC 0x00000002 129 #define IDLE_STATUS_RXQ 0x00000004 130 #define IDLE_STATUS_TXQ 0x00000008 131 #define IDLE_STATUS_DMARD 0x00000010 132 #define IDLE_STATUS_DMAWR 0x00000020 133 #define IDLE_STATUS_SMB 0x00000040 134 #define IDLE_STATUS_CMB 0x00000080 135 136 #define ALE_MDIO 0x1414 137 #define MDIO_DATA_MASK 0x0000FFFF 138 #define MDIO_REG_ADDR_MASK 0x001F0000 139 #define MDIO_OP_READ 0x00200000 140 #define MDIO_OP_WRITE 0x00000000 141 #define MDIO_SUP_PREAMBLE 0x00400000 142 #define MDIO_OP_EXECUTE 0x00800000 143 #define MDIO_CLK_25_4 0x00000000 144 #define MDIO_CLK_25_6 0x02000000 145 #define MDIO_CLK_25_8 0x03000000 146 #define MDIO_CLK_25_10 0x04000000 147 #define MDIO_CLK_25_14 0x05000000 148 #define MDIO_CLK_25_20 0x06000000 149 #define MDIO_CLK_25_28 0x07000000 150 #define MDIO_OP_BUSY 0x08000000 151 #define MDIO_DATA_SHIFT 0 152 #define MDIO_REG_ADDR_SHIFT 16 153 154 #define MDIO_REG_ADDR(x) \ 155 (((x) << MDIO_REG_ADDR_SHIFT) & MDIO_REG_ADDR_MASK) 156 /* Default PHY address. */ 157 #define ALE_PHY_ADDR 0 158 159 #define ALE_PHY_STATUS 0x1418 160 #define PHY_STATUS_100M 0x00020000 161 162 /* Packet memory BIST. */ 163 #define ALE_BIST0 0x141C 164 #define BIST0_ENB 0x00000001 165 #define BIST0_SRAM_FAIL 0x00000002 166 #define BIST0_FUSE_FLAG 0x00000004 167 168 /* PCIe retry buffer BIST. */ 169 #define ALE_BIST1 0x1420 170 #define BIST1_ENB 0x00000001 171 #define BIST1_SRAM_FAIL 0x00000002 172 #define BIST1_FUSE_FLAG 0x00000004 173 174 #define ALE_SERDES_LOCK 0x1424 175 #define SERDES_LOCK_DET 0x00000001 176 #define SERDES_LOCK_DET_ENB 0x00000002 177 178 #define ALE_MAC_CFG 0x1480 179 #define MAC_CFG_TX_ENB 0x00000001 180 #define MAC_CFG_RX_ENB 0x00000002 181 #define MAC_CFG_TX_FC 0x00000004 182 #define MAC_CFG_RX_FC 0x00000008 183 #define MAC_CFG_LOOP 0x00000010 184 #define MAC_CFG_FULL_DUPLEX 0x00000020 185 #define MAC_CFG_TX_CRC_ENB 0x00000040 186 #define MAC_CFG_TX_AUTO_PAD 0x00000080 187 #define MAC_CFG_TX_LENCHK 0x00000100 188 #define MAC_CFG_RX_JUMBO_ENB 0x00000200 189 #define MAC_CFG_PREAMBLE_MASK 0x00003C00 190 #define MAC_CFG_VLAN_TAG_STRIP 0x00004000 191 #define MAC_CFG_PROMISC 0x00008000 192 #define MAC_CFG_TX_PAUSE 0x00010000 193 #define MAC_CFG_SCNT 0x00020000 194 #define MAC_CFG_SYNC_RST_TX 0x00040000 195 #define MAC_CFG_SPEED_MASK 0x00300000 196 #define MAC_CFG_SPEED_10_100 0x00100000 197 #define MAC_CFG_SPEED_1000 0x00200000 198 #define MAC_CFG_DBG_TX_BACKOFF 0x00400000 199 #define MAC_CFG_TX_JUMBO_ENB 0x00800000 200 #define MAC_CFG_RXCSUM_ENB 0x01000000 201 #define MAC_CFG_ALLMULTI 0x02000000 202 #define MAC_CFG_BCAST 0x04000000 203 #define MAC_CFG_DBG 0x08000000 204 #define MAC_CFG_PREAMBLE_SHIFT 10 205 #define MAC_CFG_PREAMBLE_DEFAULT 7 206 207 #define ALE_IPG_IFG_CFG 0x1484 208 #define IPG_IFG_IPGT_MASK 0x0000007F 209 #define IPG_IFG_MIFG_MASK 0x0000FF00 210 #define IPG_IFG_IPG1_MASK 0x007F0000 211 #define IPG_IFG_IPG2_MASK 0x7F000000 212 #define IPG_IFG_IPGT_SHIFT 0 213 #define IPG_IFG_IPGT_DEFAULT 0x60 214 #define IPG_IFG_MIFG_SHIFT 8 215 #define IPG_IFG_MIFG_DEFAULT 0x50 216 #define IPG_IFG_IPG1_SHIFT 16 217 #define IPG_IFG_IPG1_DEFAULT 0x40 218 #define IPG_IFG_IPG2_SHIFT 24 219 #define IPG_IFG_IPG2_DEFAULT 0x60 220 221 /* Station address. */ 222 #define ALE_PAR0 0x1488 223 #define ALE_PAR1 0x148C 224 225 /* 64bit multicast hash register. */ 226 #define ALE_MAR0 0x1490 227 #define ALE_MAR1 0x1494 228 229 /* half-duplex parameter configuration. */ 230 #define ALE_HDPX_CFG 0x1498 231 #define HDPX_CFG_LCOL_MASK 0x000003FF 232 #define HDPX_CFG_RETRY_MASK 0x0000F000 233 #define HDPX_CFG_EXC_DEF_EN 0x00010000 234 #define HDPX_CFG_NO_BACK_C 0x00020000 235 #define HDPX_CFG_NO_BACK_P 0x00040000 236 #define HDPX_CFG_ABEBE 0x00080000 237 #define HDPX_CFG_ABEBT_MASK 0x00F00000 238 #define HDPX_CFG_JAMIPG_MASK 0x0F000000 239 #define HDPX_CFG_LCOL_SHIFT 0 240 #define HDPX_CFG_LCOL_DEFAULT 0x37 241 #define HDPX_CFG_RETRY_SHIFT 12 242 #define HDPX_CFG_RETRY_DEFAULT 0x0F 243 #define HDPX_CFG_ABEBT_SHIFT 20 244 #define HDPX_CFG_ABEBT_DEFAULT 0x0A 245 #define HDPX_CFG_JAMIPG_SHIFT 24 246 #define HDPX_CFG_JAMIPG_DEFAULT 0x07 247 248 #define ALE_FRAME_SIZE 0x149C 249 250 #define ALE_WOL_CFG 0x14A0 251 #define WOL_CFG_PATTERN 0x00000001 252 #define WOL_CFG_PATTERN_ENB 0x00000002 253 #define WOL_CFG_MAGIC 0x00000004 254 #define WOL_CFG_MAGIC_ENB 0x00000008 255 #define WOL_CFG_LINK_CHG 0x00000010 256 #define WOL_CFG_LINK_CHG_ENB 0x00000020 257 #define WOL_CFG_PATTERN_DET 0x00000100 258 #define WOL_CFG_MAGIC_DET 0x00000200 259 #define WOL_CFG_LINK_CHG_DET 0x00000400 260 #define WOL_CFG_CLK_SWITCH_ENB 0x00008000 261 #define WOL_CFG_PATTERN0 0x00010000 262 #define WOL_CFG_PATTERN1 0x00020000 263 #define WOL_CFG_PATTERN2 0x00040000 264 #define WOL_CFG_PATTERN3 0x00080000 265 #define WOL_CFG_PATTERN4 0x00100000 266 #define WOL_CFG_PATTERN5 0x00200000 267 #define WOL_CFG_PATTERN6 0x00400000 268 269 /* WOL pattern length. */ 270 #define ALE_PATTERN_CFG0 0x14A4 271 #define PATTERN_CFG_0_LEN_MASK 0x0000007F 272 #define PATTERN_CFG_1_LEN_MASK 0x00007F00 273 #define PATTERN_CFG_2_LEN_MASK 0x007F0000 274 #define PATTERN_CFG_3_LEN_MASK 0x7F000000 275 276 #define ALE_PATTERN_CFG1 0x14A8 277 #define PATTERN_CFG_4_LEN_MASK 0x0000007F 278 #define PATTERN_CFG_5_LEN_MASK 0x00007F00 279 #define PATTERN_CFG_6_LEN_MASK 0x007F0000 280 281 /* RSS */ 282 #define ALE_RSS_KEY0 0x14B0 283 284 #define ALE_RSS_KEY1 0x14B4 285 286 #define ALE_RSS_KEY2 0x14B8 287 288 #define ALE_RSS_KEY3 0x14BC 289 290 #define ALE_RSS_KEY4 0x14C0 291 292 #define ALE_RSS_KEY5 0x14C4 293 294 #define ALE_RSS_KEY6 0x14C8 295 296 #define ALE_RSS_KEY7 0x14CC 297 298 #define ALE_RSS_KEY8 0x14D0 299 300 #define ALE_RSS_KEY9 0x14D4 301 302 #define ALE_RSS_IDT_TABLE4 0x14E0 303 304 #define ALE_RSS_IDT_TABLE5 0x14E4 305 306 #define ALE_RSS_IDT_TABLE6 0x14E8 307 308 #define ALE_RSS_IDT_TABLE7 0x14EC 309 310 #define ALE_SRAM_RD_ADDR 0x1500 311 312 #define ALE_SRAM_RD_LEN 0x1504 313 314 #define ALE_SRAM_RRD_ADDR 0x1508 315 316 #define ALE_SRAM_RRD_LEN 0x150C 317 318 #define ALE_SRAM_TPD_ADDR 0x1510 319 320 #define ALE_SRAM_TPD_LEN 0x1514 321 322 #define ALE_SRAM_TRD_ADDR 0x1518 323 324 #define ALE_SRAM_TRD_LEN 0x151C 325 326 #define ALE_SRAM_RX_FIFO_ADDR 0x1520 327 328 #define ALE_SRAM_RX_FIFO_LEN 0x1524 329 330 #define ALE_SRAM_TX_FIFO_ADDR 0x1528 331 332 #define ALE_SRAM_TX_FIFO_LEN 0x152C 333 334 #define ALE_SRAM_TCPH_ADDR 0x1530 335 #define SRAM_TCPH_ADDR_MASK 0x00000FFF 336 #define SRAM_PATH_ADDR_MASK 0x0FFF0000 337 #define SRAM_TCPH_ADDR_SHIFT 0 338 #define SRAM_PATH_ADDR_SHIFT 16 339 340 #define ALE_DMA_BLOCK 0x1534 341 #define DMA_BLOCK_LOAD 0x00000001 342 343 #define ALE_RXF3_ADDR_HI 0x153C 344 345 #define ALE_TPD_ADDR_HI 0x1540 346 347 #define ALE_RXF0_PAGE0_ADDR_LO 0x1544 348 349 #define ALE_RXF0_PAGE1_ADDR_LO 0x1548 350 351 #define ALE_TPD_ADDR_LO 0x154C 352 353 #define ALE_RXF1_ADDR_HI 0x1550 354 355 #define ALE_RXF2_ADDR_HI 0x1554 356 357 #define ALE_RXF_PAGE_SIZE 0x1558 358 359 #define ALE_TPD_CNT 0x155C 360 #define TPD_CNT_MASK 0x00003FF 361 #define TPD_CNT_SHIFT 0 362 363 #define ALE_RSS_IDT_TABLE0 0x1560 364 365 #define ALE_RSS_IDT_TABLE1 0x1564 366 367 #define ALE_RSS_IDT_TABLE2 0x1568 368 369 #define ALE_RSS_IDT_TABLE3 0x156C 370 371 #define ALE_RSS_HASH_VALUE 0x1570 372 373 #define ALE_RSS_HASH_FLAG 0x1574 374 375 #define ALE_RSS_CPU 0x157C 376 377 #define ALE_TXQ_CFG 0x1580 378 #define TXQ_CFG_TPD_BURST_MASK 0x0000000F 379 #define TXQ_CFG_ENB 0x00000020 380 #define TXQ_CFG_ENHANCED_MODE 0x00000040 381 #define TXQ_CFG_TX_FIFO_BURST_MASK 0xFFFF0000 382 #define TXQ_CFG_TPD_BURST_SHIFT 0 383 #define TXQ_CFG_TPD_BURST_DEFAULT 4 384 #define TXQ_CFG_TX_FIFO_BURST_SHIFT 16 385 #define TXQ_CFG_TX_FIFO_BURST_DEFAULT 256 386 387 #define ALE_TX_JUMBO_THRESH 0x1584 388 #define TX_JUMBO_THRESH_MASK 0x000007FF 389 #define TX_JUMBO_THRESH_SHIFT 0 390 #define TX_JUMBO_THRESH_UNIT 8 391 #define TX_JUMBO_THRESH_UNIT_SHIFT 3 392 393 #define ALE_RXQ_CFG 0x15A0 394 #define RXQ_CFG_ALIGN_32 0x00000000 395 #define RXQ_CFG_ALIGN_64 0x00000001 396 #define RXQ_CFG_ALIGN_128 0x00000002 397 #define RXQ_CFG_ALIGN_256 0x00000003 398 #define RXQ_CFG_QUEUE1_ENB 0x00000010 399 #define RXQ_CFG_QUEUE2_ENB 0x00000020 400 #define RXQ_CFG_QUEUE3_ENB 0x00000040 401 #define RXQ_CFG_IPV6_CSUM_VERIFY 0x00000080 402 #define RXQ_CFG_RSS_HASH_TBL_LEN_MASK 0x0000FF00 403 #define RXQ_CFG_RSS_HASH_IPV4 0x00010000 404 #define RXQ_CFG_RSS_HASH_IPV4_TCP 0x00020000 405 #define RXQ_CFG_RSS_HASH_IPV6 0x00040000 406 #define RXQ_CFG_RSS_HASH_IPV6_TCP 0x00080000 407 #define RXQ_CFG_RSS_MODE_DIS 0x00000000 408 #define RXQ_CFG_RSS_MODE_SQSINT 0x04000000 409 #define RXQ_CFG_RSS_MODE_MQUESINT 0x08000000 410 #define RXQ_CFG_RSS_MODE_MQUEMINT 0x0C000000 411 #define RXQ_CFG_NIP_QUEUE_SEL_TBL 0x10000000 412 #define RXQ_CFG_RSS_HASH_ENB 0x20000000 413 #define RXQ_CFG_CUT_THROUGH_ENB 0x40000000 414 #define RXQ_CFG_ENB 0x80000000 415 #define RXQ_CFG_RSS_HASH_TBL_LEN_SHIFT 8 416 417 #define ALE_RX_JUMBO_THRESH 0x15A4 /* 16bits */ 418 #define RX_JUMBO_THRESH_MASK 0x07FF 419 #define RX_JUMBO_LKAH_MASK 0x7800 420 #define RX_JUMBO_THRESH_MASK_SHIFT 0 421 #define RX_JUMBO_THRESH_UNIT 8 422 #define RX_JUMBO_THRESH_UNIT_SHIFT 3 423 #define RX_JUMBO_LKAH_SHIFT 11 424 #define RX_JUMBO_LKAH_DEFAULT 1 425 426 #define ALE_RX_FIFO_PAUSE_THRESH 0x15A8 427 #define RX_FIFO_PAUSE_THRESH_LO_MASK 0x00000FFF 428 #define RX_FIFO_PAUSE_THRESH_HI_MASK 0x0FFF0000 429 #define RX_FIFO_PAUSE_THRESH_LO_SHIFT 0 430 #define RX_FIFO_PAUSE_THRESH_HI_SHIFT 16 431 432 #define ALE_CMB_RXF1 0x15B4 433 434 #define ALE_CMB_RXF2 0x15B8 435 436 #define ALE_CMB_RXF3 0x15BC 437 438 #define ALE_DMA_CFG 0x15C0 439 #define DMA_CFG_IN_ORDER 0x00000001 440 #define DMA_CFG_ENH_ORDER 0x00000002 441 #define DMA_CFG_OUT_ORDER 0x00000004 442 #define DMA_CFG_RCB_64 0x00000000 443 #define DMA_CFG_RCB_128 0x00000008 444 #define DMA_CFG_RD_BURST_128 0x00000000 445 #define DMA_CFG_RD_BURST_256 0x00000010 446 #define DMA_CFG_RD_BURST_512 0x00000020 447 #define DMA_CFG_RD_BURST_1024 0x00000030 448 #define DMA_CFG_RD_BURST_2048 0x00000040 449 #define DMA_CFG_RD_BURST_4096 0x00000050 450 #define DMA_CFG_WR_BURST_128 0x00000000 451 #define DMA_CFG_WR_BURST_256 0x00000080 452 #define DMA_CFG_WR_BURST_512 0x00000100 453 #define DMA_CFG_WR_BURST_1024 0x00000180 454 #define DMA_CFG_WR_BURST_2048 0x00000200 455 #define DMA_CFG_WR_BURST_4096 0x00000280 456 #define DMA_CFG_RD_REQ_PRI 0x00000400 457 #define DMA_CFG_RD_DELAY_CNT_MASK 0x0000F800 458 #define DMA_CFG_WR_DELAY_CNT_MASK 0x000F0000 459 #define DMA_CFG_TXCMB_ENB 0x00100000 460 #define DMA_CFG_RXCMB_ENB 0x00200000 461 #define DMA_CFG_RD_BURST_MASK 0x07 462 #define DMA_CFG_RD_BURST_SHIFT 4 463 #define DMA_CFG_WR_BURST_MASK 0x07 464 #define DMA_CFG_WR_BURST_SHIFT 7 465 #define DMA_CFG_RD_DELAY_CNT_SHIFT 11 466 #define DMA_CFG_WR_DELAY_CNT_SHIFT 16 467 #define DMA_CFG_RD_DELAY_CNT_DEFAULT 15 468 #define DMA_CFG_WR_DELAY_CNT_DEFAULT 4 469 470 #define ALE_SMB_STAT_TIMER 0x15C4 471 472 #define ALE_INT_TRIG_THRESH 0x15C8 473 #define INT_TRIG_TX_THRESH_MASK 0x0000FFFF 474 #define INT_TRIG_RX_THRESH_MASK 0xFFFF0000 475 #define INT_TRIG_TX_THRESH_SHIFT 0 476 #define INT_TRIG_RX_THRESH_SHIFT 16 477 478 #define ALE_INT_TRIG_TIMER 0x15CC 479 #define INT_TRIG_TX_TIMER_MASK 0x0000FFFF 480 #define INT_TRIG_RX_TIMER_MASK 0x0000FFFF 481 #define INT_TRIG_TX_TIMER_SHIFT 0 482 #define INT_TRIG_RX_TIMER_SHIFT 16 483 484 #define ALE_RXF1_PAGE0_ADDR_LO 0x15D0 485 486 #define ALE_RXF1_PAGE1_ADDR_LO 0x15D4 487 488 #define ALE_RXF2_PAGE0_ADDR_LO 0x15D8 489 490 #define ALE_RXF2_PAGE1_ADDR_LO 0x15DC 491 492 #define ALE_RXF3_PAGE0_ADDR_LO 0x15E0 493 494 #define ALE_RXF3_PAGE1_ADDR_LO 0x15E4 495 496 #define ALE_MBOX_TPD_PROD_IDX 0x15F0 497 498 #define ALE_RXF0_PAGE0 0x15F4 499 500 #define ALE_RXF0_PAGE1 0x15F5 501 502 #define ALE_RXF1_PAGE0 0x15F6 503 504 #define ALE_RXF1_PAGE1 0x15F7 505 506 #define ALE_RXF2_PAGE0 0x15F8 507 508 #define ALE_RXF2_PAGE1 0x15F9 509 510 #define ALE_RXF3_PAGE0 0x15FA 511 512 #define ALE_RXF3_PAGE1 0x15FB 513 514 #define RXF_VALID 0x01 515 516 #define ALE_INTR_STATUS 0x1600 517 #define INTR_SMB 0x00000001 518 #define INTR_TIMER 0x00000002 519 #define INTR_MANUAL_TIMER 0x00000004 520 #define INTR_RX_FIFO_OFLOW 0x00000008 521 #define INTR_RXF0_OFLOW 0x00000010 522 #define INTR_RXF1_OFLOW 0x00000020 523 #define INTR_RXF2_OFLOW 0x00000040 524 #define INTR_RXF3_OFLOW 0x00000080 525 #define INTR_TX_FIFO_UNDERRUN 0x00000100 526 #define INTR_RX0_PAGE_FULL 0x00000200 527 #define INTR_DMA_RD_TO_RST 0x00000400 528 #define INTR_DMA_WR_TO_RST 0x00000800 529 #define INTR_GPHY 0x00001000 530 #define INTR_TX_CREDIT 0x00002000 531 #define INTR_GPHY_LOW_PW 0x00004000 532 #define INTR_RX_PKT 0x00010000 533 #define INTR_TX_PKT 0x00020000 534 #define INTR_TX_DMA 0x00040000 535 #define INTR_RX_PKT1 0x00080000 536 #define INTR_RX_PKT2 0x00100000 537 #define INTR_RX_PKT3 0x00200000 538 #define INTR_MAC_RX 0x00400000 539 #define INTR_MAC_TX 0x00800000 540 #define INTR_UNDERRUN 0x01000000 541 #define INTR_FRAME_ERROR 0x02000000 542 #define INTR_FRAME_OK 0x04000000 543 #define INTR_CSUM_ERROR 0x08000000 544 #define INTR_PHY_LINK_DOWN 0x10000000 545 #define INTR_DIS_INT 0x80000000 546 547 /* Interrupt Mask Register */ 548 #define ALE_INTR_MASK 0x1604 549 550 #define ALE_INTRS \ 551 (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | \ 552 INTR_RX_PKT | INTR_TX_PKT | INTR_RX_FIFO_OFLOW | \ 553 INTR_TX_FIFO_UNDERRUN) 554 555 /* 556 * AR81xx requires register access to get MAC statistics 557 * and the format of statistics seems to be the same of L1 . 558 */ 559 #define ALE_RX_MIB_BASE 0x1700 560 561 #define ALE_TX_MIB_BASE 0x1760 562 563 /* Statistics counters collected by the MAC. */ 564 struct smb { 565 /* Rx stats. */ 566 uint32_t rx_frames; 567 uint32_t rx_bcast_frames; 568 uint32_t rx_mcast_frames; 569 uint32_t rx_pause_frames; 570 uint32_t rx_control_frames; 571 uint32_t rx_crcerrs; 572 uint32_t rx_lenerrs; 573 uint32_t rx_bytes; 574 uint32_t rx_runts; 575 uint32_t rx_fragments; 576 uint32_t rx_pkts_64; 577 uint32_t rx_pkts_65_127; 578 uint32_t rx_pkts_128_255; 579 uint32_t rx_pkts_256_511; 580 uint32_t rx_pkts_512_1023; 581 uint32_t rx_pkts_1024_1518; 582 uint32_t rx_pkts_1519_max; 583 uint32_t rx_pkts_truncated; 584 uint32_t rx_fifo_oflows; 585 uint32_t rx_rrs_errs; 586 uint32_t rx_alignerrs; 587 uint32_t rx_bcast_bytes; 588 uint32_t rx_mcast_bytes; 589 uint32_t rx_pkts_filtered; 590 /* Tx stats. */ 591 uint32_t tx_frames; 592 uint32_t tx_bcast_frames; 593 uint32_t tx_mcast_frames; 594 uint32_t tx_pause_frames; 595 uint32_t tx_excess_defer; 596 uint32_t tx_control_frames; 597 uint32_t tx_deferred; 598 uint32_t tx_bytes; 599 uint32_t tx_pkts_64; 600 uint32_t tx_pkts_65_127; 601 uint32_t tx_pkts_128_255; 602 uint32_t tx_pkts_256_511; 603 uint32_t tx_pkts_512_1023; 604 uint32_t tx_pkts_1024_1518; 605 uint32_t tx_pkts_1519_max; 606 uint32_t tx_single_colls; 607 uint32_t tx_multi_colls; 608 uint32_t tx_late_colls; 609 uint32_t tx_excess_colls; 610 uint32_t tx_underrun; 611 uint32_t tx_desc_underrun; 612 uint32_t tx_lenerrs; 613 uint32_t tx_pkts_truncated; 614 uint32_t tx_bcast_bytes; 615 uint32_t tx_mcast_bytes; 616 } __packed; 617 618 #define ALE_HOST_RXF0_PAGEOFF 0x1800 619 620 #define ALE_TPD_CONS_IDX 0x1804 621 622 #define ALE_HOST_RXF1_PAGEOFF 0x1808 623 624 #define ALE_HOST_RXF2_PAGEOFF 0x180C 625 626 #define ALE_HOST_RXF3_PAGEOFF 0x1810 627 628 #define ALE_RXF0_CMB0_ADDR_LO 0x1820 629 630 #define ALE_RXF0_CMB1_ADDR_LO 0x1824 631 632 #define ALE_RXF1_CMB0_ADDR_LO 0x1828 633 634 #define ALE_RXF1_CMB1_ADDR_LO 0x182C 635 636 #define ALE_RXF2_CMB0_ADDR_LO 0x1830 637 638 #define ALE_RXF2_CMB1_ADDR_LO 0x1834 639 640 #define ALE_RXF3_CMB0_ADDR_LO 0x1838 641 642 #define ALE_RXF3_CMB1_ADDR_LO 0x183C 643 644 #define ALE_TX_CMB_ADDR_LO 0x1840 645 646 #define ALE_SMB_ADDR_LO 0x1844 647 648 /* 649 * RRS(receive return status) structure. 650 * 651 * Note: 652 * Atheros AR81xx does not support descriptor based DMA on Rx 653 * instead it just prepends a Rx status structure prior to a 654 * received frame which also resides on the same Rx buffer. 655 * This means driver should copy an entire frame from the 656 * buffer to new mbuf chain which in turn greatly increases CPU 657 * cycles and effectively nullify the advantage of DMA 658 * operation of controller. So you should have fast CPU to cope 659 * with the copy operation. Implementing flow-controls may help 660 * a lot to minimize Rx FIFO overflows but it's not available 661 * yet on FreeBSD and hardware doesn't seem to support 662 * fine-grained Tx/Rx flow controls. 663 */ 664 struct rx_rs { 665 uint32_t seqno; 666 #define ALE_RD_SEQNO_MASK 0x0000FFFF 667 #define ALE_RD_HASH_MASK 0xFFFF0000 668 #define ALE_RD_SEQNO_SHIFT 0 669 #define ALE_RD_HASH_SHIFT 16 670 #define ALE_RX_SEQNO(x) \ 671 (((x) & ALE_RD_SEQNO_MASK) >> ALE_RD_SEQNO_SHIFT) 672 uint32_t length; 673 #define ALE_RD_CSUM_MASK 0x0000FFFF 674 #define ALE_RD_LEN_MASK 0x3FFF0000 675 #define ALE_RD_CPU_MASK 0xC0000000 676 #define ALE_RD_CSUM_SHIFT 0 677 #define ALE_RD_LEN_SHIFT 16 678 #define ALE_RD_CPU_SHIFT 30 679 #define ALE_RX_CSUM(x) \ 680 (((x) & ALE_RD_CSUM_MASK) >> ALE_RD_CSUM_SHIFT) 681 #define ALE_RX_BYTES(x) \ 682 (((x) & ALE_RD_LEN_MASK) >> ALE_RD_LEN_SHIFT) 683 #define ALE_RX_CPU(x) \ 684 (((x) & ALE_RD_CPU_MASK) >> ALE_RD_CPU_SHIFT) 685 uint32_t flags; 686 #define ALE_RD_RSS_IPV4 0x00000001 687 #define ALE_RD_RSS_IPV4_TCP 0x00000002 688 #define ALE_RD_RSS_IPV6 0x00000004 689 #define ALE_RD_RSS_IPV6_TCP 0x00000008 690 #define ALE_RD_IPV6 0x00000010 691 #define ALE_RD_IPV4_FRAG 0x00000020 692 #define ALE_RD_IPV4_DF 0x00000040 693 #define ALE_RD_802_3 0x00000080 694 #define ALE_RD_VLAN 0x00000100 695 #define ALE_RD_ERROR 0x00000200 696 #define ALE_RD_IPV4 0x00000400 697 #define ALE_RD_UDP 0x00000800 698 #define ALE_RD_TCP 0x00001000 699 #define ALE_RD_BCAST 0x00002000 700 #define ALE_RD_MCAST 0x00004000 701 #define ALE_RD_PAUSE 0x00008000 702 #define ALE_RD_CRC 0x00010000 703 #define ALE_RD_CODE 0x00020000 704 #define ALE_RD_DRIBBLE 0x00040000 705 #define ALE_RD_RUNT 0x00080000 706 #define ALE_RD_OFLOW 0x00100000 707 #define ALE_RD_TRUNC 0x00200000 708 #define ALE_RD_IPCSUM_NOK 0x00400000 709 #define ALE_RD_TCP_UDPCSUM_NOK 0x00800000 710 #define ALE_RD_LENGTH_NOK 0x01000000 711 #define ALE_RD_DES_ADDR_FILTERED 0x02000000 712 uint32_t vtags; 713 #define ALE_RD_HASH_HI_MASK 0x0000FFFF 714 #define ALE_RD_HASH_HI_SHIFT 0 715 #define ALE_RD_VLAN_MASK 0xFFFF0000 716 #define ALE_RD_VLAN_SHIFT 16 717 #define ALE_RX_VLAN(x) \ 718 (((x) & ALE_RD_VLAN_MASK) >> ALE_RD_VLAN_SHIFT) 719 #define ALE_RX_VLAN_TAG(x) \ 720 (((x) >> 4) | (((x) & 7) << 13) | (((x) & 8) << 9)) 721 } __packed; 722 723 /* Tx descriptor. */ 724 struct tx_desc { 725 uint64_t addr; 726 uint32_t len; 727 #define ALE_TD_VLAN_MASK 0xFFFF0000 728 #define ALE_TD_PKT_INT 0x00008000 729 #define ALE_TD_DMA_INT 0x00004000 730 #define ALE_TD_BUFLEN_MASK 0x00003FFF 731 #define ALE_TD_VLAN_SHIFT 16 732 #define ALE_TX_VLAN_TAG(x) \ 733 (((x) << 4) | ((x) >> 13) | (((x) >> 9) & 8)) 734 #define ALE_TD_BUFLEN_SHIFT 0 735 #define ALE_TX_BYTES(x) \ 736 (((x) << ALE_TD_BUFLEN_SHIFT) & ALE_TD_BUFLEN_MASK) 737 uint32_t flags; 738 #define ALE_TD_MSS 0xFFF80000 739 #define ALE_TD_TSO_HDR 0x00040000 740 #define ALE_TD_TCPHDR_LEN 0x0003C000 741 #define ALE_TD_IPHDR_LEN 0x00003C00 742 #define ALE_TD_IPV6HDR_LEN2 0x00003C00 743 #define ALE_TD_LLC_SNAP 0x00000200 744 #define ALE_TD_VLAN_TAGGED 0x00000100 745 #define ALE_TD_UDPCSUM 0x00000080 746 #define ALE_TD_TCPCSUM 0x00000040 747 #define ALE_TD_IPCSUM 0x00000020 748 #define ALE_TD_IPV6HDR_LEN1 0x000000E0 749 #define ALE_TD_TSO 0x00000010 750 #define ALE_TD_CXSUM 0x00000008 751 #define ALE_TD_INSERT_VLAN_TAG 0x00000004 752 #define ALE_TD_IPV6 0x00000002 753 #define ALE_TD_EOP 0x00000001 754 755 #define ALE_TD_CSUM_PLOADOFFSET 0x00FF0000 756 #define ALE_TD_CSUM_XSUMOFFSET 0xFF000000 757 #define ALE_TD_CSUM_XSUMOFFSET_SHIFT 24 758 #define ALE_TD_CSUM_PLOADOFFSET_SHIFT 16 759 #define ALE_TD_MSS_SHIFT 19 760 #define ALE_TD_TCPHDR_LEN_SHIFT 14 761 #define ALE_TD_IPHDR_LEN_SHIFT 10 762 } __packed; 763 764 #endif /* _IF_ALEREG_H */ 765