1 /*- 2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * $FreeBSD$ 28 */ 29 30 #ifndef _IF_ALEREG_H 31 #define _IF_ALEREG_H 32 33 /* 34 * Atheros Communucations, Inc. PCI vendor ID 35 */ 36 #define VENDORID_ATHEROS 0x1969 37 38 /* 39 * Atheros AR8121/AR8113/AR8114 device ID 40 */ 41 #define DEVICEID_ATHEROS_AR81XX 0x1026 42 43 #define ALE_SPI_CTRL 0x200 44 #define SPI_VPD_ENB 0x00002000 45 46 #define ALE_SPI_ADDR 0x204 /* 16bits */ 47 48 #define ALE_SPI_DATA 0x208 49 50 #define ALE_SPI_CONFIG 0x20C 51 52 #define ALE_SPI_OP_PROGRAM 0x210 /* 8bits */ 53 54 #define ALE_SPI_OP_SC_ERASE 0x211 /* 8bits */ 55 56 #define ALE_SPI_OP_CHIP_ERASE 0x212 /* 8bits */ 57 58 #define ALE_SPI_OP_RDID 0x213 /* 8bits */ 59 60 #define ALE_SPI_OP_WREN 0x214 /* 8bits */ 61 62 #define ALE_SPI_OP_RDSR 0x215 /* 8bits */ 63 64 #define ALE_SPI_OP_WRSR 0x216 /* 8bits */ 65 66 #define ALE_SPI_OP_READ 0x217 /* 8bits */ 67 68 #define ALE_TWSI_CTRL 0x218 69 #define TWSI_CTRL_SW_LD_START 0x00000800 70 #define TWSI_CTRL_HW_LD_START 0x00001000 71 #define TWSI_CTRL_LD_EXIST 0x00400000 72 73 #define ALE_DEV_MISC_CTRL 0x21C 74 75 #define ALE_PCIE_PHYMISC 0x1000 76 #define PCIE_PHYMISC_FORCE_RCV_DET 0x00000004 77 78 #define ALE_MASTER_CFG 0x1400 79 #define MASTER_RESET 0x00000001 80 #define MASTER_MTIMER_ENB 0x00000002 81 #define MASTER_IM_TX_TIMER_ENB 0x00000004 82 #define MASTER_MANUAL_INT_ENB 0x00000008 83 #define MASTER_IM_RX_TIMER_ENB 0x00000020 84 #define MASTER_INT_RDCLR 0x00000040 85 #define MASTER_LED_MODE 0x00000200 86 #define MASTER_CHIP_REV_MASK 0x00FF0000 87 #define MASTER_CHIP_ID_MASK 0xFF000000 88 #define MASTER_CHIP_REV_SHIFT 16 89 #define MASTER_CHIP_ID_SHIFT 24 90 91 /* Number of ticks per usec for AR81xx. */ 92 #define ALE_TICK_USECS 2 93 #define ALE_USECS(x) ((x) / ALE_TICK_USECS) 94 95 #define ALE_MANUAL_TIMER 0x1404 96 97 #define ALE_IM_TIMER 0x1408 98 #define IM_TIMER_TX_MASK 0x0000FFFF 99 #define IM_TIMER_RX_MASK 0xFFFF0000 100 #define IM_TIMER_TX_SHIFT 0 101 #define IM_TIMER_RX_SHIFT 16 102 #define ALE_IM_TIMER_MIN 0 103 #define ALE_IM_TIMER_MAX 130000 /* 130ms */ 104 #define ALE_IM_RX_TIMER_DEFAULT 30 105 #define ALE_IM_TX_TIMER_DEFAULT 1000 106 107 #define ALE_GPHY_CTRL 0x140C /* 16bits */ 108 #define GPHY_CTRL_EXT_RESET 0x0001 109 #define GPHY_CTRL_PIPE_MOD 0x0002 110 #define GPHY_CTRL_BERT_START 0x0010 111 #define GPHY_CTRL_GALE_25M_ENB 0x0020 112 #define GPHY_CTRL_LPW_EXIT 0x0040 113 #define GPHY_CTRL_PHY_IDDQ 0x0080 114 #define GPHY_CTRL_PHY_IDDQ_DIS 0x0100 115 #define GPHY_CTRL_PCLK_SEL_DIS 0x0200 116 #define GPHY_CTRL_HIB_EN 0x0400 117 #define GPHY_CTRL_HIB_PULSE 0x0800 118 #define GPHY_CTRL_SEL_ANA_RESET 0x1000 119 #define GPHY_CTRL_PHY_PLL_ON 0x2000 120 #define GPHY_CTRL_PWDOWN_HW 0x4000 121 122 #define ALE_INTR_CLR_TIMER 0x140E /* 16bits */ 123 124 #define ALE_IDLE_STATUS 0x1410 125 #define IDLE_STATUS_RXMAC 0x00000001 126 #define IDLE_STATUS_TXMAC 0x00000002 127 #define IDLE_STATUS_RXQ 0x00000004 128 #define IDLE_STATUS_TXQ 0x00000008 129 #define IDLE_STATUS_DMARD 0x00000010 130 #define IDLE_STATUS_DMAWR 0x00000020 131 #define IDLE_STATUS_SMB 0x00000040 132 #define IDLE_STATUS_CMB 0x00000080 133 134 #define ALE_MDIO 0x1414 135 #define MDIO_DATA_MASK 0x0000FFFF 136 #define MDIO_REG_ADDR_MASK 0x001F0000 137 #define MDIO_OP_READ 0x00200000 138 #define MDIO_OP_WRITE 0x00000000 139 #define MDIO_SUP_PREAMBLE 0x00400000 140 #define MDIO_OP_EXECUTE 0x00800000 141 #define MDIO_CLK_25_4 0x00000000 142 #define MDIO_CLK_25_6 0x02000000 143 #define MDIO_CLK_25_8 0x03000000 144 #define MDIO_CLK_25_10 0x04000000 145 #define MDIO_CLK_25_14 0x05000000 146 #define MDIO_CLK_25_20 0x06000000 147 #define MDIO_CLK_25_28 0x07000000 148 #define MDIO_OP_BUSY 0x08000000 149 #define MDIO_DATA_SHIFT 0 150 #define MDIO_REG_ADDR_SHIFT 16 151 152 #define MDIO_REG_ADDR(x) \ 153 (((x) << MDIO_REG_ADDR_SHIFT) & MDIO_REG_ADDR_MASK) 154 /* Default PHY address. */ 155 #define ALE_PHY_ADDR 0 156 157 #define ALE_PHY_STATUS 0x1418 158 #define PHY_STATUS_100M 0x00020000 159 160 /* Packet memory BIST. */ 161 #define ALE_BIST0 0x141C 162 #define BIST0_ENB 0x00000001 163 #define BIST0_SRAM_FAIL 0x00000002 164 #define BIST0_FUSE_FLAG 0x00000004 165 166 /* PCIe retry buffer BIST. */ 167 #define ALE_BIST1 0x1420 168 #define BIST1_ENB 0x00000001 169 #define BIST1_SRAM_FAIL 0x00000002 170 #define BIST1_FUSE_FLAG 0x00000004 171 172 #define ALE_SERDES_LOCK 0x1424 173 #define SERDES_LOCK_DET 0x00000001 174 #define SERDES_LOCK_DET_ENB 0x00000002 175 176 #define ALE_MAC_CFG 0x1480 177 #define MAC_CFG_TX_ENB 0x00000001 178 #define MAC_CFG_RX_ENB 0x00000002 179 #define MAC_CFG_TX_FC 0x00000004 180 #define MAC_CFG_RX_FC 0x00000008 181 #define MAC_CFG_LOOP 0x00000010 182 #define MAC_CFG_FULL_DUPLEX 0x00000020 183 #define MAC_CFG_TX_CRC_ENB 0x00000040 184 #define MAC_CFG_TX_AUTO_PAD 0x00000080 185 #define MAC_CFG_TX_LENCHK 0x00000100 186 #define MAC_CFG_RX_JUMBO_ENB 0x00000200 187 #define MAC_CFG_PREAMBLE_MASK 0x00003C00 188 #define MAC_CFG_VLAN_TAG_STRIP 0x00004000 189 #define MAC_CFG_PROMISC 0x00008000 190 #define MAC_CFG_TX_PAUSE 0x00010000 191 #define MAC_CFG_SCNT 0x00020000 192 #define MAC_CFG_SYNC_RST_TX 0x00040000 193 #define MAC_CFG_SPEED_MASK 0x00300000 194 #define MAC_CFG_SPEED_10_100 0x00100000 195 #define MAC_CFG_SPEED_1000 0x00200000 196 #define MAC_CFG_DBG_TX_BACKOFF 0x00400000 197 #define MAC_CFG_TX_JUMBO_ENB 0x00800000 198 #define MAC_CFG_RXCSUM_ENB 0x01000000 199 #define MAC_CFG_ALLMULTI 0x02000000 200 #define MAC_CFG_BCAST 0x04000000 201 #define MAC_CFG_DBG 0x08000000 202 #define MAC_CFG_PREAMBLE_SHIFT 10 203 #define MAC_CFG_PREAMBLE_DEFAULT 7 204 205 #define ALE_IPG_IFG_CFG 0x1484 206 #define IPG_IFG_IPGT_MASK 0x0000007F 207 #define IPG_IFG_MIFG_MASK 0x0000FF00 208 #define IPG_IFG_IPG1_MASK 0x007F0000 209 #define IPG_IFG_IPG2_MASK 0x7F000000 210 #define IPG_IFG_IPGT_SHIFT 0 211 #define IPG_IFG_IPGT_DEFAULT 0x60 212 #define IPG_IFG_MIFG_SHIFT 8 213 #define IPG_IFG_MIFG_DEFAULT 0x50 214 #define IPG_IFG_IPG1_SHIFT 16 215 #define IPG_IFG_IPG1_DEFAULT 0x40 216 #define IPG_IFG_IPG2_SHIFT 24 217 #define IPG_IFG_IPG2_DEFAULT 0x60 218 219 /* Station address. */ 220 #define ALE_PAR0 0x1488 221 #define ALE_PAR1 0x148C 222 223 /* 64bit multicast hash register. */ 224 #define ALE_MAR0 0x1490 225 #define ALE_MAR1 0x1494 226 227 /* half-duplex parameter configuration. */ 228 #define ALE_HDPX_CFG 0x1498 229 #define HDPX_CFG_LCOL_MASK 0x000003FF 230 #define HDPX_CFG_RETRY_MASK 0x0000F000 231 #define HDPX_CFG_EXC_DEF_EN 0x00010000 232 #define HDPX_CFG_NO_BACK_C 0x00020000 233 #define HDPX_CFG_NO_BACK_P 0x00040000 234 #define HDPX_CFG_ABEBE 0x00080000 235 #define HDPX_CFG_ABEBT_MASK 0x00F00000 236 #define HDPX_CFG_JAMIPG_MASK 0x0F000000 237 #define HDPX_CFG_LCOL_SHIFT 0 238 #define HDPX_CFG_LCOL_DEFAULT 0x37 239 #define HDPX_CFG_RETRY_SHIFT 12 240 #define HDPX_CFG_RETRY_DEFAULT 0x0F 241 #define HDPX_CFG_ABEBT_SHIFT 20 242 #define HDPX_CFG_ABEBT_DEFAULT 0x0A 243 #define HDPX_CFG_JAMIPG_SHIFT 24 244 #define HDPX_CFG_JAMIPG_DEFAULT 0x07 245 246 #define ALE_FRAME_SIZE 0x149C 247 248 #define ALE_WOL_CFG 0x14A0 249 #define WOL_CFG_PATTERN 0x00000001 250 #define WOL_CFG_PATTERN_ENB 0x00000002 251 #define WOL_CFG_MAGIC 0x00000004 252 #define WOL_CFG_MAGIC_ENB 0x00000008 253 #define WOL_CFG_LINK_CHG 0x00000010 254 #define WOL_CFG_LINK_CHG_ENB 0x00000020 255 #define WOL_CFG_PATTERN_DET 0x00000100 256 #define WOL_CFG_MAGIC_DET 0x00000200 257 #define WOL_CFG_LINK_CHG_DET 0x00000400 258 #define WOL_CFG_CLK_SWITCH_ENB 0x00008000 259 #define WOL_CFG_PATTERN0 0x00010000 260 #define WOL_CFG_PATTERN1 0x00020000 261 #define WOL_CFG_PATTERN2 0x00040000 262 #define WOL_CFG_PATTERN3 0x00080000 263 #define WOL_CFG_PATTERN4 0x00100000 264 #define WOL_CFG_PATTERN5 0x00200000 265 #define WOL_CFG_PATTERN6 0x00400000 266 267 /* WOL pattern length. */ 268 #define ALE_PATTERN_CFG0 0x14A4 269 #define PATTERN_CFG_0_LEN_MASK 0x0000007F 270 #define PATTERN_CFG_1_LEN_MASK 0x00007F00 271 #define PATTERN_CFG_2_LEN_MASK 0x007F0000 272 #define PATTERN_CFG_3_LEN_MASK 0x7F000000 273 274 #define ALE_PATTERN_CFG1 0x14A8 275 #define PATTERN_CFG_4_LEN_MASK 0x0000007F 276 #define PATTERN_CFG_5_LEN_MASK 0x00007F00 277 #define PATTERN_CFG_6_LEN_MASK 0x007F0000 278 279 /* RSS */ 280 #define ALE_RSS_KEY0 0x14B0 281 282 #define ALE_RSS_KEY1 0x14B4 283 284 #define ALE_RSS_KEY2 0x14B8 285 286 #define ALE_RSS_KEY3 0x14BC 287 288 #define ALE_RSS_KEY4 0x14C0 289 290 #define ALE_RSS_KEY5 0x14C4 291 292 #define ALE_RSS_KEY6 0x14C8 293 294 #define ALE_RSS_KEY7 0x14CC 295 296 #define ALE_RSS_KEY8 0x14D0 297 298 #define ALE_RSS_KEY9 0x14D4 299 300 #define ALE_RSS_IDT_TABLE4 0x14E0 301 302 #define ALE_RSS_IDT_TABLE5 0x14E4 303 304 #define ALE_RSS_IDT_TABLE6 0x14E8 305 306 #define ALE_RSS_IDT_TABLE7 0x14EC 307 308 #define ALE_SRAM_RD_ADDR 0x1500 309 310 #define ALE_SRAM_RD_LEN 0x1504 311 312 #define ALE_SRAM_RRD_ADDR 0x1508 313 314 #define ALE_SRAM_RRD_LEN 0x150C 315 316 #define ALE_SRAM_TPD_ADDR 0x1510 317 318 #define ALE_SRAM_TPD_LEN 0x1514 319 320 #define ALE_SRAM_TRD_ADDR 0x1518 321 322 #define ALE_SRAM_TRD_LEN 0x151C 323 324 #define ALE_SRAM_RX_FIFO_ADDR 0x1520 325 326 #define ALE_SRAM_RX_FIFO_LEN 0x1524 327 328 #define ALE_SRAM_TX_FIFO_ADDR 0x1528 329 330 #define ALE_SRAM_TX_FIFO_LEN 0x152C 331 332 #define ALE_SRAM_TCPH_ADDR 0x1530 333 #define SRAM_TCPH_ADDR_MASK 0x00000FFF 334 #define SRAM_PATH_ADDR_MASK 0x0FFF0000 335 #define SRAM_TCPH_ADDR_SHIFT 0 336 #define SRAM_PATH_ADDR_SHIFT 16 337 338 #define ALE_DMA_BLOCK 0x1534 339 #define DMA_BLOCK_LOAD 0x00000001 340 341 #define ALE_RXF3_ADDR_HI 0x153C 342 343 #define ALE_TPD_ADDR_HI 0x1540 344 345 #define ALE_RXF0_PAGE0_ADDR_LO 0x1544 346 347 #define ALE_RXF0_PAGE1_ADDR_LO 0x1548 348 349 #define ALE_TPD_ADDR_LO 0x154C 350 351 #define ALE_RXF1_ADDR_HI 0x1550 352 353 #define ALE_RXF2_ADDR_HI 0x1554 354 355 #define ALE_RXF_PAGE_SIZE 0x1558 356 357 #define ALE_TPD_CNT 0x155C 358 #define TPD_CNT_MASK 0x00003FF 359 #define TPD_CNT_SHIFT 0 360 361 #define ALE_RSS_IDT_TABLE0 0x1560 362 363 #define ALE_RSS_IDT_TABLE1 0x1564 364 365 #define ALE_RSS_IDT_TABLE2 0x1568 366 367 #define ALE_RSS_IDT_TABLE3 0x156C 368 369 #define ALE_RSS_HASH_VALUE 0x1570 370 371 #define ALE_RSS_HASH_FLAG 0x1574 372 373 #define ALE_RSS_CPU 0x157C 374 375 #define ALE_TXQ_CFG 0x1580 376 #define TXQ_CFG_TPD_BURST_MASK 0x0000000F 377 #define TXQ_CFG_ENB 0x00000020 378 #define TXQ_CFG_ENHANCED_MODE 0x00000040 379 #define TXQ_CFG_TX_FIFO_BURST_MASK 0xFFFF0000 380 #define TXQ_CFG_TPD_BURST_SHIFT 0 381 #define TXQ_CFG_TPD_BURST_DEFAULT 4 382 #define TXQ_CFG_TX_FIFO_BURST_SHIFT 16 383 #define TXQ_CFG_TX_FIFO_BURST_DEFAULT 256 384 385 #define ALE_TX_JUMBO_THRESH 0x1584 386 #define TX_JUMBO_THRESH_MASK 0x000007FF 387 #define TX_JUMBO_THRESH_SHIFT 0 388 #define TX_JUMBO_THRESH_UNIT 8 389 #define TX_JUMBO_THRESH_UNIT_SHIFT 3 390 391 #define ALE_RXQ_CFG 0x15A0 392 #define RXQ_CFG_ALIGN_32 0x00000000 393 #define RXQ_CFG_ALIGN_64 0x00000001 394 #define RXQ_CFG_ALIGN_128 0x00000002 395 #define RXQ_CFG_ALIGN_256 0x00000003 396 #define RXQ_CFG_QUEUE1_ENB 0x00000010 397 #define RXQ_CFG_QUEUE2_ENB 0x00000020 398 #define RXQ_CFG_QUEUE3_ENB 0x00000040 399 #define RXQ_CFG_IPV6_CSUM_VERIFY 0x00000080 400 #define RXQ_CFG_RSS_HASH_TBL_LEN_MASK 0x0000FF00 401 #define RXQ_CFG_RSS_HASH_IPV4 0x00010000 402 #define RXQ_CFG_RSS_HASH_IPV4_TCP 0x00020000 403 #define RXQ_CFG_RSS_HASH_IPV6 0x00040000 404 #define RXQ_CFG_RSS_HASH_IPV6_TCP 0x00080000 405 #define RXQ_CFG_RSS_MODE_DIS 0x00000000 406 #define RXQ_CFG_RSS_MODE_SQSINT 0x04000000 407 #define RXQ_CFG_RSS_MODE_MQUESINT 0x08000000 408 #define RXQ_CFG_RSS_MODE_MQUEMINT 0x0C000000 409 #define RXQ_CFG_NIP_QUEUE_SEL_TBL 0x10000000 410 #define RXQ_CFG_RSS_HASH_ENB 0x20000000 411 #define RXQ_CFG_CUT_THROUGH_ENB 0x40000000 412 #define RXQ_CFG_ENB 0x80000000 413 #define RXQ_CFG_RSS_HASH_TBL_LEN_SHIFT 8 414 415 #define ALE_RX_JUMBO_THRESH 0x15A4 /* 16bits */ 416 #define RX_JUMBO_THRESH_MASK 0x07FF 417 #define RX_JUMBO_LKAH_MASK 0x7800 418 #define RX_JUMBO_THRESH_MASK_SHIFT 0 419 #define RX_JUMBO_THRESH_UNIT 8 420 #define RX_JUMBO_THRESH_UNIT_SHIFT 3 421 #define RX_JUMBO_LKAH_SHIFT 11 422 #define RX_JUMBO_LKAH_DEFAULT 1 423 424 #define ALE_RX_FIFO_PAUSE_THRESH 0x15A8 425 #define RX_FIFO_PAUSE_THRESH_LO_MASK 0x00000FFF 426 #define RX_FIFO_PAUSE_THRESH_HI_MASK 0x0FFF0000 427 #define RX_FIFO_PAUSE_THRESH_LO_SHIFT 0 428 #define RX_FIFO_PAUSE_THRESH_HI_SHIFT 16 429 430 #define ALE_CMB_RXF1 0x15B4 431 432 #define ALE_CMB_RXF2 0x15B8 433 434 #define ALE_CMB_RXF3 0x15BC 435 436 #define ALE_DMA_CFG 0x15C0 437 #define DMA_CFG_IN_ORDER 0x00000001 438 #define DMA_CFG_ENH_ORDER 0x00000002 439 #define DMA_CFG_OUT_ORDER 0x00000004 440 #define DMA_CFG_RCB_64 0x00000000 441 #define DMA_CFG_RCB_128 0x00000008 442 #define DMA_CFG_RD_BURST_128 0x00000000 443 #define DMA_CFG_RD_BURST_256 0x00000010 444 #define DMA_CFG_RD_BURST_512 0x00000020 445 #define DMA_CFG_RD_BURST_1024 0x00000030 446 #define DMA_CFG_RD_BURST_2048 0x00000040 447 #define DMA_CFG_RD_BURST_4096 0x00000050 448 #define DMA_CFG_WR_BURST_128 0x00000000 449 #define DMA_CFG_WR_BURST_256 0x00000080 450 #define DMA_CFG_WR_BURST_512 0x00000100 451 #define DMA_CFG_WR_BURST_1024 0x00000180 452 #define DMA_CFG_WR_BURST_2048 0x00000200 453 #define DMA_CFG_WR_BURST_4096 0x00000280 454 #define DMA_CFG_RD_REQ_PRI 0x00000400 455 #define DMA_CFG_RD_DELAY_CNT_MASK 0x0000F800 456 #define DMA_CFG_WR_DELAY_CNT_MASK 0x000F0000 457 #define DMA_CFG_TXCMB_ENB 0x00100000 458 #define DMA_CFG_RXCMB_ENB 0x00200000 459 #define DMA_CFG_RD_BURST_MASK 0x07 460 #define DMA_CFG_RD_BURST_SHIFT 4 461 #define DMA_CFG_WR_BURST_MASK 0x07 462 #define DMA_CFG_WR_BURST_SHIFT 7 463 #define DMA_CFG_RD_DELAY_CNT_SHIFT 11 464 #define DMA_CFG_WR_DELAY_CNT_SHIFT 16 465 #define DMA_CFG_RD_DELAY_CNT_DEFAULT 15 466 #define DMA_CFG_WR_DELAY_CNT_DEFAULT 4 467 468 #define ALE_SMB_STAT_TIMER 0x15C4 469 470 #define ALE_INT_TRIG_THRESH 0x15C8 471 #define INT_TRIG_TX_THRESH_MASK 0x0000FFFF 472 #define INT_TRIG_RX_THRESH_MASK 0xFFFF0000 473 #define INT_TRIG_TX_THRESH_SHIFT 0 474 #define INT_TRIG_RX_THRESH_SHIFT 16 475 476 #define ALE_INT_TRIG_TIMER 0x15CC 477 #define INT_TRIG_TX_TIMER_MASK 0x0000FFFF 478 #define INT_TRIG_RX_TIMER_MASK 0x0000FFFF 479 #define INT_TRIG_TX_TIMER_SHIFT 0 480 #define INT_TRIG_RX_TIMER_SHIFT 16 481 482 #define ALE_RXF1_PAGE0_ADDR_LO 0x15D0 483 484 #define ALE_RXF1_PAGE1_ADDR_LO 0x15D4 485 486 #define ALE_RXF2_PAGE0_ADDR_LO 0x15D8 487 488 #define ALE_RXF2_PAGE1_ADDR_LO 0x15DC 489 490 #define ALE_RXF3_PAGE0_ADDR_LO 0x15E0 491 492 #define ALE_RXF3_PAGE1_ADDR_LO 0x15E4 493 494 #define ALE_MBOX_TPD_PROD_IDX 0x15F0 495 496 #define ALE_RXF0_PAGE0 0x15F4 497 498 #define ALE_RXF0_PAGE1 0x15F5 499 500 #define ALE_RXF1_PAGE0 0x15F6 501 502 #define ALE_RXF1_PAGE1 0x15F7 503 504 #define ALE_RXF2_PAGE0 0x15F8 505 506 #define ALE_RXF2_PAGE1 0x15F9 507 508 #define ALE_RXF3_PAGE0 0x15FA 509 510 #define ALE_RXF3_PAGE1 0x15FB 511 512 #define RXF_VALID 0x01 513 514 #define ALE_INTR_STATUS 0x1600 515 #define INTR_SMB 0x00000001 516 #define INTR_TIMER 0x00000002 517 #define INTR_MANUAL_TIMER 0x00000004 518 #define INTR_RX_FIFO_OFLOW 0x00000008 519 #define INTR_RXF0_OFLOW 0x00000010 520 #define INTR_RXF1_OFLOW 0x00000020 521 #define INTR_RXF2_OFLOW 0x00000040 522 #define INTR_RXF3_OFLOW 0x00000080 523 #define INTR_TX_FIFO_UNDERRUN 0x00000100 524 #define INTR_RX0_PAGE_FULL 0x00000200 525 #define INTR_DMA_RD_TO_RST 0x00000400 526 #define INTR_DMA_WR_TO_RST 0x00000800 527 #define INTR_GPHY 0x00001000 528 #define INTR_TX_CREDIT 0x00002000 529 #define INTR_GPHY_LOW_PW 0x00004000 530 #define INTR_RX_PKT 0x00010000 531 #define INTR_TX_PKT 0x00020000 532 #define INTR_TX_DMA 0x00040000 533 #define INTR_RX_PKT1 0x00080000 534 #define INTR_RX_PKT2 0x00100000 535 #define INTR_RX_PKT3 0x00200000 536 #define INTR_MAC_RX 0x00400000 537 #define INTR_MAC_TX 0x00800000 538 #define INTR_UNDERRUN 0x01000000 539 #define INTR_FRAME_ERROR 0x02000000 540 #define INTR_FRAME_OK 0x04000000 541 #define INTR_CSUM_ERROR 0x08000000 542 #define INTR_PHY_LINK_DOWN 0x10000000 543 #define INTR_DIS_INT 0x80000000 544 545 /* Interrupt Mask Register */ 546 #define ALE_INTR_MASK 0x1604 547 548 #define ALE_INTRS \ 549 (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST | \ 550 INTR_RX_PKT | INTR_TX_PKT | INTR_RX_FIFO_OFLOW | \ 551 INTR_TX_FIFO_UNDERRUN) 552 553 /* 554 * AR81xx requires register access to get MAC statistics 555 * and the format of statistics seems to be the same of L1 . 556 */ 557 #define ALE_RX_MIB_BASE 0x1700 558 559 #define ALE_TX_MIB_BASE 0x1760 560 561 /* Statistics counters collected by the MAC. */ 562 struct smb { 563 /* Rx stats. */ 564 uint32_t rx_frames; 565 uint32_t rx_bcast_frames; 566 uint32_t rx_mcast_frames; 567 uint32_t rx_pause_frames; 568 uint32_t rx_control_frames; 569 uint32_t rx_crcerrs; 570 uint32_t rx_lenerrs; 571 uint32_t rx_bytes; 572 uint32_t rx_runts; 573 uint32_t rx_fragments; 574 uint32_t rx_pkts_64; 575 uint32_t rx_pkts_65_127; 576 uint32_t rx_pkts_128_255; 577 uint32_t rx_pkts_256_511; 578 uint32_t rx_pkts_512_1023; 579 uint32_t rx_pkts_1024_1518; 580 uint32_t rx_pkts_1519_max; 581 uint32_t rx_pkts_truncated; 582 uint32_t rx_fifo_oflows; 583 uint32_t rx_rrs_errs; 584 uint32_t rx_alignerrs; 585 uint32_t rx_bcast_bytes; 586 uint32_t rx_mcast_bytes; 587 uint32_t rx_pkts_filtered; 588 /* Tx stats. */ 589 uint32_t tx_frames; 590 uint32_t tx_bcast_frames; 591 uint32_t tx_mcast_frames; 592 uint32_t tx_pause_frames; 593 uint32_t tx_excess_defer; 594 uint32_t tx_control_frames; 595 uint32_t tx_deferred; 596 uint32_t tx_bytes; 597 uint32_t tx_pkts_64; 598 uint32_t tx_pkts_65_127; 599 uint32_t tx_pkts_128_255; 600 uint32_t tx_pkts_256_511; 601 uint32_t tx_pkts_512_1023; 602 uint32_t tx_pkts_1024_1518; 603 uint32_t tx_pkts_1519_max; 604 uint32_t tx_single_colls; 605 uint32_t tx_multi_colls; 606 uint32_t tx_late_colls; 607 uint32_t tx_excess_colls; 608 uint32_t tx_underrun; 609 uint32_t tx_desc_underrun; 610 uint32_t tx_lenerrs; 611 uint32_t tx_pkts_truncated; 612 uint32_t tx_bcast_bytes; 613 uint32_t tx_mcast_bytes; 614 } __packed; 615 616 #define ALE_HOST_RXF0_PAGEOFF 0x1800 617 618 #define ALE_TPD_CONS_IDX 0x1804 619 620 #define ALE_HOST_RXF1_PAGEOFF 0x1808 621 622 #define ALE_HOST_RXF2_PAGEOFF 0x180C 623 624 #define ALE_HOST_RXF3_PAGEOFF 0x1810 625 626 #define ALE_RXF0_CMB0_ADDR_LO 0x1820 627 628 #define ALE_RXF0_CMB1_ADDR_LO 0x1824 629 630 #define ALE_RXF1_CMB0_ADDR_LO 0x1828 631 632 #define ALE_RXF1_CMB1_ADDR_LO 0x182C 633 634 #define ALE_RXF2_CMB0_ADDR_LO 0x1830 635 636 #define ALE_RXF2_CMB1_ADDR_LO 0x1834 637 638 #define ALE_RXF3_CMB0_ADDR_LO 0x1838 639 640 #define ALE_RXF3_CMB1_ADDR_LO 0x183C 641 642 #define ALE_TX_CMB_ADDR_LO 0x1840 643 644 #define ALE_SMB_ADDR_LO 0x1844 645 646 /* 647 * RRS(receive return status) structure. 648 * 649 * Note: 650 * Atheros AR81xx does not support descriptor based DMA on Rx 651 * instead it just prepends a Rx status structure prior to a 652 * received frame which also resides on the same Rx buffer. 653 * This means driver should copy an entire frame from the 654 * buffer to new mbuf chain which in turn greatly increases CPU 655 * cycles and effectively nullify the advantage of DMA 656 * operation of controller. So you should have fast CPU to cope 657 * with the copy operation. Implementing flow-controls may help 658 * a lot to minimize Rx FIFO overflows but it's not available 659 * yet on FreeBSD and hardware doesn't seem to support 660 * fine-grained Tx/Rx flow controls. 661 */ 662 struct rx_rs { 663 uint32_t seqno; 664 #define ALE_RD_SEQNO_MASK 0x0000FFFF 665 #define ALE_RD_HASH_MASK 0xFFFF0000 666 #define ALE_RD_SEQNO_SHIFT 0 667 #define ALE_RD_HASH_SHIFT 16 668 #define ALE_RX_SEQNO(x) \ 669 (((x) & ALE_RD_SEQNO_MASK) >> ALE_RD_SEQNO_SHIFT) 670 uint32_t length; 671 #define ALE_RD_CSUM_MASK 0x0000FFFF 672 #define ALE_RD_LEN_MASK 0x3FFF0000 673 #define ALE_RD_CPU_MASK 0xC0000000 674 #define ALE_RD_CSUM_SHIFT 0 675 #define ALE_RD_LEN_SHIFT 16 676 #define ALE_RD_CPU_SHIFT 30 677 #define ALE_RX_CSUM(x) \ 678 (((x) & ALE_RD_CSUM_MASK) >> ALE_RD_CSUM_SHIFT) 679 #define ALE_RX_BYTES(x) \ 680 (((x) & ALE_RD_LEN_MASK) >> ALE_RD_LEN_SHIFT) 681 #define ALE_RX_CPU(x) \ 682 (((x) & ALE_RD_CPU_MASK) >> ALE_RD_CPU_SHIFT) 683 uint32_t flags; 684 #define ALE_RD_RSS_IPV4 0x00000001 685 #define ALE_RD_RSS_IPV4_TCP 0x00000002 686 #define ALE_RD_RSS_IPV6 0x00000004 687 #define ALE_RD_RSS_IPV6_TCP 0x00000008 688 #define ALE_RD_IPV6 0x00000010 689 #define ALE_RD_IPV4_FRAG 0x00000020 690 #define ALE_RD_IPV4_DF 0x00000040 691 #define ALE_RD_802_3 0x00000080 692 #define ALE_RD_VLAN 0x00000100 693 #define ALE_RD_ERROR 0x00000200 694 #define ALE_RD_IPV4 0x00000400 695 #define ALE_RD_UDP 0x00000800 696 #define ALE_RD_TCP 0x00001000 697 #define ALE_RD_BCAST 0x00002000 698 #define ALE_RD_MCAST 0x00004000 699 #define ALE_RD_PAUSE 0x00008000 700 #define ALE_RD_CRC 0x00010000 701 #define ALE_RD_CODE 0x00020000 702 #define ALE_RD_DRIBBLE 0x00040000 703 #define ALE_RD_RUNT 0x00080000 704 #define ALE_RD_OFLOW 0x00100000 705 #define ALE_RD_TRUNC 0x00200000 706 #define ALE_RD_IPCSUM_NOK 0x00400000 707 #define ALE_RD_TCP_UDPCSUM_NOK 0x00800000 708 #define ALE_RD_LENGTH_NOK 0x01000000 709 #define ALE_RD_DES_ADDR_FILTERED 0x02000000 710 uint32_t vtags; 711 #define ALE_RD_HASH_HI_MASK 0x0000FFFF 712 #define ALE_RD_HASH_HI_SHIFT 0 713 #define ALE_RD_VLAN_MASK 0xFFFF0000 714 #define ALE_RD_VLAN_SHIFT 16 715 #define ALE_RX_VLAN(x) \ 716 (((x) & ALE_RD_VLAN_MASK) >> ALE_RD_VLAN_SHIFT) 717 #define ALE_RX_VLAN_TAG(x) \ 718 (((x) >> 4) | (((x) & 7) << 13) | (((x) & 8) << 9)) 719 } __packed; 720 721 /* Tx descriptor. */ 722 struct tx_desc { 723 uint64_t addr; 724 uint32_t len; 725 #define ALE_TD_VLAN_MASK 0xFFFF0000 726 #define ALE_TD_PKT_INT 0x00008000 727 #define ALE_TD_DMA_INT 0x00004000 728 #define ALE_TD_BUFLEN_MASK 0x00003FFF 729 #define ALE_TD_VLAN_SHIFT 16 730 #define ALE_TX_VLAN_TAG(x) \ 731 (((x) << 4) | ((x) >> 13) | (((x) >> 9) & 8)) 732 #define ALE_TD_BUFLEN_SHIFT 0 733 #define ALE_TX_BYTES(x) \ 734 (((x) << ALE_TD_BUFLEN_SHIFT) & ALE_TD_BUFLEN_MASK) 735 uint32_t flags; 736 #define ALE_TD_MSS 0xFFF80000 737 #define ALE_TD_TSO_HDR 0x00040000 738 #define ALE_TD_TCPHDR_LEN 0x0003C000 739 #define ALE_TD_IPHDR_LEN 0x00003C00 740 #define ALE_TD_IPV6HDR_LEN2 0x00003C00 741 #define ALE_TD_LLC_SNAP 0x00000200 742 #define ALE_TD_VLAN_TAGGED 0x00000100 743 #define ALE_TD_UDPCSUM 0x00000080 744 #define ALE_TD_TCPCSUM 0x00000040 745 #define ALE_TD_IPCSUM 0x00000020 746 #define ALE_TD_IPV6HDR_LEN1 0x000000E0 747 #define ALE_TD_TSO 0x00000010 748 #define ALE_TD_CXSUM 0x00000008 749 #define ALE_TD_INSERT_VLAN_TAG 0x00000004 750 #define ALE_TD_IPV6 0x00000002 751 #define ALE_TD_EOP 0x00000001 752 753 #define ALE_TD_CSUM_PLOADOFFSET 0x00FF0000 754 #define ALE_TD_CSUM_XSUMOFFSET 0xFF000000 755 #define ALE_TD_CSUM_XSUMOFFSET_SHIFT 24 756 #define ALE_TD_CSUM_PLOADOFFSET_SHIFT 16 757 #define ALE_TD_MSS_SHIFT 19 758 #define ALE_TD_TCPHDR_LEN_SHIFT 14 759 #define ALE_TD_IPHDR_LEN_SHIFT 10 760 } __packed; 761 762 #endif /* _IF_ALEREG_H */ 763