1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ 31 32 #include <sys/cdefs.h> 33 __FBSDID("$FreeBSD$"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/bus.h> 38 #include <sys/endian.h> 39 #include <sys/kernel.h> 40 #include <sys/malloc.h> 41 #include <sys/mbuf.h> 42 #include <sys/module.h> 43 #include <sys/rman.h> 44 #include <sys/queue.h> 45 #include <sys/socket.h> 46 #include <sys/sockio.h> 47 #include <sys/sysctl.h> 48 #include <sys/taskqueue.h> 49 50 #include <net/bpf.h> 51 #include <net/if.h> 52 #include <net/if_var.h> 53 #include <net/if_arp.h> 54 #include <net/ethernet.h> 55 #include <net/if_dl.h> 56 #include <net/if_llc.h> 57 #include <net/if_media.h> 58 #include <net/if_types.h> 59 #include <net/if_vlan_var.h> 60 61 #include <netinet/in.h> 62 #include <netinet/in_systm.h> 63 #include <netinet/ip.h> 64 #include <netinet/tcp.h> 65 66 #include <dev/mii/mii.h> 67 #include <dev/mii/miivar.h> 68 69 #include <dev/pci/pcireg.h> 70 #include <dev/pci/pcivar.h> 71 72 #include <machine/bus.h> 73 #include <machine/in_cksum.h> 74 75 #include <dev/ale/if_alereg.h> 76 #include <dev/ale/if_alevar.h> 77 78 /* "device miibus" required. See GENERIC if you get errors here. */ 79 #include "miibus_if.h" 80 81 /* For more information about Tx checksum offload issues see ale_encap(). */ 82 #define ALE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 83 84 MODULE_DEPEND(ale, pci, 1, 1, 1); 85 MODULE_DEPEND(ale, ether, 1, 1, 1); 86 MODULE_DEPEND(ale, miibus, 1, 1, 1); 87 88 /* Tunables. */ 89 static int msi_disable = 0; 90 static int msix_disable = 0; 91 TUNABLE_INT("hw.ale.msi_disable", &msi_disable); 92 TUNABLE_INT("hw.ale.msix_disable", &msix_disable); 93 94 /* 95 * Devices supported by this driver. 96 */ 97 static const struct ale_dev { 98 uint16_t ale_vendorid; 99 uint16_t ale_deviceid; 100 const char *ale_name; 101 } ale_devs[] = { 102 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR81XX, 103 "Atheros AR8121/AR8113/AR8114 PCIe Ethernet" }, 104 }; 105 106 static int ale_attach(device_t); 107 static int ale_check_boundary(struct ale_softc *); 108 static int ale_detach(device_t); 109 static int ale_dma_alloc(struct ale_softc *); 110 static void ale_dma_free(struct ale_softc *); 111 static void ale_dmamap_cb(void *, bus_dma_segment_t *, int, int); 112 static int ale_encap(struct ale_softc *, struct mbuf **); 113 static void ale_get_macaddr(struct ale_softc *); 114 static void ale_init(void *); 115 static void ale_init_locked(struct ale_softc *); 116 static void ale_init_rx_pages(struct ale_softc *); 117 static void ale_init_tx_ring(struct ale_softc *); 118 static void ale_int_task(void *, int); 119 static int ale_intr(void *); 120 static int ale_ioctl(if_t, u_long, caddr_t); 121 static void ale_mac_config(struct ale_softc *); 122 static int ale_miibus_readreg(device_t, int, int); 123 static void ale_miibus_statchg(device_t); 124 static int ale_miibus_writereg(device_t, int, int, int); 125 static int ale_mediachange(if_t); 126 static void ale_mediastatus(if_t, struct ifmediareq *); 127 static void ale_phy_reset(struct ale_softc *); 128 static int ale_probe(device_t); 129 static void ale_reset(struct ale_softc *); 130 static int ale_resume(device_t); 131 static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, 132 uint32_t, uint32_t *); 133 static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); 134 static int ale_rxeof(struct ale_softc *sc, int); 135 static void ale_rxfilter(struct ale_softc *); 136 static void ale_rxvlan(struct ale_softc *); 137 static void ale_setlinkspeed(struct ale_softc *); 138 static void ale_setwol(struct ale_softc *); 139 static int ale_shutdown(device_t); 140 static void ale_start(if_t); 141 static void ale_start_locked(if_t); 142 static void ale_stats_clear(struct ale_softc *); 143 static void ale_stats_update(struct ale_softc *); 144 static void ale_stop(struct ale_softc *); 145 static void ale_stop_mac(struct ale_softc *); 146 static int ale_suspend(device_t); 147 static void ale_sysctl_node(struct ale_softc *); 148 static void ale_tick(void *); 149 static void ale_txeof(struct ale_softc *); 150 static void ale_watchdog(struct ale_softc *); 151 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 152 static int sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS); 153 static int sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS); 154 155 static device_method_t ale_methods[] = { 156 /* Device interface. */ 157 DEVMETHOD(device_probe, ale_probe), 158 DEVMETHOD(device_attach, ale_attach), 159 DEVMETHOD(device_detach, ale_detach), 160 DEVMETHOD(device_shutdown, ale_shutdown), 161 DEVMETHOD(device_suspend, ale_suspend), 162 DEVMETHOD(device_resume, ale_resume), 163 164 /* MII interface. */ 165 DEVMETHOD(miibus_readreg, ale_miibus_readreg), 166 DEVMETHOD(miibus_writereg, ale_miibus_writereg), 167 DEVMETHOD(miibus_statchg, ale_miibus_statchg), 168 169 DEVMETHOD_END 170 }; 171 172 static driver_t ale_driver = { 173 "ale", 174 ale_methods, 175 sizeof(struct ale_softc) 176 }; 177 178 DRIVER_MODULE(ale, pci, ale_driver, NULL, NULL); 179 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, ale, ale_devs, 180 nitems(ale_devs)); 181 DRIVER_MODULE(miibus, ale, miibus_driver, NULL, NULL); 182 183 static struct resource_spec ale_res_spec_mem[] = { 184 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 185 { -1, 0, 0 } 186 }; 187 188 static struct resource_spec ale_irq_spec_legacy[] = { 189 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 190 { -1, 0, 0 } 191 }; 192 193 static struct resource_spec ale_irq_spec_msi[] = { 194 { SYS_RES_IRQ, 1, RF_ACTIVE }, 195 { -1, 0, 0 } 196 }; 197 198 static struct resource_spec ale_irq_spec_msix[] = { 199 { SYS_RES_IRQ, 1, RF_ACTIVE }, 200 { -1, 0, 0 } 201 }; 202 203 static int 204 ale_miibus_readreg(device_t dev, int phy, int reg) 205 { 206 struct ale_softc *sc; 207 uint32_t v; 208 int i; 209 210 sc = device_get_softc(dev); 211 212 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 213 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 214 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 215 DELAY(5); 216 v = CSR_READ_4(sc, ALE_MDIO); 217 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 218 break; 219 } 220 221 if (i == 0) { 222 device_printf(sc->ale_dev, "phy read timeout : %d\n", reg); 223 return (0); 224 } 225 226 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 227 } 228 229 static int 230 ale_miibus_writereg(device_t dev, int phy, int reg, int val) 231 { 232 struct ale_softc *sc; 233 uint32_t v; 234 int i; 235 236 sc = device_get_softc(dev); 237 238 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 239 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 240 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 241 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 242 DELAY(5); 243 v = CSR_READ_4(sc, ALE_MDIO); 244 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 245 break; 246 } 247 248 if (i == 0) 249 device_printf(sc->ale_dev, "phy write timeout : %d\n", reg); 250 251 return (0); 252 } 253 254 static void 255 ale_miibus_statchg(device_t dev) 256 { 257 struct ale_softc *sc; 258 struct mii_data *mii; 259 if_t ifp; 260 uint32_t reg; 261 262 sc = device_get_softc(dev); 263 mii = device_get_softc(sc->ale_miibus); 264 ifp = sc->ale_ifp; 265 if (mii == NULL || ifp == NULL || 266 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 267 return; 268 269 sc->ale_flags &= ~ALE_FLAG_LINK; 270 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 271 (IFM_ACTIVE | IFM_AVALID)) { 272 switch (IFM_SUBTYPE(mii->mii_media_active)) { 273 case IFM_10_T: 274 case IFM_100_TX: 275 sc->ale_flags |= ALE_FLAG_LINK; 276 break; 277 case IFM_1000_T: 278 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 279 sc->ale_flags |= ALE_FLAG_LINK; 280 break; 281 default: 282 break; 283 } 284 } 285 286 /* Stop Rx/Tx MACs. */ 287 ale_stop_mac(sc); 288 289 /* Program MACs with resolved speed/duplex/flow-control. */ 290 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { 291 ale_mac_config(sc); 292 /* Reenable Tx/Rx MACs. */ 293 reg = CSR_READ_4(sc, ALE_MAC_CFG); 294 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 295 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 296 } 297 } 298 299 static void 300 ale_mediastatus(if_t ifp, struct ifmediareq *ifmr) 301 { 302 struct ale_softc *sc; 303 struct mii_data *mii; 304 305 sc = if_getsoftc(ifp); 306 ALE_LOCK(sc); 307 if ((if_getflags(ifp) & IFF_UP) == 0) { 308 ALE_UNLOCK(sc); 309 return; 310 } 311 mii = device_get_softc(sc->ale_miibus); 312 313 mii_pollstat(mii); 314 ifmr->ifm_status = mii->mii_media_status; 315 ifmr->ifm_active = mii->mii_media_active; 316 ALE_UNLOCK(sc); 317 } 318 319 static int 320 ale_mediachange(if_t ifp) 321 { 322 struct ale_softc *sc; 323 struct mii_data *mii; 324 struct mii_softc *miisc; 325 int error; 326 327 sc = if_getsoftc(ifp); 328 ALE_LOCK(sc); 329 mii = device_get_softc(sc->ale_miibus); 330 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 331 PHY_RESET(miisc); 332 error = mii_mediachg(mii); 333 ALE_UNLOCK(sc); 334 335 return (error); 336 } 337 338 static int 339 ale_probe(device_t dev) 340 { 341 const struct ale_dev *sp; 342 int i; 343 uint16_t vendor, devid; 344 345 vendor = pci_get_vendor(dev); 346 devid = pci_get_device(dev); 347 sp = ale_devs; 348 for (i = 0; i < nitems(ale_devs); i++) { 349 if (vendor == sp->ale_vendorid && 350 devid == sp->ale_deviceid) { 351 device_set_desc(dev, sp->ale_name); 352 return (BUS_PROBE_DEFAULT); 353 } 354 sp++; 355 } 356 357 return (ENXIO); 358 } 359 360 static void 361 ale_get_macaddr(struct ale_softc *sc) 362 { 363 uint32_t ea[2], reg; 364 int i, vpdc; 365 366 reg = CSR_READ_4(sc, ALE_SPI_CTRL); 367 if ((reg & SPI_VPD_ENB) != 0) { 368 reg &= ~SPI_VPD_ENB; 369 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); 370 } 371 372 if (pci_find_cap(sc->ale_dev, PCIY_VPD, &vpdc) == 0) { 373 /* 374 * PCI VPD capability found, let TWSI reload EEPROM. 375 * This will set ethernet address of controller. 376 */ 377 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | 378 TWSI_CTRL_SW_LD_START); 379 for (i = 100; i > 0; i--) { 380 DELAY(1000); 381 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); 382 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 383 break; 384 } 385 if (i == 0) 386 device_printf(sc->ale_dev, 387 "reloading EEPROM timeout!\n"); 388 } else { 389 if (bootverbose) 390 device_printf(sc->ale_dev, 391 "PCI VPD capability not found!\n"); 392 } 393 394 ea[0] = CSR_READ_4(sc, ALE_PAR0); 395 ea[1] = CSR_READ_4(sc, ALE_PAR1); 396 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; 397 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; 398 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; 399 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; 400 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; 401 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; 402 } 403 404 static void 405 ale_phy_reset(struct ale_softc *sc) 406 { 407 408 /* Reset magic from Linux. */ 409 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 410 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 411 GPHY_CTRL_PHY_PLL_ON); 412 DELAY(1000); 413 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 414 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | 415 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); 416 DELAY(1000); 417 418 #define ATPHY_DBG_ADDR 0x1D 419 #define ATPHY_DBG_DATA 0x1E 420 421 /* Enable hibernation mode. */ 422 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 423 ATPHY_DBG_ADDR, 0x0B); 424 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 425 ATPHY_DBG_DATA, 0xBC00); 426 /* Set Class A/B for all modes. */ 427 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 428 ATPHY_DBG_ADDR, 0x00); 429 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 430 ATPHY_DBG_DATA, 0x02EF); 431 /* Enable 10BT power saving. */ 432 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 433 ATPHY_DBG_ADDR, 0x12); 434 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 435 ATPHY_DBG_DATA, 0x4C04); 436 /* Adjust 1000T power. */ 437 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 438 ATPHY_DBG_ADDR, 0x04); 439 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 440 ATPHY_DBG_ADDR, 0x8BBB); 441 /* 10BT center tap voltage. */ 442 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 443 ATPHY_DBG_ADDR, 0x05); 444 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 445 ATPHY_DBG_ADDR, 0x2C46); 446 447 #undef ATPHY_DBG_ADDR 448 #undef ATPHY_DBG_DATA 449 DELAY(1000); 450 } 451 452 static int 453 ale_attach(device_t dev) 454 { 455 struct ale_softc *sc; 456 if_t ifp; 457 uint16_t burst; 458 int error, i, msic, msixc, pmc; 459 uint32_t rxf_len, txf_len; 460 461 error = 0; 462 sc = device_get_softc(dev); 463 sc->ale_dev = dev; 464 465 mtx_init(&sc->ale_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 466 MTX_DEF); 467 callout_init_mtx(&sc->ale_tick_ch, &sc->ale_mtx, 0); 468 NET_TASK_INIT(&sc->ale_int_task, 0, ale_int_task, sc); 469 470 /* Map the device. */ 471 pci_enable_busmaster(dev); 472 sc->ale_res_spec = ale_res_spec_mem; 473 sc->ale_irq_spec = ale_irq_spec_legacy; 474 error = bus_alloc_resources(dev, sc->ale_res_spec, sc->ale_res); 475 if (error != 0) { 476 device_printf(dev, "cannot allocate memory resources.\n"); 477 goto fail; 478 } 479 480 /* Set PHY address. */ 481 sc->ale_phyaddr = ALE_PHY_ADDR; 482 483 /* Reset PHY. */ 484 ale_phy_reset(sc); 485 486 /* Reset the ethernet controller. */ 487 ale_reset(sc); 488 489 /* Get PCI and chip id/revision. */ 490 sc->ale_rev = pci_get_revid(dev); 491 if (sc->ale_rev >= 0xF0) { 492 /* L2E Rev. B. AR8114 */ 493 sc->ale_flags |= ALE_FLAG_FASTETHER; 494 } else { 495 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { 496 /* L1E AR8121 */ 497 sc->ale_flags |= ALE_FLAG_JUMBO; 498 } else { 499 /* L2E Rev. A. AR8113 */ 500 sc->ale_flags |= ALE_FLAG_FASTETHER; 501 } 502 } 503 /* 504 * All known controllers seems to require 4 bytes alignment 505 * of Tx buffers to make Tx checksum offload with custom 506 * checksum generation method work. 507 */ 508 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; 509 /* 510 * All known controllers seems to have issues on Rx checksum 511 * offload for fragmented IP datagrams. 512 */ 513 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; 514 /* 515 * Don't use Tx CMB. It is known to cause RRS update failure 516 * under certain circumstances. Typical phenomenon of the 517 * issue would be unexpected sequence number encountered in 518 * Rx handler. 519 */ 520 sc->ale_flags |= ALE_FLAG_TXCMB_BUG; 521 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> 522 MASTER_CHIP_REV_SHIFT; 523 if (bootverbose) { 524 device_printf(dev, "PCI device revision : 0x%04x\n", 525 sc->ale_rev); 526 device_printf(dev, "Chip id/revision : 0x%04x\n", 527 sc->ale_chip_rev); 528 } 529 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); 530 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 531 /* 532 * Uninitialized hardware returns an invalid chip id/revision 533 * as well as 0xFFFFFFFF for Tx/Rx fifo length. 534 */ 535 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || 536 rxf_len == 0xFFFFFFF) { 537 device_printf(dev,"chip revision : 0x%04x, %u Tx FIFO " 538 "%u Rx FIFO -- not initialized?\n", sc->ale_chip_rev, 539 txf_len, rxf_len); 540 error = ENXIO; 541 goto fail; 542 } 543 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", txf_len, rxf_len); 544 545 /* Allocate IRQ resources. */ 546 msixc = pci_msix_count(dev); 547 msic = pci_msi_count(dev); 548 if (bootverbose) { 549 device_printf(dev, "MSIX count : %d\n", msixc); 550 device_printf(dev, "MSI count : %d\n", msic); 551 } 552 553 /* Prefer MSIX over MSI. */ 554 if (msix_disable == 0 || msi_disable == 0) { 555 if (msix_disable == 0 && msixc == ALE_MSIX_MESSAGES && 556 pci_alloc_msix(dev, &msixc) == 0) { 557 if (msixc == ALE_MSIX_MESSAGES) { 558 device_printf(dev, "Using %d MSIX messages.\n", 559 msixc); 560 sc->ale_flags |= ALE_FLAG_MSIX; 561 sc->ale_irq_spec = ale_irq_spec_msix; 562 } else 563 pci_release_msi(dev); 564 } 565 if (msi_disable == 0 && (sc->ale_flags & ALE_FLAG_MSIX) == 0 && 566 msic == ALE_MSI_MESSAGES && 567 pci_alloc_msi(dev, &msic) == 0) { 568 if (msic == ALE_MSI_MESSAGES) { 569 device_printf(dev, "Using %d MSI messages.\n", 570 msic); 571 sc->ale_flags |= ALE_FLAG_MSI; 572 sc->ale_irq_spec = ale_irq_spec_msi; 573 } else 574 pci_release_msi(dev); 575 } 576 } 577 578 error = bus_alloc_resources(dev, sc->ale_irq_spec, sc->ale_irq); 579 if (error != 0) { 580 device_printf(dev, "cannot allocate IRQ resources.\n"); 581 goto fail; 582 } 583 584 /* Get DMA parameters from PCIe device control register. */ 585 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 586 sc->ale_flags |= ALE_FLAG_PCIE; 587 burst = pci_read_config(dev, i + 0x08, 2); 588 /* Max read request size. */ 589 sc->ale_dma_rd_burst = ((burst >> 12) & 0x07) << 590 DMA_CFG_RD_BURST_SHIFT; 591 /* Max payload size. */ 592 sc->ale_dma_wr_burst = ((burst >> 5) & 0x07) << 593 DMA_CFG_WR_BURST_SHIFT; 594 if (bootverbose) { 595 device_printf(dev, "Read request size : %d bytes.\n", 596 128 << ((burst >> 12) & 0x07)); 597 device_printf(dev, "TLP payload size : %d bytes.\n", 598 128 << ((burst >> 5) & 0x07)); 599 } 600 } else { 601 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; 602 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; 603 } 604 605 /* Create device sysctl node. */ 606 ale_sysctl_node(sc); 607 608 if ((error = ale_dma_alloc(sc)) != 0) 609 goto fail; 610 611 /* Load station address. */ 612 ale_get_macaddr(sc); 613 614 ifp = sc->ale_ifp = if_alloc(IFT_ETHER); 615 if (ifp == NULL) { 616 device_printf(dev, "cannot allocate ifnet structure.\n"); 617 error = ENXIO; 618 goto fail; 619 } 620 621 if_setsoftc(ifp, sc); 622 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 623 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 624 if_setioctlfn(ifp, ale_ioctl); 625 if_setstartfn(ifp, ale_start); 626 if_setinitfn(ifp, ale_init); 627 if_setsendqlen(ifp, ALE_TX_RING_CNT - 1); 628 if_setsendqready(ifp); 629 if_setcapabilities(ifp, IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4); 630 if_sethwassist(ifp, ALE_CSUM_FEATURES | CSUM_TSO); 631 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { 632 sc->ale_flags |= ALE_FLAG_PMCAP; 633 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST, 0); 634 } 635 if_setcapenable(ifp, if_getcapabilities(ifp)); 636 637 /* Set up MII bus. */ 638 error = mii_attach(dev, &sc->ale_miibus, ifp, ale_mediachange, 639 ale_mediastatus, BMSR_DEFCAPMASK, sc->ale_phyaddr, MII_OFFSET_ANY, 640 MIIF_DOPAUSE); 641 if (error != 0) { 642 device_printf(dev, "attaching PHYs failed\n"); 643 goto fail; 644 } 645 646 ether_ifattach(ifp, sc->ale_eaddr); 647 648 /* VLAN capability setup. */ 649 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 650 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0); 651 if_setcapenable(ifp, if_getcapabilities(ifp)); 652 /* 653 * Even though controllers supported by ale(3) have Rx checksum 654 * offload bug the workaround for fragmented frames seemed to 655 * work so far. However it seems Rx checksum offload does not 656 * work under certain conditions. So disable Rx checksum offload 657 * until I find more clue about it but allow users to override it. 658 */ 659 if_setcapenablebit(ifp, 0, IFCAP_RXCSUM); 660 661 /* Tell the upper layer(s) we support long frames. */ 662 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 663 664 /* Create local taskq. */ 665 sc->ale_tq = taskqueue_create_fast("ale_taskq", M_WAITOK, 666 taskqueue_thread_enqueue, &sc->ale_tq); 667 if (sc->ale_tq == NULL) { 668 device_printf(dev, "could not create taskqueue.\n"); 669 ether_ifdetach(ifp); 670 error = ENXIO; 671 goto fail; 672 } 673 taskqueue_start_threads(&sc->ale_tq, 1, PI_NET, "%s taskq", 674 device_get_nameunit(sc->ale_dev)); 675 676 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 677 msic = ALE_MSIX_MESSAGES; 678 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 679 msic = ALE_MSI_MESSAGES; 680 else 681 msic = 1; 682 for (i = 0; i < msic; i++) { 683 error = bus_setup_intr(dev, sc->ale_irq[i], 684 INTR_TYPE_NET | INTR_MPSAFE, ale_intr, NULL, sc, 685 &sc->ale_intrhand[i]); 686 if (error != 0) 687 break; 688 } 689 if (error != 0) { 690 device_printf(dev, "could not set up interrupt handler.\n"); 691 taskqueue_free(sc->ale_tq); 692 sc->ale_tq = NULL; 693 ether_ifdetach(ifp); 694 goto fail; 695 } 696 697 fail: 698 if (error != 0) 699 ale_detach(dev); 700 701 return (error); 702 } 703 704 static int 705 ale_detach(device_t dev) 706 { 707 struct ale_softc *sc; 708 if_t ifp; 709 int i, msic; 710 711 sc = device_get_softc(dev); 712 713 ifp = sc->ale_ifp; 714 if (device_is_attached(dev)) { 715 ether_ifdetach(ifp); 716 ALE_LOCK(sc); 717 ale_stop(sc); 718 ALE_UNLOCK(sc); 719 callout_drain(&sc->ale_tick_ch); 720 taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 721 } 722 723 if (sc->ale_tq != NULL) { 724 taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 725 taskqueue_free(sc->ale_tq); 726 sc->ale_tq = NULL; 727 } 728 729 if (sc->ale_miibus != NULL) { 730 device_delete_child(dev, sc->ale_miibus); 731 sc->ale_miibus = NULL; 732 } 733 bus_generic_detach(dev); 734 ale_dma_free(sc); 735 736 if (ifp != NULL) { 737 if_free(ifp); 738 sc->ale_ifp = NULL; 739 } 740 741 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 742 msic = ALE_MSIX_MESSAGES; 743 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 744 msic = ALE_MSI_MESSAGES; 745 else 746 msic = 1; 747 for (i = 0; i < msic; i++) { 748 if (sc->ale_intrhand[i] != NULL) { 749 bus_teardown_intr(dev, sc->ale_irq[i], 750 sc->ale_intrhand[i]); 751 sc->ale_intrhand[i] = NULL; 752 } 753 } 754 755 bus_release_resources(dev, sc->ale_irq_spec, sc->ale_irq); 756 if ((sc->ale_flags & (ALE_FLAG_MSI | ALE_FLAG_MSIX)) != 0) 757 pci_release_msi(dev); 758 bus_release_resources(dev, sc->ale_res_spec, sc->ale_res); 759 mtx_destroy(&sc->ale_mtx); 760 761 return (0); 762 } 763 764 #define ALE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 765 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 766 767 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 768 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 769 770 static void 771 ale_sysctl_node(struct ale_softc *sc) 772 { 773 struct sysctl_ctx_list *ctx; 774 struct sysctl_oid_list *child, *parent; 775 struct sysctl_oid *tree; 776 struct ale_hw_stats *stats; 777 int error; 778 779 stats = &sc->ale_stats; 780 ctx = device_get_sysctl_ctx(sc->ale_dev); 781 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ale_dev)); 782 783 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 784 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->ale_int_rx_mod, 785 0, sysctl_hw_ale_int_mod, "I", "ale Rx interrupt moderation"); 786 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 787 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->ale_int_tx_mod, 788 0, sysctl_hw_ale_int_mod, "I", "ale Tx interrupt moderation"); 789 /* Pull in device tunables. */ 790 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 791 error = resource_int_value(device_get_name(sc->ale_dev), 792 device_get_unit(sc->ale_dev), "int_rx_mod", &sc->ale_int_rx_mod); 793 if (error == 0) { 794 if (sc->ale_int_rx_mod < ALE_IM_TIMER_MIN || 795 sc->ale_int_rx_mod > ALE_IM_TIMER_MAX) { 796 device_printf(sc->ale_dev, "int_rx_mod value out of " 797 "range; using default: %d\n", 798 ALE_IM_RX_TIMER_DEFAULT); 799 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 800 } 801 } 802 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 803 error = resource_int_value(device_get_name(sc->ale_dev), 804 device_get_unit(sc->ale_dev), "int_tx_mod", &sc->ale_int_tx_mod); 805 if (error == 0) { 806 if (sc->ale_int_tx_mod < ALE_IM_TIMER_MIN || 807 sc->ale_int_tx_mod > ALE_IM_TIMER_MAX) { 808 device_printf(sc->ale_dev, "int_tx_mod value out of " 809 "range; using default: %d\n", 810 ALE_IM_TX_TIMER_DEFAULT); 811 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 812 } 813 } 814 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 815 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 816 &sc->ale_process_limit, 0, sysctl_hw_ale_proc_limit, "I", 817 "max number of Rx events to process"); 818 /* Pull in device tunables. */ 819 sc->ale_process_limit = ALE_PROC_DEFAULT; 820 error = resource_int_value(device_get_name(sc->ale_dev), 821 device_get_unit(sc->ale_dev), "process_limit", 822 &sc->ale_process_limit); 823 if (error == 0) { 824 if (sc->ale_process_limit < ALE_PROC_MIN || 825 sc->ale_process_limit > ALE_PROC_MAX) { 826 device_printf(sc->ale_dev, 827 "process_limit value out of range; " 828 "using default: %d\n", ALE_PROC_DEFAULT); 829 sc->ale_process_limit = ALE_PROC_DEFAULT; 830 } 831 } 832 833 /* Misc statistics. */ 834 ALE_SYSCTL_STAT_ADD32(ctx, child, "reset_brk_seq", 835 &stats->reset_brk_seq, 836 "Controller resets due to broken Rx sequnce number"); 837 838 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 839 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ATE statistics"); 840 parent = SYSCTL_CHILDREN(tree); 841 842 /* Rx statistics. */ 843 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 844 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics"); 845 child = SYSCTL_CHILDREN(tree); 846 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 847 &stats->rx_frames, "Good frames"); 848 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 849 &stats->rx_bcast_frames, "Good broadcast frames"); 850 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 851 &stats->rx_mcast_frames, "Good multicast frames"); 852 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 853 &stats->rx_pause_frames, "Pause control frames"); 854 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 855 &stats->rx_control_frames, "Control frames"); 856 ALE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 857 &stats->rx_crcerrs, "CRC errors"); 858 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 859 &stats->rx_lenerrs, "Frames with length mismatched"); 860 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 861 &stats->rx_bytes, "Good octets"); 862 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 863 &stats->rx_bcast_bytes, "Good broadcast octets"); 864 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 865 &stats->rx_mcast_bytes, "Good multicast octets"); 866 ALE_SYSCTL_STAT_ADD32(ctx, child, "runts", 867 &stats->rx_runts, "Too short frames"); 868 ALE_SYSCTL_STAT_ADD32(ctx, child, "fragments", 869 &stats->rx_fragments, "Fragmented frames"); 870 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 871 &stats->rx_pkts_64, "64 bytes frames"); 872 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 873 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 874 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 875 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 876 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 877 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 878 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 879 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 880 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 881 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 882 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 883 &stats->rx_pkts_1519_max, "1519 to max frames"); 884 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 885 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 886 ALE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 887 &stats->rx_fifo_oflows, "FIFO overflows"); 888 ALE_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 889 &stats->rx_rrs_errs, "Return status write-back errors"); 890 ALE_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 891 &stats->rx_alignerrs, "Alignment errors"); 892 ALE_SYSCTL_STAT_ADD32(ctx, child, "filtered", 893 &stats->rx_pkts_filtered, 894 "Frames dropped due to address filtering"); 895 896 /* Tx statistics. */ 897 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 898 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics"); 899 child = SYSCTL_CHILDREN(tree); 900 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 901 &stats->tx_frames, "Good frames"); 902 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 903 &stats->tx_bcast_frames, "Good broadcast frames"); 904 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 905 &stats->tx_mcast_frames, "Good multicast frames"); 906 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 907 &stats->tx_pause_frames, "Pause control frames"); 908 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 909 &stats->tx_control_frames, "Control frames"); 910 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 911 &stats->tx_excess_defer, "Frames with excessive derferrals"); 912 ALE_SYSCTL_STAT_ADD32(ctx, child, "defers", 913 &stats->tx_excess_defer, "Frames with derferrals"); 914 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 915 &stats->tx_bytes, "Good octets"); 916 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 917 &stats->tx_bcast_bytes, "Good broadcast octets"); 918 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 919 &stats->tx_mcast_bytes, "Good multicast octets"); 920 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 921 &stats->tx_pkts_64, "64 bytes frames"); 922 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 923 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 924 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 925 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 926 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 927 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 928 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 929 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 930 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 931 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 932 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 933 &stats->tx_pkts_1519_max, "1519 to max frames"); 934 ALE_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 935 &stats->tx_single_colls, "Single collisions"); 936 ALE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 937 &stats->tx_multi_colls, "Multiple collisions"); 938 ALE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 939 &stats->tx_late_colls, "Late collisions"); 940 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 941 &stats->tx_excess_colls, "Excessive collisions"); 942 ALE_SYSCTL_STAT_ADD32(ctx, child, "underruns", 943 &stats->tx_underrun, "FIFO underruns"); 944 ALE_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 945 &stats->tx_desc_underrun, "Descriptor write-back errors"); 946 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 947 &stats->tx_lenerrs, "Frames with length mismatched"); 948 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 949 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 950 } 951 952 #undef ALE_SYSCTL_STAT_ADD32 953 #undef ALE_SYSCTL_STAT_ADD64 954 955 struct ale_dmamap_arg { 956 bus_addr_t ale_busaddr; 957 }; 958 959 static void 960 ale_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 961 { 962 struct ale_dmamap_arg *ctx; 963 964 if (error != 0) 965 return; 966 967 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 968 969 ctx = (struct ale_dmamap_arg *)arg; 970 ctx->ale_busaddr = segs[0].ds_addr; 971 } 972 973 /* 974 * Tx descriptors/RXF0/CMB DMA blocks share ALE_DESC_ADDR_HI register 975 * which specifies high address region of DMA blocks. Therefore these 976 * blocks should have the same high address of given 4GB address 977 * space(i.e. crossing 4GB boundary is not allowed). 978 */ 979 static int 980 ale_check_boundary(struct ale_softc *sc) 981 { 982 bus_addr_t rx_cmb_end[ALE_RX_PAGES], tx_cmb_end; 983 bus_addr_t rx_page_end[ALE_RX_PAGES], tx_ring_end; 984 985 rx_page_end[0] = sc->ale_cdata.ale_rx_page[0].page_paddr + 986 sc->ale_pagesize; 987 rx_page_end[1] = sc->ale_cdata.ale_rx_page[1].page_paddr + 988 sc->ale_pagesize; 989 tx_ring_end = sc->ale_cdata.ale_tx_ring_paddr + ALE_TX_RING_SZ; 990 tx_cmb_end = sc->ale_cdata.ale_tx_cmb_paddr + ALE_TX_CMB_SZ; 991 rx_cmb_end[0] = sc->ale_cdata.ale_rx_page[0].cmb_paddr + ALE_RX_CMB_SZ; 992 rx_cmb_end[1] = sc->ale_cdata.ale_rx_page[1].cmb_paddr + ALE_RX_CMB_SZ; 993 994 if ((ALE_ADDR_HI(tx_ring_end) != 995 ALE_ADDR_HI(sc->ale_cdata.ale_tx_ring_paddr)) || 996 (ALE_ADDR_HI(rx_page_end[0]) != 997 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].page_paddr)) || 998 (ALE_ADDR_HI(rx_page_end[1]) != 999 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].page_paddr)) || 1000 (ALE_ADDR_HI(tx_cmb_end) != 1001 ALE_ADDR_HI(sc->ale_cdata.ale_tx_cmb_paddr)) || 1002 (ALE_ADDR_HI(rx_cmb_end[0]) != 1003 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].cmb_paddr)) || 1004 (ALE_ADDR_HI(rx_cmb_end[1]) != 1005 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].cmb_paddr))) 1006 return (EFBIG); 1007 1008 if ((ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[0])) || 1009 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[1])) || 1010 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[0])) || 1011 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[1])) || 1012 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(tx_cmb_end))) 1013 return (EFBIG); 1014 1015 return (0); 1016 } 1017 1018 static int 1019 ale_dma_alloc(struct ale_softc *sc) 1020 { 1021 struct ale_txdesc *txd; 1022 bus_addr_t lowaddr; 1023 struct ale_dmamap_arg ctx; 1024 int error, guard_size, i; 1025 1026 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 1027 guard_size = ALE_JUMBO_FRAMELEN; 1028 else 1029 guard_size = ALE_MAX_FRAMELEN; 1030 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, 1031 ALE_RX_PAGE_ALIGN); 1032 lowaddr = BUS_SPACE_MAXADDR; 1033 again: 1034 /* Create parent DMA tag. */ 1035 error = bus_dma_tag_create( 1036 bus_get_dma_tag(sc->ale_dev), /* parent */ 1037 1, 0, /* alignment, boundary */ 1038 lowaddr, /* lowaddr */ 1039 BUS_SPACE_MAXADDR, /* highaddr */ 1040 NULL, NULL, /* filter, filterarg */ 1041 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1042 0, /* nsegments */ 1043 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1044 0, /* flags */ 1045 NULL, NULL, /* lockfunc, lockarg */ 1046 &sc->ale_cdata.ale_parent_tag); 1047 if (error != 0) { 1048 device_printf(sc->ale_dev, 1049 "could not create parent DMA tag.\n"); 1050 goto fail; 1051 } 1052 1053 /* Create DMA tag for Tx descriptor ring. */ 1054 error = bus_dma_tag_create( 1055 sc->ale_cdata.ale_parent_tag, /* parent */ 1056 ALE_TX_RING_ALIGN, 0, /* alignment, boundary */ 1057 BUS_SPACE_MAXADDR, /* lowaddr */ 1058 BUS_SPACE_MAXADDR, /* highaddr */ 1059 NULL, NULL, /* filter, filterarg */ 1060 ALE_TX_RING_SZ, /* maxsize */ 1061 1, /* nsegments */ 1062 ALE_TX_RING_SZ, /* maxsegsize */ 1063 0, /* flags */ 1064 NULL, NULL, /* lockfunc, lockarg */ 1065 &sc->ale_cdata.ale_tx_ring_tag); 1066 if (error != 0) { 1067 device_printf(sc->ale_dev, 1068 "could not create Tx ring DMA tag.\n"); 1069 goto fail; 1070 } 1071 1072 /* Create DMA tag for Rx pages. */ 1073 for (i = 0; i < ALE_RX_PAGES; i++) { 1074 error = bus_dma_tag_create( 1075 sc->ale_cdata.ale_parent_tag, /* parent */ 1076 ALE_RX_PAGE_ALIGN, 0, /* alignment, boundary */ 1077 BUS_SPACE_MAXADDR, /* lowaddr */ 1078 BUS_SPACE_MAXADDR, /* highaddr */ 1079 NULL, NULL, /* filter, filterarg */ 1080 sc->ale_pagesize, /* maxsize */ 1081 1, /* nsegments */ 1082 sc->ale_pagesize, /* maxsegsize */ 1083 0, /* flags */ 1084 NULL, NULL, /* lockfunc, lockarg */ 1085 &sc->ale_cdata.ale_rx_page[i].page_tag); 1086 if (error != 0) { 1087 device_printf(sc->ale_dev, 1088 "could not create Rx page %d DMA tag.\n", i); 1089 goto fail; 1090 } 1091 } 1092 1093 /* Create DMA tag for Tx coalescing message block. */ 1094 error = bus_dma_tag_create( 1095 sc->ale_cdata.ale_parent_tag, /* parent */ 1096 ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1097 BUS_SPACE_MAXADDR, /* lowaddr */ 1098 BUS_SPACE_MAXADDR, /* highaddr */ 1099 NULL, NULL, /* filter, filterarg */ 1100 ALE_TX_CMB_SZ, /* maxsize */ 1101 1, /* nsegments */ 1102 ALE_TX_CMB_SZ, /* maxsegsize */ 1103 0, /* flags */ 1104 NULL, NULL, /* lockfunc, lockarg */ 1105 &sc->ale_cdata.ale_tx_cmb_tag); 1106 if (error != 0) { 1107 device_printf(sc->ale_dev, 1108 "could not create Tx CMB DMA tag.\n"); 1109 goto fail; 1110 } 1111 1112 /* Create DMA tag for Rx coalescing message block. */ 1113 for (i = 0; i < ALE_RX_PAGES; i++) { 1114 error = bus_dma_tag_create( 1115 sc->ale_cdata.ale_parent_tag, /* parent */ 1116 ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1117 BUS_SPACE_MAXADDR, /* lowaddr */ 1118 BUS_SPACE_MAXADDR, /* highaddr */ 1119 NULL, NULL, /* filter, filterarg */ 1120 ALE_RX_CMB_SZ, /* maxsize */ 1121 1, /* nsegments */ 1122 ALE_RX_CMB_SZ, /* maxsegsize */ 1123 0, /* flags */ 1124 NULL, NULL, /* lockfunc, lockarg */ 1125 &sc->ale_cdata.ale_rx_page[i].cmb_tag); 1126 if (error != 0) { 1127 device_printf(sc->ale_dev, 1128 "could not create Rx page %d CMB DMA tag.\n", i); 1129 goto fail; 1130 } 1131 } 1132 1133 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1134 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_ring_tag, 1135 (void **)&sc->ale_cdata.ale_tx_ring, 1136 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1137 &sc->ale_cdata.ale_tx_ring_map); 1138 if (error != 0) { 1139 device_printf(sc->ale_dev, 1140 "could not allocate DMA'able memory for Tx ring.\n"); 1141 goto fail; 1142 } 1143 ctx.ale_busaddr = 0; 1144 error = bus_dmamap_load(sc->ale_cdata.ale_tx_ring_tag, 1145 sc->ale_cdata.ale_tx_ring_map, sc->ale_cdata.ale_tx_ring, 1146 ALE_TX_RING_SZ, ale_dmamap_cb, &ctx, 0); 1147 if (error != 0 || ctx.ale_busaddr == 0) { 1148 device_printf(sc->ale_dev, 1149 "could not load DMA'able memory for Tx ring.\n"); 1150 goto fail; 1151 } 1152 sc->ale_cdata.ale_tx_ring_paddr = ctx.ale_busaddr; 1153 1154 /* Rx pages. */ 1155 for (i = 0; i < ALE_RX_PAGES; i++) { 1156 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].page_tag, 1157 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr, 1158 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1159 &sc->ale_cdata.ale_rx_page[i].page_map); 1160 if (error != 0) { 1161 device_printf(sc->ale_dev, 1162 "could not allocate DMA'able memory for " 1163 "Rx page %d.\n", i); 1164 goto fail; 1165 } 1166 ctx.ale_busaddr = 0; 1167 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].page_tag, 1168 sc->ale_cdata.ale_rx_page[i].page_map, 1169 sc->ale_cdata.ale_rx_page[i].page_addr, 1170 sc->ale_pagesize, ale_dmamap_cb, &ctx, 0); 1171 if (error != 0 || ctx.ale_busaddr == 0) { 1172 device_printf(sc->ale_dev, 1173 "could not load DMA'able memory for " 1174 "Rx page %d.\n", i); 1175 goto fail; 1176 } 1177 sc->ale_cdata.ale_rx_page[i].page_paddr = ctx.ale_busaddr; 1178 } 1179 1180 /* Tx CMB. */ 1181 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_cmb_tag, 1182 (void **)&sc->ale_cdata.ale_tx_cmb, 1183 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1184 &sc->ale_cdata.ale_tx_cmb_map); 1185 if (error != 0) { 1186 device_printf(sc->ale_dev, 1187 "could not allocate DMA'able memory for Tx CMB.\n"); 1188 goto fail; 1189 } 1190 ctx.ale_busaddr = 0; 1191 error = bus_dmamap_load(sc->ale_cdata.ale_tx_cmb_tag, 1192 sc->ale_cdata.ale_tx_cmb_map, sc->ale_cdata.ale_tx_cmb, 1193 ALE_TX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1194 if (error != 0 || ctx.ale_busaddr == 0) { 1195 device_printf(sc->ale_dev, 1196 "could not load DMA'able memory for Tx CMB.\n"); 1197 goto fail; 1198 } 1199 sc->ale_cdata.ale_tx_cmb_paddr = ctx.ale_busaddr; 1200 1201 /* Rx CMB. */ 1202 for (i = 0; i < ALE_RX_PAGES; i++) { 1203 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1204 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 1205 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1206 &sc->ale_cdata.ale_rx_page[i].cmb_map); 1207 if (error != 0) { 1208 device_printf(sc->ale_dev, "could not allocate " 1209 "DMA'able memory for Rx page %d CMB.\n", i); 1210 goto fail; 1211 } 1212 ctx.ale_busaddr = 0; 1213 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1214 sc->ale_cdata.ale_rx_page[i].cmb_map, 1215 sc->ale_cdata.ale_rx_page[i].cmb_addr, 1216 ALE_RX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1217 if (error != 0 || ctx.ale_busaddr == 0) { 1218 device_printf(sc->ale_dev, "could not load DMA'able " 1219 "memory for Rx page %d CMB.\n", i); 1220 goto fail; 1221 } 1222 sc->ale_cdata.ale_rx_page[i].cmb_paddr = ctx.ale_busaddr; 1223 } 1224 1225 /* 1226 * Tx descriptors/RXF0/CMB DMA blocks share the same 1227 * high address region of 64bit DMA address space. 1228 */ 1229 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1230 (error = ale_check_boundary(sc)) != 0) { 1231 device_printf(sc->ale_dev, "4GB boundary crossed, " 1232 "switching to 32bit DMA addressing mode.\n"); 1233 ale_dma_free(sc); 1234 /* 1235 * Limit max allowable DMA address space to 32bit 1236 * and try again. 1237 */ 1238 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1239 goto again; 1240 } 1241 1242 /* 1243 * Create Tx buffer parent tag. 1244 * AR81xx allows 64bit DMA addressing of Tx buffers so it 1245 * needs separate parent DMA tag as parent DMA address space 1246 * could be restricted to be within 32bit address space by 1247 * 4GB boundary crossing. 1248 */ 1249 error = bus_dma_tag_create( 1250 bus_get_dma_tag(sc->ale_dev), /* parent */ 1251 1, 0, /* alignment, boundary */ 1252 BUS_SPACE_MAXADDR, /* lowaddr */ 1253 BUS_SPACE_MAXADDR, /* highaddr */ 1254 NULL, NULL, /* filter, filterarg */ 1255 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1256 0, /* nsegments */ 1257 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1258 0, /* flags */ 1259 NULL, NULL, /* lockfunc, lockarg */ 1260 &sc->ale_cdata.ale_buffer_tag); 1261 if (error != 0) { 1262 device_printf(sc->ale_dev, 1263 "could not create parent buffer DMA tag.\n"); 1264 goto fail; 1265 } 1266 1267 /* Create DMA tag for Tx buffers. */ 1268 error = bus_dma_tag_create( 1269 sc->ale_cdata.ale_buffer_tag, /* parent */ 1270 1, 0, /* alignment, boundary */ 1271 BUS_SPACE_MAXADDR, /* lowaddr */ 1272 BUS_SPACE_MAXADDR, /* highaddr */ 1273 NULL, NULL, /* filter, filterarg */ 1274 ALE_TSO_MAXSIZE, /* maxsize */ 1275 ALE_MAXTXSEGS, /* nsegments */ 1276 ALE_TSO_MAXSEGSIZE, /* maxsegsize */ 1277 0, /* flags */ 1278 NULL, NULL, /* lockfunc, lockarg */ 1279 &sc->ale_cdata.ale_tx_tag); 1280 if (error != 0) { 1281 device_printf(sc->ale_dev, "could not create Tx DMA tag.\n"); 1282 goto fail; 1283 } 1284 1285 /* Create DMA maps for Tx buffers. */ 1286 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1287 txd = &sc->ale_cdata.ale_txdesc[i]; 1288 txd->tx_m = NULL; 1289 txd->tx_dmamap = NULL; 1290 error = bus_dmamap_create(sc->ale_cdata.ale_tx_tag, 0, 1291 &txd->tx_dmamap); 1292 if (error != 0) { 1293 device_printf(sc->ale_dev, 1294 "could not create Tx dmamap.\n"); 1295 goto fail; 1296 } 1297 } 1298 1299 fail: 1300 return (error); 1301 } 1302 1303 static void 1304 ale_dma_free(struct ale_softc *sc) 1305 { 1306 struct ale_txdesc *txd; 1307 int i; 1308 1309 /* Tx buffers. */ 1310 if (sc->ale_cdata.ale_tx_tag != NULL) { 1311 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1312 txd = &sc->ale_cdata.ale_txdesc[i]; 1313 if (txd->tx_dmamap != NULL) { 1314 bus_dmamap_destroy(sc->ale_cdata.ale_tx_tag, 1315 txd->tx_dmamap); 1316 txd->tx_dmamap = NULL; 1317 } 1318 } 1319 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_tag); 1320 sc->ale_cdata.ale_tx_tag = NULL; 1321 } 1322 /* Tx descriptor ring. */ 1323 if (sc->ale_cdata.ale_tx_ring_tag != NULL) { 1324 if (sc->ale_cdata.ale_tx_ring_paddr != 0) 1325 bus_dmamap_unload(sc->ale_cdata.ale_tx_ring_tag, 1326 sc->ale_cdata.ale_tx_ring_map); 1327 if (sc->ale_cdata.ale_tx_ring != NULL) 1328 bus_dmamem_free(sc->ale_cdata.ale_tx_ring_tag, 1329 sc->ale_cdata.ale_tx_ring, 1330 sc->ale_cdata.ale_tx_ring_map); 1331 sc->ale_cdata.ale_tx_ring_paddr = 0; 1332 sc->ale_cdata.ale_tx_ring = NULL; 1333 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_ring_tag); 1334 sc->ale_cdata.ale_tx_ring_tag = NULL; 1335 } 1336 /* Rx page block. */ 1337 for (i = 0; i < ALE_RX_PAGES; i++) { 1338 if (sc->ale_cdata.ale_rx_page[i].page_tag != NULL) { 1339 if (sc->ale_cdata.ale_rx_page[i].page_paddr != 0) 1340 bus_dmamap_unload( 1341 sc->ale_cdata.ale_rx_page[i].page_tag, 1342 sc->ale_cdata.ale_rx_page[i].page_map); 1343 if (sc->ale_cdata.ale_rx_page[i].page_addr != NULL) 1344 bus_dmamem_free( 1345 sc->ale_cdata.ale_rx_page[i].page_tag, 1346 sc->ale_cdata.ale_rx_page[i].page_addr, 1347 sc->ale_cdata.ale_rx_page[i].page_map); 1348 sc->ale_cdata.ale_rx_page[i].page_paddr = 0; 1349 sc->ale_cdata.ale_rx_page[i].page_addr = NULL; 1350 bus_dma_tag_destroy( 1351 sc->ale_cdata.ale_rx_page[i].page_tag); 1352 sc->ale_cdata.ale_rx_page[i].page_tag = NULL; 1353 } 1354 } 1355 /* Rx CMB. */ 1356 for (i = 0; i < ALE_RX_PAGES; i++) { 1357 if (sc->ale_cdata.ale_rx_page[i].cmb_tag != NULL) { 1358 if (sc->ale_cdata.ale_rx_page[i].cmb_paddr != 0) 1359 bus_dmamap_unload( 1360 sc->ale_cdata.ale_rx_page[i].cmb_tag, 1361 sc->ale_cdata.ale_rx_page[i].cmb_map); 1362 if (sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) 1363 bus_dmamem_free( 1364 sc->ale_cdata.ale_rx_page[i].cmb_tag, 1365 sc->ale_cdata.ale_rx_page[i].cmb_addr, 1366 sc->ale_cdata.ale_rx_page[i].cmb_map); 1367 sc->ale_cdata.ale_rx_page[i].cmb_paddr = 0; 1368 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; 1369 bus_dma_tag_destroy( 1370 sc->ale_cdata.ale_rx_page[i].cmb_tag); 1371 sc->ale_cdata.ale_rx_page[i].cmb_tag = NULL; 1372 } 1373 } 1374 /* Tx CMB. */ 1375 if (sc->ale_cdata.ale_tx_cmb_tag != NULL) { 1376 if (sc->ale_cdata.ale_tx_cmb_paddr != 0) 1377 bus_dmamap_unload(sc->ale_cdata.ale_tx_cmb_tag, 1378 sc->ale_cdata.ale_tx_cmb_map); 1379 if (sc->ale_cdata.ale_tx_cmb != NULL) 1380 bus_dmamem_free(sc->ale_cdata.ale_tx_cmb_tag, 1381 sc->ale_cdata.ale_tx_cmb, 1382 sc->ale_cdata.ale_tx_cmb_map); 1383 sc->ale_cdata.ale_tx_cmb_paddr = 0; 1384 sc->ale_cdata.ale_tx_cmb = NULL; 1385 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_cmb_tag); 1386 sc->ale_cdata.ale_tx_cmb_tag = NULL; 1387 } 1388 if (sc->ale_cdata.ale_buffer_tag != NULL) { 1389 bus_dma_tag_destroy(sc->ale_cdata.ale_buffer_tag); 1390 sc->ale_cdata.ale_buffer_tag = NULL; 1391 } 1392 if (sc->ale_cdata.ale_parent_tag != NULL) { 1393 bus_dma_tag_destroy(sc->ale_cdata.ale_parent_tag); 1394 sc->ale_cdata.ale_parent_tag = NULL; 1395 } 1396 } 1397 1398 static int 1399 ale_shutdown(device_t dev) 1400 { 1401 1402 return (ale_suspend(dev)); 1403 } 1404 1405 /* 1406 * Note, this driver resets the link speed to 10/100Mbps by 1407 * restarting auto-negotiation in suspend/shutdown phase but we 1408 * don't know whether that auto-negotiation would succeed or not 1409 * as driver has no control after powering off/suspend operation. 1410 * If the renegotiation fail WOL may not work. Running at 1Gbps 1411 * will draw more power than 375mA at 3.3V which is specified in 1412 * PCI specification and that would result in complete 1413 * shutdowning power to ethernet controller. 1414 * 1415 * TODO 1416 * Save current negotiated media speed/duplex/flow-control to 1417 * softc and restore the same link again after resuming. PHY 1418 * handling such as power down/resetting to 100Mbps may be better 1419 * handled in suspend method in phy driver. 1420 */ 1421 static void 1422 ale_setlinkspeed(struct ale_softc *sc) 1423 { 1424 struct mii_data *mii; 1425 int aneg, i; 1426 1427 mii = device_get_softc(sc->ale_miibus); 1428 mii_pollstat(mii); 1429 aneg = 0; 1430 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1431 (IFM_ACTIVE | IFM_AVALID)) { 1432 switch IFM_SUBTYPE(mii->mii_media_active) { 1433 case IFM_10_T: 1434 case IFM_100_TX: 1435 return; 1436 case IFM_1000_T: 1437 aneg++; 1438 break; 1439 default: 1440 break; 1441 } 1442 } 1443 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_100T2CR, 0); 1444 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1445 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1446 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1447 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1448 DELAY(1000); 1449 if (aneg != 0) { 1450 /* 1451 * Poll link state until ale(4) get a 10/100Mbps link. 1452 */ 1453 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1454 mii_pollstat(mii); 1455 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 1456 == (IFM_ACTIVE | IFM_AVALID)) { 1457 switch (IFM_SUBTYPE( 1458 mii->mii_media_active)) { 1459 case IFM_10_T: 1460 case IFM_100_TX: 1461 ale_mac_config(sc); 1462 return; 1463 default: 1464 break; 1465 } 1466 } 1467 ALE_UNLOCK(sc); 1468 pause("alelnk", hz); 1469 ALE_LOCK(sc); 1470 } 1471 if (i == MII_ANEGTICKS_GIGE) 1472 device_printf(sc->ale_dev, 1473 "establishing a link failed, WOL may not work!"); 1474 } 1475 /* 1476 * No link, force MAC to have 100Mbps, full-duplex link. 1477 * This is the last resort and may/may not work. 1478 */ 1479 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1480 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1481 ale_mac_config(sc); 1482 } 1483 1484 static void 1485 ale_setwol(struct ale_softc *sc) 1486 { 1487 if_t ifp; 1488 uint32_t reg, pmcs; 1489 uint16_t pmstat; 1490 int pmc; 1491 1492 ALE_LOCK_ASSERT(sc); 1493 1494 if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) != 0) { 1495 /* Disable WOL. */ 1496 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 1497 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1498 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1499 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1500 /* Force PHY power down. */ 1501 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1502 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1503 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_PHY_PLL_ON | 1504 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_IDDQ | 1505 GPHY_CTRL_PCLK_SEL_DIS | GPHY_CTRL_PWDOWN_HW); 1506 return; 1507 } 1508 1509 ifp = sc->ale_ifp; 1510 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { 1511 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 1512 ale_setlinkspeed(sc); 1513 } 1514 1515 pmcs = 0; 1516 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 1517 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1518 CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs); 1519 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1520 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 1521 MAC_CFG_BCAST); 1522 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0) 1523 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1524 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 1525 reg |= MAC_CFG_RX_ENB; 1526 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1527 1528 if ((if_getcapenable(ifp) & IFCAP_WOL) == 0) { 1529 /* WOL disabled, PHY power down. */ 1530 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1531 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1532 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1533 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1534 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1535 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 1536 GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PCLK_SEL_DIS | 1537 GPHY_CTRL_PWDOWN_HW); 1538 } 1539 /* Request PME. */ 1540 pmstat = pci_read_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, 2); 1541 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1542 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 1543 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1544 pci_write_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1545 } 1546 1547 static int 1548 ale_suspend(device_t dev) 1549 { 1550 struct ale_softc *sc; 1551 1552 sc = device_get_softc(dev); 1553 1554 ALE_LOCK(sc); 1555 ale_stop(sc); 1556 ale_setwol(sc); 1557 ALE_UNLOCK(sc); 1558 1559 return (0); 1560 } 1561 1562 static int 1563 ale_resume(device_t dev) 1564 { 1565 struct ale_softc *sc; 1566 if_t ifp; 1567 int pmc; 1568 uint16_t pmstat; 1569 1570 sc = device_get_softc(dev); 1571 1572 ALE_LOCK(sc); 1573 if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) == 0) { 1574 /* Disable PME and clear PME status. */ 1575 pmstat = pci_read_config(sc->ale_dev, 1576 pmc + PCIR_POWER_STATUS, 2); 1577 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 1578 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1579 pci_write_config(sc->ale_dev, 1580 pmc + PCIR_POWER_STATUS, pmstat, 2); 1581 } 1582 } 1583 /* Reset PHY. */ 1584 ale_phy_reset(sc); 1585 ifp = sc->ale_ifp; 1586 if ((if_getflags(ifp) & IFF_UP) != 0) { 1587 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1588 ale_init_locked(sc); 1589 } 1590 ALE_UNLOCK(sc); 1591 1592 return (0); 1593 } 1594 1595 static int 1596 ale_encap(struct ale_softc *sc, struct mbuf **m_head) 1597 { 1598 struct ale_txdesc *txd, *txd_last; 1599 struct tx_desc *desc; 1600 struct mbuf *m; 1601 struct ip *ip; 1602 struct tcphdr *tcp; 1603 bus_dma_segment_t txsegs[ALE_MAXTXSEGS]; 1604 bus_dmamap_t map; 1605 uint32_t cflags, hdrlen, ip_off, poff, vtag; 1606 int error, i, nsegs, prod, si; 1607 1608 ALE_LOCK_ASSERT(sc); 1609 1610 M_ASSERTPKTHDR((*m_head)); 1611 1612 m = *m_head; 1613 ip = NULL; 1614 tcp = NULL; 1615 cflags = vtag = 0; 1616 ip_off = poff = 0; 1617 if ((m->m_pkthdr.csum_flags & (ALE_CSUM_FEATURES | CSUM_TSO)) != 0) { 1618 /* 1619 * AR81xx requires offset of TCP/UDP payload in its Tx 1620 * descriptor to perform hardware Tx checksum offload. 1621 * Additionally, TSO requires IP/TCP header size and 1622 * modification of IP/TCP header in order to make TSO 1623 * engine work. This kind of operation takes many CPU 1624 * cycles on FreeBSD so fast host CPU is required to 1625 * get smooth TSO performance. 1626 */ 1627 struct ether_header *eh; 1628 1629 if (M_WRITABLE(m) == 0) { 1630 /* Get a writable copy. */ 1631 m = m_dup(*m_head, M_NOWAIT); 1632 /* Release original mbufs. */ 1633 m_freem(*m_head); 1634 if (m == NULL) { 1635 *m_head = NULL; 1636 return (ENOBUFS); 1637 } 1638 *m_head = m; 1639 } 1640 1641 /* 1642 * Buggy-controller requires 4 byte aligned Tx buffer 1643 * to make custom checksum offload work. 1644 */ 1645 if ((sc->ale_flags & ALE_FLAG_TXCSUM_BUG) != 0 && 1646 (m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0 && 1647 (mtod(m, intptr_t) & 3) != 0) { 1648 m = m_defrag(*m_head, M_NOWAIT); 1649 if (m == NULL) { 1650 m_freem(*m_head); 1651 *m_head = NULL; 1652 return (ENOBUFS); 1653 } 1654 *m_head = m; 1655 } 1656 1657 ip_off = sizeof(struct ether_header); 1658 m = m_pullup(m, ip_off); 1659 if (m == NULL) { 1660 *m_head = NULL; 1661 return (ENOBUFS); 1662 } 1663 eh = mtod(m, struct ether_header *); 1664 /* 1665 * Check if hardware VLAN insertion is off. 1666 * Additional check for LLC/SNAP frame? 1667 */ 1668 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1669 ip_off = sizeof(struct ether_vlan_header); 1670 m = m_pullup(m, ip_off); 1671 if (m == NULL) { 1672 *m_head = NULL; 1673 return (ENOBUFS); 1674 } 1675 } 1676 m = m_pullup(m, ip_off + sizeof(struct ip)); 1677 if (m == NULL) { 1678 *m_head = NULL; 1679 return (ENOBUFS); 1680 } 1681 ip = (struct ip *)(mtod(m, char *) + ip_off); 1682 poff = ip_off + (ip->ip_hl << 2); 1683 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1684 /* 1685 * XXX 1686 * AR81xx requires the first descriptor should 1687 * not include any TCP playload for TSO case. 1688 * (i.e. ethernet header + IP + TCP header only) 1689 * m_pullup(9) above will ensure this too. 1690 * However it's not correct if the first mbuf 1691 * of the chain does not use cluster. 1692 */ 1693 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1694 if (m == NULL) { 1695 *m_head = NULL; 1696 return (ENOBUFS); 1697 } 1698 ip = (struct ip *)(mtod(m, char *) + ip_off); 1699 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1700 m = m_pullup(m, poff + (tcp->th_off << 2)); 1701 if (m == NULL) { 1702 *m_head = NULL; 1703 return (ENOBUFS); 1704 } 1705 /* 1706 * AR81xx requires IP/TCP header size and offset as 1707 * well as TCP pseudo checksum which complicates 1708 * TSO configuration. I guess this comes from the 1709 * adherence to Microsoft NDIS Large Send 1710 * specification which requires insertion of 1711 * pseudo checksum by upper stack. The pseudo 1712 * checksum that NDIS refers to doesn't include 1713 * TCP payload length so ale(4) should recompute 1714 * the pseudo checksum here. Hopefully this wouldn't 1715 * be much burden on modern CPUs. 1716 * Reset IP checksum and recompute TCP pseudo 1717 * checksum as NDIS specification said. 1718 */ 1719 ip->ip_sum = 0; 1720 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1721 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1722 } 1723 *m_head = m; 1724 } 1725 1726 si = prod = sc->ale_cdata.ale_tx_prod; 1727 txd = &sc->ale_cdata.ale_txdesc[prod]; 1728 txd_last = txd; 1729 map = txd->tx_dmamap; 1730 1731 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1732 *m_head, txsegs, &nsegs, 0); 1733 if (error == EFBIG) { 1734 m = m_collapse(*m_head, M_NOWAIT, ALE_MAXTXSEGS); 1735 if (m == NULL) { 1736 m_freem(*m_head); 1737 *m_head = NULL; 1738 return (ENOMEM); 1739 } 1740 *m_head = m; 1741 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1742 *m_head, txsegs, &nsegs, 0); 1743 if (error != 0) { 1744 m_freem(*m_head); 1745 *m_head = NULL; 1746 return (error); 1747 } 1748 } else if (error != 0) 1749 return (error); 1750 if (nsegs == 0) { 1751 m_freem(*m_head); 1752 *m_head = NULL; 1753 return (EIO); 1754 } 1755 1756 /* Check descriptor overrun. */ 1757 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 3) { 1758 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, map); 1759 return (ENOBUFS); 1760 } 1761 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, map, BUS_DMASYNC_PREWRITE); 1762 1763 m = *m_head; 1764 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1765 /* Request TSO and set MSS. */ 1766 cflags |= ALE_TD_TSO; 1767 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << ALE_TD_MSS_SHIFT); 1768 /* Set IP/TCP header size. */ 1769 cflags |= ip->ip_hl << ALE_TD_IPHDR_LEN_SHIFT; 1770 cflags |= tcp->th_off << ALE_TD_TCPHDR_LEN_SHIFT; 1771 } else if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { 1772 /* 1773 * AR81xx supports Tx custom checksum offload feature 1774 * that offloads single 16bit checksum computation. 1775 * So you can choose one among IP, TCP and UDP. 1776 * Normally driver sets checksum start/insertion 1777 * position from the information of TCP/UDP frame as 1778 * TCP/UDP checksum takes more time than that of IP. 1779 * However it seems that custom checksum offload 1780 * requires 4 bytes aligned Tx buffers due to hardware 1781 * bug. 1782 * AR81xx also supports explicit Tx checksum computation 1783 * if it is told that the size of IP header and TCP 1784 * header(for UDP, the header size does not matter 1785 * because it's fixed length). However with this scheme 1786 * TSO does not work so you have to choose one either 1787 * TSO or explicit Tx checksum offload. I chosen TSO 1788 * plus custom checksum offload with work-around which 1789 * will cover most common usage for this consumer 1790 * ethernet controller. The work-around takes a lot of 1791 * CPU cycles if Tx buffer is not aligned on 4 bytes 1792 * boundary, though. 1793 */ 1794 cflags |= ALE_TD_CXSUM; 1795 /* Set checksum start offset. */ 1796 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); 1797 /* Set checksum insertion position of TCP/UDP. */ 1798 cflags |= ((poff + m->m_pkthdr.csum_data) << 1799 ALE_TD_CSUM_XSUMOFFSET_SHIFT); 1800 } 1801 1802 /* Configure VLAN hardware tag insertion. */ 1803 if ((m->m_flags & M_VLANTAG) != 0) { 1804 vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1805 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); 1806 cflags |= ALE_TD_INSERT_VLAN_TAG; 1807 } 1808 1809 i = 0; 1810 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1811 /* 1812 * Make sure the first fragment contains 1813 * only ethernet and IP/TCP header with options. 1814 */ 1815 hdrlen = poff + (tcp->th_off << 2); 1816 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1817 desc->addr = htole64(txsegs[i].ds_addr); 1818 desc->len = htole32(ALE_TX_BYTES(hdrlen) | vtag); 1819 desc->flags = htole32(cflags); 1820 sc->ale_cdata.ale_tx_cnt++; 1821 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1822 if (m->m_len - hdrlen > 0) { 1823 /* Handle remaining payload of the first fragment. */ 1824 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1825 desc->addr = htole64(txsegs[i].ds_addr + hdrlen); 1826 desc->len = htole32(ALE_TX_BYTES(m->m_len - hdrlen) | 1827 vtag); 1828 desc->flags = htole32(cflags); 1829 sc->ale_cdata.ale_tx_cnt++; 1830 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1831 } 1832 i = 1; 1833 } 1834 for (; i < nsegs; i++) { 1835 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1836 desc->addr = htole64(txsegs[i].ds_addr); 1837 desc->len = htole32(ALE_TX_BYTES(txsegs[i].ds_len) | vtag); 1838 desc->flags = htole32(cflags); 1839 sc->ale_cdata.ale_tx_cnt++; 1840 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1841 } 1842 /* Update producer index. */ 1843 sc->ale_cdata.ale_tx_prod = prod; 1844 /* Set TSO header on the first descriptor. */ 1845 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1846 desc = &sc->ale_cdata.ale_tx_ring[si]; 1847 desc->flags |= htole32(ALE_TD_TSO_HDR); 1848 } 1849 1850 /* Finally set EOP on the last descriptor. */ 1851 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; 1852 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1853 desc->flags |= htole32(ALE_TD_EOP); 1854 1855 /* Swap dmamap of the first and the last. */ 1856 txd = &sc->ale_cdata.ale_txdesc[prod]; 1857 map = txd_last->tx_dmamap; 1858 txd_last->tx_dmamap = txd->tx_dmamap; 1859 txd->tx_dmamap = map; 1860 txd->tx_m = m; 1861 1862 /* Sync descriptors. */ 1863 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 1864 sc->ale_cdata.ale_tx_ring_map, 1865 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1866 1867 return (0); 1868 } 1869 1870 static void 1871 ale_start(if_t ifp) 1872 { 1873 struct ale_softc *sc; 1874 1875 sc = if_getsoftc(ifp); 1876 ALE_LOCK(sc); 1877 ale_start_locked(ifp); 1878 ALE_UNLOCK(sc); 1879 } 1880 1881 static void 1882 ale_start_locked(if_t ifp) 1883 { 1884 struct ale_softc *sc; 1885 struct mbuf *m_head; 1886 int enq; 1887 1888 sc = if_getsoftc(ifp); 1889 1890 ALE_LOCK_ASSERT(sc); 1891 1892 /* Reclaim transmitted frames. */ 1893 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) 1894 ale_txeof(sc); 1895 1896 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1897 IFF_DRV_RUNNING || (sc->ale_flags & ALE_FLAG_LINK) == 0) 1898 return; 1899 1900 for (enq = 0; !if_sendq_empty(ifp); ) { 1901 m_head = if_dequeue(ifp); 1902 if (m_head == NULL) 1903 break; 1904 /* 1905 * Pack the data into the transmit ring. If we 1906 * don't have room, set the OACTIVE flag and wait 1907 * for the NIC to drain the ring. 1908 */ 1909 if (ale_encap(sc, &m_head)) { 1910 if (m_head == NULL) 1911 break; 1912 if_sendq_prepend(ifp, m_head); 1913 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1914 break; 1915 } 1916 1917 enq++; 1918 /* 1919 * If there's a BPF listener, bounce a copy of this frame 1920 * to him. 1921 */ 1922 ETHER_BPF_MTAP(ifp, m_head); 1923 } 1924 1925 if (enq > 0) { 1926 /* Kick. */ 1927 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, 1928 sc->ale_cdata.ale_tx_prod); 1929 /* Set a timeout in case the chip goes out to lunch. */ 1930 sc->ale_watchdog_timer = ALE_TX_TIMEOUT; 1931 } 1932 } 1933 1934 static void 1935 ale_watchdog(struct ale_softc *sc) 1936 { 1937 if_t ifp; 1938 1939 ALE_LOCK_ASSERT(sc); 1940 1941 if (sc->ale_watchdog_timer == 0 || --sc->ale_watchdog_timer) 1942 return; 1943 1944 ifp = sc->ale_ifp; 1945 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1946 if_printf(sc->ale_ifp, "watchdog timeout (lost link)\n"); 1947 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1948 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1949 ale_init_locked(sc); 1950 return; 1951 } 1952 if_printf(sc->ale_ifp, "watchdog timeout -- resetting\n"); 1953 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1954 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1955 ale_init_locked(sc); 1956 if (!if_sendq_empty(ifp)) 1957 ale_start_locked(ifp); 1958 } 1959 1960 static int 1961 ale_ioctl(if_t ifp, u_long cmd, caddr_t data) 1962 { 1963 struct ale_softc *sc; 1964 struct ifreq *ifr; 1965 struct mii_data *mii; 1966 int error, mask; 1967 1968 sc = if_getsoftc(ifp); 1969 ifr = (struct ifreq *)data; 1970 error = 0; 1971 switch (cmd) { 1972 case SIOCSIFMTU: 1973 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALE_JUMBO_MTU || 1974 ((sc->ale_flags & ALE_FLAG_JUMBO) == 0 && 1975 ifr->ifr_mtu > ETHERMTU)) 1976 error = EINVAL; 1977 else if (if_getmtu(ifp) != ifr->ifr_mtu) { 1978 ALE_LOCK(sc); 1979 if_setmtu(ifp, ifr->ifr_mtu); 1980 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1981 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1982 ale_init_locked(sc); 1983 } 1984 ALE_UNLOCK(sc); 1985 } 1986 break; 1987 case SIOCSIFFLAGS: 1988 ALE_LOCK(sc); 1989 if ((if_getflags(ifp) & IFF_UP) != 0) { 1990 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1991 if (((if_getflags(ifp) ^ sc->ale_if_flags) 1992 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1993 ale_rxfilter(sc); 1994 } else { 1995 ale_init_locked(sc); 1996 } 1997 } else { 1998 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1999 ale_stop(sc); 2000 } 2001 sc->ale_if_flags = if_getflags(ifp); 2002 ALE_UNLOCK(sc); 2003 break; 2004 case SIOCADDMULTI: 2005 case SIOCDELMULTI: 2006 ALE_LOCK(sc); 2007 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2008 ale_rxfilter(sc); 2009 ALE_UNLOCK(sc); 2010 break; 2011 case SIOCSIFMEDIA: 2012 case SIOCGIFMEDIA: 2013 mii = device_get_softc(sc->ale_miibus); 2014 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2015 break; 2016 case SIOCSIFCAP: 2017 ALE_LOCK(sc); 2018 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 2019 if ((mask & IFCAP_TXCSUM) != 0 && 2020 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 2021 if_togglecapenable(ifp, IFCAP_TXCSUM); 2022 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 2023 if_sethwassistbits(ifp, ALE_CSUM_FEATURES, 0); 2024 else 2025 if_sethwassistbits(ifp, 0, ALE_CSUM_FEATURES); 2026 } 2027 if ((mask & IFCAP_RXCSUM) != 0 && 2028 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) 2029 if_togglecapenable(ifp, IFCAP_RXCSUM); 2030 if ((mask & IFCAP_TSO4) != 0 && 2031 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) { 2032 if_togglecapenable(ifp, IFCAP_TSO4); 2033 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0) 2034 if_sethwassistbits(ifp, CSUM_TSO, 0); 2035 else 2036 if_sethwassistbits(ifp, 0, CSUM_TSO); 2037 } 2038 2039 if ((mask & IFCAP_WOL_MCAST) != 0 && 2040 (if_getcapabilities(ifp) & IFCAP_WOL_MCAST) != 0) 2041 if_togglecapenable(ifp, IFCAP_WOL_MCAST); 2042 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2043 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0) 2044 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 2045 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2046 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0) 2047 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 2048 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2049 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) 2050 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 2051 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2052 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 2053 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 2054 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) 2055 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO); 2056 ale_rxvlan(sc); 2057 } 2058 ALE_UNLOCK(sc); 2059 VLAN_CAPABILITIES(ifp); 2060 break; 2061 default: 2062 error = ether_ioctl(ifp, cmd, data); 2063 break; 2064 } 2065 2066 return (error); 2067 } 2068 2069 static void 2070 ale_mac_config(struct ale_softc *sc) 2071 { 2072 struct mii_data *mii; 2073 uint32_t reg; 2074 2075 ALE_LOCK_ASSERT(sc); 2076 2077 mii = device_get_softc(sc->ale_miibus); 2078 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2079 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2080 MAC_CFG_SPEED_MASK); 2081 /* Reprogram MAC with resolved speed/duplex. */ 2082 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2083 case IFM_10_T: 2084 case IFM_100_TX: 2085 reg |= MAC_CFG_SPEED_10_100; 2086 break; 2087 case IFM_1000_T: 2088 reg |= MAC_CFG_SPEED_1000; 2089 break; 2090 } 2091 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2092 reg |= MAC_CFG_FULL_DUPLEX; 2093 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2094 reg |= MAC_CFG_TX_FC; 2095 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2096 reg |= MAC_CFG_RX_FC; 2097 } 2098 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2099 } 2100 2101 static void 2102 ale_stats_clear(struct ale_softc *sc) 2103 { 2104 struct smb sb; 2105 uint32_t *reg; 2106 int i; 2107 2108 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2109 CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2110 i += sizeof(uint32_t); 2111 } 2112 /* Read Tx statistics. */ 2113 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2114 CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2115 i += sizeof(uint32_t); 2116 } 2117 } 2118 2119 static void 2120 ale_stats_update(struct ale_softc *sc) 2121 { 2122 struct ale_hw_stats *stat; 2123 struct smb sb, *smb; 2124 if_t ifp; 2125 uint32_t *reg; 2126 int i; 2127 2128 ALE_LOCK_ASSERT(sc); 2129 2130 ifp = sc->ale_ifp; 2131 stat = &sc->ale_stats; 2132 smb = &sb; 2133 2134 /* Read Rx statistics. */ 2135 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2136 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2137 i += sizeof(uint32_t); 2138 } 2139 /* Read Tx statistics. */ 2140 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2141 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2142 i += sizeof(uint32_t); 2143 } 2144 2145 /* Rx stats. */ 2146 stat->rx_frames += smb->rx_frames; 2147 stat->rx_bcast_frames += smb->rx_bcast_frames; 2148 stat->rx_mcast_frames += smb->rx_mcast_frames; 2149 stat->rx_pause_frames += smb->rx_pause_frames; 2150 stat->rx_control_frames += smb->rx_control_frames; 2151 stat->rx_crcerrs += smb->rx_crcerrs; 2152 stat->rx_lenerrs += smb->rx_lenerrs; 2153 stat->rx_bytes += smb->rx_bytes; 2154 stat->rx_runts += smb->rx_runts; 2155 stat->rx_fragments += smb->rx_fragments; 2156 stat->rx_pkts_64 += smb->rx_pkts_64; 2157 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2158 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2159 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2160 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2161 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2162 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2163 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2164 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2165 stat->rx_rrs_errs += smb->rx_rrs_errs; 2166 stat->rx_alignerrs += smb->rx_alignerrs; 2167 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2168 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2169 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2170 2171 /* Tx stats. */ 2172 stat->tx_frames += smb->tx_frames; 2173 stat->tx_bcast_frames += smb->tx_bcast_frames; 2174 stat->tx_mcast_frames += smb->tx_mcast_frames; 2175 stat->tx_pause_frames += smb->tx_pause_frames; 2176 stat->tx_excess_defer += smb->tx_excess_defer; 2177 stat->tx_control_frames += smb->tx_control_frames; 2178 stat->tx_deferred += smb->tx_deferred; 2179 stat->tx_bytes += smb->tx_bytes; 2180 stat->tx_pkts_64 += smb->tx_pkts_64; 2181 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2182 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2183 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2184 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2185 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2186 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2187 stat->tx_single_colls += smb->tx_single_colls; 2188 stat->tx_multi_colls += smb->tx_multi_colls; 2189 stat->tx_late_colls += smb->tx_late_colls; 2190 stat->tx_excess_colls += smb->tx_excess_colls; 2191 stat->tx_underrun += smb->tx_underrun; 2192 stat->tx_desc_underrun += smb->tx_desc_underrun; 2193 stat->tx_lenerrs += smb->tx_lenerrs; 2194 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2195 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2196 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2197 2198 /* Update counters in ifnet. */ 2199 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames); 2200 2201 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls + 2202 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2203 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT); 2204 2205 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_late_colls + 2206 smb->tx_excess_colls + smb->tx_underrun + smb->tx_pkts_truncated); 2207 2208 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames); 2209 2210 if_inc_counter(ifp, IFCOUNTER_IERRORS, 2211 smb->rx_crcerrs + smb->rx_lenerrs + 2212 smb->rx_runts + smb->rx_pkts_truncated + 2213 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2214 smb->rx_alignerrs); 2215 } 2216 2217 static int 2218 ale_intr(void *arg) 2219 { 2220 struct ale_softc *sc; 2221 uint32_t status; 2222 2223 sc = (struct ale_softc *)arg; 2224 2225 status = CSR_READ_4(sc, ALE_INTR_STATUS); 2226 if ((status & ALE_INTRS) == 0) 2227 return (FILTER_STRAY); 2228 /* Disable interrupts. */ 2229 CSR_WRITE_4(sc, ALE_INTR_STATUS, INTR_DIS_INT); 2230 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2231 2232 return (FILTER_HANDLED); 2233 } 2234 2235 static void 2236 ale_int_task(void *arg, int pending) 2237 { 2238 struct ale_softc *sc; 2239 if_t ifp; 2240 uint32_t status; 2241 int more; 2242 2243 sc = (struct ale_softc *)arg; 2244 2245 status = CSR_READ_4(sc, ALE_INTR_STATUS); 2246 ALE_LOCK(sc); 2247 if (sc->ale_morework != 0) 2248 status |= INTR_RX_PKT; 2249 if ((status & ALE_INTRS) == 0) 2250 goto done; 2251 2252 /* Acknowledge interrupts but still disable interrupts. */ 2253 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); 2254 2255 ifp = sc->ale_ifp; 2256 more = 0; 2257 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2258 more = ale_rxeof(sc, sc->ale_process_limit); 2259 if (more == EAGAIN) 2260 sc->ale_morework = 1; 2261 else if (more == EIO) { 2262 sc->ale_stats.reset_brk_seq++; 2263 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2264 ale_init_locked(sc); 2265 ALE_UNLOCK(sc); 2266 return; 2267 } 2268 2269 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 2270 if ((status & INTR_DMA_RD_TO_RST) != 0) 2271 device_printf(sc->ale_dev, 2272 "DMA read error! -- resetting\n"); 2273 if ((status & INTR_DMA_WR_TO_RST) != 0) 2274 device_printf(sc->ale_dev, 2275 "DMA write error! -- resetting\n"); 2276 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2277 ale_init_locked(sc); 2278 ALE_UNLOCK(sc); 2279 return; 2280 } 2281 if (!if_sendq_empty(ifp)) 2282 ale_start_locked(ifp); 2283 } 2284 2285 if (more == EAGAIN || 2286 (CSR_READ_4(sc, ALE_INTR_STATUS) & ALE_INTRS) != 0) { 2287 ALE_UNLOCK(sc); 2288 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2289 return; 2290 } 2291 2292 done: 2293 ALE_UNLOCK(sc); 2294 2295 /* Re-enable interrupts. */ 2296 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); 2297 } 2298 2299 static void 2300 ale_txeof(struct ale_softc *sc) 2301 { 2302 if_t ifp; 2303 struct ale_txdesc *txd; 2304 uint32_t cons, prod; 2305 int prog; 2306 2307 ALE_LOCK_ASSERT(sc); 2308 2309 ifp = sc->ale_ifp; 2310 2311 if (sc->ale_cdata.ale_tx_cnt == 0) 2312 return; 2313 2314 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2315 sc->ale_cdata.ale_tx_ring_map, 2316 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2317 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { 2318 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2319 sc->ale_cdata.ale_tx_cmb_map, 2320 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2321 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; 2322 } else 2323 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); 2324 cons = sc->ale_cdata.ale_tx_cons; 2325 /* 2326 * Go through our Tx list and free mbufs for those 2327 * frames which have been transmitted. 2328 */ 2329 for (prog = 0; cons != prod; prog++, 2330 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { 2331 if (sc->ale_cdata.ale_tx_cnt <= 0) 2332 break; 2333 prog++; 2334 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2335 sc->ale_cdata.ale_tx_cnt--; 2336 txd = &sc->ale_cdata.ale_txdesc[cons]; 2337 if (txd->tx_m != NULL) { 2338 /* Reclaim transmitted mbufs. */ 2339 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2340 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2341 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2342 txd->tx_dmamap); 2343 m_freem(txd->tx_m); 2344 txd->tx_m = NULL; 2345 } 2346 } 2347 2348 if (prog > 0) { 2349 sc->ale_cdata.ale_tx_cons = cons; 2350 /* 2351 * Unarm watchdog timer only when there is no pending 2352 * Tx descriptors in queue. 2353 */ 2354 if (sc->ale_cdata.ale_tx_cnt == 0) 2355 sc->ale_watchdog_timer = 0; 2356 } 2357 } 2358 2359 static void 2360 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, 2361 uint32_t length, uint32_t *prod) 2362 { 2363 struct ale_rx_page *rx_page; 2364 2365 rx_page = *page; 2366 /* Update consumer position. */ 2367 rx_page->cons += roundup(length + sizeof(struct rx_rs), 2368 ALE_RX_PAGE_ALIGN); 2369 if (rx_page->cons >= ALE_RX_PAGE_SZ) { 2370 /* 2371 * End of Rx page reached, let hardware reuse 2372 * this page. 2373 */ 2374 rx_page->cons = 0; 2375 *rx_page->cmb_addr = 0; 2376 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2377 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2378 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, 2379 RXF_VALID); 2380 /* Switch to alternate Rx page. */ 2381 sc->ale_cdata.ale_rx_curp ^= 1; 2382 rx_page = *page = 2383 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2384 /* Page flipped, sync CMB and Rx page. */ 2385 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2386 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2387 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2388 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2389 /* Sync completed, cache updated producer index. */ 2390 *prod = *rx_page->cmb_addr; 2391 } 2392 } 2393 2394 /* 2395 * It seems that AR81xx controller can compute partial checksum. 2396 * The partial checksum value can be used to accelerate checksum 2397 * computation for fragmented TCP/UDP packets. Upper network stack 2398 * already takes advantage of the partial checksum value in IP 2399 * reassembly stage. But I'm not sure the correctness of the 2400 * partial hardware checksum assistance due to lack of data sheet. 2401 * In addition, the Rx feature of controller that requires copying 2402 * for every frames effectively nullifies one of most nice offload 2403 * capability of controller. 2404 */ 2405 static void 2406 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) 2407 { 2408 if_t ifp; 2409 struct ip *ip; 2410 char *p; 2411 2412 ifp = sc->ale_ifp; 2413 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2414 if ((status & ALE_RD_IPCSUM_NOK) == 0) 2415 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2416 2417 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { 2418 if (((status & ALE_RD_IPV4_FRAG) == 0) && 2419 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && 2420 ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) { 2421 m->m_pkthdr.csum_flags |= 2422 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2423 m->m_pkthdr.csum_data = 0xffff; 2424 } 2425 } else { 2426 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 && 2427 (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) { 2428 p = mtod(m, char *); 2429 p += ETHER_HDR_LEN; 2430 if ((status & ALE_RD_802_3) != 0) 2431 p += LLC_SNAPFRAMELEN; 2432 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0 && 2433 (status & ALE_RD_VLAN) != 0) 2434 p += ETHER_VLAN_ENCAP_LEN; 2435 ip = (struct ip *)p; 2436 if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0) 2437 return; 2438 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 2439 CSUM_PSEUDO_HDR; 2440 m->m_pkthdr.csum_data = 0xffff; 2441 } 2442 } 2443 /* 2444 * Don't mark bad checksum for TCP/UDP frames 2445 * as fragmented frames may always have set 2446 * bad checksummed bit of frame status. 2447 */ 2448 } 2449 2450 /* Process received frames. */ 2451 static int 2452 ale_rxeof(struct ale_softc *sc, int count) 2453 { 2454 struct ale_rx_page *rx_page; 2455 struct rx_rs *rs; 2456 if_t ifp; 2457 struct mbuf *m; 2458 uint32_t length, prod, seqno, status, vtags; 2459 int prog; 2460 2461 ifp = sc->ale_ifp; 2462 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2463 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2464 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2465 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2466 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2467 /* 2468 * Don't directly access producer index as hardware may 2469 * update it while Rx handler is in progress. It would 2470 * be even better if there is a way to let hardware 2471 * know how far driver processed its received frames. 2472 * Alternatively, hardware could provide a way to disable 2473 * CMB updates until driver acknowledges the end of CMB 2474 * access. 2475 */ 2476 prod = *rx_page->cmb_addr; 2477 for (prog = 0; prog < count; prog++) { 2478 if (rx_page->cons >= prod) 2479 break; 2480 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); 2481 seqno = ALE_RX_SEQNO(le32toh(rs->seqno)); 2482 if (sc->ale_cdata.ale_rx_seqno != seqno) { 2483 /* 2484 * Normally I believe this should not happen unless 2485 * severe driver bug or corrupted memory. However 2486 * it seems to happen under certain conditions which 2487 * is triggered by abrupt Rx events such as initiation 2488 * of bulk transfer of remote host. It's not easy to 2489 * reproduce this and I doubt it could be related 2490 * with FIFO overflow of hardware or activity of Tx 2491 * CMB updates. I also remember similar behaviour 2492 * seen on RealTek 8139 which uses resembling Rx 2493 * scheme. 2494 */ 2495 if (bootverbose) 2496 device_printf(sc->ale_dev, 2497 "garbled seq: %u, expected: %u -- " 2498 "resetting!\n", seqno, 2499 sc->ale_cdata.ale_rx_seqno); 2500 return (EIO); 2501 } 2502 /* Frame received. */ 2503 sc->ale_cdata.ale_rx_seqno++; 2504 length = ALE_RX_BYTES(le32toh(rs->length)); 2505 status = le32toh(rs->flags); 2506 if ((status & ALE_RD_ERROR) != 0) { 2507 /* 2508 * We want to pass the following frames to upper 2509 * layer regardless of error status of Rx return 2510 * status. 2511 * 2512 * o IP/TCP/UDP checksum is bad. 2513 * o frame length and protocol specific length 2514 * does not match. 2515 */ 2516 if ((status & (ALE_RD_CRC | ALE_RD_CODE | 2517 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | 2518 ALE_RD_TRUNC)) != 0) { 2519 ale_rx_update_page(sc, &rx_page, length, &prod); 2520 continue; 2521 } 2522 } 2523 /* 2524 * m_devget(9) is major bottle-neck of ale(4)(It comes 2525 * from hardware limitation). For jumbo frames we could 2526 * get a slightly better performance if driver use 2527 * m_getjcl(9) with proper buffer size argument. However 2528 * that would make code more complicated and I don't 2529 * think users would expect good Rx performance numbers 2530 * on these low-end consumer ethernet controller. 2531 */ 2532 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, 2533 ETHER_ALIGN, ifp, NULL); 2534 if (m == NULL) { 2535 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2536 ale_rx_update_page(sc, &rx_page, length, &prod); 2537 continue; 2538 } 2539 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0 && 2540 (status & ALE_RD_IPV4) != 0) 2541 ale_rxcsum(sc, m, status); 2542 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 && 2543 (status & ALE_RD_VLAN) != 0) { 2544 vtags = ALE_RX_VLAN(le32toh(rs->vtags)); 2545 m->m_pkthdr.ether_vtag = ALE_RX_VLAN_TAG(vtags); 2546 m->m_flags |= M_VLANTAG; 2547 } 2548 2549 /* Pass it to upper layer. */ 2550 ALE_UNLOCK(sc); 2551 if_input(ifp, m); 2552 ALE_LOCK(sc); 2553 2554 ale_rx_update_page(sc, &rx_page, length, &prod); 2555 } 2556 2557 return (count > 0 ? 0 : EAGAIN); 2558 } 2559 2560 static void 2561 ale_tick(void *arg) 2562 { 2563 struct ale_softc *sc; 2564 struct mii_data *mii; 2565 2566 sc = (struct ale_softc *)arg; 2567 2568 ALE_LOCK_ASSERT(sc); 2569 2570 mii = device_get_softc(sc->ale_miibus); 2571 mii_tick(mii); 2572 ale_stats_update(sc); 2573 /* 2574 * Reclaim Tx buffers that have been transferred. It's not 2575 * needed here but it would release allocated mbuf chains 2576 * faster and limit the maximum delay to a hz. 2577 */ 2578 ale_txeof(sc); 2579 ale_watchdog(sc); 2580 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2581 } 2582 2583 static void 2584 ale_reset(struct ale_softc *sc) 2585 { 2586 uint32_t reg; 2587 int i; 2588 2589 /* Initialize PCIe module. From Linux. */ 2590 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2591 2592 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); 2593 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2594 DELAY(10); 2595 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) 2596 break; 2597 } 2598 if (i == 0) 2599 device_printf(sc->ale_dev, "master reset timeout!\n"); 2600 2601 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2602 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) 2603 break; 2604 DELAY(10); 2605 } 2606 2607 if (i == 0) 2608 device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg); 2609 } 2610 2611 static void 2612 ale_init(void *xsc) 2613 { 2614 struct ale_softc *sc; 2615 2616 sc = (struct ale_softc *)xsc; 2617 ALE_LOCK(sc); 2618 ale_init_locked(sc); 2619 ALE_UNLOCK(sc); 2620 } 2621 2622 static void 2623 ale_init_locked(struct ale_softc *sc) 2624 { 2625 if_t ifp; 2626 struct mii_data *mii; 2627 uint8_t eaddr[ETHER_ADDR_LEN]; 2628 bus_addr_t paddr; 2629 uint32_t reg, rxf_hi, rxf_lo; 2630 2631 ALE_LOCK_ASSERT(sc); 2632 2633 ifp = sc->ale_ifp; 2634 mii = device_get_softc(sc->ale_miibus); 2635 2636 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2637 return; 2638 /* 2639 * Cancel any pending I/O. 2640 */ 2641 ale_stop(sc); 2642 /* 2643 * Reset the chip to a known state. 2644 */ 2645 ale_reset(sc); 2646 /* Initialize Tx descriptors, DMA memory blocks. */ 2647 ale_init_rx_pages(sc); 2648 ale_init_tx_ring(sc); 2649 2650 /* Reprogram the station address. */ 2651 bcopy(if_getlladdr(ifp), eaddr, ETHER_ADDR_LEN); 2652 CSR_WRITE_4(sc, ALE_PAR0, 2653 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2654 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); 2655 /* 2656 * Clear WOL status and disable all WOL feature as WOL 2657 * would interfere Rx operation under normal environments. 2658 */ 2659 CSR_READ_4(sc, ALE_WOL_CFG); 2660 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 2661 /* 2662 * Set Tx descriptor/RXF0/CMB base addresses. They share 2663 * the same high address part of DMAable region. 2664 */ 2665 paddr = sc->ale_cdata.ale_tx_ring_paddr; 2666 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); 2667 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); 2668 CSR_WRITE_4(sc, ALE_TPD_CNT, 2669 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); 2670 /* Set Rx page base address, note we use single queue. */ 2671 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; 2672 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); 2673 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; 2674 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); 2675 /* Set Tx/Rx CMB addresses. */ 2676 paddr = sc->ale_cdata.ale_tx_cmb_paddr; 2677 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); 2678 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; 2679 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); 2680 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; 2681 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); 2682 /* Mark RXF0 is valid. */ 2683 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); 2684 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); 2685 /* 2686 * No need to initialize RFX1/RXF2/RXF3. We don't use 2687 * multi-queue yet. 2688 */ 2689 2690 /* Set Rx page size, excluding guard frame size. */ 2691 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); 2692 /* Tell hardware that we're ready to load DMA blocks. */ 2693 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); 2694 2695 /* Set Rx/Tx interrupt trigger threshold. */ 2696 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | 2697 (4 << INT_TRIG_TX_THRESH_SHIFT)); 2698 /* 2699 * XXX 2700 * Set interrupt trigger timer, its purpose and relation 2701 * with interrupt moderation mechanism is not clear yet. 2702 */ 2703 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, 2704 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | 2705 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); 2706 2707 /* Configure interrupt moderation timer. */ 2708 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; 2709 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; 2710 CSR_WRITE_4(sc, ALE_IM_TIMER, reg); 2711 reg = CSR_READ_4(sc, ALE_MASTER_CFG); 2712 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 2713 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 2714 if (ALE_USECS(sc->ale_int_rx_mod) != 0) 2715 reg |= MASTER_IM_RX_TIMER_ENB; 2716 if (ALE_USECS(sc->ale_int_tx_mod) != 0) 2717 reg |= MASTER_IM_TX_TIMER_ENB; 2718 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); 2719 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); 2720 2721 /* Set Maximum frame size of controller. */ 2722 if (if_getmtu(ifp) < ETHERMTU) 2723 sc->ale_max_frame_size = ETHERMTU; 2724 else 2725 sc->ale_max_frame_size = if_getmtu(ifp); 2726 sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 2727 ETHER_CRC_LEN; 2728 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); 2729 /* Configure IPG/IFG parameters. */ 2730 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, 2731 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 2732 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2733 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2734 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 2735 /* Set parameters for half-duplex media. */ 2736 CSR_WRITE_4(sc, ALE_HDPX_CFG, 2737 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2738 HDPX_CFG_LCOL_MASK) | 2739 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2740 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2741 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2742 HDPX_CFG_ABEBT_MASK) | 2743 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2744 HDPX_CFG_JAMIPG_MASK)); 2745 2746 /* Configure Tx jumbo frame parameters. */ 2747 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2748 if (if_getmtu(ifp) < ETHERMTU) 2749 reg = sc->ale_max_frame_size; 2750 else if (if_getmtu(ifp) < 6 * 1024) 2751 reg = (sc->ale_max_frame_size * 2) / 3; 2752 else 2753 reg = sc->ale_max_frame_size / 2; 2754 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, 2755 roundup(reg, TX_JUMBO_THRESH_UNIT) >> 2756 TX_JUMBO_THRESH_UNIT_SHIFT); 2757 } 2758 /* Configure TxQ. */ 2759 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) 2760 << TXQ_CFG_TX_FIFO_BURST_SHIFT; 2761 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2762 TXQ_CFG_TPD_BURST_MASK; 2763 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); 2764 2765 /* Configure Rx jumbo frame & flow control parameters. */ 2766 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2767 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); 2768 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, 2769 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << 2770 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | 2771 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & 2772 RX_JUMBO_LKAH_MASK)); 2773 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 2774 rxf_hi = (reg * 7) / 10; 2775 rxf_lo = (reg * 3)/ 10; 2776 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, 2777 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2778 RX_FIFO_PAUSE_THRESH_LO_MASK) | 2779 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2780 RX_FIFO_PAUSE_THRESH_HI_MASK)); 2781 } 2782 2783 /* Disable RSS. */ 2784 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); 2785 CSR_WRITE_4(sc, ALE_RSS_CPU, 0); 2786 2787 /* Configure RxQ. */ 2788 CSR_WRITE_4(sc, ALE_RXQ_CFG, 2789 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2790 2791 /* Configure DMA parameters. */ 2792 reg = 0; 2793 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) 2794 reg |= DMA_CFG_TXCMB_ENB; 2795 CSR_WRITE_4(sc, ALE_DMA_CFG, 2796 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | 2797 sc->ale_dma_rd_burst | reg | 2798 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | 2799 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 2800 DMA_CFG_RD_DELAY_CNT_MASK) | 2801 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 2802 DMA_CFG_WR_DELAY_CNT_MASK)); 2803 2804 /* 2805 * Hardware can be configured to issue SMB interrupt based 2806 * on programmed interval. Since there is a callout that is 2807 * invoked for every hz in driver we use that instead of 2808 * relying on periodic SMB interrupt. 2809 */ 2810 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); 2811 /* Clear MAC statistics. */ 2812 ale_stats_clear(sc); 2813 2814 /* 2815 * Configure Tx/Rx MACs. 2816 * - Auto-padding for short frames. 2817 * - Enable CRC generation. 2818 * Actual reconfiguration of MAC for resolved speed/duplex 2819 * is followed after detection of link establishment. 2820 * AR81xx always does checksum computation regardless of 2821 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will 2822 * cause Rx handling issue for fragmented IP datagrams due 2823 * to silicon bug. 2824 */ 2825 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 2826 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2827 MAC_CFG_PREAMBLE_MASK); 2828 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) 2829 reg |= MAC_CFG_SPEED_10_100; 2830 else 2831 reg |= MAC_CFG_SPEED_1000; 2832 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2833 2834 /* Set up the receive filter. */ 2835 ale_rxfilter(sc); 2836 ale_rxvlan(sc); 2837 2838 /* Acknowledge all pending interrupts and clear it. */ 2839 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); 2840 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2841 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); 2842 2843 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 2844 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2845 2846 sc->ale_flags &= ~ALE_FLAG_LINK; 2847 /* Switch to the current media. */ 2848 mii_mediachg(mii); 2849 2850 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2851 } 2852 2853 static void 2854 ale_stop(struct ale_softc *sc) 2855 { 2856 if_t ifp; 2857 struct ale_txdesc *txd; 2858 uint32_t reg; 2859 int i; 2860 2861 ALE_LOCK_ASSERT(sc); 2862 /* 2863 * Mark the interface down and cancel the watchdog timer. 2864 */ 2865 ifp = sc->ale_ifp; 2866 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 2867 sc->ale_flags &= ~ALE_FLAG_LINK; 2868 callout_stop(&sc->ale_tick_ch); 2869 sc->ale_watchdog_timer = 0; 2870 ale_stats_update(sc); 2871 /* Disable interrupts. */ 2872 CSR_WRITE_4(sc, ALE_INTR_MASK, 0); 2873 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2874 /* Disable queue processing and DMA. */ 2875 reg = CSR_READ_4(sc, ALE_TXQ_CFG); 2876 reg &= ~TXQ_CFG_ENB; 2877 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); 2878 reg = CSR_READ_4(sc, ALE_RXQ_CFG); 2879 reg &= ~RXQ_CFG_ENB; 2880 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); 2881 reg = CSR_READ_4(sc, ALE_DMA_CFG); 2882 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); 2883 CSR_WRITE_4(sc, ALE_DMA_CFG, reg); 2884 DELAY(1000); 2885 /* Stop Rx/Tx MACs. */ 2886 ale_stop_mac(sc); 2887 /* Disable interrupts which might be touched in taskq handler. */ 2888 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2889 2890 /* 2891 * Free TX mbufs still in the queues. 2892 */ 2893 for (i = 0; i < ALE_TX_RING_CNT; i++) { 2894 txd = &sc->ale_cdata.ale_txdesc[i]; 2895 if (txd->tx_m != NULL) { 2896 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2897 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2898 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2899 txd->tx_dmamap); 2900 m_freem(txd->tx_m); 2901 txd->tx_m = NULL; 2902 } 2903 } 2904 } 2905 2906 static void 2907 ale_stop_mac(struct ale_softc *sc) 2908 { 2909 uint32_t reg; 2910 int i; 2911 2912 ALE_LOCK_ASSERT(sc); 2913 2914 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2915 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 2916 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 2917 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2918 } 2919 2920 for (i = ALE_TIMEOUT; i > 0; i--) { 2921 reg = CSR_READ_4(sc, ALE_IDLE_STATUS); 2922 if (reg == 0) 2923 break; 2924 DELAY(10); 2925 } 2926 if (i == 0) 2927 device_printf(sc->ale_dev, 2928 "could not disable Tx/Rx MAC(0x%08x)!\n", reg); 2929 } 2930 2931 static void 2932 ale_init_tx_ring(struct ale_softc *sc) 2933 { 2934 struct ale_txdesc *txd; 2935 int i; 2936 2937 ALE_LOCK_ASSERT(sc); 2938 2939 sc->ale_cdata.ale_tx_prod = 0; 2940 sc->ale_cdata.ale_tx_cons = 0; 2941 sc->ale_cdata.ale_tx_cnt = 0; 2942 2943 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ); 2944 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ); 2945 for (i = 0; i < ALE_TX_RING_CNT; i++) { 2946 txd = &sc->ale_cdata.ale_txdesc[i]; 2947 txd->tx_m = NULL; 2948 } 2949 *sc->ale_cdata.ale_tx_cmb = 0; 2950 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2951 sc->ale_cdata.ale_tx_cmb_map, 2952 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2953 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2954 sc->ale_cdata.ale_tx_ring_map, 2955 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2956 } 2957 2958 static void 2959 ale_init_rx_pages(struct ale_softc *sc) 2960 { 2961 struct ale_rx_page *rx_page; 2962 int i; 2963 2964 ALE_LOCK_ASSERT(sc); 2965 2966 sc->ale_morework = 0; 2967 sc->ale_cdata.ale_rx_seqno = 0; 2968 sc->ale_cdata.ale_rx_curp = 0; 2969 2970 for (i = 0; i < ALE_RX_PAGES; i++) { 2971 rx_page = &sc->ale_cdata.ale_rx_page[i]; 2972 bzero(rx_page->page_addr, sc->ale_pagesize); 2973 bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ); 2974 rx_page->cons = 0; 2975 *rx_page->cmb_addr = 0; 2976 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2977 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2978 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2979 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2980 } 2981 } 2982 2983 static void 2984 ale_rxvlan(struct ale_softc *sc) 2985 { 2986 if_t ifp; 2987 uint32_t reg; 2988 2989 ALE_LOCK_ASSERT(sc); 2990 2991 ifp = sc->ale_ifp; 2992 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2993 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2994 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 2995 reg |= MAC_CFG_VLAN_TAG_STRIP; 2996 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2997 } 2998 2999 static u_int 3000 ale_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 3001 { 3002 uint32_t crc, *mchash = arg; 3003 3004 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 3005 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3006 3007 return (1); 3008 } 3009 3010 static void 3011 ale_rxfilter(struct ale_softc *sc) 3012 { 3013 if_t ifp; 3014 uint32_t mchash[2]; 3015 uint32_t rxcfg; 3016 3017 ALE_LOCK_ASSERT(sc); 3018 3019 ifp = sc->ale_ifp; 3020 3021 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); 3022 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3023 if ((if_getflags(ifp) & IFF_BROADCAST) != 0) 3024 rxcfg |= MAC_CFG_BCAST; 3025 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3026 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 3027 rxcfg |= MAC_CFG_PROMISC; 3028 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) 3029 rxcfg |= MAC_CFG_ALLMULTI; 3030 CSR_WRITE_4(sc, ALE_MAR0, 0xFFFFFFFF); 3031 CSR_WRITE_4(sc, ALE_MAR1, 0xFFFFFFFF); 3032 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3033 return; 3034 } 3035 3036 /* Program new filter. */ 3037 bzero(mchash, sizeof(mchash)); 3038 if_foreach_llmaddr(ifp, ale_hash_maddr, &mchash); 3039 3040 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); 3041 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); 3042 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3043 } 3044 3045 static int 3046 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3047 { 3048 int error, value; 3049 3050 if (arg1 == NULL) 3051 return (EINVAL); 3052 value = *(int *)arg1; 3053 error = sysctl_handle_int(oidp, &value, 0, req); 3054 if (error || req->newptr == NULL) 3055 return (error); 3056 if (value < low || value > high) 3057 return (EINVAL); 3058 *(int *)arg1 = value; 3059 3060 return (0); 3061 } 3062 3063 static int 3064 sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS) 3065 { 3066 return (sysctl_int_range(oidp, arg1, arg2, req, 3067 ALE_PROC_MIN, ALE_PROC_MAX)); 3068 } 3069 3070 static int 3071 sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS) 3072 { 3073 3074 return (sysctl_int_range(oidp, arg1, arg2, req, 3075 ALE_IM_TIMER_MIN, ALE_IM_TIMER_MAX)); 3076 } 3077