1 /*- 2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/kernel.h> 38 #include <sys/malloc.h> 39 #include <sys/mbuf.h> 40 #include <sys/module.h> 41 #include <sys/rman.h> 42 #include <sys/queue.h> 43 #include <sys/socket.h> 44 #include <sys/sockio.h> 45 #include <sys/sysctl.h> 46 #include <sys/taskqueue.h> 47 48 #include <net/bpf.h> 49 #include <net/if.h> 50 #include <net/if_arp.h> 51 #include <net/ethernet.h> 52 #include <net/if_dl.h> 53 #include <net/if_llc.h> 54 #include <net/if_media.h> 55 #include <net/if_types.h> 56 #include <net/if_vlan_var.h> 57 58 #include <netinet/in.h> 59 #include <netinet/in_systm.h> 60 #include <netinet/ip.h> 61 #include <netinet/tcp.h> 62 63 #include <dev/mii/mii.h> 64 #include <dev/mii/miivar.h> 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 69 #include <machine/atomic.h> 70 #include <machine/bus.h> 71 #include <machine/in_cksum.h> 72 73 #include <dev/ale/if_alereg.h> 74 #include <dev/ale/if_alevar.h> 75 76 /* "device miibus" required. See GENERIC if you get errors here. */ 77 #include "miibus_if.h" 78 79 /* For more information about Tx checksum offload issues see ale_encap(). */ 80 #define ALE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 81 #ifndef IFCAP_VLAN_HWTSO 82 #define IFCAP_VLAN_HWTSO 0 83 #endif 84 85 MODULE_DEPEND(ale, pci, 1, 1, 1); 86 MODULE_DEPEND(ale, ether, 1, 1, 1); 87 MODULE_DEPEND(ale, miibus, 1, 1, 1); 88 89 /* Tunables. */ 90 static int msi_disable = 0; 91 static int msix_disable = 0; 92 TUNABLE_INT("hw.ale.msi_disable", &msi_disable); 93 TUNABLE_INT("hw.ale.msix_disable", &msix_disable); 94 95 /* 96 * Devices supported by this driver. 97 */ 98 static struct ale_dev { 99 uint16_t ale_vendorid; 100 uint16_t ale_deviceid; 101 const char *ale_name; 102 } ale_devs[] = { 103 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR81XX, 104 "Atheros AR8121/AR8113/AR8114 PCIe Ethernet" }, 105 }; 106 107 static int ale_attach(device_t); 108 static int ale_check_boundary(struct ale_softc *); 109 static int ale_detach(device_t); 110 static int ale_dma_alloc(struct ale_softc *); 111 static void ale_dma_free(struct ale_softc *); 112 static void ale_dmamap_cb(void *, bus_dma_segment_t *, int, int); 113 static int ale_encap(struct ale_softc *, struct mbuf **); 114 static void ale_get_macaddr(struct ale_softc *); 115 static void ale_init(void *); 116 static void ale_init_locked(struct ale_softc *); 117 static void ale_init_rx_pages(struct ale_softc *); 118 static void ale_init_tx_ring(struct ale_softc *); 119 static void ale_int_task(void *, int); 120 static int ale_intr(void *); 121 static int ale_ioctl(struct ifnet *, u_long, caddr_t); 122 static void ale_link_task(void *, int); 123 static void ale_mac_config(struct ale_softc *); 124 static int ale_miibus_readreg(device_t, int, int); 125 static void ale_miibus_statchg(device_t); 126 static int ale_miibus_writereg(device_t, int, int, int); 127 static int ale_mediachange(struct ifnet *); 128 static void ale_mediastatus(struct ifnet *, struct ifmediareq *); 129 static void ale_phy_reset(struct ale_softc *); 130 static int ale_probe(device_t); 131 static void ale_reset(struct ale_softc *); 132 static int ale_resume(device_t); 133 static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, 134 uint32_t, uint32_t *); 135 static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); 136 static int ale_rxeof(struct ale_softc *sc, int); 137 static void ale_rxfilter(struct ale_softc *); 138 static void ale_rxvlan(struct ale_softc *); 139 static void ale_setlinkspeed(struct ale_softc *); 140 static void ale_setwol(struct ale_softc *); 141 static int ale_shutdown(device_t); 142 static void ale_start(struct ifnet *); 143 static void ale_stats_clear(struct ale_softc *); 144 static void ale_stats_update(struct ale_softc *); 145 static void ale_stop(struct ale_softc *); 146 static void ale_stop_mac(struct ale_softc *); 147 static int ale_suspend(device_t); 148 static void ale_sysctl_node(struct ale_softc *); 149 static void ale_tick(void *); 150 static void ale_tx_task(void *, int); 151 static void ale_txeof(struct ale_softc *); 152 static void ale_watchdog(struct ale_softc *); 153 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 154 static int sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS); 155 static int sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS); 156 157 static device_method_t ale_methods[] = { 158 /* Device interface. */ 159 DEVMETHOD(device_probe, ale_probe), 160 DEVMETHOD(device_attach, ale_attach), 161 DEVMETHOD(device_detach, ale_detach), 162 DEVMETHOD(device_shutdown, ale_shutdown), 163 DEVMETHOD(device_suspend, ale_suspend), 164 DEVMETHOD(device_resume, ale_resume), 165 166 /* MII interface. */ 167 DEVMETHOD(miibus_readreg, ale_miibus_readreg), 168 DEVMETHOD(miibus_writereg, ale_miibus_writereg), 169 DEVMETHOD(miibus_statchg, ale_miibus_statchg), 170 171 { NULL, NULL } 172 }; 173 174 static driver_t ale_driver = { 175 "ale", 176 ale_methods, 177 sizeof(struct ale_softc) 178 }; 179 180 static devclass_t ale_devclass; 181 182 DRIVER_MODULE(ale, pci, ale_driver, ale_devclass, 0, 0); 183 DRIVER_MODULE(miibus, ale, miibus_driver, miibus_devclass, 0, 0); 184 185 static struct resource_spec ale_res_spec_mem[] = { 186 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 187 { -1, 0, 0 } 188 }; 189 190 static struct resource_spec ale_irq_spec_legacy[] = { 191 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 192 { -1, 0, 0 } 193 }; 194 195 static struct resource_spec ale_irq_spec_msi[] = { 196 { SYS_RES_IRQ, 1, RF_ACTIVE }, 197 { -1, 0, 0 } 198 }; 199 200 static struct resource_spec ale_irq_spec_msix[] = { 201 { SYS_RES_IRQ, 1, RF_ACTIVE }, 202 { -1, 0, 0 } 203 }; 204 205 static int 206 ale_miibus_readreg(device_t dev, int phy, int reg) 207 { 208 struct ale_softc *sc; 209 uint32_t v; 210 int i; 211 212 sc = device_get_softc(dev); 213 214 if (phy != sc->ale_phyaddr) 215 return (0); 216 217 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 218 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 219 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 220 DELAY(5); 221 v = CSR_READ_4(sc, ALE_MDIO); 222 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 223 break; 224 } 225 226 if (i == 0) { 227 device_printf(sc->ale_dev, "phy read timeout : %d\n", reg); 228 return (0); 229 } 230 231 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 232 } 233 234 static int 235 ale_miibus_writereg(device_t dev, int phy, int reg, int val) 236 { 237 struct ale_softc *sc; 238 uint32_t v; 239 int i; 240 241 sc = device_get_softc(dev); 242 243 if (phy != sc->ale_phyaddr) 244 return (0); 245 246 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 247 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 248 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 249 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 250 DELAY(5); 251 v = CSR_READ_4(sc, ALE_MDIO); 252 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 253 break; 254 } 255 256 if (i == 0) 257 device_printf(sc->ale_dev, "phy write timeout : %d\n", reg); 258 259 return (0); 260 } 261 262 static void 263 ale_miibus_statchg(device_t dev) 264 { 265 struct ale_softc *sc; 266 267 sc = device_get_softc(dev); 268 269 taskqueue_enqueue(taskqueue_swi, &sc->ale_link_task); 270 } 271 272 static void 273 ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 274 { 275 struct ale_softc *sc; 276 struct mii_data *mii; 277 278 sc = ifp->if_softc; 279 ALE_LOCK(sc); 280 mii = device_get_softc(sc->ale_miibus); 281 282 mii_pollstat(mii); 283 ALE_UNLOCK(sc); 284 ifmr->ifm_status = mii->mii_media_status; 285 ifmr->ifm_active = mii->mii_media_active; 286 } 287 288 static int 289 ale_mediachange(struct ifnet *ifp) 290 { 291 struct ale_softc *sc; 292 struct mii_data *mii; 293 struct mii_softc *miisc; 294 int error; 295 296 sc = ifp->if_softc; 297 ALE_LOCK(sc); 298 mii = device_get_softc(sc->ale_miibus); 299 if (mii->mii_instance != 0) { 300 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 301 mii_phy_reset(miisc); 302 } 303 error = mii_mediachg(mii); 304 ALE_UNLOCK(sc); 305 306 return (error); 307 } 308 309 static int 310 ale_probe(device_t dev) 311 { 312 struct ale_dev *sp; 313 int i; 314 uint16_t vendor, devid; 315 316 vendor = pci_get_vendor(dev); 317 devid = pci_get_device(dev); 318 sp = ale_devs; 319 for (i = 0; i < sizeof(ale_devs) / sizeof(ale_devs[0]); i++) { 320 if (vendor == sp->ale_vendorid && 321 devid == sp->ale_deviceid) { 322 device_set_desc(dev, sp->ale_name); 323 return (BUS_PROBE_DEFAULT); 324 } 325 sp++; 326 } 327 328 return (ENXIO); 329 } 330 331 static void 332 ale_get_macaddr(struct ale_softc *sc) 333 { 334 uint32_t ea[2], reg; 335 int i, vpdc; 336 337 reg = CSR_READ_4(sc, ALE_SPI_CTRL); 338 if ((reg & SPI_VPD_ENB) != 0) { 339 reg &= ~SPI_VPD_ENB; 340 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); 341 } 342 343 if (pci_find_extcap(sc->ale_dev, PCIY_VPD, &vpdc) == 0) { 344 /* 345 * PCI VPD capability found, let TWSI reload EEPROM. 346 * This will set ethernet address of controller. 347 */ 348 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | 349 TWSI_CTRL_SW_LD_START); 350 for (i = 100; i > 0; i--) { 351 DELAY(1000); 352 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); 353 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 354 break; 355 } 356 if (i == 0) 357 device_printf(sc->ale_dev, 358 "reloading EEPROM timeout!\n"); 359 } else { 360 if (bootverbose) 361 device_printf(sc->ale_dev, 362 "PCI VPD capability not found!\n"); 363 } 364 365 ea[0] = CSR_READ_4(sc, ALE_PAR0); 366 ea[1] = CSR_READ_4(sc, ALE_PAR1); 367 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; 368 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; 369 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; 370 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; 371 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; 372 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; 373 } 374 375 static void 376 ale_phy_reset(struct ale_softc *sc) 377 { 378 379 /* Reset magic from Linux. */ 380 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 381 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 382 GPHY_CTRL_PHY_PLL_ON); 383 DELAY(1000); 384 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 385 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | 386 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); 387 DELAY(1000); 388 389 #define ATPHY_DBG_ADDR 0x1D 390 #define ATPHY_DBG_DATA 0x1E 391 392 /* Enable hibernation mode. */ 393 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 394 ATPHY_DBG_ADDR, 0x0B); 395 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 396 ATPHY_DBG_DATA, 0xBC00); 397 /* Set Class A/B for all modes. */ 398 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 399 ATPHY_DBG_ADDR, 0x00); 400 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 401 ATPHY_DBG_DATA, 0x02EF); 402 /* Enable 10BT power saving. */ 403 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 404 ATPHY_DBG_ADDR, 0x12); 405 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 406 ATPHY_DBG_DATA, 0x4C04); 407 /* Adjust 1000T power. */ 408 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 409 ATPHY_DBG_ADDR, 0x04); 410 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 411 ATPHY_DBG_ADDR, 0x8BBB); 412 /* 10BT center tap voltage. */ 413 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 414 ATPHY_DBG_ADDR, 0x05); 415 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 416 ATPHY_DBG_ADDR, 0x2C46); 417 418 #undef ATPHY_DBG_ADDR 419 #undef ATPHY_DBG_DATA 420 DELAY(1000); 421 } 422 423 static int 424 ale_attach(device_t dev) 425 { 426 struct ale_softc *sc; 427 struct ifnet *ifp; 428 uint16_t burst; 429 int error, i, msic, msixc, pmc; 430 uint32_t rxf_len, txf_len; 431 432 error = 0; 433 sc = device_get_softc(dev); 434 sc->ale_dev = dev; 435 436 mtx_init(&sc->ale_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 437 MTX_DEF); 438 callout_init_mtx(&sc->ale_tick_ch, &sc->ale_mtx, 0); 439 TASK_INIT(&sc->ale_int_task, 0, ale_int_task, sc); 440 TASK_INIT(&sc->ale_link_task, 0, ale_link_task, sc); 441 442 /* Map the device. */ 443 pci_enable_busmaster(dev); 444 sc->ale_res_spec = ale_res_spec_mem; 445 sc->ale_irq_spec = ale_irq_spec_legacy; 446 error = bus_alloc_resources(dev, sc->ale_res_spec, sc->ale_res); 447 if (error != 0) { 448 device_printf(dev, "cannot allocate memory resources.\n"); 449 goto fail; 450 } 451 452 /* Set PHY address. */ 453 sc->ale_phyaddr = ALE_PHY_ADDR; 454 455 /* Reset PHY. */ 456 ale_phy_reset(sc); 457 458 /* Reset the ethernet controller. */ 459 ale_reset(sc); 460 461 /* Get PCI and chip id/revision. */ 462 sc->ale_rev = pci_get_revid(dev); 463 if (sc->ale_rev >= 0xF0) { 464 /* L2E Rev. B. AR8114 */ 465 sc->ale_flags |= ALE_FLAG_FASTETHER; 466 } else { 467 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { 468 /* L1E AR8121 */ 469 sc->ale_flags |= ALE_FLAG_JUMBO; 470 } else { 471 /* L2E Rev. A. AR8113 */ 472 sc->ale_flags |= ALE_FLAG_FASTETHER; 473 } 474 } 475 /* 476 * All known controllers seems to require 4 bytes alignment 477 * of Tx buffers to make Tx checksum offload with custom 478 * checksum generation method work. 479 */ 480 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; 481 /* 482 * All known controllers seems to have issues on Rx checksum 483 * offload for fragmented IP datagrams. 484 */ 485 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; 486 /* 487 * Don't use Tx CMB. It is known to cause RRS update failure 488 * under certain circumstances. Typical phenomenon of the 489 * issue would be unexpected sequence number encountered in 490 * Rx handler. 491 */ 492 sc->ale_flags |= ALE_FLAG_TXCMB_BUG; 493 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> 494 MASTER_CHIP_REV_SHIFT; 495 if (bootverbose) { 496 device_printf(dev, "PCI device revision : 0x%04x\n", 497 sc->ale_rev); 498 device_printf(dev, "Chip id/revision : 0x%04x\n", 499 sc->ale_chip_rev); 500 } 501 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); 502 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 503 /* 504 * Uninitialized hardware returns an invalid chip id/revision 505 * as well as 0xFFFFFFFF for Tx/Rx fifo length. 506 */ 507 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || 508 rxf_len == 0xFFFFFFF) { 509 device_printf(dev,"chip revision : 0x%04x, %u Tx FIFO " 510 "%u Rx FIFO -- not initialized?\n", sc->ale_chip_rev, 511 txf_len, rxf_len); 512 error = ENXIO; 513 goto fail; 514 } 515 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", txf_len, rxf_len); 516 517 /* Allocate IRQ resources. */ 518 msixc = pci_msix_count(dev); 519 msic = pci_msi_count(dev); 520 if (bootverbose) { 521 device_printf(dev, "MSIX count : %d\n", msixc); 522 device_printf(dev, "MSI count : %d\n", msic); 523 } 524 525 /* Prefer MSIX over MSI. */ 526 if (msix_disable == 0 || msi_disable == 0) { 527 if (msix_disable == 0 && msixc == ALE_MSIX_MESSAGES && 528 pci_alloc_msix(dev, &msixc) == 0) { 529 if (msic == ALE_MSIX_MESSAGES) { 530 device_printf(dev, "Using %d MSIX messages.\n", 531 msixc); 532 sc->ale_flags |= ALE_FLAG_MSIX; 533 sc->ale_irq_spec = ale_irq_spec_msix; 534 } else 535 pci_release_msi(dev); 536 } 537 if (msi_disable == 0 && (sc->ale_flags & ALE_FLAG_MSIX) == 0 && 538 msic == ALE_MSI_MESSAGES && 539 pci_alloc_msi(dev, &msic) == 0) { 540 if (msic == ALE_MSI_MESSAGES) { 541 device_printf(dev, "Using %d MSI messages.\n", 542 msic); 543 sc->ale_flags |= ALE_FLAG_MSI; 544 sc->ale_irq_spec = ale_irq_spec_msi; 545 } else 546 pci_release_msi(dev); 547 } 548 } 549 550 error = bus_alloc_resources(dev, sc->ale_irq_spec, sc->ale_irq); 551 if (error != 0) { 552 device_printf(dev, "cannot allocate IRQ resources.\n"); 553 goto fail; 554 } 555 556 /* Get DMA parameters from PCIe device control register. */ 557 if (pci_find_extcap(dev, PCIY_EXPRESS, &i) == 0) { 558 sc->ale_flags |= ALE_FLAG_PCIE; 559 burst = pci_read_config(dev, i + 0x08, 2); 560 /* Max read request size. */ 561 sc->ale_dma_rd_burst = ((burst >> 12) & 0x07) << 562 DMA_CFG_RD_BURST_SHIFT; 563 /* Max payload size. */ 564 sc->ale_dma_wr_burst = ((burst >> 5) & 0x07) << 565 DMA_CFG_WR_BURST_SHIFT; 566 if (bootverbose) { 567 device_printf(dev, "Read request size : %d bytes.\n", 568 128 << ((burst >> 12) & 0x07)); 569 device_printf(dev, "TLP payload size : %d bytes.\n", 570 128 << ((burst >> 5) & 0x07)); 571 } 572 } else { 573 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; 574 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; 575 } 576 577 /* Create device sysctl node. */ 578 ale_sysctl_node(sc); 579 580 if ((error = ale_dma_alloc(sc) != 0)) 581 goto fail; 582 583 /* Load station address. */ 584 ale_get_macaddr(sc); 585 586 ifp = sc->ale_ifp = if_alloc(IFT_ETHER); 587 if (ifp == NULL) { 588 device_printf(dev, "cannot allocate ifnet structure.\n"); 589 error = ENXIO; 590 goto fail; 591 } 592 593 ifp->if_softc = sc; 594 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 595 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 596 ifp->if_ioctl = ale_ioctl; 597 ifp->if_start = ale_start; 598 ifp->if_init = ale_init; 599 ifp->if_snd.ifq_drv_maxlen = ALE_TX_RING_CNT - 1; 600 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 601 IFQ_SET_READY(&ifp->if_snd); 602 ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4; 603 ifp->if_hwassist = ALE_CSUM_FEATURES | CSUM_TSO; 604 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) { 605 sc->ale_flags |= ALE_FLAG_PMCAP; 606 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 607 } 608 ifp->if_capenable = ifp->if_capabilities; 609 610 /* Set up MII bus. */ 611 if ((error = mii_phy_probe(dev, &sc->ale_miibus, ale_mediachange, 612 ale_mediastatus)) != 0) { 613 device_printf(dev, "no PHY found!\n"); 614 goto fail; 615 } 616 617 ether_ifattach(ifp, sc->ale_eaddr); 618 619 /* VLAN capability setup. */ 620 ifp->if_capabilities |= IFCAP_VLAN_MTU; 621 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM; 622 ifp->if_capenable = ifp->if_capabilities; 623 624 /* Tell the upper layer(s) we support long frames. */ 625 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 626 627 /* Create local taskq. */ 628 TASK_INIT(&sc->ale_tx_task, 1, ale_tx_task, ifp); 629 sc->ale_tq = taskqueue_create_fast("ale_taskq", M_WAITOK, 630 taskqueue_thread_enqueue, &sc->ale_tq); 631 if (sc->ale_tq == NULL) { 632 device_printf(dev, "could not create taskqueue.\n"); 633 ether_ifdetach(ifp); 634 error = ENXIO; 635 goto fail; 636 } 637 taskqueue_start_threads(&sc->ale_tq, 1, PI_NET, "%s taskq", 638 device_get_nameunit(sc->ale_dev)); 639 640 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 641 msic = ALE_MSIX_MESSAGES; 642 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 643 msic = ALE_MSI_MESSAGES; 644 else 645 msic = 1; 646 for (i = 0; i < msic; i++) { 647 error = bus_setup_intr(dev, sc->ale_irq[i], 648 INTR_TYPE_NET | INTR_MPSAFE, ale_intr, NULL, sc, 649 &sc->ale_intrhand[i]); 650 if (error != 0) 651 break; 652 } 653 if (error != 0) { 654 device_printf(dev, "could not set up interrupt handler.\n"); 655 taskqueue_free(sc->ale_tq); 656 sc->ale_tq = NULL; 657 ether_ifdetach(ifp); 658 goto fail; 659 } 660 661 fail: 662 if (error != 0) 663 ale_detach(dev); 664 665 return (error); 666 } 667 668 static int 669 ale_detach(device_t dev) 670 { 671 struct ale_softc *sc; 672 struct ifnet *ifp; 673 int i, msic; 674 675 sc = device_get_softc(dev); 676 677 ifp = sc->ale_ifp; 678 if (device_is_attached(dev)) { 679 ALE_LOCK(sc); 680 sc->ale_flags |= ALE_FLAG_DETACH; 681 ale_stop(sc); 682 ALE_UNLOCK(sc); 683 callout_drain(&sc->ale_tick_ch); 684 taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 685 taskqueue_drain(sc->ale_tq, &sc->ale_tx_task); 686 taskqueue_drain(taskqueue_swi, &sc->ale_link_task); 687 ether_ifdetach(ifp); 688 } 689 690 if (sc->ale_tq != NULL) { 691 taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 692 taskqueue_free(sc->ale_tq); 693 sc->ale_tq = NULL; 694 } 695 696 if (sc->ale_miibus != NULL) { 697 device_delete_child(dev, sc->ale_miibus); 698 sc->ale_miibus = NULL; 699 } 700 bus_generic_detach(dev); 701 ale_dma_free(sc); 702 703 if (ifp != NULL) { 704 if_free(ifp); 705 sc->ale_ifp = NULL; 706 } 707 708 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 709 msic = ALE_MSIX_MESSAGES; 710 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 711 msic = ALE_MSI_MESSAGES; 712 else 713 msic = 1; 714 for (i = 0; i < msic; i++) { 715 if (sc->ale_intrhand[i] != NULL) { 716 bus_teardown_intr(dev, sc->ale_irq[i], 717 sc->ale_intrhand[i]); 718 sc->ale_intrhand[i] = NULL; 719 } 720 } 721 722 bus_release_resources(dev, sc->ale_irq_spec, sc->ale_irq); 723 if ((sc->ale_flags & (ALE_FLAG_MSI | ALE_FLAG_MSIX)) != 0) 724 pci_release_msi(dev); 725 bus_release_resources(dev, sc->ale_res_spec, sc->ale_res); 726 mtx_destroy(&sc->ale_mtx); 727 728 return (0); 729 } 730 731 #define ALE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 732 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 733 734 #if __FreeBSD_version > 800000 735 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 736 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 737 #else 738 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 739 SYSCTL_ADD_ULONG(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 740 #endif 741 742 static void 743 ale_sysctl_node(struct ale_softc *sc) 744 { 745 struct sysctl_ctx_list *ctx; 746 struct sysctl_oid_list *child, *parent; 747 struct sysctl_oid *tree; 748 struct ale_hw_stats *stats; 749 int error; 750 751 stats = &sc->ale_stats; 752 ctx = device_get_sysctl_ctx(sc->ale_dev); 753 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ale_dev)); 754 755 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 756 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_rx_mod, 0, 757 sysctl_hw_ale_int_mod, "I", "ale Rx interrupt moderation"); 758 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 759 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_tx_mod, 0, 760 sysctl_hw_ale_int_mod, "I", "ale Tx interrupt moderation"); 761 /* Pull in device tunables. */ 762 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 763 error = resource_int_value(device_get_name(sc->ale_dev), 764 device_get_unit(sc->ale_dev), "int_rx_mod", &sc->ale_int_rx_mod); 765 if (error == 0) { 766 if (sc->ale_int_rx_mod < ALE_IM_TIMER_MIN || 767 sc->ale_int_rx_mod > ALE_IM_TIMER_MAX) { 768 device_printf(sc->ale_dev, "int_rx_mod value out of " 769 "range; using default: %d\n", 770 ALE_IM_RX_TIMER_DEFAULT); 771 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 772 } 773 } 774 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 775 error = resource_int_value(device_get_name(sc->ale_dev), 776 device_get_unit(sc->ale_dev), "int_tx_mod", &sc->ale_int_tx_mod); 777 if (error == 0) { 778 if (sc->ale_int_tx_mod < ALE_IM_TIMER_MIN || 779 sc->ale_int_tx_mod > ALE_IM_TIMER_MAX) { 780 device_printf(sc->ale_dev, "int_tx_mod value out of " 781 "range; using default: %d\n", 782 ALE_IM_TX_TIMER_DEFAULT); 783 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 784 } 785 } 786 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 787 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_process_limit, 0, 788 sysctl_hw_ale_proc_limit, "I", 789 "max number of Rx events to process"); 790 /* Pull in device tunables. */ 791 sc->ale_process_limit = ALE_PROC_DEFAULT; 792 error = resource_int_value(device_get_name(sc->ale_dev), 793 device_get_unit(sc->ale_dev), "process_limit", 794 &sc->ale_process_limit); 795 if (error == 0) { 796 if (sc->ale_process_limit < ALE_PROC_MIN || 797 sc->ale_process_limit > ALE_PROC_MAX) { 798 device_printf(sc->ale_dev, 799 "process_limit value out of range; " 800 "using default: %d\n", ALE_PROC_DEFAULT); 801 sc->ale_process_limit = ALE_PROC_DEFAULT; 802 } 803 } 804 805 /* Misc statistics. */ 806 ALE_SYSCTL_STAT_ADD32(ctx, child, "reset_brk_seq", 807 &stats->reset_brk_seq, 808 "Controller resets due to broken Rx sequnce number"); 809 810 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 811 NULL, "ATE statistics"); 812 parent = SYSCTL_CHILDREN(tree); 813 814 /* Rx statistics. */ 815 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 816 NULL, "Rx MAC statistics"); 817 child = SYSCTL_CHILDREN(tree); 818 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 819 &stats->rx_frames, "Good frames"); 820 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 821 &stats->rx_bcast_frames, "Good broadcast frames"); 822 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 823 &stats->rx_mcast_frames, "Good multicast frames"); 824 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 825 &stats->rx_pause_frames, "Pause control frames"); 826 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 827 &stats->rx_control_frames, "Control frames"); 828 ALE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 829 &stats->rx_crcerrs, "CRC errors"); 830 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 831 &stats->rx_lenerrs, "Frames with length mismatched"); 832 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 833 &stats->rx_bytes, "Good octets"); 834 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 835 &stats->rx_bcast_bytes, "Good broadcast octets"); 836 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 837 &stats->rx_mcast_bytes, "Good multicast octets"); 838 ALE_SYSCTL_STAT_ADD32(ctx, child, "runts", 839 &stats->rx_runts, "Too short frames"); 840 ALE_SYSCTL_STAT_ADD32(ctx, child, "fragments", 841 &stats->rx_fragments, "Fragmented frames"); 842 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 843 &stats->rx_pkts_64, "64 bytes frames"); 844 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 845 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 846 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 847 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 848 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 849 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 850 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 851 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 852 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 853 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 854 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 855 &stats->rx_pkts_1519_max, "1519 to max frames"); 856 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 857 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 858 ALE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 859 &stats->rx_fifo_oflows, "FIFO overflows"); 860 ALE_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 861 &stats->rx_rrs_errs, "Return status write-back errors"); 862 ALE_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 863 &stats->rx_alignerrs, "Alignment errors"); 864 ALE_SYSCTL_STAT_ADD32(ctx, child, "filtered", 865 &stats->rx_pkts_filtered, 866 "Frames dropped due to address filtering"); 867 868 /* Tx statistics. */ 869 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 870 NULL, "Tx MAC statistics"); 871 child = SYSCTL_CHILDREN(tree); 872 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 873 &stats->tx_frames, "Good frames"); 874 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 875 &stats->tx_bcast_frames, "Good broadcast frames"); 876 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 877 &stats->tx_mcast_frames, "Good multicast frames"); 878 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 879 &stats->tx_pause_frames, "Pause control frames"); 880 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 881 &stats->tx_control_frames, "Control frames"); 882 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 883 &stats->tx_excess_defer, "Frames with excessive derferrals"); 884 ALE_SYSCTL_STAT_ADD32(ctx, child, "defers", 885 &stats->tx_excess_defer, "Frames with derferrals"); 886 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 887 &stats->tx_bytes, "Good octets"); 888 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 889 &stats->tx_bcast_bytes, "Good broadcast octets"); 890 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 891 &stats->tx_mcast_bytes, "Good multicast octets"); 892 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 893 &stats->tx_pkts_64, "64 bytes frames"); 894 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 895 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 896 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 897 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 898 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 899 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 900 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 901 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 902 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 903 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 904 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 905 &stats->tx_pkts_1519_max, "1519 to max frames"); 906 ALE_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 907 &stats->tx_single_colls, "Single collisions"); 908 ALE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 909 &stats->tx_multi_colls, "Multiple collisions"); 910 ALE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 911 &stats->tx_late_colls, "Late collisions"); 912 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 913 &stats->tx_excess_colls, "Excessive collisions"); 914 ALE_SYSCTL_STAT_ADD32(ctx, child, "abort", 915 &stats->tx_abort, "Aborted frames due to Excessive collisions"); 916 ALE_SYSCTL_STAT_ADD32(ctx, child, "underruns", 917 &stats->tx_underrun, "FIFO underruns"); 918 ALE_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 919 &stats->tx_desc_underrun, "Descriptor write-back errors"); 920 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 921 &stats->tx_lenerrs, "Frames with length mismatched"); 922 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 923 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 924 } 925 926 #undef ALE_SYSCTL_STAT_ADD32 927 #undef ALE_SYSCTL_STAT_ADD64 928 929 struct ale_dmamap_arg { 930 bus_addr_t ale_busaddr; 931 }; 932 933 static void 934 ale_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 935 { 936 struct ale_dmamap_arg *ctx; 937 938 if (error != 0) 939 return; 940 941 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 942 943 ctx = (struct ale_dmamap_arg *)arg; 944 ctx->ale_busaddr = segs[0].ds_addr; 945 } 946 947 /* 948 * Tx descriptors/RXF0/CMB DMA blocks share ALE_DESC_ADDR_HI register 949 * which specifies high address region of DMA blocks. Therefore these 950 * blocks should have the same high address of given 4GB address 951 * space(i.e. crossing 4GB boundary is not allowed). 952 */ 953 static int 954 ale_check_boundary(struct ale_softc *sc) 955 { 956 bus_addr_t rx_cmb_end[ALE_RX_PAGES], tx_cmb_end; 957 bus_addr_t rx_page_end[ALE_RX_PAGES], tx_ring_end; 958 959 rx_page_end[0] = sc->ale_cdata.ale_rx_page[0].page_paddr + 960 sc->ale_pagesize; 961 rx_page_end[1] = sc->ale_cdata.ale_rx_page[1].page_paddr + 962 sc->ale_pagesize; 963 tx_ring_end = sc->ale_cdata.ale_tx_ring_paddr + ALE_TX_RING_SZ; 964 tx_cmb_end = sc->ale_cdata.ale_tx_cmb_paddr + ALE_TX_CMB_SZ; 965 rx_cmb_end[0] = sc->ale_cdata.ale_rx_page[0].cmb_paddr + ALE_RX_CMB_SZ; 966 rx_cmb_end[1] = sc->ale_cdata.ale_rx_page[1].cmb_paddr + ALE_RX_CMB_SZ; 967 968 if ((ALE_ADDR_HI(tx_ring_end) != 969 ALE_ADDR_HI(sc->ale_cdata.ale_tx_ring_paddr)) || 970 (ALE_ADDR_HI(rx_page_end[0]) != 971 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].page_paddr)) || 972 (ALE_ADDR_HI(rx_page_end[1]) != 973 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].page_paddr)) || 974 (ALE_ADDR_HI(tx_cmb_end) != 975 ALE_ADDR_HI(sc->ale_cdata.ale_tx_cmb_paddr)) || 976 (ALE_ADDR_HI(rx_cmb_end[0]) != 977 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].cmb_paddr)) || 978 (ALE_ADDR_HI(rx_cmb_end[1]) != 979 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].cmb_paddr))) 980 return (EFBIG); 981 982 if ((ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[0])) || 983 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[1])) || 984 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[0])) || 985 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[1])) || 986 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(tx_cmb_end))) 987 return (EFBIG); 988 989 return (0); 990 } 991 992 static int 993 ale_dma_alloc(struct ale_softc *sc) 994 { 995 struct ale_txdesc *txd; 996 bus_addr_t lowaddr; 997 struct ale_dmamap_arg ctx; 998 int error, guard_size, i; 999 1000 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 1001 guard_size = ALE_JUMBO_FRAMELEN; 1002 else 1003 guard_size = ALE_MAX_FRAMELEN; 1004 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, 1005 ALE_RX_PAGE_ALIGN); 1006 lowaddr = BUS_SPACE_MAXADDR; 1007 again: 1008 /* Create parent DMA tag. */ 1009 error = bus_dma_tag_create( 1010 bus_get_dma_tag(sc->ale_dev), /* parent */ 1011 1, 0, /* alignment, boundary */ 1012 lowaddr, /* lowaddr */ 1013 BUS_SPACE_MAXADDR, /* highaddr */ 1014 NULL, NULL, /* filter, filterarg */ 1015 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1016 0, /* nsegments */ 1017 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1018 0, /* flags */ 1019 NULL, NULL, /* lockfunc, lockarg */ 1020 &sc->ale_cdata.ale_parent_tag); 1021 if (error != 0) { 1022 device_printf(sc->ale_dev, 1023 "could not create parent DMA tag.\n"); 1024 goto fail; 1025 } 1026 1027 /* Create DMA tag for Tx descriptor ring. */ 1028 error = bus_dma_tag_create( 1029 sc->ale_cdata.ale_parent_tag, /* parent */ 1030 ALE_TX_RING_ALIGN, 0, /* alignment, boundary */ 1031 BUS_SPACE_MAXADDR, /* lowaddr */ 1032 BUS_SPACE_MAXADDR, /* highaddr */ 1033 NULL, NULL, /* filter, filterarg */ 1034 ALE_TX_RING_SZ, /* maxsize */ 1035 1, /* nsegments */ 1036 ALE_TX_RING_SZ, /* maxsegsize */ 1037 0, /* flags */ 1038 NULL, NULL, /* lockfunc, lockarg */ 1039 &sc->ale_cdata.ale_tx_ring_tag); 1040 if (error != 0) { 1041 device_printf(sc->ale_dev, 1042 "could not create Tx ring DMA tag.\n"); 1043 goto fail; 1044 } 1045 1046 /* Create DMA tag for Rx pages. */ 1047 for (i = 0; i < ALE_RX_PAGES; i++) { 1048 error = bus_dma_tag_create( 1049 sc->ale_cdata.ale_parent_tag, /* parent */ 1050 ALE_RX_PAGE_ALIGN, 0, /* alignment, boundary */ 1051 BUS_SPACE_MAXADDR, /* lowaddr */ 1052 BUS_SPACE_MAXADDR, /* highaddr */ 1053 NULL, NULL, /* filter, filterarg */ 1054 sc->ale_pagesize, /* maxsize */ 1055 1, /* nsegments */ 1056 sc->ale_pagesize, /* maxsegsize */ 1057 0, /* flags */ 1058 NULL, NULL, /* lockfunc, lockarg */ 1059 &sc->ale_cdata.ale_rx_page[i].page_tag); 1060 if (error != 0) { 1061 device_printf(sc->ale_dev, 1062 "could not create Rx page %d DMA tag.\n", i); 1063 goto fail; 1064 } 1065 } 1066 1067 /* Create DMA tag for Tx coalescing message block. */ 1068 error = bus_dma_tag_create( 1069 sc->ale_cdata.ale_parent_tag, /* parent */ 1070 ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1071 BUS_SPACE_MAXADDR, /* lowaddr */ 1072 BUS_SPACE_MAXADDR, /* highaddr */ 1073 NULL, NULL, /* filter, filterarg */ 1074 ALE_TX_CMB_SZ, /* maxsize */ 1075 1, /* nsegments */ 1076 ALE_TX_CMB_SZ, /* maxsegsize */ 1077 0, /* flags */ 1078 NULL, NULL, /* lockfunc, lockarg */ 1079 &sc->ale_cdata.ale_tx_cmb_tag); 1080 if (error != 0) { 1081 device_printf(sc->ale_dev, 1082 "could not create Tx CMB DMA tag.\n"); 1083 goto fail; 1084 } 1085 1086 /* Create DMA tag for Rx coalescing message block. */ 1087 for (i = 0; i < ALE_RX_PAGES; i++) { 1088 error = bus_dma_tag_create( 1089 sc->ale_cdata.ale_parent_tag, /* parent */ 1090 ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1091 BUS_SPACE_MAXADDR, /* lowaddr */ 1092 BUS_SPACE_MAXADDR, /* highaddr */ 1093 NULL, NULL, /* filter, filterarg */ 1094 ALE_RX_CMB_SZ, /* maxsize */ 1095 1, /* nsegments */ 1096 ALE_RX_CMB_SZ, /* maxsegsize */ 1097 0, /* flags */ 1098 NULL, NULL, /* lockfunc, lockarg */ 1099 &sc->ale_cdata.ale_rx_page[i].cmb_tag); 1100 if (error != 0) { 1101 device_printf(sc->ale_dev, 1102 "could not create Rx page %d CMB DMA tag.\n", i); 1103 goto fail; 1104 } 1105 } 1106 1107 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1108 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_ring_tag, 1109 (void **)&sc->ale_cdata.ale_tx_ring, 1110 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1111 &sc->ale_cdata.ale_tx_ring_map); 1112 if (error != 0) { 1113 device_printf(sc->ale_dev, 1114 "could not allocate DMA'able memory for Tx ring.\n"); 1115 goto fail; 1116 } 1117 ctx.ale_busaddr = 0; 1118 error = bus_dmamap_load(sc->ale_cdata.ale_tx_ring_tag, 1119 sc->ale_cdata.ale_tx_ring_map, sc->ale_cdata.ale_tx_ring, 1120 ALE_TX_RING_SZ, ale_dmamap_cb, &ctx, 0); 1121 if (error != 0 || ctx.ale_busaddr == 0) { 1122 device_printf(sc->ale_dev, 1123 "could not load DMA'able memory for Tx ring.\n"); 1124 goto fail; 1125 } 1126 sc->ale_cdata.ale_tx_ring_paddr = ctx.ale_busaddr; 1127 1128 /* Rx pages. */ 1129 for (i = 0; i < ALE_RX_PAGES; i++) { 1130 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].page_tag, 1131 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr, 1132 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1133 &sc->ale_cdata.ale_rx_page[i].page_map); 1134 if (error != 0) { 1135 device_printf(sc->ale_dev, 1136 "could not allocate DMA'able memory for " 1137 "Rx page %d.\n", i); 1138 goto fail; 1139 } 1140 ctx.ale_busaddr = 0; 1141 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].page_tag, 1142 sc->ale_cdata.ale_rx_page[i].page_map, 1143 sc->ale_cdata.ale_rx_page[i].page_addr, 1144 sc->ale_pagesize, ale_dmamap_cb, &ctx, 0); 1145 if (error != 0 || ctx.ale_busaddr == 0) { 1146 device_printf(sc->ale_dev, 1147 "could not load DMA'able memory for " 1148 "Rx page %d.\n", i); 1149 goto fail; 1150 } 1151 sc->ale_cdata.ale_rx_page[i].page_paddr = ctx.ale_busaddr; 1152 } 1153 1154 /* Tx CMB. */ 1155 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_cmb_tag, 1156 (void **)&sc->ale_cdata.ale_tx_cmb, 1157 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1158 &sc->ale_cdata.ale_tx_cmb_map); 1159 if (error != 0) { 1160 device_printf(sc->ale_dev, 1161 "could not allocate DMA'able memory for Tx CMB.\n"); 1162 goto fail; 1163 } 1164 ctx.ale_busaddr = 0; 1165 error = bus_dmamap_load(sc->ale_cdata.ale_tx_cmb_tag, 1166 sc->ale_cdata.ale_tx_cmb_map, sc->ale_cdata.ale_tx_cmb, 1167 ALE_TX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1168 if (error != 0 || ctx.ale_busaddr == 0) { 1169 device_printf(sc->ale_dev, 1170 "could not load DMA'able memory for Tx CMB.\n"); 1171 goto fail; 1172 } 1173 sc->ale_cdata.ale_tx_cmb_paddr = ctx.ale_busaddr; 1174 1175 /* Rx CMB. */ 1176 for (i = 0; i < ALE_RX_PAGES; i++) { 1177 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1178 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 1179 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1180 &sc->ale_cdata.ale_rx_page[i].cmb_map); 1181 if (error != 0) { 1182 device_printf(sc->ale_dev, "could not allocate " 1183 "DMA'able memory for Rx page %d CMB.\n", i); 1184 goto fail; 1185 } 1186 ctx.ale_busaddr = 0; 1187 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1188 sc->ale_cdata.ale_rx_page[i].cmb_map, 1189 sc->ale_cdata.ale_rx_page[i].cmb_addr, 1190 ALE_RX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1191 if (error != 0 || ctx.ale_busaddr == 0) { 1192 device_printf(sc->ale_dev, "could not load DMA'able " 1193 "memory for Rx page %d CMB.\n", i); 1194 goto fail; 1195 } 1196 sc->ale_cdata.ale_rx_page[i].cmb_paddr = ctx.ale_busaddr; 1197 } 1198 1199 /* 1200 * Tx descriptors/RXF0/CMB DMA blocks share the same 1201 * high address region of 64bit DMA address space. 1202 */ 1203 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1204 (error = ale_check_boundary(sc)) != 0) { 1205 device_printf(sc->ale_dev, "4GB boundary crossed, " 1206 "switching to 32bit DMA addressing mode.\n"); 1207 ale_dma_free(sc); 1208 /* 1209 * Limit max allowable DMA address space to 32bit 1210 * and try again. 1211 */ 1212 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1213 goto again; 1214 } 1215 1216 /* 1217 * Create Tx buffer parent tag. 1218 * AR81xx allows 64bit DMA addressing of Tx buffers so it 1219 * needs separate parent DMA tag as parent DMA address space 1220 * could be restricted to be within 32bit address space by 1221 * 4GB boundary crossing. 1222 */ 1223 error = bus_dma_tag_create( 1224 bus_get_dma_tag(sc->ale_dev), /* parent */ 1225 1, 0, /* alignment, boundary */ 1226 BUS_SPACE_MAXADDR, /* lowaddr */ 1227 BUS_SPACE_MAXADDR, /* highaddr */ 1228 NULL, NULL, /* filter, filterarg */ 1229 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1230 0, /* nsegments */ 1231 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1232 0, /* flags */ 1233 NULL, NULL, /* lockfunc, lockarg */ 1234 &sc->ale_cdata.ale_buffer_tag); 1235 if (error != 0) { 1236 device_printf(sc->ale_dev, 1237 "could not create parent buffer DMA tag.\n"); 1238 goto fail; 1239 } 1240 1241 /* Create DMA tag for Tx buffers. */ 1242 error = bus_dma_tag_create( 1243 sc->ale_cdata.ale_buffer_tag, /* parent */ 1244 1, 0, /* alignment, boundary */ 1245 BUS_SPACE_MAXADDR, /* lowaddr */ 1246 BUS_SPACE_MAXADDR, /* highaddr */ 1247 NULL, NULL, /* filter, filterarg */ 1248 ALE_TSO_MAXSIZE, /* maxsize */ 1249 ALE_MAXTXSEGS, /* nsegments */ 1250 ALE_TSO_MAXSEGSIZE, /* maxsegsize */ 1251 0, /* flags */ 1252 NULL, NULL, /* lockfunc, lockarg */ 1253 &sc->ale_cdata.ale_tx_tag); 1254 if (error != 0) { 1255 device_printf(sc->ale_dev, "could not create Tx DMA tag.\n"); 1256 goto fail; 1257 } 1258 1259 /* Create DMA maps for Tx buffers. */ 1260 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1261 txd = &sc->ale_cdata.ale_txdesc[i]; 1262 txd->tx_m = NULL; 1263 txd->tx_dmamap = NULL; 1264 error = bus_dmamap_create(sc->ale_cdata.ale_tx_tag, 0, 1265 &txd->tx_dmamap); 1266 if (error != 0) { 1267 device_printf(sc->ale_dev, 1268 "could not create Tx dmamap.\n"); 1269 goto fail; 1270 } 1271 } 1272 1273 fail: 1274 return (error); 1275 } 1276 1277 static void 1278 ale_dma_free(struct ale_softc *sc) 1279 { 1280 struct ale_txdesc *txd; 1281 int i; 1282 1283 /* Tx buffers. */ 1284 if (sc->ale_cdata.ale_tx_tag != NULL) { 1285 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1286 txd = &sc->ale_cdata.ale_txdesc[i]; 1287 if (txd->tx_dmamap != NULL) { 1288 bus_dmamap_destroy(sc->ale_cdata.ale_tx_tag, 1289 txd->tx_dmamap); 1290 txd->tx_dmamap = NULL; 1291 } 1292 } 1293 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_tag); 1294 sc->ale_cdata.ale_tx_tag = NULL; 1295 } 1296 /* Tx descriptor ring. */ 1297 if (sc->ale_cdata.ale_tx_ring_tag != NULL) { 1298 if (sc->ale_cdata.ale_tx_ring_map != NULL) 1299 bus_dmamap_unload(sc->ale_cdata.ale_tx_ring_tag, 1300 sc->ale_cdata.ale_tx_ring_map); 1301 if (sc->ale_cdata.ale_tx_ring_map != NULL && 1302 sc->ale_cdata.ale_tx_ring != NULL) 1303 bus_dmamem_free(sc->ale_cdata.ale_tx_ring_tag, 1304 sc->ale_cdata.ale_tx_ring, 1305 sc->ale_cdata.ale_tx_ring_map); 1306 sc->ale_cdata.ale_tx_ring = NULL; 1307 sc->ale_cdata.ale_tx_ring_map = NULL; 1308 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_ring_tag); 1309 sc->ale_cdata.ale_tx_ring_tag = NULL; 1310 } 1311 /* Rx page block. */ 1312 for (i = 0; i < ALE_RX_PAGES; i++) { 1313 if (sc->ale_cdata.ale_rx_page[i].page_tag != NULL) { 1314 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL) 1315 bus_dmamap_unload( 1316 sc->ale_cdata.ale_rx_page[i].page_tag, 1317 sc->ale_cdata.ale_rx_page[i].page_map); 1318 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL && 1319 sc->ale_cdata.ale_rx_page[i].page_addr != NULL) 1320 bus_dmamem_free( 1321 sc->ale_cdata.ale_rx_page[i].page_tag, 1322 sc->ale_cdata.ale_rx_page[i].page_addr, 1323 sc->ale_cdata.ale_rx_page[i].page_map); 1324 sc->ale_cdata.ale_rx_page[i].page_addr = NULL; 1325 sc->ale_cdata.ale_rx_page[i].page_map = NULL; 1326 bus_dma_tag_destroy( 1327 sc->ale_cdata.ale_rx_page[i].page_tag); 1328 sc->ale_cdata.ale_rx_page[i].page_tag = NULL; 1329 } 1330 } 1331 /* Rx CMB. */ 1332 for (i = 0; i < ALE_RX_PAGES; i++) { 1333 if (sc->ale_cdata.ale_rx_page[i].cmb_tag != NULL) { 1334 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL) 1335 bus_dmamap_unload( 1336 sc->ale_cdata.ale_rx_page[i].cmb_tag, 1337 sc->ale_cdata.ale_rx_page[i].cmb_map); 1338 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL && 1339 sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) 1340 bus_dmamem_free( 1341 sc->ale_cdata.ale_rx_page[i].cmb_tag, 1342 sc->ale_cdata.ale_rx_page[i].cmb_addr, 1343 sc->ale_cdata.ale_rx_page[i].cmb_map); 1344 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; 1345 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL; 1346 bus_dma_tag_destroy( 1347 sc->ale_cdata.ale_rx_page[i].cmb_tag); 1348 sc->ale_cdata.ale_rx_page[i].cmb_tag = NULL; 1349 } 1350 } 1351 /* Tx CMB. */ 1352 if (sc->ale_cdata.ale_tx_cmb_tag != NULL) { 1353 if (sc->ale_cdata.ale_tx_cmb_map != NULL) 1354 bus_dmamap_unload(sc->ale_cdata.ale_tx_cmb_tag, 1355 sc->ale_cdata.ale_tx_cmb_map); 1356 if (sc->ale_cdata.ale_tx_cmb_map != NULL && 1357 sc->ale_cdata.ale_tx_cmb != NULL) 1358 bus_dmamem_free(sc->ale_cdata.ale_tx_cmb_tag, 1359 sc->ale_cdata.ale_tx_cmb, 1360 sc->ale_cdata.ale_tx_cmb_map); 1361 sc->ale_cdata.ale_tx_cmb = NULL; 1362 sc->ale_cdata.ale_tx_cmb_map = NULL; 1363 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_cmb_tag); 1364 sc->ale_cdata.ale_tx_cmb_tag = NULL; 1365 } 1366 if (sc->ale_cdata.ale_buffer_tag != NULL) { 1367 bus_dma_tag_destroy(sc->ale_cdata.ale_buffer_tag); 1368 sc->ale_cdata.ale_buffer_tag = NULL; 1369 } 1370 if (sc->ale_cdata.ale_parent_tag != NULL) { 1371 bus_dma_tag_destroy(sc->ale_cdata.ale_parent_tag); 1372 sc->ale_cdata.ale_parent_tag = NULL; 1373 } 1374 } 1375 1376 static int 1377 ale_shutdown(device_t dev) 1378 { 1379 1380 return (ale_suspend(dev)); 1381 } 1382 1383 /* 1384 * Note, this driver resets the link speed to 10/100Mbps by 1385 * restarting auto-negotiation in suspend/shutdown phase but we 1386 * don't know whether that auto-negotiation would succeed or not 1387 * as driver has no control after powering off/suspend operation. 1388 * If the renegotiation fail WOL may not work. Running at 1Gbps 1389 * will draw more power than 375mA at 3.3V which is specified in 1390 * PCI specification and that would result in complete 1391 * shutdowning power to ethernet controller. 1392 * 1393 * TODO 1394 * Save current negotiated media speed/duplex/flow-control to 1395 * softc and restore the same link again after resuming. PHY 1396 * handling such as power down/resetting to 100Mbps may be better 1397 * handled in suspend method in phy driver. 1398 */ 1399 static void 1400 ale_setlinkspeed(struct ale_softc *sc) 1401 { 1402 struct mii_data *mii; 1403 int aneg, i; 1404 1405 mii = device_get_softc(sc->ale_miibus); 1406 mii_pollstat(mii); 1407 aneg = 0; 1408 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1409 (IFM_ACTIVE | IFM_AVALID)) { 1410 switch IFM_SUBTYPE(mii->mii_media_active) { 1411 case IFM_10_T: 1412 case IFM_100_TX: 1413 return; 1414 case IFM_1000_T: 1415 aneg++; 1416 break; 1417 default: 1418 break; 1419 } 1420 } 1421 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_100T2CR, 0); 1422 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1423 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1424 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1425 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1426 DELAY(1000); 1427 if (aneg != 0) { 1428 /* 1429 * Poll link state until ale(4) get a 10/100Mbps link. 1430 */ 1431 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1432 mii_pollstat(mii); 1433 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 1434 == (IFM_ACTIVE | IFM_AVALID)) { 1435 switch (IFM_SUBTYPE( 1436 mii->mii_media_active)) { 1437 case IFM_10_T: 1438 case IFM_100_TX: 1439 ale_mac_config(sc); 1440 return; 1441 default: 1442 break; 1443 } 1444 } 1445 ALE_UNLOCK(sc); 1446 pause("alelnk", hz); 1447 ALE_LOCK(sc); 1448 } 1449 if (i == MII_ANEGTICKS_GIGE) 1450 device_printf(sc->ale_dev, 1451 "establishing a link failed, WOL may not work!"); 1452 } 1453 /* 1454 * No link, force MAC to have 100Mbps, full-duplex link. 1455 * This is the last resort and may/may not work. 1456 */ 1457 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1458 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1459 ale_mac_config(sc); 1460 } 1461 1462 static void 1463 ale_setwol(struct ale_softc *sc) 1464 { 1465 struct ifnet *ifp; 1466 uint32_t reg, pmcs; 1467 uint16_t pmstat; 1468 int pmc; 1469 1470 ALE_LOCK_ASSERT(sc); 1471 1472 if (pci_find_extcap(sc->ale_dev, PCIY_PMG, &pmc) != 0) { 1473 /* Disable WOL. */ 1474 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 1475 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1476 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1477 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1478 /* Force PHY power down. */ 1479 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1480 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1481 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_PHY_PLL_ON | 1482 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_IDDQ | 1483 GPHY_CTRL_PCLK_SEL_DIS | GPHY_CTRL_PWDOWN_HW); 1484 return; 1485 } 1486 1487 ifp = sc->ale_ifp; 1488 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1489 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 1490 ale_setlinkspeed(sc); 1491 } 1492 1493 pmcs = 0; 1494 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1495 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1496 CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs); 1497 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1498 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 1499 MAC_CFG_BCAST); 1500 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1501 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1502 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1503 reg |= MAC_CFG_RX_ENB; 1504 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1505 1506 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1507 /* WOL disabled, PHY power down. */ 1508 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1509 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1510 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1511 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1512 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1513 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 1514 GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PCLK_SEL_DIS | 1515 GPHY_CTRL_PWDOWN_HW); 1516 } 1517 /* Request PME. */ 1518 pmstat = pci_read_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, 2); 1519 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1520 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1521 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1522 pci_write_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1523 } 1524 1525 static int 1526 ale_suspend(device_t dev) 1527 { 1528 struct ale_softc *sc; 1529 1530 sc = device_get_softc(dev); 1531 1532 ALE_LOCK(sc); 1533 ale_stop(sc); 1534 ale_setwol(sc); 1535 ALE_UNLOCK(sc); 1536 1537 return (0); 1538 } 1539 1540 static int 1541 ale_resume(device_t dev) 1542 { 1543 struct ale_softc *sc; 1544 struct ifnet *ifp; 1545 int pmc; 1546 uint16_t pmstat; 1547 1548 sc = device_get_softc(dev); 1549 1550 ALE_LOCK(sc); 1551 if (pci_find_extcap(sc->ale_dev, PCIY_PMG, &pmc) == 0) { 1552 /* Disable PME and clear PME status. */ 1553 pmstat = pci_read_config(sc->ale_dev, 1554 pmc + PCIR_POWER_STATUS, 2); 1555 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 1556 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1557 pci_write_config(sc->ale_dev, 1558 pmc + PCIR_POWER_STATUS, pmstat, 2); 1559 } 1560 } 1561 /* Reset PHY. */ 1562 ale_phy_reset(sc); 1563 ifp = sc->ale_ifp; 1564 if ((ifp->if_flags & IFF_UP) != 0) { 1565 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1566 ale_init_locked(sc); 1567 } 1568 ALE_UNLOCK(sc); 1569 1570 return (0); 1571 } 1572 1573 static int 1574 ale_encap(struct ale_softc *sc, struct mbuf **m_head) 1575 { 1576 struct ale_txdesc *txd, *txd_last; 1577 struct tx_desc *desc; 1578 struct mbuf *m; 1579 struct ip *ip; 1580 struct tcphdr *tcp; 1581 bus_dma_segment_t txsegs[ALE_MAXTXSEGS]; 1582 bus_dmamap_t map; 1583 uint32_t cflags, ip_off, poff, vtag; 1584 int error, i, nsegs, prod, si; 1585 1586 ALE_LOCK_ASSERT(sc); 1587 1588 M_ASSERTPKTHDR((*m_head)); 1589 1590 m = *m_head; 1591 ip = NULL; 1592 tcp = NULL; 1593 cflags = vtag = 0; 1594 ip_off = poff = 0; 1595 if ((m->m_pkthdr.csum_flags & (ALE_CSUM_FEATURES | CSUM_TSO)) != 0) { 1596 /* 1597 * AR81xx requires offset of TCP/UDP payload in its Tx 1598 * descriptor to perform hardware Tx checksum offload. 1599 * Additionally, TSO requires IP/TCP header size and 1600 * modification of IP/TCP header in order to make TSO 1601 * engine work. This kind of operation takes many CPU 1602 * cycles on FreeBSD so fast host CPU is required to 1603 * get smooth TSO performance. 1604 */ 1605 struct ether_header *eh; 1606 1607 if (M_WRITABLE(m) == 0) { 1608 /* Get a writable copy. */ 1609 m = m_dup(*m_head, M_DONTWAIT); 1610 /* Release original mbufs. */ 1611 m_freem(*m_head); 1612 if (m == NULL) { 1613 *m_head = NULL; 1614 return (ENOBUFS); 1615 } 1616 *m_head = m; 1617 } 1618 1619 /* 1620 * Buggy-controller requires 4 byte aligned Tx buffer 1621 * to make custom checksum offload work. 1622 */ 1623 if ((sc->ale_flags & ALE_FLAG_TXCSUM_BUG) != 0 && 1624 (m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0 && 1625 (mtod(m, intptr_t) & 3) != 0) { 1626 m = m_defrag(*m_head, M_DONTWAIT); 1627 if (m == NULL) { 1628 *m_head = NULL; 1629 return (ENOBUFS); 1630 } 1631 *m_head = m; 1632 } 1633 1634 ip_off = sizeof(struct ether_header); 1635 m = m_pullup(m, ip_off); 1636 if (m == NULL) { 1637 *m_head = NULL; 1638 return (ENOBUFS); 1639 } 1640 eh = mtod(m, struct ether_header *); 1641 /* 1642 * Check if hardware VLAN insertion is off. 1643 * Additional check for LLC/SNAP frame? 1644 */ 1645 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1646 ip_off = sizeof(struct ether_vlan_header); 1647 m = m_pullup(m, ip_off); 1648 if (m == NULL) { 1649 *m_head = NULL; 1650 return (ENOBUFS); 1651 } 1652 } 1653 m = m_pullup(m, ip_off + sizeof(struct ip)); 1654 if (m == NULL) { 1655 *m_head = NULL; 1656 return (ENOBUFS); 1657 } 1658 ip = (struct ip *)(mtod(m, char *) + ip_off); 1659 poff = ip_off + (ip->ip_hl << 2); 1660 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1661 /* 1662 * XXX 1663 * AR81xx requires the first descriptor should 1664 * not include any TCP playload for TSO case. 1665 * (i.e. ethernet header + IP + TCP header only) 1666 * m_pullup(9) above will ensure this too. 1667 * However it's not correct if the first mbuf 1668 * of the chain does not use cluster. 1669 */ 1670 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1671 if (m == NULL) { 1672 *m_head = NULL; 1673 return (ENOBUFS); 1674 } 1675 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1676 /* 1677 * AR81xx requires IP/TCP header size and offset as 1678 * well as TCP pseudo checksum which complicates 1679 * TSO configuration. I guess this comes from the 1680 * adherence to Microsoft NDIS Large Send 1681 * specification which requires insertion of 1682 * pseudo checksum by upper stack. The pseudo 1683 * checksum that NDIS refers to doesn't include 1684 * TCP payload length so ale(4) should recompute 1685 * the pseudo checksum here. Hopefully this wouldn't 1686 * be much burden on modern CPUs. 1687 * Reset IP checksum and recompute TCP pseudo 1688 * checksum as NDIS specification said. 1689 */ 1690 ip->ip_sum = 0; 1691 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1692 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1693 } 1694 *m_head = m; 1695 } 1696 1697 si = prod = sc->ale_cdata.ale_tx_prod; 1698 txd = &sc->ale_cdata.ale_txdesc[prod]; 1699 txd_last = txd; 1700 map = txd->tx_dmamap; 1701 1702 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1703 *m_head, txsegs, &nsegs, 0); 1704 if (error == EFBIG) { 1705 m = m_collapse(*m_head, M_DONTWAIT, ALE_MAXTXSEGS); 1706 if (m == NULL) { 1707 m_freem(*m_head); 1708 *m_head = NULL; 1709 return (ENOMEM); 1710 } 1711 *m_head = m; 1712 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1713 *m_head, txsegs, &nsegs, 0); 1714 if (error != 0) { 1715 m_freem(*m_head); 1716 *m_head = NULL; 1717 return (error); 1718 } 1719 } else if (error != 0) 1720 return (error); 1721 if (nsegs == 0) { 1722 m_freem(*m_head); 1723 *m_head = NULL; 1724 return (EIO); 1725 } 1726 1727 /* Check descriptor overrun. */ 1728 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 2) { 1729 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, map); 1730 return (ENOBUFS); 1731 } 1732 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, map, BUS_DMASYNC_PREWRITE); 1733 1734 m = *m_head; 1735 /* Configure Tx checksum offload. */ 1736 if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { 1737 /* 1738 * AR81xx supports Tx custom checksum offload feature 1739 * that offloads single 16bit checksum computation. 1740 * So you can choose one among IP, TCP and UDP. 1741 * Normally driver sets checksum start/insertion 1742 * position from the information of TCP/UDP frame as 1743 * TCP/UDP checksum takes more time than that of IP. 1744 * However it seems that custom checksum offload 1745 * requires 4 bytes aligned Tx buffers due to hardware 1746 * bug. 1747 * AR81xx also supports explicit Tx checksum computation 1748 * if it is told that the size of IP header and TCP 1749 * header(for UDP, the header size does not matter 1750 * because it's fixed length). However with this scheme 1751 * TSO does not work so you have to choose one either 1752 * TSO or explicit Tx checksum offload. I chosen TSO 1753 * plus custom checksum offload with work-around which 1754 * will cover most common usage for this consumer 1755 * ethernet controller. The work-around takes a lot of 1756 * CPU cycles if Tx buffer is not aligned on 4 bytes 1757 * boundary, though. 1758 */ 1759 cflags |= ALE_TD_CXSUM; 1760 /* Set checksum start offset. */ 1761 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); 1762 /* Set checksum insertion position of TCP/UDP. */ 1763 cflags |= ((poff + m->m_pkthdr.csum_data) << 1764 ALE_TD_CSUM_XSUMOFFSET_SHIFT); 1765 } 1766 1767 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1768 /* Request TSO and set MSS. */ 1769 cflags |= ALE_TD_TSO; 1770 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << ALE_TD_MSS_SHIFT); 1771 /* Set IP/TCP header size. */ 1772 cflags |= ip->ip_hl << ALE_TD_IPHDR_LEN_SHIFT; 1773 cflags |= tcp->th_off << ALE_TD_TCPHDR_LEN_SHIFT; 1774 } 1775 1776 /* Configure VLAN hardware tag insertion. */ 1777 if ((m->m_flags & M_VLANTAG) != 0) { 1778 vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1779 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); 1780 cflags |= ALE_TD_INSERT_VLAN_TAG; 1781 } 1782 1783 desc = NULL; 1784 for (i = 0; i < nsegs; i++) { 1785 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1786 desc->addr = htole64(txsegs[i].ds_addr); 1787 desc->len = htole32(ALE_TX_BYTES(txsegs[i].ds_len) | vtag); 1788 desc->flags = htole32(cflags); 1789 sc->ale_cdata.ale_tx_cnt++; 1790 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1791 } 1792 /* Update producer index. */ 1793 sc->ale_cdata.ale_tx_prod = prod; 1794 /* Set TSO header on the first descriptor. */ 1795 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1796 desc = &sc->ale_cdata.ale_tx_ring[si]; 1797 desc->flags |= htole32(ALE_TD_TSO_HDR); 1798 } 1799 1800 /* Finally set EOP on the last descriptor. */ 1801 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; 1802 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1803 desc->flags |= htole32(ALE_TD_EOP); 1804 1805 /* Swap dmamap of the first and the last. */ 1806 txd = &sc->ale_cdata.ale_txdesc[prod]; 1807 map = txd_last->tx_dmamap; 1808 txd_last->tx_dmamap = txd->tx_dmamap; 1809 txd->tx_dmamap = map; 1810 txd->tx_m = m; 1811 1812 /* Sync descriptors. */ 1813 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 1814 sc->ale_cdata.ale_tx_ring_map, 1815 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1816 1817 return (0); 1818 } 1819 1820 static void 1821 ale_tx_task(void *arg, int pending) 1822 { 1823 struct ifnet *ifp; 1824 1825 ifp = (struct ifnet *)arg; 1826 ale_start(ifp); 1827 } 1828 1829 static void 1830 ale_start(struct ifnet *ifp) 1831 { 1832 struct ale_softc *sc; 1833 struct mbuf *m_head; 1834 int enq; 1835 1836 sc = ifp->if_softc; 1837 1838 ALE_LOCK(sc); 1839 1840 /* Reclaim transmitted frames. */ 1841 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) 1842 ale_txeof(sc); 1843 1844 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1845 IFF_DRV_RUNNING || (sc->ale_flags & ALE_FLAG_LINK) == 0) { 1846 ALE_UNLOCK(sc); 1847 return; 1848 } 1849 1850 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1851 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1852 if (m_head == NULL) 1853 break; 1854 /* 1855 * Pack the data into the transmit ring. If we 1856 * don't have room, set the OACTIVE flag and wait 1857 * for the NIC to drain the ring. 1858 */ 1859 if (ale_encap(sc, &m_head)) { 1860 if (m_head == NULL) 1861 break; 1862 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1863 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1864 break; 1865 } 1866 1867 enq++; 1868 /* 1869 * If there's a BPF listener, bounce a copy of this frame 1870 * to him. 1871 */ 1872 ETHER_BPF_MTAP(ifp, m_head); 1873 } 1874 1875 if (enq > 0) { 1876 /* Kick. */ 1877 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, 1878 sc->ale_cdata.ale_tx_prod); 1879 /* Set a timeout in case the chip goes out to lunch. */ 1880 sc->ale_watchdog_timer = ALE_TX_TIMEOUT; 1881 } 1882 1883 ALE_UNLOCK(sc); 1884 } 1885 1886 static void 1887 ale_watchdog(struct ale_softc *sc) 1888 { 1889 struct ifnet *ifp; 1890 1891 ALE_LOCK_ASSERT(sc); 1892 1893 if (sc->ale_watchdog_timer == 0 || --sc->ale_watchdog_timer) 1894 return; 1895 1896 ifp = sc->ale_ifp; 1897 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1898 if_printf(sc->ale_ifp, "watchdog timeout (lost link)\n"); 1899 ifp->if_oerrors++; 1900 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1901 ale_init_locked(sc); 1902 return; 1903 } 1904 if_printf(sc->ale_ifp, "watchdog timeout -- resetting\n"); 1905 ifp->if_oerrors++; 1906 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1907 ale_init_locked(sc); 1908 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1909 taskqueue_enqueue(sc->ale_tq, &sc->ale_tx_task); 1910 } 1911 1912 static int 1913 ale_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1914 { 1915 struct ale_softc *sc; 1916 struct ifreq *ifr; 1917 struct mii_data *mii; 1918 int error, mask; 1919 1920 sc = ifp->if_softc; 1921 ifr = (struct ifreq *)data; 1922 error = 0; 1923 switch (cmd) { 1924 case SIOCSIFMTU: 1925 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALE_JUMBO_MTU || 1926 ((sc->ale_flags & ALE_FLAG_JUMBO) == 0 && 1927 ifr->ifr_mtu > ETHERMTU)) 1928 error = EINVAL; 1929 else if (ifp->if_mtu != ifr->ifr_mtu) { 1930 ALE_LOCK(sc); 1931 ifp->if_mtu = ifr->ifr_mtu; 1932 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1933 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1934 ale_init_locked(sc); 1935 } 1936 ALE_UNLOCK(sc); 1937 } 1938 break; 1939 case SIOCSIFFLAGS: 1940 ALE_LOCK(sc); 1941 if ((ifp->if_flags & IFF_UP) != 0) { 1942 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1943 if (((ifp->if_flags ^ sc->ale_if_flags) 1944 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1945 ale_rxfilter(sc); 1946 } else { 1947 if ((sc->ale_flags & ALE_FLAG_DETACH) == 0) 1948 ale_init_locked(sc); 1949 } 1950 } else { 1951 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1952 ale_stop(sc); 1953 } 1954 sc->ale_if_flags = ifp->if_flags; 1955 ALE_UNLOCK(sc); 1956 break; 1957 case SIOCADDMULTI: 1958 case SIOCDELMULTI: 1959 ALE_LOCK(sc); 1960 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1961 ale_rxfilter(sc); 1962 ALE_UNLOCK(sc); 1963 break; 1964 case SIOCSIFMEDIA: 1965 case SIOCGIFMEDIA: 1966 mii = device_get_softc(sc->ale_miibus); 1967 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1968 break; 1969 case SIOCSIFCAP: 1970 ALE_LOCK(sc); 1971 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1972 if ((mask & IFCAP_TXCSUM) != 0 && 1973 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 1974 ifp->if_capenable ^= IFCAP_TXCSUM; 1975 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1976 ifp->if_hwassist |= ALE_CSUM_FEATURES; 1977 else 1978 ifp->if_hwassist &= ~ALE_CSUM_FEATURES; 1979 } 1980 if ((mask & IFCAP_RXCSUM) != 0 && 1981 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 1982 ifp->if_capenable ^= IFCAP_RXCSUM; 1983 if ((mask & IFCAP_TSO4) != 0 && 1984 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 1985 ifp->if_capenable ^= IFCAP_TSO4; 1986 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 1987 ifp->if_hwassist |= CSUM_TSO; 1988 else 1989 ifp->if_hwassist &= ~CSUM_TSO; 1990 } 1991 1992 if ((mask & IFCAP_WOL_MCAST) != 0 && 1993 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 1994 ifp->if_capenable ^= IFCAP_WOL_MCAST; 1995 if ((mask & IFCAP_WOL_MAGIC) != 0 && 1996 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 1997 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 1998 1999 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2000 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2001 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2002 ale_rxvlan(sc); 2003 } 2004 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2005 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 2006 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2007 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2008 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 2009 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2010 /* 2011 * VLAN hardware tagging is required to do checksum 2012 * offload or TSO on VLAN interface. Checksum offload 2013 * on VLAN interface also requires hardware checksum 2014 * offload of parent interface. 2015 */ 2016 if ((ifp->if_capenable & IFCAP_TXCSUM) == 0) 2017 ifp->if_capenable &= ~IFCAP_VLAN_HWCSUM; 2018 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 2019 ifp->if_capenable &= 2020 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 2021 ALE_UNLOCK(sc); 2022 VLAN_CAPABILITIES(ifp); 2023 break; 2024 default: 2025 error = ether_ioctl(ifp, cmd, data); 2026 break; 2027 } 2028 2029 return (error); 2030 } 2031 2032 static void 2033 ale_mac_config(struct ale_softc *sc) 2034 { 2035 struct mii_data *mii; 2036 uint32_t reg; 2037 2038 ALE_LOCK_ASSERT(sc); 2039 2040 mii = device_get_softc(sc->ale_miibus); 2041 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2042 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2043 MAC_CFG_SPEED_MASK); 2044 /* Reprogram MAC with resolved speed/duplex. */ 2045 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2046 case IFM_10_T: 2047 case IFM_100_TX: 2048 reg |= MAC_CFG_SPEED_10_100; 2049 break; 2050 case IFM_1000_T: 2051 reg |= MAC_CFG_SPEED_1000; 2052 break; 2053 } 2054 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2055 reg |= MAC_CFG_FULL_DUPLEX; 2056 #ifdef notyet 2057 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2058 reg |= MAC_CFG_TX_FC; 2059 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2060 reg |= MAC_CFG_RX_FC; 2061 #endif 2062 } 2063 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2064 } 2065 2066 static void 2067 ale_link_task(void *arg, int pending) 2068 { 2069 struct ale_softc *sc; 2070 struct mii_data *mii; 2071 struct ifnet *ifp; 2072 uint32_t reg; 2073 2074 sc = (struct ale_softc *)arg; 2075 2076 ALE_LOCK(sc); 2077 mii = device_get_softc(sc->ale_miibus); 2078 ifp = sc->ale_ifp; 2079 if (mii == NULL || ifp == NULL || 2080 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2081 ALE_UNLOCK(sc); 2082 return; 2083 } 2084 2085 sc->ale_flags &= ~ALE_FLAG_LINK; 2086 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 2087 (IFM_ACTIVE | IFM_AVALID)) { 2088 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2089 case IFM_10_T: 2090 case IFM_100_TX: 2091 sc->ale_flags |= ALE_FLAG_LINK; 2092 break; 2093 case IFM_1000_T: 2094 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 2095 sc->ale_flags |= ALE_FLAG_LINK; 2096 break; 2097 default: 2098 break; 2099 } 2100 } 2101 2102 /* Stop Rx/Tx MACs. */ 2103 ale_stop_mac(sc); 2104 2105 /* Program MACs with resolved speed/duplex/flow-control. */ 2106 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { 2107 ale_mac_config(sc); 2108 /* Reenable Tx/Rx MACs. */ 2109 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2110 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 2111 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2112 } 2113 2114 ALE_UNLOCK(sc); 2115 } 2116 2117 static void 2118 ale_stats_clear(struct ale_softc *sc) 2119 { 2120 struct smb sb; 2121 uint32_t *reg; 2122 int i; 2123 2124 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2125 CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2126 i += sizeof(uint32_t); 2127 } 2128 /* Read Tx statistics. */ 2129 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2130 CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2131 i += sizeof(uint32_t); 2132 } 2133 } 2134 2135 static void 2136 ale_stats_update(struct ale_softc *sc) 2137 { 2138 struct ale_hw_stats *stat; 2139 struct smb sb, *smb; 2140 struct ifnet *ifp; 2141 uint32_t *reg; 2142 int i; 2143 2144 ALE_LOCK_ASSERT(sc); 2145 2146 ifp = sc->ale_ifp; 2147 stat = &sc->ale_stats; 2148 smb = &sb; 2149 2150 /* Read Rx statistics. */ 2151 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2152 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2153 i += sizeof(uint32_t); 2154 } 2155 /* Read Tx statistics. */ 2156 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2157 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2158 i += sizeof(uint32_t); 2159 } 2160 2161 /* Rx stats. */ 2162 stat->rx_frames += smb->rx_frames; 2163 stat->rx_bcast_frames += smb->rx_bcast_frames; 2164 stat->rx_mcast_frames += smb->rx_mcast_frames; 2165 stat->rx_pause_frames += smb->rx_pause_frames; 2166 stat->rx_control_frames += smb->rx_control_frames; 2167 stat->rx_crcerrs += smb->rx_crcerrs; 2168 stat->rx_lenerrs += smb->rx_lenerrs; 2169 stat->rx_bytes += smb->rx_bytes; 2170 stat->rx_runts += smb->rx_runts; 2171 stat->rx_fragments += smb->rx_fragments; 2172 stat->rx_pkts_64 += smb->rx_pkts_64; 2173 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2174 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2175 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2176 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2177 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2178 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2179 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2180 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2181 stat->rx_rrs_errs += smb->rx_rrs_errs; 2182 stat->rx_alignerrs += smb->rx_alignerrs; 2183 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2184 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2185 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2186 2187 /* Tx stats. */ 2188 stat->tx_frames += smb->tx_frames; 2189 stat->tx_bcast_frames += smb->tx_bcast_frames; 2190 stat->tx_mcast_frames += smb->tx_mcast_frames; 2191 stat->tx_pause_frames += smb->tx_pause_frames; 2192 stat->tx_excess_defer += smb->tx_excess_defer; 2193 stat->tx_control_frames += smb->tx_control_frames; 2194 stat->tx_deferred += smb->tx_deferred; 2195 stat->tx_bytes += smb->tx_bytes; 2196 stat->tx_pkts_64 += smb->tx_pkts_64; 2197 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2198 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2199 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2200 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2201 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2202 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2203 stat->tx_single_colls += smb->tx_single_colls; 2204 stat->tx_multi_colls += smb->tx_multi_colls; 2205 stat->tx_late_colls += smb->tx_late_colls; 2206 stat->tx_excess_colls += smb->tx_excess_colls; 2207 stat->tx_abort += smb->tx_abort; 2208 stat->tx_underrun += smb->tx_underrun; 2209 stat->tx_desc_underrun += smb->tx_desc_underrun; 2210 stat->tx_lenerrs += smb->tx_lenerrs; 2211 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2212 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2213 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2214 2215 /* Update counters in ifnet. */ 2216 ifp->if_opackets += smb->tx_frames; 2217 2218 ifp->if_collisions += smb->tx_single_colls + 2219 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2220 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 2221 2222 /* 2223 * XXX 2224 * tx_pkts_truncated counter looks suspicious. It constantly 2225 * increments with no sign of Tx errors. This may indicate 2226 * the counter name is not correct one so I've removed the 2227 * counter in output errors. 2228 */ 2229 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 2230 smb->tx_underrun; 2231 2232 ifp->if_ipackets += smb->rx_frames; 2233 2234 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2235 smb->rx_runts + smb->rx_pkts_truncated + 2236 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2237 smb->rx_alignerrs; 2238 } 2239 2240 static int 2241 ale_intr(void *arg) 2242 { 2243 struct ale_softc *sc; 2244 uint32_t status; 2245 2246 sc = (struct ale_softc *)arg; 2247 2248 status = CSR_READ_4(sc, ALE_INTR_STATUS); 2249 if ((status & ALE_INTRS) == 0) 2250 return (FILTER_STRAY); 2251 /* Disable interrupts. */ 2252 CSR_WRITE_4(sc, ALE_INTR_STATUS, INTR_DIS_INT); 2253 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2254 2255 return (FILTER_HANDLED); 2256 } 2257 2258 static void 2259 ale_int_task(void *arg, int pending) 2260 { 2261 struct ale_softc *sc; 2262 struct ifnet *ifp; 2263 uint32_t status; 2264 int more; 2265 2266 sc = (struct ale_softc *)arg; 2267 2268 status = CSR_READ_4(sc, ALE_INTR_STATUS); 2269 more = atomic_readandclear_int(&sc->ale_morework); 2270 if (more != 0) 2271 status |= INTR_RX_PKT; 2272 if ((status & ALE_INTRS) == 0) 2273 goto done; 2274 2275 /* Acknowledge interrupts but still disable interrupts. */ 2276 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); 2277 2278 ifp = sc->ale_ifp; 2279 more = 0; 2280 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2281 more = ale_rxeof(sc, sc->ale_process_limit); 2282 if (more == EAGAIN) 2283 atomic_set_int(&sc->ale_morework, 1); 2284 else if (more == EIO) { 2285 ALE_LOCK(sc); 2286 sc->ale_stats.reset_brk_seq++; 2287 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2288 ale_init_locked(sc); 2289 ALE_UNLOCK(sc); 2290 return; 2291 } 2292 2293 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 2294 if ((status & INTR_DMA_RD_TO_RST) != 0) 2295 device_printf(sc->ale_dev, 2296 "DMA read error! -- resetting\n"); 2297 if ((status & INTR_DMA_WR_TO_RST) != 0) 2298 device_printf(sc->ale_dev, 2299 "DMA write error! -- resetting\n"); 2300 ALE_LOCK(sc); 2301 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2302 ale_init_locked(sc); 2303 ALE_UNLOCK(sc); 2304 return; 2305 } 2306 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2307 taskqueue_enqueue(sc->ale_tq, &sc->ale_tx_task); 2308 } 2309 2310 if (more == EAGAIN || 2311 (CSR_READ_4(sc, ALE_INTR_STATUS) & ALE_INTRS) != 0) { 2312 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2313 return; 2314 } 2315 2316 done: 2317 /* Re-enable interrupts. */ 2318 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); 2319 } 2320 2321 static void 2322 ale_txeof(struct ale_softc *sc) 2323 { 2324 struct ifnet *ifp; 2325 struct ale_txdesc *txd; 2326 uint32_t cons, prod; 2327 int prog; 2328 2329 ALE_LOCK_ASSERT(sc); 2330 2331 ifp = sc->ale_ifp; 2332 2333 if (sc->ale_cdata.ale_tx_cnt == 0) 2334 return; 2335 2336 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2337 sc->ale_cdata.ale_tx_ring_map, 2338 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2339 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { 2340 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2341 sc->ale_cdata.ale_tx_cmb_map, 2342 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2343 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; 2344 } else 2345 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); 2346 cons = sc->ale_cdata.ale_tx_cons; 2347 /* 2348 * Go through our Tx list and free mbufs for those 2349 * frames which have been transmitted. 2350 */ 2351 for (prog = 0; cons != prod; prog++, 2352 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { 2353 if (sc->ale_cdata.ale_tx_cnt <= 0) 2354 break; 2355 prog++; 2356 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2357 sc->ale_cdata.ale_tx_cnt--; 2358 txd = &sc->ale_cdata.ale_txdesc[cons]; 2359 if (txd->tx_m != NULL) { 2360 /* Reclaim transmitted mbufs. */ 2361 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2362 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2363 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2364 txd->tx_dmamap); 2365 m_freem(txd->tx_m); 2366 txd->tx_m = NULL; 2367 } 2368 } 2369 2370 if (prog > 0) { 2371 sc->ale_cdata.ale_tx_cons = cons; 2372 /* 2373 * Unarm watchdog timer only when there is no pending 2374 * Tx descriptors in queue. 2375 */ 2376 if (sc->ale_cdata.ale_tx_cnt == 0) 2377 sc->ale_watchdog_timer = 0; 2378 } 2379 } 2380 2381 static void 2382 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, 2383 uint32_t length, uint32_t *prod) 2384 { 2385 struct ale_rx_page *rx_page; 2386 2387 rx_page = *page; 2388 /* Update consumer position. */ 2389 rx_page->cons += roundup(length + sizeof(struct rx_rs), 2390 ALE_RX_PAGE_ALIGN); 2391 if (rx_page->cons >= ALE_RX_PAGE_SZ) { 2392 /* 2393 * End of Rx page reached, let hardware reuse 2394 * this page. 2395 */ 2396 rx_page->cons = 0; 2397 *rx_page->cmb_addr = 0; 2398 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2399 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2400 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, 2401 RXF_VALID); 2402 /* Switch to alternate Rx page. */ 2403 sc->ale_cdata.ale_rx_curp ^= 1; 2404 rx_page = *page = 2405 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2406 /* Page flipped, sync CMB and Rx page. */ 2407 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2408 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2409 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2410 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2411 /* Sync completed, cache updated producer index. */ 2412 *prod = *rx_page->cmb_addr; 2413 } 2414 } 2415 2416 2417 /* 2418 * It seems that AR81xx controller can compute partial checksum. 2419 * The partial checksum value can be used to accelerate checksum 2420 * computation for fragmented TCP/UDP packets. Upper network stack 2421 * already takes advantage of the partial checksum value in IP 2422 * reassembly stage. But I'm not sure the correctness of the 2423 * partial hardware checksum assistance due to lack of data sheet. 2424 * In addition, the Rx feature of controller that requires copying 2425 * for every frames effectively nullifies one of most nice offload 2426 * capability of controller. 2427 */ 2428 static void 2429 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) 2430 { 2431 struct ifnet *ifp; 2432 struct ip *ip; 2433 char *p; 2434 2435 ifp = sc->ale_ifp; 2436 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2437 if ((status & ALE_RD_IPCSUM_NOK) == 0) 2438 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2439 2440 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { 2441 if (((status & ALE_RD_IPV4_FRAG) == 0) && 2442 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && 2443 ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) { 2444 m->m_pkthdr.csum_flags |= 2445 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2446 m->m_pkthdr.csum_data = 0xffff; 2447 } 2448 } else { 2449 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 && 2450 (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) { 2451 p = mtod(m, char *); 2452 p += ETHER_HDR_LEN; 2453 if ((status & ALE_RD_802_3) != 0) 2454 p += LLC_SNAPFRAMELEN; 2455 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0 && 2456 (status & ALE_RD_VLAN) != 0) 2457 p += ETHER_VLAN_ENCAP_LEN; 2458 ip = (struct ip *)p; 2459 if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0) 2460 return; 2461 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 2462 CSUM_PSEUDO_HDR; 2463 m->m_pkthdr.csum_data = 0xffff; 2464 } 2465 } 2466 /* 2467 * Don't mark bad checksum for TCP/UDP frames 2468 * as fragmented frames may always have set 2469 * bad checksummed bit of frame status. 2470 */ 2471 } 2472 2473 /* Process received frames. */ 2474 static int 2475 ale_rxeof(struct ale_softc *sc, int count) 2476 { 2477 struct ale_rx_page *rx_page; 2478 struct rx_rs *rs; 2479 struct ifnet *ifp; 2480 struct mbuf *m; 2481 uint32_t length, prod, seqno, status, vtags; 2482 int prog; 2483 2484 ifp = sc->ale_ifp; 2485 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2486 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2487 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2488 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2489 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2490 /* 2491 * Don't directly access producer index as hardware may 2492 * update it while Rx handler is in progress. It would 2493 * be even better if there is a way to let hardware 2494 * know how far driver processed its received frames. 2495 * Alternatively, hardware could provide a way to disable 2496 * CMB updates until driver acknowledges the end of CMB 2497 * access. 2498 */ 2499 prod = *rx_page->cmb_addr; 2500 for (prog = 0; prog < count; prog++) { 2501 if (rx_page->cons >= prod) 2502 break; 2503 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); 2504 seqno = ALE_RX_SEQNO(le32toh(rs->seqno)); 2505 if (sc->ale_cdata.ale_rx_seqno != seqno) { 2506 /* 2507 * Normally I believe this should not happen unless 2508 * severe driver bug or corrupted memory. However 2509 * it seems to happen under certain conditions which 2510 * is triggered by abrupt Rx events such as initiation 2511 * of bulk transfer of remote host. It's not easy to 2512 * reproduce this and I doubt it could be related 2513 * with FIFO overflow of hardware or activity of Tx 2514 * CMB updates. I also remember similar behaviour 2515 * seen on RealTek 8139 which uses resembling Rx 2516 * scheme. 2517 */ 2518 if (bootverbose) 2519 device_printf(sc->ale_dev, 2520 "garbled seq: %u, expected: %u -- " 2521 "resetting!\n", seqno, 2522 sc->ale_cdata.ale_rx_seqno); 2523 return (EIO); 2524 } 2525 /* Frame received. */ 2526 sc->ale_cdata.ale_rx_seqno++; 2527 length = ALE_RX_BYTES(le32toh(rs->length)); 2528 status = le32toh(rs->flags); 2529 if ((status & ALE_RD_ERROR) != 0) { 2530 /* 2531 * We want to pass the following frames to upper 2532 * layer regardless of error status of Rx return 2533 * status. 2534 * 2535 * o IP/TCP/UDP checksum is bad. 2536 * o frame length and protocol specific length 2537 * does not match. 2538 */ 2539 if ((status & (ALE_RD_CRC | ALE_RD_CODE | 2540 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | 2541 ALE_RD_TRUNC)) != 0) { 2542 ale_rx_update_page(sc, &rx_page, length, &prod); 2543 continue; 2544 } 2545 } 2546 /* 2547 * m_devget(9) is major bottle-neck of ale(4)(It comes 2548 * from hardware limitation). For jumbo frames we could 2549 * get a slightly better performance if driver use 2550 * m_getjcl(9) with proper buffer size argument. However 2551 * that would make code more complicated and I don't 2552 * think users would expect good Rx performance numbers 2553 * on these low-end consumer ethernet controller. 2554 */ 2555 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, 2556 ETHER_ALIGN, ifp, NULL); 2557 if (m == NULL) { 2558 ifp->if_iqdrops++; 2559 ale_rx_update_page(sc, &rx_page, length, &prod); 2560 continue; 2561 } 2562 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 2563 (status & ALE_RD_IPV4) != 0) 2564 ale_rxcsum(sc, m, status); 2565 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 2566 (status & ALE_RD_VLAN) != 0) { 2567 vtags = ALE_RX_VLAN(le32toh(rs->vtags)); 2568 m->m_pkthdr.ether_vtag = ALE_RX_VLAN_TAG(vtags); 2569 m->m_flags |= M_VLANTAG; 2570 } 2571 2572 /* Pass it to upper layer. */ 2573 (*ifp->if_input)(ifp, m); 2574 2575 ale_rx_update_page(sc, &rx_page, length, &prod); 2576 } 2577 2578 return (count > 0 ? 0 : EAGAIN); 2579 } 2580 2581 static void 2582 ale_tick(void *arg) 2583 { 2584 struct ale_softc *sc; 2585 struct mii_data *mii; 2586 2587 sc = (struct ale_softc *)arg; 2588 2589 ALE_LOCK_ASSERT(sc); 2590 2591 mii = device_get_softc(sc->ale_miibus); 2592 mii_tick(mii); 2593 ale_stats_update(sc); 2594 /* 2595 * Reclaim Tx buffers that have been transferred. It's not 2596 * needed here but it would release allocated mbuf chains 2597 * faster and limit the maximum delay to a hz. 2598 */ 2599 ale_txeof(sc); 2600 ale_watchdog(sc); 2601 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2602 } 2603 2604 static void 2605 ale_reset(struct ale_softc *sc) 2606 { 2607 uint32_t reg; 2608 int i; 2609 2610 /* Initialize PCIe module. From Linux. */ 2611 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2612 2613 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); 2614 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2615 DELAY(10); 2616 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) 2617 break; 2618 } 2619 if (i == 0) 2620 device_printf(sc->ale_dev, "master reset timeout!\n"); 2621 2622 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2623 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) 2624 break; 2625 DELAY(10); 2626 } 2627 2628 if (i == 0) 2629 device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg); 2630 } 2631 2632 static void 2633 ale_init(void *xsc) 2634 { 2635 struct ale_softc *sc; 2636 2637 sc = (struct ale_softc *)xsc; 2638 ALE_LOCK(sc); 2639 ale_init_locked(sc); 2640 ALE_UNLOCK(sc); 2641 } 2642 2643 static void 2644 ale_init_locked(struct ale_softc *sc) 2645 { 2646 struct ifnet *ifp; 2647 struct mii_data *mii; 2648 uint8_t eaddr[ETHER_ADDR_LEN]; 2649 bus_addr_t paddr; 2650 uint32_t reg, rxf_hi, rxf_lo; 2651 2652 ALE_LOCK_ASSERT(sc); 2653 2654 ifp = sc->ale_ifp; 2655 mii = device_get_softc(sc->ale_miibus); 2656 2657 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2658 return; 2659 /* 2660 * Cancel any pending I/O. 2661 */ 2662 ale_stop(sc); 2663 /* 2664 * Reset the chip to a known state. 2665 */ 2666 ale_reset(sc); 2667 /* Initialize Tx descriptors, DMA memory blocks. */ 2668 ale_init_rx_pages(sc); 2669 ale_init_tx_ring(sc); 2670 2671 /* Reprogram the station address. */ 2672 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2673 CSR_WRITE_4(sc, ALE_PAR0, 2674 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2675 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); 2676 /* 2677 * Clear WOL status and disable all WOL feature as WOL 2678 * would interfere Rx operation under normal environments. 2679 */ 2680 CSR_READ_4(sc, ALE_WOL_CFG); 2681 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 2682 /* 2683 * Set Tx descriptor/RXF0/CMB base addresses. They share 2684 * the same high address part of DMAable region. 2685 */ 2686 paddr = sc->ale_cdata.ale_tx_ring_paddr; 2687 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); 2688 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); 2689 CSR_WRITE_4(sc, ALE_TPD_CNT, 2690 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); 2691 /* Set Rx page base address, note we use single queue. */ 2692 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; 2693 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); 2694 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; 2695 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); 2696 /* Set Tx/Rx CMB addresses. */ 2697 paddr = sc->ale_cdata.ale_tx_cmb_paddr; 2698 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); 2699 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; 2700 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); 2701 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; 2702 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); 2703 /* Mark RXF0 is valid. */ 2704 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); 2705 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); 2706 /* 2707 * No need to initialize RFX1/RXF2/RXF3. We don't use 2708 * multi-queue yet. 2709 */ 2710 2711 /* Set Rx page size, excluding guard frame size. */ 2712 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); 2713 /* Tell hardware that we're ready to load DMA blocks. */ 2714 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); 2715 2716 /* Set Rx/Tx interrupt trigger threshold. */ 2717 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | 2718 (4 << INT_TRIG_TX_THRESH_SHIFT)); 2719 /* 2720 * XXX 2721 * Set interrupt trigger timer, its purpose and relation 2722 * with interrupt moderation mechanism is not clear yet. 2723 */ 2724 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, 2725 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | 2726 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); 2727 2728 /* Configure interrupt moderation timer. */ 2729 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; 2730 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; 2731 CSR_WRITE_4(sc, ALE_IM_TIMER, reg); 2732 reg = CSR_READ_4(sc, ALE_MASTER_CFG); 2733 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 2734 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 2735 if (ALE_USECS(sc->ale_int_rx_mod) != 0) 2736 reg |= MASTER_IM_RX_TIMER_ENB; 2737 if (ALE_USECS(sc->ale_int_tx_mod) != 0) 2738 reg |= MASTER_IM_TX_TIMER_ENB; 2739 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); 2740 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); 2741 2742 /* Set Maximum frame size of controller. */ 2743 if (ifp->if_mtu < ETHERMTU) 2744 sc->ale_max_frame_size = ETHERMTU; 2745 else 2746 sc->ale_max_frame_size = ifp->if_mtu; 2747 sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 2748 ETHER_CRC_LEN; 2749 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); 2750 /* Configure IPG/IFG parameters. */ 2751 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, 2752 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 2753 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2754 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2755 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 2756 /* Set parameters for half-duplex media. */ 2757 CSR_WRITE_4(sc, ALE_HDPX_CFG, 2758 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2759 HDPX_CFG_LCOL_MASK) | 2760 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2761 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2762 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2763 HDPX_CFG_ABEBT_MASK) | 2764 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2765 HDPX_CFG_JAMIPG_MASK)); 2766 2767 /* Configure Tx jumbo frame parameters. */ 2768 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2769 if (ifp->if_mtu < ETHERMTU) 2770 reg = sc->ale_max_frame_size; 2771 else if (ifp->if_mtu < 6 * 1024) 2772 reg = (sc->ale_max_frame_size * 2) / 3; 2773 else 2774 reg = sc->ale_max_frame_size / 2; 2775 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, 2776 roundup(reg, TX_JUMBO_THRESH_UNIT) >> 2777 TX_JUMBO_THRESH_UNIT_SHIFT); 2778 } 2779 /* Configure TxQ. */ 2780 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) 2781 << TXQ_CFG_TX_FIFO_BURST_SHIFT; 2782 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2783 TXQ_CFG_TPD_BURST_MASK; 2784 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); 2785 2786 /* Configure Rx jumbo frame & flow control parameters. */ 2787 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2788 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); 2789 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, 2790 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << 2791 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | 2792 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & 2793 RX_JUMBO_LKAH_MASK)); 2794 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 2795 rxf_hi = (reg * 7) / 10; 2796 rxf_lo = (reg * 3)/ 10; 2797 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, 2798 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2799 RX_FIFO_PAUSE_THRESH_LO_MASK) | 2800 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2801 RX_FIFO_PAUSE_THRESH_HI_MASK)); 2802 } 2803 2804 /* Disable RSS. */ 2805 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); 2806 CSR_WRITE_4(sc, ALE_RSS_CPU, 0); 2807 2808 /* Configure RxQ. */ 2809 CSR_WRITE_4(sc, ALE_RXQ_CFG, 2810 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2811 2812 /* Configure DMA parameters. */ 2813 reg = 0; 2814 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) 2815 reg |= DMA_CFG_TXCMB_ENB; 2816 CSR_WRITE_4(sc, ALE_DMA_CFG, 2817 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | 2818 sc->ale_dma_rd_burst | reg | 2819 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | 2820 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 2821 DMA_CFG_RD_DELAY_CNT_MASK) | 2822 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 2823 DMA_CFG_WR_DELAY_CNT_MASK)); 2824 2825 /* 2826 * Hardware can be configured to issue SMB interrupt based 2827 * on programmed interval. Since there is a callout that is 2828 * invoked for every hz in driver we use that instead of 2829 * relying on periodic SMB interrupt. 2830 */ 2831 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); 2832 /* Clear MAC statistics. */ 2833 ale_stats_clear(sc); 2834 2835 /* 2836 * Configure Tx/Rx MACs. 2837 * - Auto-padding for short frames. 2838 * - Enable CRC generation. 2839 * Actual reconfiguration of MAC for resolved speed/duplex 2840 * is followed after detection of link establishment. 2841 * AR81xx always does checksum computation regardless of 2842 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will 2843 * cause Rx handling issue for fragmented IP datagrams due 2844 * to silicon bug. 2845 */ 2846 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 2847 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2848 MAC_CFG_PREAMBLE_MASK); 2849 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) 2850 reg |= MAC_CFG_SPEED_10_100; 2851 else 2852 reg |= MAC_CFG_SPEED_1000; 2853 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2854 2855 /* Set up the receive filter. */ 2856 ale_rxfilter(sc); 2857 ale_rxvlan(sc); 2858 2859 /* Acknowledge all pending interrupts and clear it. */ 2860 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); 2861 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2862 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); 2863 2864 sc->ale_flags &= ~ALE_FLAG_LINK; 2865 /* Switch to the current media. */ 2866 mii_mediachg(mii); 2867 2868 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2869 2870 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2871 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2872 } 2873 2874 static void 2875 ale_stop(struct ale_softc *sc) 2876 { 2877 struct ifnet *ifp; 2878 struct ale_txdesc *txd; 2879 uint32_t reg; 2880 int i; 2881 2882 ALE_LOCK_ASSERT(sc); 2883 /* 2884 * Mark the interface down and cancel the watchdog timer. 2885 */ 2886 ifp = sc->ale_ifp; 2887 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2888 sc->ale_flags &= ~ALE_FLAG_LINK; 2889 callout_stop(&sc->ale_tick_ch); 2890 sc->ale_watchdog_timer = 0; 2891 ale_stats_update(sc); 2892 /* Disable interrupts. */ 2893 CSR_WRITE_4(sc, ALE_INTR_MASK, 0); 2894 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2895 /* Disable queue processing and DMA. */ 2896 reg = CSR_READ_4(sc, ALE_TXQ_CFG); 2897 reg &= ~TXQ_CFG_ENB; 2898 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); 2899 reg = CSR_READ_4(sc, ALE_RXQ_CFG); 2900 reg &= ~RXQ_CFG_ENB; 2901 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); 2902 reg = CSR_READ_4(sc, ALE_DMA_CFG); 2903 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); 2904 CSR_WRITE_4(sc, ALE_DMA_CFG, reg); 2905 DELAY(1000); 2906 /* Stop Rx/Tx MACs. */ 2907 ale_stop_mac(sc); 2908 /* Disable interrupts which might be touched in taskq handler. */ 2909 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2910 2911 /* 2912 * Free TX mbufs still in the queues. 2913 */ 2914 for (i = 0; i < ALE_TX_RING_CNT; i++) { 2915 txd = &sc->ale_cdata.ale_txdesc[i]; 2916 if (txd->tx_m != NULL) { 2917 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2918 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2919 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2920 txd->tx_dmamap); 2921 m_freem(txd->tx_m); 2922 txd->tx_m = NULL; 2923 } 2924 } 2925 } 2926 2927 static void 2928 ale_stop_mac(struct ale_softc *sc) 2929 { 2930 uint32_t reg; 2931 int i; 2932 2933 ALE_LOCK_ASSERT(sc); 2934 2935 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2936 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 2937 reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 2938 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2939 } 2940 2941 for (i = ALE_TIMEOUT; i > 0; i--) { 2942 reg = CSR_READ_4(sc, ALE_IDLE_STATUS); 2943 if (reg == 0) 2944 break; 2945 DELAY(10); 2946 } 2947 if (i == 0) 2948 device_printf(sc->ale_dev, 2949 "could not disable Tx/Rx MAC(0x%08x)!\n", reg); 2950 } 2951 2952 static void 2953 ale_init_tx_ring(struct ale_softc *sc) 2954 { 2955 struct ale_txdesc *txd; 2956 int i; 2957 2958 ALE_LOCK_ASSERT(sc); 2959 2960 sc->ale_cdata.ale_tx_prod = 0; 2961 sc->ale_cdata.ale_tx_cons = 0; 2962 sc->ale_cdata.ale_tx_cnt = 0; 2963 2964 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ); 2965 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ); 2966 for (i = 0; i < ALE_TX_RING_CNT; i++) { 2967 txd = &sc->ale_cdata.ale_txdesc[i]; 2968 txd->tx_m = NULL; 2969 } 2970 *sc->ale_cdata.ale_tx_cmb = 0; 2971 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2972 sc->ale_cdata.ale_tx_cmb_map, 2973 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2974 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2975 sc->ale_cdata.ale_tx_ring_map, 2976 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2977 } 2978 2979 static void 2980 ale_init_rx_pages(struct ale_softc *sc) 2981 { 2982 struct ale_rx_page *rx_page; 2983 int i; 2984 2985 ALE_LOCK_ASSERT(sc); 2986 2987 atomic_set_int(&sc->ale_morework, 0); 2988 sc->ale_cdata.ale_rx_seqno = 0; 2989 sc->ale_cdata.ale_rx_curp = 0; 2990 2991 for (i = 0; i < ALE_RX_PAGES; i++) { 2992 rx_page = &sc->ale_cdata.ale_rx_page[i]; 2993 bzero(rx_page->page_addr, sc->ale_pagesize); 2994 bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ); 2995 rx_page->cons = 0; 2996 *rx_page->cmb_addr = 0; 2997 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2998 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2999 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 3000 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3001 } 3002 } 3003 3004 static void 3005 ale_rxvlan(struct ale_softc *sc) 3006 { 3007 struct ifnet *ifp; 3008 uint32_t reg; 3009 3010 ALE_LOCK_ASSERT(sc); 3011 3012 ifp = sc->ale_ifp; 3013 reg = CSR_READ_4(sc, ALE_MAC_CFG); 3014 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3015 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3016 reg |= MAC_CFG_VLAN_TAG_STRIP; 3017 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 3018 } 3019 3020 static void 3021 ale_rxfilter(struct ale_softc *sc) 3022 { 3023 struct ifnet *ifp; 3024 struct ifmultiaddr *ifma; 3025 uint32_t crc; 3026 uint32_t mchash[2]; 3027 uint32_t rxcfg; 3028 3029 ALE_LOCK_ASSERT(sc); 3030 3031 ifp = sc->ale_ifp; 3032 3033 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); 3034 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3035 if ((ifp->if_flags & IFF_BROADCAST) != 0) 3036 rxcfg |= MAC_CFG_BCAST; 3037 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3038 if ((ifp->if_flags & IFF_PROMISC) != 0) 3039 rxcfg |= MAC_CFG_PROMISC; 3040 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3041 rxcfg |= MAC_CFG_ALLMULTI; 3042 CSR_WRITE_4(sc, ALE_MAR0, 0xFFFFFFFF); 3043 CSR_WRITE_4(sc, ALE_MAR1, 0xFFFFFFFF); 3044 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3045 return; 3046 } 3047 3048 /* Program new filter. */ 3049 bzero(mchash, sizeof(mchash)); 3050 3051 IF_ADDR_LOCK(ifp); 3052 TAILQ_FOREACH(ifma, &sc->ale_ifp->if_multiaddrs, ifma_link) { 3053 if (ifma->ifma_addr->sa_family != AF_LINK) 3054 continue; 3055 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 3056 ifma->ifma_addr), ETHER_ADDR_LEN); 3057 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3058 } 3059 IF_ADDR_UNLOCK(ifp); 3060 3061 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); 3062 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); 3063 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3064 } 3065 3066 static int 3067 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3068 { 3069 int error, value; 3070 3071 if (arg1 == NULL) 3072 return (EINVAL); 3073 value = *(int *)arg1; 3074 error = sysctl_handle_int(oidp, &value, 0, req); 3075 if (error || req->newptr == NULL) 3076 return (error); 3077 if (value < low || value > high) 3078 return (EINVAL); 3079 *(int *)arg1 = value; 3080 3081 return (0); 3082 } 3083 3084 static int 3085 sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS) 3086 { 3087 return (sysctl_int_range(oidp, arg1, arg2, req, 3088 ALE_PROC_MIN, ALE_PROC_MAX)); 3089 } 3090 3091 static int 3092 sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS) 3093 { 3094 3095 return (sysctl_int_range(oidp, arg1, arg2, req, 3096 ALE_IM_TIMER_MIN, ALE_IM_TIMER_MAX)); 3097 } 3098