1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/endian.h> 36 #include <sys/kernel.h> 37 #include <sys/malloc.h> 38 #include <sys/mbuf.h> 39 #include <sys/module.h> 40 #include <sys/rman.h> 41 #include <sys/queue.h> 42 #include <sys/socket.h> 43 #include <sys/sockio.h> 44 #include <sys/sysctl.h> 45 #include <sys/taskqueue.h> 46 47 #include <net/bpf.h> 48 #include <net/if.h> 49 #include <net/if_var.h> 50 #include <net/if_arp.h> 51 #include <net/ethernet.h> 52 #include <net/if_dl.h> 53 #include <net/if_llc.h> 54 #include <net/if_media.h> 55 #include <net/if_types.h> 56 #include <net/if_vlan_var.h> 57 58 #include <netinet/in.h> 59 #include <netinet/in_systm.h> 60 #include <netinet/ip.h> 61 #include <netinet/tcp.h> 62 63 #include <dev/mii/mii.h> 64 #include <dev/mii/miivar.h> 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 69 #include <machine/bus.h> 70 #include <machine/in_cksum.h> 71 72 #include <dev/ale/if_alereg.h> 73 #include <dev/ale/if_alevar.h> 74 75 /* "device miibus" required. See GENERIC if you get errors here. */ 76 #include "miibus_if.h" 77 78 /* For more information about Tx checksum offload issues see ale_encap(). */ 79 #define ALE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 80 81 MODULE_DEPEND(ale, pci, 1, 1, 1); 82 MODULE_DEPEND(ale, ether, 1, 1, 1); 83 MODULE_DEPEND(ale, miibus, 1, 1, 1); 84 85 /* Tunables. */ 86 static int msi_disable = 0; 87 static int msix_disable = 0; 88 TUNABLE_INT("hw.ale.msi_disable", &msi_disable); 89 TUNABLE_INT("hw.ale.msix_disable", &msix_disable); 90 91 /* 92 * Devices supported by this driver. 93 */ 94 static const struct ale_dev { 95 uint16_t ale_vendorid; 96 uint16_t ale_deviceid; 97 const char *ale_name; 98 } ale_devs[] = { 99 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR81XX, 100 "Atheros AR8121/AR8113/AR8114 PCIe Ethernet" }, 101 }; 102 103 static int ale_attach(device_t); 104 static int ale_check_boundary(struct ale_softc *); 105 static int ale_detach(device_t); 106 static int ale_dma_alloc(struct ale_softc *); 107 static void ale_dma_free(struct ale_softc *); 108 static void ale_dmamap_cb(void *, bus_dma_segment_t *, int, int); 109 static int ale_encap(struct ale_softc *, struct mbuf **); 110 static void ale_get_macaddr(struct ale_softc *); 111 static void ale_init(void *); 112 static void ale_init_locked(struct ale_softc *); 113 static void ale_init_rx_pages(struct ale_softc *); 114 static void ale_init_tx_ring(struct ale_softc *); 115 static void ale_int_task(void *, int); 116 static int ale_intr(void *); 117 static int ale_ioctl(if_t, u_long, caddr_t); 118 static void ale_mac_config(struct ale_softc *); 119 static int ale_miibus_readreg(device_t, int, int); 120 static void ale_miibus_statchg(device_t); 121 static int ale_miibus_writereg(device_t, int, int, int); 122 static int ale_mediachange(if_t); 123 static void ale_mediastatus(if_t, struct ifmediareq *); 124 static void ale_phy_reset(struct ale_softc *); 125 static int ale_probe(device_t); 126 static void ale_reset(struct ale_softc *); 127 static int ale_resume(device_t); 128 static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, 129 uint32_t, uint32_t *); 130 static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); 131 static int ale_rxeof(struct ale_softc *sc, int); 132 static void ale_rxfilter(struct ale_softc *); 133 static void ale_rxvlan(struct ale_softc *); 134 static void ale_setlinkspeed(struct ale_softc *); 135 static void ale_setwol(struct ale_softc *); 136 static int ale_shutdown(device_t); 137 static void ale_start(if_t); 138 static void ale_start_locked(if_t); 139 static void ale_stats_clear(struct ale_softc *); 140 static void ale_stats_update(struct ale_softc *); 141 static void ale_stop(struct ale_softc *); 142 static void ale_stop_mac(struct ale_softc *); 143 static int ale_suspend(device_t); 144 static void ale_sysctl_node(struct ale_softc *); 145 static void ale_tick(void *); 146 static void ale_txeof(struct ale_softc *); 147 static void ale_watchdog(struct ale_softc *); 148 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 149 static int sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS); 150 static int sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS); 151 152 static device_method_t ale_methods[] = { 153 /* Device interface. */ 154 DEVMETHOD(device_probe, ale_probe), 155 DEVMETHOD(device_attach, ale_attach), 156 DEVMETHOD(device_detach, ale_detach), 157 DEVMETHOD(device_shutdown, ale_shutdown), 158 DEVMETHOD(device_suspend, ale_suspend), 159 DEVMETHOD(device_resume, ale_resume), 160 161 /* MII interface. */ 162 DEVMETHOD(miibus_readreg, ale_miibus_readreg), 163 DEVMETHOD(miibus_writereg, ale_miibus_writereg), 164 DEVMETHOD(miibus_statchg, ale_miibus_statchg), 165 166 DEVMETHOD_END 167 }; 168 169 static driver_t ale_driver = { 170 "ale", 171 ale_methods, 172 sizeof(struct ale_softc) 173 }; 174 175 DRIVER_MODULE(ale, pci, ale_driver, NULL, NULL); 176 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, ale, ale_devs, 177 nitems(ale_devs)); 178 DRIVER_MODULE(miibus, ale, miibus_driver, NULL, NULL); 179 180 static struct resource_spec ale_res_spec_mem[] = { 181 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 182 { -1, 0, 0 } 183 }; 184 185 static struct resource_spec ale_irq_spec_legacy[] = { 186 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 187 { -1, 0, 0 } 188 }; 189 190 static struct resource_spec ale_irq_spec_msi[] = { 191 { SYS_RES_IRQ, 1, RF_ACTIVE }, 192 { -1, 0, 0 } 193 }; 194 195 static struct resource_spec ale_irq_spec_msix[] = { 196 { SYS_RES_IRQ, 1, RF_ACTIVE }, 197 { -1, 0, 0 } 198 }; 199 200 static int 201 ale_miibus_readreg(device_t dev, int phy, int reg) 202 { 203 struct ale_softc *sc; 204 uint32_t v; 205 int i; 206 207 sc = device_get_softc(dev); 208 209 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 210 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 211 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 212 DELAY(5); 213 v = CSR_READ_4(sc, ALE_MDIO); 214 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 215 break; 216 } 217 218 if (i == 0) { 219 device_printf(sc->ale_dev, "phy read timeout : %d\n", reg); 220 return (0); 221 } 222 223 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 224 } 225 226 static int 227 ale_miibus_writereg(device_t dev, int phy, int reg, int val) 228 { 229 struct ale_softc *sc; 230 uint32_t v; 231 int i; 232 233 sc = device_get_softc(dev); 234 235 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 236 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 237 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 238 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 239 DELAY(5); 240 v = CSR_READ_4(sc, ALE_MDIO); 241 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 242 break; 243 } 244 245 if (i == 0) 246 device_printf(sc->ale_dev, "phy write timeout : %d\n", reg); 247 248 return (0); 249 } 250 251 static void 252 ale_miibus_statchg(device_t dev) 253 { 254 struct ale_softc *sc; 255 struct mii_data *mii; 256 if_t ifp; 257 uint32_t reg; 258 259 sc = device_get_softc(dev); 260 mii = device_get_softc(sc->ale_miibus); 261 ifp = sc->ale_ifp; 262 if (mii == NULL || ifp == NULL || 263 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 264 return; 265 266 sc->ale_flags &= ~ALE_FLAG_LINK; 267 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 268 (IFM_ACTIVE | IFM_AVALID)) { 269 switch (IFM_SUBTYPE(mii->mii_media_active)) { 270 case IFM_10_T: 271 case IFM_100_TX: 272 sc->ale_flags |= ALE_FLAG_LINK; 273 break; 274 case IFM_1000_T: 275 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 276 sc->ale_flags |= ALE_FLAG_LINK; 277 break; 278 default: 279 break; 280 } 281 } 282 283 /* Stop Rx/Tx MACs. */ 284 ale_stop_mac(sc); 285 286 /* Program MACs with resolved speed/duplex/flow-control. */ 287 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { 288 ale_mac_config(sc); 289 /* Reenable Tx/Rx MACs. */ 290 reg = CSR_READ_4(sc, ALE_MAC_CFG); 291 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 292 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 293 } 294 } 295 296 static void 297 ale_mediastatus(if_t ifp, struct ifmediareq *ifmr) 298 { 299 struct ale_softc *sc; 300 struct mii_data *mii; 301 302 sc = if_getsoftc(ifp); 303 ALE_LOCK(sc); 304 if ((if_getflags(ifp) & IFF_UP) == 0) { 305 ALE_UNLOCK(sc); 306 return; 307 } 308 mii = device_get_softc(sc->ale_miibus); 309 310 mii_pollstat(mii); 311 ifmr->ifm_status = mii->mii_media_status; 312 ifmr->ifm_active = mii->mii_media_active; 313 ALE_UNLOCK(sc); 314 } 315 316 static int 317 ale_mediachange(if_t ifp) 318 { 319 struct ale_softc *sc; 320 struct mii_data *mii; 321 struct mii_softc *miisc; 322 int error; 323 324 sc = if_getsoftc(ifp); 325 ALE_LOCK(sc); 326 mii = device_get_softc(sc->ale_miibus); 327 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 328 PHY_RESET(miisc); 329 error = mii_mediachg(mii); 330 ALE_UNLOCK(sc); 331 332 return (error); 333 } 334 335 static int 336 ale_probe(device_t dev) 337 { 338 const struct ale_dev *sp; 339 int i; 340 uint16_t vendor, devid; 341 342 vendor = pci_get_vendor(dev); 343 devid = pci_get_device(dev); 344 sp = ale_devs; 345 for (i = 0; i < nitems(ale_devs); i++) { 346 if (vendor == sp->ale_vendorid && 347 devid == sp->ale_deviceid) { 348 device_set_desc(dev, sp->ale_name); 349 return (BUS_PROBE_DEFAULT); 350 } 351 sp++; 352 } 353 354 return (ENXIO); 355 } 356 357 static void 358 ale_get_macaddr(struct ale_softc *sc) 359 { 360 uint32_t ea[2], reg; 361 int i, vpdc; 362 363 reg = CSR_READ_4(sc, ALE_SPI_CTRL); 364 if ((reg & SPI_VPD_ENB) != 0) { 365 reg &= ~SPI_VPD_ENB; 366 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); 367 } 368 369 if (pci_find_cap(sc->ale_dev, PCIY_VPD, &vpdc) == 0) { 370 /* 371 * PCI VPD capability found, let TWSI reload EEPROM. 372 * This will set ethernet address of controller. 373 */ 374 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | 375 TWSI_CTRL_SW_LD_START); 376 for (i = 100; i > 0; i--) { 377 DELAY(1000); 378 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); 379 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 380 break; 381 } 382 if (i == 0) 383 device_printf(sc->ale_dev, 384 "reloading EEPROM timeout!\n"); 385 } else { 386 if (bootverbose) 387 device_printf(sc->ale_dev, 388 "PCI VPD capability not found!\n"); 389 } 390 391 ea[0] = CSR_READ_4(sc, ALE_PAR0); 392 ea[1] = CSR_READ_4(sc, ALE_PAR1); 393 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; 394 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; 395 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; 396 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; 397 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; 398 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; 399 } 400 401 static void 402 ale_phy_reset(struct ale_softc *sc) 403 { 404 405 /* Reset magic from Linux. */ 406 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 407 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 408 GPHY_CTRL_PHY_PLL_ON); 409 DELAY(1000); 410 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 411 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | 412 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); 413 DELAY(1000); 414 415 #define ATPHY_DBG_ADDR 0x1D 416 #define ATPHY_DBG_DATA 0x1E 417 418 /* Enable hibernation mode. */ 419 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 420 ATPHY_DBG_ADDR, 0x0B); 421 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 422 ATPHY_DBG_DATA, 0xBC00); 423 /* Set Class A/B for all modes. */ 424 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 425 ATPHY_DBG_ADDR, 0x00); 426 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 427 ATPHY_DBG_DATA, 0x02EF); 428 /* Enable 10BT power saving. */ 429 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 430 ATPHY_DBG_ADDR, 0x12); 431 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 432 ATPHY_DBG_DATA, 0x4C04); 433 /* Adjust 1000T power. */ 434 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 435 ATPHY_DBG_ADDR, 0x04); 436 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 437 ATPHY_DBG_ADDR, 0x8BBB); 438 /* 10BT center tap voltage. */ 439 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 440 ATPHY_DBG_ADDR, 0x05); 441 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 442 ATPHY_DBG_ADDR, 0x2C46); 443 444 #undef ATPHY_DBG_ADDR 445 #undef ATPHY_DBG_DATA 446 DELAY(1000); 447 } 448 449 static int 450 ale_attach(device_t dev) 451 { 452 struct ale_softc *sc; 453 if_t ifp; 454 uint16_t burst; 455 int error, i, msic, msixc; 456 uint32_t rxf_len, txf_len; 457 458 error = 0; 459 sc = device_get_softc(dev); 460 sc->ale_dev = dev; 461 462 mtx_init(&sc->ale_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 463 MTX_DEF); 464 callout_init_mtx(&sc->ale_tick_ch, &sc->ale_mtx, 0); 465 NET_TASK_INIT(&sc->ale_int_task, 0, ale_int_task, sc); 466 467 /* Map the device. */ 468 pci_enable_busmaster(dev); 469 sc->ale_res_spec = ale_res_spec_mem; 470 sc->ale_irq_spec = ale_irq_spec_legacy; 471 error = bus_alloc_resources(dev, sc->ale_res_spec, sc->ale_res); 472 if (error != 0) { 473 device_printf(dev, "cannot allocate memory resources.\n"); 474 goto fail; 475 } 476 477 /* Set PHY address. */ 478 sc->ale_phyaddr = ALE_PHY_ADDR; 479 480 /* Reset PHY. */ 481 ale_phy_reset(sc); 482 483 /* Reset the ethernet controller. */ 484 ale_reset(sc); 485 486 /* Get PCI and chip id/revision. */ 487 sc->ale_rev = pci_get_revid(dev); 488 if (sc->ale_rev >= 0xF0) { 489 /* L2E Rev. B. AR8114 */ 490 sc->ale_flags |= ALE_FLAG_FASTETHER; 491 } else { 492 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { 493 /* L1E AR8121 */ 494 sc->ale_flags |= ALE_FLAG_JUMBO; 495 } else { 496 /* L2E Rev. A. AR8113 */ 497 sc->ale_flags |= ALE_FLAG_FASTETHER; 498 } 499 } 500 /* 501 * All known controllers seems to require 4 bytes alignment 502 * of Tx buffers to make Tx checksum offload with custom 503 * checksum generation method work. 504 */ 505 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; 506 /* 507 * All known controllers seems to have issues on Rx checksum 508 * offload for fragmented IP datagrams. 509 */ 510 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; 511 /* 512 * Don't use Tx CMB. It is known to cause RRS update failure 513 * under certain circumstances. Typical phenomenon of the 514 * issue would be unexpected sequence number encountered in 515 * Rx handler. 516 */ 517 sc->ale_flags |= ALE_FLAG_TXCMB_BUG; 518 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> 519 MASTER_CHIP_REV_SHIFT; 520 if (bootverbose) { 521 device_printf(dev, "PCI device revision : 0x%04x\n", 522 sc->ale_rev); 523 device_printf(dev, "Chip id/revision : 0x%04x\n", 524 sc->ale_chip_rev); 525 } 526 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); 527 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 528 /* 529 * Uninitialized hardware returns an invalid chip id/revision 530 * as well as 0xFFFFFFFF for Tx/Rx fifo length. 531 */ 532 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || 533 rxf_len == 0xFFFFFFF) { 534 device_printf(dev,"chip revision : 0x%04x, %u Tx FIFO " 535 "%u Rx FIFO -- not initialized?\n", sc->ale_chip_rev, 536 txf_len, rxf_len); 537 error = ENXIO; 538 goto fail; 539 } 540 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", txf_len, rxf_len); 541 542 /* Allocate IRQ resources. */ 543 msixc = pci_msix_count(dev); 544 msic = pci_msi_count(dev); 545 if (bootverbose) { 546 device_printf(dev, "MSIX count : %d\n", msixc); 547 device_printf(dev, "MSI count : %d\n", msic); 548 } 549 550 /* Prefer MSIX over MSI. */ 551 if (msix_disable == 0 || msi_disable == 0) { 552 if (msix_disable == 0 && msixc == ALE_MSIX_MESSAGES && 553 pci_alloc_msix(dev, &msixc) == 0) { 554 if (msixc == ALE_MSIX_MESSAGES) { 555 device_printf(dev, "Using %d MSIX messages.\n", 556 msixc); 557 sc->ale_flags |= ALE_FLAG_MSIX; 558 sc->ale_irq_spec = ale_irq_spec_msix; 559 } else 560 pci_release_msi(dev); 561 } 562 if (msi_disable == 0 && (sc->ale_flags & ALE_FLAG_MSIX) == 0 && 563 msic == ALE_MSI_MESSAGES && 564 pci_alloc_msi(dev, &msic) == 0) { 565 if (msic == ALE_MSI_MESSAGES) { 566 device_printf(dev, "Using %d MSI messages.\n", 567 msic); 568 sc->ale_flags |= ALE_FLAG_MSI; 569 sc->ale_irq_spec = ale_irq_spec_msi; 570 } else 571 pci_release_msi(dev); 572 } 573 } 574 575 error = bus_alloc_resources(dev, sc->ale_irq_spec, sc->ale_irq); 576 if (error != 0) { 577 device_printf(dev, "cannot allocate IRQ resources.\n"); 578 goto fail; 579 } 580 581 /* Get DMA parameters from PCIe device control register. */ 582 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 583 sc->ale_flags |= ALE_FLAG_PCIE; 584 burst = pci_read_config(dev, i + 0x08, 2); 585 /* Max read request size. */ 586 sc->ale_dma_rd_burst = ((burst >> 12) & 0x07) << 587 DMA_CFG_RD_BURST_SHIFT; 588 /* Max payload size. */ 589 sc->ale_dma_wr_burst = ((burst >> 5) & 0x07) << 590 DMA_CFG_WR_BURST_SHIFT; 591 if (bootverbose) { 592 device_printf(dev, "Read request size : %d bytes.\n", 593 128 << ((burst >> 12) & 0x07)); 594 device_printf(dev, "TLP payload size : %d bytes.\n", 595 128 << ((burst >> 5) & 0x07)); 596 } 597 } else { 598 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; 599 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; 600 } 601 602 /* Create device sysctl node. */ 603 ale_sysctl_node(sc); 604 605 if ((error = ale_dma_alloc(sc)) != 0) 606 goto fail; 607 608 /* Load station address. */ 609 ale_get_macaddr(sc); 610 611 ifp = sc->ale_ifp = if_alloc(IFT_ETHER); 612 if_setsoftc(ifp, sc); 613 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 614 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 615 if_setioctlfn(ifp, ale_ioctl); 616 if_setstartfn(ifp, ale_start); 617 if_setinitfn(ifp, ale_init); 618 if_setsendqlen(ifp, ALE_TX_RING_CNT - 1); 619 if_setsendqready(ifp); 620 if_setcapabilities(ifp, IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4); 621 if_sethwassist(ifp, ALE_CSUM_FEATURES | CSUM_TSO); 622 if (pci_has_pm(dev)) { 623 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST, 0); 624 } 625 if_setcapenable(ifp, if_getcapabilities(ifp)); 626 627 /* Set up MII bus. */ 628 error = mii_attach(dev, &sc->ale_miibus, ifp, ale_mediachange, 629 ale_mediastatus, BMSR_DEFCAPMASK, sc->ale_phyaddr, MII_OFFSET_ANY, 630 MIIF_DOPAUSE); 631 if (error != 0) { 632 device_printf(dev, "attaching PHYs failed\n"); 633 goto fail; 634 } 635 636 ether_ifattach(ifp, sc->ale_eaddr); 637 638 /* VLAN capability setup. */ 639 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 640 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0); 641 if_setcapenable(ifp, if_getcapabilities(ifp)); 642 /* 643 * Even though controllers supported by ale(3) have Rx checksum 644 * offload bug the workaround for fragmented frames seemed to 645 * work so far. However it seems Rx checksum offload does not 646 * work under certain conditions. So disable Rx checksum offload 647 * until I find more clue about it but allow users to override it. 648 */ 649 if_setcapenablebit(ifp, 0, IFCAP_RXCSUM); 650 651 /* Tell the upper layer(s) we support long frames. */ 652 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 653 654 /* Create local taskq. */ 655 sc->ale_tq = taskqueue_create_fast("ale_taskq", M_WAITOK, 656 taskqueue_thread_enqueue, &sc->ale_tq); 657 taskqueue_start_threads(&sc->ale_tq, 1, PI_NET, "%s taskq", 658 device_get_nameunit(sc->ale_dev)); 659 660 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 661 msic = ALE_MSIX_MESSAGES; 662 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 663 msic = ALE_MSI_MESSAGES; 664 else 665 msic = 1; 666 for (i = 0; i < msic; i++) { 667 error = bus_setup_intr(dev, sc->ale_irq[i], 668 INTR_TYPE_NET | INTR_MPSAFE, ale_intr, NULL, sc, 669 &sc->ale_intrhand[i]); 670 if (error != 0) 671 break; 672 } 673 if (error != 0) { 674 device_printf(dev, "could not set up interrupt handler.\n"); 675 taskqueue_free(sc->ale_tq); 676 sc->ale_tq = NULL; 677 ether_ifdetach(ifp); 678 goto fail; 679 } 680 681 fail: 682 if (error != 0) 683 ale_detach(dev); 684 685 return (error); 686 } 687 688 static int 689 ale_detach(device_t dev) 690 { 691 struct ale_softc *sc; 692 if_t ifp; 693 int i, msic; 694 695 sc = device_get_softc(dev); 696 697 ifp = sc->ale_ifp; 698 if (device_is_attached(dev)) { 699 ether_ifdetach(ifp); 700 ALE_LOCK(sc); 701 ale_stop(sc); 702 ALE_UNLOCK(sc); 703 callout_drain(&sc->ale_tick_ch); 704 taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 705 } 706 707 if (sc->ale_tq != NULL) { 708 taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 709 taskqueue_free(sc->ale_tq); 710 sc->ale_tq = NULL; 711 } 712 713 bus_generic_detach(dev); 714 ale_dma_free(sc); 715 716 if (ifp != NULL) { 717 if_free(ifp); 718 sc->ale_ifp = NULL; 719 } 720 721 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 722 msic = ALE_MSIX_MESSAGES; 723 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 724 msic = ALE_MSI_MESSAGES; 725 else 726 msic = 1; 727 for (i = 0; i < msic; i++) { 728 if (sc->ale_intrhand[i] != NULL) { 729 bus_teardown_intr(dev, sc->ale_irq[i], 730 sc->ale_intrhand[i]); 731 sc->ale_intrhand[i] = NULL; 732 } 733 } 734 735 bus_release_resources(dev, sc->ale_irq_spec, sc->ale_irq); 736 if ((sc->ale_flags & (ALE_FLAG_MSI | ALE_FLAG_MSIX)) != 0) 737 pci_release_msi(dev); 738 bus_release_resources(dev, sc->ale_res_spec, sc->ale_res); 739 mtx_destroy(&sc->ale_mtx); 740 741 return (0); 742 } 743 744 #define ALE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 745 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 746 747 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 748 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 749 750 static void 751 ale_sysctl_node(struct ale_softc *sc) 752 { 753 struct sysctl_ctx_list *ctx; 754 struct sysctl_oid_list *child, *parent; 755 struct sysctl_oid *tree; 756 struct ale_hw_stats *stats; 757 int error; 758 759 stats = &sc->ale_stats; 760 ctx = device_get_sysctl_ctx(sc->ale_dev); 761 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ale_dev)); 762 763 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 764 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->ale_int_rx_mod, 765 0, sysctl_hw_ale_int_mod, "I", "ale Rx interrupt moderation"); 766 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 767 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->ale_int_tx_mod, 768 0, sysctl_hw_ale_int_mod, "I", "ale Tx interrupt moderation"); 769 /* Pull in device tunables. */ 770 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 771 error = resource_int_value(device_get_name(sc->ale_dev), 772 device_get_unit(sc->ale_dev), "int_rx_mod", &sc->ale_int_rx_mod); 773 if (error == 0) { 774 if (sc->ale_int_rx_mod < ALE_IM_TIMER_MIN || 775 sc->ale_int_rx_mod > ALE_IM_TIMER_MAX) { 776 device_printf(sc->ale_dev, "int_rx_mod value out of " 777 "range; using default: %d\n", 778 ALE_IM_RX_TIMER_DEFAULT); 779 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 780 } 781 } 782 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 783 error = resource_int_value(device_get_name(sc->ale_dev), 784 device_get_unit(sc->ale_dev), "int_tx_mod", &sc->ale_int_tx_mod); 785 if (error == 0) { 786 if (sc->ale_int_tx_mod < ALE_IM_TIMER_MIN || 787 sc->ale_int_tx_mod > ALE_IM_TIMER_MAX) { 788 device_printf(sc->ale_dev, "int_tx_mod value out of " 789 "range; using default: %d\n", 790 ALE_IM_TX_TIMER_DEFAULT); 791 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 792 } 793 } 794 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 795 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 796 &sc->ale_process_limit, 0, sysctl_hw_ale_proc_limit, "I", 797 "max number of Rx events to process"); 798 /* Pull in device tunables. */ 799 sc->ale_process_limit = ALE_PROC_DEFAULT; 800 error = resource_int_value(device_get_name(sc->ale_dev), 801 device_get_unit(sc->ale_dev), "process_limit", 802 &sc->ale_process_limit); 803 if (error == 0) { 804 if (sc->ale_process_limit < ALE_PROC_MIN || 805 sc->ale_process_limit > ALE_PROC_MAX) { 806 device_printf(sc->ale_dev, 807 "process_limit value out of range; " 808 "using default: %d\n", ALE_PROC_DEFAULT); 809 sc->ale_process_limit = ALE_PROC_DEFAULT; 810 } 811 } 812 813 /* Misc statistics. */ 814 ALE_SYSCTL_STAT_ADD32(ctx, child, "reset_brk_seq", 815 &stats->reset_brk_seq, 816 "Controller resets due to broken Rx sequnce number"); 817 818 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 819 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ATE statistics"); 820 parent = SYSCTL_CHILDREN(tree); 821 822 /* Rx statistics. */ 823 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 824 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics"); 825 child = SYSCTL_CHILDREN(tree); 826 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 827 &stats->rx_frames, "Good frames"); 828 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 829 &stats->rx_bcast_frames, "Good broadcast frames"); 830 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 831 &stats->rx_mcast_frames, "Good multicast frames"); 832 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 833 &stats->rx_pause_frames, "Pause control frames"); 834 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 835 &stats->rx_control_frames, "Control frames"); 836 ALE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 837 &stats->rx_crcerrs, "CRC errors"); 838 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 839 &stats->rx_lenerrs, "Frames with length mismatched"); 840 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 841 &stats->rx_bytes, "Good octets"); 842 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 843 &stats->rx_bcast_bytes, "Good broadcast octets"); 844 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 845 &stats->rx_mcast_bytes, "Good multicast octets"); 846 ALE_SYSCTL_STAT_ADD32(ctx, child, "runts", 847 &stats->rx_runts, "Too short frames"); 848 ALE_SYSCTL_STAT_ADD32(ctx, child, "fragments", 849 &stats->rx_fragments, "Fragmented frames"); 850 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 851 &stats->rx_pkts_64, "64 bytes frames"); 852 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 853 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 854 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 855 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 856 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 857 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 858 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 859 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 860 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 861 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 862 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 863 &stats->rx_pkts_1519_max, "1519 to max frames"); 864 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 865 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 866 ALE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 867 &stats->rx_fifo_oflows, "FIFO overflows"); 868 ALE_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 869 &stats->rx_rrs_errs, "Return status write-back errors"); 870 ALE_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 871 &stats->rx_alignerrs, "Alignment errors"); 872 ALE_SYSCTL_STAT_ADD32(ctx, child, "filtered", 873 &stats->rx_pkts_filtered, 874 "Frames dropped due to address filtering"); 875 876 /* Tx statistics. */ 877 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 878 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics"); 879 child = SYSCTL_CHILDREN(tree); 880 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 881 &stats->tx_frames, "Good frames"); 882 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 883 &stats->tx_bcast_frames, "Good broadcast frames"); 884 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 885 &stats->tx_mcast_frames, "Good multicast frames"); 886 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 887 &stats->tx_pause_frames, "Pause control frames"); 888 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 889 &stats->tx_control_frames, "Control frames"); 890 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 891 &stats->tx_excess_defer, "Frames with excessive derferrals"); 892 ALE_SYSCTL_STAT_ADD32(ctx, child, "defers", 893 &stats->tx_excess_defer, "Frames with derferrals"); 894 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 895 &stats->tx_bytes, "Good octets"); 896 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 897 &stats->tx_bcast_bytes, "Good broadcast octets"); 898 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 899 &stats->tx_mcast_bytes, "Good multicast octets"); 900 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 901 &stats->tx_pkts_64, "64 bytes frames"); 902 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 903 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 904 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 905 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 906 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 907 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 908 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 909 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 910 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 911 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 912 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 913 &stats->tx_pkts_1519_max, "1519 to max frames"); 914 ALE_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 915 &stats->tx_single_colls, "Single collisions"); 916 ALE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 917 &stats->tx_multi_colls, "Multiple collisions"); 918 ALE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 919 &stats->tx_late_colls, "Late collisions"); 920 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 921 &stats->tx_excess_colls, "Excessive collisions"); 922 ALE_SYSCTL_STAT_ADD32(ctx, child, "underruns", 923 &stats->tx_underrun, "FIFO underruns"); 924 ALE_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 925 &stats->tx_desc_underrun, "Descriptor write-back errors"); 926 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 927 &stats->tx_lenerrs, "Frames with length mismatched"); 928 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 929 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 930 } 931 932 #undef ALE_SYSCTL_STAT_ADD32 933 #undef ALE_SYSCTL_STAT_ADD64 934 935 struct ale_dmamap_arg { 936 bus_addr_t ale_busaddr; 937 }; 938 939 static void 940 ale_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 941 { 942 struct ale_dmamap_arg *ctx; 943 944 if (error != 0) 945 return; 946 947 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 948 949 ctx = (struct ale_dmamap_arg *)arg; 950 ctx->ale_busaddr = segs[0].ds_addr; 951 } 952 953 /* 954 * Tx descriptors/RXF0/CMB DMA blocks share ALE_DESC_ADDR_HI register 955 * which specifies high address region of DMA blocks. Therefore these 956 * blocks should have the same high address of given 4GB address 957 * space(i.e. crossing 4GB boundary is not allowed). 958 */ 959 static int 960 ale_check_boundary(struct ale_softc *sc) 961 { 962 bus_addr_t rx_cmb_end[ALE_RX_PAGES], tx_cmb_end; 963 bus_addr_t rx_page_end[ALE_RX_PAGES], tx_ring_end; 964 965 rx_page_end[0] = sc->ale_cdata.ale_rx_page[0].page_paddr + 966 sc->ale_pagesize; 967 rx_page_end[1] = sc->ale_cdata.ale_rx_page[1].page_paddr + 968 sc->ale_pagesize; 969 tx_ring_end = sc->ale_cdata.ale_tx_ring_paddr + ALE_TX_RING_SZ; 970 tx_cmb_end = sc->ale_cdata.ale_tx_cmb_paddr + ALE_TX_CMB_SZ; 971 rx_cmb_end[0] = sc->ale_cdata.ale_rx_page[0].cmb_paddr + ALE_RX_CMB_SZ; 972 rx_cmb_end[1] = sc->ale_cdata.ale_rx_page[1].cmb_paddr + ALE_RX_CMB_SZ; 973 974 if ((ALE_ADDR_HI(tx_ring_end) != 975 ALE_ADDR_HI(sc->ale_cdata.ale_tx_ring_paddr)) || 976 (ALE_ADDR_HI(rx_page_end[0]) != 977 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].page_paddr)) || 978 (ALE_ADDR_HI(rx_page_end[1]) != 979 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].page_paddr)) || 980 (ALE_ADDR_HI(tx_cmb_end) != 981 ALE_ADDR_HI(sc->ale_cdata.ale_tx_cmb_paddr)) || 982 (ALE_ADDR_HI(rx_cmb_end[0]) != 983 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].cmb_paddr)) || 984 (ALE_ADDR_HI(rx_cmb_end[1]) != 985 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].cmb_paddr))) 986 return (EFBIG); 987 988 if ((ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[0])) || 989 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[1])) || 990 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[0])) || 991 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[1])) || 992 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(tx_cmb_end))) 993 return (EFBIG); 994 995 return (0); 996 } 997 998 static int 999 ale_dma_alloc(struct ale_softc *sc) 1000 { 1001 struct ale_txdesc *txd; 1002 bus_addr_t lowaddr; 1003 struct ale_dmamap_arg ctx; 1004 int error, guard_size, i; 1005 1006 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 1007 guard_size = ALE_JUMBO_FRAMELEN; 1008 else 1009 guard_size = ALE_MAX_FRAMELEN; 1010 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, 1011 ALE_RX_PAGE_ALIGN); 1012 lowaddr = BUS_SPACE_MAXADDR; 1013 again: 1014 /* Create parent DMA tag. */ 1015 error = bus_dma_tag_create( 1016 bus_get_dma_tag(sc->ale_dev), /* parent */ 1017 1, 0, /* alignment, boundary */ 1018 lowaddr, /* lowaddr */ 1019 BUS_SPACE_MAXADDR, /* highaddr */ 1020 NULL, NULL, /* filter, filterarg */ 1021 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1022 0, /* nsegments */ 1023 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1024 0, /* flags */ 1025 NULL, NULL, /* lockfunc, lockarg */ 1026 &sc->ale_cdata.ale_parent_tag); 1027 if (error != 0) { 1028 device_printf(sc->ale_dev, 1029 "could not create parent DMA tag.\n"); 1030 goto fail; 1031 } 1032 1033 /* Create DMA tag for Tx descriptor ring. */ 1034 error = bus_dma_tag_create( 1035 sc->ale_cdata.ale_parent_tag, /* parent */ 1036 ALE_TX_RING_ALIGN, 0, /* alignment, boundary */ 1037 BUS_SPACE_MAXADDR, /* lowaddr */ 1038 BUS_SPACE_MAXADDR, /* highaddr */ 1039 NULL, NULL, /* filter, filterarg */ 1040 ALE_TX_RING_SZ, /* maxsize */ 1041 1, /* nsegments */ 1042 ALE_TX_RING_SZ, /* maxsegsize */ 1043 0, /* flags */ 1044 NULL, NULL, /* lockfunc, lockarg */ 1045 &sc->ale_cdata.ale_tx_ring_tag); 1046 if (error != 0) { 1047 device_printf(sc->ale_dev, 1048 "could not create Tx ring DMA tag.\n"); 1049 goto fail; 1050 } 1051 1052 /* Create DMA tag for Rx pages. */ 1053 for (i = 0; i < ALE_RX_PAGES; i++) { 1054 error = bus_dma_tag_create( 1055 sc->ale_cdata.ale_parent_tag, /* parent */ 1056 ALE_RX_PAGE_ALIGN, 0, /* alignment, boundary */ 1057 BUS_SPACE_MAXADDR, /* lowaddr */ 1058 BUS_SPACE_MAXADDR, /* highaddr */ 1059 NULL, NULL, /* filter, filterarg */ 1060 sc->ale_pagesize, /* maxsize */ 1061 1, /* nsegments */ 1062 sc->ale_pagesize, /* maxsegsize */ 1063 0, /* flags */ 1064 NULL, NULL, /* lockfunc, lockarg */ 1065 &sc->ale_cdata.ale_rx_page[i].page_tag); 1066 if (error != 0) { 1067 device_printf(sc->ale_dev, 1068 "could not create Rx page %d DMA tag.\n", i); 1069 goto fail; 1070 } 1071 } 1072 1073 /* Create DMA tag for Tx coalescing message block. */ 1074 error = bus_dma_tag_create( 1075 sc->ale_cdata.ale_parent_tag, /* parent */ 1076 ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1077 BUS_SPACE_MAXADDR, /* lowaddr */ 1078 BUS_SPACE_MAXADDR, /* highaddr */ 1079 NULL, NULL, /* filter, filterarg */ 1080 ALE_TX_CMB_SZ, /* maxsize */ 1081 1, /* nsegments */ 1082 ALE_TX_CMB_SZ, /* maxsegsize */ 1083 0, /* flags */ 1084 NULL, NULL, /* lockfunc, lockarg */ 1085 &sc->ale_cdata.ale_tx_cmb_tag); 1086 if (error != 0) { 1087 device_printf(sc->ale_dev, 1088 "could not create Tx CMB DMA tag.\n"); 1089 goto fail; 1090 } 1091 1092 /* Create DMA tag for Rx coalescing message block. */ 1093 for (i = 0; i < ALE_RX_PAGES; i++) { 1094 error = bus_dma_tag_create( 1095 sc->ale_cdata.ale_parent_tag, /* parent */ 1096 ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1097 BUS_SPACE_MAXADDR, /* lowaddr */ 1098 BUS_SPACE_MAXADDR, /* highaddr */ 1099 NULL, NULL, /* filter, filterarg */ 1100 ALE_RX_CMB_SZ, /* maxsize */ 1101 1, /* nsegments */ 1102 ALE_RX_CMB_SZ, /* maxsegsize */ 1103 0, /* flags */ 1104 NULL, NULL, /* lockfunc, lockarg */ 1105 &sc->ale_cdata.ale_rx_page[i].cmb_tag); 1106 if (error != 0) { 1107 device_printf(sc->ale_dev, 1108 "could not create Rx page %d CMB DMA tag.\n", i); 1109 goto fail; 1110 } 1111 } 1112 1113 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1114 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_ring_tag, 1115 (void **)&sc->ale_cdata.ale_tx_ring, 1116 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1117 &sc->ale_cdata.ale_tx_ring_map); 1118 if (error != 0) { 1119 device_printf(sc->ale_dev, 1120 "could not allocate DMA'able memory for Tx ring.\n"); 1121 goto fail; 1122 } 1123 ctx.ale_busaddr = 0; 1124 error = bus_dmamap_load(sc->ale_cdata.ale_tx_ring_tag, 1125 sc->ale_cdata.ale_tx_ring_map, sc->ale_cdata.ale_tx_ring, 1126 ALE_TX_RING_SZ, ale_dmamap_cb, &ctx, 0); 1127 if (error != 0 || ctx.ale_busaddr == 0) { 1128 device_printf(sc->ale_dev, 1129 "could not load DMA'able memory for Tx ring.\n"); 1130 goto fail; 1131 } 1132 sc->ale_cdata.ale_tx_ring_paddr = ctx.ale_busaddr; 1133 1134 /* Rx pages. */ 1135 for (i = 0; i < ALE_RX_PAGES; i++) { 1136 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].page_tag, 1137 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr, 1138 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1139 &sc->ale_cdata.ale_rx_page[i].page_map); 1140 if (error != 0) { 1141 device_printf(sc->ale_dev, 1142 "could not allocate DMA'able memory for " 1143 "Rx page %d.\n", i); 1144 goto fail; 1145 } 1146 ctx.ale_busaddr = 0; 1147 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].page_tag, 1148 sc->ale_cdata.ale_rx_page[i].page_map, 1149 sc->ale_cdata.ale_rx_page[i].page_addr, 1150 sc->ale_pagesize, ale_dmamap_cb, &ctx, 0); 1151 if (error != 0 || ctx.ale_busaddr == 0) { 1152 device_printf(sc->ale_dev, 1153 "could not load DMA'able memory for " 1154 "Rx page %d.\n", i); 1155 goto fail; 1156 } 1157 sc->ale_cdata.ale_rx_page[i].page_paddr = ctx.ale_busaddr; 1158 } 1159 1160 /* Tx CMB. */ 1161 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_cmb_tag, 1162 (void **)&sc->ale_cdata.ale_tx_cmb, 1163 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1164 &sc->ale_cdata.ale_tx_cmb_map); 1165 if (error != 0) { 1166 device_printf(sc->ale_dev, 1167 "could not allocate DMA'able memory for Tx CMB.\n"); 1168 goto fail; 1169 } 1170 ctx.ale_busaddr = 0; 1171 error = bus_dmamap_load(sc->ale_cdata.ale_tx_cmb_tag, 1172 sc->ale_cdata.ale_tx_cmb_map, sc->ale_cdata.ale_tx_cmb, 1173 ALE_TX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1174 if (error != 0 || ctx.ale_busaddr == 0) { 1175 device_printf(sc->ale_dev, 1176 "could not load DMA'able memory for Tx CMB.\n"); 1177 goto fail; 1178 } 1179 sc->ale_cdata.ale_tx_cmb_paddr = ctx.ale_busaddr; 1180 1181 /* Rx CMB. */ 1182 for (i = 0; i < ALE_RX_PAGES; i++) { 1183 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1184 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 1185 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1186 &sc->ale_cdata.ale_rx_page[i].cmb_map); 1187 if (error != 0) { 1188 device_printf(sc->ale_dev, "could not allocate " 1189 "DMA'able memory for Rx page %d CMB.\n", i); 1190 goto fail; 1191 } 1192 ctx.ale_busaddr = 0; 1193 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1194 sc->ale_cdata.ale_rx_page[i].cmb_map, 1195 sc->ale_cdata.ale_rx_page[i].cmb_addr, 1196 ALE_RX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1197 if (error != 0 || ctx.ale_busaddr == 0) { 1198 device_printf(sc->ale_dev, "could not load DMA'able " 1199 "memory for Rx page %d CMB.\n", i); 1200 goto fail; 1201 } 1202 sc->ale_cdata.ale_rx_page[i].cmb_paddr = ctx.ale_busaddr; 1203 } 1204 1205 /* 1206 * Tx descriptors/RXF0/CMB DMA blocks share the same 1207 * high address region of 64bit DMA address space. 1208 */ 1209 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1210 (error = ale_check_boundary(sc)) != 0) { 1211 device_printf(sc->ale_dev, "4GB boundary crossed, " 1212 "switching to 32bit DMA addressing mode.\n"); 1213 ale_dma_free(sc); 1214 /* 1215 * Limit max allowable DMA address space to 32bit 1216 * and try again. 1217 */ 1218 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1219 goto again; 1220 } 1221 1222 /* 1223 * Create Tx buffer parent tag. 1224 * AR81xx allows 64bit DMA addressing of Tx buffers so it 1225 * needs separate parent DMA tag as parent DMA address space 1226 * could be restricted to be within 32bit address space by 1227 * 4GB boundary crossing. 1228 */ 1229 error = bus_dma_tag_create( 1230 bus_get_dma_tag(sc->ale_dev), /* parent */ 1231 1, 0, /* alignment, boundary */ 1232 BUS_SPACE_MAXADDR, /* lowaddr */ 1233 BUS_SPACE_MAXADDR, /* highaddr */ 1234 NULL, NULL, /* filter, filterarg */ 1235 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1236 0, /* nsegments */ 1237 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1238 0, /* flags */ 1239 NULL, NULL, /* lockfunc, lockarg */ 1240 &sc->ale_cdata.ale_buffer_tag); 1241 if (error != 0) { 1242 device_printf(sc->ale_dev, 1243 "could not create parent buffer DMA tag.\n"); 1244 goto fail; 1245 } 1246 1247 /* Create DMA tag for Tx buffers. */ 1248 error = bus_dma_tag_create( 1249 sc->ale_cdata.ale_buffer_tag, /* parent */ 1250 1, 0, /* alignment, boundary */ 1251 BUS_SPACE_MAXADDR, /* lowaddr */ 1252 BUS_SPACE_MAXADDR, /* highaddr */ 1253 NULL, NULL, /* filter, filterarg */ 1254 ALE_TSO_MAXSIZE, /* maxsize */ 1255 ALE_MAXTXSEGS, /* nsegments */ 1256 ALE_TSO_MAXSEGSIZE, /* maxsegsize */ 1257 0, /* flags */ 1258 NULL, NULL, /* lockfunc, lockarg */ 1259 &sc->ale_cdata.ale_tx_tag); 1260 if (error != 0) { 1261 device_printf(sc->ale_dev, "could not create Tx DMA tag.\n"); 1262 goto fail; 1263 } 1264 1265 /* Create DMA maps for Tx buffers. */ 1266 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1267 txd = &sc->ale_cdata.ale_txdesc[i]; 1268 txd->tx_m = NULL; 1269 txd->tx_dmamap = NULL; 1270 error = bus_dmamap_create(sc->ale_cdata.ale_tx_tag, 0, 1271 &txd->tx_dmamap); 1272 if (error != 0) { 1273 device_printf(sc->ale_dev, 1274 "could not create Tx dmamap.\n"); 1275 goto fail; 1276 } 1277 } 1278 1279 fail: 1280 return (error); 1281 } 1282 1283 static void 1284 ale_dma_free(struct ale_softc *sc) 1285 { 1286 struct ale_txdesc *txd; 1287 int i; 1288 1289 /* Tx buffers. */ 1290 if (sc->ale_cdata.ale_tx_tag != NULL) { 1291 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1292 txd = &sc->ale_cdata.ale_txdesc[i]; 1293 if (txd->tx_dmamap != NULL) { 1294 bus_dmamap_destroy(sc->ale_cdata.ale_tx_tag, 1295 txd->tx_dmamap); 1296 txd->tx_dmamap = NULL; 1297 } 1298 } 1299 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_tag); 1300 sc->ale_cdata.ale_tx_tag = NULL; 1301 } 1302 /* Tx descriptor ring. */ 1303 if (sc->ale_cdata.ale_tx_ring_tag != NULL) { 1304 if (sc->ale_cdata.ale_tx_ring_paddr != 0) 1305 bus_dmamap_unload(sc->ale_cdata.ale_tx_ring_tag, 1306 sc->ale_cdata.ale_tx_ring_map); 1307 if (sc->ale_cdata.ale_tx_ring != NULL) 1308 bus_dmamem_free(sc->ale_cdata.ale_tx_ring_tag, 1309 sc->ale_cdata.ale_tx_ring, 1310 sc->ale_cdata.ale_tx_ring_map); 1311 sc->ale_cdata.ale_tx_ring_paddr = 0; 1312 sc->ale_cdata.ale_tx_ring = NULL; 1313 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_ring_tag); 1314 sc->ale_cdata.ale_tx_ring_tag = NULL; 1315 } 1316 /* Rx page block. */ 1317 for (i = 0; i < ALE_RX_PAGES; i++) { 1318 if (sc->ale_cdata.ale_rx_page[i].page_tag != NULL) { 1319 if (sc->ale_cdata.ale_rx_page[i].page_paddr != 0) 1320 bus_dmamap_unload( 1321 sc->ale_cdata.ale_rx_page[i].page_tag, 1322 sc->ale_cdata.ale_rx_page[i].page_map); 1323 if (sc->ale_cdata.ale_rx_page[i].page_addr != NULL) 1324 bus_dmamem_free( 1325 sc->ale_cdata.ale_rx_page[i].page_tag, 1326 sc->ale_cdata.ale_rx_page[i].page_addr, 1327 sc->ale_cdata.ale_rx_page[i].page_map); 1328 sc->ale_cdata.ale_rx_page[i].page_paddr = 0; 1329 sc->ale_cdata.ale_rx_page[i].page_addr = NULL; 1330 bus_dma_tag_destroy( 1331 sc->ale_cdata.ale_rx_page[i].page_tag); 1332 sc->ale_cdata.ale_rx_page[i].page_tag = NULL; 1333 } 1334 } 1335 /* Rx CMB. */ 1336 for (i = 0; i < ALE_RX_PAGES; i++) { 1337 if (sc->ale_cdata.ale_rx_page[i].cmb_tag != NULL) { 1338 if (sc->ale_cdata.ale_rx_page[i].cmb_paddr != 0) 1339 bus_dmamap_unload( 1340 sc->ale_cdata.ale_rx_page[i].cmb_tag, 1341 sc->ale_cdata.ale_rx_page[i].cmb_map); 1342 if (sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) 1343 bus_dmamem_free( 1344 sc->ale_cdata.ale_rx_page[i].cmb_tag, 1345 sc->ale_cdata.ale_rx_page[i].cmb_addr, 1346 sc->ale_cdata.ale_rx_page[i].cmb_map); 1347 sc->ale_cdata.ale_rx_page[i].cmb_paddr = 0; 1348 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; 1349 bus_dma_tag_destroy( 1350 sc->ale_cdata.ale_rx_page[i].cmb_tag); 1351 sc->ale_cdata.ale_rx_page[i].cmb_tag = NULL; 1352 } 1353 } 1354 /* Tx CMB. */ 1355 if (sc->ale_cdata.ale_tx_cmb_tag != NULL) { 1356 if (sc->ale_cdata.ale_tx_cmb_paddr != 0) 1357 bus_dmamap_unload(sc->ale_cdata.ale_tx_cmb_tag, 1358 sc->ale_cdata.ale_tx_cmb_map); 1359 if (sc->ale_cdata.ale_tx_cmb != NULL) 1360 bus_dmamem_free(sc->ale_cdata.ale_tx_cmb_tag, 1361 sc->ale_cdata.ale_tx_cmb, 1362 sc->ale_cdata.ale_tx_cmb_map); 1363 sc->ale_cdata.ale_tx_cmb_paddr = 0; 1364 sc->ale_cdata.ale_tx_cmb = NULL; 1365 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_cmb_tag); 1366 sc->ale_cdata.ale_tx_cmb_tag = NULL; 1367 } 1368 if (sc->ale_cdata.ale_buffer_tag != NULL) { 1369 bus_dma_tag_destroy(sc->ale_cdata.ale_buffer_tag); 1370 sc->ale_cdata.ale_buffer_tag = NULL; 1371 } 1372 if (sc->ale_cdata.ale_parent_tag != NULL) { 1373 bus_dma_tag_destroy(sc->ale_cdata.ale_parent_tag); 1374 sc->ale_cdata.ale_parent_tag = NULL; 1375 } 1376 } 1377 1378 static int 1379 ale_shutdown(device_t dev) 1380 { 1381 1382 return (ale_suspend(dev)); 1383 } 1384 1385 /* 1386 * Note, this driver resets the link speed to 10/100Mbps by 1387 * restarting auto-negotiation in suspend/shutdown phase but we 1388 * don't know whether that auto-negotiation would succeed or not 1389 * as driver has no control after powering off/suspend operation. 1390 * If the renegotiation fail WOL may not work. Running at 1Gbps 1391 * will draw more power than 375mA at 3.3V which is specified in 1392 * PCI specification and that would result in complete 1393 * shutdowning power to ethernet controller. 1394 * 1395 * TODO 1396 * Save current negotiated media speed/duplex/flow-control to 1397 * softc and restore the same link again after resuming. PHY 1398 * handling such as power down/resetting to 100Mbps may be better 1399 * handled in suspend method in phy driver. 1400 */ 1401 static void 1402 ale_setlinkspeed(struct ale_softc *sc) 1403 { 1404 struct mii_data *mii; 1405 int aneg, i; 1406 1407 mii = device_get_softc(sc->ale_miibus); 1408 mii_pollstat(mii); 1409 aneg = 0; 1410 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1411 (IFM_ACTIVE | IFM_AVALID)) { 1412 switch IFM_SUBTYPE(mii->mii_media_active) { 1413 case IFM_10_T: 1414 case IFM_100_TX: 1415 return; 1416 case IFM_1000_T: 1417 aneg++; 1418 break; 1419 default: 1420 break; 1421 } 1422 } 1423 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_100T2CR, 0); 1424 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1425 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1426 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1427 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1428 DELAY(1000); 1429 if (aneg != 0) { 1430 /* 1431 * Poll link state until ale(4) get a 10/100Mbps link. 1432 */ 1433 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1434 mii_pollstat(mii); 1435 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 1436 == (IFM_ACTIVE | IFM_AVALID)) { 1437 switch (IFM_SUBTYPE( 1438 mii->mii_media_active)) { 1439 case IFM_10_T: 1440 case IFM_100_TX: 1441 ale_mac_config(sc); 1442 return; 1443 default: 1444 break; 1445 } 1446 } 1447 ALE_UNLOCK(sc); 1448 pause("alelnk", hz); 1449 ALE_LOCK(sc); 1450 } 1451 if (i == MII_ANEGTICKS_GIGE) 1452 device_printf(sc->ale_dev, 1453 "establishing a link failed, WOL may not work!"); 1454 } 1455 /* 1456 * No link, force MAC to have 100Mbps, full-duplex link. 1457 * This is the last resort and may/may not work. 1458 */ 1459 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1460 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1461 ale_mac_config(sc); 1462 } 1463 1464 static void 1465 ale_setwol(struct ale_softc *sc) 1466 { 1467 if_t ifp; 1468 uint32_t reg, pmcs; 1469 1470 ALE_LOCK_ASSERT(sc); 1471 1472 if (!pci_has_pm(sc->ale_dev)) { 1473 /* Disable WOL. */ 1474 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 1475 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1476 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1477 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1478 /* Force PHY power down. */ 1479 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1480 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1481 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_PHY_PLL_ON | 1482 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_IDDQ | 1483 GPHY_CTRL_PCLK_SEL_DIS | GPHY_CTRL_PWDOWN_HW); 1484 return; 1485 } 1486 1487 ifp = sc->ale_ifp; 1488 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { 1489 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 1490 ale_setlinkspeed(sc); 1491 } 1492 1493 pmcs = 0; 1494 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 1495 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1496 CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs); 1497 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1498 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 1499 MAC_CFG_BCAST); 1500 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0) 1501 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1502 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 1503 reg |= MAC_CFG_RX_ENB; 1504 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1505 1506 if ((if_getcapenable(ifp) & IFCAP_WOL) == 0) { 1507 /* WOL disabled, PHY power down. */ 1508 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1509 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1510 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1511 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1512 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1513 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 1514 GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PCLK_SEL_DIS | 1515 GPHY_CTRL_PWDOWN_HW); 1516 } 1517 /* Request PME. */ 1518 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 1519 pci_enable_pme(sc->ale_dev); 1520 } 1521 1522 static int 1523 ale_suspend(device_t dev) 1524 { 1525 struct ale_softc *sc; 1526 1527 sc = device_get_softc(dev); 1528 1529 ALE_LOCK(sc); 1530 ale_stop(sc); 1531 ale_setwol(sc); 1532 ALE_UNLOCK(sc); 1533 1534 return (0); 1535 } 1536 1537 static int 1538 ale_resume(device_t dev) 1539 { 1540 struct ale_softc *sc; 1541 if_t ifp; 1542 1543 sc = device_get_softc(dev); 1544 1545 /* Reset PHY. */ 1546 ALE_LOCK(sc); 1547 ale_phy_reset(sc); 1548 ifp = sc->ale_ifp; 1549 if ((if_getflags(ifp) & IFF_UP) != 0) { 1550 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1551 ale_init_locked(sc); 1552 } 1553 ALE_UNLOCK(sc); 1554 1555 return (0); 1556 } 1557 1558 static int 1559 ale_encap(struct ale_softc *sc, struct mbuf **m_head) 1560 { 1561 struct ale_txdesc *txd, *txd_last; 1562 struct tx_desc *desc; 1563 struct mbuf *m; 1564 struct ip *ip; 1565 struct tcphdr *tcp; 1566 bus_dma_segment_t txsegs[ALE_MAXTXSEGS]; 1567 bus_dmamap_t map; 1568 uint32_t cflags, hdrlen, ip_off, poff, vtag; 1569 int error, i, nsegs, prod, si; 1570 1571 ALE_LOCK_ASSERT(sc); 1572 1573 M_ASSERTPKTHDR((*m_head)); 1574 1575 m = *m_head; 1576 ip = NULL; 1577 tcp = NULL; 1578 cflags = vtag = 0; 1579 ip_off = poff = 0; 1580 if ((m->m_pkthdr.csum_flags & (ALE_CSUM_FEATURES | CSUM_TSO)) != 0) { 1581 /* 1582 * AR81xx requires offset of TCP/UDP payload in its Tx 1583 * descriptor to perform hardware Tx checksum offload. 1584 * Additionally, TSO requires IP/TCP header size and 1585 * modification of IP/TCP header in order to make TSO 1586 * engine work. This kind of operation takes many CPU 1587 * cycles on FreeBSD so fast host CPU is required to 1588 * get smooth TSO performance. 1589 */ 1590 struct ether_header *eh; 1591 1592 if (M_WRITABLE(m) == 0) { 1593 /* Get a writable copy. */ 1594 m = m_dup(*m_head, M_NOWAIT); 1595 /* Release original mbufs. */ 1596 m_freem(*m_head); 1597 if (m == NULL) { 1598 *m_head = NULL; 1599 return (ENOBUFS); 1600 } 1601 *m_head = m; 1602 } 1603 1604 /* 1605 * Buggy-controller requires 4 byte aligned Tx buffer 1606 * to make custom checksum offload work. 1607 */ 1608 if ((sc->ale_flags & ALE_FLAG_TXCSUM_BUG) != 0 && 1609 (m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0 && 1610 (mtod(m, intptr_t) & 3) != 0) { 1611 m = m_defrag(*m_head, M_NOWAIT); 1612 if (m == NULL) { 1613 m_freem(*m_head); 1614 *m_head = NULL; 1615 return (ENOBUFS); 1616 } 1617 *m_head = m; 1618 } 1619 1620 ip_off = sizeof(struct ether_header); 1621 m = m_pullup(m, ip_off); 1622 if (m == NULL) { 1623 *m_head = NULL; 1624 return (ENOBUFS); 1625 } 1626 eh = mtod(m, struct ether_header *); 1627 /* 1628 * Check if hardware VLAN insertion is off. 1629 * Additional check for LLC/SNAP frame? 1630 */ 1631 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1632 ip_off = sizeof(struct ether_vlan_header); 1633 m = m_pullup(m, ip_off); 1634 if (m == NULL) { 1635 *m_head = NULL; 1636 return (ENOBUFS); 1637 } 1638 } 1639 m = m_pullup(m, ip_off + sizeof(struct ip)); 1640 if (m == NULL) { 1641 *m_head = NULL; 1642 return (ENOBUFS); 1643 } 1644 ip = (struct ip *)(mtod(m, char *) + ip_off); 1645 poff = ip_off + (ip->ip_hl << 2); 1646 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1647 /* 1648 * XXX 1649 * AR81xx requires the first descriptor should 1650 * not include any TCP playload for TSO case. 1651 * (i.e. ethernet header + IP + TCP header only) 1652 * m_pullup(9) above will ensure this too. 1653 * However it's not correct if the first mbuf 1654 * of the chain does not use cluster. 1655 */ 1656 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1657 if (m == NULL) { 1658 *m_head = NULL; 1659 return (ENOBUFS); 1660 } 1661 ip = (struct ip *)(mtod(m, char *) + ip_off); 1662 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1663 m = m_pullup(m, poff + (tcp->th_off << 2)); 1664 if (m == NULL) { 1665 *m_head = NULL; 1666 return (ENOBUFS); 1667 } 1668 /* 1669 * AR81xx requires IP/TCP header size and offset as 1670 * well as TCP pseudo checksum which complicates 1671 * TSO configuration. I guess this comes from the 1672 * adherence to Microsoft NDIS Large Send 1673 * specification which requires insertion of 1674 * pseudo checksum by upper stack. The pseudo 1675 * checksum that NDIS refers to doesn't include 1676 * TCP payload length so ale(4) should recompute 1677 * the pseudo checksum here. Hopefully this wouldn't 1678 * be much burden on modern CPUs. 1679 * Reset IP checksum and recompute TCP pseudo 1680 * checksum as NDIS specification said. 1681 */ 1682 ip->ip_sum = 0; 1683 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1684 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1685 } 1686 *m_head = m; 1687 } 1688 1689 si = prod = sc->ale_cdata.ale_tx_prod; 1690 txd = &sc->ale_cdata.ale_txdesc[prod]; 1691 txd_last = txd; 1692 map = txd->tx_dmamap; 1693 1694 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1695 *m_head, txsegs, &nsegs, 0); 1696 if (error == EFBIG) { 1697 m = m_collapse(*m_head, M_NOWAIT, ALE_MAXTXSEGS); 1698 if (m == NULL) { 1699 m_freem(*m_head); 1700 *m_head = NULL; 1701 return (ENOMEM); 1702 } 1703 *m_head = m; 1704 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1705 *m_head, txsegs, &nsegs, 0); 1706 if (error != 0) { 1707 m_freem(*m_head); 1708 *m_head = NULL; 1709 return (error); 1710 } 1711 } else if (error != 0) 1712 return (error); 1713 if (nsegs == 0) { 1714 m_freem(*m_head); 1715 *m_head = NULL; 1716 return (EIO); 1717 } 1718 1719 /* Check descriptor overrun. */ 1720 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 3) { 1721 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, map); 1722 return (ENOBUFS); 1723 } 1724 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, map, BUS_DMASYNC_PREWRITE); 1725 1726 m = *m_head; 1727 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1728 /* Request TSO and set MSS. */ 1729 cflags |= ALE_TD_TSO; 1730 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << ALE_TD_MSS_SHIFT); 1731 /* Set IP/TCP header size. */ 1732 cflags |= ip->ip_hl << ALE_TD_IPHDR_LEN_SHIFT; 1733 cflags |= tcp->th_off << ALE_TD_TCPHDR_LEN_SHIFT; 1734 } else if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { 1735 /* 1736 * AR81xx supports Tx custom checksum offload feature 1737 * that offloads single 16bit checksum computation. 1738 * So you can choose one among IP, TCP and UDP. 1739 * Normally driver sets checksum start/insertion 1740 * position from the information of TCP/UDP frame as 1741 * TCP/UDP checksum takes more time than that of IP. 1742 * However it seems that custom checksum offload 1743 * requires 4 bytes aligned Tx buffers due to hardware 1744 * bug. 1745 * AR81xx also supports explicit Tx checksum computation 1746 * if it is told that the size of IP header and TCP 1747 * header(for UDP, the header size does not matter 1748 * because it's fixed length). However with this scheme 1749 * TSO does not work so you have to choose one either 1750 * TSO or explicit Tx checksum offload. I chosen TSO 1751 * plus custom checksum offload with work-around which 1752 * will cover most common usage for this consumer 1753 * ethernet controller. The work-around takes a lot of 1754 * CPU cycles if Tx buffer is not aligned on 4 bytes 1755 * boundary, though. 1756 */ 1757 cflags |= ALE_TD_CXSUM; 1758 /* Set checksum start offset. */ 1759 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); 1760 /* Set checksum insertion position of TCP/UDP. */ 1761 cflags |= ((poff + m->m_pkthdr.csum_data) << 1762 ALE_TD_CSUM_XSUMOFFSET_SHIFT); 1763 } 1764 1765 /* Configure VLAN hardware tag insertion. */ 1766 if ((m->m_flags & M_VLANTAG) != 0) { 1767 vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1768 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); 1769 cflags |= ALE_TD_INSERT_VLAN_TAG; 1770 } 1771 1772 i = 0; 1773 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1774 /* 1775 * Make sure the first fragment contains 1776 * only ethernet and IP/TCP header with options. 1777 */ 1778 hdrlen = poff + (tcp->th_off << 2); 1779 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1780 desc->addr = htole64(txsegs[i].ds_addr); 1781 desc->len = htole32(ALE_TX_BYTES(hdrlen) | vtag); 1782 desc->flags = htole32(cflags); 1783 sc->ale_cdata.ale_tx_cnt++; 1784 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1785 if (m->m_len - hdrlen > 0) { 1786 /* Handle remaining payload of the first fragment. */ 1787 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1788 desc->addr = htole64(txsegs[i].ds_addr + hdrlen); 1789 desc->len = htole32(ALE_TX_BYTES(m->m_len - hdrlen) | 1790 vtag); 1791 desc->flags = htole32(cflags); 1792 sc->ale_cdata.ale_tx_cnt++; 1793 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1794 } 1795 i = 1; 1796 } 1797 for (; i < nsegs; i++) { 1798 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1799 desc->addr = htole64(txsegs[i].ds_addr); 1800 desc->len = htole32(ALE_TX_BYTES(txsegs[i].ds_len) | vtag); 1801 desc->flags = htole32(cflags); 1802 sc->ale_cdata.ale_tx_cnt++; 1803 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1804 } 1805 /* Update producer index. */ 1806 sc->ale_cdata.ale_tx_prod = prod; 1807 /* Set TSO header on the first descriptor. */ 1808 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1809 desc = &sc->ale_cdata.ale_tx_ring[si]; 1810 desc->flags |= htole32(ALE_TD_TSO_HDR); 1811 } 1812 1813 /* Finally set EOP on the last descriptor. */ 1814 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; 1815 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1816 desc->flags |= htole32(ALE_TD_EOP); 1817 1818 /* Swap dmamap of the first and the last. */ 1819 txd = &sc->ale_cdata.ale_txdesc[prod]; 1820 map = txd_last->tx_dmamap; 1821 txd_last->tx_dmamap = txd->tx_dmamap; 1822 txd->tx_dmamap = map; 1823 txd->tx_m = m; 1824 1825 /* Sync descriptors. */ 1826 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 1827 sc->ale_cdata.ale_tx_ring_map, 1828 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1829 1830 return (0); 1831 } 1832 1833 static void 1834 ale_start(if_t ifp) 1835 { 1836 struct ale_softc *sc; 1837 1838 sc = if_getsoftc(ifp); 1839 ALE_LOCK(sc); 1840 ale_start_locked(ifp); 1841 ALE_UNLOCK(sc); 1842 } 1843 1844 static void 1845 ale_start_locked(if_t ifp) 1846 { 1847 struct ale_softc *sc; 1848 struct mbuf *m_head; 1849 int enq; 1850 1851 sc = if_getsoftc(ifp); 1852 1853 ALE_LOCK_ASSERT(sc); 1854 1855 /* Reclaim transmitted frames. */ 1856 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) 1857 ale_txeof(sc); 1858 1859 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1860 IFF_DRV_RUNNING || (sc->ale_flags & ALE_FLAG_LINK) == 0) 1861 return; 1862 1863 for (enq = 0; !if_sendq_empty(ifp); ) { 1864 m_head = if_dequeue(ifp); 1865 if (m_head == NULL) 1866 break; 1867 /* 1868 * Pack the data into the transmit ring. If we 1869 * don't have room, set the OACTIVE flag and wait 1870 * for the NIC to drain the ring. 1871 */ 1872 if (ale_encap(sc, &m_head)) { 1873 if (m_head == NULL) 1874 break; 1875 if_sendq_prepend(ifp, m_head); 1876 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1877 break; 1878 } 1879 1880 enq++; 1881 /* 1882 * If there's a BPF listener, bounce a copy of this frame 1883 * to him. 1884 */ 1885 ETHER_BPF_MTAP(ifp, m_head); 1886 } 1887 1888 if (enq > 0) { 1889 /* Kick. */ 1890 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, 1891 sc->ale_cdata.ale_tx_prod); 1892 /* Set a timeout in case the chip goes out to lunch. */ 1893 sc->ale_watchdog_timer = ALE_TX_TIMEOUT; 1894 } 1895 } 1896 1897 static void 1898 ale_watchdog(struct ale_softc *sc) 1899 { 1900 if_t ifp; 1901 1902 ALE_LOCK_ASSERT(sc); 1903 1904 if (sc->ale_watchdog_timer == 0 || --sc->ale_watchdog_timer) 1905 return; 1906 1907 ifp = sc->ale_ifp; 1908 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1909 if_printf(sc->ale_ifp, "watchdog timeout (lost link)\n"); 1910 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1911 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1912 ale_init_locked(sc); 1913 return; 1914 } 1915 if_printf(sc->ale_ifp, "watchdog timeout -- resetting\n"); 1916 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1917 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1918 ale_init_locked(sc); 1919 if (!if_sendq_empty(ifp)) 1920 ale_start_locked(ifp); 1921 } 1922 1923 static int 1924 ale_ioctl(if_t ifp, u_long cmd, caddr_t data) 1925 { 1926 struct ale_softc *sc; 1927 struct ifreq *ifr; 1928 struct mii_data *mii; 1929 int error, mask; 1930 1931 sc = if_getsoftc(ifp); 1932 ifr = (struct ifreq *)data; 1933 error = 0; 1934 switch (cmd) { 1935 case SIOCSIFMTU: 1936 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALE_JUMBO_MTU || 1937 ((sc->ale_flags & ALE_FLAG_JUMBO) == 0 && 1938 ifr->ifr_mtu > ETHERMTU)) 1939 error = EINVAL; 1940 else if (if_getmtu(ifp) != ifr->ifr_mtu) { 1941 ALE_LOCK(sc); 1942 if_setmtu(ifp, ifr->ifr_mtu); 1943 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1944 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1945 ale_init_locked(sc); 1946 } 1947 ALE_UNLOCK(sc); 1948 } 1949 break; 1950 case SIOCSIFFLAGS: 1951 ALE_LOCK(sc); 1952 if ((if_getflags(ifp) & IFF_UP) != 0) { 1953 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1954 if (((if_getflags(ifp) ^ sc->ale_if_flags) 1955 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1956 ale_rxfilter(sc); 1957 } else { 1958 ale_init_locked(sc); 1959 } 1960 } else { 1961 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1962 ale_stop(sc); 1963 } 1964 sc->ale_if_flags = if_getflags(ifp); 1965 ALE_UNLOCK(sc); 1966 break; 1967 case SIOCADDMULTI: 1968 case SIOCDELMULTI: 1969 ALE_LOCK(sc); 1970 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1971 ale_rxfilter(sc); 1972 ALE_UNLOCK(sc); 1973 break; 1974 case SIOCSIFMEDIA: 1975 case SIOCGIFMEDIA: 1976 mii = device_get_softc(sc->ale_miibus); 1977 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1978 break; 1979 case SIOCSIFCAP: 1980 ALE_LOCK(sc); 1981 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 1982 if ((mask & IFCAP_TXCSUM) != 0 && 1983 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 1984 if_togglecapenable(ifp, IFCAP_TXCSUM); 1985 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 1986 if_sethwassistbits(ifp, ALE_CSUM_FEATURES, 0); 1987 else 1988 if_sethwassistbits(ifp, 0, ALE_CSUM_FEATURES); 1989 } 1990 if ((mask & IFCAP_RXCSUM) != 0 && 1991 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) 1992 if_togglecapenable(ifp, IFCAP_RXCSUM); 1993 if ((mask & IFCAP_TSO4) != 0 && 1994 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) { 1995 if_togglecapenable(ifp, IFCAP_TSO4); 1996 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0) 1997 if_sethwassistbits(ifp, CSUM_TSO, 0); 1998 else 1999 if_sethwassistbits(ifp, 0, CSUM_TSO); 2000 } 2001 2002 if ((mask & IFCAP_WOL_MCAST) != 0 && 2003 (if_getcapabilities(ifp) & IFCAP_WOL_MCAST) != 0) 2004 if_togglecapenable(ifp, IFCAP_WOL_MCAST); 2005 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2006 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0) 2007 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 2008 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2009 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0) 2010 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 2011 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2012 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) 2013 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 2014 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2015 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 2016 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 2017 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) 2018 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO); 2019 ale_rxvlan(sc); 2020 } 2021 ALE_UNLOCK(sc); 2022 VLAN_CAPABILITIES(ifp); 2023 break; 2024 default: 2025 error = ether_ioctl(ifp, cmd, data); 2026 break; 2027 } 2028 2029 return (error); 2030 } 2031 2032 static void 2033 ale_mac_config(struct ale_softc *sc) 2034 { 2035 struct mii_data *mii; 2036 uint32_t reg; 2037 2038 ALE_LOCK_ASSERT(sc); 2039 2040 mii = device_get_softc(sc->ale_miibus); 2041 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2042 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2043 MAC_CFG_SPEED_MASK); 2044 /* Reprogram MAC with resolved speed/duplex. */ 2045 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2046 case IFM_10_T: 2047 case IFM_100_TX: 2048 reg |= MAC_CFG_SPEED_10_100; 2049 break; 2050 case IFM_1000_T: 2051 reg |= MAC_CFG_SPEED_1000; 2052 break; 2053 } 2054 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2055 reg |= MAC_CFG_FULL_DUPLEX; 2056 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2057 reg |= MAC_CFG_TX_FC; 2058 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2059 reg |= MAC_CFG_RX_FC; 2060 } 2061 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2062 } 2063 2064 static void 2065 ale_stats_clear(struct ale_softc *sc) 2066 { 2067 struct smb sb; 2068 uint32_t *reg; 2069 int i; 2070 2071 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2072 CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2073 i += sizeof(uint32_t); 2074 } 2075 /* Read Tx statistics. */ 2076 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2077 CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2078 i += sizeof(uint32_t); 2079 } 2080 } 2081 2082 static void 2083 ale_stats_update(struct ale_softc *sc) 2084 { 2085 struct ale_hw_stats *stat; 2086 struct smb sb, *smb; 2087 if_t ifp; 2088 uint32_t *reg; 2089 int i; 2090 2091 ALE_LOCK_ASSERT(sc); 2092 2093 ifp = sc->ale_ifp; 2094 stat = &sc->ale_stats; 2095 smb = &sb; 2096 2097 /* Read Rx statistics. */ 2098 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2099 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2100 i += sizeof(uint32_t); 2101 } 2102 /* Read Tx statistics. */ 2103 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2104 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2105 i += sizeof(uint32_t); 2106 } 2107 2108 /* Rx stats. */ 2109 stat->rx_frames += smb->rx_frames; 2110 stat->rx_bcast_frames += smb->rx_bcast_frames; 2111 stat->rx_mcast_frames += smb->rx_mcast_frames; 2112 stat->rx_pause_frames += smb->rx_pause_frames; 2113 stat->rx_control_frames += smb->rx_control_frames; 2114 stat->rx_crcerrs += smb->rx_crcerrs; 2115 stat->rx_lenerrs += smb->rx_lenerrs; 2116 stat->rx_bytes += smb->rx_bytes; 2117 stat->rx_runts += smb->rx_runts; 2118 stat->rx_fragments += smb->rx_fragments; 2119 stat->rx_pkts_64 += smb->rx_pkts_64; 2120 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2121 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2122 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2123 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2124 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2125 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2126 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2127 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2128 stat->rx_rrs_errs += smb->rx_rrs_errs; 2129 stat->rx_alignerrs += smb->rx_alignerrs; 2130 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2131 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2132 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2133 2134 /* Tx stats. */ 2135 stat->tx_frames += smb->tx_frames; 2136 stat->tx_bcast_frames += smb->tx_bcast_frames; 2137 stat->tx_mcast_frames += smb->tx_mcast_frames; 2138 stat->tx_pause_frames += smb->tx_pause_frames; 2139 stat->tx_excess_defer += smb->tx_excess_defer; 2140 stat->tx_control_frames += smb->tx_control_frames; 2141 stat->tx_deferred += smb->tx_deferred; 2142 stat->tx_bytes += smb->tx_bytes; 2143 stat->tx_pkts_64 += smb->tx_pkts_64; 2144 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2145 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2146 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2147 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2148 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2149 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2150 stat->tx_single_colls += smb->tx_single_colls; 2151 stat->tx_multi_colls += smb->tx_multi_colls; 2152 stat->tx_late_colls += smb->tx_late_colls; 2153 stat->tx_excess_colls += smb->tx_excess_colls; 2154 stat->tx_underrun += smb->tx_underrun; 2155 stat->tx_desc_underrun += smb->tx_desc_underrun; 2156 stat->tx_lenerrs += smb->tx_lenerrs; 2157 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2158 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2159 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2160 2161 /* Update counters in ifnet. */ 2162 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames); 2163 2164 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls + 2165 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2166 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT); 2167 2168 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_late_colls + 2169 smb->tx_excess_colls + smb->tx_underrun + smb->tx_pkts_truncated); 2170 2171 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames); 2172 2173 if_inc_counter(ifp, IFCOUNTER_IERRORS, 2174 smb->rx_crcerrs + smb->rx_lenerrs + 2175 smb->rx_runts + smb->rx_pkts_truncated + 2176 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2177 smb->rx_alignerrs); 2178 } 2179 2180 static int 2181 ale_intr(void *arg) 2182 { 2183 struct ale_softc *sc; 2184 uint32_t status; 2185 2186 sc = (struct ale_softc *)arg; 2187 2188 status = CSR_READ_4(sc, ALE_INTR_STATUS); 2189 if ((status & ALE_INTRS) == 0) 2190 return (FILTER_STRAY); 2191 /* Disable interrupts. */ 2192 CSR_WRITE_4(sc, ALE_INTR_STATUS, INTR_DIS_INT); 2193 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2194 2195 return (FILTER_HANDLED); 2196 } 2197 2198 static void 2199 ale_int_task(void *arg, int pending) 2200 { 2201 struct ale_softc *sc; 2202 if_t ifp; 2203 uint32_t status; 2204 int more; 2205 2206 sc = (struct ale_softc *)arg; 2207 2208 status = CSR_READ_4(sc, ALE_INTR_STATUS); 2209 ALE_LOCK(sc); 2210 if (sc->ale_morework != 0) 2211 status |= INTR_RX_PKT; 2212 if ((status & ALE_INTRS) == 0) 2213 goto done; 2214 2215 /* Acknowledge interrupts but still disable interrupts. */ 2216 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); 2217 2218 ifp = sc->ale_ifp; 2219 more = 0; 2220 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2221 more = ale_rxeof(sc, sc->ale_process_limit); 2222 if (more == EAGAIN) 2223 sc->ale_morework = 1; 2224 else if (more == EIO) { 2225 sc->ale_stats.reset_brk_seq++; 2226 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2227 ale_init_locked(sc); 2228 ALE_UNLOCK(sc); 2229 return; 2230 } 2231 2232 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 2233 if ((status & INTR_DMA_RD_TO_RST) != 0) 2234 device_printf(sc->ale_dev, 2235 "DMA read error! -- resetting\n"); 2236 if ((status & INTR_DMA_WR_TO_RST) != 0) 2237 device_printf(sc->ale_dev, 2238 "DMA write error! -- resetting\n"); 2239 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2240 ale_init_locked(sc); 2241 ALE_UNLOCK(sc); 2242 return; 2243 } 2244 if (!if_sendq_empty(ifp)) 2245 ale_start_locked(ifp); 2246 } 2247 2248 if (more == EAGAIN || 2249 (CSR_READ_4(sc, ALE_INTR_STATUS) & ALE_INTRS) != 0) { 2250 ALE_UNLOCK(sc); 2251 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2252 return; 2253 } 2254 2255 done: 2256 ALE_UNLOCK(sc); 2257 2258 /* Re-enable interrupts. */ 2259 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); 2260 } 2261 2262 static void 2263 ale_txeof(struct ale_softc *sc) 2264 { 2265 if_t ifp; 2266 struct ale_txdesc *txd; 2267 uint32_t cons, prod; 2268 int prog; 2269 2270 ALE_LOCK_ASSERT(sc); 2271 2272 ifp = sc->ale_ifp; 2273 2274 if (sc->ale_cdata.ale_tx_cnt == 0) 2275 return; 2276 2277 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2278 sc->ale_cdata.ale_tx_ring_map, 2279 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2280 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { 2281 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2282 sc->ale_cdata.ale_tx_cmb_map, 2283 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2284 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; 2285 } else 2286 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); 2287 cons = sc->ale_cdata.ale_tx_cons; 2288 /* 2289 * Go through our Tx list and free mbufs for those 2290 * frames which have been transmitted. 2291 */ 2292 for (prog = 0; cons != prod; prog++, 2293 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { 2294 if (sc->ale_cdata.ale_tx_cnt <= 0) 2295 break; 2296 prog++; 2297 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2298 sc->ale_cdata.ale_tx_cnt--; 2299 txd = &sc->ale_cdata.ale_txdesc[cons]; 2300 if (txd->tx_m != NULL) { 2301 /* Reclaim transmitted mbufs. */ 2302 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2303 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2304 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2305 txd->tx_dmamap); 2306 m_freem(txd->tx_m); 2307 txd->tx_m = NULL; 2308 } 2309 } 2310 2311 if (prog > 0) { 2312 sc->ale_cdata.ale_tx_cons = cons; 2313 /* 2314 * Unarm watchdog timer only when there is no pending 2315 * Tx descriptors in queue. 2316 */ 2317 if (sc->ale_cdata.ale_tx_cnt == 0) 2318 sc->ale_watchdog_timer = 0; 2319 } 2320 } 2321 2322 static void 2323 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, 2324 uint32_t length, uint32_t *prod) 2325 { 2326 struct ale_rx_page *rx_page; 2327 2328 rx_page = *page; 2329 /* Update consumer position. */ 2330 rx_page->cons += roundup(length + sizeof(struct rx_rs), 2331 ALE_RX_PAGE_ALIGN); 2332 if (rx_page->cons >= ALE_RX_PAGE_SZ) { 2333 /* 2334 * End of Rx page reached, let hardware reuse 2335 * this page. 2336 */ 2337 rx_page->cons = 0; 2338 *rx_page->cmb_addr = 0; 2339 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2340 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2341 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, 2342 RXF_VALID); 2343 /* Switch to alternate Rx page. */ 2344 sc->ale_cdata.ale_rx_curp ^= 1; 2345 rx_page = *page = 2346 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2347 /* Page flipped, sync CMB and Rx page. */ 2348 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2349 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2350 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2351 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2352 /* Sync completed, cache updated producer index. */ 2353 *prod = *rx_page->cmb_addr; 2354 } 2355 } 2356 2357 /* 2358 * It seems that AR81xx controller can compute partial checksum. 2359 * The partial checksum value can be used to accelerate checksum 2360 * computation for fragmented TCP/UDP packets. Upper network stack 2361 * already takes advantage of the partial checksum value in IP 2362 * reassembly stage. But I'm not sure the correctness of the 2363 * partial hardware checksum assistance due to lack of data sheet. 2364 * In addition, the Rx feature of controller that requires copying 2365 * for every frames effectively nullifies one of most nice offload 2366 * capability of controller. 2367 */ 2368 static void 2369 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) 2370 { 2371 if_t ifp; 2372 struct ip *ip; 2373 char *p; 2374 2375 ifp = sc->ale_ifp; 2376 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2377 if ((status & ALE_RD_IPCSUM_NOK) == 0) 2378 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2379 2380 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { 2381 if (((status & ALE_RD_IPV4_FRAG) == 0) && 2382 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && 2383 ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) { 2384 m->m_pkthdr.csum_flags |= 2385 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2386 m->m_pkthdr.csum_data = 0xffff; 2387 } 2388 } else { 2389 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 && 2390 (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) { 2391 p = mtod(m, char *); 2392 p += ETHER_HDR_LEN; 2393 if ((status & ALE_RD_802_3) != 0) 2394 p += LLC_SNAPFRAMELEN; 2395 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0 && 2396 (status & ALE_RD_VLAN) != 0) 2397 p += ETHER_VLAN_ENCAP_LEN; 2398 ip = (struct ip *)p; 2399 if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0) 2400 return; 2401 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 2402 CSUM_PSEUDO_HDR; 2403 m->m_pkthdr.csum_data = 0xffff; 2404 } 2405 } 2406 /* 2407 * Don't mark bad checksum for TCP/UDP frames 2408 * as fragmented frames may always have set 2409 * bad checksummed bit of frame status. 2410 */ 2411 } 2412 2413 /* Process received frames. */ 2414 static int 2415 ale_rxeof(struct ale_softc *sc, int count) 2416 { 2417 struct ale_rx_page *rx_page; 2418 struct rx_rs *rs; 2419 if_t ifp; 2420 struct mbuf *m; 2421 uint32_t length, prod, seqno, status, vtags; 2422 int prog; 2423 2424 ifp = sc->ale_ifp; 2425 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2426 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2427 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2428 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2429 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2430 /* 2431 * Don't directly access producer index as hardware may 2432 * update it while Rx handler is in progress. It would 2433 * be even better if there is a way to let hardware 2434 * know how far driver processed its received frames. 2435 * Alternatively, hardware could provide a way to disable 2436 * CMB updates until driver acknowledges the end of CMB 2437 * access. 2438 */ 2439 prod = *rx_page->cmb_addr; 2440 for (prog = 0; prog < count; prog++) { 2441 if (rx_page->cons >= prod) 2442 break; 2443 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); 2444 seqno = ALE_RX_SEQNO(le32toh(rs->seqno)); 2445 if (sc->ale_cdata.ale_rx_seqno != seqno) { 2446 /* 2447 * Normally I believe this should not happen unless 2448 * severe driver bug or corrupted memory. However 2449 * it seems to happen under certain conditions which 2450 * is triggered by abrupt Rx events such as initiation 2451 * of bulk transfer of remote host. It's not easy to 2452 * reproduce this and I doubt it could be related 2453 * with FIFO overflow of hardware or activity of Tx 2454 * CMB updates. I also remember similar behaviour 2455 * seen on RealTek 8139 which uses resembling Rx 2456 * scheme. 2457 */ 2458 if (bootverbose) 2459 device_printf(sc->ale_dev, 2460 "garbled seq: %u, expected: %u -- " 2461 "resetting!\n", seqno, 2462 sc->ale_cdata.ale_rx_seqno); 2463 return (EIO); 2464 } 2465 /* Frame received. */ 2466 sc->ale_cdata.ale_rx_seqno++; 2467 length = ALE_RX_BYTES(le32toh(rs->length)); 2468 status = le32toh(rs->flags); 2469 if ((status & ALE_RD_ERROR) != 0) { 2470 /* 2471 * We want to pass the following frames to upper 2472 * layer regardless of error status of Rx return 2473 * status. 2474 * 2475 * o IP/TCP/UDP checksum is bad. 2476 * o frame length and protocol specific length 2477 * does not match. 2478 */ 2479 if ((status & (ALE_RD_CRC | ALE_RD_CODE | 2480 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | 2481 ALE_RD_TRUNC)) != 0) { 2482 ale_rx_update_page(sc, &rx_page, length, &prod); 2483 continue; 2484 } 2485 } 2486 /* 2487 * m_devget(9) is major bottle-neck of ale(4)(It comes 2488 * from hardware limitation). For jumbo frames we could 2489 * get a slightly better performance if driver use 2490 * m_getjcl(9) with proper buffer size argument. However 2491 * that would make code more complicated and I don't 2492 * think users would expect good Rx performance numbers 2493 * on these low-end consumer ethernet controller. 2494 */ 2495 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, 2496 ETHER_ALIGN, ifp, NULL); 2497 if (m == NULL) { 2498 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2499 ale_rx_update_page(sc, &rx_page, length, &prod); 2500 continue; 2501 } 2502 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0 && 2503 (status & ALE_RD_IPV4) != 0) 2504 ale_rxcsum(sc, m, status); 2505 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 && 2506 (status & ALE_RD_VLAN) != 0) { 2507 vtags = ALE_RX_VLAN(le32toh(rs->vtags)); 2508 m->m_pkthdr.ether_vtag = ALE_RX_VLAN_TAG(vtags); 2509 m->m_flags |= M_VLANTAG; 2510 } 2511 2512 /* Pass it to upper layer. */ 2513 ALE_UNLOCK(sc); 2514 if_input(ifp, m); 2515 ALE_LOCK(sc); 2516 2517 ale_rx_update_page(sc, &rx_page, length, &prod); 2518 } 2519 2520 return (count > 0 ? 0 : EAGAIN); 2521 } 2522 2523 static void 2524 ale_tick(void *arg) 2525 { 2526 struct ale_softc *sc; 2527 struct mii_data *mii; 2528 2529 sc = (struct ale_softc *)arg; 2530 2531 ALE_LOCK_ASSERT(sc); 2532 2533 mii = device_get_softc(sc->ale_miibus); 2534 mii_tick(mii); 2535 ale_stats_update(sc); 2536 /* 2537 * Reclaim Tx buffers that have been transferred. It's not 2538 * needed here but it would release allocated mbuf chains 2539 * faster and limit the maximum delay to a hz. 2540 */ 2541 ale_txeof(sc); 2542 ale_watchdog(sc); 2543 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2544 } 2545 2546 static void 2547 ale_reset(struct ale_softc *sc) 2548 { 2549 uint32_t reg; 2550 int i; 2551 2552 /* Initialize PCIe module. From Linux. */ 2553 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2554 2555 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); 2556 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2557 DELAY(10); 2558 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) 2559 break; 2560 } 2561 if (i == 0) 2562 device_printf(sc->ale_dev, "master reset timeout!\n"); 2563 2564 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2565 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) 2566 break; 2567 DELAY(10); 2568 } 2569 2570 if (i == 0) 2571 device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg); 2572 } 2573 2574 static void 2575 ale_init(void *xsc) 2576 { 2577 struct ale_softc *sc; 2578 2579 sc = (struct ale_softc *)xsc; 2580 ALE_LOCK(sc); 2581 ale_init_locked(sc); 2582 ALE_UNLOCK(sc); 2583 } 2584 2585 static void 2586 ale_init_locked(struct ale_softc *sc) 2587 { 2588 if_t ifp; 2589 struct mii_data *mii; 2590 uint8_t eaddr[ETHER_ADDR_LEN]; 2591 bus_addr_t paddr; 2592 uint32_t reg, rxf_hi, rxf_lo; 2593 2594 ALE_LOCK_ASSERT(sc); 2595 2596 ifp = sc->ale_ifp; 2597 mii = device_get_softc(sc->ale_miibus); 2598 2599 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2600 return; 2601 /* 2602 * Cancel any pending I/O. 2603 */ 2604 ale_stop(sc); 2605 /* 2606 * Reset the chip to a known state. 2607 */ 2608 ale_reset(sc); 2609 /* Initialize Tx descriptors, DMA memory blocks. */ 2610 ale_init_rx_pages(sc); 2611 ale_init_tx_ring(sc); 2612 2613 /* Reprogram the station address. */ 2614 bcopy(if_getlladdr(ifp), eaddr, ETHER_ADDR_LEN); 2615 CSR_WRITE_4(sc, ALE_PAR0, 2616 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2617 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); 2618 /* 2619 * Clear WOL status and disable all WOL feature as WOL 2620 * would interfere Rx operation under normal environments. 2621 */ 2622 CSR_READ_4(sc, ALE_WOL_CFG); 2623 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 2624 /* 2625 * Set Tx descriptor/RXF0/CMB base addresses. They share 2626 * the same high address part of DMAable region. 2627 */ 2628 paddr = sc->ale_cdata.ale_tx_ring_paddr; 2629 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); 2630 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); 2631 CSR_WRITE_4(sc, ALE_TPD_CNT, 2632 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); 2633 /* Set Rx page base address, note we use single queue. */ 2634 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; 2635 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); 2636 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; 2637 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); 2638 /* Set Tx/Rx CMB addresses. */ 2639 paddr = sc->ale_cdata.ale_tx_cmb_paddr; 2640 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); 2641 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; 2642 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); 2643 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; 2644 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); 2645 /* Mark RXF0 is valid. */ 2646 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); 2647 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); 2648 /* 2649 * No need to initialize RFX1/RXF2/RXF3. We don't use 2650 * multi-queue yet. 2651 */ 2652 2653 /* Set Rx page size, excluding guard frame size. */ 2654 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); 2655 /* Tell hardware that we're ready to load DMA blocks. */ 2656 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); 2657 2658 /* Set Rx/Tx interrupt trigger threshold. */ 2659 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | 2660 (4 << INT_TRIG_TX_THRESH_SHIFT)); 2661 /* 2662 * XXX 2663 * Set interrupt trigger timer, its purpose and relation 2664 * with interrupt moderation mechanism is not clear yet. 2665 */ 2666 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, 2667 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | 2668 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); 2669 2670 /* Configure interrupt moderation timer. */ 2671 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; 2672 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; 2673 CSR_WRITE_4(sc, ALE_IM_TIMER, reg); 2674 reg = CSR_READ_4(sc, ALE_MASTER_CFG); 2675 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 2676 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 2677 if (ALE_USECS(sc->ale_int_rx_mod) != 0) 2678 reg |= MASTER_IM_RX_TIMER_ENB; 2679 if (ALE_USECS(sc->ale_int_tx_mod) != 0) 2680 reg |= MASTER_IM_TX_TIMER_ENB; 2681 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); 2682 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); 2683 2684 /* Set Maximum frame size of controller. */ 2685 if (if_getmtu(ifp) < ETHERMTU) 2686 sc->ale_max_frame_size = ETHERMTU; 2687 else 2688 sc->ale_max_frame_size = if_getmtu(ifp); 2689 sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 2690 ETHER_CRC_LEN; 2691 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); 2692 /* Configure IPG/IFG parameters. */ 2693 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, 2694 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 2695 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2696 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2697 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 2698 /* Set parameters for half-duplex media. */ 2699 CSR_WRITE_4(sc, ALE_HDPX_CFG, 2700 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2701 HDPX_CFG_LCOL_MASK) | 2702 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2703 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2704 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2705 HDPX_CFG_ABEBT_MASK) | 2706 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2707 HDPX_CFG_JAMIPG_MASK)); 2708 2709 /* Configure Tx jumbo frame parameters. */ 2710 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2711 if (if_getmtu(ifp) < ETHERMTU) 2712 reg = sc->ale_max_frame_size; 2713 else if (if_getmtu(ifp) < 6 * 1024) 2714 reg = (sc->ale_max_frame_size * 2) / 3; 2715 else 2716 reg = sc->ale_max_frame_size / 2; 2717 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, 2718 roundup(reg, TX_JUMBO_THRESH_UNIT) >> 2719 TX_JUMBO_THRESH_UNIT_SHIFT); 2720 } 2721 /* Configure TxQ. */ 2722 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) 2723 << TXQ_CFG_TX_FIFO_BURST_SHIFT; 2724 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2725 TXQ_CFG_TPD_BURST_MASK; 2726 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); 2727 2728 /* Configure Rx jumbo frame & flow control parameters. */ 2729 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2730 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); 2731 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, 2732 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << 2733 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | 2734 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & 2735 RX_JUMBO_LKAH_MASK)); 2736 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 2737 rxf_hi = (reg * 7) / 10; 2738 rxf_lo = (reg * 3)/ 10; 2739 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, 2740 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2741 RX_FIFO_PAUSE_THRESH_LO_MASK) | 2742 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2743 RX_FIFO_PAUSE_THRESH_HI_MASK)); 2744 } 2745 2746 /* Disable RSS. */ 2747 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); 2748 CSR_WRITE_4(sc, ALE_RSS_CPU, 0); 2749 2750 /* Configure RxQ. */ 2751 CSR_WRITE_4(sc, ALE_RXQ_CFG, 2752 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2753 2754 /* Configure DMA parameters. */ 2755 reg = 0; 2756 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) 2757 reg |= DMA_CFG_TXCMB_ENB; 2758 CSR_WRITE_4(sc, ALE_DMA_CFG, 2759 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | 2760 sc->ale_dma_rd_burst | reg | 2761 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | 2762 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 2763 DMA_CFG_RD_DELAY_CNT_MASK) | 2764 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 2765 DMA_CFG_WR_DELAY_CNT_MASK)); 2766 2767 /* 2768 * Hardware can be configured to issue SMB interrupt based 2769 * on programmed interval. Since there is a callout that is 2770 * invoked for every hz in driver we use that instead of 2771 * relying on periodic SMB interrupt. 2772 */ 2773 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); 2774 /* Clear MAC statistics. */ 2775 ale_stats_clear(sc); 2776 2777 /* 2778 * Configure Tx/Rx MACs. 2779 * - Auto-padding for short frames. 2780 * - Enable CRC generation. 2781 * Actual reconfiguration of MAC for resolved speed/duplex 2782 * is followed after detection of link establishment. 2783 * AR81xx always does checksum computation regardless of 2784 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will 2785 * cause Rx handling issue for fragmented IP datagrams due 2786 * to silicon bug. 2787 */ 2788 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 2789 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2790 MAC_CFG_PREAMBLE_MASK); 2791 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) 2792 reg |= MAC_CFG_SPEED_10_100; 2793 else 2794 reg |= MAC_CFG_SPEED_1000; 2795 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2796 2797 /* Set up the receive filter. */ 2798 ale_rxfilter(sc); 2799 ale_rxvlan(sc); 2800 2801 /* Acknowledge all pending interrupts and clear it. */ 2802 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); 2803 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2804 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); 2805 2806 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 2807 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2808 2809 sc->ale_flags &= ~ALE_FLAG_LINK; 2810 /* Switch to the current media. */ 2811 mii_mediachg(mii); 2812 2813 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2814 } 2815 2816 static void 2817 ale_stop(struct ale_softc *sc) 2818 { 2819 if_t ifp; 2820 struct ale_txdesc *txd; 2821 uint32_t reg; 2822 int i; 2823 2824 ALE_LOCK_ASSERT(sc); 2825 /* 2826 * Mark the interface down and cancel the watchdog timer. 2827 */ 2828 ifp = sc->ale_ifp; 2829 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 2830 sc->ale_flags &= ~ALE_FLAG_LINK; 2831 callout_stop(&sc->ale_tick_ch); 2832 sc->ale_watchdog_timer = 0; 2833 ale_stats_update(sc); 2834 /* Disable interrupts. */ 2835 CSR_WRITE_4(sc, ALE_INTR_MASK, 0); 2836 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2837 /* Disable queue processing and DMA. */ 2838 reg = CSR_READ_4(sc, ALE_TXQ_CFG); 2839 reg &= ~TXQ_CFG_ENB; 2840 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); 2841 reg = CSR_READ_4(sc, ALE_RXQ_CFG); 2842 reg &= ~RXQ_CFG_ENB; 2843 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); 2844 reg = CSR_READ_4(sc, ALE_DMA_CFG); 2845 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); 2846 CSR_WRITE_4(sc, ALE_DMA_CFG, reg); 2847 DELAY(1000); 2848 /* Stop Rx/Tx MACs. */ 2849 ale_stop_mac(sc); 2850 /* Disable interrupts which might be touched in taskq handler. */ 2851 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2852 2853 /* 2854 * Free TX mbufs still in the queues. 2855 */ 2856 for (i = 0; i < ALE_TX_RING_CNT; i++) { 2857 txd = &sc->ale_cdata.ale_txdesc[i]; 2858 if (txd->tx_m != NULL) { 2859 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2860 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2861 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2862 txd->tx_dmamap); 2863 m_freem(txd->tx_m); 2864 txd->tx_m = NULL; 2865 } 2866 } 2867 } 2868 2869 static void 2870 ale_stop_mac(struct ale_softc *sc) 2871 { 2872 uint32_t reg; 2873 int i; 2874 2875 ALE_LOCK_ASSERT(sc); 2876 2877 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2878 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 2879 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 2880 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2881 } 2882 2883 for (i = ALE_TIMEOUT; i > 0; i--) { 2884 reg = CSR_READ_4(sc, ALE_IDLE_STATUS); 2885 if (reg == 0) 2886 break; 2887 DELAY(10); 2888 } 2889 if (i == 0) 2890 device_printf(sc->ale_dev, 2891 "could not disable Tx/Rx MAC(0x%08x)!\n", reg); 2892 } 2893 2894 static void 2895 ale_init_tx_ring(struct ale_softc *sc) 2896 { 2897 struct ale_txdesc *txd; 2898 int i; 2899 2900 ALE_LOCK_ASSERT(sc); 2901 2902 sc->ale_cdata.ale_tx_prod = 0; 2903 sc->ale_cdata.ale_tx_cons = 0; 2904 sc->ale_cdata.ale_tx_cnt = 0; 2905 2906 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ); 2907 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ); 2908 for (i = 0; i < ALE_TX_RING_CNT; i++) { 2909 txd = &sc->ale_cdata.ale_txdesc[i]; 2910 txd->tx_m = NULL; 2911 } 2912 *sc->ale_cdata.ale_tx_cmb = 0; 2913 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2914 sc->ale_cdata.ale_tx_cmb_map, 2915 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2916 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2917 sc->ale_cdata.ale_tx_ring_map, 2918 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2919 } 2920 2921 static void 2922 ale_init_rx_pages(struct ale_softc *sc) 2923 { 2924 struct ale_rx_page *rx_page; 2925 int i; 2926 2927 ALE_LOCK_ASSERT(sc); 2928 2929 sc->ale_morework = 0; 2930 sc->ale_cdata.ale_rx_seqno = 0; 2931 sc->ale_cdata.ale_rx_curp = 0; 2932 2933 for (i = 0; i < ALE_RX_PAGES; i++) { 2934 rx_page = &sc->ale_cdata.ale_rx_page[i]; 2935 bzero(rx_page->page_addr, sc->ale_pagesize); 2936 bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ); 2937 rx_page->cons = 0; 2938 *rx_page->cmb_addr = 0; 2939 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2940 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2941 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2942 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2943 } 2944 } 2945 2946 static void 2947 ale_rxvlan(struct ale_softc *sc) 2948 { 2949 if_t ifp; 2950 uint32_t reg; 2951 2952 ALE_LOCK_ASSERT(sc); 2953 2954 ifp = sc->ale_ifp; 2955 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2956 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2957 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 2958 reg |= MAC_CFG_VLAN_TAG_STRIP; 2959 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2960 } 2961 2962 static u_int 2963 ale_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 2964 { 2965 uint32_t crc, *mchash = arg; 2966 2967 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 2968 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2969 2970 return (1); 2971 } 2972 2973 static void 2974 ale_rxfilter(struct ale_softc *sc) 2975 { 2976 if_t ifp; 2977 uint32_t mchash[2]; 2978 uint32_t rxcfg; 2979 2980 ALE_LOCK_ASSERT(sc); 2981 2982 ifp = sc->ale_ifp; 2983 2984 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); 2985 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 2986 if ((if_getflags(ifp) & IFF_BROADCAST) != 0) 2987 rxcfg |= MAC_CFG_BCAST; 2988 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 2989 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 2990 rxcfg |= MAC_CFG_PROMISC; 2991 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) 2992 rxcfg |= MAC_CFG_ALLMULTI; 2993 CSR_WRITE_4(sc, ALE_MAR0, 0xFFFFFFFF); 2994 CSR_WRITE_4(sc, ALE_MAR1, 0xFFFFFFFF); 2995 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 2996 return; 2997 } 2998 2999 /* Program new filter. */ 3000 bzero(mchash, sizeof(mchash)); 3001 if_foreach_llmaddr(ifp, ale_hash_maddr, &mchash); 3002 3003 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); 3004 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); 3005 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3006 } 3007 3008 static int 3009 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3010 { 3011 int error, value; 3012 3013 if (arg1 == NULL) 3014 return (EINVAL); 3015 value = *(int *)arg1; 3016 error = sysctl_handle_int(oidp, &value, 0, req); 3017 if (error || req->newptr == NULL) 3018 return (error); 3019 if (value < low || value > high) 3020 return (EINVAL); 3021 *(int *)arg1 = value; 3022 3023 return (0); 3024 } 3025 3026 static int 3027 sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS) 3028 { 3029 return (sysctl_int_range(oidp, arg1, arg2, req, 3030 ALE_PROC_MIN, ALE_PROC_MAX)); 3031 } 3032 3033 static int 3034 sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS) 3035 { 3036 3037 return (sysctl_int_range(oidp, arg1, arg2, req, 3038 ALE_IM_TIMER_MIN, ALE_IM_TIMER_MAX)); 3039 } 3040