1 /*- 2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/kernel.h> 38 #include <sys/malloc.h> 39 #include <sys/mbuf.h> 40 #include <sys/module.h> 41 #include <sys/rman.h> 42 #include <sys/queue.h> 43 #include <sys/socket.h> 44 #include <sys/sockio.h> 45 #include <sys/sysctl.h> 46 #include <sys/taskqueue.h> 47 48 #include <net/bpf.h> 49 #include <net/if.h> 50 #include <net/if_var.h> 51 #include <net/if_arp.h> 52 #include <net/ethernet.h> 53 #include <net/if_dl.h> 54 #include <net/if_llc.h> 55 #include <net/if_media.h> 56 #include <net/if_types.h> 57 #include <net/if_vlan_var.h> 58 59 #include <netinet/in.h> 60 #include <netinet/in_systm.h> 61 #include <netinet/ip.h> 62 #include <netinet/tcp.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 70 #include <machine/bus.h> 71 #include <machine/in_cksum.h> 72 73 #include <dev/ale/if_alereg.h> 74 #include <dev/ale/if_alevar.h> 75 76 /* "device miibus" required. See GENERIC if you get errors here. */ 77 #include "miibus_if.h" 78 79 /* For more information about Tx checksum offload issues see ale_encap(). */ 80 #define ALE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 81 82 MODULE_DEPEND(ale, pci, 1, 1, 1); 83 MODULE_DEPEND(ale, ether, 1, 1, 1); 84 MODULE_DEPEND(ale, miibus, 1, 1, 1); 85 86 /* Tunables. */ 87 static int msi_disable = 0; 88 static int msix_disable = 0; 89 TUNABLE_INT("hw.ale.msi_disable", &msi_disable); 90 TUNABLE_INT("hw.ale.msix_disable", &msix_disable); 91 92 /* 93 * Devices supported by this driver. 94 */ 95 static const struct ale_dev { 96 uint16_t ale_vendorid; 97 uint16_t ale_deviceid; 98 const char *ale_name; 99 } ale_devs[] = { 100 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR81XX, 101 "Atheros AR8121/AR8113/AR8114 PCIe Ethernet" }, 102 }; 103 104 static int ale_attach(device_t); 105 static int ale_check_boundary(struct ale_softc *); 106 static int ale_detach(device_t); 107 static int ale_dma_alloc(struct ale_softc *); 108 static void ale_dma_free(struct ale_softc *); 109 static void ale_dmamap_cb(void *, bus_dma_segment_t *, int, int); 110 static int ale_encap(struct ale_softc *, struct mbuf **); 111 static void ale_get_macaddr(struct ale_softc *); 112 static void ale_init(void *); 113 static void ale_init_locked(struct ale_softc *); 114 static void ale_init_rx_pages(struct ale_softc *); 115 static void ale_init_tx_ring(struct ale_softc *); 116 static void ale_int_task(void *, int); 117 static int ale_intr(void *); 118 static int ale_ioctl(struct ifnet *, u_long, caddr_t); 119 static void ale_mac_config(struct ale_softc *); 120 static int ale_miibus_readreg(device_t, int, int); 121 static void ale_miibus_statchg(device_t); 122 static int ale_miibus_writereg(device_t, int, int, int); 123 static int ale_mediachange(struct ifnet *); 124 static void ale_mediastatus(struct ifnet *, struct ifmediareq *); 125 static void ale_phy_reset(struct ale_softc *); 126 static int ale_probe(device_t); 127 static void ale_reset(struct ale_softc *); 128 static int ale_resume(device_t); 129 static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, 130 uint32_t, uint32_t *); 131 static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); 132 static int ale_rxeof(struct ale_softc *sc, int); 133 static void ale_rxfilter(struct ale_softc *); 134 static void ale_rxvlan(struct ale_softc *); 135 static void ale_setlinkspeed(struct ale_softc *); 136 static void ale_setwol(struct ale_softc *); 137 static int ale_shutdown(device_t); 138 static void ale_start(struct ifnet *); 139 static void ale_start_locked(struct ifnet *); 140 static void ale_stats_clear(struct ale_softc *); 141 static void ale_stats_update(struct ale_softc *); 142 static void ale_stop(struct ale_softc *); 143 static void ale_stop_mac(struct ale_softc *); 144 static int ale_suspend(device_t); 145 static void ale_sysctl_node(struct ale_softc *); 146 static void ale_tick(void *); 147 static void ale_txeof(struct ale_softc *); 148 static void ale_watchdog(struct ale_softc *); 149 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 150 static int sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS); 151 static int sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS); 152 153 static device_method_t ale_methods[] = { 154 /* Device interface. */ 155 DEVMETHOD(device_probe, ale_probe), 156 DEVMETHOD(device_attach, ale_attach), 157 DEVMETHOD(device_detach, ale_detach), 158 DEVMETHOD(device_shutdown, ale_shutdown), 159 DEVMETHOD(device_suspend, ale_suspend), 160 DEVMETHOD(device_resume, ale_resume), 161 162 /* MII interface. */ 163 DEVMETHOD(miibus_readreg, ale_miibus_readreg), 164 DEVMETHOD(miibus_writereg, ale_miibus_writereg), 165 DEVMETHOD(miibus_statchg, ale_miibus_statchg), 166 167 DEVMETHOD_END 168 }; 169 170 static driver_t ale_driver = { 171 "ale", 172 ale_methods, 173 sizeof(struct ale_softc) 174 }; 175 176 static devclass_t ale_devclass; 177 178 DRIVER_MODULE(ale, pci, ale_driver, ale_devclass, NULL, NULL); 179 DRIVER_MODULE(miibus, ale, miibus_driver, miibus_devclass, NULL, NULL); 180 181 static struct resource_spec ale_res_spec_mem[] = { 182 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 183 { -1, 0, 0 } 184 }; 185 186 static struct resource_spec ale_irq_spec_legacy[] = { 187 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 188 { -1, 0, 0 } 189 }; 190 191 static struct resource_spec ale_irq_spec_msi[] = { 192 { SYS_RES_IRQ, 1, RF_ACTIVE }, 193 { -1, 0, 0 } 194 }; 195 196 static struct resource_spec ale_irq_spec_msix[] = { 197 { SYS_RES_IRQ, 1, RF_ACTIVE }, 198 { -1, 0, 0 } 199 }; 200 201 static int 202 ale_miibus_readreg(device_t dev, int phy, int reg) 203 { 204 struct ale_softc *sc; 205 uint32_t v; 206 int i; 207 208 sc = device_get_softc(dev); 209 210 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 211 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 212 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 213 DELAY(5); 214 v = CSR_READ_4(sc, ALE_MDIO); 215 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 216 break; 217 } 218 219 if (i == 0) { 220 device_printf(sc->ale_dev, "phy read timeout : %d\n", reg); 221 return (0); 222 } 223 224 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 225 } 226 227 static int 228 ale_miibus_writereg(device_t dev, int phy, int reg, int val) 229 { 230 struct ale_softc *sc; 231 uint32_t v; 232 int i; 233 234 sc = device_get_softc(dev); 235 236 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 237 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 238 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 239 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 240 DELAY(5); 241 v = CSR_READ_4(sc, ALE_MDIO); 242 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 243 break; 244 } 245 246 if (i == 0) 247 device_printf(sc->ale_dev, "phy write timeout : %d\n", reg); 248 249 return (0); 250 } 251 252 static void 253 ale_miibus_statchg(device_t dev) 254 { 255 struct ale_softc *sc; 256 struct mii_data *mii; 257 struct ifnet *ifp; 258 uint32_t reg; 259 260 sc = device_get_softc(dev); 261 mii = device_get_softc(sc->ale_miibus); 262 ifp = sc->ale_ifp; 263 if (mii == NULL || ifp == NULL || 264 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 265 return; 266 267 sc->ale_flags &= ~ALE_FLAG_LINK; 268 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 269 (IFM_ACTIVE | IFM_AVALID)) { 270 switch (IFM_SUBTYPE(mii->mii_media_active)) { 271 case IFM_10_T: 272 case IFM_100_TX: 273 sc->ale_flags |= ALE_FLAG_LINK; 274 break; 275 case IFM_1000_T: 276 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 277 sc->ale_flags |= ALE_FLAG_LINK; 278 break; 279 default: 280 break; 281 } 282 } 283 284 /* Stop Rx/Tx MACs. */ 285 ale_stop_mac(sc); 286 287 /* Program MACs with resolved speed/duplex/flow-control. */ 288 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { 289 ale_mac_config(sc); 290 /* Reenable Tx/Rx MACs. */ 291 reg = CSR_READ_4(sc, ALE_MAC_CFG); 292 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 293 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 294 } 295 } 296 297 static void 298 ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 299 { 300 struct ale_softc *sc; 301 struct mii_data *mii; 302 303 sc = ifp->if_softc; 304 ALE_LOCK(sc); 305 if ((ifp->if_flags & IFF_UP) == 0) { 306 ALE_UNLOCK(sc); 307 return; 308 } 309 mii = device_get_softc(sc->ale_miibus); 310 311 mii_pollstat(mii); 312 ifmr->ifm_status = mii->mii_media_status; 313 ifmr->ifm_active = mii->mii_media_active; 314 ALE_UNLOCK(sc); 315 } 316 317 static int 318 ale_mediachange(struct ifnet *ifp) 319 { 320 struct ale_softc *sc; 321 struct mii_data *mii; 322 struct mii_softc *miisc; 323 int error; 324 325 sc = ifp->if_softc; 326 ALE_LOCK(sc); 327 mii = device_get_softc(sc->ale_miibus); 328 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 329 PHY_RESET(miisc); 330 error = mii_mediachg(mii); 331 ALE_UNLOCK(sc); 332 333 return (error); 334 } 335 336 static int 337 ale_probe(device_t dev) 338 { 339 const struct ale_dev *sp; 340 int i; 341 uint16_t vendor, devid; 342 343 vendor = pci_get_vendor(dev); 344 devid = pci_get_device(dev); 345 sp = ale_devs; 346 for (i = 0; i < sizeof(ale_devs) / sizeof(ale_devs[0]); i++) { 347 if (vendor == sp->ale_vendorid && 348 devid == sp->ale_deviceid) { 349 device_set_desc(dev, sp->ale_name); 350 return (BUS_PROBE_DEFAULT); 351 } 352 sp++; 353 } 354 355 return (ENXIO); 356 } 357 358 static void 359 ale_get_macaddr(struct ale_softc *sc) 360 { 361 uint32_t ea[2], reg; 362 int i, vpdc; 363 364 reg = CSR_READ_4(sc, ALE_SPI_CTRL); 365 if ((reg & SPI_VPD_ENB) != 0) { 366 reg &= ~SPI_VPD_ENB; 367 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); 368 } 369 370 if (pci_find_cap(sc->ale_dev, PCIY_VPD, &vpdc) == 0) { 371 /* 372 * PCI VPD capability found, let TWSI reload EEPROM. 373 * This will set ethernet address of controller. 374 */ 375 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | 376 TWSI_CTRL_SW_LD_START); 377 for (i = 100; i > 0; i--) { 378 DELAY(1000); 379 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); 380 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 381 break; 382 } 383 if (i == 0) 384 device_printf(sc->ale_dev, 385 "reloading EEPROM timeout!\n"); 386 } else { 387 if (bootverbose) 388 device_printf(sc->ale_dev, 389 "PCI VPD capability not found!\n"); 390 } 391 392 ea[0] = CSR_READ_4(sc, ALE_PAR0); 393 ea[1] = CSR_READ_4(sc, ALE_PAR1); 394 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; 395 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; 396 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; 397 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; 398 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; 399 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; 400 } 401 402 static void 403 ale_phy_reset(struct ale_softc *sc) 404 { 405 406 /* Reset magic from Linux. */ 407 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 408 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 409 GPHY_CTRL_PHY_PLL_ON); 410 DELAY(1000); 411 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 412 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | 413 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); 414 DELAY(1000); 415 416 #define ATPHY_DBG_ADDR 0x1D 417 #define ATPHY_DBG_DATA 0x1E 418 419 /* Enable hibernation mode. */ 420 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 421 ATPHY_DBG_ADDR, 0x0B); 422 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 423 ATPHY_DBG_DATA, 0xBC00); 424 /* Set Class A/B for all modes. */ 425 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 426 ATPHY_DBG_ADDR, 0x00); 427 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 428 ATPHY_DBG_DATA, 0x02EF); 429 /* Enable 10BT power saving. */ 430 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 431 ATPHY_DBG_ADDR, 0x12); 432 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 433 ATPHY_DBG_DATA, 0x4C04); 434 /* Adjust 1000T power. */ 435 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 436 ATPHY_DBG_ADDR, 0x04); 437 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 438 ATPHY_DBG_ADDR, 0x8BBB); 439 /* 10BT center tap voltage. */ 440 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 441 ATPHY_DBG_ADDR, 0x05); 442 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 443 ATPHY_DBG_ADDR, 0x2C46); 444 445 #undef ATPHY_DBG_ADDR 446 #undef ATPHY_DBG_DATA 447 DELAY(1000); 448 } 449 450 static int 451 ale_attach(device_t dev) 452 { 453 struct ale_softc *sc; 454 struct ifnet *ifp; 455 uint16_t burst; 456 int error, i, msic, msixc, pmc; 457 uint32_t rxf_len, txf_len; 458 459 error = 0; 460 sc = device_get_softc(dev); 461 sc->ale_dev = dev; 462 463 mtx_init(&sc->ale_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 464 MTX_DEF); 465 callout_init_mtx(&sc->ale_tick_ch, &sc->ale_mtx, 0); 466 TASK_INIT(&sc->ale_int_task, 0, ale_int_task, sc); 467 468 /* Map the device. */ 469 pci_enable_busmaster(dev); 470 sc->ale_res_spec = ale_res_spec_mem; 471 sc->ale_irq_spec = ale_irq_spec_legacy; 472 error = bus_alloc_resources(dev, sc->ale_res_spec, sc->ale_res); 473 if (error != 0) { 474 device_printf(dev, "cannot allocate memory resources.\n"); 475 goto fail; 476 } 477 478 /* Set PHY address. */ 479 sc->ale_phyaddr = ALE_PHY_ADDR; 480 481 /* Reset PHY. */ 482 ale_phy_reset(sc); 483 484 /* Reset the ethernet controller. */ 485 ale_reset(sc); 486 487 /* Get PCI and chip id/revision. */ 488 sc->ale_rev = pci_get_revid(dev); 489 if (sc->ale_rev >= 0xF0) { 490 /* L2E Rev. B. AR8114 */ 491 sc->ale_flags |= ALE_FLAG_FASTETHER; 492 } else { 493 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { 494 /* L1E AR8121 */ 495 sc->ale_flags |= ALE_FLAG_JUMBO; 496 } else { 497 /* L2E Rev. A. AR8113 */ 498 sc->ale_flags |= ALE_FLAG_FASTETHER; 499 } 500 } 501 /* 502 * All known controllers seems to require 4 bytes alignment 503 * of Tx buffers to make Tx checksum offload with custom 504 * checksum generation method work. 505 */ 506 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; 507 /* 508 * All known controllers seems to have issues on Rx checksum 509 * offload for fragmented IP datagrams. 510 */ 511 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; 512 /* 513 * Don't use Tx CMB. It is known to cause RRS update failure 514 * under certain circumstances. Typical phenomenon of the 515 * issue would be unexpected sequence number encountered in 516 * Rx handler. 517 */ 518 sc->ale_flags |= ALE_FLAG_TXCMB_BUG; 519 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> 520 MASTER_CHIP_REV_SHIFT; 521 if (bootverbose) { 522 device_printf(dev, "PCI device revision : 0x%04x\n", 523 sc->ale_rev); 524 device_printf(dev, "Chip id/revision : 0x%04x\n", 525 sc->ale_chip_rev); 526 } 527 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); 528 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 529 /* 530 * Uninitialized hardware returns an invalid chip id/revision 531 * as well as 0xFFFFFFFF for Tx/Rx fifo length. 532 */ 533 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || 534 rxf_len == 0xFFFFFFF) { 535 device_printf(dev,"chip revision : 0x%04x, %u Tx FIFO " 536 "%u Rx FIFO -- not initialized?\n", sc->ale_chip_rev, 537 txf_len, rxf_len); 538 error = ENXIO; 539 goto fail; 540 } 541 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", txf_len, rxf_len); 542 543 /* Allocate IRQ resources. */ 544 msixc = pci_msix_count(dev); 545 msic = pci_msi_count(dev); 546 if (bootverbose) { 547 device_printf(dev, "MSIX count : %d\n", msixc); 548 device_printf(dev, "MSI count : %d\n", msic); 549 } 550 551 /* Prefer MSIX over MSI. */ 552 if (msix_disable == 0 || msi_disable == 0) { 553 if (msix_disable == 0 && msixc == ALE_MSIX_MESSAGES && 554 pci_alloc_msix(dev, &msixc) == 0) { 555 if (msixc == ALE_MSIX_MESSAGES) { 556 device_printf(dev, "Using %d MSIX messages.\n", 557 msixc); 558 sc->ale_flags |= ALE_FLAG_MSIX; 559 sc->ale_irq_spec = ale_irq_spec_msix; 560 } else 561 pci_release_msi(dev); 562 } 563 if (msi_disable == 0 && (sc->ale_flags & ALE_FLAG_MSIX) == 0 && 564 msic == ALE_MSI_MESSAGES && 565 pci_alloc_msi(dev, &msic) == 0) { 566 if (msic == ALE_MSI_MESSAGES) { 567 device_printf(dev, "Using %d MSI messages.\n", 568 msic); 569 sc->ale_flags |= ALE_FLAG_MSI; 570 sc->ale_irq_spec = ale_irq_spec_msi; 571 } else 572 pci_release_msi(dev); 573 } 574 } 575 576 error = bus_alloc_resources(dev, sc->ale_irq_spec, sc->ale_irq); 577 if (error != 0) { 578 device_printf(dev, "cannot allocate IRQ resources.\n"); 579 goto fail; 580 } 581 582 /* Get DMA parameters from PCIe device control register. */ 583 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 584 sc->ale_flags |= ALE_FLAG_PCIE; 585 burst = pci_read_config(dev, i + 0x08, 2); 586 /* Max read request size. */ 587 sc->ale_dma_rd_burst = ((burst >> 12) & 0x07) << 588 DMA_CFG_RD_BURST_SHIFT; 589 /* Max payload size. */ 590 sc->ale_dma_wr_burst = ((burst >> 5) & 0x07) << 591 DMA_CFG_WR_BURST_SHIFT; 592 if (bootverbose) { 593 device_printf(dev, "Read request size : %d bytes.\n", 594 128 << ((burst >> 12) & 0x07)); 595 device_printf(dev, "TLP payload size : %d bytes.\n", 596 128 << ((burst >> 5) & 0x07)); 597 } 598 } else { 599 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; 600 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; 601 } 602 603 /* Create device sysctl node. */ 604 ale_sysctl_node(sc); 605 606 if ((error = ale_dma_alloc(sc) != 0)) 607 goto fail; 608 609 /* Load station address. */ 610 ale_get_macaddr(sc); 611 612 ifp = sc->ale_ifp = if_alloc(IFT_ETHER); 613 if (ifp == NULL) { 614 device_printf(dev, "cannot allocate ifnet structure.\n"); 615 error = ENXIO; 616 goto fail; 617 } 618 619 ifp->if_softc = sc; 620 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 621 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 622 ifp->if_ioctl = ale_ioctl; 623 ifp->if_start = ale_start; 624 ifp->if_init = ale_init; 625 ifp->if_snd.ifq_drv_maxlen = ALE_TX_RING_CNT - 1; 626 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 627 IFQ_SET_READY(&ifp->if_snd); 628 ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4; 629 ifp->if_hwassist = ALE_CSUM_FEATURES | CSUM_TSO; 630 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { 631 sc->ale_flags |= ALE_FLAG_PMCAP; 632 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 633 } 634 ifp->if_capenable = ifp->if_capabilities; 635 636 /* Set up MII bus. */ 637 error = mii_attach(dev, &sc->ale_miibus, ifp, ale_mediachange, 638 ale_mediastatus, BMSR_DEFCAPMASK, sc->ale_phyaddr, MII_OFFSET_ANY, 639 MIIF_DOPAUSE); 640 if (error != 0) { 641 device_printf(dev, "attaching PHYs failed\n"); 642 goto fail; 643 } 644 645 ether_ifattach(ifp, sc->ale_eaddr); 646 647 /* VLAN capability setup. */ 648 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 649 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 650 ifp->if_capenable = ifp->if_capabilities; 651 /* 652 * Even though controllers supported by ale(3) have Rx checksum 653 * offload bug the workaround for fragmented frames seemed to 654 * work so far. However it seems Rx checksum offload does not 655 * work under certain conditions. So disable Rx checksum offload 656 * until I find more clue about it but allow users to override it. 657 */ 658 ifp->if_capenable &= ~IFCAP_RXCSUM; 659 660 /* Tell the upper layer(s) we support long frames. */ 661 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 662 663 /* Create local taskq. */ 664 sc->ale_tq = taskqueue_create_fast("ale_taskq", M_WAITOK, 665 taskqueue_thread_enqueue, &sc->ale_tq); 666 if (sc->ale_tq == NULL) { 667 device_printf(dev, "could not create taskqueue.\n"); 668 ether_ifdetach(ifp); 669 error = ENXIO; 670 goto fail; 671 } 672 taskqueue_start_threads(&sc->ale_tq, 1, PI_NET, "%s taskq", 673 device_get_nameunit(sc->ale_dev)); 674 675 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 676 msic = ALE_MSIX_MESSAGES; 677 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 678 msic = ALE_MSI_MESSAGES; 679 else 680 msic = 1; 681 for (i = 0; i < msic; i++) { 682 error = bus_setup_intr(dev, sc->ale_irq[i], 683 INTR_TYPE_NET | INTR_MPSAFE, ale_intr, NULL, sc, 684 &sc->ale_intrhand[i]); 685 if (error != 0) 686 break; 687 } 688 if (error != 0) { 689 device_printf(dev, "could not set up interrupt handler.\n"); 690 taskqueue_free(sc->ale_tq); 691 sc->ale_tq = NULL; 692 ether_ifdetach(ifp); 693 goto fail; 694 } 695 696 fail: 697 if (error != 0) 698 ale_detach(dev); 699 700 return (error); 701 } 702 703 static int 704 ale_detach(device_t dev) 705 { 706 struct ale_softc *sc; 707 struct ifnet *ifp; 708 int i, msic; 709 710 sc = device_get_softc(dev); 711 712 ifp = sc->ale_ifp; 713 if (device_is_attached(dev)) { 714 ether_ifdetach(ifp); 715 ALE_LOCK(sc); 716 ale_stop(sc); 717 ALE_UNLOCK(sc); 718 callout_drain(&sc->ale_tick_ch); 719 taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 720 } 721 722 if (sc->ale_tq != NULL) { 723 taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 724 taskqueue_free(sc->ale_tq); 725 sc->ale_tq = NULL; 726 } 727 728 if (sc->ale_miibus != NULL) { 729 device_delete_child(dev, sc->ale_miibus); 730 sc->ale_miibus = NULL; 731 } 732 bus_generic_detach(dev); 733 ale_dma_free(sc); 734 735 if (ifp != NULL) { 736 if_free(ifp); 737 sc->ale_ifp = NULL; 738 } 739 740 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 741 msic = ALE_MSIX_MESSAGES; 742 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 743 msic = ALE_MSI_MESSAGES; 744 else 745 msic = 1; 746 for (i = 0; i < msic; i++) { 747 if (sc->ale_intrhand[i] != NULL) { 748 bus_teardown_intr(dev, sc->ale_irq[i], 749 sc->ale_intrhand[i]); 750 sc->ale_intrhand[i] = NULL; 751 } 752 } 753 754 bus_release_resources(dev, sc->ale_irq_spec, sc->ale_irq); 755 if ((sc->ale_flags & (ALE_FLAG_MSI | ALE_FLAG_MSIX)) != 0) 756 pci_release_msi(dev); 757 bus_release_resources(dev, sc->ale_res_spec, sc->ale_res); 758 mtx_destroy(&sc->ale_mtx); 759 760 return (0); 761 } 762 763 #define ALE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 764 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 765 766 #if __FreeBSD_version >= 900030 767 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 768 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 769 #elif __FreeBSD_version > 800000 770 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 771 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 772 #else 773 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 774 SYSCTL_ADD_ULONG(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 775 #endif 776 777 static void 778 ale_sysctl_node(struct ale_softc *sc) 779 { 780 struct sysctl_ctx_list *ctx; 781 struct sysctl_oid_list *child, *parent; 782 struct sysctl_oid *tree; 783 struct ale_hw_stats *stats; 784 int error; 785 786 stats = &sc->ale_stats; 787 ctx = device_get_sysctl_ctx(sc->ale_dev); 788 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ale_dev)); 789 790 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 791 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_rx_mod, 0, 792 sysctl_hw_ale_int_mod, "I", "ale Rx interrupt moderation"); 793 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 794 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_tx_mod, 0, 795 sysctl_hw_ale_int_mod, "I", "ale Tx interrupt moderation"); 796 /* Pull in device tunables. */ 797 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 798 error = resource_int_value(device_get_name(sc->ale_dev), 799 device_get_unit(sc->ale_dev), "int_rx_mod", &sc->ale_int_rx_mod); 800 if (error == 0) { 801 if (sc->ale_int_rx_mod < ALE_IM_TIMER_MIN || 802 sc->ale_int_rx_mod > ALE_IM_TIMER_MAX) { 803 device_printf(sc->ale_dev, "int_rx_mod value out of " 804 "range; using default: %d\n", 805 ALE_IM_RX_TIMER_DEFAULT); 806 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 807 } 808 } 809 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 810 error = resource_int_value(device_get_name(sc->ale_dev), 811 device_get_unit(sc->ale_dev), "int_tx_mod", &sc->ale_int_tx_mod); 812 if (error == 0) { 813 if (sc->ale_int_tx_mod < ALE_IM_TIMER_MIN || 814 sc->ale_int_tx_mod > ALE_IM_TIMER_MAX) { 815 device_printf(sc->ale_dev, "int_tx_mod value out of " 816 "range; using default: %d\n", 817 ALE_IM_TX_TIMER_DEFAULT); 818 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 819 } 820 } 821 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 822 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_process_limit, 0, 823 sysctl_hw_ale_proc_limit, "I", 824 "max number of Rx events to process"); 825 /* Pull in device tunables. */ 826 sc->ale_process_limit = ALE_PROC_DEFAULT; 827 error = resource_int_value(device_get_name(sc->ale_dev), 828 device_get_unit(sc->ale_dev), "process_limit", 829 &sc->ale_process_limit); 830 if (error == 0) { 831 if (sc->ale_process_limit < ALE_PROC_MIN || 832 sc->ale_process_limit > ALE_PROC_MAX) { 833 device_printf(sc->ale_dev, 834 "process_limit value out of range; " 835 "using default: %d\n", ALE_PROC_DEFAULT); 836 sc->ale_process_limit = ALE_PROC_DEFAULT; 837 } 838 } 839 840 /* Misc statistics. */ 841 ALE_SYSCTL_STAT_ADD32(ctx, child, "reset_brk_seq", 842 &stats->reset_brk_seq, 843 "Controller resets due to broken Rx sequnce number"); 844 845 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 846 NULL, "ATE statistics"); 847 parent = SYSCTL_CHILDREN(tree); 848 849 /* Rx statistics. */ 850 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 851 NULL, "Rx MAC statistics"); 852 child = SYSCTL_CHILDREN(tree); 853 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 854 &stats->rx_frames, "Good frames"); 855 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 856 &stats->rx_bcast_frames, "Good broadcast frames"); 857 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 858 &stats->rx_mcast_frames, "Good multicast frames"); 859 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 860 &stats->rx_pause_frames, "Pause control frames"); 861 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 862 &stats->rx_control_frames, "Control frames"); 863 ALE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 864 &stats->rx_crcerrs, "CRC errors"); 865 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 866 &stats->rx_lenerrs, "Frames with length mismatched"); 867 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 868 &stats->rx_bytes, "Good octets"); 869 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 870 &stats->rx_bcast_bytes, "Good broadcast octets"); 871 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 872 &stats->rx_mcast_bytes, "Good multicast octets"); 873 ALE_SYSCTL_STAT_ADD32(ctx, child, "runts", 874 &stats->rx_runts, "Too short frames"); 875 ALE_SYSCTL_STAT_ADD32(ctx, child, "fragments", 876 &stats->rx_fragments, "Fragmented frames"); 877 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 878 &stats->rx_pkts_64, "64 bytes frames"); 879 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 880 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 881 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 882 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 883 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 884 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 885 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 886 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 887 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 888 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 889 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 890 &stats->rx_pkts_1519_max, "1519 to max frames"); 891 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 892 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 893 ALE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 894 &stats->rx_fifo_oflows, "FIFO overflows"); 895 ALE_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 896 &stats->rx_rrs_errs, "Return status write-back errors"); 897 ALE_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 898 &stats->rx_alignerrs, "Alignment errors"); 899 ALE_SYSCTL_STAT_ADD32(ctx, child, "filtered", 900 &stats->rx_pkts_filtered, 901 "Frames dropped due to address filtering"); 902 903 /* Tx statistics. */ 904 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 905 NULL, "Tx MAC statistics"); 906 child = SYSCTL_CHILDREN(tree); 907 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 908 &stats->tx_frames, "Good frames"); 909 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 910 &stats->tx_bcast_frames, "Good broadcast frames"); 911 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 912 &stats->tx_mcast_frames, "Good multicast frames"); 913 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 914 &stats->tx_pause_frames, "Pause control frames"); 915 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 916 &stats->tx_control_frames, "Control frames"); 917 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 918 &stats->tx_excess_defer, "Frames with excessive derferrals"); 919 ALE_SYSCTL_STAT_ADD32(ctx, child, "defers", 920 &stats->tx_excess_defer, "Frames with derferrals"); 921 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 922 &stats->tx_bytes, "Good octets"); 923 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 924 &stats->tx_bcast_bytes, "Good broadcast octets"); 925 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 926 &stats->tx_mcast_bytes, "Good multicast octets"); 927 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 928 &stats->tx_pkts_64, "64 bytes frames"); 929 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 930 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 931 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 932 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 933 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 934 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 935 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 936 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 937 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 938 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 939 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 940 &stats->tx_pkts_1519_max, "1519 to max frames"); 941 ALE_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 942 &stats->tx_single_colls, "Single collisions"); 943 ALE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 944 &stats->tx_multi_colls, "Multiple collisions"); 945 ALE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 946 &stats->tx_late_colls, "Late collisions"); 947 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 948 &stats->tx_excess_colls, "Excessive collisions"); 949 ALE_SYSCTL_STAT_ADD32(ctx, child, "abort", 950 &stats->tx_abort, "Aborted frames due to Excessive collisions"); 951 ALE_SYSCTL_STAT_ADD32(ctx, child, "underruns", 952 &stats->tx_underrun, "FIFO underruns"); 953 ALE_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 954 &stats->tx_desc_underrun, "Descriptor write-back errors"); 955 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 956 &stats->tx_lenerrs, "Frames with length mismatched"); 957 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 958 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 959 } 960 961 #undef ALE_SYSCTL_STAT_ADD32 962 #undef ALE_SYSCTL_STAT_ADD64 963 964 struct ale_dmamap_arg { 965 bus_addr_t ale_busaddr; 966 }; 967 968 static void 969 ale_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 970 { 971 struct ale_dmamap_arg *ctx; 972 973 if (error != 0) 974 return; 975 976 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 977 978 ctx = (struct ale_dmamap_arg *)arg; 979 ctx->ale_busaddr = segs[0].ds_addr; 980 } 981 982 /* 983 * Tx descriptors/RXF0/CMB DMA blocks share ALE_DESC_ADDR_HI register 984 * which specifies high address region of DMA blocks. Therefore these 985 * blocks should have the same high address of given 4GB address 986 * space(i.e. crossing 4GB boundary is not allowed). 987 */ 988 static int 989 ale_check_boundary(struct ale_softc *sc) 990 { 991 bus_addr_t rx_cmb_end[ALE_RX_PAGES], tx_cmb_end; 992 bus_addr_t rx_page_end[ALE_RX_PAGES], tx_ring_end; 993 994 rx_page_end[0] = sc->ale_cdata.ale_rx_page[0].page_paddr + 995 sc->ale_pagesize; 996 rx_page_end[1] = sc->ale_cdata.ale_rx_page[1].page_paddr + 997 sc->ale_pagesize; 998 tx_ring_end = sc->ale_cdata.ale_tx_ring_paddr + ALE_TX_RING_SZ; 999 tx_cmb_end = sc->ale_cdata.ale_tx_cmb_paddr + ALE_TX_CMB_SZ; 1000 rx_cmb_end[0] = sc->ale_cdata.ale_rx_page[0].cmb_paddr + ALE_RX_CMB_SZ; 1001 rx_cmb_end[1] = sc->ale_cdata.ale_rx_page[1].cmb_paddr + ALE_RX_CMB_SZ; 1002 1003 if ((ALE_ADDR_HI(tx_ring_end) != 1004 ALE_ADDR_HI(sc->ale_cdata.ale_tx_ring_paddr)) || 1005 (ALE_ADDR_HI(rx_page_end[0]) != 1006 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].page_paddr)) || 1007 (ALE_ADDR_HI(rx_page_end[1]) != 1008 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].page_paddr)) || 1009 (ALE_ADDR_HI(tx_cmb_end) != 1010 ALE_ADDR_HI(sc->ale_cdata.ale_tx_cmb_paddr)) || 1011 (ALE_ADDR_HI(rx_cmb_end[0]) != 1012 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].cmb_paddr)) || 1013 (ALE_ADDR_HI(rx_cmb_end[1]) != 1014 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].cmb_paddr))) 1015 return (EFBIG); 1016 1017 if ((ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[0])) || 1018 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[1])) || 1019 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[0])) || 1020 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[1])) || 1021 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(tx_cmb_end))) 1022 return (EFBIG); 1023 1024 return (0); 1025 } 1026 1027 static int 1028 ale_dma_alloc(struct ale_softc *sc) 1029 { 1030 struct ale_txdesc *txd; 1031 bus_addr_t lowaddr; 1032 struct ale_dmamap_arg ctx; 1033 int error, guard_size, i; 1034 1035 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 1036 guard_size = ALE_JUMBO_FRAMELEN; 1037 else 1038 guard_size = ALE_MAX_FRAMELEN; 1039 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, 1040 ALE_RX_PAGE_ALIGN); 1041 lowaddr = BUS_SPACE_MAXADDR; 1042 again: 1043 /* Create parent DMA tag. */ 1044 error = bus_dma_tag_create( 1045 bus_get_dma_tag(sc->ale_dev), /* parent */ 1046 1, 0, /* alignment, boundary */ 1047 lowaddr, /* lowaddr */ 1048 BUS_SPACE_MAXADDR, /* highaddr */ 1049 NULL, NULL, /* filter, filterarg */ 1050 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1051 0, /* nsegments */ 1052 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1053 0, /* flags */ 1054 NULL, NULL, /* lockfunc, lockarg */ 1055 &sc->ale_cdata.ale_parent_tag); 1056 if (error != 0) { 1057 device_printf(sc->ale_dev, 1058 "could not create parent DMA tag.\n"); 1059 goto fail; 1060 } 1061 1062 /* Create DMA tag for Tx descriptor ring. */ 1063 error = bus_dma_tag_create( 1064 sc->ale_cdata.ale_parent_tag, /* parent */ 1065 ALE_TX_RING_ALIGN, 0, /* alignment, boundary */ 1066 BUS_SPACE_MAXADDR, /* lowaddr */ 1067 BUS_SPACE_MAXADDR, /* highaddr */ 1068 NULL, NULL, /* filter, filterarg */ 1069 ALE_TX_RING_SZ, /* maxsize */ 1070 1, /* nsegments */ 1071 ALE_TX_RING_SZ, /* maxsegsize */ 1072 0, /* flags */ 1073 NULL, NULL, /* lockfunc, lockarg */ 1074 &sc->ale_cdata.ale_tx_ring_tag); 1075 if (error != 0) { 1076 device_printf(sc->ale_dev, 1077 "could not create Tx ring DMA tag.\n"); 1078 goto fail; 1079 } 1080 1081 /* Create DMA tag for Rx pages. */ 1082 for (i = 0; i < ALE_RX_PAGES; i++) { 1083 error = bus_dma_tag_create( 1084 sc->ale_cdata.ale_parent_tag, /* parent */ 1085 ALE_RX_PAGE_ALIGN, 0, /* alignment, boundary */ 1086 BUS_SPACE_MAXADDR, /* lowaddr */ 1087 BUS_SPACE_MAXADDR, /* highaddr */ 1088 NULL, NULL, /* filter, filterarg */ 1089 sc->ale_pagesize, /* maxsize */ 1090 1, /* nsegments */ 1091 sc->ale_pagesize, /* maxsegsize */ 1092 0, /* flags */ 1093 NULL, NULL, /* lockfunc, lockarg */ 1094 &sc->ale_cdata.ale_rx_page[i].page_tag); 1095 if (error != 0) { 1096 device_printf(sc->ale_dev, 1097 "could not create Rx page %d DMA tag.\n", i); 1098 goto fail; 1099 } 1100 } 1101 1102 /* Create DMA tag for Tx coalescing message block. */ 1103 error = bus_dma_tag_create( 1104 sc->ale_cdata.ale_parent_tag, /* parent */ 1105 ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1106 BUS_SPACE_MAXADDR, /* lowaddr */ 1107 BUS_SPACE_MAXADDR, /* highaddr */ 1108 NULL, NULL, /* filter, filterarg */ 1109 ALE_TX_CMB_SZ, /* maxsize */ 1110 1, /* nsegments */ 1111 ALE_TX_CMB_SZ, /* maxsegsize */ 1112 0, /* flags */ 1113 NULL, NULL, /* lockfunc, lockarg */ 1114 &sc->ale_cdata.ale_tx_cmb_tag); 1115 if (error != 0) { 1116 device_printf(sc->ale_dev, 1117 "could not create Tx CMB DMA tag.\n"); 1118 goto fail; 1119 } 1120 1121 /* Create DMA tag for Rx coalescing message block. */ 1122 for (i = 0; i < ALE_RX_PAGES; i++) { 1123 error = bus_dma_tag_create( 1124 sc->ale_cdata.ale_parent_tag, /* parent */ 1125 ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1126 BUS_SPACE_MAXADDR, /* lowaddr */ 1127 BUS_SPACE_MAXADDR, /* highaddr */ 1128 NULL, NULL, /* filter, filterarg */ 1129 ALE_RX_CMB_SZ, /* maxsize */ 1130 1, /* nsegments */ 1131 ALE_RX_CMB_SZ, /* maxsegsize */ 1132 0, /* flags */ 1133 NULL, NULL, /* lockfunc, lockarg */ 1134 &sc->ale_cdata.ale_rx_page[i].cmb_tag); 1135 if (error != 0) { 1136 device_printf(sc->ale_dev, 1137 "could not create Rx page %d CMB DMA tag.\n", i); 1138 goto fail; 1139 } 1140 } 1141 1142 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1143 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_ring_tag, 1144 (void **)&sc->ale_cdata.ale_tx_ring, 1145 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1146 &sc->ale_cdata.ale_tx_ring_map); 1147 if (error != 0) { 1148 device_printf(sc->ale_dev, 1149 "could not allocate DMA'able memory for Tx ring.\n"); 1150 goto fail; 1151 } 1152 ctx.ale_busaddr = 0; 1153 error = bus_dmamap_load(sc->ale_cdata.ale_tx_ring_tag, 1154 sc->ale_cdata.ale_tx_ring_map, sc->ale_cdata.ale_tx_ring, 1155 ALE_TX_RING_SZ, ale_dmamap_cb, &ctx, 0); 1156 if (error != 0 || ctx.ale_busaddr == 0) { 1157 device_printf(sc->ale_dev, 1158 "could not load DMA'able memory for Tx ring.\n"); 1159 goto fail; 1160 } 1161 sc->ale_cdata.ale_tx_ring_paddr = ctx.ale_busaddr; 1162 1163 /* Rx pages. */ 1164 for (i = 0; i < ALE_RX_PAGES; i++) { 1165 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].page_tag, 1166 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr, 1167 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1168 &sc->ale_cdata.ale_rx_page[i].page_map); 1169 if (error != 0) { 1170 device_printf(sc->ale_dev, 1171 "could not allocate DMA'able memory for " 1172 "Rx page %d.\n", i); 1173 goto fail; 1174 } 1175 ctx.ale_busaddr = 0; 1176 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].page_tag, 1177 sc->ale_cdata.ale_rx_page[i].page_map, 1178 sc->ale_cdata.ale_rx_page[i].page_addr, 1179 sc->ale_pagesize, ale_dmamap_cb, &ctx, 0); 1180 if (error != 0 || ctx.ale_busaddr == 0) { 1181 device_printf(sc->ale_dev, 1182 "could not load DMA'able memory for " 1183 "Rx page %d.\n", i); 1184 goto fail; 1185 } 1186 sc->ale_cdata.ale_rx_page[i].page_paddr = ctx.ale_busaddr; 1187 } 1188 1189 /* Tx CMB. */ 1190 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_cmb_tag, 1191 (void **)&sc->ale_cdata.ale_tx_cmb, 1192 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1193 &sc->ale_cdata.ale_tx_cmb_map); 1194 if (error != 0) { 1195 device_printf(sc->ale_dev, 1196 "could not allocate DMA'able memory for Tx CMB.\n"); 1197 goto fail; 1198 } 1199 ctx.ale_busaddr = 0; 1200 error = bus_dmamap_load(sc->ale_cdata.ale_tx_cmb_tag, 1201 sc->ale_cdata.ale_tx_cmb_map, sc->ale_cdata.ale_tx_cmb, 1202 ALE_TX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1203 if (error != 0 || ctx.ale_busaddr == 0) { 1204 device_printf(sc->ale_dev, 1205 "could not load DMA'able memory for Tx CMB.\n"); 1206 goto fail; 1207 } 1208 sc->ale_cdata.ale_tx_cmb_paddr = ctx.ale_busaddr; 1209 1210 /* Rx CMB. */ 1211 for (i = 0; i < ALE_RX_PAGES; i++) { 1212 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1213 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 1214 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1215 &sc->ale_cdata.ale_rx_page[i].cmb_map); 1216 if (error != 0) { 1217 device_printf(sc->ale_dev, "could not allocate " 1218 "DMA'able memory for Rx page %d CMB.\n", i); 1219 goto fail; 1220 } 1221 ctx.ale_busaddr = 0; 1222 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1223 sc->ale_cdata.ale_rx_page[i].cmb_map, 1224 sc->ale_cdata.ale_rx_page[i].cmb_addr, 1225 ALE_RX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1226 if (error != 0 || ctx.ale_busaddr == 0) { 1227 device_printf(sc->ale_dev, "could not load DMA'able " 1228 "memory for Rx page %d CMB.\n", i); 1229 goto fail; 1230 } 1231 sc->ale_cdata.ale_rx_page[i].cmb_paddr = ctx.ale_busaddr; 1232 } 1233 1234 /* 1235 * Tx descriptors/RXF0/CMB DMA blocks share the same 1236 * high address region of 64bit DMA address space. 1237 */ 1238 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1239 (error = ale_check_boundary(sc)) != 0) { 1240 device_printf(sc->ale_dev, "4GB boundary crossed, " 1241 "switching to 32bit DMA addressing mode.\n"); 1242 ale_dma_free(sc); 1243 /* 1244 * Limit max allowable DMA address space to 32bit 1245 * and try again. 1246 */ 1247 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1248 goto again; 1249 } 1250 1251 /* 1252 * Create Tx buffer parent tag. 1253 * AR81xx allows 64bit DMA addressing of Tx buffers so it 1254 * needs separate parent DMA tag as parent DMA address space 1255 * could be restricted to be within 32bit address space by 1256 * 4GB boundary crossing. 1257 */ 1258 error = bus_dma_tag_create( 1259 bus_get_dma_tag(sc->ale_dev), /* parent */ 1260 1, 0, /* alignment, boundary */ 1261 BUS_SPACE_MAXADDR, /* lowaddr */ 1262 BUS_SPACE_MAXADDR, /* highaddr */ 1263 NULL, NULL, /* filter, filterarg */ 1264 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1265 0, /* nsegments */ 1266 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1267 0, /* flags */ 1268 NULL, NULL, /* lockfunc, lockarg */ 1269 &sc->ale_cdata.ale_buffer_tag); 1270 if (error != 0) { 1271 device_printf(sc->ale_dev, 1272 "could not create parent buffer DMA tag.\n"); 1273 goto fail; 1274 } 1275 1276 /* Create DMA tag for Tx buffers. */ 1277 error = bus_dma_tag_create( 1278 sc->ale_cdata.ale_buffer_tag, /* parent */ 1279 1, 0, /* alignment, boundary */ 1280 BUS_SPACE_MAXADDR, /* lowaddr */ 1281 BUS_SPACE_MAXADDR, /* highaddr */ 1282 NULL, NULL, /* filter, filterarg */ 1283 ALE_TSO_MAXSIZE, /* maxsize */ 1284 ALE_MAXTXSEGS, /* nsegments */ 1285 ALE_TSO_MAXSEGSIZE, /* maxsegsize */ 1286 0, /* flags */ 1287 NULL, NULL, /* lockfunc, lockarg */ 1288 &sc->ale_cdata.ale_tx_tag); 1289 if (error != 0) { 1290 device_printf(sc->ale_dev, "could not create Tx DMA tag.\n"); 1291 goto fail; 1292 } 1293 1294 /* Create DMA maps for Tx buffers. */ 1295 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1296 txd = &sc->ale_cdata.ale_txdesc[i]; 1297 txd->tx_m = NULL; 1298 txd->tx_dmamap = NULL; 1299 error = bus_dmamap_create(sc->ale_cdata.ale_tx_tag, 0, 1300 &txd->tx_dmamap); 1301 if (error != 0) { 1302 device_printf(sc->ale_dev, 1303 "could not create Tx dmamap.\n"); 1304 goto fail; 1305 } 1306 } 1307 1308 fail: 1309 return (error); 1310 } 1311 1312 static void 1313 ale_dma_free(struct ale_softc *sc) 1314 { 1315 struct ale_txdesc *txd; 1316 int i; 1317 1318 /* Tx buffers. */ 1319 if (sc->ale_cdata.ale_tx_tag != NULL) { 1320 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1321 txd = &sc->ale_cdata.ale_txdesc[i]; 1322 if (txd->tx_dmamap != NULL) { 1323 bus_dmamap_destroy(sc->ale_cdata.ale_tx_tag, 1324 txd->tx_dmamap); 1325 txd->tx_dmamap = NULL; 1326 } 1327 } 1328 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_tag); 1329 sc->ale_cdata.ale_tx_tag = NULL; 1330 } 1331 /* Tx descriptor ring. */ 1332 if (sc->ale_cdata.ale_tx_ring_tag != NULL) { 1333 if (sc->ale_cdata.ale_tx_ring_paddr != 0) 1334 bus_dmamap_unload(sc->ale_cdata.ale_tx_ring_tag, 1335 sc->ale_cdata.ale_tx_ring_map); 1336 if (sc->ale_cdata.ale_tx_ring != NULL) 1337 bus_dmamem_free(sc->ale_cdata.ale_tx_ring_tag, 1338 sc->ale_cdata.ale_tx_ring, 1339 sc->ale_cdata.ale_tx_ring_map); 1340 sc->ale_cdata.ale_tx_ring_paddr = 0; 1341 sc->ale_cdata.ale_tx_ring = NULL; 1342 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_ring_tag); 1343 sc->ale_cdata.ale_tx_ring_tag = NULL; 1344 } 1345 /* Rx page block. */ 1346 for (i = 0; i < ALE_RX_PAGES; i++) { 1347 if (sc->ale_cdata.ale_rx_page[i].page_tag != NULL) { 1348 if (sc->ale_cdata.ale_rx_page[i].page_paddr != 0) 1349 bus_dmamap_unload( 1350 sc->ale_cdata.ale_rx_page[i].page_tag, 1351 sc->ale_cdata.ale_rx_page[i].page_map); 1352 if (sc->ale_cdata.ale_rx_page[i].page_addr != NULL) 1353 bus_dmamem_free( 1354 sc->ale_cdata.ale_rx_page[i].page_tag, 1355 sc->ale_cdata.ale_rx_page[i].page_addr, 1356 sc->ale_cdata.ale_rx_page[i].page_map); 1357 sc->ale_cdata.ale_rx_page[i].page_paddr = 0; 1358 sc->ale_cdata.ale_rx_page[i].page_addr = NULL; 1359 bus_dma_tag_destroy( 1360 sc->ale_cdata.ale_rx_page[i].page_tag); 1361 sc->ale_cdata.ale_rx_page[i].page_tag = NULL; 1362 } 1363 } 1364 /* Rx CMB. */ 1365 for (i = 0; i < ALE_RX_PAGES; i++) { 1366 if (sc->ale_cdata.ale_rx_page[i].cmb_tag != NULL) { 1367 if (sc->ale_cdata.ale_rx_page[i].cmb_paddr != 0) 1368 bus_dmamap_unload( 1369 sc->ale_cdata.ale_rx_page[i].cmb_tag, 1370 sc->ale_cdata.ale_rx_page[i].cmb_map); 1371 if (sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) 1372 bus_dmamem_free( 1373 sc->ale_cdata.ale_rx_page[i].cmb_tag, 1374 sc->ale_cdata.ale_rx_page[i].cmb_addr, 1375 sc->ale_cdata.ale_rx_page[i].cmb_map); 1376 sc->ale_cdata.ale_rx_page[i].cmb_paddr = 0; 1377 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; 1378 bus_dma_tag_destroy( 1379 sc->ale_cdata.ale_rx_page[i].cmb_tag); 1380 sc->ale_cdata.ale_rx_page[i].cmb_tag = NULL; 1381 } 1382 } 1383 /* Tx CMB. */ 1384 if (sc->ale_cdata.ale_tx_cmb_tag != NULL) { 1385 if (sc->ale_cdata.ale_tx_cmb_paddr != 0) 1386 bus_dmamap_unload(sc->ale_cdata.ale_tx_cmb_tag, 1387 sc->ale_cdata.ale_tx_cmb_map); 1388 if (sc->ale_cdata.ale_tx_cmb != NULL) 1389 bus_dmamem_free(sc->ale_cdata.ale_tx_cmb_tag, 1390 sc->ale_cdata.ale_tx_cmb, 1391 sc->ale_cdata.ale_tx_cmb_map); 1392 sc->ale_cdata.ale_tx_cmb_paddr = 0; 1393 sc->ale_cdata.ale_tx_cmb = NULL; 1394 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_cmb_tag); 1395 sc->ale_cdata.ale_tx_cmb_tag = NULL; 1396 } 1397 if (sc->ale_cdata.ale_buffer_tag != NULL) { 1398 bus_dma_tag_destroy(sc->ale_cdata.ale_buffer_tag); 1399 sc->ale_cdata.ale_buffer_tag = NULL; 1400 } 1401 if (sc->ale_cdata.ale_parent_tag != NULL) { 1402 bus_dma_tag_destroy(sc->ale_cdata.ale_parent_tag); 1403 sc->ale_cdata.ale_parent_tag = NULL; 1404 } 1405 } 1406 1407 static int 1408 ale_shutdown(device_t dev) 1409 { 1410 1411 return (ale_suspend(dev)); 1412 } 1413 1414 /* 1415 * Note, this driver resets the link speed to 10/100Mbps by 1416 * restarting auto-negotiation in suspend/shutdown phase but we 1417 * don't know whether that auto-negotiation would succeed or not 1418 * as driver has no control after powering off/suspend operation. 1419 * If the renegotiation fail WOL may not work. Running at 1Gbps 1420 * will draw more power than 375mA at 3.3V which is specified in 1421 * PCI specification and that would result in complete 1422 * shutdowning power to ethernet controller. 1423 * 1424 * TODO 1425 * Save current negotiated media speed/duplex/flow-control to 1426 * softc and restore the same link again after resuming. PHY 1427 * handling such as power down/resetting to 100Mbps may be better 1428 * handled in suspend method in phy driver. 1429 */ 1430 static void 1431 ale_setlinkspeed(struct ale_softc *sc) 1432 { 1433 struct mii_data *mii; 1434 int aneg, i; 1435 1436 mii = device_get_softc(sc->ale_miibus); 1437 mii_pollstat(mii); 1438 aneg = 0; 1439 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1440 (IFM_ACTIVE | IFM_AVALID)) { 1441 switch IFM_SUBTYPE(mii->mii_media_active) { 1442 case IFM_10_T: 1443 case IFM_100_TX: 1444 return; 1445 case IFM_1000_T: 1446 aneg++; 1447 break; 1448 default: 1449 break; 1450 } 1451 } 1452 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_100T2CR, 0); 1453 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1454 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1455 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1456 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1457 DELAY(1000); 1458 if (aneg != 0) { 1459 /* 1460 * Poll link state until ale(4) get a 10/100Mbps link. 1461 */ 1462 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1463 mii_pollstat(mii); 1464 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 1465 == (IFM_ACTIVE | IFM_AVALID)) { 1466 switch (IFM_SUBTYPE( 1467 mii->mii_media_active)) { 1468 case IFM_10_T: 1469 case IFM_100_TX: 1470 ale_mac_config(sc); 1471 return; 1472 default: 1473 break; 1474 } 1475 } 1476 ALE_UNLOCK(sc); 1477 pause("alelnk", hz); 1478 ALE_LOCK(sc); 1479 } 1480 if (i == MII_ANEGTICKS_GIGE) 1481 device_printf(sc->ale_dev, 1482 "establishing a link failed, WOL may not work!"); 1483 } 1484 /* 1485 * No link, force MAC to have 100Mbps, full-duplex link. 1486 * This is the last resort and may/may not work. 1487 */ 1488 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1489 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1490 ale_mac_config(sc); 1491 } 1492 1493 static void 1494 ale_setwol(struct ale_softc *sc) 1495 { 1496 struct ifnet *ifp; 1497 uint32_t reg, pmcs; 1498 uint16_t pmstat; 1499 int pmc; 1500 1501 ALE_LOCK_ASSERT(sc); 1502 1503 if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) != 0) { 1504 /* Disable WOL. */ 1505 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 1506 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1507 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1508 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1509 /* Force PHY power down. */ 1510 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1511 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1512 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_PHY_PLL_ON | 1513 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_IDDQ | 1514 GPHY_CTRL_PCLK_SEL_DIS | GPHY_CTRL_PWDOWN_HW); 1515 return; 1516 } 1517 1518 ifp = sc->ale_ifp; 1519 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1520 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 1521 ale_setlinkspeed(sc); 1522 } 1523 1524 pmcs = 0; 1525 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1526 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1527 CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs); 1528 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1529 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 1530 MAC_CFG_BCAST); 1531 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1532 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1533 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1534 reg |= MAC_CFG_RX_ENB; 1535 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1536 1537 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1538 /* WOL disabled, PHY power down. */ 1539 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1540 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1541 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1542 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1543 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1544 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 1545 GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PCLK_SEL_DIS | 1546 GPHY_CTRL_PWDOWN_HW); 1547 } 1548 /* Request PME. */ 1549 pmstat = pci_read_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, 2); 1550 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1551 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1552 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1553 pci_write_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1554 } 1555 1556 static int 1557 ale_suspend(device_t dev) 1558 { 1559 struct ale_softc *sc; 1560 1561 sc = device_get_softc(dev); 1562 1563 ALE_LOCK(sc); 1564 ale_stop(sc); 1565 ale_setwol(sc); 1566 ALE_UNLOCK(sc); 1567 1568 return (0); 1569 } 1570 1571 static int 1572 ale_resume(device_t dev) 1573 { 1574 struct ale_softc *sc; 1575 struct ifnet *ifp; 1576 int pmc; 1577 uint16_t pmstat; 1578 1579 sc = device_get_softc(dev); 1580 1581 ALE_LOCK(sc); 1582 if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) == 0) { 1583 /* Disable PME and clear PME status. */ 1584 pmstat = pci_read_config(sc->ale_dev, 1585 pmc + PCIR_POWER_STATUS, 2); 1586 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 1587 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1588 pci_write_config(sc->ale_dev, 1589 pmc + PCIR_POWER_STATUS, pmstat, 2); 1590 } 1591 } 1592 /* Reset PHY. */ 1593 ale_phy_reset(sc); 1594 ifp = sc->ale_ifp; 1595 if ((ifp->if_flags & IFF_UP) != 0) { 1596 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1597 ale_init_locked(sc); 1598 } 1599 ALE_UNLOCK(sc); 1600 1601 return (0); 1602 } 1603 1604 static int 1605 ale_encap(struct ale_softc *sc, struct mbuf **m_head) 1606 { 1607 struct ale_txdesc *txd, *txd_last; 1608 struct tx_desc *desc; 1609 struct mbuf *m; 1610 struct ip *ip; 1611 struct tcphdr *tcp; 1612 bus_dma_segment_t txsegs[ALE_MAXTXSEGS]; 1613 bus_dmamap_t map; 1614 uint32_t cflags, hdrlen, ip_off, poff, vtag; 1615 int error, i, nsegs, prod, si; 1616 1617 ALE_LOCK_ASSERT(sc); 1618 1619 M_ASSERTPKTHDR((*m_head)); 1620 1621 m = *m_head; 1622 ip = NULL; 1623 tcp = NULL; 1624 cflags = vtag = 0; 1625 ip_off = poff = 0; 1626 if ((m->m_pkthdr.csum_flags & (ALE_CSUM_FEATURES | CSUM_TSO)) != 0) { 1627 /* 1628 * AR81xx requires offset of TCP/UDP payload in its Tx 1629 * descriptor to perform hardware Tx checksum offload. 1630 * Additionally, TSO requires IP/TCP header size and 1631 * modification of IP/TCP header in order to make TSO 1632 * engine work. This kind of operation takes many CPU 1633 * cycles on FreeBSD so fast host CPU is required to 1634 * get smooth TSO performance. 1635 */ 1636 struct ether_header *eh; 1637 1638 if (M_WRITABLE(m) == 0) { 1639 /* Get a writable copy. */ 1640 m = m_dup(*m_head, M_NOWAIT); 1641 /* Release original mbufs. */ 1642 m_freem(*m_head); 1643 if (m == NULL) { 1644 *m_head = NULL; 1645 return (ENOBUFS); 1646 } 1647 *m_head = m; 1648 } 1649 1650 /* 1651 * Buggy-controller requires 4 byte aligned Tx buffer 1652 * to make custom checksum offload work. 1653 */ 1654 if ((sc->ale_flags & ALE_FLAG_TXCSUM_BUG) != 0 && 1655 (m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0 && 1656 (mtod(m, intptr_t) & 3) != 0) { 1657 m = m_defrag(*m_head, M_NOWAIT); 1658 if (m == NULL) { 1659 m_freem(*m_head); 1660 *m_head = NULL; 1661 return (ENOBUFS); 1662 } 1663 *m_head = m; 1664 } 1665 1666 ip_off = sizeof(struct ether_header); 1667 m = m_pullup(m, ip_off); 1668 if (m == NULL) { 1669 *m_head = NULL; 1670 return (ENOBUFS); 1671 } 1672 eh = mtod(m, struct ether_header *); 1673 /* 1674 * Check if hardware VLAN insertion is off. 1675 * Additional check for LLC/SNAP frame? 1676 */ 1677 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1678 ip_off = sizeof(struct ether_vlan_header); 1679 m = m_pullup(m, ip_off); 1680 if (m == NULL) { 1681 *m_head = NULL; 1682 return (ENOBUFS); 1683 } 1684 } 1685 m = m_pullup(m, ip_off + sizeof(struct ip)); 1686 if (m == NULL) { 1687 *m_head = NULL; 1688 return (ENOBUFS); 1689 } 1690 ip = (struct ip *)(mtod(m, char *) + ip_off); 1691 poff = ip_off + (ip->ip_hl << 2); 1692 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1693 /* 1694 * XXX 1695 * AR81xx requires the first descriptor should 1696 * not include any TCP playload for TSO case. 1697 * (i.e. ethernet header + IP + TCP header only) 1698 * m_pullup(9) above will ensure this too. 1699 * However it's not correct if the first mbuf 1700 * of the chain does not use cluster. 1701 */ 1702 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1703 if (m == NULL) { 1704 *m_head = NULL; 1705 return (ENOBUFS); 1706 } 1707 ip = (struct ip *)(mtod(m, char *) + ip_off); 1708 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1709 m = m_pullup(m, poff + (tcp->th_off << 2)); 1710 if (m == NULL) { 1711 *m_head = NULL; 1712 return (ENOBUFS); 1713 } 1714 /* 1715 * AR81xx requires IP/TCP header size and offset as 1716 * well as TCP pseudo checksum which complicates 1717 * TSO configuration. I guess this comes from the 1718 * adherence to Microsoft NDIS Large Send 1719 * specification which requires insertion of 1720 * pseudo checksum by upper stack. The pseudo 1721 * checksum that NDIS refers to doesn't include 1722 * TCP payload length so ale(4) should recompute 1723 * the pseudo checksum here. Hopefully this wouldn't 1724 * be much burden on modern CPUs. 1725 * Reset IP checksum and recompute TCP pseudo 1726 * checksum as NDIS specification said. 1727 */ 1728 ip->ip_sum = 0; 1729 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1730 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1731 } 1732 *m_head = m; 1733 } 1734 1735 si = prod = sc->ale_cdata.ale_tx_prod; 1736 txd = &sc->ale_cdata.ale_txdesc[prod]; 1737 txd_last = txd; 1738 map = txd->tx_dmamap; 1739 1740 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1741 *m_head, txsegs, &nsegs, 0); 1742 if (error == EFBIG) { 1743 m = m_collapse(*m_head, M_NOWAIT, ALE_MAXTXSEGS); 1744 if (m == NULL) { 1745 m_freem(*m_head); 1746 *m_head = NULL; 1747 return (ENOMEM); 1748 } 1749 *m_head = m; 1750 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1751 *m_head, txsegs, &nsegs, 0); 1752 if (error != 0) { 1753 m_freem(*m_head); 1754 *m_head = NULL; 1755 return (error); 1756 } 1757 } else if (error != 0) 1758 return (error); 1759 if (nsegs == 0) { 1760 m_freem(*m_head); 1761 *m_head = NULL; 1762 return (EIO); 1763 } 1764 1765 /* Check descriptor overrun. */ 1766 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 3) { 1767 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, map); 1768 return (ENOBUFS); 1769 } 1770 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, map, BUS_DMASYNC_PREWRITE); 1771 1772 m = *m_head; 1773 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1774 /* Request TSO and set MSS. */ 1775 cflags |= ALE_TD_TSO; 1776 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << ALE_TD_MSS_SHIFT); 1777 /* Set IP/TCP header size. */ 1778 cflags |= ip->ip_hl << ALE_TD_IPHDR_LEN_SHIFT; 1779 cflags |= tcp->th_off << ALE_TD_TCPHDR_LEN_SHIFT; 1780 } else if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { 1781 /* 1782 * AR81xx supports Tx custom checksum offload feature 1783 * that offloads single 16bit checksum computation. 1784 * So you can choose one among IP, TCP and UDP. 1785 * Normally driver sets checksum start/insertion 1786 * position from the information of TCP/UDP frame as 1787 * TCP/UDP checksum takes more time than that of IP. 1788 * However it seems that custom checksum offload 1789 * requires 4 bytes aligned Tx buffers due to hardware 1790 * bug. 1791 * AR81xx also supports explicit Tx checksum computation 1792 * if it is told that the size of IP header and TCP 1793 * header(for UDP, the header size does not matter 1794 * because it's fixed length). However with this scheme 1795 * TSO does not work so you have to choose one either 1796 * TSO or explicit Tx checksum offload. I chosen TSO 1797 * plus custom checksum offload with work-around which 1798 * will cover most common usage for this consumer 1799 * ethernet controller. The work-around takes a lot of 1800 * CPU cycles if Tx buffer is not aligned on 4 bytes 1801 * boundary, though. 1802 */ 1803 cflags |= ALE_TD_CXSUM; 1804 /* Set checksum start offset. */ 1805 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); 1806 /* Set checksum insertion position of TCP/UDP. */ 1807 cflags |= ((poff + m->m_pkthdr.csum_data) << 1808 ALE_TD_CSUM_XSUMOFFSET_SHIFT); 1809 } 1810 1811 /* Configure VLAN hardware tag insertion. */ 1812 if ((m->m_flags & M_VLANTAG) != 0) { 1813 vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1814 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); 1815 cflags |= ALE_TD_INSERT_VLAN_TAG; 1816 } 1817 1818 i = 0; 1819 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1820 /* 1821 * Make sure the first fragment contains 1822 * only ethernet and IP/TCP header with options. 1823 */ 1824 hdrlen = poff + (tcp->th_off << 2); 1825 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1826 desc->addr = htole64(txsegs[i].ds_addr); 1827 desc->len = htole32(ALE_TX_BYTES(hdrlen) | vtag); 1828 desc->flags = htole32(cflags); 1829 sc->ale_cdata.ale_tx_cnt++; 1830 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1831 if (m->m_len - hdrlen > 0) { 1832 /* Handle remaining payload of the first fragment. */ 1833 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1834 desc->addr = htole64(txsegs[i].ds_addr + hdrlen); 1835 desc->len = htole32(ALE_TX_BYTES(m->m_len - hdrlen) | 1836 vtag); 1837 desc->flags = htole32(cflags); 1838 sc->ale_cdata.ale_tx_cnt++; 1839 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1840 } 1841 i = 1; 1842 } 1843 for (; i < nsegs; i++) { 1844 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1845 desc->addr = htole64(txsegs[i].ds_addr); 1846 desc->len = htole32(ALE_TX_BYTES(txsegs[i].ds_len) | vtag); 1847 desc->flags = htole32(cflags); 1848 sc->ale_cdata.ale_tx_cnt++; 1849 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1850 } 1851 /* Update producer index. */ 1852 sc->ale_cdata.ale_tx_prod = prod; 1853 /* Set TSO header on the first descriptor. */ 1854 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1855 desc = &sc->ale_cdata.ale_tx_ring[si]; 1856 desc->flags |= htole32(ALE_TD_TSO_HDR); 1857 } 1858 1859 /* Finally set EOP on the last descriptor. */ 1860 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; 1861 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1862 desc->flags |= htole32(ALE_TD_EOP); 1863 1864 /* Swap dmamap of the first and the last. */ 1865 txd = &sc->ale_cdata.ale_txdesc[prod]; 1866 map = txd_last->tx_dmamap; 1867 txd_last->tx_dmamap = txd->tx_dmamap; 1868 txd->tx_dmamap = map; 1869 txd->tx_m = m; 1870 1871 /* Sync descriptors. */ 1872 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 1873 sc->ale_cdata.ale_tx_ring_map, 1874 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1875 1876 return (0); 1877 } 1878 1879 static void 1880 ale_start(struct ifnet *ifp) 1881 { 1882 struct ale_softc *sc; 1883 1884 sc = ifp->if_softc; 1885 ALE_LOCK(sc); 1886 ale_start_locked(ifp); 1887 ALE_UNLOCK(sc); 1888 } 1889 1890 static void 1891 ale_start_locked(struct ifnet *ifp) 1892 { 1893 struct ale_softc *sc; 1894 struct mbuf *m_head; 1895 int enq; 1896 1897 sc = ifp->if_softc; 1898 1899 ALE_LOCK_ASSERT(sc); 1900 1901 /* Reclaim transmitted frames. */ 1902 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) 1903 ale_txeof(sc); 1904 1905 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1906 IFF_DRV_RUNNING || (sc->ale_flags & ALE_FLAG_LINK) == 0) 1907 return; 1908 1909 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1910 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1911 if (m_head == NULL) 1912 break; 1913 /* 1914 * Pack the data into the transmit ring. If we 1915 * don't have room, set the OACTIVE flag and wait 1916 * for the NIC to drain the ring. 1917 */ 1918 if (ale_encap(sc, &m_head)) { 1919 if (m_head == NULL) 1920 break; 1921 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1922 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1923 break; 1924 } 1925 1926 enq++; 1927 /* 1928 * If there's a BPF listener, bounce a copy of this frame 1929 * to him. 1930 */ 1931 ETHER_BPF_MTAP(ifp, m_head); 1932 } 1933 1934 if (enq > 0) { 1935 /* Kick. */ 1936 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, 1937 sc->ale_cdata.ale_tx_prod); 1938 /* Set a timeout in case the chip goes out to lunch. */ 1939 sc->ale_watchdog_timer = ALE_TX_TIMEOUT; 1940 } 1941 } 1942 1943 static void 1944 ale_watchdog(struct ale_softc *sc) 1945 { 1946 struct ifnet *ifp; 1947 1948 ALE_LOCK_ASSERT(sc); 1949 1950 if (sc->ale_watchdog_timer == 0 || --sc->ale_watchdog_timer) 1951 return; 1952 1953 ifp = sc->ale_ifp; 1954 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1955 if_printf(sc->ale_ifp, "watchdog timeout (lost link)\n"); 1956 ifp->if_oerrors++; 1957 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1958 ale_init_locked(sc); 1959 return; 1960 } 1961 if_printf(sc->ale_ifp, "watchdog timeout -- resetting\n"); 1962 ifp->if_oerrors++; 1963 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1964 ale_init_locked(sc); 1965 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1966 ale_start_locked(ifp); 1967 } 1968 1969 static int 1970 ale_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1971 { 1972 struct ale_softc *sc; 1973 struct ifreq *ifr; 1974 struct mii_data *mii; 1975 int error, mask; 1976 1977 sc = ifp->if_softc; 1978 ifr = (struct ifreq *)data; 1979 error = 0; 1980 switch (cmd) { 1981 case SIOCSIFMTU: 1982 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALE_JUMBO_MTU || 1983 ((sc->ale_flags & ALE_FLAG_JUMBO) == 0 && 1984 ifr->ifr_mtu > ETHERMTU)) 1985 error = EINVAL; 1986 else if (ifp->if_mtu != ifr->ifr_mtu) { 1987 ALE_LOCK(sc); 1988 ifp->if_mtu = ifr->ifr_mtu; 1989 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1990 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1991 ale_init_locked(sc); 1992 } 1993 ALE_UNLOCK(sc); 1994 } 1995 break; 1996 case SIOCSIFFLAGS: 1997 ALE_LOCK(sc); 1998 if ((ifp->if_flags & IFF_UP) != 0) { 1999 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2000 if (((ifp->if_flags ^ sc->ale_if_flags) 2001 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2002 ale_rxfilter(sc); 2003 } else { 2004 ale_init_locked(sc); 2005 } 2006 } else { 2007 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2008 ale_stop(sc); 2009 } 2010 sc->ale_if_flags = ifp->if_flags; 2011 ALE_UNLOCK(sc); 2012 break; 2013 case SIOCADDMULTI: 2014 case SIOCDELMULTI: 2015 ALE_LOCK(sc); 2016 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2017 ale_rxfilter(sc); 2018 ALE_UNLOCK(sc); 2019 break; 2020 case SIOCSIFMEDIA: 2021 case SIOCGIFMEDIA: 2022 mii = device_get_softc(sc->ale_miibus); 2023 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2024 break; 2025 case SIOCSIFCAP: 2026 ALE_LOCK(sc); 2027 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2028 if ((mask & IFCAP_TXCSUM) != 0 && 2029 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2030 ifp->if_capenable ^= IFCAP_TXCSUM; 2031 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2032 ifp->if_hwassist |= ALE_CSUM_FEATURES; 2033 else 2034 ifp->if_hwassist &= ~ALE_CSUM_FEATURES; 2035 } 2036 if ((mask & IFCAP_RXCSUM) != 0 && 2037 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 2038 ifp->if_capenable ^= IFCAP_RXCSUM; 2039 if ((mask & IFCAP_TSO4) != 0 && 2040 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 2041 ifp->if_capenable ^= IFCAP_TSO4; 2042 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 2043 ifp->if_hwassist |= CSUM_TSO; 2044 else 2045 ifp->if_hwassist &= ~CSUM_TSO; 2046 } 2047 2048 if ((mask & IFCAP_WOL_MCAST) != 0 && 2049 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 2050 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2051 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2052 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2053 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2054 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2055 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 2056 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2057 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2058 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 2059 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2060 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2061 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2062 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2063 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 2064 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 2065 ale_rxvlan(sc); 2066 } 2067 ALE_UNLOCK(sc); 2068 VLAN_CAPABILITIES(ifp); 2069 break; 2070 default: 2071 error = ether_ioctl(ifp, cmd, data); 2072 break; 2073 } 2074 2075 return (error); 2076 } 2077 2078 static void 2079 ale_mac_config(struct ale_softc *sc) 2080 { 2081 struct mii_data *mii; 2082 uint32_t reg; 2083 2084 ALE_LOCK_ASSERT(sc); 2085 2086 mii = device_get_softc(sc->ale_miibus); 2087 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2088 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2089 MAC_CFG_SPEED_MASK); 2090 /* Reprogram MAC with resolved speed/duplex. */ 2091 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2092 case IFM_10_T: 2093 case IFM_100_TX: 2094 reg |= MAC_CFG_SPEED_10_100; 2095 break; 2096 case IFM_1000_T: 2097 reg |= MAC_CFG_SPEED_1000; 2098 break; 2099 } 2100 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2101 reg |= MAC_CFG_FULL_DUPLEX; 2102 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2103 reg |= MAC_CFG_TX_FC; 2104 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2105 reg |= MAC_CFG_RX_FC; 2106 } 2107 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2108 } 2109 2110 static void 2111 ale_stats_clear(struct ale_softc *sc) 2112 { 2113 struct smb sb; 2114 uint32_t *reg; 2115 int i; 2116 2117 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2118 CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2119 i += sizeof(uint32_t); 2120 } 2121 /* Read Tx statistics. */ 2122 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2123 CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2124 i += sizeof(uint32_t); 2125 } 2126 } 2127 2128 static void 2129 ale_stats_update(struct ale_softc *sc) 2130 { 2131 struct ale_hw_stats *stat; 2132 struct smb sb, *smb; 2133 struct ifnet *ifp; 2134 uint32_t *reg; 2135 int i; 2136 2137 ALE_LOCK_ASSERT(sc); 2138 2139 ifp = sc->ale_ifp; 2140 stat = &sc->ale_stats; 2141 smb = &sb; 2142 2143 /* Read Rx statistics. */ 2144 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2145 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2146 i += sizeof(uint32_t); 2147 } 2148 /* Read Tx statistics. */ 2149 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2150 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2151 i += sizeof(uint32_t); 2152 } 2153 2154 /* Rx stats. */ 2155 stat->rx_frames += smb->rx_frames; 2156 stat->rx_bcast_frames += smb->rx_bcast_frames; 2157 stat->rx_mcast_frames += smb->rx_mcast_frames; 2158 stat->rx_pause_frames += smb->rx_pause_frames; 2159 stat->rx_control_frames += smb->rx_control_frames; 2160 stat->rx_crcerrs += smb->rx_crcerrs; 2161 stat->rx_lenerrs += smb->rx_lenerrs; 2162 stat->rx_bytes += smb->rx_bytes; 2163 stat->rx_runts += smb->rx_runts; 2164 stat->rx_fragments += smb->rx_fragments; 2165 stat->rx_pkts_64 += smb->rx_pkts_64; 2166 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2167 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2168 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2169 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2170 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2171 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2172 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2173 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2174 stat->rx_rrs_errs += smb->rx_rrs_errs; 2175 stat->rx_alignerrs += smb->rx_alignerrs; 2176 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2177 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2178 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2179 2180 /* Tx stats. */ 2181 stat->tx_frames += smb->tx_frames; 2182 stat->tx_bcast_frames += smb->tx_bcast_frames; 2183 stat->tx_mcast_frames += smb->tx_mcast_frames; 2184 stat->tx_pause_frames += smb->tx_pause_frames; 2185 stat->tx_excess_defer += smb->tx_excess_defer; 2186 stat->tx_control_frames += smb->tx_control_frames; 2187 stat->tx_deferred += smb->tx_deferred; 2188 stat->tx_bytes += smb->tx_bytes; 2189 stat->tx_pkts_64 += smb->tx_pkts_64; 2190 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2191 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2192 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2193 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2194 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2195 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2196 stat->tx_single_colls += smb->tx_single_colls; 2197 stat->tx_multi_colls += smb->tx_multi_colls; 2198 stat->tx_late_colls += smb->tx_late_colls; 2199 stat->tx_excess_colls += smb->tx_excess_colls; 2200 stat->tx_abort += smb->tx_abort; 2201 stat->tx_underrun += smb->tx_underrun; 2202 stat->tx_desc_underrun += smb->tx_desc_underrun; 2203 stat->tx_lenerrs += smb->tx_lenerrs; 2204 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2205 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2206 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2207 2208 /* Update counters in ifnet. */ 2209 ifp->if_opackets += smb->tx_frames; 2210 2211 ifp->if_collisions += smb->tx_single_colls + 2212 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2213 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 2214 2215 /* 2216 * XXX 2217 * tx_pkts_truncated counter looks suspicious. It constantly 2218 * increments with no sign of Tx errors. This may indicate 2219 * the counter name is not correct one so I've removed the 2220 * counter in output errors. 2221 */ 2222 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 2223 smb->tx_underrun; 2224 2225 ifp->if_ipackets += smb->rx_frames; 2226 2227 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2228 smb->rx_runts + smb->rx_pkts_truncated + 2229 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2230 smb->rx_alignerrs; 2231 } 2232 2233 static int 2234 ale_intr(void *arg) 2235 { 2236 struct ale_softc *sc; 2237 uint32_t status; 2238 2239 sc = (struct ale_softc *)arg; 2240 2241 status = CSR_READ_4(sc, ALE_INTR_STATUS); 2242 if ((status & ALE_INTRS) == 0) 2243 return (FILTER_STRAY); 2244 /* Disable interrupts. */ 2245 CSR_WRITE_4(sc, ALE_INTR_STATUS, INTR_DIS_INT); 2246 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2247 2248 return (FILTER_HANDLED); 2249 } 2250 2251 static void 2252 ale_int_task(void *arg, int pending) 2253 { 2254 struct ale_softc *sc; 2255 struct ifnet *ifp; 2256 uint32_t status; 2257 int more; 2258 2259 sc = (struct ale_softc *)arg; 2260 2261 status = CSR_READ_4(sc, ALE_INTR_STATUS); 2262 ALE_LOCK(sc); 2263 if (sc->ale_morework != 0) 2264 status |= INTR_RX_PKT; 2265 if ((status & ALE_INTRS) == 0) 2266 goto done; 2267 2268 /* Acknowledge interrupts but still disable interrupts. */ 2269 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); 2270 2271 ifp = sc->ale_ifp; 2272 more = 0; 2273 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2274 more = ale_rxeof(sc, sc->ale_process_limit); 2275 if (more == EAGAIN) 2276 sc->ale_morework = 1; 2277 else if (more == EIO) { 2278 sc->ale_stats.reset_brk_seq++; 2279 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2280 ale_init_locked(sc); 2281 ALE_UNLOCK(sc); 2282 return; 2283 } 2284 2285 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 2286 if ((status & INTR_DMA_RD_TO_RST) != 0) 2287 device_printf(sc->ale_dev, 2288 "DMA read error! -- resetting\n"); 2289 if ((status & INTR_DMA_WR_TO_RST) != 0) 2290 device_printf(sc->ale_dev, 2291 "DMA write error! -- resetting\n"); 2292 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2293 ale_init_locked(sc); 2294 ALE_UNLOCK(sc); 2295 return; 2296 } 2297 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2298 ale_start_locked(ifp); 2299 } 2300 2301 if (more == EAGAIN || 2302 (CSR_READ_4(sc, ALE_INTR_STATUS) & ALE_INTRS) != 0) { 2303 ALE_UNLOCK(sc); 2304 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2305 return; 2306 } 2307 2308 done: 2309 ALE_UNLOCK(sc); 2310 2311 /* Re-enable interrupts. */ 2312 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); 2313 } 2314 2315 static void 2316 ale_txeof(struct ale_softc *sc) 2317 { 2318 struct ifnet *ifp; 2319 struct ale_txdesc *txd; 2320 uint32_t cons, prod; 2321 int prog; 2322 2323 ALE_LOCK_ASSERT(sc); 2324 2325 ifp = sc->ale_ifp; 2326 2327 if (sc->ale_cdata.ale_tx_cnt == 0) 2328 return; 2329 2330 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2331 sc->ale_cdata.ale_tx_ring_map, 2332 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2333 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { 2334 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2335 sc->ale_cdata.ale_tx_cmb_map, 2336 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2337 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; 2338 } else 2339 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); 2340 cons = sc->ale_cdata.ale_tx_cons; 2341 /* 2342 * Go through our Tx list and free mbufs for those 2343 * frames which have been transmitted. 2344 */ 2345 for (prog = 0; cons != prod; prog++, 2346 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { 2347 if (sc->ale_cdata.ale_tx_cnt <= 0) 2348 break; 2349 prog++; 2350 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2351 sc->ale_cdata.ale_tx_cnt--; 2352 txd = &sc->ale_cdata.ale_txdesc[cons]; 2353 if (txd->tx_m != NULL) { 2354 /* Reclaim transmitted mbufs. */ 2355 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2356 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2357 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2358 txd->tx_dmamap); 2359 m_freem(txd->tx_m); 2360 txd->tx_m = NULL; 2361 } 2362 } 2363 2364 if (prog > 0) { 2365 sc->ale_cdata.ale_tx_cons = cons; 2366 /* 2367 * Unarm watchdog timer only when there is no pending 2368 * Tx descriptors in queue. 2369 */ 2370 if (sc->ale_cdata.ale_tx_cnt == 0) 2371 sc->ale_watchdog_timer = 0; 2372 } 2373 } 2374 2375 static void 2376 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, 2377 uint32_t length, uint32_t *prod) 2378 { 2379 struct ale_rx_page *rx_page; 2380 2381 rx_page = *page; 2382 /* Update consumer position. */ 2383 rx_page->cons += roundup(length + sizeof(struct rx_rs), 2384 ALE_RX_PAGE_ALIGN); 2385 if (rx_page->cons >= ALE_RX_PAGE_SZ) { 2386 /* 2387 * End of Rx page reached, let hardware reuse 2388 * this page. 2389 */ 2390 rx_page->cons = 0; 2391 *rx_page->cmb_addr = 0; 2392 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2393 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2394 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, 2395 RXF_VALID); 2396 /* Switch to alternate Rx page. */ 2397 sc->ale_cdata.ale_rx_curp ^= 1; 2398 rx_page = *page = 2399 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2400 /* Page flipped, sync CMB and Rx page. */ 2401 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2402 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2403 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2404 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2405 /* Sync completed, cache updated producer index. */ 2406 *prod = *rx_page->cmb_addr; 2407 } 2408 } 2409 2410 2411 /* 2412 * It seems that AR81xx controller can compute partial checksum. 2413 * The partial checksum value can be used to accelerate checksum 2414 * computation for fragmented TCP/UDP packets. Upper network stack 2415 * already takes advantage of the partial checksum value in IP 2416 * reassembly stage. But I'm not sure the correctness of the 2417 * partial hardware checksum assistance due to lack of data sheet. 2418 * In addition, the Rx feature of controller that requires copying 2419 * for every frames effectively nullifies one of most nice offload 2420 * capability of controller. 2421 */ 2422 static void 2423 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) 2424 { 2425 struct ifnet *ifp; 2426 struct ip *ip; 2427 char *p; 2428 2429 ifp = sc->ale_ifp; 2430 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2431 if ((status & ALE_RD_IPCSUM_NOK) == 0) 2432 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2433 2434 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { 2435 if (((status & ALE_RD_IPV4_FRAG) == 0) && 2436 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && 2437 ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) { 2438 m->m_pkthdr.csum_flags |= 2439 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2440 m->m_pkthdr.csum_data = 0xffff; 2441 } 2442 } else { 2443 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 && 2444 (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) { 2445 p = mtod(m, char *); 2446 p += ETHER_HDR_LEN; 2447 if ((status & ALE_RD_802_3) != 0) 2448 p += LLC_SNAPFRAMELEN; 2449 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0 && 2450 (status & ALE_RD_VLAN) != 0) 2451 p += ETHER_VLAN_ENCAP_LEN; 2452 ip = (struct ip *)p; 2453 if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0) 2454 return; 2455 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 2456 CSUM_PSEUDO_HDR; 2457 m->m_pkthdr.csum_data = 0xffff; 2458 } 2459 } 2460 /* 2461 * Don't mark bad checksum for TCP/UDP frames 2462 * as fragmented frames may always have set 2463 * bad checksummed bit of frame status. 2464 */ 2465 } 2466 2467 /* Process received frames. */ 2468 static int 2469 ale_rxeof(struct ale_softc *sc, int count) 2470 { 2471 struct ale_rx_page *rx_page; 2472 struct rx_rs *rs; 2473 struct ifnet *ifp; 2474 struct mbuf *m; 2475 uint32_t length, prod, seqno, status, vtags; 2476 int prog; 2477 2478 ifp = sc->ale_ifp; 2479 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2480 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2481 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2482 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2483 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2484 /* 2485 * Don't directly access producer index as hardware may 2486 * update it while Rx handler is in progress. It would 2487 * be even better if there is a way to let hardware 2488 * know how far driver processed its received frames. 2489 * Alternatively, hardware could provide a way to disable 2490 * CMB updates until driver acknowledges the end of CMB 2491 * access. 2492 */ 2493 prod = *rx_page->cmb_addr; 2494 for (prog = 0; prog < count; prog++) { 2495 if (rx_page->cons >= prod) 2496 break; 2497 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); 2498 seqno = ALE_RX_SEQNO(le32toh(rs->seqno)); 2499 if (sc->ale_cdata.ale_rx_seqno != seqno) { 2500 /* 2501 * Normally I believe this should not happen unless 2502 * severe driver bug or corrupted memory. However 2503 * it seems to happen under certain conditions which 2504 * is triggered by abrupt Rx events such as initiation 2505 * of bulk transfer of remote host. It's not easy to 2506 * reproduce this and I doubt it could be related 2507 * with FIFO overflow of hardware or activity of Tx 2508 * CMB updates. I also remember similar behaviour 2509 * seen on RealTek 8139 which uses resembling Rx 2510 * scheme. 2511 */ 2512 if (bootverbose) 2513 device_printf(sc->ale_dev, 2514 "garbled seq: %u, expected: %u -- " 2515 "resetting!\n", seqno, 2516 sc->ale_cdata.ale_rx_seqno); 2517 return (EIO); 2518 } 2519 /* Frame received. */ 2520 sc->ale_cdata.ale_rx_seqno++; 2521 length = ALE_RX_BYTES(le32toh(rs->length)); 2522 status = le32toh(rs->flags); 2523 if ((status & ALE_RD_ERROR) != 0) { 2524 /* 2525 * We want to pass the following frames to upper 2526 * layer regardless of error status of Rx return 2527 * status. 2528 * 2529 * o IP/TCP/UDP checksum is bad. 2530 * o frame length and protocol specific length 2531 * does not match. 2532 */ 2533 if ((status & (ALE_RD_CRC | ALE_RD_CODE | 2534 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | 2535 ALE_RD_TRUNC)) != 0) { 2536 ale_rx_update_page(sc, &rx_page, length, &prod); 2537 continue; 2538 } 2539 } 2540 /* 2541 * m_devget(9) is major bottle-neck of ale(4)(It comes 2542 * from hardware limitation). For jumbo frames we could 2543 * get a slightly better performance if driver use 2544 * m_getjcl(9) with proper buffer size argument. However 2545 * that would make code more complicated and I don't 2546 * think users would expect good Rx performance numbers 2547 * on these low-end consumer ethernet controller. 2548 */ 2549 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, 2550 ETHER_ALIGN, ifp, NULL); 2551 if (m == NULL) { 2552 ifp->if_iqdrops++; 2553 ale_rx_update_page(sc, &rx_page, length, &prod); 2554 continue; 2555 } 2556 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 2557 (status & ALE_RD_IPV4) != 0) 2558 ale_rxcsum(sc, m, status); 2559 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 2560 (status & ALE_RD_VLAN) != 0) { 2561 vtags = ALE_RX_VLAN(le32toh(rs->vtags)); 2562 m->m_pkthdr.ether_vtag = ALE_RX_VLAN_TAG(vtags); 2563 m->m_flags |= M_VLANTAG; 2564 } 2565 2566 /* Pass it to upper layer. */ 2567 ALE_UNLOCK(sc); 2568 (*ifp->if_input)(ifp, m); 2569 ALE_LOCK(sc); 2570 2571 ale_rx_update_page(sc, &rx_page, length, &prod); 2572 } 2573 2574 return (count > 0 ? 0 : EAGAIN); 2575 } 2576 2577 static void 2578 ale_tick(void *arg) 2579 { 2580 struct ale_softc *sc; 2581 struct mii_data *mii; 2582 2583 sc = (struct ale_softc *)arg; 2584 2585 ALE_LOCK_ASSERT(sc); 2586 2587 mii = device_get_softc(sc->ale_miibus); 2588 mii_tick(mii); 2589 ale_stats_update(sc); 2590 /* 2591 * Reclaim Tx buffers that have been transferred. It's not 2592 * needed here but it would release allocated mbuf chains 2593 * faster and limit the maximum delay to a hz. 2594 */ 2595 ale_txeof(sc); 2596 ale_watchdog(sc); 2597 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2598 } 2599 2600 static void 2601 ale_reset(struct ale_softc *sc) 2602 { 2603 uint32_t reg; 2604 int i; 2605 2606 /* Initialize PCIe module. From Linux. */ 2607 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2608 2609 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); 2610 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2611 DELAY(10); 2612 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) 2613 break; 2614 } 2615 if (i == 0) 2616 device_printf(sc->ale_dev, "master reset timeout!\n"); 2617 2618 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2619 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) 2620 break; 2621 DELAY(10); 2622 } 2623 2624 if (i == 0) 2625 device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg); 2626 } 2627 2628 static void 2629 ale_init(void *xsc) 2630 { 2631 struct ale_softc *sc; 2632 2633 sc = (struct ale_softc *)xsc; 2634 ALE_LOCK(sc); 2635 ale_init_locked(sc); 2636 ALE_UNLOCK(sc); 2637 } 2638 2639 static void 2640 ale_init_locked(struct ale_softc *sc) 2641 { 2642 struct ifnet *ifp; 2643 struct mii_data *mii; 2644 uint8_t eaddr[ETHER_ADDR_LEN]; 2645 bus_addr_t paddr; 2646 uint32_t reg, rxf_hi, rxf_lo; 2647 2648 ALE_LOCK_ASSERT(sc); 2649 2650 ifp = sc->ale_ifp; 2651 mii = device_get_softc(sc->ale_miibus); 2652 2653 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2654 return; 2655 /* 2656 * Cancel any pending I/O. 2657 */ 2658 ale_stop(sc); 2659 /* 2660 * Reset the chip to a known state. 2661 */ 2662 ale_reset(sc); 2663 /* Initialize Tx descriptors, DMA memory blocks. */ 2664 ale_init_rx_pages(sc); 2665 ale_init_tx_ring(sc); 2666 2667 /* Reprogram the station address. */ 2668 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2669 CSR_WRITE_4(sc, ALE_PAR0, 2670 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2671 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); 2672 /* 2673 * Clear WOL status and disable all WOL feature as WOL 2674 * would interfere Rx operation under normal environments. 2675 */ 2676 CSR_READ_4(sc, ALE_WOL_CFG); 2677 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 2678 /* 2679 * Set Tx descriptor/RXF0/CMB base addresses. They share 2680 * the same high address part of DMAable region. 2681 */ 2682 paddr = sc->ale_cdata.ale_tx_ring_paddr; 2683 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); 2684 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); 2685 CSR_WRITE_4(sc, ALE_TPD_CNT, 2686 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); 2687 /* Set Rx page base address, note we use single queue. */ 2688 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; 2689 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); 2690 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; 2691 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); 2692 /* Set Tx/Rx CMB addresses. */ 2693 paddr = sc->ale_cdata.ale_tx_cmb_paddr; 2694 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); 2695 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; 2696 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); 2697 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; 2698 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); 2699 /* Mark RXF0 is valid. */ 2700 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); 2701 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); 2702 /* 2703 * No need to initialize RFX1/RXF2/RXF3. We don't use 2704 * multi-queue yet. 2705 */ 2706 2707 /* Set Rx page size, excluding guard frame size. */ 2708 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); 2709 /* Tell hardware that we're ready to load DMA blocks. */ 2710 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); 2711 2712 /* Set Rx/Tx interrupt trigger threshold. */ 2713 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | 2714 (4 << INT_TRIG_TX_THRESH_SHIFT)); 2715 /* 2716 * XXX 2717 * Set interrupt trigger timer, its purpose and relation 2718 * with interrupt moderation mechanism is not clear yet. 2719 */ 2720 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, 2721 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | 2722 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); 2723 2724 /* Configure interrupt moderation timer. */ 2725 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; 2726 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; 2727 CSR_WRITE_4(sc, ALE_IM_TIMER, reg); 2728 reg = CSR_READ_4(sc, ALE_MASTER_CFG); 2729 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 2730 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 2731 if (ALE_USECS(sc->ale_int_rx_mod) != 0) 2732 reg |= MASTER_IM_RX_TIMER_ENB; 2733 if (ALE_USECS(sc->ale_int_tx_mod) != 0) 2734 reg |= MASTER_IM_TX_TIMER_ENB; 2735 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); 2736 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); 2737 2738 /* Set Maximum frame size of controller. */ 2739 if (ifp->if_mtu < ETHERMTU) 2740 sc->ale_max_frame_size = ETHERMTU; 2741 else 2742 sc->ale_max_frame_size = ifp->if_mtu; 2743 sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 2744 ETHER_CRC_LEN; 2745 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); 2746 /* Configure IPG/IFG parameters. */ 2747 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, 2748 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 2749 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2750 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2751 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 2752 /* Set parameters for half-duplex media. */ 2753 CSR_WRITE_4(sc, ALE_HDPX_CFG, 2754 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2755 HDPX_CFG_LCOL_MASK) | 2756 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2757 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2758 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2759 HDPX_CFG_ABEBT_MASK) | 2760 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2761 HDPX_CFG_JAMIPG_MASK)); 2762 2763 /* Configure Tx jumbo frame parameters. */ 2764 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2765 if (ifp->if_mtu < ETHERMTU) 2766 reg = sc->ale_max_frame_size; 2767 else if (ifp->if_mtu < 6 * 1024) 2768 reg = (sc->ale_max_frame_size * 2) / 3; 2769 else 2770 reg = sc->ale_max_frame_size / 2; 2771 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, 2772 roundup(reg, TX_JUMBO_THRESH_UNIT) >> 2773 TX_JUMBO_THRESH_UNIT_SHIFT); 2774 } 2775 /* Configure TxQ. */ 2776 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) 2777 << TXQ_CFG_TX_FIFO_BURST_SHIFT; 2778 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2779 TXQ_CFG_TPD_BURST_MASK; 2780 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); 2781 2782 /* Configure Rx jumbo frame & flow control parameters. */ 2783 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2784 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); 2785 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, 2786 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << 2787 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | 2788 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & 2789 RX_JUMBO_LKAH_MASK)); 2790 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 2791 rxf_hi = (reg * 7) / 10; 2792 rxf_lo = (reg * 3)/ 10; 2793 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, 2794 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2795 RX_FIFO_PAUSE_THRESH_LO_MASK) | 2796 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2797 RX_FIFO_PAUSE_THRESH_HI_MASK)); 2798 } 2799 2800 /* Disable RSS. */ 2801 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); 2802 CSR_WRITE_4(sc, ALE_RSS_CPU, 0); 2803 2804 /* Configure RxQ. */ 2805 CSR_WRITE_4(sc, ALE_RXQ_CFG, 2806 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2807 2808 /* Configure DMA parameters. */ 2809 reg = 0; 2810 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) 2811 reg |= DMA_CFG_TXCMB_ENB; 2812 CSR_WRITE_4(sc, ALE_DMA_CFG, 2813 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | 2814 sc->ale_dma_rd_burst | reg | 2815 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | 2816 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 2817 DMA_CFG_RD_DELAY_CNT_MASK) | 2818 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 2819 DMA_CFG_WR_DELAY_CNT_MASK)); 2820 2821 /* 2822 * Hardware can be configured to issue SMB interrupt based 2823 * on programmed interval. Since there is a callout that is 2824 * invoked for every hz in driver we use that instead of 2825 * relying on periodic SMB interrupt. 2826 */ 2827 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); 2828 /* Clear MAC statistics. */ 2829 ale_stats_clear(sc); 2830 2831 /* 2832 * Configure Tx/Rx MACs. 2833 * - Auto-padding for short frames. 2834 * - Enable CRC generation. 2835 * Actual reconfiguration of MAC for resolved speed/duplex 2836 * is followed after detection of link establishment. 2837 * AR81xx always does checksum computation regardless of 2838 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will 2839 * cause Rx handling issue for fragmented IP datagrams due 2840 * to silicon bug. 2841 */ 2842 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 2843 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2844 MAC_CFG_PREAMBLE_MASK); 2845 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) 2846 reg |= MAC_CFG_SPEED_10_100; 2847 else 2848 reg |= MAC_CFG_SPEED_1000; 2849 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2850 2851 /* Set up the receive filter. */ 2852 ale_rxfilter(sc); 2853 ale_rxvlan(sc); 2854 2855 /* Acknowledge all pending interrupts and clear it. */ 2856 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); 2857 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2858 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); 2859 2860 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2861 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2862 2863 sc->ale_flags &= ~ALE_FLAG_LINK; 2864 /* Switch to the current media. */ 2865 mii_mediachg(mii); 2866 2867 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2868 } 2869 2870 static void 2871 ale_stop(struct ale_softc *sc) 2872 { 2873 struct ifnet *ifp; 2874 struct ale_txdesc *txd; 2875 uint32_t reg; 2876 int i; 2877 2878 ALE_LOCK_ASSERT(sc); 2879 /* 2880 * Mark the interface down and cancel the watchdog timer. 2881 */ 2882 ifp = sc->ale_ifp; 2883 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2884 sc->ale_flags &= ~ALE_FLAG_LINK; 2885 callout_stop(&sc->ale_tick_ch); 2886 sc->ale_watchdog_timer = 0; 2887 ale_stats_update(sc); 2888 /* Disable interrupts. */ 2889 CSR_WRITE_4(sc, ALE_INTR_MASK, 0); 2890 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2891 /* Disable queue processing and DMA. */ 2892 reg = CSR_READ_4(sc, ALE_TXQ_CFG); 2893 reg &= ~TXQ_CFG_ENB; 2894 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); 2895 reg = CSR_READ_4(sc, ALE_RXQ_CFG); 2896 reg &= ~RXQ_CFG_ENB; 2897 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); 2898 reg = CSR_READ_4(sc, ALE_DMA_CFG); 2899 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); 2900 CSR_WRITE_4(sc, ALE_DMA_CFG, reg); 2901 DELAY(1000); 2902 /* Stop Rx/Tx MACs. */ 2903 ale_stop_mac(sc); 2904 /* Disable interrupts which might be touched in taskq handler. */ 2905 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2906 2907 /* 2908 * Free TX mbufs still in the queues. 2909 */ 2910 for (i = 0; i < ALE_TX_RING_CNT; i++) { 2911 txd = &sc->ale_cdata.ale_txdesc[i]; 2912 if (txd->tx_m != NULL) { 2913 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2914 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2915 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2916 txd->tx_dmamap); 2917 m_freem(txd->tx_m); 2918 txd->tx_m = NULL; 2919 } 2920 } 2921 } 2922 2923 static void 2924 ale_stop_mac(struct ale_softc *sc) 2925 { 2926 uint32_t reg; 2927 int i; 2928 2929 ALE_LOCK_ASSERT(sc); 2930 2931 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2932 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 2933 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 2934 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2935 } 2936 2937 for (i = ALE_TIMEOUT; i > 0; i--) { 2938 reg = CSR_READ_4(sc, ALE_IDLE_STATUS); 2939 if (reg == 0) 2940 break; 2941 DELAY(10); 2942 } 2943 if (i == 0) 2944 device_printf(sc->ale_dev, 2945 "could not disable Tx/Rx MAC(0x%08x)!\n", reg); 2946 } 2947 2948 static void 2949 ale_init_tx_ring(struct ale_softc *sc) 2950 { 2951 struct ale_txdesc *txd; 2952 int i; 2953 2954 ALE_LOCK_ASSERT(sc); 2955 2956 sc->ale_cdata.ale_tx_prod = 0; 2957 sc->ale_cdata.ale_tx_cons = 0; 2958 sc->ale_cdata.ale_tx_cnt = 0; 2959 2960 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ); 2961 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ); 2962 for (i = 0; i < ALE_TX_RING_CNT; i++) { 2963 txd = &sc->ale_cdata.ale_txdesc[i]; 2964 txd->tx_m = NULL; 2965 } 2966 *sc->ale_cdata.ale_tx_cmb = 0; 2967 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2968 sc->ale_cdata.ale_tx_cmb_map, 2969 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2970 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2971 sc->ale_cdata.ale_tx_ring_map, 2972 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2973 } 2974 2975 static void 2976 ale_init_rx_pages(struct ale_softc *sc) 2977 { 2978 struct ale_rx_page *rx_page; 2979 int i; 2980 2981 ALE_LOCK_ASSERT(sc); 2982 2983 sc->ale_morework = 0; 2984 sc->ale_cdata.ale_rx_seqno = 0; 2985 sc->ale_cdata.ale_rx_curp = 0; 2986 2987 for (i = 0; i < ALE_RX_PAGES; i++) { 2988 rx_page = &sc->ale_cdata.ale_rx_page[i]; 2989 bzero(rx_page->page_addr, sc->ale_pagesize); 2990 bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ); 2991 rx_page->cons = 0; 2992 *rx_page->cmb_addr = 0; 2993 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2994 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2995 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2996 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2997 } 2998 } 2999 3000 static void 3001 ale_rxvlan(struct ale_softc *sc) 3002 { 3003 struct ifnet *ifp; 3004 uint32_t reg; 3005 3006 ALE_LOCK_ASSERT(sc); 3007 3008 ifp = sc->ale_ifp; 3009 reg = CSR_READ_4(sc, ALE_MAC_CFG); 3010 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3011 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3012 reg |= MAC_CFG_VLAN_TAG_STRIP; 3013 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 3014 } 3015 3016 static void 3017 ale_rxfilter(struct ale_softc *sc) 3018 { 3019 struct ifnet *ifp; 3020 struct ifmultiaddr *ifma; 3021 uint32_t crc; 3022 uint32_t mchash[2]; 3023 uint32_t rxcfg; 3024 3025 ALE_LOCK_ASSERT(sc); 3026 3027 ifp = sc->ale_ifp; 3028 3029 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); 3030 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3031 if ((ifp->if_flags & IFF_BROADCAST) != 0) 3032 rxcfg |= MAC_CFG_BCAST; 3033 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3034 if ((ifp->if_flags & IFF_PROMISC) != 0) 3035 rxcfg |= MAC_CFG_PROMISC; 3036 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3037 rxcfg |= MAC_CFG_ALLMULTI; 3038 CSR_WRITE_4(sc, ALE_MAR0, 0xFFFFFFFF); 3039 CSR_WRITE_4(sc, ALE_MAR1, 0xFFFFFFFF); 3040 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3041 return; 3042 } 3043 3044 /* Program new filter. */ 3045 bzero(mchash, sizeof(mchash)); 3046 3047 if_maddr_rlock(ifp); 3048 TAILQ_FOREACH(ifma, &sc->ale_ifp->if_multiaddrs, ifma_link) { 3049 if (ifma->ifma_addr->sa_family != AF_LINK) 3050 continue; 3051 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3052 ifma->ifma_addr), ETHER_ADDR_LEN); 3053 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3054 } 3055 if_maddr_runlock(ifp); 3056 3057 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); 3058 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); 3059 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3060 } 3061 3062 static int 3063 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3064 { 3065 int error, value; 3066 3067 if (arg1 == NULL) 3068 return (EINVAL); 3069 value = *(int *)arg1; 3070 error = sysctl_handle_int(oidp, &value, 0, req); 3071 if (error || req->newptr == NULL) 3072 return (error); 3073 if (value < low || value > high) 3074 return (EINVAL); 3075 *(int *)arg1 = value; 3076 3077 return (0); 3078 } 3079 3080 static int 3081 sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS) 3082 { 3083 return (sysctl_int_range(oidp, arg1, arg2, req, 3084 ALE_PROC_MIN, ALE_PROC_MAX)); 3085 } 3086 3087 static int 3088 sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS) 3089 { 3090 3091 return (sysctl_int_range(oidp, arg1, arg2, req, 3092 ALE_IM_TIMER_MIN, ALE_IM_TIMER_MAX)); 3093 } 3094