xref: /freebsd/sys/dev/ale/if_ale.c (revision 8ddb146abcdf061be9f2c0db7e391697dafad85c)
1 /*-
2  * SPDX-License-Identifier: BSD-2-Clause-FreeBSD
3  *
4  * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice unmodified, this list of conditions, and the following
12  *    disclaimer.
13  * 2. Redistributions in binary form must reproduce the above copyright
14  *    notice, this list of conditions and the following disclaimer in the
15  *    documentation and/or other materials provided with the distribution.
16  *
17  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
27  * SUCH DAMAGE.
28  */
29 
30 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */
31 
32 #include <sys/cdefs.h>
33 __FBSDID("$FreeBSD$");
34 
35 #include <sys/param.h>
36 #include <sys/systm.h>
37 #include <sys/bus.h>
38 #include <sys/endian.h>
39 #include <sys/kernel.h>
40 #include <sys/malloc.h>
41 #include <sys/mbuf.h>
42 #include <sys/module.h>
43 #include <sys/rman.h>
44 #include <sys/queue.h>
45 #include <sys/socket.h>
46 #include <sys/sockio.h>
47 #include <sys/sysctl.h>
48 #include <sys/taskqueue.h>
49 
50 #include <net/bpf.h>
51 #include <net/if.h>
52 #include <net/if_var.h>
53 #include <net/if_arp.h>
54 #include <net/ethernet.h>
55 #include <net/if_dl.h>
56 #include <net/if_llc.h>
57 #include <net/if_media.h>
58 #include <net/if_types.h>
59 #include <net/if_vlan_var.h>
60 
61 #include <netinet/in.h>
62 #include <netinet/in_systm.h>
63 #include <netinet/ip.h>
64 #include <netinet/tcp.h>
65 
66 #include <dev/mii/mii.h>
67 #include <dev/mii/miivar.h>
68 
69 #include <dev/pci/pcireg.h>
70 #include <dev/pci/pcivar.h>
71 
72 #include <machine/bus.h>
73 #include <machine/in_cksum.h>
74 
75 #include <dev/ale/if_alereg.h>
76 #include <dev/ale/if_alevar.h>
77 
78 /* "device miibus" required.  See GENERIC if you get errors here. */
79 #include "miibus_if.h"
80 
81 /* For more information about Tx checksum offload issues see ale_encap(). */
82 #define	ALE_CSUM_FEATURES	(CSUM_TCP | CSUM_UDP)
83 
84 MODULE_DEPEND(ale, pci, 1, 1, 1);
85 MODULE_DEPEND(ale, ether, 1, 1, 1);
86 MODULE_DEPEND(ale, miibus, 1, 1, 1);
87 
88 /* Tunables. */
89 static int msi_disable = 0;
90 static int msix_disable = 0;
91 TUNABLE_INT("hw.ale.msi_disable", &msi_disable);
92 TUNABLE_INT("hw.ale.msix_disable", &msix_disable);
93 
94 /*
95  * Devices supported by this driver.
96  */
97 static const struct ale_dev {
98 	uint16_t	ale_vendorid;
99 	uint16_t	ale_deviceid;
100 	const char	*ale_name;
101 } ale_devs[] = {
102     { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR81XX,
103     "Atheros AR8121/AR8113/AR8114 PCIe Ethernet" },
104 };
105 
106 static int	ale_attach(device_t);
107 static int	ale_check_boundary(struct ale_softc *);
108 static int	ale_detach(device_t);
109 static int	ale_dma_alloc(struct ale_softc *);
110 static void	ale_dma_free(struct ale_softc *);
111 static void	ale_dmamap_cb(void *, bus_dma_segment_t *, int, int);
112 static int	ale_encap(struct ale_softc *, struct mbuf **);
113 static void	ale_get_macaddr(struct ale_softc *);
114 static void	ale_init(void *);
115 static void	ale_init_locked(struct ale_softc *);
116 static void	ale_init_rx_pages(struct ale_softc *);
117 static void	ale_init_tx_ring(struct ale_softc *);
118 static void	ale_int_task(void *, int);
119 static int	ale_intr(void *);
120 static int	ale_ioctl(struct ifnet *, u_long, caddr_t);
121 static void	ale_mac_config(struct ale_softc *);
122 static int	ale_miibus_readreg(device_t, int, int);
123 static void	ale_miibus_statchg(device_t);
124 static int	ale_miibus_writereg(device_t, int, int, int);
125 static int	ale_mediachange(struct ifnet *);
126 static void	ale_mediastatus(struct ifnet *, struct ifmediareq *);
127 static void	ale_phy_reset(struct ale_softc *);
128 static int	ale_probe(device_t);
129 static void	ale_reset(struct ale_softc *);
130 static int	ale_resume(device_t);
131 static void	ale_rx_update_page(struct ale_softc *, struct ale_rx_page **,
132     uint32_t, uint32_t *);
133 static void	ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t);
134 static int	ale_rxeof(struct ale_softc *sc, int);
135 static void	ale_rxfilter(struct ale_softc *);
136 static void	ale_rxvlan(struct ale_softc *);
137 static void	ale_setlinkspeed(struct ale_softc *);
138 static void	ale_setwol(struct ale_softc *);
139 static int	ale_shutdown(device_t);
140 static void	ale_start(struct ifnet *);
141 static void	ale_start_locked(struct ifnet *);
142 static void	ale_stats_clear(struct ale_softc *);
143 static void	ale_stats_update(struct ale_softc *);
144 static void	ale_stop(struct ale_softc *);
145 static void	ale_stop_mac(struct ale_softc *);
146 static int	ale_suspend(device_t);
147 static void	ale_sysctl_node(struct ale_softc *);
148 static void	ale_tick(void *);
149 static void	ale_txeof(struct ale_softc *);
150 static void	ale_watchdog(struct ale_softc *);
151 static int	sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int);
152 static int	sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS);
153 static int	sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS);
154 
155 static device_method_t ale_methods[] = {
156 	/* Device interface. */
157 	DEVMETHOD(device_probe,		ale_probe),
158 	DEVMETHOD(device_attach,	ale_attach),
159 	DEVMETHOD(device_detach,	ale_detach),
160 	DEVMETHOD(device_shutdown,	ale_shutdown),
161 	DEVMETHOD(device_suspend,	ale_suspend),
162 	DEVMETHOD(device_resume,	ale_resume),
163 
164 	/* MII interface. */
165 	DEVMETHOD(miibus_readreg,	ale_miibus_readreg),
166 	DEVMETHOD(miibus_writereg,	ale_miibus_writereg),
167 	DEVMETHOD(miibus_statchg,	ale_miibus_statchg),
168 
169 	DEVMETHOD_END
170 };
171 
172 static driver_t ale_driver = {
173 	"ale",
174 	ale_methods,
175 	sizeof(struct ale_softc)
176 };
177 
178 DRIVER_MODULE(ale, pci, ale_driver, NULL, NULL);
179 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, ale, ale_devs,
180     nitems(ale_devs));
181 DRIVER_MODULE(miibus, ale, miibus_driver, NULL, NULL);
182 
183 static struct resource_spec ale_res_spec_mem[] = {
184 	{ SYS_RES_MEMORY,	PCIR_BAR(0),	RF_ACTIVE },
185 	{ -1,			0,		0 }
186 };
187 
188 static struct resource_spec ale_irq_spec_legacy[] = {
189 	{ SYS_RES_IRQ,		0,		RF_ACTIVE | RF_SHAREABLE },
190 	{ -1,			0,		0 }
191 };
192 
193 static struct resource_spec ale_irq_spec_msi[] = {
194 	{ SYS_RES_IRQ,		1,		RF_ACTIVE },
195 	{ -1,			0,		0 }
196 };
197 
198 static struct resource_spec ale_irq_spec_msix[] = {
199 	{ SYS_RES_IRQ,		1,		RF_ACTIVE },
200 	{ -1,			0,		0 }
201 };
202 
203 static int
204 ale_miibus_readreg(device_t dev, int phy, int reg)
205 {
206 	struct ale_softc *sc;
207 	uint32_t v;
208 	int i;
209 
210 	sc = device_get_softc(dev);
211 
212 	CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ |
213 	    MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
214 	for (i = ALE_PHY_TIMEOUT; i > 0; i--) {
215 		DELAY(5);
216 		v = CSR_READ_4(sc, ALE_MDIO);
217 		if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
218 			break;
219 	}
220 
221 	if (i == 0) {
222 		device_printf(sc->ale_dev, "phy read timeout : %d\n", reg);
223 		return (0);
224 	}
225 
226 	return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT);
227 }
228 
229 static int
230 ale_miibus_writereg(device_t dev, int phy, int reg, int val)
231 {
232 	struct ale_softc *sc;
233 	uint32_t v;
234 	int i;
235 
236 	sc = device_get_softc(dev);
237 
238 	CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE |
239 	    (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT |
240 	    MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg));
241 	for (i = ALE_PHY_TIMEOUT; i > 0; i--) {
242 		DELAY(5);
243 		v = CSR_READ_4(sc, ALE_MDIO);
244 		if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0)
245 			break;
246 	}
247 
248 	if (i == 0)
249 		device_printf(sc->ale_dev, "phy write timeout : %d\n", reg);
250 
251 	return (0);
252 }
253 
254 static void
255 ale_miibus_statchg(device_t dev)
256 {
257 	struct ale_softc *sc;
258 	struct mii_data *mii;
259 	struct ifnet *ifp;
260 	uint32_t reg;
261 
262 	sc = device_get_softc(dev);
263 	mii = device_get_softc(sc->ale_miibus);
264 	ifp = sc->ale_ifp;
265 	if (mii == NULL || ifp == NULL ||
266 	    (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
267 		return;
268 
269 	sc->ale_flags &= ~ALE_FLAG_LINK;
270 	if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
271 	    (IFM_ACTIVE | IFM_AVALID)) {
272 		switch (IFM_SUBTYPE(mii->mii_media_active)) {
273 		case IFM_10_T:
274 		case IFM_100_TX:
275 			sc->ale_flags |= ALE_FLAG_LINK;
276 			break;
277 		case IFM_1000_T:
278 			if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0)
279 				sc->ale_flags |= ALE_FLAG_LINK;
280 			break;
281 		default:
282 			break;
283 		}
284 	}
285 
286 	/* Stop Rx/Tx MACs. */
287 	ale_stop_mac(sc);
288 
289 	/* Program MACs with resolved speed/duplex/flow-control. */
290 	if ((sc->ale_flags & ALE_FLAG_LINK) != 0) {
291 		ale_mac_config(sc);
292 		/* Reenable Tx/Rx MACs. */
293 		reg = CSR_READ_4(sc, ALE_MAC_CFG);
294 		reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB;
295 		CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
296 	}
297 }
298 
299 static void
300 ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr)
301 {
302 	struct ale_softc *sc;
303 	struct mii_data *mii;
304 
305 	sc = ifp->if_softc;
306 	ALE_LOCK(sc);
307 	if ((ifp->if_flags & IFF_UP) == 0) {
308 		ALE_UNLOCK(sc);
309 		return;
310 	}
311 	mii = device_get_softc(sc->ale_miibus);
312 
313 	mii_pollstat(mii);
314 	ifmr->ifm_status = mii->mii_media_status;
315 	ifmr->ifm_active = mii->mii_media_active;
316 	ALE_UNLOCK(sc);
317 }
318 
319 static int
320 ale_mediachange(struct ifnet *ifp)
321 {
322 	struct ale_softc *sc;
323 	struct mii_data *mii;
324 	struct mii_softc *miisc;
325 	int error;
326 
327 	sc = ifp->if_softc;
328 	ALE_LOCK(sc);
329 	mii = device_get_softc(sc->ale_miibus);
330 	LIST_FOREACH(miisc, &mii->mii_phys, mii_list)
331 		PHY_RESET(miisc);
332 	error = mii_mediachg(mii);
333 	ALE_UNLOCK(sc);
334 
335 	return (error);
336 }
337 
338 static int
339 ale_probe(device_t dev)
340 {
341 	const struct ale_dev *sp;
342 	int i;
343 	uint16_t vendor, devid;
344 
345 	vendor = pci_get_vendor(dev);
346 	devid = pci_get_device(dev);
347 	sp = ale_devs;
348 	for (i = 0; i < nitems(ale_devs); i++) {
349 		if (vendor == sp->ale_vendorid &&
350 		    devid == sp->ale_deviceid) {
351 			device_set_desc(dev, sp->ale_name);
352 			return (BUS_PROBE_DEFAULT);
353 		}
354 		sp++;
355 	}
356 
357 	return (ENXIO);
358 }
359 
360 static void
361 ale_get_macaddr(struct ale_softc *sc)
362 {
363 	uint32_t ea[2], reg;
364 	int i, vpdc;
365 
366 	reg = CSR_READ_4(sc, ALE_SPI_CTRL);
367 	if ((reg & SPI_VPD_ENB) != 0) {
368 		reg &= ~SPI_VPD_ENB;
369 		CSR_WRITE_4(sc, ALE_SPI_CTRL, reg);
370 	}
371 
372 	if (pci_find_cap(sc->ale_dev, PCIY_VPD, &vpdc) == 0) {
373 		/*
374 		 * PCI VPD capability found, let TWSI reload EEPROM.
375 		 * This will set ethernet address of controller.
376 		 */
377 		CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) |
378 		    TWSI_CTRL_SW_LD_START);
379 		for (i = 100; i > 0; i--) {
380 			DELAY(1000);
381 			reg = CSR_READ_4(sc, ALE_TWSI_CTRL);
382 			if ((reg & TWSI_CTRL_SW_LD_START) == 0)
383 				break;
384 		}
385 		if (i == 0)
386 			device_printf(sc->ale_dev,
387 			    "reloading EEPROM timeout!\n");
388 	} else {
389 		if (bootverbose)
390 			device_printf(sc->ale_dev,
391 			    "PCI VPD capability not found!\n");
392 	}
393 
394 	ea[0] = CSR_READ_4(sc, ALE_PAR0);
395 	ea[1] = CSR_READ_4(sc, ALE_PAR1);
396 	sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF;
397 	sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF;
398 	sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF;
399 	sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF;
400 	sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF;
401 	sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF;
402 }
403 
404 static void
405 ale_phy_reset(struct ale_softc *sc)
406 {
407 
408 	/* Reset magic from Linux. */
409 	CSR_WRITE_2(sc, ALE_GPHY_CTRL,
410 	    GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET |
411 	    GPHY_CTRL_PHY_PLL_ON);
412 	DELAY(1000);
413 	CSR_WRITE_2(sc, ALE_GPHY_CTRL,
414 	    GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE |
415 	    GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON);
416 	DELAY(1000);
417 
418 #define	ATPHY_DBG_ADDR		0x1D
419 #define	ATPHY_DBG_DATA		0x1E
420 
421 	/* Enable hibernation mode. */
422 	ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
423 	    ATPHY_DBG_ADDR, 0x0B);
424 	ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
425 	    ATPHY_DBG_DATA, 0xBC00);
426 	/* Set Class A/B for all modes. */
427 	ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
428 	    ATPHY_DBG_ADDR, 0x00);
429 	ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
430 	    ATPHY_DBG_DATA, 0x02EF);
431 	/* Enable 10BT power saving. */
432 	ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
433 	    ATPHY_DBG_ADDR, 0x12);
434 	ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
435 	    ATPHY_DBG_DATA, 0x4C04);
436 	/* Adjust 1000T power. */
437 	ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
438 	    ATPHY_DBG_ADDR, 0x04);
439 	ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
440 	    ATPHY_DBG_ADDR, 0x8BBB);
441 	/* 10BT center tap voltage. */
442 	ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
443 	    ATPHY_DBG_ADDR, 0x05);
444 	ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
445 	    ATPHY_DBG_ADDR, 0x2C46);
446 
447 #undef	ATPHY_DBG_ADDR
448 #undef	ATPHY_DBG_DATA
449 	DELAY(1000);
450 }
451 
452 static int
453 ale_attach(device_t dev)
454 {
455 	struct ale_softc *sc;
456 	struct ifnet *ifp;
457 	uint16_t burst;
458 	int error, i, msic, msixc, pmc;
459 	uint32_t rxf_len, txf_len;
460 
461 	error = 0;
462 	sc = device_get_softc(dev);
463 	sc->ale_dev = dev;
464 
465 	mtx_init(&sc->ale_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
466 	    MTX_DEF);
467 	callout_init_mtx(&sc->ale_tick_ch, &sc->ale_mtx, 0);
468 	NET_TASK_INIT(&sc->ale_int_task, 0, ale_int_task, sc);
469 
470 	/* Map the device. */
471 	pci_enable_busmaster(dev);
472 	sc->ale_res_spec = ale_res_spec_mem;
473 	sc->ale_irq_spec = ale_irq_spec_legacy;
474 	error = bus_alloc_resources(dev, sc->ale_res_spec, sc->ale_res);
475 	if (error != 0) {
476 		device_printf(dev, "cannot allocate memory resources.\n");
477 		goto fail;
478 	}
479 
480 	/* Set PHY address. */
481 	sc->ale_phyaddr = ALE_PHY_ADDR;
482 
483 	/* Reset PHY. */
484 	ale_phy_reset(sc);
485 
486 	/* Reset the ethernet controller. */
487 	ale_reset(sc);
488 
489 	/* Get PCI and chip id/revision. */
490 	sc->ale_rev = pci_get_revid(dev);
491 	if (sc->ale_rev >= 0xF0) {
492 		/* L2E Rev. B. AR8114 */
493 		sc->ale_flags |= ALE_FLAG_FASTETHER;
494 	} else {
495 		if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) {
496 			/* L1E AR8121 */
497 			sc->ale_flags |= ALE_FLAG_JUMBO;
498 		} else {
499 			/* L2E Rev. A. AR8113 */
500 			sc->ale_flags |= ALE_FLAG_FASTETHER;
501 		}
502 	}
503 	/*
504 	 * All known controllers seems to require 4 bytes alignment
505 	 * of Tx buffers to make Tx checksum offload with custom
506 	 * checksum generation method work.
507 	 */
508 	sc->ale_flags |= ALE_FLAG_TXCSUM_BUG;
509 	/*
510 	 * All known controllers seems to have issues on Rx checksum
511 	 * offload for fragmented IP datagrams.
512 	 */
513 	sc->ale_flags |= ALE_FLAG_RXCSUM_BUG;
514 	/*
515 	 * Don't use Tx CMB. It is known to cause RRS update failure
516 	 * under certain circumstances. Typical phenomenon of the
517 	 * issue would be unexpected sequence number encountered in
518 	 * Rx handler.
519 	 */
520 	sc->ale_flags |= ALE_FLAG_TXCMB_BUG;
521 	sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >>
522 	    MASTER_CHIP_REV_SHIFT;
523 	if (bootverbose) {
524 		device_printf(dev, "PCI device revision : 0x%04x\n",
525 		    sc->ale_rev);
526 		device_printf(dev, "Chip id/revision : 0x%04x\n",
527 		    sc->ale_chip_rev);
528 	}
529 	txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN);
530 	rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);
531 	/*
532 	 * Uninitialized hardware returns an invalid chip id/revision
533 	 * as well as 0xFFFFFFFF for Tx/Rx fifo length.
534 	 */
535 	if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF ||
536 	    rxf_len == 0xFFFFFFF) {
537 		device_printf(dev,"chip revision : 0x%04x, %u Tx FIFO "
538 		    "%u Rx FIFO -- not initialized?\n", sc->ale_chip_rev,
539 		    txf_len, rxf_len);
540 		error = ENXIO;
541 		goto fail;
542 	}
543 	device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", txf_len, rxf_len);
544 
545 	/* Allocate IRQ resources. */
546 	msixc = pci_msix_count(dev);
547 	msic = pci_msi_count(dev);
548 	if (bootverbose) {
549 		device_printf(dev, "MSIX count : %d\n", msixc);
550 		device_printf(dev, "MSI count : %d\n", msic);
551 	}
552 
553 	/* Prefer MSIX over MSI. */
554 	if (msix_disable == 0 || msi_disable == 0) {
555 		if (msix_disable == 0 && msixc == ALE_MSIX_MESSAGES &&
556 		    pci_alloc_msix(dev, &msixc) == 0) {
557 			if (msixc == ALE_MSIX_MESSAGES) {
558 				device_printf(dev, "Using %d MSIX messages.\n",
559 				    msixc);
560 				sc->ale_flags |= ALE_FLAG_MSIX;
561 				sc->ale_irq_spec = ale_irq_spec_msix;
562 			} else
563 				pci_release_msi(dev);
564 		}
565 		if (msi_disable == 0 && (sc->ale_flags & ALE_FLAG_MSIX) == 0 &&
566 		    msic == ALE_MSI_MESSAGES &&
567 		    pci_alloc_msi(dev, &msic) == 0) {
568 			if (msic == ALE_MSI_MESSAGES) {
569 				device_printf(dev, "Using %d MSI messages.\n",
570 				    msic);
571 				sc->ale_flags |= ALE_FLAG_MSI;
572 				sc->ale_irq_spec = ale_irq_spec_msi;
573 			} else
574 				pci_release_msi(dev);
575 		}
576 	}
577 
578 	error = bus_alloc_resources(dev, sc->ale_irq_spec, sc->ale_irq);
579 	if (error != 0) {
580 		device_printf(dev, "cannot allocate IRQ resources.\n");
581 		goto fail;
582 	}
583 
584 	/* Get DMA parameters from PCIe device control register. */
585 	if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) {
586 		sc->ale_flags |= ALE_FLAG_PCIE;
587 		burst = pci_read_config(dev, i + 0x08, 2);
588 		/* Max read request size. */
589 		sc->ale_dma_rd_burst = ((burst >> 12) & 0x07) <<
590 		    DMA_CFG_RD_BURST_SHIFT;
591 		/* Max payload size. */
592 		sc->ale_dma_wr_burst = ((burst >> 5) & 0x07) <<
593 		    DMA_CFG_WR_BURST_SHIFT;
594 		if (bootverbose) {
595 			device_printf(dev, "Read request size : %d bytes.\n",
596 			    128 << ((burst >> 12) & 0x07));
597 			device_printf(dev, "TLP payload size : %d bytes.\n",
598 			    128 << ((burst >> 5) & 0x07));
599 		}
600 	} else {
601 		sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128;
602 		sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128;
603 	}
604 
605 	/* Create device sysctl node. */
606 	ale_sysctl_node(sc);
607 
608 	if ((error = ale_dma_alloc(sc)) != 0)
609 		goto fail;
610 
611 	/* Load station address. */
612 	ale_get_macaddr(sc);
613 
614 	ifp = sc->ale_ifp = if_alloc(IFT_ETHER);
615 	if (ifp == NULL) {
616 		device_printf(dev, "cannot allocate ifnet structure.\n");
617 		error = ENXIO;
618 		goto fail;
619 	}
620 
621 	ifp->if_softc = sc;
622 	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
623 	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
624 	ifp->if_ioctl = ale_ioctl;
625 	ifp->if_start = ale_start;
626 	ifp->if_init = ale_init;
627 	ifp->if_snd.ifq_drv_maxlen = ALE_TX_RING_CNT - 1;
628 	IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen);
629 	IFQ_SET_READY(&ifp->if_snd);
630 	ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4;
631 	ifp->if_hwassist = ALE_CSUM_FEATURES | CSUM_TSO;
632 	if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) {
633 		sc->ale_flags |= ALE_FLAG_PMCAP;
634 		ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST;
635 	}
636 	ifp->if_capenable = ifp->if_capabilities;
637 
638 	/* Set up MII bus. */
639 	error = mii_attach(dev, &sc->ale_miibus, ifp, ale_mediachange,
640 	    ale_mediastatus, BMSR_DEFCAPMASK, sc->ale_phyaddr, MII_OFFSET_ANY,
641 	    MIIF_DOPAUSE);
642 	if (error != 0) {
643 		device_printf(dev, "attaching PHYs failed\n");
644 		goto fail;
645 	}
646 
647 	ether_ifattach(ifp, sc->ale_eaddr);
648 
649 	/* VLAN capability setup. */
650 	ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING |
651 	    IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO;
652 	ifp->if_capenable = ifp->if_capabilities;
653 	/*
654 	 * Even though controllers supported by ale(3) have Rx checksum
655 	 * offload bug the workaround for fragmented frames seemed to
656 	 * work so far. However it seems Rx checksum offload does not
657 	 * work under certain conditions. So disable Rx checksum offload
658 	 * until I find more clue about it but allow users to override it.
659 	 */
660 	ifp->if_capenable &= ~IFCAP_RXCSUM;
661 
662 	/* Tell the upper layer(s) we support long frames. */
663 	ifp->if_hdrlen = sizeof(struct ether_vlan_header);
664 
665 	/* Create local taskq. */
666 	sc->ale_tq = taskqueue_create_fast("ale_taskq", M_WAITOK,
667 	    taskqueue_thread_enqueue, &sc->ale_tq);
668 	if (sc->ale_tq == NULL) {
669 		device_printf(dev, "could not create taskqueue.\n");
670 		ether_ifdetach(ifp);
671 		error = ENXIO;
672 		goto fail;
673 	}
674 	taskqueue_start_threads(&sc->ale_tq, 1, PI_NET, "%s taskq",
675 	    device_get_nameunit(sc->ale_dev));
676 
677 	if ((sc->ale_flags & ALE_FLAG_MSIX) != 0)
678 		msic = ALE_MSIX_MESSAGES;
679 	else if ((sc->ale_flags & ALE_FLAG_MSI) != 0)
680 		msic = ALE_MSI_MESSAGES;
681 	else
682 		msic = 1;
683 	for (i = 0; i < msic; i++) {
684 		error = bus_setup_intr(dev, sc->ale_irq[i],
685 		    INTR_TYPE_NET | INTR_MPSAFE, ale_intr, NULL, sc,
686 		    &sc->ale_intrhand[i]);
687 		if (error != 0)
688 			break;
689 	}
690 	if (error != 0) {
691 		device_printf(dev, "could not set up interrupt handler.\n");
692 		taskqueue_free(sc->ale_tq);
693 		sc->ale_tq = NULL;
694 		ether_ifdetach(ifp);
695 		goto fail;
696 	}
697 
698 fail:
699 	if (error != 0)
700 		ale_detach(dev);
701 
702 	return (error);
703 }
704 
705 static int
706 ale_detach(device_t dev)
707 {
708 	struct ale_softc *sc;
709 	struct ifnet *ifp;
710 	int i, msic;
711 
712 	sc = device_get_softc(dev);
713 
714 	ifp = sc->ale_ifp;
715 	if (device_is_attached(dev)) {
716 		ether_ifdetach(ifp);
717 		ALE_LOCK(sc);
718 		ale_stop(sc);
719 		ALE_UNLOCK(sc);
720 		callout_drain(&sc->ale_tick_ch);
721 		taskqueue_drain(sc->ale_tq, &sc->ale_int_task);
722 	}
723 
724 	if (sc->ale_tq != NULL) {
725 		taskqueue_drain(sc->ale_tq, &sc->ale_int_task);
726 		taskqueue_free(sc->ale_tq);
727 		sc->ale_tq = NULL;
728 	}
729 
730 	if (sc->ale_miibus != NULL) {
731 		device_delete_child(dev, sc->ale_miibus);
732 		sc->ale_miibus = NULL;
733 	}
734 	bus_generic_detach(dev);
735 	ale_dma_free(sc);
736 
737 	if (ifp != NULL) {
738 		if_free(ifp);
739 		sc->ale_ifp = NULL;
740 	}
741 
742 	if ((sc->ale_flags & ALE_FLAG_MSIX) != 0)
743 		msic = ALE_MSIX_MESSAGES;
744 	else if ((sc->ale_flags & ALE_FLAG_MSI) != 0)
745 		msic = ALE_MSI_MESSAGES;
746 	else
747 		msic = 1;
748 	for (i = 0; i < msic; i++) {
749 		if (sc->ale_intrhand[i] != NULL) {
750 			bus_teardown_intr(dev, sc->ale_irq[i],
751 			    sc->ale_intrhand[i]);
752 			sc->ale_intrhand[i] = NULL;
753 		}
754 	}
755 
756 	bus_release_resources(dev, sc->ale_irq_spec, sc->ale_irq);
757 	if ((sc->ale_flags & (ALE_FLAG_MSI | ALE_FLAG_MSIX)) != 0)
758 		pci_release_msi(dev);
759 	bus_release_resources(dev, sc->ale_res_spec, sc->ale_res);
760 	mtx_destroy(&sc->ale_mtx);
761 
762 	return (0);
763 }
764 
765 #define	ALE_SYSCTL_STAT_ADD32(c, h, n, p, d)	\
766 	    SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
767 
768 #define	ALE_SYSCTL_STAT_ADD64(c, h, n, p, d)	\
769 	    SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d)
770 
771 static void
772 ale_sysctl_node(struct ale_softc *sc)
773 {
774 	struct sysctl_ctx_list *ctx;
775 	struct sysctl_oid_list *child, *parent;
776 	struct sysctl_oid *tree;
777 	struct ale_hw_stats *stats;
778 	int error;
779 
780 	stats = &sc->ale_stats;
781 	ctx = device_get_sysctl_ctx(sc->ale_dev);
782 	child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ale_dev));
783 
784 	SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod",
785 	    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->ale_int_rx_mod,
786 	    0, sysctl_hw_ale_int_mod, "I", "ale Rx interrupt moderation");
787 	SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod",
788 	    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->ale_int_tx_mod,
789 	    0, sysctl_hw_ale_int_mod, "I", "ale Tx interrupt moderation");
790 	/* Pull in device tunables. */
791 	sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT;
792 	error = resource_int_value(device_get_name(sc->ale_dev),
793 	    device_get_unit(sc->ale_dev), "int_rx_mod", &sc->ale_int_rx_mod);
794 	if (error == 0) {
795 		if (sc->ale_int_rx_mod < ALE_IM_TIMER_MIN ||
796 		    sc->ale_int_rx_mod > ALE_IM_TIMER_MAX) {
797 			device_printf(sc->ale_dev, "int_rx_mod value out of "
798 			    "range; using default: %d\n",
799 			    ALE_IM_RX_TIMER_DEFAULT);
800 			sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT;
801 		}
802 	}
803 	sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT;
804 	error = resource_int_value(device_get_name(sc->ale_dev),
805 	    device_get_unit(sc->ale_dev), "int_tx_mod", &sc->ale_int_tx_mod);
806 	if (error == 0) {
807 		if (sc->ale_int_tx_mod < ALE_IM_TIMER_MIN ||
808 		    sc->ale_int_tx_mod > ALE_IM_TIMER_MAX) {
809 			device_printf(sc->ale_dev, "int_tx_mod value out of "
810 			    "range; using default: %d\n",
811 			    ALE_IM_TX_TIMER_DEFAULT);
812 			sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT;
813 		}
814 	}
815 	SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit",
816 	    CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT,
817 	    &sc->ale_process_limit, 0, sysctl_hw_ale_proc_limit, "I",
818 	    "max number of Rx events to process");
819 	/* Pull in device tunables. */
820 	sc->ale_process_limit = ALE_PROC_DEFAULT;
821 	error = resource_int_value(device_get_name(sc->ale_dev),
822 	    device_get_unit(sc->ale_dev), "process_limit",
823 	    &sc->ale_process_limit);
824 	if (error == 0) {
825 		if (sc->ale_process_limit < ALE_PROC_MIN ||
826 		    sc->ale_process_limit > ALE_PROC_MAX) {
827 			device_printf(sc->ale_dev,
828 			    "process_limit value out of range; "
829 			    "using default: %d\n", ALE_PROC_DEFAULT);
830 			sc->ale_process_limit = ALE_PROC_DEFAULT;
831 		}
832 	}
833 
834 	/* Misc statistics. */
835 	ALE_SYSCTL_STAT_ADD32(ctx, child, "reset_brk_seq",
836 	    &stats->reset_brk_seq,
837 	    "Controller resets due to broken Rx sequnce number");
838 
839 	tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats",
840 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ATE statistics");
841 	parent = SYSCTL_CHILDREN(tree);
842 
843 	/* Rx statistics. */
844 	tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx",
845 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics");
846 	child = SYSCTL_CHILDREN(tree);
847 	ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
848 	    &stats->rx_frames, "Good frames");
849 	ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
850 	    &stats->rx_bcast_frames, "Good broadcast frames");
851 	ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
852 	    &stats->rx_mcast_frames, "Good multicast frames");
853 	ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
854 	    &stats->rx_pause_frames, "Pause control frames");
855 	ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
856 	    &stats->rx_control_frames, "Control frames");
857 	ALE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs",
858 	    &stats->rx_crcerrs, "CRC errors");
859 	ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
860 	    &stats->rx_lenerrs, "Frames with length mismatched");
861 	ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
862 	    &stats->rx_bytes, "Good octets");
863 	ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
864 	    &stats->rx_bcast_bytes, "Good broadcast octets");
865 	ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
866 	    &stats->rx_mcast_bytes, "Good multicast octets");
867 	ALE_SYSCTL_STAT_ADD32(ctx, child, "runts",
868 	    &stats->rx_runts, "Too short frames");
869 	ALE_SYSCTL_STAT_ADD32(ctx, child, "fragments",
870 	    &stats->rx_fragments, "Fragmented frames");
871 	ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
872 	    &stats->rx_pkts_64, "64 bytes frames");
873 	ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
874 	    &stats->rx_pkts_65_127, "65 to 127 bytes frames");
875 	ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
876 	    &stats->rx_pkts_128_255, "128 to 255 bytes frames");
877 	ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
878 	    &stats->rx_pkts_256_511, "256 to 511 bytes frames");
879 	ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
880 	    &stats->rx_pkts_512_1023, "512 to 1023 bytes frames");
881 	ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
882 	    &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames");
883 	ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
884 	    &stats->rx_pkts_1519_max, "1519 to max frames");
885 	ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
886 	    &stats->rx_pkts_truncated, "Truncated frames due to MTU size");
887 	ALE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows",
888 	    &stats->rx_fifo_oflows, "FIFO overflows");
889 	ALE_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs",
890 	    &stats->rx_rrs_errs, "Return status write-back errors");
891 	ALE_SYSCTL_STAT_ADD32(ctx, child, "align_errs",
892 	    &stats->rx_alignerrs, "Alignment errors");
893 	ALE_SYSCTL_STAT_ADD32(ctx, child, "filtered",
894 	    &stats->rx_pkts_filtered,
895 	    "Frames dropped due to address filtering");
896 
897 	/* Tx statistics. */
898 	tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx",
899 	    CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics");
900 	child = SYSCTL_CHILDREN(tree);
901 	ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames",
902 	    &stats->tx_frames, "Good frames");
903 	ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames",
904 	    &stats->tx_bcast_frames, "Good broadcast frames");
905 	ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames",
906 	    &stats->tx_mcast_frames, "Good multicast frames");
907 	ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames",
908 	    &stats->tx_pause_frames, "Pause control frames");
909 	ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames",
910 	    &stats->tx_control_frames, "Control frames");
911 	ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers",
912 	    &stats->tx_excess_defer, "Frames with excessive derferrals");
913 	ALE_SYSCTL_STAT_ADD32(ctx, child, "defers",
914 	    &stats->tx_excess_defer, "Frames with derferrals");
915 	ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets",
916 	    &stats->tx_bytes, "Good octets");
917 	ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets",
918 	    &stats->tx_bcast_bytes, "Good broadcast octets");
919 	ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets",
920 	    &stats->tx_mcast_bytes, "Good multicast octets");
921 	ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64",
922 	    &stats->tx_pkts_64, "64 bytes frames");
923 	ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127",
924 	    &stats->tx_pkts_65_127, "65 to 127 bytes frames");
925 	ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255",
926 	    &stats->tx_pkts_128_255, "128 to 255 bytes frames");
927 	ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511",
928 	    &stats->tx_pkts_256_511, "256 to 511 bytes frames");
929 	ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023",
930 	    &stats->tx_pkts_512_1023, "512 to 1023 bytes frames");
931 	ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518",
932 	    &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames");
933 	ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max",
934 	    &stats->tx_pkts_1519_max, "1519 to max frames");
935 	ALE_SYSCTL_STAT_ADD32(ctx, child, "single_colls",
936 	    &stats->tx_single_colls, "Single collisions");
937 	ALE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls",
938 	    &stats->tx_multi_colls, "Multiple collisions");
939 	ALE_SYSCTL_STAT_ADD32(ctx, child, "late_colls",
940 	    &stats->tx_late_colls, "Late collisions");
941 	ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_colls",
942 	    &stats->tx_excess_colls, "Excessive collisions");
943 	ALE_SYSCTL_STAT_ADD32(ctx, child, "underruns",
944 	    &stats->tx_underrun, "FIFO underruns");
945 	ALE_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns",
946 	    &stats->tx_desc_underrun, "Descriptor write-back errors");
947 	ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs",
948 	    &stats->tx_lenerrs, "Frames with length mismatched");
949 	ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs",
950 	    &stats->tx_pkts_truncated, "Truncated frames due to MTU size");
951 }
952 
953 #undef ALE_SYSCTL_STAT_ADD32
954 #undef ALE_SYSCTL_STAT_ADD64
955 
956 struct ale_dmamap_arg {
957 	bus_addr_t	ale_busaddr;
958 };
959 
960 static void
961 ale_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
962 {
963 	struct ale_dmamap_arg *ctx;
964 
965 	if (error != 0)
966 		return;
967 
968 	KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs));
969 
970 	ctx = (struct ale_dmamap_arg *)arg;
971 	ctx->ale_busaddr = segs[0].ds_addr;
972 }
973 
974 /*
975  * Tx descriptors/RXF0/CMB DMA blocks share ALE_DESC_ADDR_HI register
976  * which specifies high address region of DMA blocks. Therefore these
977  * blocks should have the same high address of given 4GB address
978  * space(i.e. crossing 4GB boundary is not allowed).
979  */
980 static int
981 ale_check_boundary(struct ale_softc *sc)
982 {
983 	bus_addr_t rx_cmb_end[ALE_RX_PAGES], tx_cmb_end;
984 	bus_addr_t rx_page_end[ALE_RX_PAGES], tx_ring_end;
985 
986 	rx_page_end[0] = sc->ale_cdata.ale_rx_page[0].page_paddr +
987 	    sc->ale_pagesize;
988 	rx_page_end[1] = sc->ale_cdata.ale_rx_page[1].page_paddr +
989 	    sc->ale_pagesize;
990 	tx_ring_end = sc->ale_cdata.ale_tx_ring_paddr + ALE_TX_RING_SZ;
991 	tx_cmb_end = sc->ale_cdata.ale_tx_cmb_paddr + ALE_TX_CMB_SZ;
992 	rx_cmb_end[0] = sc->ale_cdata.ale_rx_page[0].cmb_paddr + ALE_RX_CMB_SZ;
993 	rx_cmb_end[1] = sc->ale_cdata.ale_rx_page[1].cmb_paddr + ALE_RX_CMB_SZ;
994 
995 	if ((ALE_ADDR_HI(tx_ring_end) !=
996 	    ALE_ADDR_HI(sc->ale_cdata.ale_tx_ring_paddr)) ||
997 	    (ALE_ADDR_HI(rx_page_end[0]) !=
998 	    ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].page_paddr)) ||
999 	    (ALE_ADDR_HI(rx_page_end[1]) !=
1000 	    ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].page_paddr)) ||
1001 	    (ALE_ADDR_HI(tx_cmb_end) !=
1002 	    ALE_ADDR_HI(sc->ale_cdata.ale_tx_cmb_paddr)) ||
1003 	    (ALE_ADDR_HI(rx_cmb_end[0]) !=
1004 	    ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].cmb_paddr)) ||
1005 	    (ALE_ADDR_HI(rx_cmb_end[1]) !=
1006 	    ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].cmb_paddr)))
1007 		return (EFBIG);
1008 
1009 	if ((ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[0])) ||
1010 	    (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[1])) ||
1011 	    (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[0])) ||
1012 	    (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[1])) ||
1013 	    (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(tx_cmb_end)))
1014 		return (EFBIG);
1015 
1016 	return (0);
1017 }
1018 
1019 static int
1020 ale_dma_alloc(struct ale_softc *sc)
1021 {
1022 	struct ale_txdesc *txd;
1023 	bus_addr_t lowaddr;
1024 	struct ale_dmamap_arg ctx;
1025 	int error, guard_size, i;
1026 
1027 	if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0)
1028 		guard_size = ALE_JUMBO_FRAMELEN;
1029 	else
1030 		guard_size = ALE_MAX_FRAMELEN;
1031 	sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ,
1032 	    ALE_RX_PAGE_ALIGN);
1033 	lowaddr = BUS_SPACE_MAXADDR;
1034 again:
1035 	/* Create parent DMA tag. */
1036 	error = bus_dma_tag_create(
1037 	    bus_get_dma_tag(sc->ale_dev), /* parent */
1038 	    1, 0,			/* alignment, boundary */
1039 	    lowaddr,			/* lowaddr */
1040 	    BUS_SPACE_MAXADDR,		/* highaddr */
1041 	    NULL, NULL,			/* filter, filterarg */
1042 	    BUS_SPACE_MAXSIZE_32BIT,	/* maxsize */
1043 	    0,				/* nsegments */
1044 	    BUS_SPACE_MAXSIZE_32BIT,	/* maxsegsize */
1045 	    0,				/* flags */
1046 	    NULL, NULL,			/* lockfunc, lockarg */
1047 	    &sc->ale_cdata.ale_parent_tag);
1048 	if (error != 0) {
1049 		device_printf(sc->ale_dev,
1050 		    "could not create parent DMA tag.\n");
1051 		goto fail;
1052 	}
1053 
1054 	/* Create DMA tag for Tx descriptor ring. */
1055 	error = bus_dma_tag_create(
1056 	    sc->ale_cdata.ale_parent_tag, /* parent */
1057 	    ALE_TX_RING_ALIGN, 0,	/* alignment, boundary */
1058 	    BUS_SPACE_MAXADDR,		/* lowaddr */
1059 	    BUS_SPACE_MAXADDR,		/* highaddr */
1060 	    NULL, NULL,			/* filter, filterarg */
1061 	    ALE_TX_RING_SZ,		/* maxsize */
1062 	    1,				/* nsegments */
1063 	    ALE_TX_RING_SZ,		/* maxsegsize */
1064 	    0,				/* flags */
1065 	    NULL, NULL,			/* lockfunc, lockarg */
1066 	    &sc->ale_cdata.ale_tx_ring_tag);
1067 	if (error != 0) {
1068 		device_printf(sc->ale_dev,
1069 		    "could not create Tx ring DMA tag.\n");
1070 		goto fail;
1071 	}
1072 
1073 	/* Create DMA tag for Rx pages. */
1074 	for (i = 0; i < ALE_RX_PAGES; i++) {
1075 		error = bus_dma_tag_create(
1076 		    sc->ale_cdata.ale_parent_tag, /* parent */
1077 		    ALE_RX_PAGE_ALIGN, 0,	/* alignment, boundary */
1078 		    BUS_SPACE_MAXADDR,		/* lowaddr */
1079 		    BUS_SPACE_MAXADDR,		/* highaddr */
1080 		    NULL, NULL,			/* filter, filterarg */
1081 		    sc->ale_pagesize,		/* maxsize */
1082 		    1,				/* nsegments */
1083 		    sc->ale_pagesize,		/* maxsegsize */
1084 		    0,				/* flags */
1085 		    NULL, NULL,			/* lockfunc, lockarg */
1086 		    &sc->ale_cdata.ale_rx_page[i].page_tag);
1087 		if (error != 0) {
1088 			device_printf(sc->ale_dev,
1089 			    "could not create Rx page %d DMA tag.\n", i);
1090 			goto fail;
1091 		}
1092 	}
1093 
1094 	/* Create DMA tag for Tx coalescing message block. */
1095 	error = bus_dma_tag_create(
1096 	    sc->ale_cdata.ale_parent_tag, /* parent */
1097 	    ALE_CMB_ALIGN, 0,		/* alignment, boundary */
1098 	    BUS_SPACE_MAXADDR,		/* lowaddr */
1099 	    BUS_SPACE_MAXADDR,		/* highaddr */
1100 	    NULL, NULL,			/* filter, filterarg */
1101 	    ALE_TX_CMB_SZ,		/* maxsize */
1102 	    1,				/* nsegments */
1103 	    ALE_TX_CMB_SZ,		/* maxsegsize */
1104 	    0,				/* flags */
1105 	    NULL, NULL,			/* lockfunc, lockarg */
1106 	    &sc->ale_cdata.ale_tx_cmb_tag);
1107 	if (error != 0) {
1108 		device_printf(sc->ale_dev,
1109 		    "could not create Tx CMB DMA tag.\n");
1110 		goto fail;
1111 	}
1112 
1113 	/* Create DMA tag for Rx coalescing message block. */
1114 	for (i = 0; i < ALE_RX_PAGES; i++) {
1115 		error = bus_dma_tag_create(
1116 		    sc->ale_cdata.ale_parent_tag, /* parent */
1117 		    ALE_CMB_ALIGN, 0,		/* alignment, boundary */
1118 		    BUS_SPACE_MAXADDR,		/* lowaddr */
1119 		    BUS_SPACE_MAXADDR,		/* highaddr */
1120 		    NULL, NULL,			/* filter, filterarg */
1121 		    ALE_RX_CMB_SZ,		/* maxsize */
1122 		    1,				/* nsegments */
1123 		    ALE_RX_CMB_SZ,		/* maxsegsize */
1124 		    0,				/* flags */
1125 		    NULL, NULL,			/* lockfunc, lockarg */
1126 		    &sc->ale_cdata.ale_rx_page[i].cmb_tag);
1127 		if (error != 0) {
1128 			device_printf(sc->ale_dev,
1129 			    "could not create Rx page %d CMB DMA tag.\n", i);
1130 			goto fail;
1131 		}
1132 	}
1133 
1134 	/* Allocate DMA'able memory and load the DMA map for Tx ring. */
1135 	error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_ring_tag,
1136 	    (void **)&sc->ale_cdata.ale_tx_ring,
1137 	    BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1138 	    &sc->ale_cdata.ale_tx_ring_map);
1139 	if (error != 0) {
1140 		device_printf(sc->ale_dev,
1141 		    "could not allocate DMA'able memory for Tx ring.\n");
1142 		goto fail;
1143 	}
1144 	ctx.ale_busaddr = 0;
1145 	error = bus_dmamap_load(sc->ale_cdata.ale_tx_ring_tag,
1146 	    sc->ale_cdata.ale_tx_ring_map, sc->ale_cdata.ale_tx_ring,
1147 	    ALE_TX_RING_SZ, ale_dmamap_cb, &ctx, 0);
1148 	if (error != 0 || ctx.ale_busaddr == 0) {
1149 		device_printf(sc->ale_dev,
1150 		    "could not load DMA'able memory for Tx ring.\n");
1151 		goto fail;
1152 	}
1153 	sc->ale_cdata.ale_tx_ring_paddr = ctx.ale_busaddr;
1154 
1155 	/* Rx pages. */
1156 	for (i = 0; i < ALE_RX_PAGES; i++) {
1157 		error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].page_tag,
1158 		    (void **)&sc->ale_cdata.ale_rx_page[i].page_addr,
1159 		    BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1160 		    &sc->ale_cdata.ale_rx_page[i].page_map);
1161 		if (error != 0) {
1162 			device_printf(sc->ale_dev,
1163 			    "could not allocate DMA'able memory for "
1164 			    "Rx page %d.\n", i);
1165 			goto fail;
1166 		}
1167 		ctx.ale_busaddr = 0;
1168 		error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].page_tag,
1169 		    sc->ale_cdata.ale_rx_page[i].page_map,
1170 		    sc->ale_cdata.ale_rx_page[i].page_addr,
1171 		    sc->ale_pagesize, ale_dmamap_cb, &ctx, 0);
1172 		if (error != 0 || ctx.ale_busaddr == 0) {
1173 			device_printf(sc->ale_dev,
1174 			    "could not load DMA'able memory for "
1175 			    "Rx page %d.\n", i);
1176 			goto fail;
1177 		}
1178 		sc->ale_cdata.ale_rx_page[i].page_paddr = ctx.ale_busaddr;
1179 	}
1180 
1181 	/* Tx CMB. */
1182 	error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_cmb_tag,
1183 	    (void **)&sc->ale_cdata.ale_tx_cmb,
1184 	    BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1185 	    &sc->ale_cdata.ale_tx_cmb_map);
1186 	if (error != 0) {
1187 		device_printf(sc->ale_dev,
1188 		    "could not allocate DMA'able memory for Tx CMB.\n");
1189 		goto fail;
1190 	}
1191 	ctx.ale_busaddr = 0;
1192 	error = bus_dmamap_load(sc->ale_cdata.ale_tx_cmb_tag,
1193 	    sc->ale_cdata.ale_tx_cmb_map, sc->ale_cdata.ale_tx_cmb,
1194 	    ALE_TX_CMB_SZ, ale_dmamap_cb, &ctx, 0);
1195 	if (error != 0 || ctx.ale_busaddr == 0) {
1196 		device_printf(sc->ale_dev,
1197 		    "could not load DMA'able memory for Tx CMB.\n");
1198 		goto fail;
1199 	}
1200 	sc->ale_cdata.ale_tx_cmb_paddr = ctx.ale_busaddr;
1201 
1202 	/* Rx CMB. */
1203 	for (i = 0; i < ALE_RX_PAGES; i++) {
1204 		error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].cmb_tag,
1205 		    (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr,
1206 		    BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT,
1207 		    &sc->ale_cdata.ale_rx_page[i].cmb_map);
1208 		if (error != 0) {
1209 			device_printf(sc->ale_dev, "could not allocate "
1210 			    "DMA'able memory for Rx page %d CMB.\n", i);
1211 			goto fail;
1212 		}
1213 		ctx.ale_busaddr = 0;
1214 		error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].cmb_tag,
1215 		    sc->ale_cdata.ale_rx_page[i].cmb_map,
1216 		    sc->ale_cdata.ale_rx_page[i].cmb_addr,
1217 		    ALE_RX_CMB_SZ, ale_dmamap_cb, &ctx, 0);
1218 		if (error != 0 || ctx.ale_busaddr == 0) {
1219 			device_printf(sc->ale_dev, "could not load DMA'able "
1220 			    "memory for Rx page %d CMB.\n", i);
1221 			goto fail;
1222 		}
1223 		sc->ale_cdata.ale_rx_page[i].cmb_paddr = ctx.ale_busaddr;
1224 	}
1225 
1226 	/*
1227 	 * Tx descriptors/RXF0/CMB DMA blocks share the same
1228 	 * high address region of 64bit DMA address space.
1229 	 */
1230 	if (lowaddr != BUS_SPACE_MAXADDR_32BIT &&
1231 	    (error = ale_check_boundary(sc)) != 0) {
1232 		device_printf(sc->ale_dev, "4GB boundary crossed, "
1233 		    "switching to 32bit DMA addressing mode.\n");
1234 		ale_dma_free(sc);
1235 		/*
1236 		 * Limit max allowable DMA address space to 32bit
1237 		 * and try again.
1238 		 */
1239 		lowaddr = BUS_SPACE_MAXADDR_32BIT;
1240 		goto again;
1241 	}
1242 
1243 	/*
1244 	 * Create Tx buffer parent tag.
1245 	 * AR81xx allows 64bit DMA addressing of Tx buffers so it
1246 	 * needs separate parent DMA tag as parent DMA address space
1247 	 * could be restricted to be within 32bit address space by
1248 	 * 4GB boundary crossing.
1249 	 */
1250 	error = bus_dma_tag_create(
1251 	    bus_get_dma_tag(sc->ale_dev), /* parent */
1252 	    1, 0,			/* alignment, boundary */
1253 	    BUS_SPACE_MAXADDR,		/* lowaddr */
1254 	    BUS_SPACE_MAXADDR,		/* highaddr */
1255 	    NULL, NULL,			/* filter, filterarg */
1256 	    BUS_SPACE_MAXSIZE_32BIT,	/* maxsize */
1257 	    0,				/* nsegments */
1258 	    BUS_SPACE_MAXSIZE_32BIT,	/* maxsegsize */
1259 	    0,				/* flags */
1260 	    NULL, NULL,			/* lockfunc, lockarg */
1261 	    &sc->ale_cdata.ale_buffer_tag);
1262 	if (error != 0) {
1263 		device_printf(sc->ale_dev,
1264 		    "could not create parent buffer DMA tag.\n");
1265 		goto fail;
1266 	}
1267 
1268 	/* Create DMA tag for Tx buffers. */
1269 	error = bus_dma_tag_create(
1270 	    sc->ale_cdata.ale_buffer_tag, /* parent */
1271 	    1, 0,			/* alignment, boundary */
1272 	    BUS_SPACE_MAXADDR,		/* lowaddr */
1273 	    BUS_SPACE_MAXADDR,		/* highaddr */
1274 	    NULL, NULL,			/* filter, filterarg */
1275 	    ALE_TSO_MAXSIZE,		/* maxsize */
1276 	    ALE_MAXTXSEGS,		/* nsegments */
1277 	    ALE_TSO_MAXSEGSIZE,		/* maxsegsize */
1278 	    0,				/* flags */
1279 	    NULL, NULL,			/* lockfunc, lockarg */
1280 	    &sc->ale_cdata.ale_tx_tag);
1281 	if (error != 0) {
1282 		device_printf(sc->ale_dev, "could not create Tx DMA tag.\n");
1283 		goto fail;
1284 	}
1285 
1286 	/* Create DMA maps for Tx buffers. */
1287 	for (i = 0; i < ALE_TX_RING_CNT; i++) {
1288 		txd = &sc->ale_cdata.ale_txdesc[i];
1289 		txd->tx_m = NULL;
1290 		txd->tx_dmamap = NULL;
1291 		error = bus_dmamap_create(sc->ale_cdata.ale_tx_tag, 0,
1292 		    &txd->tx_dmamap);
1293 		if (error != 0) {
1294 			device_printf(sc->ale_dev,
1295 			    "could not create Tx dmamap.\n");
1296 			goto fail;
1297 		}
1298 	}
1299 
1300 fail:
1301 	return (error);
1302 }
1303 
1304 static void
1305 ale_dma_free(struct ale_softc *sc)
1306 {
1307 	struct ale_txdesc *txd;
1308 	int i;
1309 
1310 	/* Tx buffers. */
1311 	if (sc->ale_cdata.ale_tx_tag != NULL) {
1312 		for (i = 0; i < ALE_TX_RING_CNT; i++) {
1313 			txd = &sc->ale_cdata.ale_txdesc[i];
1314 			if (txd->tx_dmamap != NULL) {
1315 				bus_dmamap_destroy(sc->ale_cdata.ale_tx_tag,
1316 				    txd->tx_dmamap);
1317 				txd->tx_dmamap = NULL;
1318 			}
1319 		}
1320 		bus_dma_tag_destroy(sc->ale_cdata.ale_tx_tag);
1321 		sc->ale_cdata.ale_tx_tag = NULL;
1322 	}
1323 	/* Tx descriptor ring. */
1324 	if (sc->ale_cdata.ale_tx_ring_tag != NULL) {
1325 		if (sc->ale_cdata.ale_tx_ring_paddr != 0)
1326 			bus_dmamap_unload(sc->ale_cdata.ale_tx_ring_tag,
1327 			    sc->ale_cdata.ale_tx_ring_map);
1328 		if (sc->ale_cdata.ale_tx_ring != NULL)
1329 			bus_dmamem_free(sc->ale_cdata.ale_tx_ring_tag,
1330 			    sc->ale_cdata.ale_tx_ring,
1331 			    sc->ale_cdata.ale_tx_ring_map);
1332 		sc->ale_cdata.ale_tx_ring_paddr = 0;
1333 		sc->ale_cdata.ale_tx_ring = NULL;
1334 		bus_dma_tag_destroy(sc->ale_cdata.ale_tx_ring_tag);
1335 		sc->ale_cdata.ale_tx_ring_tag = NULL;
1336 	}
1337 	/* Rx page block. */
1338 	for (i = 0; i < ALE_RX_PAGES; i++) {
1339 		if (sc->ale_cdata.ale_rx_page[i].page_tag != NULL) {
1340 			if (sc->ale_cdata.ale_rx_page[i].page_paddr != 0)
1341 				bus_dmamap_unload(
1342 				    sc->ale_cdata.ale_rx_page[i].page_tag,
1343 				    sc->ale_cdata.ale_rx_page[i].page_map);
1344 			if (sc->ale_cdata.ale_rx_page[i].page_addr != NULL)
1345 				bus_dmamem_free(
1346 				    sc->ale_cdata.ale_rx_page[i].page_tag,
1347 				    sc->ale_cdata.ale_rx_page[i].page_addr,
1348 				    sc->ale_cdata.ale_rx_page[i].page_map);
1349 			sc->ale_cdata.ale_rx_page[i].page_paddr = 0;
1350 			sc->ale_cdata.ale_rx_page[i].page_addr = NULL;
1351 			bus_dma_tag_destroy(
1352 			    sc->ale_cdata.ale_rx_page[i].page_tag);
1353 			sc->ale_cdata.ale_rx_page[i].page_tag = NULL;
1354 		}
1355 	}
1356 	/* Rx CMB. */
1357 	for (i = 0; i < ALE_RX_PAGES; i++) {
1358 		if (sc->ale_cdata.ale_rx_page[i].cmb_tag != NULL) {
1359 			if (sc->ale_cdata.ale_rx_page[i].cmb_paddr != 0)
1360 				bus_dmamap_unload(
1361 				    sc->ale_cdata.ale_rx_page[i].cmb_tag,
1362 				    sc->ale_cdata.ale_rx_page[i].cmb_map);
1363 			if (sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL)
1364 				bus_dmamem_free(
1365 				    sc->ale_cdata.ale_rx_page[i].cmb_tag,
1366 				    sc->ale_cdata.ale_rx_page[i].cmb_addr,
1367 				    sc->ale_cdata.ale_rx_page[i].cmb_map);
1368 			sc->ale_cdata.ale_rx_page[i].cmb_paddr = 0;
1369 			sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL;
1370 			bus_dma_tag_destroy(
1371 			    sc->ale_cdata.ale_rx_page[i].cmb_tag);
1372 			sc->ale_cdata.ale_rx_page[i].cmb_tag = NULL;
1373 		}
1374 	}
1375 	/* Tx CMB. */
1376 	if (sc->ale_cdata.ale_tx_cmb_tag != NULL) {
1377 		if (sc->ale_cdata.ale_tx_cmb_paddr != 0)
1378 			bus_dmamap_unload(sc->ale_cdata.ale_tx_cmb_tag,
1379 			    sc->ale_cdata.ale_tx_cmb_map);
1380 		if (sc->ale_cdata.ale_tx_cmb != NULL)
1381 			bus_dmamem_free(sc->ale_cdata.ale_tx_cmb_tag,
1382 			    sc->ale_cdata.ale_tx_cmb,
1383 			    sc->ale_cdata.ale_tx_cmb_map);
1384 		sc->ale_cdata.ale_tx_cmb_paddr = 0;
1385 		sc->ale_cdata.ale_tx_cmb = NULL;
1386 		bus_dma_tag_destroy(sc->ale_cdata.ale_tx_cmb_tag);
1387 		sc->ale_cdata.ale_tx_cmb_tag = NULL;
1388 	}
1389 	if (sc->ale_cdata.ale_buffer_tag != NULL) {
1390 		bus_dma_tag_destroy(sc->ale_cdata.ale_buffer_tag);
1391 		sc->ale_cdata.ale_buffer_tag = NULL;
1392 	}
1393 	if (sc->ale_cdata.ale_parent_tag != NULL) {
1394 		bus_dma_tag_destroy(sc->ale_cdata.ale_parent_tag);
1395 		sc->ale_cdata.ale_parent_tag = NULL;
1396 	}
1397 }
1398 
1399 static int
1400 ale_shutdown(device_t dev)
1401 {
1402 
1403 	return (ale_suspend(dev));
1404 }
1405 
1406 /*
1407  * Note, this driver resets the link speed to 10/100Mbps by
1408  * restarting auto-negotiation in suspend/shutdown phase but we
1409  * don't know whether that auto-negotiation would succeed or not
1410  * as driver has no control after powering off/suspend operation.
1411  * If the renegotiation fail WOL may not work. Running at 1Gbps
1412  * will draw more power than 375mA at 3.3V which is specified in
1413  * PCI specification and that would result in complete
1414  * shutdowning power to ethernet controller.
1415  *
1416  * TODO
1417  * Save current negotiated media speed/duplex/flow-control to
1418  * softc and restore the same link again after resuming. PHY
1419  * handling such as power down/resetting to 100Mbps may be better
1420  * handled in suspend method in phy driver.
1421  */
1422 static void
1423 ale_setlinkspeed(struct ale_softc *sc)
1424 {
1425 	struct mii_data *mii;
1426 	int aneg, i;
1427 
1428 	mii = device_get_softc(sc->ale_miibus);
1429 	mii_pollstat(mii);
1430 	aneg = 0;
1431 	if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) ==
1432 	    (IFM_ACTIVE | IFM_AVALID)) {
1433 		switch IFM_SUBTYPE(mii->mii_media_active) {
1434 		case IFM_10_T:
1435 		case IFM_100_TX:
1436 			return;
1437 		case IFM_1000_T:
1438 			aneg++;
1439 			break;
1440 		default:
1441 			break;
1442 		}
1443 	}
1444 	ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_100T2CR, 0);
1445 	ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
1446 	    MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA);
1447 	ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr,
1448 	    MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
1449 	DELAY(1000);
1450 	if (aneg != 0) {
1451 		/*
1452 		 * Poll link state until ale(4) get a 10/100Mbps link.
1453 		 */
1454 		for (i = 0; i < MII_ANEGTICKS_GIGE; i++) {
1455 			mii_pollstat(mii);
1456 			if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID))
1457 			    == (IFM_ACTIVE | IFM_AVALID)) {
1458 				switch (IFM_SUBTYPE(
1459 				    mii->mii_media_active)) {
1460 				case IFM_10_T:
1461 				case IFM_100_TX:
1462 					ale_mac_config(sc);
1463 					return;
1464 				default:
1465 					break;
1466 				}
1467 			}
1468 			ALE_UNLOCK(sc);
1469 			pause("alelnk", hz);
1470 			ALE_LOCK(sc);
1471 		}
1472 		if (i == MII_ANEGTICKS_GIGE)
1473 			device_printf(sc->ale_dev,
1474 			    "establishing a link failed, WOL may not work!");
1475 	}
1476 	/*
1477 	 * No link, force MAC to have 100Mbps, full-duplex link.
1478 	 * This is the last resort and may/may not work.
1479 	 */
1480 	mii->mii_media_status = IFM_AVALID | IFM_ACTIVE;
1481 	mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX;
1482 	ale_mac_config(sc);
1483 }
1484 
1485 static void
1486 ale_setwol(struct ale_softc *sc)
1487 {
1488 	struct ifnet *ifp;
1489 	uint32_t reg, pmcs;
1490 	uint16_t pmstat;
1491 	int pmc;
1492 
1493 	ALE_LOCK_ASSERT(sc);
1494 
1495 	if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) != 0) {
1496 		/* Disable WOL. */
1497 		CSR_WRITE_4(sc, ALE_WOL_CFG, 0);
1498 		reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);
1499 		reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1500 		CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg);
1501 		/* Force PHY power down. */
1502 		CSR_WRITE_2(sc, ALE_GPHY_CTRL,
1503 		    GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN |
1504 		    GPHY_CTRL_HIB_PULSE | GPHY_CTRL_PHY_PLL_ON |
1505 		    GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_IDDQ |
1506 		    GPHY_CTRL_PCLK_SEL_DIS | GPHY_CTRL_PWDOWN_HW);
1507 		return;
1508 	}
1509 
1510 	ifp = sc->ale_ifp;
1511 	if ((ifp->if_capenable & IFCAP_WOL) != 0) {
1512 		if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0)
1513 			ale_setlinkspeed(sc);
1514 	}
1515 
1516 	pmcs = 0;
1517 	if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0)
1518 		pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB;
1519 	CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs);
1520 	reg = CSR_READ_4(sc, ALE_MAC_CFG);
1521 	reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI |
1522 	    MAC_CFG_BCAST);
1523 	if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0)
1524 		reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST;
1525 	if ((ifp->if_capenable & IFCAP_WOL) != 0)
1526 		reg |= MAC_CFG_RX_ENB;
1527 	CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
1528 
1529 	if ((ifp->if_capenable & IFCAP_WOL) == 0) {
1530 		/* WOL disabled, PHY power down. */
1531 		reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC);
1532 		reg |= PCIE_PHYMISC_FORCE_RCV_DET;
1533 		CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg);
1534 		CSR_WRITE_2(sc, ALE_GPHY_CTRL,
1535 		    GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN |
1536 		    GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET |
1537 		    GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PCLK_SEL_DIS |
1538 		    GPHY_CTRL_PWDOWN_HW);
1539 	}
1540 	/* Request PME. */
1541 	pmstat = pci_read_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, 2);
1542 	pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE);
1543 	if ((ifp->if_capenable & IFCAP_WOL) != 0)
1544 		pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE;
1545 	pci_write_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, pmstat, 2);
1546 }
1547 
1548 static int
1549 ale_suspend(device_t dev)
1550 {
1551 	struct ale_softc *sc;
1552 
1553 	sc = device_get_softc(dev);
1554 
1555 	ALE_LOCK(sc);
1556 	ale_stop(sc);
1557 	ale_setwol(sc);
1558 	ALE_UNLOCK(sc);
1559 
1560 	return (0);
1561 }
1562 
1563 static int
1564 ale_resume(device_t dev)
1565 {
1566 	struct ale_softc *sc;
1567 	struct ifnet *ifp;
1568 	int pmc;
1569 	uint16_t pmstat;
1570 
1571 	sc = device_get_softc(dev);
1572 
1573 	ALE_LOCK(sc);
1574 	if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) == 0) {
1575 		/* Disable PME and clear PME status. */
1576 		pmstat = pci_read_config(sc->ale_dev,
1577 		    pmc + PCIR_POWER_STATUS, 2);
1578 		if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) {
1579 			pmstat &= ~PCIM_PSTAT_PMEENABLE;
1580 			pci_write_config(sc->ale_dev,
1581 			    pmc + PCIR_POWER_STATUS, pmstat, 2);
1582 		}
1583 	}
1584 	/* Reset PHY. */
1585 	ale_phy_reset(sc);
1586 	ifp = sc->ale_ifp;
1587 	if ((ifp->if_flags & IFF_UP) != 0) {
1588 		ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1589 		ale_init_locked(sc);
1590 	}
1591 	ALE_UNLOCK(sc);
1592 
1593 	return (0);
1594 }
1595 
1596 static int
1597 ale_encap(struct ale_softc *sc, struct mbuf **m_head)
1598 {
1599 	struct ale_txdesc *txd, *txd_last;
1600 	struct tx_desc *desc;
1601 	struct mbuf *m;
1602 	struct ip *ip;
1603 	struct tcphdr *tcp;
1604 	bus_dma_segment_t txsegs[ALE_MAXTXSEGS];
1605 	bus_dmamap_t map;
1606 	uint32_t cflags, hdrlen, ip_off, poff, vtag;
1607 	int error, i, nsegs, prod, si;
1608 
1609 	ALE_LOCK_ASSERT(sc);
1610 
1611 	M_ASSERTPKTHDR((*m_head));
1612 
1613 	m = *m_head;
1614 	ip = NULL;
1615 	tcp = NULL;
1616 	cflags = vtag = 0;
1617 	ip_off = poff = 0;
1618 	if ((m->m_pkthdr.csum_flags & (ALE_CSUM_FEATURES | CSUM_TSO)) != 0) {
1619 		/*
1620 		 * AR81xx requires offset of TCP/UDP payload in its Tx
1621 		 * descriptor to perform hardware Tx checksum offload.
1622 		 * Additionally, TSO requires IP/TCP header size and
1623 		 * modification of IP/TCP header in order to make TSO
1624 		 * engine work. This kind of operation takes many CPU
1625 		 * cycles on FreeBSD so fast host CPU is required to
1626 		 * get smooth TSO performance.
1627 		 */
1628 		struct ether_header *eh;
1629 
1630 		if (M_WRITABLE(m) == 0) {
1631 			/* Get a writable copy. */
1632 			m = m_dup(*m_head, M_NOWAIT);
1633 			/* Release original mbufs. */
1634 			m_freem(*m_head);
1635 			if (m == NULL) {
1636 				*m_head = NULL;
1637 				return (ENOBUFS);
1638 			}
1639 			*m_head = m;
1640 		}
1641 
1642 		/*
1643 		 * Buggy-controller requires 4 byte aligned Tx buffer
1644 		 * to make custom checksum offload work.
1645 		 */
1646 		if ((sc->ale_flags & ALE_FLAG_TXCSUM_BUG) != 0 &&
1647 		    (m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0 &&
1648 		    (mtod(m, intptr_t) & 3) != 0) {
1649 			m = m_defrag(*m_head, M_NOWAIT);
1650 			if (m == NULL) {
1651 				m_freem(*m_head);
1652 				*m_head = NULL;
1653 				return (ENOBUFS);
1654 			}
1655 			*m_head = m;
1656 		}
1657 
1658 		ip_off = sizeof(struct ether_header);
1659 		m = m_pullup(m, ip_off);
1660 		if (m == NULL) {
1661 			*m_head = NULL;
1662 			return (ENOBUFS);
1663 		}
1664 		eh = mtod(m, struct ether_header *);
1665 		/*
1666 		 * Check if hardware VLAN insertion is off.
1667 		 * Additional check for LLC/SNAP frame?
1668 		 */
1669 		if (eh->ether_type == htons(ETHERTYPE_VLAN)) {
1670 			ip_off = sizeof(struct ether_vlan_header);
1671 			m = m_pullup(m, ip_off);
1672 			if (m == NULL) {
1673 				*m_head = NULL;
1674 				return (ENOBUFS);
1675 			}
1676 		}
1677 		m = m_pullup(m, ip_off + sizeof(struct ip));
1678 		if (m == NULL) {
1679 			*m_head = NULL;
1680 			return (ENOBUFS);
1681 		}
1682 		ip = (struct ip *)(mtod(m, char *) + ip_off);
1683 		poff = ip_off + (ip->ip_hl << 2);
1684 		if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1685 			/*
1686 			 * XXX
1687 			 * AR81xx requires the first descriptor should
1688 			 * not include any TCP playload for TSO case.
1689 			 * (i.e. ethernet header + IP + TCP header only)
1690 			 * m_pullup(9) above will ensure this too.
1691 			 * However it's not correct if the first mbuf
1692 			 * of the chain does not use cluster.
1693 			 */
1694 			m = m_pullup(m, poff + sizeof(struct tcphdr));
1695 			if (m == NULL) {
1696 				*m_head = NULL;
1697 				return (ENOBUFS);
1698 			}
1699 			ip = (struct ip *)(mtod(m, char *) + ip_off);
1700 			tcp = (struct tcphdr *)(mtod(m, char *) + poff);
1701 			m = m_pullup(m, poff + (tcp->th_off << 2));
1702 			if (m == NULL) {
1703 				*m_head = NULL;
1704 				return (ENOBUFS);
1705 			}
1706 			/*
1707 			 * AR81xx requires IP/TCP header size and offset as
1708 			 * well as TCP pseudo checksum which complicates
1709 			 * TSO configuration. I guess this comes from the
1710 			 * adherence to Microsoft NDIS Large Send
1711 			 * specification which requires insertion of
1712 			 * pseudo checksum by upper stack. The pseudo
1713 			 * checksum that NDIS refers to doesn't include
1714 			 * TCP payload length so ale(4) should recompute
1715 			 * the pseudo checksum here. Hopefully this wouldn't
1716 			 * be much burden on modern CPUs.
1717 			 * Reset IP checksum and recompute TCP pseudo
1718 			 * checksum as NDIS specification said.
1719 			 */
1720 			ip->ip_sum = 0;
1721 			tcp->th_sum = in_pseudo(ip->ip_src.s_addr,
1722 			    ip->ip_dst.s_addr, htons(IPPROTO_TCP));
1723 		}
1724 		*m_head = m;
1725 	}
1726 
1727 	si = prod = sc->ale_cdata.ale_tx_prod;
1728 	txd = &sc->ale_cdata.ale_txdesc[prod];
1729 	txd_last = txd;
1730 	map = txd->tx_dmamap;
1731 
1732 	error =  bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map,
1733 	    *m_head, txsegs, &nsegs, 0);
1734 	if (error == EFBIG) {
1735 		m = m_collapse(*m_head, M_NOWAIT, ALE_MAXTXSEGS);
1736 		if (m == NULL) {
1737 			m_freem(*m_head);
1738 			*m_head = NULL;
1739 			return (ENOMEM);
1740 		}
1741 		*m_head = m;
1742 		error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map,
1743 		    *m_head, txsegs, &nsegs, 0);
1744 		if (error != 0) {
1745 			m_freem(*m_head);
1746 			*m_head = NULL;
1747 			return (error);
1748 		}
1749 	} else if (error != 0)
1750 		return (error);
1751 	if (nsegs == 0) {
1752 		m_freem(*m_head);
1753 		*m_head = NULL;
1754 		return (EIO);
1755 	}
1756 
1757 	/* Check descriptor overrun. */
1758 	if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 3) {
1759 		bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, map);
1760 		return (ENOBUFS);
1761 	}
1762 	bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, map, BUS_DMASYNC_PREWRITE);
1763 
1764 	m = *m_head;
1765 	if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1766 		/* Request TSO and set MSS. */
1767 		cflags |= ALE_TD_TSO;
1768 		cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << ALE_TD_MSS_SHIFT);
1769 		/* Set IP/TCP header size. */
1770 		cflags |= ip->ip_hl << ALE_TD_IPHDR_LEN_SHIFT;
1771 		cflags |= tcp->th_off << ALE_TD_TCPHDR_LEN_SHIFT;
1772 	} else if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) {
1773 		/*
1774 		 * AR81xx supports Tx custom checksum offload feature
1775 		 * that offloads single 16bit checksum computation.
1776 		 * So you can choose one among IP, TCP and UDP.
1777 		 * Normally driver sets checksum start/insertion
1778 		 * position from the information of TCP/UDP frame as
1779 		 * TCP/UDP checksum takes more time than that of IP.
1780 		 * However it seems that custom checksum offload
1781 		 * requires 4 bytes aligned Tx buffers due to hardware
1782 		 * bug.
1783 		 * AR81xx also supports explicit Tx checksum computation
1784 		 * if it is told that the size of IP header and TCP
1785 		 * header(for UDP, the header size does not matter
1786 		 * because it's fixed length). However with this scheme
1787 		 * TSO does not work so you have to choose one either
1788 		 * TSO or explicit Tx checksum offload. I chosen TSO
1789 		 * plus custom checksum offload with work-around which
1790 		 * will cover most common usage for this consumer
1791 		 * ethernet controller. The work-around takes a lot of
1792 		 * CPU cycles if Tx buffer is not aligned on 4 bytes
1793 		 * boundary, though.
1794 		 */
1795 		cflags |= ALE_TD_CXSUM;
1796 		/* Set checksum start offset. */
1797 		cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT);
1798 		/* Set checksum insertion position of TCP/UDP. */
1799 		cflags |= ((poff + m->m_pkthdr.csum_data) <<
1800 		    ALE_TD_CSUM_XSUMOFFSET_SHIFT);
1801 	}
1802 
1803 	/* Configure VLAN hardware tag insertion. */
1804 	if ((m->m_flags & M_VLANTAG) != 0) {
1805 		vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag);
1806 		vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK);
1807 		cflags |= ALE_TD_INSERT_VLAN_TAG;
1808 	}
1809 
1810 	i = 0;
1811 	if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1812 		/*
1813 		 * Make sure the first fragment contains
1814 		 * only ethernet and IP/TCP header with options.
1815 		 */
1816 		hdrlen =  poff + (tcp->th_off << 2);
1817 		desc = &sc->ale_cdata.ale_tx_ring[prod];
1818 		desc->addr = htole64(txsegs[i].ds_addr);
1819 		desc->len = htole32(ALE_TX_BYTES(hdrlen) | vtag);
1820 		desc->flags = htole32(cflags);
1821 		sc->ale_cdata.ale_tx_cnt++;
1822 		ALE_DESC_INC(prod, ALE_TX_RING_CNT);
1823 		if (m->m_len - hdrlen > 0) {
1824 			/* Handle remaining payload of the first fragment. */
1825 			desc = &sc->ale_cdata.ale_tx_ring[prod];
1826 			desc->addr = htole64(txsegs[i].ds_addr + hdrlen);
1827 			desc->len = htole32(ALE_TX_BYTES(m->m_len - hdrlen) |
1828 			    vtag);
1829 			desc->flags = htole32(cflags);
1830 			sc->ale_cdata.ale_tx_cnt++;
1831 			ALE_DESC_INC(prod, ALE_TX_RING_CNT);
1832 		}
1833 		i = 1;
1834 	}
1835 	for (; i < nsegs; i++) {
1836 		desc = &sc->ale_cdata.ale_tx_ring[prod];
1837 		desc->addr = htole64(txsegs[i].ds_addr);
1838 		desc->len = htole32(ALE_TX_BYTES(txsegs[i].ds_len) | vtag);
1839 		desc->flags = htole32(cflags);
1840 		sc->ale_cdata.ale_tx_cnt++;
1841 		ALE_DESC_INC(prod, ALE_TX_RING_CNT);
1842 	}
1843 	/* Update producer index. */
1844 	sc->ale_cdata.ale_tx_prod = prod;
1845 	/* Set TSO header on the first descriptor. */
1846 	if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) {
1847 		desc = &sc->ale_cdata.ale_tx_ring[si];
1848 		desc->flags |= htole32(ALE_TD_TSO_HDR);
1849 	}
1850 
1851 	/* Finally set EOP on the last descriptor. */
1852 	prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT;
1853 	desc = &sc->ale_cdata.ale_tx_ring[prod];
1854 	desc->flags |= htole32(ALE_TD_EOP);
1855 
1856 	/* Swap dmamap of the first and the last. */
1857 	txd = &sc->ale_cdata.ale_txdesc[prod];
1858 	map = txd_last->tx_dmamap;
1859 	txd_last->tx_dmamap = txd->tx_dmamap;
1860 	txd->tx_dmamap = map;
1861 	txd->tx_m = m;
1862 
1863 	/* Sync descriptors. */
1864 	bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
1865 	    sc->ale_cdata.ale_tx_ring_map,
1866 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
1867 
1868 	return (0);
1869 }
1870 
1871 static void
1872 ale_start(struct ifnet *ifp)
1873 {
1874         struct ale_softc *sc;
1875 
1876 	sc = ifp->if_softc;
1877 	ALE_LOCK(sc);
1878 	ale_start_locked(ifp);
1879 	ALE_UNLOCK(sc);
1880 }
1881 
1882 static void
1883 ale_start_locked(struct ifnet *ifp)
1884 {
1885         struct ale_softc *sc;
1886         struct mbuf *m_head;
1887 	int enq;
1888 
1889 	sc = ifp->if_softc;
1890 
1891 	ALE_LOCK_ASSERT(sc);
1892 
1893 	/* Reclaim transmitted frames. */
1894 	if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT)
1895 		ale_txeof(sc);
1896 
1897 	if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) !=
1898 	    IFF_DRV_RUNNING || (sc->ale_flags & ALE_FLAG_LINK) == 0)
1899 		return;
1900 
1901 	for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) {
1902 		IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
1903 		if (m_head == NULL)
1904 			break;
1905 		/*
1906 		 * Pack the data into the transmit ring. If we
1907 		 * don't have room, set the OACTIVE flag and wait
1908 		 * for the NIC to drain the ring.
1909 		 */
1910 		if (ale_encap(sc, &m_head)) {
1911 			if (m_head == NULL)
1912 				break;
1913 			IFQ_DRV_PREPEND(&ifp->if_snd, m_head);
1914 			ifp->if_drv_flags |= IFF_DRV_OACTIVE;
1915 			break;
1916 		}
1917 
1918 		enq++;
1919 		/*
1920 		 * If there's a BPF listener, bounce a copy of this frame
1921 		 * to him.
1922 		 */
1923 		ETHER_BPF_MTAP(ifp, m_head);
1924 	}
1925 
1926 	if (enq > 0) {
1927 		/* Kick. */
1928 		CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX,
1929 		    sc->ale_cdata.ale_tx_prod);
1930 		/* Set a timeout in case the chip goes out to lunch. */
1931 		sc->ale_watchdog_timer = ALE_TX_TIMEOUT;
1932 	}
1933 }
1934 
1935 static void
1936 ale_watchdog(struct ale_softc *sc)
1937 {
1938 	struct ifnet *ifp;
1939 
1940 	ALE_LOCK_ASSERT(sc);
1941 
1942 	if (sc->ale_watchdog_timer == 0 || --sc->ale_watchdog_timer)
1943 		return;
1944 
1945 	ifp = sc->ale_ifp;
1946 	if ((sc->ale_flags & ALE_FLAG_LINK) == 0) {
1947 		if_printf(sc->ale_ifp, "watchdog timeout (lost link)\n");
1948 		if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1949 		ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1950 		ale_init_locked(sc);
1951 		return;
1952 	}
1953 	if_printf(sc->ale_ifp, "watchdog timeout -- resetting\n");
1954 	if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
1955 	ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1956 	ale_init_locked(sc);
1957 	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
1958 		ale_start_locked(ifp);
1959 }
1960 
1961 static int
1962 ale_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1963 {
1964 	struct ale_softc *sc;
1965 	struct ifreq *ifr;
1966 	struct mii_data *mii;
1967 	int error, mask;
1968 
1969 	sc = ifp->if_softc;
1970 	ifr = (struct ifreq *)data;
1971 	error = 0;
1972 	switch (cmd) {
1973 	case SIOCSIFMTU:
1974 		if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALE_JUMBO_MTU ||
1975 		    ((sc->ale_flags & ALE_FLAG_JUMBO) == 0 &&
1976 		    ifr->ifr_mtu > ETHERMTU))
1977 			error = EINVAL;
1978 		else if (ifp->if_mtu != ifr->ifr_mtu) {
1979 			ALE_LOCK(sc);
1980 			ifp->if_mtu = ifr->ifr_mtu;
1981 			if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1982 				ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
1983 				ale_init_locked(sc);
1984 			}
1985 			ALE_UNLOCK(sc);
1986 		}
1987 		break;
1988 	case SIOCSIFFLAGS:
1989 		ALE_LOCK(sc);
1990 		if ((ifp->if_flags & IFF_UP) != 0) {
1991 			if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
1992 				if (((ifp->if_flags ^ sc->ale_if_flags)
1993 				    & (IFF_PROMISC | IFF_ALLMULTI)) != 0)
1994 					ale_rxfilter(sc);
1995 			} else {
1996 				ale_init_locked(sc);
1997 			}
1998 		} else {
1999 			if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2000 				ale_stop(sc);
2001 		}
2002 		sc->ale_if_flags = ifp->if_flags;
2003 		ALE_UNLOCK(sc);
2004 		break;
2005 	case SIOCADDMULTI:
2006 	case SIOCDELMULTI:
2007 		ALE_LOCK(sc);
2008 		if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2009 			ale_rxfilter(sc);
2010 		ALE_UNLOCK(sc);
2011 		break;
2012 	case SIOCSIFMEDIA:
2013 	case SIOCGIFMEDIA:
2014 		mii = device_get_softc(sc->ale_miibus);
2015 		error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
2016 		break;
2017 	case SIOCSIFCAP:
2018 		ALE_LOCK(sc);
2019 		mask = ifr->ifr_reqcap ^ ifp->if_capenable;
2020 		if ((mask & IFCAP_TXCSUM) != 0 &&
2021 		    (ifp->if_capabilities & IFCAP_TXCSUM) != 0) {
2022 			ifp->if_capenable ^= IFCAP_TXCSUM;
2023 			if ((ifp->if_capenable & IFCAP_TXCSUM) != 0)
2024 				ifp->if_hwassist |= ALE_CSUM_FEATURES;
2025 			else
2026 				ifp->if_hwassist &= ~ALE_CSUM_FEATURES;
2027 		}
2028 		if ((mask & IFCAP_RXCSUM) != 0 &&
2029 		    (ifp->if_capabilities & IFCAP_RXCSUM) != 0)
2030 			ifp->if_capenable ^= IFCAP_RXCSUM;
2031 		if ((mask & IFCAP_TSO4) != 0 &&
2032 		    (ifp->if_capabilities & IFCAP_TSO4) != 0) {
2033 			ifp->if_capenable ^= IFCAP_TSO4;
2034 			if ((ifp->if_capenable & IFCAP_TSO4) != 0)
2035 				ifp->if_hwassist |= CSUM_TSO;
2036 			else
2037 				ifp->if_hwassist &= ~CSUM_TSO;
2038 		}
2039 
2040 		if ((mask & IFCAP_WOL_MCAST) != 0 &&
2041 		    (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0)
2042 			ifp->if_capenable ^= IFCAP_WOL_MCAST;
2043 		if ((mask & IFCAP_WOL_MAGIC) != 0 &&
2044 		    (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0)
2045 			ifp->if_capenable ^= IFCAP_WOL_MAGIC;
2046 		if ((mask & IFCAP_VLAN_HWCSUM) != 0 &&
2047 		    (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0)
2048 			ifp->if_capenable ^= IFCAP_VLAN_HWCSUM;
2049 		if ((mask & IFCAP_VLAN_HWTSO) != 0 &&
2050 		    (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0)
2051 			ifp->if_capenable ^= IFCAP_VLAN_HWTSO;
2052 		if ((mask & IFCAP_VLAN_HWTAGGING) != 0 &&
2053 		    (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) {
2054 			ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING;
2055 			if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0)
2056 				ifp->if_capenable &= ~IFCAP_VLAN_HWTSO;
2057 			ale_rxvlan(sc);
2058 		}
2059 		ALE_UNLOCK(sc);
2060 		VLAN_CAPABILITIES(ifp);
2061 		break;
2062 	default:
2063 		error = ether_ioctl(ifp, cmd, data);
2064 		break;
2065 	}
2066 
2067 	return (error);
2068 }
2069 
2070 static void
2071 ale_mac_config(struct ale_softc *sc)
2072 {
2073 	struct mii_data *mii;
2074 	uint32_t reg;
2075 
2076 	ALE_LOCK_ASSERT(sc);
2077 
2078 	mii = device_get_softc(sc->ale_miibus);
2079 	reg = CSR_READ_4(sc, ALE_MAC_CFG);
2080 	reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC |
2081 	    MAC_CFG_SPEED_MASK);
2082 	/* Reprogram MAC with resolved speed/duplex. */
2083 	switch (IFM_SUBTYPE(mii->mii_media_active)) {
2084 	case IFM_10_T:
2085 	case IFM_100_TX:
2086 		reg |= MAC_CFG_SPEED_10_100;
2087 		break;
2088 	case IFM_1000_T:
2089 		reg |= MAC_CFG_SPEED_1000;
2090 		break;
2091 	}
2092 	if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) {
2093 		reg |= MAC_CFG_FULL_DUPLEX;
2094 		if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0)
2095 			reg |= MAC_CFG_TX_FC;
2096 		if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0)
2097 			reg |= MAC_CFG_RX_FC;
2098 	}
2099 	CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2100 }
2101 
2102 static void
2103 ale_stats_clear(struct ale_softc *sc)
2104 {
2105 	struct smb sb;
2106 	uint32_t *reg;
2107 	int i;
2108 
2109 	for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {
2110 		CSR_READ_4(sc, ALE_RX_MIB_BASE + i);
2111 		i += sizeof(uint32_t);
2112 	}
2113 	/* Read Tx statistics. */
2114 	for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {
2115 		CSR_READ_4(sc, ALE_TX_MIB_BASE + i);
2116 		i += sizeof(uint32_t);
2117 	}
2118 }
2119 
2120 static void
2121 ale_stats_update(struct ale_softc *sc)
2122 {
2123 	struct ale_hw_stats *stat;
2124 	struct smb sb, *smb;
2125 	struct ifnet *ifp;
2126 	uint32_t *reg;
2127 	int i;
2128 
2129 	ALE_LOCK_ASSERT(sc);
2130 
2131 	ifp = sc->ale_ifp;
2132 	stat = &sc->ale_stats;
2133 	smb = &sb;
2134 
2135 	/* Read Rx statistics. */
2136 	for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) {
2137 		*reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i);
2138 		i += sizeof(uint32_t);
2139 	}
2140 	/* Read Tx statistics. */
2141 	for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) {
2142 		*reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i);
2143 		i += sizeof(uint32_t);
2144 	}
2145 
2146 	/* Rx stats. */
2147 	stat->rx_frames += smb->rx_frames;
2148 	stat->rx_bcast_frames += smb->rx_bcast_frames;
2149 	stat->rx_mcast_frames += smb->rx_mcast_frames;
2150 	stat->rx_pause_frames += smb->rx_pause_frames;
2151 	stat->rx_control_frames += smb->rx_control_frames;
2152 	stat->rx_crcerrs += smb->rx_crcerrs;
2153 	stat->rx_lenerrs += smb->rx_lenerrs;
2154 	stat->rx_bytes += smb->rx_bytes;
2155 	stat->rx_runts += smb->rx_runts;
2156 	stat->rx_fragments += smb->rx_fragments;
2157 	stat->rx_pkts_64 += smb->rx_pkts_64;
2158 	stat->rx_pkts_65_127 += smb->rx_pkts_65_127;
2159 	stat->rx_pkts_128_255 += smb->rx_pkts_128_255;
2160 	stat->rx_pkts_256_511 += smb->rx_pkts_256_511;
2161 	stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023;
2162 	stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518;
2163 	stat->rx_pkts_1519_max += smb->rx_pkts_1519_max;
2164 	stat->rx_pkts_truncated += smb->rx_pkts_truncated;
2165 	stat->rx_fifo_oflows += smb->rx_fifo_oflows;
2166 	stat->rx_rrs_errs += smb->rx_rrs_errs;
2167 	stat->rx_alignerrs += smb->rx_alignerrs;
2168 	stat->rx_bcast_bytes += smb->rx_bcast_bytes;
2169 	stat->rx_mcast_bytes += smb->rx_mcast_bytes;
2170 	stat->rx_pkts_filtered += smb->rx_pkts_filtered;
2171 
2172 	/* Tx stats. */
2173 	stat->tx_frames += smb->tx_frames;
2174 	stat->tx_bcast_frames += smb->tx_bcast_frames;
2175 	stat->tx_mcast_frames += smb->tx_mcast_frames;
2176 	stat->tx_pause_frames += smb->tx_pause_frames;
2177 	stat->tx_excess_defer += smb->tx_excess_defer;
2178 	stat->tx_control_frames += smb->tx_control_frames;
2179 	stat->tx_deferred += smb->tx_deferred;
2180 	stat->tx_bytes += smb->tx_bytes;
2181 	stat->tx_pkts_64 += smb->tx_pkts_64;
2182 	stat->tx_pkts_65_127 += smb->tx_pkts_65_127;
2183 	stat->tx_pkts_128_255 += smb->tx_pkts_128_255;
2184 	stat->tx_pkts_256_511 += smb->tx_pkts_256_511;
2185 	stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023;
2186 	stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518;
2187 	stat->tx_pkts_1519_max += smb->tx_pkts_1519_max;
2188 	stat->tx_single_colls += smb->tx_single_colls;
2189 	stat->tx_multi_colls += smb->tx_multi_colls;
2190 	stat->tx_late_colls += smb->tx_late_colls;
2191 	stat->tx_excess_colls += smb->tx_excess_colls;
2192 	stat->tx_underrun += smb->tx_underrun;
2193 	stat->tx_desc_underrun += smb->tx_desc_underrun;
2194 	stat->tx_lenerrs += smb->tx_lenerrs;
2195 	stat->tx_pkts_truncated += smb->tx_pkts_truncated;
2196 	stat->tx_bcast_bytes += smb->tx_bcast_bytes;
2197 	stat->tx_mcast_bytes += smb->tx_mcast_bytes;
2198 
2199 	/* Update counters in ifnet. */
2200 	if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames);
2201 
2202 	if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls +
2203 	    smb->tx_multi_colls * 2 + smb->tx_late_colls +
2204 	    smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT);
2205 
2206 	if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_late_colls +
2207 	    smb->tx_excess_colls + smb->tx_underrun + smb->tx_pkts_truncated);
2208 
2209 	if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames);
2210 
2211 	if_inc_counter(ifp, IFCOUNTER_IERRORS,
2212 	    smb->rx_crcerrs + smb->rx_lenerrs +
2213 	    smb->rx_runts + smb->rx_pkts_truncated +
2214 	    smb->rx_fifo_oflows + smb->rx_rrs_errs +
2215 	    smb->rx_alignerrs);
2216 }
2217 
2218 static int
2219 ale_intr(void *arg)
2220 {
2221 	struct ale_softc *sc;
2222 	uint32_t status;
2223 
2224 	sc = (struct ale_softc *)arg;
2225 
2226 	status = CSR_READ_4(sc, ALE_INTR_STATUS);
2227 	if ((status & ALE_INTRS) == 0)
2228 		return (FILTER_STRAY);
2229 	/* Disable interrupts. */
2230 	CSR_WRITE_4(sc, ALE_INTR_STATUS, INTR_DIS_INT);
2231 	taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task);
2232 
2233 	return (FILTER_HANDLED);
2234 }
2235 
2236 static void
2237 ale_int_task(void *arg, int pending)
2238 {
2239 	struct ale_softc *sc;
2240 	struct ifnet *ifp;
2241 	uint32_t status;
2242 	int more;
2243 
2244 	sc = (struct ale_softc *)arg;
2245 
2246 	status = CSR_READ_4(sc, ALE_INTR_STATUS);
2247 	ALE_LOCK(sc);
2248 	if (sc->ale_morework != 0)
2249 		status |= INTR_RX_PKT;
2250 	if ((status & ALE_INTRS) == 0)
2251 		goto done;
2252 
2253 	/* Acknowledge interrupts but still disable interrupts. */
2254 	CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT);
2255 
2256 	ifp = sc->ale_ifp;
2257 	more = 0;
2258 	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) {
2259 		more = ale_rxeof(sc, sc->ale_process_limit);
2260 		if (more == EAGAIN)
2261 			sc->ale_morework = 1;
2262 		else if (more == EIO) {
2263 			sc->ale_stats.reset_brk_seq++;
2264 			ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2265 			ale_init_locked(sc);
2266 			ALE_UNLOCK(sc);
2267 			return;
2268 		}
2269 
2270 		if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) {
2271 			if ((status & INTR_DMA_RD_TO_RST) != 0)
2272 				device_printf(sc->ale_dev,
2273 				    "DMA read error! -- resetting\n");
2274 			if ((status & INTR_DMA_WR_TO_RST) != 0)
2275 				device_printf(sc->ale_dev,
2276 				    "DMA write error! -- resetting\n");
2277 			ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
2278 			ale_init_locked(sc);
2279 			ALE_UNLOCK(sc);
2280 			return;
2281 		}
2282 		if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
2283 			ale_start_locked(ifp);
2284 	}
2285 
2286 	if (more == EAGAIN ||
2287 	    (CSR_READ_4(sc, ALE_INTR_STATUS) & ALE_INTRS) != 0) {
2288 		ALE_UNLOCK(sc);
2289 		taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task);
2290 		return;
2291 	}
2292 
2293 done:
2294 	ALE_UNLOCK(sc);
2295 
2296 	/* Re-enable interrupts. */
2297 	CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF);
2298 }
2299 
2300 static void
2301 ale_txeof(struct ale_softc *sc)
2302 {
2303 	struct ifnet *ifp;
2304 	struct ale_txdesc *txd;
2305 	uint32_t cons, prod;
2306 	int prog;
2307 
2308 	ALE_LOCK_ASSERT(sc);
2309 
2310 	ifp = sc->ale_ifp;
2311 
2312 	if (sc->ale_cdata.ale_tx_cnt == 0)
2313 		return;
2314 
2315 	bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
2316 	    sc->ale_cdata.ale_tx_ring_map,
2317 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2318 	if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) {
2319 		bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag,
2320 		    sc->ale_cdata.ale_tx_cmb_map,
2321 		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2322 		prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK;
2323 	} else
2324 		prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX);
2325 	cons = sc->ale_cdata.ale_tx_cons;
2326 	/*
2327 	 * Go through our Tx list and free mbufs for those
2328 	 * frames which have been transmitted.
2329 	 */
2330 	for (prog = 0; cons != prod; prog++,
2331 	    ALE_DESC_INC(cons, ALE_TX_RING_CNT)) {
2332 		if (sc->ale_cdata.ale_tx_cnt <= 0)
2333 			break;
2334 		prog++;
2335 		ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2336 		sc->ale_cdata.ale_tx_cnt--;
2337 		txd = &sc->ale_cdata.ale_txdesc[cons];
2338 		if (txd->tx_m != NULL) {
2339 			/* Reclaim transmitted mbufs. */
2340 			bus_dmamap_sync(sc->ale_cdata.ale_tx_tag,
2341 			    txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2342 			bus_dmamap_unload(sc->ale_cdata.ale_tx_tag,
2343 			    txd->tx_dmamap);
2344 			m_freem(txd->tx_m);
2345 			txd->tx_m = NULL;
2346 		}
2347 	}
2348 
2349 	if (prog > 0) {
2350 		sc->ale_cdata.ale_tx_cons = cons;
2351 		/*
2352 		 * Unarm watchdog timer only when there is no pending
2353 		 * Tx descriptors in queue.
2354 		 */
2355 		if (sc->ale_cdata.ale_tx_cnt == 0)
2356 			sc->ale_watchdog_timer = 0;
2357 	}
2358 }
2359 
2360 static void
2361 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page,
2362     uint32_t length, uint32_t *prod)
2363 {
2364 	struct ale_rx_page *rx_page;
2365 
2366 	rx_page = *page;
2367 	/* Update consumer position. */
2368 	rx_page->cons += roundup(length + sizeof(struct rx_rs),
2369 	    ALE_RX_PAGE_ALIGN);
2370 	if (rx_page->cons >= ALE_RX_PAGE_SZ) {
2371 		/*
2372 		 * End of Rx page reached, let hardware reuse
2373 		 * this page.
2374 		 */
2375 		rx_page->cons = 0;
2376 		*rx_page->cmb_addr = 0;
2377 		bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2378 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2379 		CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp,
2380 		    RXF_VALID);
2381 		/* Switch to alternate Rx page. */
2382 		sc->ale_cdata.ale_rx_curp ^= 1;
2383 		rx_page = *page =
2384 		    &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp];
2385 		/* Page flipped, sync CMB and Rx page. */
2386 		bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2387 		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2388 		bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2389 		    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2390 		/* Sync completed, cache updated producer index. */
2391 		*prod = *rx_page->cmb_addr;
2392 	}
2393 }
2394 
2395 /*
2396  * It seems that AR81xx controller can compute partial checksum.
2397  * The partial checksum value can be used to accelerate checksum
2398  * computation for fragmented TCP/UDP packets. Upper network stack
2399  * already takes advantage of the partial checksum value in IP
2400  * reassembly stage. But I'm not sure the correctness of the
2401  * partial hardware checksum assistance due to lack of data sheet.
2402  * In addition, the Rx feature of controller that requires copying
2403  * for every frames effectively nullifies one of most nice offload
2404  * capability of controller.
2405  */
2406 static void
2407 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status)
2408 {
2409 	struct ifnet *ifp;
2410 	struct ip *ip;
2411 	char *p;
2412 
2413 	ifp = sc->ale_ifp;
2414 	m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED;
2415 	if ((status & ALE_RD_IPCSUM_NOK) == 0)
2416 		m->m_pkthdr.csum_flags |= CSUM_IP_VALID;
2417 
2418 	if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) {
2419 		if (((status & ALE_RD_IPV4_FRAG) == 0) &&
2420 		    ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) &&
2421 		    ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) {
2422 			m->m_pkthdr.csum_flags |=
2423 			    CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
2424 			m->m_pkthdr.csum_data = 0xffff;
2425 		}
2426 	} else {
2427 		if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 &&
2428 		    (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) {
2429 			p = mtod(m, char *);
2430 			p += ETHER_HDR_LEN;
2431 			if ((status & ALE_RD_802_3) != 0)
2432 				p += LLC_SNAPFRAMELEN;
2433 			if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0 &&
2434 			    (status & ALE_RD_VLAN) != 0)
2435 				p += ETHER_VLAN_ENCAP_LEN;
2436 			ip = (struct ip *)p;
2437 			if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0)
2438 				return;
2439 			m->m_pkthdr.csum_flags |= CSUM_DATA_VALID |
2440 			    CSUM_PSEUDO_HDR;
2441 			m->m_pkthdr.csum_data = 0xffff;
2442 		}
2443 	}
2444 	/*
2445 	 * Don't mark bad checksum for TCP/UDP frames
2446 	 * as fragmented frames may always have set
2447 	 * bad checksummed bit of frame status.
2448 	 */
2449 }
2450 
2451 /* Process received frames. */
2452 static int
2453 ale_rxeof(struct ale_softc *sc, int count)
2454 {
2455 	struct ale_rx_page *rx_page;
2456 	struct rx_rs *rs;
2457 	struct ifnet *ifp;
2458 	struct mbuf *m;
2459 	uint32_t length, prod, seqno, status, vtags;
2460 	int prog;
2461 
2462 	ifp = sc->ale_ifp;
2463 	rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp];
2464 	bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2465 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2466 	bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2467 	    BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
2468 	/*
2469 	 * Don't directly access producer index as hardware may
2470 	 * update it while Rx handler is in progress. It would
2471 	 * be even better if there is a way to let hardware
2472 	 * know how far driver processed its received frames.
2473 	 * Alternatively, hardware could provide a way to disable
2474 	 * CMB updates until driver acknowledges the end of CMB
2475 	 * access.
2476 	 */
2477 	prod = *rx_page->cmb_addr;
2478 	for (prog = 0; prog < count; prog++) {
2479 		if (rx_page->cons >= prod)
2480 			break;
2481 		rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons);
2482 		seqno = ALE_RX_SEQNO(le32toh(rs->seqno));
2483 		if (sc->ale_cdata.ale_rx_seqno != seqno) {
2484 			/*
2485 			 * Normally I believe this should not happen unless
2486 			 * severe driver bug or corrupted memory. However
2487 			 * it seems to happen under certain conditions which
2488 			 * is triggered by abrupt Rx events such as initiation
2489 			 * of bulk transfer of remote host. It's not easy to
2490 			 * reproduce this and I doubt it could be related
2491 			 * with FIFO overflow of hardware or activity of Tx
2492 			 * CMB updates. I also remember similar behaviour
2493 			 * seen on RealTek 8139 which uses resembling Rx
2494 			 * scheme.
2495 			 */
2496 			if (bootverbose)
2497 				device_printf(sc->ale_dev,
2498 				    "garbled seq: %u, expected: %u -- "
2499 				    "resetting!\n", seqno,
2500 				    sc->ale_cdata.ale_rx_seqno);
2501 			return (EIO);
2502 		}
2503 		/* Frame received. */
2504 		sc->ale_cdata.ale_rx_seqno++;
2505 		length = ALE_RX_BYTES(le32toh(rs->length));
2506 		status = le32toh(rs->flags);
2507 		if ((status & ALE_RD_ERROR) != 0) {
2508 			/*
2509 			 * We want to pass the following frames to upper
2510 			 * layer regardless of error status of Rx return
2511 			 * status.
2512 			 *
2513 			 *  o IP/TCP/UDP checksum is bad.
2514 			 *  o frame length and protocol specific length
2515 			 *     does not match.
2516 			 */
2517 			if ((status & (ALE_RD_CRC | ALE_RD_CODE |
2518 			    ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW |
2519 			    ALE_RD_TRUNC)) != 0) {
2520 				ale_rx_update_page(sc, &rx_page, length, &prod);
2521 				continue;
2522 			}
2523 		}
2524 		/*
2525 		 * m_devget(9) is major bottle-neck of ale(4)(It comes
2526 		 * from hardware limitation). For jumbo frames we could
2527 		 * get a slightly better performance if driver use
2528 		 * m_getjcl(9) with proper buffer size argument. However
2529 		 * that would make code more complicated and I don't
2530 		 * think users would expect good Rx performance numbers
2531 		 * on these low-end consumer ethernet controller.
2532 		 */
2533 		m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN,
2534 		    ETHER_ALIGN, ifp, NULL);
2535 		if (m == NULL) {
2536 			if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1);
2537 			ale_rx_update_page(sc, &rx_page, length, &prod);
2538 			continue;
2539 		}
2540 		if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 &&
2541 		    (status & ALE_RD_IPV4) != 0)
2542 			ale_rxcsum(sc, m, status);
2543 		if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 &&
2544 		    (status & ALE_RD_VLAN) != 0) {
2545 			vtags = ALE_RX_VLAN(le32toh(rs->vtags));
2546 			m->m_pkthdr.ether_vtag = ALE_RX_VLAN_TAG(vtags);
2547 			m->m_flags |= M_VLANTAG;
2548 		}
2549 
2550 		/* Pass it to upper layer. */
2551 		ALE_UNLOCK(sc);
2552 		(*ifp->if_input)(ifp, m);
2553 		ALE_LOCK(sc);
2554 
2555 		ale_rx_update_page(sc, &rx_page, length, &prod);
2556 	}
2557 
2558 	return (count > 0 ? 0 : EAGAIN);
2559 }
2560 
2561 static void
2562 ale_tick(void *arg)
2563 {
2564 	struct ale_softc *sc;
2565 	struct mii_data *mii;
2566 
2567 	sc = (struct ale_softc *)arg;
2568 
2569 	ALE_LOCK_ASSERT(sc);
2570 
2571 	mii = device_get_softc(sc->ale_miibus);
2572 	mii_tick(mii);
2573 	ale_stats_update(sc);
2574 	/*
2575 	 * Reclaim Tx buffers that have been transferred. It's not
2576 	 * needed here but it would release allocated mbuf chains
2577 	 * faster and limit the maximum delay to a hz.
2578 	 */
2579 	ale_txeof(sc);
2580 	ale_watchdog(sc);
2581 	callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc);
2582 }
2583 
2584 static void
2585 ale_reset(struct ale_softc *sc)
2586 {
2587 	uint32_t reg;
2588 	int i;
2589 
2590 	/* Initialize PCIe module. From Linux. */
2591 	CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000);
2592 
2593 	CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET);
2594 	for (i = ALE_RESET_TIMEOUT; i > 0; i--) {
2595 		DELAY(10);
2596 		if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0)
2597 			break;
2598 	}
2599 	if (i == 0)
2600 		device_printf(sc->ale_dev, "master reset timeout!\n");
2601 
2602 	for (i = ALE_RESET_TIMEOUT; i > 0; i--) {
2603 		if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0)
2604 			break;
2605 		DELAY(10);
2606 	}
2607 
2608 	if (i == 0)
2609 		device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg);
2610 }
2611 
2612 static void
2613 ale_init(void *xsc)
2614 {
2615 	struct ale_softc *sc;
2616 
2617 	sc = (struct ale_softc *)xsc;
2618 	ALE_LOCK(sc);
2619 	ale_init_locked(sc);
2620 	ALE_UNLOCK(sc);
2621 }
2622 
2623 static void
2624 ale_init_locked(struct ale_softc *sc)
2625 {
2626 	struct ifnet *ifp;
2627 	struct mii_data *mii;
2628 	uint8_t eaddr[ETHER_ADDR_LEN];
2629 	bus_addr_t paddr;
2630 	uint32_t reg, rxf_hi, rxf_lo;
2631 
2632 	ALE_LOCK_ASSERT(sc);
2633 
2634 	ifp = sc->ale_ifp;
2635 	mii = device_get_softc(sc->ale_miibus);
2636 
2637 	if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0)
2638 		return;
2639 	/*
2640 	 * Cancel any pending I/O.
2641 	 */
2642 	ale_stop(sc);
2643 	/*
2644 	 * Reset the chip to a known state.
2645 	 */
2646 	ale_reset(sc);
2647 	/* Initialize Tx descriptors, DMA memory blocks. */
2648 	ale_init_rx_pages(sc);
2649 	ale_init_tx_ring(sc);
2650 
2651 	/* Reprogram the station address. */
2652 	bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN);
2653 	CSR_WRITE_4(sc, ALE_PAR0,
2654 	    eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]);
2655 	CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]);
2656 	/*
2657 	 * Clear WOL status and disable all WOL feature as WOL
2658 	 * would interfere Rx operation under normal environments.
2659 	 */
2660 	CSR_READ_4(sc, ALE_WOL_CFG);
2661 	CSR_WRITE_4(sc, ALE_WOL_CFG, 0);
2662 	/*
2663 	 * Set Tx descriptor/RXF0/CMB base addresses. They share
2664 	 * the same high address part of DMAable region.
2665 	 */
2666 	paddr = sc->ale_cdata.ale_tx_ring_paddr;
2667 	CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr));
2668 	CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr));
2669 	CSR_WRITE_4(sc, ALE_TPD_CNT,
2670 	    (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK);
2671 	/* Set Rx page base address, note we use single queue. */
2672 	paddr = sc->ale_cdata.ale_rx_page[0].page_paddr;
2673 	CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr));
2674 	paddr = sc->ale_cdata.ale_rx_page[1].page_paddr;
2675 	CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr));
2676 	/* Set Tx/Rx CMB addresses. */
2677 	paddr = sc->ale_cdata.ale_tx_cmb_paddr;
2678 	CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr));
2679 	paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr;
2680 	CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr));
2681 	paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr;
2682 	CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr));
2683 	/* Mark RXF0 is valid. */
2684 	CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID);
2685 	CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID);
2686 	/*
2687 	 * No need to initialize RFX1/RXF2/RXF3. We don't use
2688 	 * multi-queue yet.
2689 	 */
2690 
2691 	/* Set Rx page size, excluding guard frame size. */
2692 	CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ);
2693 	/* Tell hardware that we're ready to load DMA blocks. */
2694 	CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD);
2695 
2696 	/* Set Rx/Tx interrupt trigger threshold. */
2697 	CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) |
2698 	    (4 << INT_TRIG_TX_THRESH_SHIFT));
2699 	/*
2700 	 * XXX
2701 	 * Set interrupt trigger timer, its purpose and relation
2702 	 * with interrupt moderation mechanism is not clear yet.
2703 	 */
2704 	CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER,
2705 	    ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) |
2706 	    (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT)));
2707 
2708 	/* Configure interrupt moderation timer. */
2709 	reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT;
2710 	reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT;
2711 	CSR_WRITE_4(sc, ALE_IM_TIMER, reg);
2712 	reg = CSR_READ_4(sc, ALE_MASTER_CFG);
2713 	reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK);
2714 	reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB);
2715 	if (ALE_USECS(sc->ale_int_rx_mod) != 0)
2716 		reg |= MASTER_IM_RX_TIMER_ENB;
2717 	if (ALE_USECS(sc->ale_int_tx_mod) != 0)
2718 		reg |= MASTER_IM_TX_TIMER_ENB;
2719 	CSR_WRITE_4(sc, ALE_MASTER_CFG, reg);
2720 	CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000));
2721 
2722 	/* Set Maximum frame size of controller. */
2723 	if (ifp->if_mtu < ETHERMTU)
2724 		sc->ale_max_frame_size = ETHERMTU;
2725 	else
2726 		sc->ale_max_frame_size = ifp->if_mtu;
2727 	sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +
2728 	    ETHER_CRC_LEN;
2729 	CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size);
2730 	/* Configure IPG/IFG parameters. */
2731 	CSR_WRITE_4(sc, ALE_IPG_IFG_CFG,
2732 	    ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) |
2733 	    ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) |
2734 	    ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) |
2735 	    ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK));
2736 	/* Set parameters for half-duplex media. */
2737 	CSR_WRITE_4(sc, ALE_HDPX_CFG,
2738 	    ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) &
2739 	    HDPX_CFG_LCOL_MASK) |
2740 	    ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) &
2741 	    HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN |
2742 	    ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) &
2743 	    HDPX_CFG_ABEBT_MASK) |
2744 	    ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) &
2745 	    HDPX_CFG_JAMIPG_MASK));
2746 
2747 	/* Configure Tx jumbo frame parameters. */
2748 	if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) {
2749 		if (ifp->if_mtu < ETHERMTU)
2750 			reg = sc->ale_max_frame_size;
2751 		else if (ifp->if_mtu < 6 * 1024)
2752 			reg = (sc->ale_max_frame_size * 2) / 3;
2753 		else
2754 			reg = sc->ale_max_frame_size / 2;
2755 		CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH,
2756 		    roundup(reg, TX_JUMBO_THRESH_UNIT) >>
2757 		    TX_JUMBO_THRESH_UNIT_SHIFT);
2758 	}
2759 	/* Configure TxQ. */
2760 	reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT))
2761 	    << TXQ_CFG_TX_FIFO_BURST_SHIFT;
2762 	reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) &
2763 	    TXQ_CFG_TPD_BURST_MASK;
2764 	CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB);
2765 
2766 	/* Configure Rx jumbo frame & flow control parameters. */
2767 	if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) {
2768 		reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT);
2769 		CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH,
2770 		    (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) <<
2771 		    RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) |
2772 		    ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) &
2773 		    RX_JUMBO_LKAH_MASK));
2774 		reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN);
2775 		rxf_hi = (reg * 7) / 10;
2776 		rxf_lo = (reg * 3)/ 10;
2777 		CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH,
2778 		    ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) &
2779 		    RX_FIFO_PAUSE_THRESH_LO_MASK) |
2780 		    ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) &
2781 		    RX_FIFO_PAUSE_THRESH_HI_MASK));
2782 	}
2783 
2784 	/* Disable RSS. */
2785 	CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0);
2786 	CSR_WRITE_4(sc, ALE_RSS_CPU, 0);
2787 
2788 	/* Configure RxQ. */
2789 	CSR_WRITE_4(sc, ALE_RXQ_CFG,
2790 	    RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB);
2791 
2792 	/* Configure DMA parameters. */
2793 	reg = 0;
2794 	if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0)
2795 		reg |= DMA_CFG_TXCMB_ENB;
2796 	CSR_WRITE_4(sc, ALE_DMA_CFG,
2797 	    DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 |
2798 	    sc->ale_dma_rd_burst | reg |
2799 	    sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB |
2800 	    ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) &
2801 	    DMA_CFG_RD_DELAY_CNT_MASK) |
2802 	    ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) &
2803 	    DMA_CFG_WR_DELAY_CNT_MASK));
2804 
2805 	/*
2806 	 * Hardware can be configured to issue SMB interrupt based
2807 	 * on programmed interval. Since there is a callout that is
2808 	 * invoked for every hz in driver we use that instead of
2809 	 * relying on periodic SMB interrupt.
2810 	 */
2811 	CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0));
2812 	/* Clear MAC statistics. */
2813 	ale_stats_clear(sc);
2814 
2815 	/*
2816 	 * Configure Tx/Rx MACs.
2817 	 *  - Auto-padding for short frames.
2818 	 *  - Enable CRC generation.
2819 	 *  Actual reconfiguration of MAC for resolved speed/duplex
2820 	 *  is followed after detection of link establishment.
2821 	 *  AR81xx always does checksum computation regardless of
2822 	 *  MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will
2823 	 *  cause Rx handling issue for fragmented IP datagrams due
2824 	 *  to silicon bug.
2825 	 */
2826 	reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX |
2827 	    ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) &
2828 	    MAC_CFG_PREAMBLE_MASK);
2829 	if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0)
2830 		reg |= MAC_CFG_SPEED_10_100;
2831 	else
2832 		reg |= MAC_CFG_SPEED_1000;
2833 	CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2834 
2835 	/* Set up the receive filter. */
2836 	ale_rxfilter(sc);
2837 	ale_rxvlan(sc);
2838 
2839 	/* Acknowledge all pending interrupts and clear it. */
2840 	CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS);
2841 	CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2842 	CSR_WRITE_4(sc, ALE_INTR_STATUS, 0);
2843 
2844 	ifp->if_drv_flags |= IFF_DRV_RUNNING;
2845 	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
2846 
2847 	sc->ale_flags &= ~ALE_FLAG_LINK;
2848 	/* Switch to the current media. */
2849 	mii_mediachg(mii);
2850 
2851 	callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc);
2852 }
2853 
2854 static void
2855 ale_stop(struct ale_softc *sc)
2856 {
2857 	struct ifnet *ifp;
2858 	struct ale_txdesc *txd;
2859 	uint32_t reg;
2860 	int i;
2861 
2862 	ALE_LOCK_ASSERT(sc);
2863 	/*
2864 	 * Mark the interface down and cancel the watchdog timer.
2865 	 */
2866 	ifp = sc->ale_ifp;
2867 	ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
2868 	sc->ale_flags &= ~ALE_FLAG_LINK;
2869 	callout_stop(&sc->ale_tick_ch);
2870 	sc->ale_watchdog_timer = 0;
2871 	ale_stats_update(sc);
2872 	/* Disable interrupts. */
2873 	CSR_WRITE_4(sc, ALE_INTR_MASK, 0);
2874 	CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2875 	/* Disable queue processing and DMA. */
2876 	reg = CSR_READ_4(sc, ALE_TXQ_CFG);
2877 	reg &= ~TXQ_CFG_ENB;
2878 	CSR_WRITE_4(sc, ALE_TXQ_CFG, reg);
2879 	reg = CSR_READ_4(sc, ALE_RXQ_CFG);
2880 	reg &= ~RXQ_CFG_ENB;
2881 	CSR_WRITE_4(sc, ALE_RXQ_CFG, reg);
2882 	reg = CSR_READ_4(sc, ALE_DMA_CFG);
2883 	reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB);
2884 	CSR_WRITE_4(sc, ALE_DMA_CFG, reg);
2885 	DELAY(1000);
2886 	/* Stop Rx/Tx MACs. */
2887 	ale_stop_mac(sc);
2888 	/* Disable interrupts which might be touched in taskq handler. */
2889 	CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF);
2890 
2891 	/*
2892 	 * Free TX mbufs still in the queues.
2893 	 */
2894 	for (i = 0; i < ALE_TX_RING_CNT; i++) {
2895 		txd = &sc->ale_cdata.ale_txdesc[i];
2896 		if (txd->tx_m != NULL) {
2897 			bus_dmamap_sync(sc->ale_cdata.ale_tx_tag,
2898 			    txd->tx_dmamap, BUS_DMASYNC_POSTWRITE);
2899 			bus_dmamap_unload(sc->ale_cdata.ale_tx_tag,
2900 			    txd->tx_dmamap);
2901 			m_freem(txd->tx_m);
2902 			txd->tx_m = NULL;
2903 		}
2904         }
2905 }
2906 
2907 static void
2908 ale_stop_mac(struct ale_softc *sc)
2909 {
2910 	uint32_t reg;
2911 	int i;
2912 
2913 	ALE_LOCK_ASSERT(sc);
2914 
2915 	reg = CSR_READ_4(sc, ALE_MAC_CFG);
2916 	if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) {
2917 		reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB);
2918 		CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2919 	}
2920 
2921 	for (i = ALE_TIMEOUT; i > 0; i--) {
2922 		reg = CSR_READ_4(sc, ALE_IDLE_STATUS);
2923 		if (reg == 0)
2924 			break;
2925 		DELAY(10);
2926 	}
2927 	if (i == 0)
2928 		device_printf(sc->ale_dev,
2929 		    "could not disable Tx/Rx MAC(0x%08x)!\n", reg);
2930 }
2931 
2932 static void
2933 ale_init_tx_ring(struct ale_softc *sc)
2934 {
2935 	struct ale_txdesc *txd;
2936 	int i;
2937 
2938 	ALE_LOCK_ASSERT(sc);
2939 
2940 	sc->ale_cdata.ale_tx_prod = 0;
2941 	sc->ale_cdata.ale_tx_cons = 0;
2942 	sc->ale_cdata.ale_tx_cnt = 0;
2943 
2944 	bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ);
2945 	bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ);
2946 	for (i = 0; i < ALE_TX_RING_CNT; i++) {
2947 		txd = &sc->ale_cdata.ale_txdesc[i];
2948 		txd->tx_m = NULL;
2949 	}
2950 	*sc->ale_cdata.ale_tx_cmb = 0;
2951 	bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag,
2952 	    sc->ale_cdata.ale_tx_cmb_map,
2953 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2954 	bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag,
2955 	    sc->ale_cdata.ale_tx_ring_map,
2956 	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2957 }
2958 
2959 static void
2960 ale_init_rx_pages(struct ale_softc *sc)
2961 {
2962 	struct ale_rx_page *rx_page;
2963 	int i;
2964 
2965 	ALE_LOCK_ASSERT(sc);
2966 
2967 	sc->ale_morework = 0;
2968 	sc->ale_cdata.ale_rx_seqno = 0;
2969 	sc->ale_cdata.ale_rx_curp = 0;
2970 
2971 	for (i = 0; i < ALE_RX_PAGES; i++) {
2972 		rx_page = &sc->ale_cdata.ale_rx_page[i];
2973 		bzero(rx_page->page_addr, sc->ale_pagesize);
2974 		bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ);
2975 		rx_page->cons = 0;
2976 		*rx_page->cmb_addr = 0;
2977 		bus_dmamap_sync(rx_page->page_tag, rx_page->page_map,
2978 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2979 		bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map,
2980 		    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
2981 	}
2982 }
2983 
2984 static void
2985 ale_rxvlan(struct ale_softc *sc)
2986 {
2987 	struct ifnet *ifp;
2988 	uint32_t reg;
2989 
2990 	ALE_LOCK_ASSERT(sc);
2991 
2992 	ifp = sc->ale_ifp;
2993 	reg = CSR_READ_4(sc, ALE_MAC_CFG);
2994 	reg &= ~MAC_CFG_VLAN_TAG_STRIP;
2995 	if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0)
2996 		reg |= MAC_CFG_VLAN_TAG_STRIP;
2997 	CSR_WRITE_4(sc, ALE_MAC_CFG, reg);
2998 }
2999 
3000 static u_int
3001 ale_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt)
3002 {
3003 	uint32_t crc, *mchash = arg;
3004 
3005 	crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN);
3006 	mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f);
3007 
3008 	return (1);
3009 }
3010 
3011 static void
3012 ale_rxfilter(struct ale_softc *sc)
3013 {
3014 	struct ifnet *ifp;
3015 	uint32_t mchash[2];
3016 	uint32_t rxcfg;
3017 
3018 	ALE_LOCK_ASSERT(sc);
3019 
3020 	ifp = sc->ale_ifp;
3021 
3022 	rxcfg = CSR_READ_4(sc, ALE_MAC_CFG);
3023 	rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC);
3024 	if ((ifp->if_flags & IFF_BROADCAST) != 0)
3025 		rxcfg |= MAC_CFG_BCAST;
3026 	if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) {
3027 		if ((ifp->if_flags & IFF_PROMISC) != 0)
3028 			rxcfg |= MAC_CFG_PROMISC;
3029 		if ((ifp->if_flags & IFF_ALLMULTI) != 0)
3030 			rxcfg |= MAC_CFG_ALLMULTI;
3031 		CSR_WRITE_4(sc, ALE_MAR0, 0xFFFFFFFF);
3032 		CSR_WRITE_4(sc, ALE_MAR1, 0xFFFFFFFF);
3033 		CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg);
3034 		return;
3035 	}
3036 
3037 	/* Program new filter. */
3038 	bzero(mchash, sizeof(mchash));
3039 	if_foreach_llmaddr(ifp, ale_hash_maddr, &mchash);
3040 
3041 	CSR_WRITE_4(sc, ALE_MAR0, mchash[0]);
3042 	CSR_WRITE_4(sc, ALE_MAR1, mchash[1]);
3043 	CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg);
3044 }
3045 
3046 static int
3047 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high)
3048 {
3049 	int error, value;
3050 
3051 	if (arg1 == NULL)
3052 		return (EINVAL);
3053 	value = *(int *)arg1;
3054 	error = sysctl_handle_int(oidp, &value, 0, req);
3055 	if (error || req->newptr == NULL)
3056 		return (error);
3057 	if (value < low || value > high)
3058 		return (EINVAL);
3059         *(int *)arg1 = value;
3060 
3061         return (0);
3062 }
3063 
3064 static int
3065 sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS)
3066 {
3067 	return (sysctl_int_range(oidp, arg1, arg2, req,
3068 	    ALE_PROC_MIN, ALE_PROC_MAX));
3069 }
3070 
3071 static int
3072 sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS)
3073 {
3074 
3075 	return (sysctl_int_range(oidp, arg1, arg2, req,
3076 	    ALE_IM_TIMER_MIN, ALE_IM_TIMER_MAX));
3077 }
3078