1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/endian.h> 36 #include <sys/kernel.h> 37 #include <sys/malloc.h> 38 #include <sys/mbuf.h> 39 #include <sys/module.h> 40 #include <sys/rman.h> 41 #include <sys/queue.h> 42 #include <sys/socket.h> 43 #include <sys/sockio.h> 44 #include <sys/sysctl.h> 45 #include <sys/taskqueue.h> 46 47 #include <net/bpf.h> 48 #include <net/if.h> 49 #include <net/if_var.h> 50 #include <net/if_arp.h> 51 #include <net/ethernet.h> 52 #include <net/if_dl.h> 53 #include <net/if_llc.h> 54 #include <net/if_media.h> 55 #include <net/if_types.h> 56 #include <net/if_vlan_var.h> 57 58 #include <netinet/in.h> 59 #include <netinet/in_systm.h> 60 #include <netinet/ip.h> 61 #include <netinet/tcp.h> 62 63 #include <dev/mii/mii.h> 64 #include <dev/mii/miivar.h> 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 69 #include <machine/bus.h> 70 #include <machine/in_cksum.h> 71 72 #include <dev/ale/if_alereg.h> 73 #include <dev/ale/if_alevar.h> 74 75 /* "device miibus" required. See GENERIC if you get errors here. */ 76 #include "miibus_if.h" 77 78 /* For more information about Tx checksum offload issues see ale_encap(). */ 79 #define ALE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 80 81 MODULE_DEPEND(ale, pci, 1, 1, 1); 82 MODULE_DEPEND(ale, ether, 1, 1, 1); 83 MODULE_DEPEND(ale, miibus, 1, 1, 1); 84 85 /* Tunables. */ 86 static int msi_disable = 0; 87 static int msix_disable = 0; 88 TUNABLE_INT("hw.ale.msi_disable", &msi_disable); 89 TUNABLE_INT("hw.ale.msix_disable", &msix_disable); 90 91 /* 92 * Devices supported by this driver. 93 */ 94 static const struct ale_dev { 95 uint16_t ale_vendorid; 96 uint16_t ale_deviceid; 97 const char *ale_name; 98 } ale_devs[] = { 99 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR81XX, 100 "Atheros AR8121/AR8113/AR8114 PCIe Ethernet" }, 101 }; 102 103 static int ale_attach(device_t); 104 static int ale_check_boundary(struct ale_softc *); 105 static int ale_detach(device_t); 106 static int ale_dma_alloc(struct ale_softc *); 107 static void ale_dma_free(struct ale_softc *); 108 static void ale_dmamap_cb(void *, bus_dma_segment_t *, int, int); 109 static int ale_encap(struct ale_softc *, struct mbuf **); 110 static void ale_get_macaddr(struct ale_softc *); 111 static void ale_init(void *); 112 static void ale_init_locked(struct ale_softc *); 113 static void ale_init_rx_pages(struct ale_softc *); 114 static void ale_init_tx_ring(struct ale_softc *); 115 static void ale_int_task(void *, int); 116 static int ale_intr(void *); 117 static int ale_ioctl(if_t, u_long, caddr_t); 118 static void ale_mac_config(struct ale_softc *); 119 static int ale_miibus_readreg(device_t, int, int); 120 static void ale_miibus_statchg(device_t); 121 static int ale_miibus_writereg(device_t, int, int, int); 122 static int ale_mediachange(if_t); 123 static void ale_mediastatus(if_t, struct ifmediareq *); 124 static void ale_phy_reset(struct ale_softc *); 125 static int ale_probe(device_t); 126 static void ale_reset(struct ale_softc *); 127 static int ale_resume(device_t); 128 static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, 129 uint32_t, uint32_t *); 130 static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); 131 static int ale_rxeof(struct ale_softc *sc, int); 132 static void ale_rxfilter(struct ale_softc *); 133 static void ale_rxvlan(struct ale_softc *); 134 static void ale_setlinkspeed(struct ale_softc *); 135 static void ale_setwol(struct ale_softc *); 136 static int ale_shutdown(device_t); 137 static void ale_start(if_t); 138 static void ale_start_locked(if_t); 139 static void ale_stats_clear(struct ale_softc *); 140 static void ale_stats_update(struct ale_softc *); 141 static void ale_stop(struct ale_softc *); 142 static void ale_stop_mac(struct ale_softc *); 143 static int ale_suspend(device_t); 144 static void ale_sysctl_node(struct ale_softc *); 145 static void ale_tick(void *); 146 static void ale_txeof(struct ale_softc *); 147 static void ale_watchdog(struct ale_softc *); 148 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 149 static int sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS); 150 static int sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS); 151 152 static device_method_t ale_methods[] = { 153 /* Device interface. */ 154 DEVMETHOD(device_probe, ale_probe), 155 DEVMETHOD(device_attach, ale_attach), 156 DEVMETHOD(device_detach, ale_detach), 157 DEVMETHOD(device_shutdown, ale_shutdown), 158 DEVMETHOD(device_suspend, ale_suspend), 159 DEVMETHOD(device_resume, ale_resume), 160 161 /* MII interface. */ 162 DEVMETHOD(miibus_readreg, ale_miibus_readreg), 163 DEVMETHOD(miibus_writereg, ale_miibus_writereg), 164 DEVMETHOD(miibus_statchg, ale_miibus_statchg), 165 166 DEVMETHOD_END 167 }; 168 169 static driver_t ale_driver = { 170 "ale", 171 ale_methods, 172 sizeof(struct ale_softc) 173 }; 174 175 DRIVER_MODULE(ale, pci, ale_driver, NULL, NULL); 176 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, ale, ale_devs, 177 nitems(ale_devs)); 178 DRIVER_MODULE(miibus, ale, miibus_driver, NULL, NULL); 179 180 static struct resource_spec ale_res_spec_mem[] = { 181 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 182 { -1, 0, 0 } 183 }; 184 185 static struct resource_spec ale_irq_spec_legacy[] = { 186 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 187 { -1, 0, 0 } 188 }; 189 190 static struct resource_spec ale_irq_spec_msi[] = { 191 { SYS_RES_IRQ, 1, RF_ACTIVE }, 192 { -1, 0, 0 } 193 }; 194 195 static struct resource_spec ale_irq_spec_msix[] = { 196 { SYS_RES_IRQ, 1, RF_ACTIVE }, 197 { -1, 0, 0 } 198 }; 199 200 static int 201 ale_miibus_readreg(device_t dev, int phy, int reg) 202 { 203 struct ale_softc *sc; 204 uint32_t v; 205 int i; 206 207 sc = device_get_softc(dev); 208 209 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 210 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 211 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 212 DELAY(5); 213 v = CSR_READ_4(sc, ALE_MDIO); 214 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 215 break; 216 } 217 218 if (i == 0) { 219 device_printf(sc->ale_dev, "phy read timeout : %d\n", reg); 220 return (0); 221 } 222 223 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 224 } 225 226 static int 227 ale_miibus_writereg(device_t dev, int phy, int reg, int val) 228 { 229 struct ale_softc *sc; 230 uint32_t v; 231 int i; 232 233 sc = device_get_softc(dev); 234 235 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 236 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 237 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 238 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 239 DELAY(5); 240 v = CSR_READ_4(sc, ALE_MDIO); 241 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 242 break; 243 } 244 245 if (i == 0) 246 device_printf(sc->ale_dev, "phy write timeout : %d\n", reg); 247 248 return (0); 249 } 250 251 static void 252 ale_miibus_statchg(device_t dev) 253 { 254 struct ale_softc *sc; 255 struct mii_data *mii; 256 if_t ifp; 257 uint32_t reg; 258 259 sc = device_get_softc(dev); 260 mii = device_get_softc(sc->ale_miibus); 261 ifp = sc->ale_ifp; 262 if (mii == NULL || ifp == NULL || 263 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 264 return; 265 266 sc->ale_flags &= ~ALE_FLAG_LINK; 267 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 268 (IFM_ACTIVE | IFM_AVALID)) { 269 switch (IFM_SUBTYPE(mii->mii_media_active)) { 270 case IFM_10_T: 271 case IFM_100_TX: 272 sc->ale_flags |= ALE_FLAG_LINK; 273 break; 274 case IFM_1000_T: 275 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 276 sc->ale_flags |= ALE_FLAG_LINK; 277 break; 278 default: 279 break; 280 } 281 } 282 283 /* Stop Rx/Tx MACs. */ 284 ale_stop_mac(sc); 285 286 /* Program MACs with resolved speed/duplex/flow-control. */ 287 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { 288 ale_mac_config(sc); 289 /* Reenable Tx/Rx MACs. */ 290 reg = CSR_READ_4(sc, ALE_MAC_CFG); 291 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 292 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 293 } 294 } 295 296 static void 297 ale_mediastatus(if_t ifp, struct ifmediareq *ifmr) 298 { 299 struct ale_softc *sc; 300 struct mii_data *mii; 301 302 sc = if_getsoftc(ifp); 303 ALE_LOCK(sc); 304 if ((if_getflags(ifp) & IFF_UP) == 0) { 305 ALE_UNLOCK(sc); 306 return; 307 } 308 mii = device_get_softc(sc->ale_miibus); 309 310 mii_pollstat(mii); 311 ifmr->ifm_status = mii->mii_media_status; 312 ifmr->ifm_active = mii->mii_media_active; 313 ALE_UNLOCK(sc); 314 } 315 316 static int 317 ale_mediachange(if_t ifp) 318 { 319 struct ale_softc *sc; 320 struct mii_data *mii; 321 struct mii_softc *miisc; 322 int error; 323 324 sc = if_getsoftc(ifp); 325 ALE_LOCK(sc); 326 mii = device_get_softc(sc->ale_miibus); 327 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 328 PHY_RESET(miisc); 329 error = mii_mediachg(mii); 330 ALE_UNLOCK(sc); 331 332 return (error); 333 } 334 335 static int 336 ale_probe(device_t dev) 337 { 338 const struct ale_dev *sp; 339 int i; 340 uint16_t vendor, devid; 341 342 vendor = pci_get_vendor(dev); 343 devid = pci_get_device(dev); 344 sp = ale_devs; 345 for (i = 0; i < nitems(ale_devs); i++) { 346 if (vendor == sp->ale_vendorid && 347 devid == sp->ale_deviceid) { 348 device_set_desc(dev, sp->ale_name); 349 return (BUS_PROBE_DEFAULT); 350 } 351 sp++; 352 } 353 354 return (ENXIO); 355 } 356 357 static void 358 ale_get_macaddr(struct ale_softc *sc) 359 { 360 uint32_t ea[2], reg; 361 int i, vpdc; 362 363 reg = CSR_READ_4(sc, ALE_SPI_CTRL); 364 if ((reg & SPI_VPD_ENB) != 0) { 365 reg &= ~SPI_VPD_ENB; 366 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); 367 } 368 369 if (pci_find_cap(sc->ale_dev, PCIY_VPD, &vpdc) == 0) { 370 /* 371 * PCI VPD capability found, let TWSI reload EEPROM. 372 * This will set ethernet address of controller. 373 */ 374 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | 375 TWSI_CTRL_SW_LD_START); 376 for (i = 100; i > 0; i--) { 377 DELAY(1000); 378 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); 379 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 380 break; 381 } 382 if (i == 0) 383 device_printf(sc->ale_dev, 384 "reloading EEPROM timeout!\n"); 385 } else { 386 if (bootverbose) 387 device_printf(sc->ale_dev, 388 "PCI VPD capability not found!\n"); 389 } 390 391 ea[0] = CSR_READ_4(sc, ALE_PAR0); 392 ea[1] = CSR_READ_4(sc, ALE_PAR1); 393 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; 394 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; 395 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; 396 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; 397 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; 398 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; 399 } 400 401 static void 402 ale_phy_reset(struct ale_softc *sc) 403 { 404 405 /* Reset magic from Linux. */ 406 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 407 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 408 GPHY_CTRL_PHY_PLL_ON); 409 DELAY(1000); 410 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 411 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | 412 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); 413 DELAY(1000); 414 415 #define ATPHY_DBG_ADDR 0x1D 416 #define ATPHY_DBG_DATA 0x1E 417 418 /* Enable hibernation mode. */ 419 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 420 ATPHY_DBG_ADDR, 0x0B); 421 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 422 ATPHY_DBG_DATA, 0xBC00); 423 /* Set Class A/B for all modes. */ 424 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 425 ATPHY_DBG_ADDR, 0x00); 426 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 427 ATPHY_DBG_DATA, 0x02EF); 428 /* Enable 10BT power saving. */ 429 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 430 ATPHY_DBG_ADDR, 0x12); 431 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 432 ATPHY_DBG_DATA, 0x4C04); 433 /* Adjust 1000T power. */ 434 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 435 ATPHY_DBG_ADDR, 0x04); 436 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 437 ATPHY_DBG_ADDR, 0x8BBB); 438 /* 10BT center tap voltage. */ 439 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 440 ATPHY_DBG_ADDR, 0x05); 441 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 442 ATPHY_DBG_ADDR, 0x2C46); 443 444 #undef ATPHY_DBG_ADDR 445 #undef ATPHY_DBG_DATA 446 DELAY(1000); 447 } 448 449 static int 450 ale_attach(device_t dev) 451 { 452 struct ale_softc *sc; 453 if_t ifp; 454 uint16_t burst; 455 int error, i, msic, msixc, pmc; 456 uint32_t rxf_len, txf_len; 457 458 error = 0; 459 sc = device_get_softc(dev); 460 sc->ale_dev = dev; 461 462 mtx_init(&sc->ale_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 463 MTX_DEF); 464 callout_init_mtx(&sc->ale_tick_ch, &sc->ale_mtx, 0); 465 NET_TASK_INIT(&sc->ale_int_task, 0, ale_int_task, sc); 466 467 /* Map the device. */ 468 pci_enable_busmaster(dev); 469 sc->ale_res_spec = ale_res_spec_mem; 470 sc->ale_irq_spec = ale_irq_spec_legacy; 471 error = bus_alloc_resources(dev, sc->ale_res_spec, sc->ale_res); 472 if (error != 0) { 473 device_printf(dev, "cannot allocate memory resources.\n"); 474 goto fail; 475 } 476 477 /* Set PHY address. */ 478 sc->ale_phyaddr = ALE_PHY_ADDR; 479 480 /* Reset PHY. */ 481 ale_phy_reset(sc); 482 483 /* Reset the ethernet controller. */ 484 ale_reset(sc); 485 486 /* Get PCI and chip id/revision. */ 487 sc->ale_rev = pci_get_revid(dev); 488 if (sc->ale_rev >= 0xF0) { 489 /* L2E Rev. B. AR8114 */ 490 sc->ale_flags |= ALE_FLAG_FASTETHER; 491 } else { 492 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { 493 /* L1E AR8121 */ 494 sc->ale_flags |= ALE_FLAG_JUMBO; 495 } else { 496 /* L2E Rev. A. AR8113 */ 497 sc->ale_flags |= ALE_FLAG_FASTETHER; 498 } 499 } 500 /* 501 * All known controllers seems to require 4 bytes alignment 502 * of Tx buffers to make Tx checksum offload with custom 503 * checksum generation method work. 504 */ 505 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; 506 /* 507 * All known controllers seems to have issues on Rx checksum 508 * offload for fragmented IP datagrams. 509 */ 510 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; 511 /* 512 * Don't use Tx CMB. It is known to cause RRS update failure 513 * under certain circumstances. Typical phenomenon of the 514 * issue would be unexpected sequence number encountered in 515 * Rx handler. 516 */ 517 sc->ale_flags |= ALE_FLAG_TXCMB_BUG; 518 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> 519 MASTER_CHIP_REV_SHIFT; 520 if (bootverbose) { 521 device_printf(dev, "PCI device revision : 0x%04x\n", 522 sc->ale_rev); 523 device_printf(dev, "Chip id/revision : 0x%04x\n", 524 sc->ale_chip_rev); 525 } 526 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); 527 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 528 /* 529 * Uninitialized hardware returns an invalid chip id/revision 530 * as well as 0xFFFFFFFF for Tx/Rx fifo length. 531 */ 532 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || 533 rxf_len == 0xFFFFFFF) { 534 device_printf(dev,"chip revision : 0x%04x, %u Tx FIFO " 535 "%u Rx FIFO -- not initialized?\n", sc->ale_chip_rev, 536 txf_len, rxf_len); 537 error = ENXIO; 538 goto fail; 539 } 540 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", txf_len, rxf_len); 541 542 /* Allocate IRQ resources. */ 543 msixc = pci_msix_count(dev); 544 msic = pci_msi_count(dev); 545 if (bootverbose) { 546 device_printf(dev, "MSIX count : %d\n", msixc); 547 device_printf(dev, "MSI count : %d\n", msic); 548 } 549 550 /* Prefer MSIX over MSI. */ 551 if (msix_disable == 0 || msi_disable == 0) { 552 if (msix_disable == 0 && msixc == ALE_MSIX_MESSAGES && 553 pci_alloc_msix(dev, &msixc) == 0) { 554 if (msixc == ALE_MSIX_MESSAGES) { 555 device_printf(dev, "Using %d MSIX messages.\n", 556 msixc); 557 sc->ale_flags |= ALE_FLAG_MSIX; 558 sc->ale_irq_spec = ale_irq_spec_msix; 559 } else 560 pci_release_msi(dev); 561 } 562 if (msi_disable == 0 && (sc->ale_flags & ALE_FLAG_MSIX) == 0 && 563 msic == ALE_MSI_MESSAGES && 564 pci_alloc_msi(dev, &msic) == 0) { 565 if (msic == ALE_MSI_MESSAGES) { 566 device_printf(dev, "Using %d MSI messages.\n", 567 msic); 568 sc->ale_flags |= ALE_FLAG_MSI; 569 sc->ale_irq_spec = ale_irq_spec_msi; 570 } else 571 pci_release_msi(dev); 572 } 573 } 574 575 error = bus_alloc_resources(dev, sc->ale_irq_spec, sc->ale_irq); 576 if (error != 0) { 577 device_printf(dev, "cannot allocate IRQ resources.\n"); 578 goto fail; 579 } 580 581 /* Get DMA parameters from PCIe device control register. */ 582 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 583 sc->ale_flags |= ALE_FLAG_PCIE; 584 burst = pci_read_config(dev, i + 0x08, 2); 585 /* Max read request size. */ 586 sc->ale_dma_rd_burst = ((burst >> 12) & 0x07) << 587 DMA_CFG_RD_BURST_SHIFT; 588 /* Max payload size. */ 589 sc->ale_dma_wr_burst = ((burst >> 5) & 0x07) << 590 DMA_CFG_WR_BURST_SHIFT; 591 if (bootverbose) { 592 device_printf(dev, "Read request size : %d bytes.\n", 593 128 << ((burst >> 12) & 0x07)); 594 device_printf(dev, "TLP payload size : %d bytes.\n", 595 128 << ((burst >> 5) & 0x07)); 596 } 597 } else { 598 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; 599 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; 600 } 601 602 /* Create device sysctl node. */ 603 ale_sysctl_node(sc); 604 605 if ((error = ale_dma_alloc(sc)) != 0) 606 goto fail; 607 608 /* Load station address. */ 609 ale_get_macaddr(sc); 610 611 ifp = sc->ale_ifp = if_alloc(IFT_ETHER); 612 if_setsoftc(ifp, sc); 613 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 614 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 615 if_setioctlfn(ifp, ale_ioctl); 616 if_setstartfn(ifp, ale_start); 617 if_setinitfn(ifp, ale_init); 618 if_setsendqlen(ifp, ALE_TX_RING_CNT - 1); 619 if_setsendqready(ifp); 620 if_setcapabilities(ifp, IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4); 621 if_sethwassist(ifp, ALE_CSUM_FEATURES | CSUM_TSO); 622 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { 623 sc->ale_flags |= ALE_FLAG_PMCAP; 624 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST, 0); 625 } 626 if_setcapenable(ifp, if_getcapabilities(ifp)); 627 628 /* Set up MII bus. */ 629 error = mii_attach(dev, &sc->ale_miibus, ifp, ale_mediachange, 630 ale_mediastatus, BMSR_DEFCAPMASK, sc->ale_phyaddr, MII_OFFSET_ANY, 631 MIIF_DOPAUSE); 632 if (error != 0) { 633 device_printf(dev, "attaching PHYs failed\n"); 634 goto fail; 635 } 636 637 ether_ifattach(ifp, sc->ale_eaddr); 638 639 /* VLAN capability setup. */ 640 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 641 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0); 642 if_setcapenable(ifp, if_getcapabilities(ifp)); 643 /* 644 * Even though controllers supported by ale(3) have Rx checksum 645 * offload bug the workaround for fragmented frames seemed to 646 * work so far. However it seems Rx checksum offload does not 647 * work under certain conditions. So disable Rx checksum offload 648 * until I find more clue about it but allow users to override it. 649 */ 650 if_setcapenablebit(ifp, 0, IFCAP_RXCSUM); 651 652 /* Tell the upper layer(s) we support long frames. */ 653 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 654 655 /* Create local taskq. */ 656 sc->ale_tq = taskqueue_create_fast("ale_taskq", M_WAITOK, 657 taskqueue_thread_enqueue, &sc->ale_tq); 658 taskqueue_start_threads(&sc->ale_tq, 1, PI_NET, "%s taskq", 659 device_get_nameunit(sc->ale_dev)); 660 661 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 662 msic = ALE_MSIX_MESSAGES; 663 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 664 msic = ALE_MSI_MESSAGES; 665 else 666 msic = 1; 667 for (i = 0; i < msic; i++) { 668 error = bus_setup_intr(dev, sc->ale_irq[i], 669 INTR_TYPE_NET | INTR_MPSAFE, ale_intr, NULL, sc, 670 &sc->ale_intrhand[i]); 671 if (error != 0) 672 break; 673 } 674 if (error != 0) { 675 device_printf(dev, "could not set up interrupt handler.\n"); 676 taskqueue_free(sc->ale_tq); 677 sc->ale_tq = NULL; 678 ether_ifdetach(ifp); 679 goto fail; 680 } 681 682 fail: 683 if (error != 0) 684 ale_detach(dev); 685 686 return (error); 687 } 688 689 static int 690 ale_detach(device_t dev) 691 { 692 struct ale_softc *sc; 693 if_t ifp; 694 int i, msic; 695 696 sc = device_get_softc(dev); 697 698 ifp = sc->ale_ifp; 699 if (device_is_attached(dev)) { 700 ether_ifdetach(ifp); 701 ALE_LOCK(sc); 702 ale_stop(sc); 703 ALE_UNLOCK(sc); 704 callout_drain(&sc->ale_tick_ch); 705 taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 706 } 707 708 if (sc->ale_tq != NULL) { 709 taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 710 taskqueue_free(sc->ale_tq); 711 sc->ale_tq = NULL; 712 } 713 714 bus_generic_detach(dev); 715 ale_dma_free(sc); 716 717 if (ifp != NULL) { 718 if_free(ifp); 719 sc->ale_ifp = NULL; 720 } 721 722 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 723 msic = ALE_MSIX_MESSAGES; 724 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 725 msic = ALE_MSI_MESSAGES; 726 else 727 msic = 1; 728 for (i = 0; i < msic; i++) { 729 if (sc->ale_intrhand[i] != NULL) { 730 bus_teardown_intr(dev, sc->ale_irq[i], 731 sc->ale_intrhand[i]); 732 sc->ale_intrhand[i] = NULL; 733 } 734 } 735 736 bus_release_resources(dev, sc->ale_irq_spec, sc->ale_irq); 737 if ((sc->ale_flags & (ALE_FLAG_MSI | ALE_FLAG_MSIX)) != 0) 738 pci_release_msi(dev); 739 bus_release_resources(dev, sc->ale_res_spec, sc->ale_res); 740 mtx_destroy(&sc->ale_mtx); 741 742 return (0); 743 } 744 745 #define ALE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 746 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 747 748 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 749 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 750 751 static void 752 ale_sysctl_node(struct ale_softc *sc) 753 { 754 struct sysctl_ctx_list *ctx; 755 struct sysctl_oid_list *child, *parent; 756 struct sysctl_oid *tree; 757 struct ale_hw_stats *stats; 758 int error; 759 760 stats = &sc->ale_stats; 761 ctx = device_get_sysctl_ctx(sc->ale_dev); 762 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ale_dev)); 763 764 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 765 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->ale_int_rx_mod, 766 0, sysctl_hw_ale_int_mod, "I", "ale Rx interrupt moderation"); 767 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 768 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->ale_int_tx_mod, 769 0, sysctl_hw_ale_int_mod, "I", "ale Tx interrupt moderation"); 770 /* Pull in device tunables. */ 771 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 772 error = resource_int_value(device_get_name(sc->ale_dev), 773 device_get_unit(sc->ale_dev), "int_rx_mod", &sc->ale_int_rx_mod); 774 if (error == 0) { 775 if (sc->ale_int_rx_mod < ALE_IM_TIMER_MIN || 776 sc->ale_int_rx_mod > ALE_IM_TIMER_MAX) { 777 device_printf(sc->ale_dev, "int_rx_mod value out of " 778 "range; using default: %d\n", 779 ALE_IM_RX_TIMER_DEFAULT); 780 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 781 } 782 } 783 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 784 error = resource_int_value(device_get_name(sc->ale_dev), 785 device_get_unit(sc->ale_dev), "int_tx_mod", &sc->ale_int_tx_mod); 786 if (error == 0) { 787 if (sc->ale_int_tx_mod < ALE_IM_TIMER_MIN || 788 sc->ale_int_tx_mod > ALE_IM_TIMER_MAX) { 789 device_printf(sc->ale_dev, "int_tx_mod value out of " 790 "range; using default: %d\n", 791 ALE_IM_TX_TIMER_DEFAULT); 792 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 793 } 794 } 795 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 796 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 797 &sc->ale_process_limit, 0, sysctl_hw_ale_proc_limit, "I", 798 "max number of Rx events to process"); 799 /* Pull in device tunables. */ 800 sc->ale_process_limit = ALE_PROC_DEFAULT; 801 error = resource_int_value(device_get_name(sc->ale_dev), 802 device_get_unit(sc->ale_dev), "process_limit", 803 &sc->ale_process_limit); 804 if (error == 0) { 805 if (sc->ale_process_limit < ALE_PROC_MIN || 806 sc->ale_process_limit > ALE_PROC_MAX) { 807 device_printf(sc->ale_dev, 808 "process_limit value out of range; " 809 "using default: %d\n", ALE_PROC_DEFAULT); 810 sc->ale_process_limit = ALE_PROC_DEFAULT; 811 } 812 } 813 814 /* Misc statistics. */ 815 ALE_SYSCTL_STAT_ADD32(ctx, child, "reset_brk_seq", 816 &stats->reset_brk_seq, 817 "Controller resets due to broken Rx sequnce number"); 818 819 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 820 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ATE statistics"); 821 parent = SYSCTL_CHILDREN(tree); 822 823 /* Rx statistics. */ 824 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 825 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics"); 826 child = SYSCTL_CHILDREN(tree); 827 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 828 &stats->rx_frames, "Good frames"); 829 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 830 &stats->rx_bcast_frames, "Good broadcast frames"); 831 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 832 &stats->rx_mcast_frames, "Good multicast frames"); 833 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 834 &stats->rx_pause_frames, "Pause control frames"); 835 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 836 &stats->rx_control_frames, "Control frames"); 837 ALE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 838 &stats->rx_crcerrs, "CRC errors"); 839 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 840 &stats->rx_lenerrs, "Frames with length mismatched"); 841 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 842 &stats->rx_bytes, "Good octets"); 843 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 844 &stats->rx_bcast_bytes, "Good broadcast octets"); 845 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 846 &stats->rx_mcast_bytes, "Good multicast octets"); 847 ALE_SYSCTL_STAT_ADD32(ctx, child, "runts", 848 &stats->rx_runts, "Too short frames"); 849 ALE_SYSCTL_STAT_ADD32(ctx, child, "fragments", 850 &stats->rx_fragments, "Fragmented frames"); 851 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 852 &stats->rx_pkts_64, "64 bytes frames"); 853 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 854 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 855 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 856 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 857 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 858 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 859 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 860 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 861 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 862 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 863 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 864 &stats->rx_pkts_1519_max, "1519 to max frames"); 865 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 866 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 867 ALE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 868 &stats->rx_fifo_oflows, "FIFO overflows"); 869 ALE_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 870 &stats->rx_rrs_errs, "Return status write-back errors"); 871 ALE_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 872 &stats->rx_alignerrs, "Alignment errors"); 873 ALE_SYSCTL_STAT_ADD32(ctx, child, "filtered", 874 &stats->rx_pkts_filtered, 875 "Frames dropped due to address filtering"); 876 877 /* Tx statistics. */ 878 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 879 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics"); 880 child = SYSCTL_CHILDREN(tree); 881 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 882 &stats->tx_frames, "Good frames"); 883 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 884 &stats->tx_bcast_frames, "Good broadcast frames"); 885 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 886 &stats->tx_mcast_frames, "Good multicast frames"); 887 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 888 &stats->tx_pause_frames, "Pause control frames"); 889 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 890 &stats->tx_control_frames, "Control frames"); 891 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 892 &stats->tx_excess_defer, "Frames with excessive derferrals"); 893 ALE_SYSCTL_STAT_ADD32(ctx, child, "defers", 894 &stats->tx_excess_defer, "Frames with derferrals"); 895 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 896 &stats->tx_bytes, "Good octets"); 897 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 898 &stats->tx_bcast_bytes, "Good broadcast octets"); 899 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 900 &stats->tx_mcast_bytes, "Good multicast octets"); 901 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 902 &stats->tx_pkts_64, "64 bytes frames"); 903 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 904 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 905 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 906 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 907 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 908 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 909 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 910 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 911 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 912 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 913 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 914 &stats->tx_pkts_1519_max, "1519 to max frames"); 915 ALE_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 916 &stats->tx_single_colls, "Single collisions"); 917 ALE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 918 &stats->tx_multi_colls, "Multiple collisions"); 919 ALE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 920 &stats->tx_late_colls, "Late collisions"); 921 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 922 &stats->tx_excess_colls, "Excessive collisions"); 923 ALE_SYSCTL_STAT_ADD32(ctx, child, "underruns", 924 &stats->tx_underrun, "FIFO underruns"); 925 ALE_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 926 &stats->tx_desc_underrun, "Descriptor write-back errors"); 927 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 928 &stats->tx_lenerrs, "Frames with length mismatched"); 929 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 930 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 931 } 932 933 #undef ALE_SYSCTL_STAT_ADD32 934 #undef ALE_SYSCTL_STAT_ADD64 935 936 struct ale_dmamap_arg { 937 bus_addr_t ale_busaddr; 938 }; 939 940 static void 941 ale_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 942 { 943 struct ale_dmamap_arg *ctx; 944 945 if (error != 0) 946 return; 947 948 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 949 950 ctx = (struct ale_dmamap_arg *)arg; 951 ctx->ale_busaddr = segs[0].ds_addr; 952 } 953 954 /* 955 * Tx descriptors/RXF0/CMB DMA blocks share ALE_DESC_ADDR_HI register 956 * which specifies high address region of DMA blocks. Therefore these 957 * blocks should have the same high address of given 4GB address 958 * space(i.e. crossing 4GB boundary is not allowed). 959 */ 960 static int 961 ale_check_boundary(struct ale_softc *sc) 962 { 963 bus_addr_t rx_cmb_end[ALE_RX_PAGES], tx_cmb_end; 964 bus_addr_t rx_page_end[ALE_RX_PAGES], tx_ring_end; 965 966 rx_page_end[0] = sc->ale_cdata.ale_rx_page[0].page_paddr + 967 sc->ale_pagesize; 968 rx_page_end[1] = sc->ale_cdata.ale_rx_page[1].page_paddr + 969 sc->ale_pagesize; 970 tx_ring_end = sc->ale_cdata.ale_tx_ring_paddr + ALE_TX_RING_SZ; 971 tx_cmb_end = sc->ale_cdata.ale_tx_cmb_paddr + ALE_TX_CMB_SZ; 972 rx_cmb_end[0] = sc->ale_cdata.ale_rx_page[0].cmb_paddr + ALE_RX_CMB_SZ; 973 rx_cmb_end[1] = sc->ale_cdata.ale_rx_page[1].cmb_paddr + ALE_RX_CMB_SZ; 974 975 if ((ALE_ADDR_HI(tx_ring_end) != 976 ALE_ADDR_HI(sc->ale_cdata.ale_tx_ring_paddr)) || 977 (ALE_ADDR_HI(rx_page_end[0]) != 978 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].page_paddr)) || 979 (ALE_ADDR_HI(rx_page_end[1]) != 980 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].page_paddr)) || 981 (ALE_ADDR_HI(tx_cmb_end) != 982 ALE_ADDR_HI(sc->ale_cdata.ale_tx_cmb_paddr)) || 983 (ALE_ADDR_HI(rx_cmb_end[0]) != 984 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].cmb_paddr)) || 985 (ALE_ADDR_HI(rx_cmb_end[1]) != 986 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].cmb_paddr))) 987 return (EFBIG); 988 989 if ((ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[0])) || 990 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[1])) || 991 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[0])) || 992 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[1])) || 993 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(tx_cmb_end))) 994 return (EFBIG); 995 996 return (0); 997 } 998 999 static int 1000 ale_dma_alloc(struct ale_softc *sc) 1001 { 1002 struct ale_txdesc *txd; 1003 bus_addr_t lowaddr; 1004 struct ale_dmamap_arg ctx; 1005 int error, guard_size, i; 1006 1007 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 1008 guard_size = ALE_JUMBO_FRAMELEN; 1009 else 1010 guard_size = ALE_MAX_FRAMELEN; 1011 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, 1012 ALE_RX_PAGE_ALIGN); 1013 lowaddr = BUS_SPACE_MAXADDR; 1014 again: 1015 /* Create parent DMA tag. */ 1016 error = bus_dma_tag_create( 1017 bus_get_dma_tag(sc->ale_dev), /* parent */ 1018 1, 0, /* alignment, boundary */ 1019 lowaddr, /* lowaddr */ 1020 BUS_SPACE_MAXADDR, /* highaddr */ 1021 NULL, NULL, /* filter, filterarg */ 1022 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1023 0, /* nsegments */ 1024 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1025 0, /* flags */ 1026 NULL, NULL, /* lockfunc, lockarg */ 1027 &sc->ale_cdata.ale_parent_tag); 1028 if (error != 0) { 1029 device_printf(sc->ale_dev, 1030 "could not create parent DMA tag.\n"); 1031 goto fail; 1032 } 1033 1034 /* Create DMA tag for Tx descriptor ring. */ 1035 error = bus_dma_tag_create( 1036 sc->ale_cdata.ale_parent_tag, /* parent */ 1037 ALE_TX_RING_ALIGN, 0, /* alignment, boundary */ 1038 BUS_SPACE_MAXADDR, /* lowaddr */ 1039 BUS_SPACE_MAXADDR, /* highaddr */ 1040 NULL, NULL, /* filter, filterarg */ 1041 ALE_TX_RING_SZ, /* maxsize */ 1042 1, /* nsegments */ 1043 ALE_TX_RING_SZ, /* maxsegsize */ 1044 0, /* flags */ 1045 NULL, NULL, /* lockfunc, lockarg */ 1046 &sc->ale_cdata.ale_tx_ring_tag); 1047 if (error != 0) { 1048 device_printf(sc->ale_dev, 1049 "could not create Tx ring DMA tag.\n"); 1050 goto fail; 1051 } 1052 1053 /* Create DMA tag for Rx pages. */ 1054 for (i = 0; i < ALE_RX_PAGES; i++) { 1055 error = bus_dma_tag_create( 1056 sc->ale_cdata.ale_parent_tag, /* parent */ 1057 ALE_RX_PAGE_ALIGN, 0, /* alignment, boundary */ 1058 BUS_SPACE_MAXADDR, /* lowaddr */ 1059 BUS_SPACE_MAXADDR, /* highaddr */ 1060 NULL, NULL, /* filter, filterarg */ 1061 sc->ale_pagesize, /* maxsize */ 1062 1, /* nsegments */ 1063 sc->ale_pagesize, /* maxsegsize */ 1064 0, /* flags */ 1065 NULL, NULL, /* lockfunc, lockarg */ 1066 &sc->ale_cdata.ale_rx_page[i].page_tag); 1067 if (error != 0) { 1068 device_printf(sc->ale_dev, 1069 "could not create Rx page %d DMA tag.\n", i); 1070 goto fail; 1071 } 1072 } 1073 1074 /* Create DMA tag for Tx coalescing message block. */ 1075 error = bus_dma_tag_create( 1076 sc->ale_cdata.ale_parent_tag, /* parent */ 1077 ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1078 BUS_SPACE_MAXADDR, /* lowaddr */ 1079 BUS_SPACE_MAXADDR, /* highaddr */ 1080 NULL, NULL, /* filter, filterarg */ 1081 ALE_TX_CMB_SZ, /* maxsize */ 1082 1, /* nsegments */ 1083 ALE_TX_CMB_SZ, /* maxsegsize */ 1084 0, /* flags */ 1085 NULL, NULL, /* lockfunc, lockarg */ 1086 &sc->ale_cdata.ale_tx_cmb_tag); 1087 if (error != 0) { 1088 device_printf(sc->ale_dev, 1089 "could not create Tx CMB DMA tag.\n"); 1090 goto fail; 1091 } 1092 1093 /* Create DMA tag for Rx coalescing message block. */ 1094 for (i = 0; i < ALE_RX_PAGES; i++) { 1095 error = bus_dma_tag_create( 1096 sc->ale_cdata.ale_parent_tag, /* parent */ 1097 ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1098 BUS_SPACE_MAXADDR, /* lowaddr */ 1099 BUS_SPACE_MAXADDR, /* highaddr */ 1100 NULL, NULL, /* filter, filterarg */ 1101 ALE_RX_CMB_SZ, /* maxsize */ 1102 1, /* nsegments */ 1103 ALE_RX_CMB_SZ, /* maxsegsize */ 1104 0, /* flags */ 1105 NULL, NULL, /* lockfunc, lockarg */ 1106 &sc->ale_cdata.ale_rx_page[i].cmb_tag); 1107 if (error != 0) { 1108 device_printf(sc->ale_dev, 1109 "could not create Rx page %d CMB DMA tag.\n", i); 1110 goto fail; 1111 } 1112 } 1113 1114 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1115 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_ring_tag, 1116 (void **)&sc->ale_cdata.ale_tx_ring, 1117 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1118 &sc->ale_cdata.ale_tx_ring_map); 1119 if (error != 0) { 1120 device_printf(sc->ale_dev, 1121 "could not allocate DMA'able memory for Tx ring.\n"); 1122 goto fail; 1123 } 1124 ctx.ale_busaddr = 0; 1125 error = bus_dmamap_load(sc->ale_cdata.ale_tx_ring_tag, 1126 sc->ale_cdata.ale_tx_ring_map, sc->ale_cdata.ale_tx_ring, 1127 ALE_TX_RING_SZ, ale_dmamap_cb, &ctx, 0); 1128 if (error != 0 || ctx.ale_busaddr == 0) { 1129 device_printf(sc->ale_dev, 1130 "could not load DMA'able memory for Tx ring.\n"); 1131 goto fail; 1132 } 1133 sc->ale_cdata.ale_tx_ring_paddr = ctx.ale_busaddr; 1134 1135 /* Rx pages. */ 1136 for (i = 0; i < ALE_RX_PAGES; i++) { 1137 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].page_tag, 1138 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr, 1139 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1140 &sc->ale_cdata.ale_rx_page[i].page_map); 1141 if (error != 0) { 1142 device_printf(sc->ale_dev, 1143 "could not allocate DMA'able memory for " 1144 "Rx page %d.\n", i); 1145 goto fail; 1146 } 1147 ctx.ale_busaddr = 0; 1148 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].page_tag, 1149 sc->ale_cdata.ale_rx_page[i].page_map, 1150 sc->ale_cdata.ale_rx_page[i].page_addr, 1151 sc->ale_pagesize, ale_dmamap_cb, &ctx, 0); 1152 if (error != 0 || ctx.ale_busaddr == 0) { 1153 device_printf(sc->ale_dev, 1154 "could not load DMA'able memory for " 1155 "Rx page %d.\n", i); 1156 goto fail; 1157 } 1158 sc->ale_cdata.ale_rx_page[i].page_paddr = ctx.ale_busaddr; 1159 } 1160 1161 /* Tx CMB. */ 1162 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_cmb_tag, 1163 (void **)&sc->ale_cdata.ale_tx_cmb, 1164 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1165 &sc->ale_cdata.ale_tx_cmb_map); 1166 if (error != 0) { 1167 device_printf(sc->ale_dev, 1168 "could not allocate DMA'able memory for Tx CMB.\n"); 1169 goto fail; 1170 } 1171 ctx.ale_busaddr = 0; 1172 error = bus_dmamap_load(sc->ale_cdata.ale_tx_cmb_tag, 1173 sc->ale_cdata.ale_tx_cmb_map, sc->ale_cdata.ale_tx_cmb, 1174 ALE_TX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1175 if (error != 0 || ctx.ale_busaddr == 0) { 1176 device_printf(sc->ale_dev, 1177 "could not load DMA'able memory for Tx CMB.\n"); 1178 goto fail; 1179 } 1180 sc->ale_cdata.ale_tx_cmb_paddr = ctx.ale_busaddr; 1181 1182 /* Rx CMB. */ 1183 for (i = 0; i < ALE_RX_PAGES; i++) { 1184 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1185 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 1186 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1187 &sc->ale_cdata.ale_rx_page[i].cmb_map); 1188 if (error != 0) { 1189 device_printf(sc->ale_dev, "could not allocate " 1190 "DMA'able memory for Rx page %d CMB.\n", i); 1191 goto fail; 1192 } 1193 ctx.ale_busaddr = 0; 1194 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1195 sc->ale_cdata.ale_rx_page[i].cmb_map, 1196 sc->ale_cdata.ale_rx_page[i].cmb_addr, 1197 ALE_RX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1198 if (error != 0 || ctx.ale_busaddr == 0) { 1199 device_printf(sc->ale_dev, "could not load DMA'able " 1200 "memory for Rx page %d CMB.\n", i); 1201 goto fail; 1202 } 1203 sc->ale_cdata.ale_rx_page[i].cmb_paddr = ctx.ale_busaddr; 1204 } 1205 1206 /* 1207 * Tx descriptors/RXF0/CMB DMA blocks share the same 1208 * high address region of 64bit DMA address space. 1209 */ 1210 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1211 (error = ale_check_boundary(sc)) != 0) { 1212 device_printf(sc->ale_dev, "4GB boundary crossed, " 1213 "switching to 32bit DMA addressing mode.\n"); 1214 ale_dma_free(sc); 1215 /* 1216 * Limit max allowable DMA address space to 32bit 1217 * and try again. 1218 */ 1219 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1220 goto again; 1221 } 1222 1223 /* 1224 * Create Tx buffer parent tag. 1225 * AR81xx allows 64bit DMA addressing of Tx buffers so it 1226 * needs separate parent DMA tag as parent DMA address space 1227 * could be restricted to be within 32bit address space by 1228 * 4GB boundary crossing. 1229 */ 1230 error = bus_dma_tag_create( 1231 bus_get_dma_tag(sc->ale_dev), /* parent */ 1232 1, 0, /* alignment, boundary */ 1233 BUS_SPACE_MAXADDR, /* lowaddr */ 1234 BUS_SPACE_MAXADDR, /* highaddr */ 1235 NULL, NULL, /* filter, filterarg */ 1236 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1237 0, /* nsegments */ 1238 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1239 0, /* flags */ 1240 NULL, NULL, /* lockfunc, lockarg */ 1241 &sc->ale_cdata.ale_buffer_tag); 1242 if (error != 0) { 1243 device_printf(sc->ale_dev, 1244 "could not create parent buffer DMA tag.\n"); 1245 goto fail; 1246 } 1247 1248 /* Create DMA tag for Tx buffers. */ 1249 error = bus_dma_tag_create( 1250 sc->ale_cdata.ale_buffer_tag, /* parent */ 1251 1, 0, /* alignment, boundary */ 1252 BUS_SPACE_MAXADDR, /* lowaddr */ 1253 BUS_SPACE_MAXADDR, /* highaddr */ 1254 NULL, NULL, /* filter, filterarg */ 1255 ALE_TSO_MAXSIZE, /* maxsize */ 1256 ALE_MAXTXSEGS, /* nsegments */ 1257 ALE_TSO_MAXSEGSIZE, /* maxsegsize */ 1258 0, /* flags */ 1259 NULL, NULL, /* lockfunc, lockarg */ 1260 &sc->ale_cdata.ale_tx_tag); 1261 if (error != 0) { 1262 device_printf(sc->ale_dev, "could not create Tx DMA tag.\n"); 1263 goto fail; 1264 } 1265 1266 /* Create DMA maps for Tx buffers. */ 1267 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1268 txd = &sc->ale_cdata.ale_txdesc[i]; 1269 txd->tx_m = NULL; 1270 txd->tx_dmamap = NULL; 1271 error = bus_dmamap_create(sc->ale_cdata.ale_tx_tag, 0, 1272 &txd->tx_dmamap); 1273 if (error != 0) { 1274 device_printf(sc->ale_dev, 1275 "could not create Tx dmamap.\n"); 1276 goto fail; 1277 } 1278 } 1279 1280 fail: 1281 return (error); 1282 } 1283 1284 static void 1285 ale_dma_free(struct ale_softc *sc) 1286 { 1287 struct ale_txdesc *txd; 1288 int i; 1289 1290 /* Tx buffers. */ 1291 if (sc->ale_cdata.ale_tx_tag != NULL) { 1292 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1293 txd = &sc->ale_cdata.ale_txdesc[i]; 1294 if (txd->tx_dmamap != NULL) { 1295 bus_dmamap_destroy(sc->ale_cdata.ale_tx_tag, 1296 txd->tx_dmamap); 1297 txd->tx_dmamap = NULL; 1298 } 1299 } 1300 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_tag); 1301 sc->ale_cdata.ale_tx_tag = NULL; 1302 } 1303 /* Tx descriptor ring. */ 1304 if (sc->ale_cdata.ale_tx_ring_tag != NULL) { 1305 if (sc->ale_cdata.ale_tx_ring_paddr != 0) 1306 bus_dmamap_unload(sc->ale_cdata.ale_tx_ring_tag, 1307 sc->ale_cdata.ale_tx_ring_map); 1308 if (sc->ale_cdata.ale_tx_ring != NULL) 1309 bus_dmamem_free(sc->ale_cdata.ale_tx_ring_tag, 1310 sc->ale_cdata.ale_tx_ring, 1311 sc->ale_cdata.ale_tx_ring_map); 1312 sc->ale_cdata.ale_tx_ring_paddr = 0; 1313 sc->ale_cdata.ale_tx_ring = NULL; 1314 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_ring_tag); 1315 sc->ale_cdata.ale_tx_ring_tag = NULL; 1316 } 1317 /* Rx page block. */ 1318 for (i = 0; i < ALE_RX_PAGES; i++) { 1319 if (sc->ale_cdata.ale_rx_page[i].page_tag != NULL) { 1320 if (sc->ale_cdata.ale_rx_page[i].page_paddr != 0) 1321 bus_dmamap_unload( 1322 sc->ale_cdata.ale_rx_page[i].page_tag, 1323 sc->ale_cdata.ale_rx_page[i].page_map); 1324 if (sc->ale_cdata.ale_rx_page[i].page_addr != NULL) 1325 bus_dmamem_free( 1326 sc->ale_cdata.ale_rx_page[i].page_tag, 1327 sc->ale_cdata.ale_rx_page[i].page_addr, 1328 sc->ale_cdata.ale_rx_page[i].page_map); 1329 sc->ale_cdata.ale_rx_page[i].page_paddr = 0; 1330 sc->ale_cdata.ale_rx_page[i].page_addr = NULL; 1331 bus_dma_tag_destroy( 1332 sc->ale_cdata.ale_rx_page[i].page_tag); 1333 sc->ale_cdata.ale_rx_page[i].page_tag = NULL; 1334 } 1335 } 1336 /* Rx CMB. */ 1337 for (i = 0; i < ALE_RX_PAGES; i++) { 1338 if (sc->ale_cdata.ale_rx_page[i].cmb_tag != NULL) { 1339 if (sc->ale_cdata.ale_rx_page[i].cmb_paddr != 0) 1340 bus_dmamap_unload( 1341 sc->ale_cdata.ale_rx_page[i].cmb_tag, 1342 sc->ale_cdata.ale_rx_page[i].cmb_map); 1343 if (sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) 1344 bus_dmamem_free( 1345 sc->ale_cdata.ale_rx_page[i].cmb_tag, 1346 sc->ale_cdata.ale_rx_page[i].cmb_addr, 1347 sc->ale_cdata.ale_rx_page[i].cmb_map); 1348 sc->ale_cdata.ale_rx_page[i].cmb_paddr = 0; 1349 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; 1350 bus_dma_tag_destroy( 1351 sc->ale_cdata.ale_rx_page[i].cmb_tag); 1352 sc->ale_cdata.ale_rx_page[i].cmb_tag = NULL; 1353 } 1354 } 1355 /* Tx CMB. */ 1356 if (sc->ale_cdata.ale_tx_cmb_tag != NULL) { 1357 if (sc->ale_cdata.ale_tx_cmb_paddr != 0) 1358 bus_dmamap_unload(sc->ale_cdata.ale_tx_cmb_tag, 1359 sc->ale_cdata.ale_tx_cmb_map); 1360 if (sc->ale_cdata.ale_tx_cmb != NULL) 1361 bus_dmamem_free(sc->ale_cdata.ale_tx_cmb_tag, 1362 sc->ale_cdata.ale_tx_cmb, 1363 sc->ale_cdata.ale_tx_cmb_map); 1364 sc->ale_cdata.ale_tx_cmb_paddr = 0; 1365 sc->ale_cdata.ale_tx_cmb = NULL; 1366 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_cmb_tag); 1367 sc->ale_cdata.ale_tx_cmb_tag = NULL; 1368 } 1369 if (sc->ale_cdata.ale_buffer_tag != NULL) { 1370 bus_dma_tag_destroy(sc->ale_cdata.ale_buffer_tag); 1371 sc->ale_cdata.ale_buffer_tag = NULL; 1372 } 1373 if (sc->ale_cdata.ale_parent_tag != NULL) { 1374 bus_dma_tag_destroy(sc->ale_cdata.ale_parent_tag); 1375 sc->ale_cdata.ale_parent_tag = NULL; 1376 } 1377 } 1378 1379 static int 1380 ale_shutdown(device_t dev) 1381 { 1382 1383 return (ale_suspend(dev)); 1384 } 1385 1386 /* 1387 * Note, this driver resets the link speed to 10/100Mbps by 1388 * restarting auto-negotiation in suspend/shutdown phase but we 1389 * don't know whether that auto-negotiation would succeed or not 1390 * as driver has no control after powering off/suspend operation. 1391 * If the renegotiation fail WOL may not work. Running at 1Gbps 1392 * will draw more power than 375mA at 3.3V which is specified in 1393 * PCI specification and that would result in complete 1394 * shutdowning power to ethernet controller. 1395 * 1396 * TODO 1397 * Save current negotiated media speed/duplex/flow-control to 1398 * softc and restore the same link again after resuming. PHY 1399 * handling such as power down/resetting to 100Mbps may be better 1400 * handled in suspend method in phy driver. 1401 */ 1402 static void 1403 ale_setlinkspeed(struct ale_softc *sc) 1404 { 1405 struct mii_data *mii; 1406 int aneg, i; 1407 1408 mii = device_get_softc(sc->ale_miibus); 1409 mii_pollstat(mii); 1410 aneg = 0; 1411 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1412 (IFM_ACTIVE | IFM_AVALID)) { 1413 switch IFM_SUBTYPE(mii->mii_media_active) { 1414 case IFM_10_T: 1415 case IFM_100_TX: 1416 return; 1417 case IFM_1000_T: 1418 aneg++; 1419 break; 1420 default: 1421 break; 1422 } 1423 } 1424 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_100T2CR, 0); 1425 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1426 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1427 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1428 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1429 DELAY(1000); 1430 if (aneg != 0) { 1431 /* 1432 * Poll link state until ale(4) get a 10/100Mbps link. 1433 */ 1434 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1435 mii_pollstat(mii); 1436 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 1437 == (IFM_ACTIVE | IFM_AVALID)) { 1438 switch (IFM_SUBTYPE( 1439 mii->mii_media_active)) { 1440 case IFM_10_T: 1441 case IFM_100_TX: 1442 ale_mac_config(sc); 1443 return; 1444 default: 1445 break; 1446 } 1447 } 1448 ALE_UNLOCK(sc); 1449 pause("alelnk", hz); 1450 ALE_LOCK(sc); 1451 } 1452 if (i == MII_ANEGTICKS_GIGE) 1453 device_printf(sc->ale_dev, 1454 "establishing a link failed, WOL may not work!"); 1455 } 1456 /* 1457 * No link, force MAC to have 100Mbps, full-duplex link. 1458 * This is the last resort and may/may not work. 1459 */ 1460 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1461 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1462 ale_mac_config(sc); 1463 } 1464 1465 static void 1466 ale_setwol(struct ale_softc *sc) 1467 { 1468 if_t ifp; 1469 uint32_t reg, pmcs; 1470 uint16_t pmstat; 1471 int pmc; 1472 1473 ALE_LOCK_ASSERT(sc); 1474 1475 if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) != 0) { 1476 /* Disable WOL. */ 1477 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 1478 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1479 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1480 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1481 /* Force PHY power down. */ 1482 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1483 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1484 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_PHY_PLL_ON | 1485 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_IDDQ | 1486 GPHY_CTRL_PCLK_SEL_DIS | GPHY_CTRL_PWDOWN_HW); 1487 return; 1488 } 1489 1490 ifp = sc->ale_ifp; 1491 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { 1492 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 1493 ale_setlinkspeed(sc); 1494 } 1495 1496 pmcs = 0; 1497 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 1498 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1499 CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs); 1500 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1501 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 1502 MAC_CFG_BCAST); 1503 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0) 1504 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1505 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 1506 reg |= MAC_CFG_RX_ENB; 1507 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1508 1509 if ((if_getcapenable(ifp) & IFCAP_WOL) == 0) { 1510 /* WOL disabled, PHY power down. */ 1511 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1512 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1513 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1514 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1515 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1516 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 1517 GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PCLK_SEL_DIS | 1518 GPHY_CTRL_PWDOWN_HW); 1519 } 1520 /* Request PME. */ 1521 pmstat = pci_read_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, 2); 1522 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1523 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 1524 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1525 pci_write_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1526 } 1527 1528 static int 1529 ale_suspend(device_t dev) 1530 { 1531 struct ale_softc *sc; 1532 1533 sc = device_get_softc(dev); 1534 1535 ALE_LOCK(sc); 1536 ale_stop(sc); 1537 ale_setwol(sc); 1538 ALE_UNLOCK(sc); 1539 1540 return (0); 1541 } 1542 1543 static int 1544 ale_resume(device_t dev) 1545 { 1546 struct ale_softc *sc; 1547 if_t ifp; 1548 int pmc; 1549 uint16_t pmstat; 1550 1551 sc = device_get_softc(dev); 1552 1553 ALE_LOCK(sc); 1554 if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) == 0) { 1555 /* Disable PME and clear PME status. */ 1556 pmstat = pci_read_config(sc->ale_dev, 1557 pmc + PCIR_POWER_STATUS, 2); 1558 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 1559 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1560 pci_write_config(sc->ale_dev, 1561 pmc + PCIR_POWER_STATUS, pmstat, 2); 1562 } 1563 } 1564 /* Reset PHY. */ 1565 ale_phy_reset(sc); 1566 ifp = sc->ale_ifp; 1567 if ((if_getflags(ifp) & IFF_UP) != 0) { 1568 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1569 ale_init_locked(sc); 1570 } 1571 ALE_UNLOCK(sc); 1572 1573 return (0); 1574 } 1575 1576 static int 1577 ale_encap(struct ale_softc *sc, struct mbuf **m_head) 1578 { 1579 struct ale_txdesc *txd, *txd_last; 1580 struct tx_desc *desc; 1581 struct mbuf *m; 1582 struct ip *ip; 1583 struct tcphdr *tcp; 1584 bus_dma_segment_t txsegs[ALE_MAXTXSEGS]; 1585 bus_dmamap_t map; 1586 uint32_t cflags, hdrlen, ip_off, poff, vtag; 1587 int error, i, nsegs, prod, si; 1588 1589 ALE_LOCK_ASSERT(sc); 1590 1591 M_ASSERTPKTHDR((*m_head)); 1592 1593 m = *m_head; 1594 ip = NULL; 1595 tcp = NULL; 1596 cflags = vtag = 0; 1597 ip_off = poff = 0; 1598 if ((m->m_pkthdr.csum_flags & (ALE_CSUM_FEATURES | CSUM_TSO)) != 0) { 1599 /* 1600 * AR81xx requires offset of TCP/UDP payload in its Tx 1601 * descriptor to perform hardware Tx checksum offload. 1602 * Additionally, TSO requires IP/TCP header size and 1603 * modification of IP/TCP header in order to make TSO 1604 * engine work. This kind of operation takes many CPU 1605 * cycles on FreeBSD so fast host CPU is required to 1606 * get smooth TSO performance. 1607 */ 1608 struct ether_header *eh; 1609 1610 if (M_WRITABLE(m) == 0) { 1611 /* Get a writable copy. */ 1612 m = m_dup(*m_head, M_NOWAIT); 1613 /* Release original mbufs. */ 1614 m_freem(*m_head); 1615 if (m == NULL) { 1616 *m_head = NULL; 1617 return (ENOBUFS); 1618 } 1619 *m_head = m; 1620 } 1621 1622 /* 1623 * Buggy-controller requires 4 byte aligned Tx buffer 1624 * to make custom checksum offload work. 1625 */ 1626 if ((sc->ale_flags & ALE_FLAG_TXCSUM_BUG) != 0 && 1627 (m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0 && 1628 (mtod(m, intptr_t) & 3) != 0) { 1629 m = m_defrag(*m_head, M_NOWAIT); 1630 if (m == NULL) { 1631 m_freem(*m_head); 1632 *m_head = NULL; 1633 return (ENOBUFS); 1634 } 1635 *m_head = m; 1636 } 1637 1638 ip_off = sizeof(struct ether_header); 1639 m = m_pullup(m, ip_off); 1640 if (m == NULL) { 1641 *m_head = NULL; 1642 return (ENOBUFS); 1643 } 1644 eh = mtod(m, struct ether_header *); 1645 /* 1646 * Check if hardware VLAN insertion is off. 1647 * Additional check for LLC/SNAP frame? 1648 */ 1649 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1650 ip_off = sizeof(struct ether_vlan_header); 1651 m = m_pullup(m, ip_off); 1652 if (m == NULL) { 1653 *m_head = NULL; 1654 return (ENOBUFS); 1655 } 1656 } 1657 m = m_pullup(m, ip_off + sizeof(struct ip)); 1658 if (m == NULL) { 1659 *m_head = NULL; 1660 return (ENOBUFS); 1661 } 1662 ip = (struct ip *)(mtod(m, char *) + ip_off); 1663 poff = ip_off + (ip->ip_hl << 2); 1664 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1665 /* 1666 * XXX 1667 * AR81xx requires the first descriptor should 1668 * not include any TCP playload for TSO case. 1669 * (i.e. ethernet header + IP + TCP header only) 1670 * m_pullup(9) above will ensure this too. 1671 * However it's not correct if the first mbuf 1672 * of the chain does not use cluster. 1673 */ 1674 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1675 if (m == NULL) { 1676 *m_head = NULL; 1677 return (ENOBUFS); 1678 } 1679 ip = (struct ip *)(mtod(m, char *) + ip_off); 1680 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1681 m = m_pullup(m, poff + (tcp->th_off << 2)); 1682 if (m == NULL) { 1683 *m_head = NULL; 1684 return (ENOBUFS); 1685 } 1686 /* 1687 * AR81xx requires IP/TCP header size and offset as 1688 * well as TCP pseudo checksum which complicates 1689 * TSO configuration. I guess this comes from the 1690 * adherence to Microsoft NDIS Large Send 1691 * specification which requires insertion of 1692 * pseudo checksum by upper stack. The pseudo 1693 * checksum that NDIS refers to doesn't include 1694 * TCP payload length so ale(4) should recompute 1695 * the pseudo checksum here. Hopefully this wouldn't 1696 * be much burden on modern CPUs. 1697 * Reset IP checksum and recompute TCP pseudo 1698 * checksum as NDIS specification said. 1699 */ 1700 ip->ip_sum = 0; 1701 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1702 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1703 } 1704 *m_head = m; 1705 } 1706 1707 si = prod = sc->ale_cdata.ale_tx_prod; 1708 txd = &sc->ale_cdata.ale_txdesc[prod]; 1709 txd_last = txd; 1710 map = txd->tx_dmamap; 1711 1712 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1713 *m_head, txsegs, &nsegs, 0); 1714 if (error == EFBIG) { 1715 m = m_collapse(*m_head, M_NOWAIT, ALE_MAXTXSEGS); 1716 if (m == NULL) { 1717 m_freem(*m_head); 1718 *m_head = NULL; 1719 return (ENOMEM); 1720 } 1721 *m_head = m; 1722 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1723 *m_head, txsegs, &nsegs, 0); 1724 if (error != 0) { 1725 m_freem(*m_head); 1726 *m_head = NULL; 1727 return (error); 1728 } 1729 } else if (error != 0) 1730 return (error); 1731 if (nsegs == 0) { 1732 m_freem(*m_head); 1733 *m_head = NULL; 1734 return (EIO); 1735 } 1736 1737 /* Check descriptor overrun. */ 1738 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 3) { 1739 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, map); 1740 return (ENOBUFS); 1741 } 1742 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, map, BUS_DMASYNC_PREWRITE); 1743 1744 m = *m_head; 1745 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1746 /* Request TSO and set MSS. */ 1747 cflags |= ALE_TD_TSO; 1748 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << ALE_TD_MSS_SHIFT); 1749 /* Set IP/TCP header size. */ 1750 cflags |= ip->ip_hl << ALE_TD_IPHDR_LEN_SHIFT; 1751 cflags |= tcp->th_off << ALE_TD_TCPHDR_LEN_SHIFT; 1752 } else if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { 1753 /* 1754 * AR81xx supports Tx custom checksum offload feature 1755 * that offloads single 16bit checksum computation. 1756 * So you can choose one among IP, TCP and UDP. 1757 * Normally driver sets checksum start/insertion 1758 * position from the information of TCP/UDP frame as 1759 * TCP/UDP checksum takes more time than that of IP. 1760 * However it seems that custom checksum offload 1761 * requires 4 bytes aligned Tx buffers due to hardware 1762 * bug. 1763 * AR81xx also supports explicit Tx checksum computation 1764 * if it is told that the size of IP header and TCP 1765 * header(for UDP, the header size does not matter 1766 * because it's fixed length). However with this scheme 1767 * TSO does not work so you have to choose one either 1768 * TSO or explicit Tx checksum offload. I chosen TSO 1769 * plus custom checksum offload with work-around which 1770 * will cover most common usage for this consumer 1771 * ethernet controller. The work-around takes a lot of 1772 * CPU cycles if Tx buffer is not aligned on 4 bytes 1773 * boundary, though. 1774 */ 1775 cflags |= ALE_TD_CXSUM; 1776 /* Set checksum start offset. */ 1777 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); 1778 /* Set checksum insertion position of TCP/UDP. */ 1779 cflags |= ((poff + m->m_pkthdr.csum_data) << 1780 ALE_TD_CSUM_XSUMOFFSET_SHIFT); 1781 } 1782 1783 /* Configure VLAN hardware tag insertion. */ 1784 if ((m->m_flags & M_VLANTAG) != 0) { 1785 vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1786 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); 1787 cflags |= ALE_TD_INSERT_VLAN_TAG; 1788 } 1789 1790 i = 0; 1791 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1792 /* 1793 * Make sure the first fragment contains 1794 * only ethernet and IP/TCP header with options. 1795 */ 1796 hdrlen = poff + (tcp->th_off << 2); 1797 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1798 desc->addr = htole64(txsegs[i].ds_addr); 1799 desc->len = htole32(ALE_TX_BYTES(hdrlen) | vtag); 1800 desc->flags = htole32(cflags); 1801 sc->ale_cdata.ale_tx_cnt++; 1802 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1803 if (m->m_len - hdrlen > 0) { 1804 /* Handle remaining payload of the first fragment. */ 1805 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1806 desc->addr = htole64(txsegs[i].ds_addr + hdrlen); 1807 desc->len = htole32(ALE_TX_BYTES(m->m_len - hdrlen) | 1808 vtag); 1809 desc->flags = htole32(cflags); 1810 sc->ale_cdata.ale_tx_cnt++; 1811 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1812 } 1813 i = 1; 1814 } 1815 for (; i < nsegs; i++) { 1816 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1817 desc->addr = htole64(txsegs[i].ds_addr); 1818 desc->len = htole32(ALE_TX_BYTES(txsegs[i].ds_len) | vtag); 1819 desc->flags = htole32(cflags); 1820 sc->ale_cdata.ale_tx_cnt++; 1821 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1822 } 1823 /* Update producer index. */ 1824 sc->ale_cdata.ale_tx_prod = prod; 1825 /* Set TSO header on the first descriptor. */ 1826 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1827 desc = &sc->ale_cdata.ale_tx_ring[si]; 1828 desc->flags |= htole32(ALE_TD_TSO_HDR); 1829 } 1830 1831 /* Finally set EOP on the last descriptor. */ 1832 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; 1833 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1834 desc->flags |= htole32(ALE_TD_EOP); 1835 1836 /* Swap dmamap of the first and the last. */ 1837 txd = &sc->ale_cdata.ale_txdesc[prod]; 1838 map = txd_last->tx_dmamap; 1839 txd_last->tx_dmamap = txd->tx_dmamap; 1840 txd->tx_dmamap = map; 1841 txd->tx_m = m; 1842 1843 /* Sync descriptors. */ 1844 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 1845 sc->ale_cdata.ale_tx_ring_map, 1846 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1847 1848 return (0); 1849 } 1850 1851 static void 1852 ale_start(if_t ifp) 1853 { 1854 struct ale_softc *sc; 1855 1856 sc = if_getsoftc(ifp); 1857 ALE_LOCK(sc); 1858 ale_start_locked(ifp); 1859 ALE_UNLOCK(sc); 1860 } 1861 1862 static void 1863 ale_start_locked(if_t ifp) 1864 { 1865 struct ale_softc *sc; 1866 struct mbuf *m_head; 1867 int enq; 1868 1869 sc = if_getsoftc(ifp); 1870 1871 ALE_LOCK_ASSERT(sc); 1872 1873 /* Reclaim transmitted frames. */ 1874 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) 1875 ale_txeof(sc); 1876 1877 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1878 IFF_DRV_RUNNING || (sc->ale_flags & ALE_FLAG_LINK) == 0) 1879 return; 1880 1881 for (enq = 0; !if_sendq_empty(ifp); ) { 1882 m_head = if_dequeue(ifp); 1883 if (m_head == NULL) 1884 break; 1885 /* 1886 * Pack the data into the transmit ring. If we 1887 * don't have room, set the OACTIVE flag and wait 1888 * for the NIC to drain the ring. 1889 */ 1890 if (ale_encap(sc, &m_head)) { 1891 if (m_head == NULL) 1892 break; 1893 if_sendq_prepend(ifp, m_head); 1894 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1895 break; 1896 } 1897 1898 enq++; 1899 /* 1900 * If there's a BPF listener, bounce a copy of this frame 1901 * to him. 1902 */ 1903 ETHER_BPF_MTAP(ifp, m_head); 1904 } 1905 1906 if (enq > 0) { 1907 /* Kick. */ 1908 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, 1909 sc->ale_cdata.ale_tx_prod); 1910 /* Set a timeout in case the chip goes out to lunch. */ 1911 sc->ale_watchdog_timer = ALE_TX_TIMEOUT; 1912 } 1913 } 1914 1915 static void 1916 ale_watchdog(struct ale_softc *sc) 1917 { 1918 if_t ifp; 1919 1920 ALE_LOCK_ASSERT(sc); 1921 1922 if (sc->ale_watchdog_timer == 0 || --sc->ale_watchdog_timer) 1923 return; 1924 1925 ifp = sc->ale_ifp; 1926 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1927 if_printf(sc->ale_ifp, "watchdog timeout (lost link)\n"); 1928 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1929 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1930 ale_init_locked(sc); 1931 return; 1932 } 1933 if_printf(sc->ale_ifp, "watchdog timeout -- resetting\n"); 1934 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1935 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1936 ale_init_locked(sc); 1937 if (!if_sendq_empty(ifp)) 1938 ale_start_locked(ifp); 1939 } 1940 1941 static int 1942 ale_ioctl(if_t ifp, u_long cmd, caddr_t data) 1943 { 1944 struct ale_softc *sc; 1945 struct ifreq *ifr; 1946 struct mii_data *mii; 1947 int error, mask; 1948 1949 sc = if_getsoftc(ifp); 1950 ifr = (struct ifreq *)data; 1951 error = 0; 1952 switch (cmd) { 1953 case SIOCSIFMTU: 1954 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALE_JUMBO_MTU || 1955 ((sc->ale_flags & ALE_FLAG_JUMBO) == 0 && 1956 ifr->ifr_mtu > ETHERMTU)) 1957 error = EINVAL; 1958 else if (if_getmtu(ifp) != ifr->ifr_mtu) { 1959 ALE_LOCK(sc); 1960 if_setmtu(ifp, ifr->ifr_mtu); 1961 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1962 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1963 ale_init_locked(sc); 1964 } 1965 ALE_UNLOCK(sc); 1966 } 1967 break; 1968 case SIOCSIFFLAGS: 1969 ALE_LOCK(sc); 1970 if ((if_getflags(ifp) & IFF_UP) != 0) { 1971 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1972 if (((if_getflags(ifp) ^ sc->ale_if_flags) 1973 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1974 ale_rxfilter(sc); 1975 } else { 1976 ale_init_locked(sc); 1977 } 1978 } else { 1979 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1980 ale_stop(sc); 1981 } 1982 sc->ale_if_flags = if_getflags(ifp); 1983 ALE_UNLOCK(sc); 1984 break; 1985 case SIOCADDMULTI: 1986 case SIOCDELMULTI: 1987 ALE_LOCK(sc); 1988 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1989 ale_rxfilter(sc); 1990 ALE_UNLOCK(sc); 1991 break; 1992 case SIOCSIFMEDIA: 1993 case SIOCGIFMEDIA: 1994 mii = device_get_softc(sc->ale_miibus); 1995 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1996 break; 1997 case SIOCSIFCAP: 1998 ALE_LOCK(sc); 1999 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 2000 if ((mask & IFCAP_TXCSUM) != 0 && 2001 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 2002 if_togglecapenable(ifp, IFCAP_TXCSUM); 2003 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 2004 if_sethwassistbits(ifp, ALE_CSUM_FEATURES, 0); 2005 else 2006 if_sethwassistbits(ifp, 0, ALE_CSUM_FEATURES); 2007 } 2008 if ((mask & IFCAP_RXCSUM) != 0 && 2009 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) 2010 if_togglecapenable(ifp, IFCAP_RXCSUM); 2011 if ((mask & IFCAP_TSO4) != 0 && 2012 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) { 2013 if_togglecapenable(ifp, IFCAP_TSO4); 2014 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0) 2015 if_sethwassistbits(ifp, CSUM_TSO, 0); 2016 else 2017 if_sethwassistbits(ifp, 0, CSUM_TSO); 2018 } 2019 2020 if ((mask & IFCAP_WOL_MCAST) != 0 && 2021 (if_getcapabilities(ifp) & IFCAP_WOL_MCAST) != 0) 2022 if_togglecapenable(ifp, IFCAP_WOL_MCAST); 2023 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2024 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0) 2025 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 2026 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2027 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0) 2028 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 2029 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2030 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) 2031 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 2032 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2033 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 2034 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 2035 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) 2036 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO); 2037 ale_rxvlan(sc); 2038 } 2039 ALE_UNLOCK(sc); 2040 VLAN_CAPABILITIES(ifp); 2041 break; 2042 default: 2043 error = ether_ioctl(ifp, cmd, data); 2044 break; 2045 } 2046 2047 return (error); 2048 } 2049 2050 static void 2051 ale_mac_config(struct ale_softc *sc) 2052 { 2053 struct mii_data *mii; 2054 uint32_t reg; 2055 2056 ALE_LOCK_ASSERT(sc); 2057 2058 mii = device_get_softc(sc->ale_miibus); 2059 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2060 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2061 MAC_CFG_SPEED_MASK); 2062 /* Reprogram MAC with resolved speed/duplex. */ 2063 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2064 case IFM_10_T: 2065 case IFM_100_TX: 2066 reg |= MAC_CFG_SPEED_10_100; 2067 break; 2068 case IFM_1000_T: 2069 reg |= MAC_CFG_SPEED_1000; 2070 break; 2071 } 2072 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2073 reg |= MAC_CFG_FULL_DUPLEX; 2074 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2075 reg |= MAC_CFG_TX_FC; 2076 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2077 reg |= MAC_CFG_RX_FC; 2078 } 2079 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2080 } 2081 2082 static void 2083 ale_stats_clear(struct ale_softc *sc) 2084 { 2085 struct smb sb; 2086 uint32_t *reg; 2087 int i; 2088 2089 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2090 CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2091 i += sizeof(uint32_t); 2092 } 2093 /* Read Tx statistics. */ 2094 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2095 CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2096 i += sizeof(uint32_t); 2097 } 2098 } 2099 2100 static void 2101 ale_stats_update(struct ale_softc *sc) 2102 { 2103 struct ale_hw_stats *stat; 2104 struct smb sb, *smb; 2105 if_t ifp; 2106 uint32_t *reg; 2107 int i; 2108 2109 ALE_LOCK_ASSERT(sc); 2110 2111 ifp = sc->ale_ifp; 2112 stat = &sc->ale_stats; 2113 smb = &sb; 2114 2115 /* Read Rx statistics. */ 2116 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2117 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2118 i += sizeof(uint32_t); 2119 } 2120 /* Read Tx statistics. */ 2121 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2122 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2123 i += sizeof(uint32_t); 2124 } 2125 2126 /* Rx stats. */ 2127 stat->rx_frames += smb->rx_frames; 2128 stat->rx_bcast_frames += smb->rx_bcast_frames; 2129 stat->rx_mcast_frames += smb->rx_mcast_frames; 2130 stat->rx_pause_frames += smb->rx_pause_frames; 2131 stat->rx_control_frames += smb->rx_control_frames; 2132 stat->rx_crcerrs += smb->rx_crcerrs; 2133 stat->rx_lenerrs += smb->rx_lenerrs; 2134 stat->rx_bytes += smb->rx_bytes; 2135 stat->rx_runts += smb->rx_runts; 2136 stat->rx_fragments += smb->rx_fragments; 2137 stat->rx_pkts_64 += smb->rx_pkts_64; 2138 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2139 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2140 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2141 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2142 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2143 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2144 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2145 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2146 stat->rx_rrs_errs += smb->rx_rrs_errs; 2147 stat->rx_alignerrs += smb->rx_alignerrs; 2148 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2149 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2150 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2151 2152 /* Tx stats. */ 2153 stat->tx_frames += smb->tx_frames; 2154 stat->tx_bcast_frames += smb->tx_bcast_frames; 2155 stat->tx_mcast_frames += smb->tx_mcast_frames; 2156 stat->tx_pause_frames += smb->tx_pause_frames; 2157 stat->tx_excess_defer += smb->tx_excess_defer; 2158 stat->tx_control_frames += smb->tx_control_frames; 2159 stat->tx_deferred += smb->tx_deferred; 2160 stat->tx_bytes += smb->tx_bytes; 2161 stat->tx_pkts_64 += smb->tx_pkts_64; 2162 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2163 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2164 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2165 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2166 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2167 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2168 stat->tx_single_colls += smb->tx_single_colls; 2169 stat->tx_multi_colls += smb->tx_multi_colls; 2170 stat->tx_late_colls += smb->tx_late_colls; 2171 stat->tx_excess_colls += smb->tx_excess_colls; 2172 stat->tx_underrun += smb->tx_underrun; 2173 stat->tx_desc_underrun += smb->tx_desc_underrun; 2174 stat->tx_lenerrs += smb->tx_lenerrs; 2175 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2176 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2177 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2178 2179 /* Update counters in ifnet. */ 2180 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames); 2181 2182 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls + 2183 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2184 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT); 2185 2186 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_late_colls + 2187 smb->tx_excess_colls + smb->tx_underrun + smb->tx_pkts_truncated); 2188 2189 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames); 2190 2191 if_inc_counter(ifp, IFCOUNTER_IERRORS, 2192 smb->rx_crcerrs + smb->rx_lenerrs + 2193 smb->rx_runts + smb->rx_pkts_truncated + 2194 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2195 smb->rx_alignerrs); 2196 } 2197 2198 static int 2199 ale_intr(void *arg) 2200 { 2201 struct ale_softc *sc; 2202 uint32_t status; 2203 2204 sc = (struct ale_softc *)arg; 2205 2206 status = CSR_READ_4(sc, ALE_INTR_STATUS); 2207 if ((status & ALE_INTRS) == 0) 2208 return (FILTER_STRAY); 2209 /* Disable interrupts. */ 2210 CSR_WRITE_4(sc, ALE_INTR_STATUS, INTR_DIS_INT); 2211 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2212 2213 return (FILTER_HANDLED); 2214 } 2215 2216 static void 2217 ale_int_task(void *arg, int pending) 2218 { 2219 struct ale_softc *sc; 2220 if_t ifp; 2221 uint32_t status; 2222 int more; 2223 2224 sc = (struct ale_softc *)arg; 2225 2226 status = CSR_READ_4(sc, ALE_INTR_STATUS); 2227 ALE_LOCK(sc); 2228 if (sc->ale_morework != 0) 2229 status |= INTR_RX_PKT; 2230 if ((status & ALE_INTRS) == 0) 2231 goto done; 2232 2233 /* Acknowledge interrupts but still disable interrupts. */ 2234 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); 2235 2236 ifp = sc->ale_ifp; 2237 more = 0; 2238 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2239 more = ale_rxeof(sc, sc->ale_process_limit); 2240 if (more == EAGAIN) 2241 sc->ale_morework = 1; 2242 else if (more == EIO) { 2243 sc->ale_stats.reset_brk_seq++; 2244 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2245 ale_init_locked(sc); 2246 ALE_UNLOCK(sc); 2247 return; 2248 } 2249 2250 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 2251 if ((status & INTR_DMA_RD_TO_RST) != 0) 2252 device_printf(sc->ale_dev, 2253 "DMA read error! -- resetting\n"); 2254 if ((status & INTR_DMA_WR_TO_RST) != 0) 2255 device_printf(sc->ale_dev, 2256 "DMA write error! -- resetting\n"); 2257 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2258 ale_init_locked(sc); 2259 ALE_UNLOCK(sc); 2260 return; 2261 } 2262 if (!if_sendq_empty(ifp)) 2263 ale_start_locked(ifp); 2264 } 2265 2266 if (more == EAGAIN || 2267 (CSR_READ_4(sc, ALE_INTR_STATUS) & ALE_INTRS) != 0) { 2268 ALE_UNLOCK(sc); 2269 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2270 return; 2271 } 2272 2273 done: 2274 ALE_UNLOCK(sc); 2275 2276 /* Re-enable interrupts. */ 2277 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); 2278 } 2279 2280 static void 2281 ale_txeof(struct ale_softc *sc) 2282 { 2283 if_t ifp; 2284 struct ale_txdesc *txd; 2285 uint32_t cons, prod; 2286 int prog; 2287 2288 ALE_LOCK_ASSERT(sc); 2289 2290 ifp = sc->ale_ifp; 2291 2292 if (sc->ale_cdata.ale_tx_cnt == 0) 2293 return; 2294 2295 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2296 sc->ale_cdata.ale_tx_ring_map, 2297 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2298 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { 2299 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2300 sc->ale_cdata.ale_tx_cmb_map, 2301 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2302 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; 2303 } else 2304 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); 2305 cons = sc->ale_cdata.ale_tx_cons; 2306 /* 2307 * Go through our Tx list and free mbufs for those 2308 * frames which have been transmitted. 2309 */ 2310 for (prog = 0; cons != prod; prog++, 2311 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { 2312 if (sc->ale_cdata.ale_tx_cnt <= 0) 2313 break; 2314 prog++; 2315 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2316 sc->ale_cdata.ale_tx_cnt--; 2317 txd = &sc->ale_cdata.ale_txdesc[cons]; 2318 if (txd->tx_m != NULL) { 2319 /* Reclaim transmitted mbufs. */ 2320 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2321 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2322 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2323 txd->tx_dmamap); 2324 m_freem(txd->tx_m); 2325 txd->tx_m = NULL; 2326 } 2327 } 2328 2329 if (prog > 0) { 2330 sc->ale_cdata.ale_tx_cons = cons; 2331 /* 2332 * Unarm watchdog timer only when there is no pending 2333 * Tx descriptors in queue. 2334 */ 2335 if (sc->ale_cdata.ale_tx_cnt == 0) 2336 sc->ale_watchdog_timer = 0; 2337 } 2338 } 2339 2340 static void 2341 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, 2342 uint32_t length, uint32_t *prod) 2343 { 2344 struct ale_rx_page *rx_page; 2345 2346 rx_page = *page; 2347 /* Update consumer position. */ 2348 rx_page->cons += roundup(length + sizeof(struct rx_rs), 2349 ALE_RX_PAGE_ALIGN); 2350 if (rx_page->cons >= ALE_RX_PAGE_SZ) { 2351 /* 2352 * End of Rx page reached, let hardware reuse 2353 * this page. 2354 */ 2355 rx_page->cons = 0; 2356 *rx_page->cmb_addr = 0; 2357 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2358 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2359 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, 2360 RXF_VALID); 2361 /* Switch to alternate Rx page. */ 2362 sc->ale_cdata.ale_rx_curp ^= 1; 2363 rx_page = *page = 2364 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2365 /* Page flipped, sync CMB and Rx page. */ 2366 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2367 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2368 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2369 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2370 /* Sync completed, cache updated producer index. */ 2371 *prod = *rx_page->cmb_addr; 2372 } 2373 } 2374 2375 /* 2376 * It seems that AR81xx controller can compute partial checksum. 2377 * The partial checksum value can be used to accelerate checksum 2378 * computation for fragmented TCP/UDP packets. Upper network stack 2379 * already takes advantage of the partial checksum value in IP 2380 * reassembly stage. But I'm not sure the correctness of the 2381 * partial hardware checksum assistance due to lack of data sheet. 2382 * In addition, the Rx feature of controller that requires copying 2383 * for every frames effectively nullifies one of most nice offload 2384 * capability of controller. 2385 */ 2386 static void 2387 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) 2388 { 2389 if_t ifp; 2390 struct ip *ip; 2391 char *p; 2392 2393 ifp = sc->ale_ifp; 2394 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2395 if ((status & ALE_RD_IPCSUM_NOK) == 0) 2396 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2397 2398 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { 2399 if (((status & ALE_RD_IPV4_FRAG) == 0) && 2400 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && 2401 ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) { 2402 m->m_pkthdr.csum_flags |= 2403 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2404 m->m_pkthdr.csum_data = 0xffff; 2405 } 2406 } else { 2407 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 && 2408 (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) { 2409 p = mtod(m, char *); 2410 p += ETHER_HDR_LEN; 2411 if ((status & ALE_RD_802_3) != 0) 2412 p += LLC_SNAPFRAMELEN; 2413 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0 && 2414 (status & ALE_RD_VLAN) != 0) 2415 p += ETHER_VLAN_ENCAP_LEN; 2416 ip = (struct ip *)p; 2417 if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0) 2418 return; 2419 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 2420 CSUM_PSEUDO_HDR; 2421 m->m_pkthdr.csum_data = 0xffff; 2422 } 2423 } 2424 /* 2425 * Don't mark bad checksum for TCP/UDP frames 2426 * as fragmented frames may always have set 2427 * bad checksummed bit of frame status. 2428 */ 2429 } 2430 2431 /* Process received frames. */ 2432 static int 2433 ale_rxeof(struct ale_softc *sc, int count) 2434 { 2435 struct ale_rx_page *rx_page; 2436 struct rx_rs *rs; 2437 if_t ifp; 2438 struct mbuf *m; 2439 uint32_t length, prod, seqno, status, vtags; 2440 int prog; 2441 2442 ifp = sc->ale_ifp; 2443 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2444 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2445 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2446 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2447 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2448 /* 2449 * Don't directly access producer index as hardware may 2450 * update it while Rx handler is in progress. It would 2451 * be even better if there is a way to let hardware 2452 * know how far driver processed its received frames. 2453 * Alternatively, hardware could provide a way to disable 2454 * CMB updates until driver acknowledges the end of CMB 2455 * access. 2456 */ 2457 prod = *rx_page->cmb_addr; 2458 for (prog = 0; prog < count; prog++) { 2459 if (rx_page->cons >= prod) 2460 break; 2461 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); 2462 seqno = ALE_RX_SEQNO(le32toh(rs->seqno)); 2463 if (sc->ale_cdata.ale_rx_seqno != seqno) { 2464 /* 2465 * Normally I believe this should not happen unless 2466 * severe driver bug or corrupted memory. However 2467 * it seems to happen under certain conditions which 2468 * is triggered by abrupt Rx events such as initiation 2469 * of bulk transfer of remote host. It's not easy to 2470 * reproduce this and I doubt it could be related 2471 * with FIFO overflow of hardware or activity of Tx 2472 * CMB updates. I also remember similar behaviour 2473 * seen on RealTek 8139 which uses resembling Rx 2474 * scheme. 2475 */ 2476 if (bootverbose) 2477 device_printf(sc->ale_dev, 2478 "garbled seq: %u, expected: %u -- " 2479 "resetting!\n", seqno, 2480 sc->ale_cdata.ale_rx_seqno); 2481 return (EIO); 2482 } 2483 /* Frame received. */ 2484 sc->ale_cdata.ale_rx_seqno++; 2485 length = ALE_RX_BYTES(le32toh(rs->length)); 2486 status = le32toh(rs->flags); 2487 if ((status & ALE_RD_ERROR) != 0) { 2488 /* 2489 * We want to pass the following frames to upper 2490 * layer regardless of error status of Rx return 2491 * status. 2492 * 2493 * o IP/TCP/UDP checksum is bad. 2494 * o frame length and protocol specific length 2495 * does not match. 2496 */ 2497 if ((status & (ALE_RD_CRC | ALE_RD_CODE | 2498 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | 2499 ALE_RD_TRUNC)) != 0) { 2500 ale_rx_update_page(sc, &rx_page, length, &prod); 2501 continue; 2502 } 2503 } 2504 /* 2505 * m_devget(9) is major bottle-neck of ale(4)(It comes 2506 * from hardware limitation). For jumbo frames we could 2507 * get a slightly better performance if driver use 2508 * m_getjcl(9) with proper buffer size argument. However 2509 * that would make code more complicated and I don't 2510 * think users would expect good Rx performance numbers 2511 * on these low-end consumer ethernet controller. 2512 */ 2513 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, 2514 ETHER_ALIGN, ifp, NULL); 2515 if (m == NULL) { 2516 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2517 ale_rx_update_page(sc, &rx_page, length, &prod); 2518 continue; 2519 } 2520 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0 && 2521 (status & ALE_RD_IPV4) != 0) 2522 ale_rxcsum(sc, m, status); 2523 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 && 2524 (status & ALE_RD_VLAN) != 0) { 2525 vtags = ALE_RX_VLAN(le32toh(rs->vtags)); 2526 m->m_pkthdr.ether_vtag = ALE_RX_VLAN_TAG(vtags); 2527 m->m_flags |= M_VLANTAG; 2528 } 2529 2530 /* Pass it to upper layer. */ 2531 ALE_UNLOCK(sc); 2532 if_input(ifp, m); 2533 ALE_LOCK(sc); 2534 2535 ale_rx_update_page(sc, &rx_page, length, &prod); 2536 } 2537 2538 return (count > 0 ? 0 : EAGAIN); 2539 } 2540 2541 static void 2542 ale_tick(void *arg) 2543 { 2544 struct ale_softc *sc; 2545 struct mii_data *mii; 2546 2547 sc = (struct ale_softc *)arg; 2548 2549 ALE_LOCK_ASSERT(sc); 2550 2551 mii = device_get_softc(sc->ale_miibus); 2552 mii_tick(mii); 2553 ale_stats_update(sc); 2554 /* 2555 * Reclaim Tx buffers that have been transferred. It's not 2556 * needed here but it would release allocated mbuf chains 2557 * faster and limit the maximum delay to a hz. 2558 */ 2559 ale_txeof(sc); 2560 ale_watchdog(sc); 2561 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2562 } 2563 2564 static void 2565 ale_reset(struct ale_softc *sc) 2566 { 2567 uint32_t reg; 2568 int i; 2569 2570 /* Initialize PCIe module. From Linux. */ 2571 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2572 2573 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); 2574 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2575 DELAY(10); 2576 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) 2577 break; 2578 } 2579 if (i == 0) 2580 device_printf(sc->ale_dev, "master reset timeout!\n"); 2581 2582 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2583 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) 2584 break; 2585 DELAY(10); 2586 } 2587 2588 if (i == 0) 2589 device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg); 2590 } 2591 2592 static void 2593 ale_init(void *xsc) 2594 { 2595 struct ale_softc *sc; 2596 2597 sc = (struct ale_softc *)xsc; 2598 ALE_LOCK(sc); 2599 ale_init_locked(sc); 2600 ALE_UNLOCK(sc); 2601 } 2602 2603 static void 2604 ale_init_locked(struct ale_softc *sc) 2605 { 2606 if_t ifp; 2607 struct mii_data *mii; 2608 uint8_t eaddr[ETHER_ADDR_LEN]; 2609 bus_addr_t paddr; 2610 uint32_t reg, rxf_hi, rxf_lo; 2611 2612 ALE_LOCK_ASSERT(sc); 2613 2614 ifp = sc->ale_ifp; 2615 mii = device_get_softc(sc->ale_miibus); 2616 2617 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2618 return; 2619 /* 2620 * Cancel any pending I/O. 2621 */ 2622 ale_stop(sc); 2623 /* 2624 * Reset the chip to a known state. 2625 */ 2626 ale_reset(sc); 2627 /* Initialize Tx descriptors, DMA memory blocks. */ 2628 ale_init_rx_pages(sc); 2629 ale_init_tx_ring(sc); 2630 2631 /* Reprogram the station address. */ 2632 bcopy(if_getlladdr(ifp), eaddr, ETHER_ADDR_LEN); 2633 CSR_WRITE_4(sc, ALE_PAR0, 2634 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2635 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); 2636 /* 2637 * Clear WOL status and disable all WOL feature as WOL 2638 * would interfere Rx operation under normal environments. 2639 */ 2640 CSR_READ_4(sc, ALE_WOL_CFG); 2641 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 2642 /* 2643 * Set Tx descriptor/RXF0/CMB base addresses. They share 2644 * the same high address part of DMAable region. 2645 */ 2646 paddr = sc->ale_cdata.ale_tx_ring_paddr; 2647 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); 2648 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); 2649 CSR_WRITE_4(sc, ALE_TPD_CNT, 2650 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); 2651 /* Set Rx page base address, note we use single queue. */ 2652 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; 2653 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); 2654 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; 2655 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); 2656 /* Set Tx/Rx CMB addresses. */ 2657 paddr = sc->ale_cdata.ale_tx_cmb_paddr; 2658 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); 2659 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; 2660 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); 2661 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; 2662 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); 2663 /* Mark RXF0 is valid. */ 2664 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); 2665 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); 2666 /* 2667 * No need to initialize RFX1/RXF2/RXF3. We don't use 2668 * multi-queue yet. 2669 */ 2670 2671 /* Set Rx page size, excluding guard frame size. */ 2672 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); 2673 /* Tell hardware that we're ready to load DMA blocks. */ 2674 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); 2675 2676 /* Set Rx/Tx interrupt trigger threshold. */ 2677 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | 2678 (4 << INT_TRIG_TX_THRESH_SHIFT)); 2679 /* 2680 * XXX 2681 * Set interrupt trigger timer, its purpose and relation 2682 * with interrupt moderation mechanism is not clear yet. 2683 */ 2684 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, 2685 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | 2686 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); 2687 2688 /* Configure interrupt moderation timer. */ 2689 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; 2690 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; 2691 CSR_WRITE_4(sc, ALE_IM_TIMER, reg); 2692 reg = CSR_READ_4(sc, ALE_MASTER_CFG); 2693 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 2694 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 2695 if (ALE_USECS(sc->ale_int_rx_mod) != 0) 2696 reg |= MASTER_IM_RX_TIMER_ENB; 2697 if (ALE_USECS(sc->ale_int_tx_mod) != 0) 2698 reg |= MASTER_IM_TX_TIMER_ENB; 2699 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); 2700 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); 2701 2702 /* Set Maximum frame size of controller. */ 2703 if (if_getmtu(ifp) < ETHERMTU) 2704 sc->ale_max_frame_size = ETHERMTU; 2705 else 2706 sc->ale_max_frame_size = if_getmtu(ifp); 2707 sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 2708 ETHER_CRC_LEN; 2709 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); 2710 /* Configure IPG/IFG parameters. */ 2711 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, 2712 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 2713 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2714 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2715 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 2716 /* Set parameters for half-duplex media. */ 2717 CSR_WRITE_4(sc, ALE_HDPX_CFG, 2718 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2719 HDPX_CFG_LCOL_MASK) | 2720 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2721 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2722 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2723 HDPX_CFG_ABEBT_MASK) | 2724 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2725 HDPX_CFG_JAMIPG_MASK)); 2726 2727 /* Configure Tx jumbo frame parameters. */ 2728 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2729 if (if_getmtu(ifp) < ETHERMTU) 2730 reg = sc->ale_max_frame_size; 2731 else if (if_getmtu(ifp) < 6 * 1024) 2732 reg = (sc->ale_max_frame_size * 2) / 3; 2733 else 2734 reg = sc->ale_max_frame_size / 2; 2735 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, 2736 roundup(reg, TX_JUMBO_THRESH_UNIT) >> 2737 TX_JUMBO_THRESH_UNIT_SHIFT); 2738 } 2739 /* Configure TxQ. */ 2740 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) 2741 << TXQ_CFG_TX_FIFO_BURST_SHIFT; 2742 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2743 TXQ_CFG_TPD_BURST_MASK; 2744 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); 2745 2746 /* Configure Rx jumbo frame & flow control parameters. */ 2747 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2748 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); 2749 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, 2750 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << 2751 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | 2752 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & 2753 RX_JUMBO_LKAH_MASK)); 2754 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 2755 rxf_hi = (reg * 7) / 10; 2756 rxf_lo = (reg * 3)/ 10; 2757 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, 2758 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2759 RX_FIFO_PAUSE_THRESH_LO_MASK) | 2760 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2761 RX_FIFO_PAUSE_THRESH_HI_MASK)); 2762 } 2763 2764 /* Disable RSS. */ 2765 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); 2766 CSR_WRITE_4(sc, ALE_RSS_CPU, 0); 2767 2768 /* Configure RxQ. */ 2769 CSR_WRITE_4(sc, ALE_RXQ_CFG, 2770 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2771 2772 /* Configure DMA parameters. */ 2773 reg = 0; 2774 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) 2775 reg |= DMA_CFG_TXCMB_ENB; 2776 CSR_WRITE_4(sc, ALE_DMA_CFG, 2777 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | 2778 sc->ale_dma_rd_burst | reg | 2779 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | 2780 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 2781 DMA_CFG_RD_DELAY_CNT_MASK) | 2782 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 2783 DMA_CFG_WR_DELAY_CNT_MASK)); 2784 2785 /* 2786 * Hardware can be configured to issue SMB interrupt based 2787 * on programmed interval. Since there is a callout that is 2788 * invoked for every hz in driver we use that instead of 2789 * relying on periodic SMB interrupt. 2790 */ 2791 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); 2792 /* Clear MAC statistics. */ 2793 ale_stats_clear(sc); 2794 2795 /* 2796 * Configure Tx/Rx MACs. 2797 * - Auto-padding for short frames. 2798 * - Enable CRC generation. 2799 * Actual reconfiguration of MAC for resolved speed/duplex 2800 * is followed after detection of link establishment. 2801 * AR81xx always does checksum computation regardless of 2802 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will 2803 * cause Rx handling issue for fragmented IP datagrams due 2804 * to silicon bug. 2805 */ 2806 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 2807 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2808 MAC_CFG_PREAMBLE_MASK); 2809 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) 2810 reg |= MAC_CFG_SPEED_10_100; 2811 else 2812 reg |= MAC_CFG_SPEED_1000; 2813 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2814 2815 /* Set up the receive filter. */ 2816 ale_rxfilter(sc); 2817 ale_rxvlan(sc); 2818 2819 /* Acknowledge all pending interrupts and clear it. */ 2820 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); 2821 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2822 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); 2823 2824 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 2825 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2826 2827 sc->ale_flags &= ~ALE_FLAG_LINK; 2828 /* Switch to the current media. */ 2829 mii_mediachg(mii); 2830 2831 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2832 } 2833 2834 static void 2835 ale_stop(struct ale_softc *sc) 2836 { 2837 if_t ifp; 2838 struct ale_txdesc *txd; 2839 uint32_t reg; 2840 int i; 2841 2842 ALE_LOCK_ASSERT(sc); 2843 /* 2844 * Mark the interface down and cancel the watchdog timer. 2845 */ 2846 ifp = sc->ale_ifp; 2847 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 2848 sc->ale_flags &= ~ALE_FLAG_LINK; 2849 callout_stop(&sc->ale_tick_ch); 2850 sc->ale_watchdog_timer = 0; 2851 ale_stats_update(sc); 2852 /* Disable interrupts. */ 2853 CSR_WRITE_4(sc, ALE_INTR_MASK, 0); 2854 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2855 /* Disable queue processing and DMA. */ 2856 reg = CSR_READ_4(sc, ALE_TXQ_CFG); 2857 reg &= ~TXQ_CFG_ENB; 2858 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); 2859 reg = CSR_READ_4(sc, ALE_RXQ_CFG); 2860 reg &= ~RXQ_CFG_ENB; 2861 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); 2862 reg = CSR_READ_4(sc, ALE_DMA_CFG); 2863 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); 2864 CSR_WRITE_4(sc, ALE_DMA_CFG, reg); 2865 DELAY(1000); 2866 /* Stop Rx/Tx MACs. */ 2867 ale_stop_mac(sc); 2868 /* Disable interrupts which might be touched in taskq handler. */ 2869 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2870 2871 /* 2872 * Free TX mbufs still in the queues. 2873 */ 2874 for (i = 0; i < ALE_TX_RING_CNT; i++) { 2875 txd = &sc->ale_cdata.ale_txdesc[i]; 2876 if (txd->tx_m != NULL) { 2877 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2878 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2879 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2880 txd->tx_dmamap); 2881 m_freem(txd->tx_m); 2882 txd->tx_m = NULL; 2883 } 2884 } 2885 } 2886 2887 static void 2888 ale_stop_mac(struct ale_softc *sc) 2889 { 2890 uint32_t reg; 2891 int i; 2892 2893 ALE_LOCK_ASSERT(sc); 2894 2895 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2896 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 2897 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 2898 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2899 } 2900 2901 for (i = ALE_TIMEOUT; i > 0; i--) { 2902 reg = CSR_READ_4(sc, ALE_IDLE_STATUS); 2903 if (reg == 0) 2904 break; 2905 DELAY(10); 2906 } 2907 if (i == 0) 2908 device_printf(sc->ale_dev, 2909 "could not disable Tx/Rx MAC(0x%08x)!\n", reg); 2910 } 2911 2912 static void 2913 ale_init_tx_ring(struct ale_softc *sc) 2914 { 2915 struct ale_txdesc *txd; 2916 int i; 2917 2918 ALE_LOCK_ASSERT(sc); 2919 2920 sc->ale_cdata.ale_tx_prod = 0; 2921 sc->ale_cdata.ale_tx_cons = 0; 2922 sc->ale_cdata.ale_tx_cnt = 0; 2923 2924 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ); 2925 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ); 2926 for (i = 0; i < ALE_TX_RING_CNT; i++) { 2927 txd = &sc->ale_cdata.ale_txdesc[i]; 2928 txd->tx_m = NULL; 2929 } 2930 *sc->ale_cdata.ale_tx_cmb = 0; 2931 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2932 sc->ale_cdata.ale_tx_cmb_map, 2933 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2934 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2935 sc->ale_cdata.ale_tx_ring_map, 2936 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2937 } 2938 2939 static void 2940 ale_init_rx_pages(struct ale_softc *sc) 2941 { 2942 struct ale_rx_page *rx_page; 2943 int i; 2944 2945 ALE_LOCK_ASSERT(sc); 2946 2947 sc->ale_morework = 0; 2948 sc->ale_cdata.ale_rx_seqno = 0; 2949 sc->ale_cdata.ale_rx_curp = 0; 2950 2951 for (i = 0; i < ALE_RX_PAGES; i++) { 2952 rx_page = &sc->ale_cdata.ale_rx_page[i]; 2953 bzero(rx_page->page_addr, sc->ale_pagesize); 2954 bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ); 2955 rx_page->cons = 0; 2956 *rx_page->cmb_addr = 0; 2957 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2958 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2959 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2960 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2961 } 2962 } 2963 2964 static void 2965 ale_rxvlan(struct ale_softc *sc) 2966 { 2967 if_t ifp; 2968 uint32_t reg; 2969 2970 ALE_LOCK_ASSERT(sc); 2971 2972 ifp = sc->ale_ifp; 2973 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2974 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2975 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 2976 reg |= MAC_CFG_VLAN_TAG_STRIP; 2977 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2978 } 2979 2980 static u_int 2981 ale_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 2982 { 2983 uint32_t crc, *mchash = arg; 2984 2985 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 2986 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2987 2988 return (1); 2989 } 2990 2991 static void 2992 ale_rxfilter(struct ale_softc *sc) 2993 { 2994 if_t ifp; 2995 uint32_t mchash[2]; 2996 uint32_t rxcfg; 2997 2998 ALE_LOCK_ASSERT(sc); 2999 3000 ifp = sc->ale_ifp; 3001 3002 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); 3003 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3004 if ((if_getflags(ifp) & IFF_BROADCAST) != 0) 3005 rxcfg |= MAC_CFG_BCAST; 3006 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3007 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 3008 rxcfg |= MAC_CFG_PROMISC; 3009 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) 3010 rxcfg |= MAC_CFG_ALLMULTI; 3011 CSR_WRITE_4(sc, ALE_MAR0, 0xFFFFFFFF); 3012 CSR_WRITE_4(sc, ALE_MAR1, 0xFFFFFFFF); 3013 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3014 return; 3015 } 3016 3017 /* Program new filter. */ 3018 bzero(mchash, sizeof(mchash)); 3019 if_foreach_llmaddr(ifp, ale_hash_maddr, &mchash); 3020 3021 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); 3022 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); 3023 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3024 } 3025 3026 static int 3027 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3028 { 3029 int error, value; 3030 3031 if (arg1 == NULL) 3032 return (EINVAL); 3033 value = *(int *)arg1; 3034 error = sysctl_handle_int(oidp, &value, 0, req); 3035 if (error || req->newptr == NULL) 3036 return (error); 3037 if (value < low || value > high) 3038 return (EINVAL); 3039 *(int *)arg1 = value; 3040 3041 return (0); 3042 } 3043 3044 static int 3045 sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS) 3046 { 3047 return (sysctl_int_range(oidp, arg1, arg2, req, 3048 ALE_PROC_MIN, ALE_PROC_MAX)); 3049 } 3050 3051 static int 3052 sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS) 3053 { 3054 3055 return (sysctl_int_range(oidp, arg1, arg2, req, 3056 ALE_IM_TIMER_MIN, ALE_IM_TIMER_MAX)); 3057 } 3058