1 /*- 2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/kernel.h> 38 #include <sys/malloc.h> 39 #include <sys/mbuf.h> 40 #include <sys/module.h> 41 #include <sys/rman.h> 42 #include <sys/queue.h> 43 #include <sys/socket.h> 44 #include <sys/sockio.h> 45 #include <sys/sysctl.h> 46 #include <sys/taskqueue.h> 47 48 #include <net/bpf.h> 49 #include <net/if.h> 50 #include <net/if_var.h> 51 #include <net/if_arp.h> 52 #include <net/ethernet.h> 53 #include <net/if_dl.h> 54 #include <net/if_llc.h> 55 #include <net/if_media.h> 56 #include <net/if_types.h> 57 #include <net/if_vlan_var.h> 58 59 #include <netinet/in.h> 60 #include <netinet/in_systm.h> 61 #include <netinet/ip.h> 62 #include <netinet/tcp.h> 63 64 #include <dev/mii/mii.h> 65 #include <dev/mii/miivar.h> 66 67 #include <dev/pci/pcireg.h> 68 #include <dev/pci/pcivar.h> 69 70 #include <machine/bus.h> 71 #include <machine/in_cksum.h> 72 73 #include <dev/ale/if_alereg.h> 74 #include <dev/ale/if_alevar.h> 75 76 /* "device miibus" required. See GENERIC if you get errors here. */ 77 #include "miibus_if.h" 78 79 /* For more information about Tx checksum offload issues see ale_encap(). */ 80 #define ALE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 81 82 MODULE_DEPEND(ale, pci, 1, 1, 1); 83 MODULE_DEPEND(ale, ether, 1, 1, 1); 84 MODULE_DEPEND(ale, miibus, 1, 1, 1); 85 86 /* Tunables. */ 87 static int msi_disable = 0; 88 static int msix_disable = 0; 89 TUNABLE_INT("hw.ale.msi_disable", &msi_disable); 90 TUNABLE_INT("hw.ale.msix_disable", &msix_disable); 91 92 /* 93 * Devices supported by this driver. 94 */ 95 static const struct ale_dev { 96 uint16_t ale_vendorid; 97 uint16_t ale_deviceid; 98 const char *ale_name; 99 } ale_devs[] = { 100 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR81XX, 101 "Atheros AR8121/AR8113/AR8114 PCIe Ethernet" }, 102 }; 103 104 static int ale_attach(device_t); 105 static int ale_check_boundary(struct ale_softc *); 106 static int ale_detach(device_t); 107 static int ale_dma_alloc(struct ale_softc *); 108 static void ale_dma_free(struct ale_softc *); 109 static void ale_dmamap_cb(void *, bus_dma_segment_t *, int, int); 110 static int ale_encap(struct ale_softc *, struct mbuf **); 111 static void ale_get_macaddr(struct ale_softc *); 112 static void ale_init(void *); 113 static void ale_init_locked(struct ale_softc *); 114 static void ale_init_rx_pages(struct ale_softc *); 115 static void ale_init_tx_ring(struct ale_softc *); 116 static void ale_int_task(void *, int); 117 static int ale_intr(void *); 118 static int ale_ioctl(struct ifnet *, u_long, caddr_t); 119 static void ale_mac_config(struct ale_softc *); 120 static int ale_miibus_readreg(device_t, int, int); 121 static void ale_miibus_statchg(device_t); 122 static int ale_miibus_writereg(device_t, int, int, int); 123 static int ale_mediachange(struct ifnet *); 124 static void ale_mediastatus(struct ifnet *, struct ifmediareq *); 125 static void ale_phy_reset(struct ale_softc *); 126 static int ale_probe(device_t); 127 static void ale_reset(struct ale_softc *); 128 static int ale_resume(device_t); 129 static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, 130 uint32_t, uint32_t *); 131 static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); 132 static int ale_rxeof(struct ale_softc *sc, int); 133 static void ale_rxfilter(struct ale_softc *); 134 static void ale_rxvlan(struct ale_softc *); 135 static void ale_setlinkspeed(struct ale_softc *); 136 static void ale_setwol(struct ale_softc *); 137 static int ale_shutdown(device_t); 138 static void ale_start(struct ifnet *); 139 static void ale_start_locked(struct ifnet *); 140 static void ale_stats_clear(struct ale_softc *); 141 static void ale_stats_update(struct ale_softc *); 142 static void ale_stop(struct ale_softc *); 143 static void ale_stop_mac(struct ale_softc *); 144 static int ale_suspend(device_t); 145 static void ale_sysctl_node(struct ale_softc *); 146 static void ale_tick(void *); 147 static void ale_txeof(struct ale_softc *); 148 static void ale_watchdog(struct ale_softc *); 149 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 150 static int sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS); 151 static int sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS); 152 153 static device_method_t ale_methods[] = { 154 /* Device interface. */ 155 DEVMETHOD(device_probe, ale_probe), 156 DEVMETHOD(device_attach, ale_attach), 157 DEVMETHOD(device_detach, ale_detach), 158 DEVMETHOD(device_shutdown, ale_shutdown), 159 DEVMETHOD(device_suspend, ale_suspend), 160 DEVMETHOD(device_resume, ale_resume), 161 162 /* MII interface. */ 163 DEVMETHOD(miibus_readreg, ale_miibus_readreg), 164 DEVMETHOD(miibus_writereg, ale_miibus_writereg), 165 DEVMETHOD(miibus_statchg, ale_miibus_statchg), 166 167 DEVMETHOD_END 168 }; 169 170 static driver_t ale_driver = { 171 "ale", 172 ale_methods, 173 sizeof(struct ale_softc) 174 }; 175 176 static devclass_t ale_devclass; 177 178 DRIVER_MODULE(ale, pci, ale_driver, ale_devclass, NULL, NULL); 179 DRIVER_MODULE(miibus, ale, miibus_driver, miibus_devclass, NULL, NULL); 180 181 static struct resource_spec ale_res_spec_mem[] = { 182 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 183 { -1, 0, 0 } 184 }; 185 186 static struct resource_spec ale_irq_spec_legacy[] = { 187 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 188 { -1, 0, 0 } 189 }; 190 191 static struct resource_spec ale_irq_spec_msi[] = { 192 { SYS_RES_IRQ, 1, RF_ACTIVE }, 193 { -1, 0, 0 } 194 }; 195 196 static struct resource_spec ale_irq_spec_msix[] = { 197 { SYS_RES_IRQ, 1, RF_ACTIVE }, 198 { -1, 0, 0 } 199 }; 200 201 static int 202 ale_miibus_readreg(device_t dev, int phy, int reg) 203 { 204 struct ale_softc *sc; 205 uint32_t v; 206 int i; 207 208 sc = device_get_softc(dev); 209 210 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 211 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 212 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 213 DELAY(5); 214 v = CSR_READ_4(sc, ALE_MDIO); 215 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 216 break; 217 } 218 219 if (i == 0) { 220 device_printf(sc->ale_dev, "phy read timeout : %d\n", reg); 221 return (0); 222 } 223 224 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 225 } 226 227 static int 228 ale_miibus_writereg(device_t dev, int phy, int reg, int val) 229 { 230 struct ale_softc *sc; 231 uint32_t v; 232 int i; 233 234 sc = device_get_softc(dev); 235 236 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 237 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 238 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 239 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 240 DELAY(5); 241 v = CSR_READ_4(sc, ALE_MDIO); 242 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 243 break; 244 } 245 246 if (i == 0) 247 device_printf(sc->ale_dev, "phy write timeout : %d\n", reg); 248 249 return (0); 250 } 251 252 static void 253 ale_miibus_statchg(device_t dev) 254 { 255 struct ale_softc *sc; 256 struct mii_data *mii; 257 struct ifnet *ifp; 258 uint32_t reg; 259 260 sc = device_get_softc(dev); 261 mii = device_get_softc(sc->ale_miibus); 262 ifp = sc->ale_ifp; 263 if (mii == NULL || ifp == NULL || 264 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 265 return; 266 267 sc->ale_flags &= ~ALE_FLAG_LINK; 268 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 269 (IFM_ACTIVE | IFM_AVALID)) { 270 switch (IFM_SUBTYPE(mii->mii_media_active)) { 271 case IFM_10_T: 272 case IFM_100_TX: 273 sc->ale_flags |= ALE_FLAG_LINK; 274 break; 275 case IFM_1000_T: 276 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 277 sc->ale_flags |= ALE_FLAG_LINK; 278 break; 279 default: 280 break; 281 } 282 } 283 284 /* Stop Rx/Tx MACs. */ 285 ale_stop_mac(sc); 286 287 /* Program MACs with resolved speed/duplex/flow-control. */ 288 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { 289 ale_mac_config(sc); 290 /* Reenable Tx/Rx MACs. */ 291 reg = CSR_READ_4(sc, ALE_MAC_CFG); 292 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 293 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 294 } 295 } 296 297 static void 298 ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 299 { 300 struct ale_softc *sc; 301 struct mii_data *mii; 302 303 sc = ifp->if_softc; 304 ALE_LOCK(sc); 305 if ((ifp->if_flags & IFF_UP) == 0) { 306 ALE_UNLOCK(sc); 307 return; 308 } 309 mii = device_get_softc(sc->ale_miibus); 310 311 mii_pollstat(mii); 312 ifmr->ifm_status = mii->mii_media_status; 313 ifmr->ifm_active = mii->mii_media_active; 314 ALE_UNLOCK(sc); 315 } 316 317 static int 318 ale_mediachange(struct ifnet *ifp) 319 { 320 struct ale_softc *sc; 321 struct mii_data *mii; 322 struct mii_softc *miisc; 323 int error; 324 325 sc = ifp->if_softc; 326 ALE_LOCK(sc); 327 mii = device_get_softc(sc->ale_miibus); 328 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 329 PHY_RESET(miisc); 330 error = mii_mediachg(mii); 331 ALE_UNLOCK(sc); 332 333 return (error); 334 } 335 336 static int 337 ale_probe(device_t dev) 338 { 339 const struct ale_dev *sp; 340 int i; 341 uint16_t vendor, devid; 342 343 vendor = pci_get_vendor(dev); 344 devid = pci_get_device(dev); 345 sp = ale_devs; 346 for (i = 0; i < sizeof(ale_devs) / sizeof(ale_devs[0]); i++) { 347 if (vendor == sp->ale_vendorid && 348 devid == sp->ale_deviceid) { 349 device_set_desc(dev, sp->ale_name); 350 return (BUS_PROBE_DEFAULT); 351 } 352 sp++; 353 } 354 355 return (ENXIO); 356 } 357 358 static void 359 ale_get_macaddr(struct ale_softc *sc) 360 { 361 uint32_t ea[2], reg; 362 int i, vpdc; 363 364 reg = CSR_READ_4(sc, ALE_SPI_CTRL); 365 if ((reg & SPI_VPD_ENB) != 0) { 366 reg &= ~SPI_VPD_ENB; 367 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); 368 } 369 370 if (pci_find_cap(sc->ale_dev, PCIY_VPD, &vpdc) == 0) { 371 /* 372 * PCI VPD capability found, let TWSI reload EEPROM. 373 * This will set ethernet address of controller. 374 */ 375 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | 376 TWSI_CTRL_SW_LD_START); 377 for (i = 100; i > 0; i--) { 378 DELAY(1000); 379 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); 380 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 381 break; 382 } 383 if (i == 0) 384 device_printf(sc->ale_dev, 385 "reloading EEPROM timeout!\n"); 386 } else { 387 if (bootverbose) 388 device_printf(sc->ale_dev, 389 "PCI VPD capability not found!\n"); 390 } 391 392 ea[0] = CSR_READ_4(sc, ALE_PAR0); 393 ea[1] = CSR_READ_4(sc, ALE_PAR1); 394 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; 395 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; 396 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; 397 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; 398 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; 399 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; 400 } 401 402 static void 403 ale_phy_reset(struct ale_softc *sc) 404 { 405 406 /* Reset magic from Linux. */ 407 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 408 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 409 GPHY_CTRL_PHY_PLL_ON); 410 DELAY(1000); 411 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 412 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | 413 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); 414 DELAY(1000); 415 416 #define ATPHY_DBG_ADDR 0x1D 417 #define ATPHY_DBG_DATA 0x1E 418 419 /* Enable hibernation mode. */ 420 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 421 ATPHY_DBG_ADDR, 0x0B); 422 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 423 ATPHY_DBG_DATA, 0xBC00); 424 /* Set Class A/B for all modes. */ 425 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 426 ATPHY_DBG_ADDR, 0x00); 427 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 428 ATPHY_DBG_DATA, 0x02EF); 429 /* Enable 10BT power saving. */ 430 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 431 ATPHY_DBG_ADDR, 0x12); 432 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 433 ATPHY_DBG_DATA, 0x4C04); 434 /* Adjust 1000T power. */ 435 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 436 ATPHY_DBG_ADDR, 0x04); 437 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 438 ATPHY_DBG_ADDR, 0x8BBB); 439 /* 10BT center tap voltage. */ 440 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 441 ATPHY_DBG_ADDR, 0x05); 442 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 443 ATPHY_DBG_ADDR, 0x2C46); 444 445 #undef ATPHY_DBG_ADDR 446 #undef ATPHY_DBG_DATA 447 DELAY(1000); 448 } 449 450 static int 451 ale_attach(device_t dev) 452 { 453 struct ale_softc *sc; 454 struct ifnet *ifp; 455 uint16_t burst; 456 int error, i, msic, msixc, pmc; 457 uint32_t rxf_len, txf_len; 458 459 error = 0; 460 sc = device_get_softc(dev); 461 sc->ale_dev = dev; 462 463 mtx_init(&sc->ale_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 464 MTX_DEF); 465 callout_init_mtx(&sc->ale_tick_ch, &sc->ale_mtx, 0); 466 TASK_INIT(&sc->ale_int_task, 0, ale_int_task, sc); 467 468 /* Map the device. */ 469 pci_enable_busmaster(dev); 470 sc->ale_res_spec = ale_res_spec_mem; 471 sc->ale_irq_spec = ale_irq_spec_legacy; 472 error = bus_alloc_resources(dev, sc->ale_res_spec, sc->ale_res); 473 if (error != 0) { 474 device_printf(dev, "cannot allocate memory resources.\n"); 475 goto fail; 476 } 477 478 /* Set PHY address. */ 479 sc->ale_phyaddr = ALE_PHY_ADDR; 480 481 /* Reset PHY. */ 482 ale_phy_reset(sc); 483 484 /* Reset the ethernet controller. */ 485 ale_reset(sc); 486 487 /* Get PCI and chip id/revision. */ 488 sc->ale_rev = pci_get_revid(dev); 489 if (sc->ale_rev >= 0xF0) { 490 /* L2E Rev. B. AR8114 */ 491 sc->ale_flags |= ALE_FLAG_FASTETHER; 492 } else { 493 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { 494 /* L1E AR8121 */ 495 sc->ale_flags |= ALE_FLAG_JUMBO; 496 } else { 497 /* L2E Rev. A. AR8113 */ 498 sc->ale_flags |= ALE_FLAG_FASTETHER; 499 } 500 } 501 /* 502 * All known controllers seems to require 4 bytes alignment 503 * of Tx buffers to make Tx checksum offload with custom 504 * checksum generation method work. 505 */ 506 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; 507 /* 508 * All known controllers seems to have issues on Rx checksum 509 * offload for fragmented IP datagrams. 510 */ 511 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; 512 /* 513 * Don't use Tx CMB. It is known to cause RRS update failure 514 * under certain circumstances. Typical phenomenon of the 515 * issue would be unexpected sequence number encountered in 516 * Rx handler. 517 */ 518 sc->ale_flags |= ALE_FLAG_TXCMB_BUG; 519 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> 520 MASTER_CHIP_REV_SHIFT; 521 if (bootverbose) { 522 device_printf(dev, "PCI device revision : 0x%04x\n", 523 sc->ale_rev); 524 device_printf(dev, "Chip id/revision : 0x%04x\n", 525 sc->ale_chip_rev); 526 } 527 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); 528 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 529 /* 530 * Uninitialized hardware returns an invalid chip id/revision 531 * as well as 0xFFFFFFFF for Tx/Rx fifo length. 532 */ 533 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || 534 rxf_len == 0xFFFFFFF) { 535 device_printf(dev,"chip revision : 0x%04x, %u Tx FIFO " 536 "%u Rx FIFO -- not initialized?\n", sc->ale_chip_rev, 537 txf_len, rxf_len); 538 error = ENXIO; 539 goto fail; 540 } 541 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", txf_len, rxf_len); 542 543 /* Allocate IRQ resources. */ 544 msixc = pci_msix_count(dev); 545 msic = pci_msi_count(dev); 546 if (bootverbose) { 547 device_printf(dev, "MSIX count : %d\n", msixc); 548 device_printf(dev, "MSI count : %d\n", msic); 549 } 550 551 /* Prefer MSIX over MSI. */ 552 if (msix_disable == 0 || msi_disable == 0) { 553 if (msix_disable == 0 && msixc == ALE_MSIX_MESSAGES && 554 pci_alloc_msix(dev, &msixc) == 0) { 555 if (msixc == ALE_MSIX_MESSAGES) { 556 device_printf(dev, "Using %d MSIX messages.\n", 557 msixc); 558 sc->ale_flags |= ALE_FLAG_MSIX; 559 sc->ale_irq_spec = ale_irq_spec_msix; 560 } else 561 pci_release_msi(dev); 562 } 563 if (msi_disable == 0 && (sc->ale_flags & ALE_FLAG_MSIX) == 0 && 564 msic == ALE_MSI_MESSAGES && 565 pci_alloc_msi(dev, &msic) == 0) { 566 if (msic == ALE_MSI_MESSAGES) { 567 device_printf(dev, "Using %d MSI messages.\n", 568 msic); 569 sc->ale_flags |= ALE_FLAG_MSI; 570 sc->ale_irq_spec = ale_irq_spec_msi; 571 } else 572 pci_release_msi(dev); 573 } 574 } 575 576 error = bus_alloc_resources(dev, sc->ale_irq_spec, sc->ale_irq); 577 if (error != 0) { 578 device_printf(dev, "cannot allocate IRQ resources.\n"); 579 goto fail; 580 } 581 582 /* Get DMA parameters from PCIe device control register. */ 583 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 584 sc->ale_flags |= ALE_FLAG_PCIE; 585 burst = pci_read_config(dev, i + 0x08, 2); 586 /* Max read request size. */ 587 sc->ale_dma_rd_burst = ((burst >> 12) & 0x07) << 588 DMA_CFG_RD_BURST_SHIFT; 589 /* Max payload size. */ 590 sc->ale_dma_wr_burst = ((burst >> 5) & 0x07) << 591 DMA_CFG_WR_BURST_SHIFT; 592 if (bootverbose) { 593 device_printf(dev, "Read request size : %d bytes.\n", 594 128 << ((burst >> 12) & 0x07)); 595 device_printf(dev, "TLP payload size : %d bytes.\n", 596 128 << ((burst >> 5) & 0x07)); 597 } 598 } else { 599 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; 600 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; 601 } 602 603 /* Create device sysctl node. */ 604 ale_sysctl_node(sc); 605 606 if ((error = ale_dma_alloc(sc) != 0)) 607 goto fail; 608 609 /* Load station address. */ 610 ale_get_macaddr(sc); 611 612 ifp = sc->ale_ifp = if_alloc(IFT_ETHER); 613 if (ifp == NULL) { 614 device_printf(dev, "cannot allocate ifnet structure.\n"); 615 error = ENXIO; 616 goto fail; 617 } 618 619 ifp->if_softc = sc; 620 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 621 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 622 ifp->if_ioctl = ale_ioctl; 623 ifp->if_start = ale_start; 624 ifp->if_init = ale_init; 625 ifp->if_snd.ifq_drv_maxlen = ALE_TX_RING_CNT - 1; 626 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 627 IFQ_SET_READY(&ifp->if_snd); 628 ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4; 629 ifp->if_hwassist = ALE_CSUM_FEATURES | CSUM_TSO; 630 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { 631 sc->ale_flags |= ALE_FLAG_PMCAP; 632 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 633 } 634 ifp->if_capenable = ifp->if_capabilities; 635 636 /* Set up MII bus. */ 637 error = mii_attach(dev, &sc->ale_miibus, ifp, ale_mediachange, 638 ale_mediastatus, BMSR_DEFCAPMASK, sc->ale_phyaddr, MII_OFFSET_ANY, 639 MIIF_DOPAUSE); 640 if (error != 0) { 641 device_printf(dev, "attaching PHYs failed\n"); 642 goto fail; 643 } 644 645 ether_ifattach(ifp, sc->ale_eaddr); 646 647 /* VLAN capability setup. */ 648 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 649 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO; 650 ifp->if_capenable = ifp->if_capabilities; 651 /* 652 * Even though controllers supported by ale(3) have Rx checksum 653 * offload bug the workaround for fragmented frames seemed to 654 * work so far. However it seems Rx checksum offload does not 655 * work under certain conditions. So disable Rx checksum offload 656 * until I find more clue about it but allow users to override it. 657 */ 658 ifp->if_capenable &= ~IFCAP_RXCSUM; 659 660 /* Tell the upper layer(s) we support long frames. */ 661 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 662 663 /* Create local taskq. */ 664 sc->ale_tq = taskqueue_create_fast("ale_taskq", M_WAITOK, 665 taskqueue_thread_enqueue, &sc->ale_tq); 666 if (sc->ale_tq == NULL) { 667 device_printf(dev, "could not create taskqueue.\n"); 668 ether_ifdetach(ifp); 669 error = ENXIO; 670 goto fail; 671 } 672 taskqueue_start_threads(&sc->ale_tq, 1, PI_NET, "%s taskq", 673 device_get_nameunit(sc->ale_dev)); 674 675 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 676 msic = ALE_MSIX_MESSAGES; 677 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 678 msic = ALE_MSI_MESSAGES; 679 else 680 msic = 1; 681 for (i = 0; i < msic; i++) { 682 error = bus_setup_intr(dev, sc->ale_irq[i], 683 INTR_TYPE_NET | INTR_MPSAFE, ale_intr, NULL, sc, 684 &sc->ale_intrhand[i]); 685 if (error != 0) 686 break; 687 } 688 if (error != 0) { 689 device_printf(dev, "could not set up interrupt handler.\n"); 690 taskqueue_free(sc->ale_tq); 691 sc->ale_tq = NULL; 692 ether_ifdetach(ifp); 693 goto fail; 694 } 695 696 fail: 697 if (error != 0) 698 ale_detach(dev); 699 700 return (error); 701 } 702 703 static int 704 ale_detach(device_t dev) 705 { 706 struct ale_softc *sc; 707 struct ifnet *ifp; 708 int i, msic; 709 710 sc = device_get_softc(dev); 711 712 ifp = sc->ale_ifp; 713 if (device_is_attached(dev)) { 714 ether_ifdetach(ifp); 715 ALE_LOCK(sc); 716 ale_stop(sc); 717 ALE_UNLOCK(sc); 718 callout_drain(&sc->ale_tick_ch); 719 taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 720 } 721 722 if (sc->ale_tq != NULL) { 723 taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 724 taskqueue_free(sc->ale_tq); 725 sc->ale_tq = NULL; 726 } 727 728 if (sc->ale_miibus != NULL) { 729 device_delete_child(dev, sc->ale_miibus); 730 sc->ale_miibus = NULL; 731 } 732 bus_generic_detach(dev); 733 ale_dma_free(sc); 734 735 if (ifp != NULL) { 736 if_free(ifp); 737 sc->ale_ifp = NULL; 738 } 739 740 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 741 msic = ALE_MSIX_MESSAGES; 742 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 743 msic = ALE_MSI_MESSAGES; 744 else 745 msic = 1; 746 for (i = 0; i < msic; i++) { 747 if (sc->ale_intrhand[i] != NULL) { 748 bus_teardown_intr(dev, sc->ale_irq[i], 749 sc->ale_intrhand[i]); 750 sc->ale_intrhand[i] = NULL; 751 } 752 } 753 754 bus_release_resources(dev, sc->ale_irq_spec, sc->ale_irq); 755 if ((sc->ale_flags & (ALE_FLAG_MSI | ALE_FLAG_MSIX)) != 0) 756 pci_release_msi(dev); 757 bus_release_resources(dev, sc->ale_res_spec, sc->ale_res); 758 mtx_destroy(&sc->ale_mtx); 759 760 return (0); 761 } 762 763 #define ALE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 764 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 765 766 #if __FreeBSD_version >= 900030 767 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 768 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 769 #elif __FreeBSD_version > 800000 770 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 771 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 772 #else 773 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 774 SYSCTL_ADD_ULONG(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 775 #endif 776 777 static void 778 ale_sysctl_node(struct ale_softc *sc) 779 { 780 struct sysctl_ctx_list *ctx; 781 struct sysctl_oid_list *child, *parent; 782 struct sysctl_oid *tree; 783 struct ale_hw_stats *stats; 784 int error; 785 786 stats = &sc->ale_stats; 787 ctx = device_get_sysctl_ctx(sc->ale_dev); 788 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ale_dev)); 789 790 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 791 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_rx_mod, 0, 792 sysctl_hw_ale_int_mod, "I", "ale Rx interrupt moderation"); 793 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 794 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_tx_mod, 0, 795 sysctl_hw_ale_int_mod, "I", "ale Tx interrupt moderation"); 796 /* Pull in device tunables. */ 797 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 798 error = resource_int_value(device_get_name(sc->ale_dev), 799 device_get_unit(sc->ale_dev), "int_rx_mod", &sc->ale_int_rx_mod); 800 if (error == 0) { 801 if (sc->ale_int_rx_mod < ALE_IM_TIMER_MIN || 802 sc->ale_int_rx_mod > ALE_IM_TIMER_MAX) { 803 device_printf(sc->ale_dev, "int_rx_mod value out of " 804 "range; using default: %d\n", 805 ALE_IM_RX_TIMER_DEFAULT); 806 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 807 } 808 } 809 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 810 error = resource_int_value(device_get_name(sc->ale_dev), 811 device_get_unit(sc->ale_dev), "int_tx_mod", &sc->ale_int_tx_mod); 812 if (error == 0) { 813 if (sc->ale_int_tx_mod < ALE_IM_TIMER_MIN || 814 sc->ale_int_tx_mod > ALE_IM_TIMER_MAX) { 815 device_printf(sc->ale_dev, "int_tx_mod value out of " 816 "range; using default: %d\n", 817 ALE_IM_TX_TIMER_DEFAULT); 818 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 819 } 820 } 821 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 822 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_process_limit, 0, 823 sysctl_hw_ale_proc_limit, "I", 824 "max number of Rx events to process"); 825 /* Pull in device tunables. */ 826 sc->ale_process_limit = ALE_PROC_DEFAULT; 827 error = resource_int_value(device_get_name(sc->ale_dev), 828 device_get_unit(sc->ale_dev), "process_limit", 829 &sc->ale_process_limit); 830 if (error == 0) { 831 if (sc->ale_process_limit < ALE_PROC_MIN || 832 sc->ale_process_limit > ALE_PROC_MAX) { 833 device_printf(sc->ale_dev, 834 "process_limit value out of range; " 835 "using default: %d\n", ALE_PROC_DEFAULT); 836 sc->ale_process_limit = ALE_PROC_DEFAULT; 837 } 838 } 839 840 /* Misc statistics. */ 841 ALE_SYSCTL_STAT_ADD32(ctx, child, "reset_brk_seq", 842 &stats->reset_brk_seq, 843 "Controller resets due to broken Rx sequnce number"); 844 845 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 846 NULL, "ATE statistics"); 847 parent = SYSCTL_CHILDREN(tree); 848 849 /* Rx statistics. */ 850 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 851 NULL, "Rx MAC statistics"); 852 child = SYSCTL_CHILDREN(tree); 853 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 854 &stats->rx_frames, "Good frames"); 855 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 856 &stats->rx_bcast_frames, "Good broadcast frames"); 857 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 858 &stats->rx_mcast_frames, "Good multicast frames"); 859 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 860 &stats->rx_pause_frames, "Pause control frames"); 861 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 862 &stats->rx_control_frames, "Control frames"); 863 ALE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 864 &stats->rx_crcerrs, "CRC errors"); 865 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 866 &stats->rx_lenerrs, "Frames with length mismatched"); 867 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 868 &stats->rx_bytes, "Good octets"); 869 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 870 &stats->rx_bcast_bytes, "Good broadcast octets"); 871 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 872 &stats->rx_mcast_bytes, "Good multicast octets"); 873 ALE_SYSCTL_STAT_ADD32(ctx, child, "runts", 874 &stats->rx_runts, "Too short frames"); 875 ALE_SYSCTL_STAT_ADD32(ctx, child, "fragments", 876 &stats->rx_fragments, "Fragmented frames"); 877 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 878 &stats->rx_pkts_64, "64 bytes frames"); 879 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 880 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 881 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 882 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 883 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 884 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 885 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 886 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 887 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 888 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 889 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 890 &stats->rx_pkts_1519_max, "1519 to max frames"); 891 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 892 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 893 ALE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 894 &stats->rx_fifo_oflows, "FIFO overflows"); 895 ALE_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 896 &stats->rx_rrs_errs, "Return status write-back errors"); 897 ALE_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 898 &stats->rx_alignerrs, "Alignment errors"); 899 ALE_SYSCTL_STAT_ADD32(ctx, child, "filtered", 900 &stats->rx_pkts_filtered, 901 "Frames dropped due to address filtering"); 902 903 /* Tx statistics. */ 904 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 905 NULL, "Tx MAC statistics"); 906 child = SYSCTL_CHILDREN(tree); 907 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 908 &stats->tx_frames, "Good frames"); 909 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 910 &stats->tx_bcast_frames, "Good broadcast frames"); 911 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 912 &stats->tx_mcast_frames, "Good multicast frames"); 913 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 914 &stats->tx_pause_frames, "Pause control frames"); 915 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 916 &stats->tx_control_frames, "Control frames"); 917 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 918 &stats->tx_excess_defer, "Frames with excessive derferrals"); 919 ALE_SYSCTL_STAT_ADD32(ctx, child, "defers", 920 &stats->tx_excess_defer, "Frames with derferrals"); 921 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 922 &stats->tx_bytes, "Good octets"); 923 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 924 &stats->tx_bcast_bytes, "Good broadcast octets"); 925 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 926 &stats->tx_mcast_bytes, "Good multicast octets"); 927 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 928 &stats->tx_pkts_64, "64 bytes frames"); 929 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 930 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 931 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 932 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 933 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 934 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 935 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 936 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 937 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 938 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 939 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 940 &stats->tx_pkts_1519_max, "1519 to max frames"); 941 ALE_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 942 &stats->tx_single_colls, "Single collisions"); 943 ALE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 944 &stats->tx_multi_colls, "Multiple collisions"); 945 ALE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 946 &stats->tx_late_colls, "Late collisions"); 947 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 948 &stats->tx_excess_colls, "Excessive collisions"); 949 ALE_SYSCTL_STAT_ADD32(ctx, child, "abort", 950 &stats->tx_abort, "Aborted frames due to Excessive collisions"); 951 ALE_SYSCTL_STAT_ADD32(ctx, child, "underruns", 952 &stats->tx_underrun, "FIFO underruns"); 953 ALE_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 954 &stats->tx_desc_underrun, "Descriptor write-back errors"); 955 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 956 &stats->tx_lenerrs, "Frames with length mismatched"); 957 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 958 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 959 } 960 961 #undef ALE_SYSCTL_STAT_ADD32 962 #undef ALE_SYSCTL_STAT_ADD64 963 964 struct ale_dmamap_arg { 965 bus_addr_t ale_busaddr; 966 }; 967 968 static void 969 ale_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 970 { 971 struct ale_dmamap_arg *ctx; 972 973 if (error != 0) 974 return; 975 976 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 977 978 ctx = (struct ale_dmamap_arg *)arg; 979 ctx->ale_busaddr = segs[0].ds_addr; 980 } 981 982 /* 983 * Tx descriptors/RXF0/CMB DMA blocks share ALE_DESC_ADDR_HI register 984 * which specifies high address region of DMA blocks. Therefore these 985 * blocks should have the same high address of given 4GB address 986 * space(i.e. crossing 4GB boundary is not allowed). 987 */ 988 static int 989 ale_check_boundary(struct ale_softc *sc) 990 { 991 bus_addr_t rx_cmb_end[ALE_RX_PAGES], tx_cmb_end; 992 bus_addr_t rx_page_end[ALE_RX_PAGES], tx_ring_end; 993 994 rx_page_end[0] = sc->ale_cdata.ale_rx_page[0].page_paddr + 995 sc->ale_pagesize; 996 rx_page_end[1] = sc->ale_cdata.ale_rx_page[1].page_paddr + 997 sc->ale_pagesize; 998 tx_ring_end = sc->ale_cdata.ale_tx_ring_paddr + ALE_TX_RING_SZ; 999 tx_cmb_end = sc->ale_cdata.ale_tx_cmb_paddr + ALE_TX_CMB_SZ; 1000 rx_cmb_end[0] = sc->ale_cdata.ale_rx_page[0].cmb_paddr + ALE_RX_CMB_SZ; 1001 rx_cmb_end[1] = sc->ale_cdata.ale_rx_page[1].cmb_paddr + ALE_RX_CMB_SZ; 1002 1003 if ((ALE_ADDR_HI(tx_ring_end) != 1004 ALE_ADDR_HI(sc->ale_cdata.ale_tx_ring_paddr)) || 1005 (ALE_ADDR_HI(rx_page_end[0]) != 1006 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].page_paddr)) || 1007 (ALE_ADDR_HI(rx_page_end[1]) != 1008 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].page_paddr)) || 1009 (ALE_ADDR_HI(tx_cmb_end) != 1010 ALE_ADDR_HI(sc->ale_cdata.ale_tx_cmb_paddr)) || 1011 (ALE_ADDR_HI(rx_cmb_end[0]) != 1012 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].cmb_paddr)) || 1013 (ALE_ADDR_HI(rx_cmb_end[1]) != 1014 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].cmb_paddr))) 1015 return (EFBIG); 1016 1017 if ((ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[0])) || 1018 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[1])) || 1019 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[0])) || 1020 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[1])) || 1021 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(tx_cmb_end))) 1022 return (EFBIG); 1023 1024 return (0); 1025 } 1026 1027 static int 1028 ale_dma_alloc(struct ale_softc *sc) 1029 { 1030 struct ale_txdesc *txd; 1031 bus_addr_t lowaddr; 1032 struct ale_dmamap_arg ctx; 1033 int error, guard_size, i; 1034 1035 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 1036 guard_size = ALE_JUMBO_FRAMELEN; 1037 else 1038 guard_size = ALE_MAX_FRAMELEN; 1039 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, 1040 ALE_RX_PAGE_ALIGN); 1041 lowaddr = BUS_SPACE_MAXADDR; 1042 again: 1043 /* Create parent DMA tag. */ 1044 error = bus_dma_tag_create( 1045 bus_get_dma_tag(sc->ale_dev), /* parent */ 1046 1, 0, /* alignment, boundary */ 1047 lowaddr, /* lowaddr */ 1048 BUS_SPACE_MAXADDR, /* highaddr */ 1049 NULL, NULL, /* filter, filterarg */ 1050 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1051 0, /* nsegments */ 1052 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1053 0, /* flags */ 1054 NULL, NULL, /* lockfunc, lockarg */ 1055 &sc->ale_cdata.ale_parent_tag); 1056 if (error != 0) { 1057 device_printf(sc->ale_dev, 1058 "could not create parent DMA tag.\n"); 1059 goto fail; 1060 } 1061 1062 /* Create DMA tag for Tx descriptor ring. */ 1063 error = bus_dma_tag_create( 1064 sc->ale_cdata.ale_parent_tag, /* parent */ 1065 ALE_TX_RING_ALIGN, 0, /* alignment, boundary */ 1066 BUS_SPACE_MAXADDR, /* lowaddr */ 1067 BUS_SPACE_MAXADDR, /* highaddr */ 1068 NULL, NULL, /* filter, filterarg */ 1069 ALE_TX_RING_SZ, /* maxsize */ 1070 1, /* nsegments */ 1071 ALE_TX_RING_SZ, /* maxsegsize */ 1072 0, /* flags */ 1073 NULL, NULL, /* lockfunc, lockarg */ 1074 &sc->ale_cdata.ale_tx_ring_tag); 1075 if (error != 0) { 1076 device_printf(sc->ale_dev, 1077 "could not create Tx ring DMA tag.\n"); 1078 goto fail; 1079 } 1080 1081 /* Create DMA tag for Rx pages. */ 1082 for (i = 0; i < ALE_RX_PAGES; i++) { 1083 error = bus_dma_tag_create( 1084 sc->ale_cdata.ale_parent_tag, /* parent */ 1085 ALE_RX_PAGE_ALIGN, 0, /* alignment, boundary */ 1086 BUS_SPACE_MAXADDR, /* lowaddr */ 1087 BUS_SPACE_MAXADDR, /* highaddr */ 1088 NULL, NULL, /* filter, filterarg */ 1089 sc->ale_pagesize, /* maxsize */ 1090 1, /* nsegments */ 1091 sc->ale_pagesize, /* maxsegsize */ 1092 0, /* flags */ 1093 NULL, NULL, /* lockfunc, lockarg */ 1094 &sc->ale_cdata.ale_rx_page[i].page_tag); 1095 if (error != 0) { 1096 device_printf(sc->ale_dev, 1097 "could not create Rx page %d DMA tag.\n", i); 1098 goto fail; 1099 } 1100 } 1101 1102 /* Create DMA tag for Tx coalescing message block. */ 1103 error = bus_dma_tag_create( 1104 sc->ale_cdata.ale_parent_tag, /* parent */ 1105 ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1106 BUS_SPACE_MAXADDR, /* lowaddr */ 1107 BUS_SPACE_MAXADDR, /* highaddr */ 1108 NULL, NULL, /* filter, filterarg */ 1109 ALE_TX_CMB_SZ, /* maxsize */ 1110 1, /* nsegments */ 1111 ALE_TX_CMB_SZ, /* maxsegsize */ 1112 0, /* flags */ 1113 NULL, NULL, /* lockfunc, lockarg */ 1114 &sc->ale_cdata.ale_tx_cmb_tag); 1115 if (error != 0) { 1116 device_printf(sc->ale_dev, 1117 "could not create Tx CMB DMA tag.\n"); 1118 goto fail; 1119 } 1120 1121 /* Create DMA tag for Rx coalescing message block. */ 1122 for (i = 0; i < ALE_RX_PAGES; i++) { 1123 error = bus_dma_tag_create( 1124 sc->ale_cdata.ale_parent_tag, /* parent */ 1125 ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1126 BUS_SPACE_MAXADDR, /* lowaddr */ 1127 BUS_SPACE_MAXADDR, /* highaddr */ 1128 NULL, NULL, /* filter, filterarg */ 1129 ALE_RX_CMB_SZ, /* maxsize */ 1130 1, /* nsegments */ 1131 ALE_RX_CMB_SZ, /* maxsegsize */ 1132 0, /* flags */ 1133 NULL, NULL, /* lockfunc, lockarg */ 1134 &sc->ale_cdata.ale_rx_page[i].cmb_tag); 1135 if (error != 0) { 1136 device_printf(sc->ale_dev, 1137 "could not create Rx page %d CMB DMA tag.\n", i); 1138 goto fail; 1139 } 1140 } 1141 1142 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1143 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_ring_tag, 1144 (void **)&sc->ale_cdata.ale_tx_ring, 1145 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1146 &sc->ale_cdata.ale_tx_ring_map); 1147 if (error != 0) { 1148 device_printf(sc->ale_dev, 1149 "could not allocate DMA'able memory for Tx ring.\n"); 1150 goto fail; 1151 } 1152 ctx.ale_busaddr = 0; 1153 error = bus_dmamap_load(sc->ale_cdata.ale_tx_ring_tag, 1154 sc->ale_cdata.ale_tx_ring_map, sc->ale_cdata.ale_tx_ring, 1155 ALE_TX_RING_SZ, ale_dmamap_cb, &ctx, 0); 1156 if (error != 0 || ctx.ale_busaddr == 0) { 1157 device_printf(sc->ale_dev, 1158 "could not load DMA'able memory for Tx ring.\n"); 1159 goto fail; 1160 } 1161 sc->ale_cdata.ale_tx_ring_paddr = ctx.ale_busaddr; 1162 1163 /* Rx pages. */ 1164 for (i = 0; i < ALE_RX_PAGES; i++) { 1165 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].page_tag, 1166 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr, 1167 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1168 &sc->ale_cdata.ale_rx_page[i].page_map); 1169 if (error != 0) { 1170 device_printf(sc->ale_dev, 1171 "could not allocate DMA'able memory for " 1172 "Rx page %d.\n", i); 1173 goto fail; 1174 } 1175 ctx.ale_busaddr = 0; 1176 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].page_tag, 1177 sc->ale_cdata.ale_rx_page[i].page_map, 1178 sc->ale_cdata.ale_rx_page[i].page_addr, 1179 sc->ale_pagesize, ale_dmamap_cb, &ctx, 0); 1180 if (error != 0 || ctx.ale_busaddr == 0) { 1181 device_printf(sc->ale_dev, 1182 "could not load DMA'able memory for " 1183 "Rx page %d.\n", i); 1184 goto fail; 1185 } 1186 sc->ale_cdata.ale_rx_page[i].page_paddr = ctx.ale_busaddr; 1187 } 1188 1189 /* Tx CMB. */ 1190 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_cmb_tag, 1191 (void **)&sc->ale_cdata.ale_tx_cmb, 1192 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1193 &sc->ale_cdata.ale_tx_cmb_map); 1194 if (error != 0) { 1195 device_printf(sc->ale_dev, 1196 "could not allocate DMA'able memory for Tx CMB.\n"); 1197 goto fail; 1198 } 1199 ctx.ale_busaddr = 0; 1200 error = bus_dmamap_load(sc->ale_cdata.ale_tx_cmb_tag, 1201 sc->ale_cdata.ale_tx_cmb_map, sc->ale_cdata.ale_tx_cmb, 1202 ALE_TX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1203 if (error != 0 || ctx.ale_busaddr == 0) { 1204 device_printf(sc->ale_dev, 1205 "could not load DMA'able memory for Tx CMB.\n"); 1206 goto fail; 1207 } 1208 sc->ale_cdata.ale_tx_cmb_paddr = ctx.ale_busaddr; 1209 1210 /* Rx CMB. */ 1211 for (i = 0; i < ALE_RX_PAGES; i++) { 1212 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1213 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 1214 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1215 &sc->ale_cdata.ale_rx_page[i].cmb_map); 1216 if (error != 0) { 1217 device_printf(sc->ale_dev, "could not allocate " 1218 "DMA'able memory for Rx page %d CMB.\n", i); 1219 goto fail; 1220 } 1221 ctx.ale_busaddr = 0; 1222 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1223 sc->ale_cdata.ale_rx_page[i].cmb_map, 1224 sc->ale_cdata.ale_rx_page[i].cmb_addr, 1225 ALE_RX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1226 if (error != 0 || ctx.ale_busaddr == 0) { 1227 device_printf(sc->ale_dev, "could not load DMA'able " 1228 "memory for Rx page %d CMB.\n", i); 1229 goto fail; 1230 } 1231 sc->ale_cdata.ale_rx_page[i].cmb_paddr = ctx.ale_busaddr; 1232 } 1233 1234 /* 1235 * Tx descriptors/RXF0/CMB DMA blocks share the same 1236 * high address region of 64bit DMA address space. 1237 */ 1238 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1239 (error = ale_check_boundary(sc)) != 0) { 1240 device_printf(sc->ale_dev, "4GB boundary crossed, " 1241 "switching to 32bit DMA addressing mode.\n"); 1242 ale_dma_free(sc); 1243 /* 1244 * Limit max allowable DMA address space to 32bit 1245 * and try again. 1246 */ 1247 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1248 goto again; 1249 } 1250 1251 /* 1252 * Create Tx buffer parent tag. 1253 * AR81xx allows 64bit DMA addressing of Tx buffers so it 1254 * needs separate parent DMA tag as parent DMA address space 1255 * could be restricted to be within 32bit address space by 1256 * 4GB boundary crossing. 1257 */ 1258 error = bus_dma_tag_create( 1259 bus_get_dma_tag(sc->ale_dev), /* parent */ 1260 1, 0, /* alignment, boundary */ 1261 BUS_SPACE_MAXADDR, /* lowaddr */ 1262 BUS_SPACE_MAXADDR, /* highaddr */ 1263 NULL, NULL, /* filter, filterarg */ 1264 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1265 0, /* nsegments */ 1266 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1267 0, /* flags */ 1268 NULL, NULL, /* lockfunc, lockarg */ 1269 &sc->ale_cdata.ale_buffer_tag); 1270 if (error != 0) { 1271 device_printf(sc->ale_dev, 1272 "could not create parent buffer DMA tag.\n"); 1273 goto fail; 1274 } 1275 1276 /* Create DMA tag for Tx buffers. */ 1277 error = bus_dma_tag_create( 1278 sc->ale_cdata.ale_buffer_tag, /* parent */ 1279 1, 0, /* alignment, boundary */ 1280 BUS_SPACE_MAXADDR, /* lowaddr */ 1281 BUS_SPACE_MAXADDR, /* highaddr */ 1282 NULL, NULL, /* filter, filterarg */ 1283 ALE_TSO_MAXSIZE, /* maxsize */ 1284 ALE_MAXTXSEGS, /* nsegments */ 1285 ALE_TSO_MAXSEGSIZE, /* maxsegsize */ 1286 0, /* flags */ 1287 NULL, NULL, /* lockfunc, lockarg */ 1288 &sc->ale_cdata.ale_tx_tag); 1289 if (error != 0) { 1290 device_printf(sc->ale_dev, "could not create Tx DMA tag.\n"); 1291 goto fail; 1292 } 1293 1294 /* Create DMA maps for Tx buffers. */ 1295 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1296 txd = &sc->ale_cdata.ale_txdesc[i]; 1297 txd->tx_m = NULL; 1298 txd->tx_dmamap = NULL; 1299 error = bus_dmamap_create(sc->ale_cdata.ale_tx_tag, 0, 1300 &txd->tx_dmamap); 1301 if (error != 0) { 1302 device_printf(sc->ale_dev, 1303 "could not create Tx dmamap.\n"); 1304 goto fail; 1305 } 1306 } 1307 1308 fail: 1309 return (error); 1310 } 1311 1312 static void 1313 ale_dma_free(struct ale_softc *sc) 1314 { 1315 struct ale_txdesc *txd; 1316 int i; 1317 1318 /* Tx buffers. */ 1319 if (sc->ale_cdata.ale_tx_tag != NULL) { 1320 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1321 txd = &sc->ale_cdata.ale_txdesc[i]; 1322 if (txd->tx_dmamap != NULL) { 1323 bus_dmamap_destroy(sc->ale_cdata.ale_tx_tag, 1324 txd->tx_dmamap); 1325 txd->tx_dmamap = NULL; 1326 } 1327 } 1328 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_tag); 1329 sc->ale_cdata.ale_tx_tag = NULL; 1330 } 1331 /* Tx descriptor ring. */ 1332 if (sc->ale_cdata.ale_tx_ring_tag != NULL) { 1333 if (sc->ale_cdata.ale_tx_ring_map != NULL) 1334 bus_dmamap_unload(sc->ale_cdata.ale_tx_ring_tag, 1335 sc->ale_cdata.ale_tx_ring_map); 1336 if (sc->ale_cdata.ale_tx_ring_map != NULL && 1337 sc->ale_cdata.ale_tx_ring != NULL) 1338 bus_dmamem_free(sc->ale_cdata.ale_tx_ring_tag, 1339 sc->ale_cdata.ale_tx_ring, 1340 sc->ale_cdata.ale_tx_ring_map); 1341 sc->ale_cdata.ale_tx_ring = NULL; 1342 sc->ale_cdata.ale_tx_ring_map = NULL; 1343 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_ring_tag); 1344 sc->ale_cdata.ale_tx_ring_tag = NULL; 1345 } 1346 /* Rx page block. */ 1347 for (i = 0; i < ALE_RX_PAGES; i++) { 1348 if (sc->ale_cdata.ale_rx_page[i].page_tag != NULL) { 1349 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL) 1350 bus_dmamap_unload( 1351 sc->ale_cdata.ale_rx_page[i].page_tag, 1352 sc->ale_cdata.ale_rx_page[i].page_map); 1353 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL && 1354 sc->ale_cdata.ale_rx_page[i].page_addr != NULL) 1355 bus_dmamem_free( 1356 sc->ale_cdata.ale_rx_page[i].page_tag, 1357 sc->ale_cdata.ale_rx_page[i].page_addr, 1358 sc->ale_cdata.ale_rx_page[i].page_map); 1359 sc->ale_cdata.ale_rx_page[i].page_addr = NULL; 1360 sc->ale_cdata.ale_rx_page[i].page_map = NULL; 1361 bus_dma_tag_destroy( 1362 sc->ale_cdata.ale_rx_page[i].page_tag); 1363 sc->ale_cdata.ale_rx_page[i].page_tag = NULL; 1364 } 1365 } 1366 /* Rx CMB. */ 1367 for (i = 0; i < ALE_RX_PAGES; i++) { 1368 if (sc->ale_cdata.ale_rx_page[i].cmb_tag != NULL) { 1369 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL) 1370 bus_dmamap_unload( 1371 sc->ale_cdata.ale_rx_page[i].cmb_tag, 1372 sc->ale_cdata.ale_rx_page[i].cmb_map); 1373 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL && 1374 sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) 1375 bus_dmamem_free( 1376 sc->ale_cdata.ale_rx_page[i].cmb_tag, 1377 sc->ale_cdata.ale_rx_page[i].cmb_addr, 1378 sc->ale_cdata.ale_rx_page[i].cmb_map); 1379 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; 1380 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL; 1381 bus_dma_tag_destroy( 1382 sc->ale_cdata.ale_rx_page[i].cmb_tag); 1383 sc->ale_cdata.ale_rx_page[i].cmb_tag = NULL; 1384 } 1385 } 1386 /* Tx CMB. */ 1387 if (sc->ale_cdata.ale_tx_cmb_tag != NULL) { 1388 if (sc->ale_cdata.ale_tx_cmb_map != NULL) 1389 bus_dmamap_unload(sc->ale_cdata.ale_tx_cmb_tag, 1390 sc->ale_cdata.ale_tx_cmb_map); 1391 if (sc->ale_cdata.ale_tx_cmb_map != NULL && 1392 sc->ale_cdata.ale_tx_cmb != NULL) 1393 bus_dmamem_free(sc->ale_cdata.ale_tx_cmb_tag, 1394 sc->ale_cdata.ale_tx_cmb, 1395 sc->ale_cdata.ale_tx_cmb_map); 1396 sc->ale_cdata.ale_tx_cmb = NULL; 1397 sc->ale_cdata.ale_tx_cmb_map = NULL; 1398 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_cmb_tag); 1399 sc->ale_cdata.ale_tx_cmb_tag = NULL; 1400 } 1401 if (sc->ale_cdata.ale_buffer_tag != NULL) { 1402 bus_dma_tag_destroy(sc->ale_cdata.ale_buffer_tag); 1403 sc->ale_cdata.ale_buffer_tag = NULL; 1404 } 1405 if (sc->ale_cdata.ale_parent_tag != NULL) { 1406 bus_dma_tag_destroy(sc->ale_cdata.ale_parent_tag); 1407 sc->ale_cdata.ale_parent_tag = NULL; 1408 } 1409 } 1410 1411 static int 1412 ale_shutdown(device_t dev) 1413 { 1414 1415 return (ale_suspend(dev)); 1416 } 1417 1418 /* 1419 * Note, this driver resets the link speed to 10/100Mbps by 1420 * restarting auto-negotiation in suspend/shutdown phase but we 1421 * don't know whether that auto-negotiation would succeed or not 1422 * as driver has no control after powering off/suspend operation. 1423 * If the renegotiation fail WOL may not work. Running at 1Gbps 1424 * will draw more power than 375mA at 3.3V which is specified in 1425 * PCI specification and that would result in complete 1426 * shutdowning power to ethernet controller. 1427 * 1428 * TODO 1429 * Save current negotiated media speed/duplex/flow-control to 1430 * softc and restore the same link again after resuming. PHY 1431 * handling such as power down/resetting to 100Mbps may be better 1432 * handled in suspend method in phy driver. 1433 */ 1434 static void 1435 ale_setlinkspeed(struct ale_softc *sc) 1436 { 1437 struct mii_data *mii; 1438 int aneg, i; 1439 1440 mii = device_get_softc(sc->ale_miibus); 1441 mii_pollstat(mii); 1442 aneg = 0; 1443 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1444 (IFM_ACTIVE | IFM_AVALID)) { 1445 switch IFM_SUBTYPE(mii->mii_media_active) { 1446 case IFM_10_T: 1447 case IFM_100_TX: 1448 return; 1449 case IFM_1000_T: 1450 aneg++; 1451 break; 1452 default: 1453 break; 1454 } 1455 } 1456 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_100T2CR, 0); 1457 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1458 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1459 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1460 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1461 DELAY(1000); 1462 if (aneg != 0) { 1463 /* 1464 * Poll link state until ale(4) get a 10/100Mbps link. 1465 */ 1466 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1467 mii_pollstat(mii); 1468 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 1469 == (IFM_ACTIVE | IFM_AVALID)) { 1470 switch (IFM_SUBTYPE( 1471 mii->mii_media_active)) { 1472 case IFM_10_T: 1473 case IFM_100_TX: 1474 ale_mac_config(sc); 1475 return; 1476 default: 1477 break; 1478 } 1479 } 1480 ALE_UNLOCK(sc); 1481 pause("alelnk", hz); 1482 ALE_LOCK(sc); 1483 } 1484 if (i == MII_ANEGTICKS_GIGE) 1485 device_printf(sc->ale_dev, 1486 "establishing a link failed, WOL may not work!"); 1487 } 1488 /* 1489 * No link, force MAC to have 100Mbps, full-duplex link. 1490 * This is the last resort and may/may not work. 1491 */ 1492 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1493 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1494 ale_mac_config(sc); 1495 } 1496 1497 static void 1498 ale_setwol(struct ale_softc *sc) 1499 { 1500 struct ifnet *ifp; 1501 uint32_t reg, pmcs; 1502 uint16_t pmstat; 1503 int pmc; 1504 1505 ALE_LOCK_ASSERT(sc); 1506 1507 if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) != 0) { 1508 /* Disable WOL. */ 1509 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 1510 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1511 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1512 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1513 /* Force PHY power down. */ 1514 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1515 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1516 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_PHY_PLL_ON | 1517 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_IDDQ | 1518 GPHY_CTRL_PCLK_SEL_DIS | GPHY_CTRL_PWDOWN_HW); 1519 return; 1520 } 1521 1522 ifp = sc->ale_ifp; 1523 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1524 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 1525 ale_setlinkspeed(sc); 1526 } 1527 1528 pmcs = 0; 1529 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1530 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1531 CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs); 1532 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1533 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 1534 MAC_CFG_BCAST); 1535 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1536 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1537 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1538 reg |= MAC_CFG_RX_ENB; 1539 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1540 1541 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1542 /* WOL disabled, PHY power down. */ 1543 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1544 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1545 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1546 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1547 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1548 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 1549 GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PCLK_SEL_DIS | 1550 GPHY_CTRL_PWDOWN_HW); 1551 } 1552 /* Request PME. */ 1553 pmstat = pci_read_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, 2); 1554 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1555 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1556 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1557 pci_write_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1558 } 1559 1560 static int 1561 ale_suspend(device_t dev) 1562 { 1563 struct ale_softc *sc; 1564 1565 sc = device_get_softc(dev); 1566 1567 ALE_LOCK(sc); 1568 ale_stop(sc); 1569 ale_setwol(sc); 1570 ALE_UNLOCK(sc); 1571 1572 return (0); 1573 } 1574 1575 static int 1576 ale_resume(device_t dev) 1577 { 1578 struct ale_softc *sc; 1579 struct ifnet *ifp; 1580 int pmc; 1581 uint16_t pmstat; 1582 1583 sc = device_get_softc(dev); 1584 1585 ALE_LOCK(sc); 1586 if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) == 0) { 1587 /* Disable PME and clear PME status. */ 1588 pmstat = pci_read_config(sc->ale_dev, 1589 pmc + PCIR_POWER_STATUS, 2); 1590 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 1591 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1592 pci_write_config(sc->ale_dev, 1593 pmc + PCIR_POWER_STATUS, pmstat, 2); 1594 } 1595 } 1596 /* Reset PHY. */ 1597 ale_phy_reset(sc); 1598 ifp = sc->ale_ifp; 1599 if ((ifp->if_flags & IFF_UP) != 0) { 1600 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1601 ale_init_locked(sc); 1602 } 1603 ALE_UNLOCK(sc); 1604 1605 return (0); 1606 } 1607 1608 static int 1609 ale_encap(struct ale_softc *sc, struct mbuf **m_head) 1610 { 1611 struct ale_txdesc *txd, *txd_last; 1612 struct tx_desc *desc; 1613 struct mbuf *m; 1614 struct ip *ip; 1615 struct tcphdr *tcp; 1616 bus_dma_segment_t txsegs[ALE_MAXTXSEGS]; 1617 bus_dmamap_t map; 1618 uint32_t cflags, hdrlen, ip_off, poff, vtag; 1619 int error, i, nsegs, prod, si; 1620 1621 ALE_LOCK_ASSERT(sc); 1622 1623 M_ASSERTPKTHDR((*m_head)); 1624 1625 m = *m_head; 1626 ip = NULL; 1627 tcp = NULL; 1628 cflags = vtag = 0; 1629 ip_off = poff = 0; 1630 if ((m->m_pkthdr.csum_flags & (ALE_CSUM_FEATURES | CSUM_TSO)) != 0) { 1631 /* 1632 * AR81xx requires offset of TCP/UDP payload in its Tx 1633 * descriptor to perform hardware Tx checksum offload. 1634 * Additionally, TSO requires IP/TCP header size and 1635 * modification of IP/TCP header in order to make TSO 1636 * engine work. This kind of operation takes many CPU 1637 * cycles on FreeBSD so fast host CPU is required to 1638 * get smooth TSO performance. 1639 */ 1640 struct ether_header *eh; 1641 1642 if (M_WRITABLE(m) == 0) { 1643 /* Get a writable copy. */ 1644 m = m_dup(*m_head, M_NOWAIT); 1645 /* Release original mbufs. */ 1646 m_freem(*m_head); 1647 if (m == NULL) { 1648 *m_head = NULL; 1649 return (ENOBUFS); 1650 } 1651 *m_head = m; 1652 } 1653 1654 /* 1655 * Buggy-controller requires 4 byte aligned Tx buffer 1656 * to make custom checksum offload work. 1657 */ 1658 if ((sc->ale_flags & ALE_FLAG_TXCSUM_BUG) != 0 && 1659 (m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0 && 1660 (mtod(m, intptr_t) & 3) != 0) { 1661 m = m_defrag(*m_head, M_NOWAIT); 1662 if (m == NULL) { 1663 *m_head = NULL; 1664 return (ENOBUFS); 1665 } 1666 *m_head = m; 1667 } 1668 1669 ip_off = sizeof(struct ether_header); 1670 m = m_pullup(m, ip_off); 1671 if (m == NULL) { 1672 *m_head = NULL; 1673 return (ENOBUFS); 1674 } 1675 eh = mtod(m, struct ether_header *); 1676 /* 1677 * Check if hardware VLAN insertion is off. 1678 * Additional check for LLC/SNAP frame? 1679 */ 1680 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1681 ip_off = sizeof(struct ether_vlan_header); 1682 m = m_pullup(m, ip_off); 1683 if (m == NULL) { 1684 *m_head = NULL; 1685 return (ENOBUFS); 1686 } 1687 } 1688 m = m_pullup(m, ip_off + sizeof(struct ip)); 1689 if (m == NULL) { 1690 *m_head = NULL; 1691 return (ENOBUFS); 1692 } 1693 ip = (struct ip *)(mtod(m, char *) + ip_off); 1694 poff = ip_off + (ip->ip_hl << 2); 1695 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1696 /* 1697 * XXX 1698 * AR81xx requires the first descriptor should 1699 * not include any TCP playload for TSO case. 1700 * (i.e. ethernet header + IP + TCP header only) 1701 * m_pullup(9) above will ensure this too. 1702 * However it's not correct if the first mbuf 1703 * of the chain does not use cluster. 1704 */ 1705 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1706 if (m == NULL) { 1707 *m_head = NULL; 1708 return (ENOBUFS); 1709 } 1710 ip = (struct ip *)(mtod(m, char *) + ip_off); 1711 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1712 m = m_pullup(m, poff + (tcp->th_off << 2)); 1713 if (m == NULL) { 1714 *m_head = NULL; 1715 return (ENOBUFS); 1716 } 1717 /* 1718 * AR81xx requires IP/TCP header size and offset as 1719 * well as TCP pseudo checksum which complicates 1720 * TSO configuration. I guess this comes from the 1721 * adherence to Microsoft NDIS Large Send 1722 * specification which requires insertion of 1723 * pseudo checksum by upper stack. The pseudo 1724 * checksum that NDIS refers to doesn't include 1725 * TCP payload length so ale(4) should recompute 1726 * the pseudo checksum here. Hopefully this wouldn't 1727 * be much burden on modern CPUs. 1728 * Reset IP checksum and recompute TCP pseudo 1729 * checksum as NDIS specification said. 1730 */ 1731 ip->ip_sum = 0; 1732 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1733 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1734 } 1735 *m_head = m; 1736 } 1737 1738 si = prod = sc->ale_cdata.ale_tx_prod; 1739 txd = &sc->ale_cdata.ale_txdesc[prod]; 1740 txd_last = txd; 1741 map = txd->tx_dmamap; 1742 1743 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1744 *m_head, txsegs, &nsegs, 0); 1745 if (error == EFBIG) { 1746 m = m_collapse(*m_head, M_NOWAIT, ALE_MAXTXSEGS); 1747 if (m == NULL) { 1748 m_freem(*m_head); 1749 *m_head = NULL; 1750 return (ENOMEM); 1751 } 1752 *m_head = m; 1753 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1754 *m_head, txsegs, &nsegs, 0); 1755 if (error != 0) { 1756 m_freem(*m_head); 1757 *m_head = NULL; 1758 return (error); 1759 } 1760 } else if (error != 0) 1761 return (error); 1762 if (nsegs == 0) { 1763 m_freem(*m_head); 1764 *m_head = NULL; 1765 return (EIO); 1766 } 1767 1768 /* Check descriptor overrun. */ 1769 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 3) { 1770 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, map); 1771 return (ENOBUFS); 1772 } 1773 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, map, BUS_DMASYNC_PREWRITE); 1774 1775 m = *m_head; 1776 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1777 /* Request TSO and set MSS. */ 1778 cflags |= ALE_TD_TSO; 1779 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << ALE_TD_MSS_SHIFT); 1780 /* Set IP/TCP header size. */ 1781 cflags |= ip->ip_hl << ALE_TD_IPHDR_LEN_SHIFT; 1782 cflags |= tcp->th_off << ALE_TD_TCPHDR_LEN_SHIFT; 1783 } else if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { 1784 /* 1785 * AR81xx supports Tx custom checksum offload feature 1786 * that offloads single 16bit checksum computation. 1787 * So you can choose one among IP, TCP and UDP. 1788 * Normally driver sets checksum start/insertion 1789 * position from the information of TCP/UDP frame as 1790 * TCP/UDP checksum takes more time than that of IP. 1791 * However it seems that custom checksum offload 1792 * requires 4 bytes aligned Tx buffers due to hardware 1793 * bug. 1794 * AR81xx also supports explicit Tx checksum computation 1795 * if it is told that the size of IP header and TCP 1796 * header(for UDP, the header size does not matter 1797 * because it's fixed length). However with this scheme 1798 * TSO does not work so you have to choose one either 1799 * TSO or explicit Tx checksum offload. I chosen TSO 1800 * plus custom checksum offload with work-around which 1801 * will cover most common usage for this consumer 1802 * ethernet controller. The work-around takes a lot of 1803 * CPU cycles if Tx buffer is not aligned on 4 bytes 1804 * boundary, though. 1805 */ 1806 cflags |= ALE_TD_CXSUM; 1807 /* Set checksum start offset. */ 1808 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); 1809 /* Set checksum insertion position of TCP/UDP. */ 1810 cflags |= ((poff + m->m_pkthdr.csum_data) << 1811 ALE_TD_CSUM_XSUMOFFSET_SHIFT); 1812 } 1813 1814 /* Configure VLAN hardware tag insertion. */ 1815 if ((m->m_flags & M_VLANTAG) != 0) { 1816 vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1817 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); 1818 cflags |= ALE_TD_INSERT_VLAN_TAG; 1819 } 1820 1821 i = 0; 1822 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1823 /* 1824 * Make sure the first fragment contains 1825 * only ethernet and IP/TCP header with options. 1826 */ 1827 hdrlen = poff + (tcp->th_off << 2); 1828 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1829 desc->addr = htole64(txsegs[i].ds_addr); 1830 desc->len = htole32(ALE_TX_BYTES(hdrlen) | vtag); 1831 desc->flags = htole32(cflags); 1832 sc->ale_cdata.ale_tx_cnt++; 1833 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1834 if (m->m_len - hdrlen > 0) { 1835 /* Handle remaining payload of the first fragment. */ 1836 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1837 desc->addr = htole64(txsegs[i].ds_addr + hdrlen); 1838 desc->len = htole32(ALE_TX_BYTES(m->m_len - hdrlen) | 1839 vtag); 1840 desc->flags = htole32(cflags); 1841 sc->ale_cdata.ale_tx_cnt++; 1842 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1843 } 1844 i = 1; 1845 } 1846 for (; i < nsegs; i++) { 1847 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1848 desc->addr = htole64(txsegs[i].ds_addr); 1849 desc->len = htole32(ALE_TX_BYTES(txsegs[i].ds_len) | vtag); 1850 desc->flags = htole32(cflags); 1851 sc->ale_cdata.ale_tx_cnt++; 1852 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1853 } 1854 /* Update producer index. */ 1855 sc->ale_cdata.ale_tx_prod = prod; 1856 /* Set TSO header on the first descriptor. */ 1857 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1858 desc = &sc->ale_cdata.ale_tx_ring[si]; 1859 desc->flags |= htole32(ALE_TD_TSO_HDR); 1860 } 1861 1862 /* Finally set EOP on the last descriptor. */ 1863 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; 1864 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1865 desc->flags |= htole32(ALE_TD_EOP); 1866 1867 /* Swap dmamap of the first and the last. */ 1868 txd = &sc->ale_cdata.ale_txdesc[prod]; 1869 map = txd_last->tx_dmamap; 1870 txd_last->tx_dmamap = txd->tx_dmamap; 1871 txd->tx_dmamap = map; 1872 txd->tx_m = m; 1873 1874 /* Sync descriptors. */ 1875 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 1876 sc->ale_cdata.ale_tx_ring_map, 1877 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1878 1879 return (0); 1880 } 1881 1882 static void 1883 ale_start(struct ifnet *ifp) 1884 { 1885 struct ale_softc *sc; 1886 1887 sc = ifp->if_softc; 1888 ALE_LOCK(sc); 1889 ale_start_locked(ifp); 1890 ALE_UNLOCK(sc); 1891 } 1892 1893 static void 1894 ale_start_locked(struct ifnet *ifp) 1895 { 1896 struct ale_softc *sc; 1897 struct mbuf *m_head; 1898 int enq; 1899 1900 sc = ifp->if_softc; 1901 1902 ALE_LOCK_ASSERT(sc); 1903 1904 /* Reclaim transmitted frames. */ 1905 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) 1906 ale_txeof(sc); 1907 1908 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1909 IFF_DRV_RUNNING || (sc->ale_flags & ALE_FLAG_LINK) == 0) 1910 return; 1911 1912 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1913 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1914 if (m_head == NULL) 1915 break; 1916 /* 1917 * Pack the data into the transmit ring. If we 1918 * don't have room, set the OACTIVE flag and wait 1919 * for the NIC to drain the ring. 1920 */ 1921 if (ale_encap(sc, &m_head)) { 1922 if (m_head == NULL) 1923 break; 1924 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1925 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1926 break; 1927 } 1928 1929 enq++; 1930 /* 1931 * If there's a BPF listener, bounce a copy of this frame 1932 * to him. 1933 */ 1934 ETHER_BPF_MTAP(ifp, m_head); 1935 } 1936 1937 if (enq > 0) { 1938 /* Kick. */ 1939 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, 1940 sc->ale_cdata.ale_tx_prod); 1941 /* Set a timeout in case the chip goes out to lunch. */ 1942 sc->ale_watchdog_timer = ALE_TX_TIMEOUT; 1943 } 1944 } 1945 1946 static void 1947 ale_watchdog(struct ale_softc *sc) 1948 { 1949 struct ifnet *ifp; 1950 1951 ALE_LOCK_ASSERT(sc); 1952 1953 if (sc->ale_watchdog_timer == 0 || --sc->ale_watchdog_timer) 1954 return; 1955 1956 ifp = sc->ale_ifp; 1957 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1958 if_printf(sc->ale_ifp, "watchdog timeout (lost link)\n"); 1959 ifp->if_oerrors++; 1960 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1961 ale_init_locked(sc); 1962 return; 1963 } 1964 if_printf(sc->ale_ifp, "watchdog timeout -- resetting\n"); 1965 ifp->if_oerrors++; 1966 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1967 ale_init_locked(sc); 1968 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1969 ale_start_locked(ifp); 1970 } 1971 1972 static int 1973 ale_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1974 { 1975 struct ale_softc *sc; 1976 struct ifreq *ifr; 1977 struct mii_data *mii; 1978 int error, mask; 1979 1980 sc = ifp->if_softc; 1981 ifr = (struct ifreq *)data; 1982 error = 0; 1983 switch (cmd) { 1984 case SIOCSIFMTU: 1985 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALE_JUMBO_MTU || 1986 ((sc->ale_flags & ALE_FLAG_JUMBO) == 0 && 1987 ifr->ifr_mtu > ETHERMTU)) 1988 error = EINVAL; 1989 else if (ifp->if_mtu != ifr->ifr_mtu) { 1990 ALE_LOCK(sc); 1991 ifp->if_mtu = ifr->ifr_mtu; 1992 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1993 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1994 ale_init_locked(sc); 1995 } 1996 ALE_UNLOCK(sc); 1997 } 1998 break; 1999 case SIOCSIFFLAGS: 2000 ALE_LOCK(sc); 2001 if ((ifp->if_flags & IFF_UP) != 0) { 2002 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2003 if (((ifp->if_flags ^ sc->ale_if_flags) 2004 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 2005 ale_rxfilter(sc); 2006 } else { 2007 ale_init_locked(sc); 2008 } 2009 } else { 2010 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2011 ale_stop(sc); 2012 } 2013 sc->ale_if_flags = ifp->if_flags; 2014 ALE_UNLOCK(sc); 2015 break; 2016 case SIOCADDMULTI: 2017 case SIOCDELMULTI: 2018 ALE_LOCK(sc); 2019 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2020 ale_rxfilter(sc); 2021 ALE_UNLOCK(sc); 2022 break; 2023 case SIOCSIFMEDIA: 2024 case SIOCGIFMEDIA: 2025 mii = device_get_softc(sc->ale_miibus); 2026 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2027 break; 2028 case SIOCSIFCAP: 2029 ALE_LOCK(sc); 2030 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2031 if ((mask & IFCAP_TXCSUM) != 0 && 2032 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2033 ifp->if_capenable ^= IFCAP_TXCSUM; 2034 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2035 ifp->if_hwassist |= ALE_CSUM_FEATURES; 2036 else 2037 ifp->if_hwassist &= ~ALE_CSUM_FEATURES; 2038 } 2039 if ((mask & IFCAP_RXCSUM) != 0 && 2040 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 2041 ifp->if_capenable ^= IFCAP_RXCSUM; 2042 if ((mask & IFCAP_TSO4) != 0 && 2043 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 2044 ifp->if_capenable ^= IFCAP_TSO4; 2045 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 2046 ifp->if_hwassist |= CSUM_TSO; 2047 else 2048 ifp->if_hwassist &= ~CSUM_TSO; 2049 } 2050 2051 if ((mask & IFCAP_WOL_MCAST) != 0 && 2052 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 2053 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2054 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2055 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2056 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2057 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2058 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 2059 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2060 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2061 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 2062 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2063 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2064 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2065 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2066 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 2067 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 2068 ale_rxvlan(sc); 2069 } 2070 ALE_UNLOCK(sc); 2071 VLAN_CAPABILITIES(ifp); 2072 break; 2073 default: 2074 error = ether_ioctl(ifp, cmd, data); 2075 break; 2076 } 2077 2078 return (error); 2079 } 2080 2081 static void 2082 ale_mac_config(struct ale_softc *sc) 2083 { 2084 struct mii_data *mii; 2085 uint32_t reg; 2086 2087 ALE_LOCK_ASSERT(sc); 2088 2089 mii = device_get_softc(sc->ale_miibus); 2090 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2091 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2092 MAC_CFG_SPEED_MASK); 2093 /* Reprogram MAC with resolved speed/duplex. */ 2094 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2095 case IFM_10_T: 2096 case IFM_100_TX: 2097 reg |= MAC_CFG_SPEED_10_100; 2098 break; 2099 case IFM_1000_T: 2100 reg |= MAC_CFG_SPEED_1000; 2101 break; 2102 } 2103 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2104 reg |= MAC_CFG_FULL_DUPLEX; 2105 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2106 reg |= MAC_CFG_TX_FC; 2107 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2108 reg |= MAC_CFG_RX_FC; 2109 } 2110 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2111 } 2112 2113 static void 2114 ale_stats_clear(struct ale_softc *sc) 2115 { 2116 struct smb sb; 2117 uint32_t *reg; 2118 int i; 2119 2120 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2121 CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2122 i += sizeof(uint32_t); 2123 } 2124 /* Read Tx statistics. */ 2125 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2126 CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2127 i += sizeof(uint32_t); 2128 } 2129 } 2130 2131 static void 2132 ale_stats_update(struct ale_softc *sc) 2133 { 2134 struct ale_hw_stats *stat; 2135 struct smb sb, *smb; 2136 struct ifnet *ifp; 2137 uint32_t *reg; 2138 int i; 2139 2140 ALE_LOCK_ASSERT(sc); 2141 2142 ifp = sc->ale_ifp; 2143 stat = &sc->ale_stats; 2144 smb = &sb; 2145 2146 /* Read Rx statistics. */ 2147 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2148 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2149 i += sizeof(uint32_t); 2150 } 2151 /* Read Tx statistics. */ 2152 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2153 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2154 i += sizeof(uint32_t); 2155 } 2156 2157 /* Rx stats. */ 2158 stat->rx_frames += smb->rx_frames; 2159 stat->rx_bcast_frames += smb->rx_bcast_frames; 2160 stat->rx_mcast_frames += smb->rx_mcast_frames; 2161 stat->rx_pause_frames += smb->rx_pause_frames; 2162 stat->rx_control_frames += smb->rx_control_frames; 2163 stat->rx_crcerrs += smb->rx_crcerrs; 2164 stat->rx_lenerrs += smb->rx_lenerrs; 2165 stat->rx_bytes += smb->rx_bytes; 2166 stat->rx_runts += smb->rx_runts; 2167 stat->rx_fragments += smb->rx_fragments; 2168 stat->rx_pkts_64 += smb->rx_pkts_64; 2169 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2170 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2171 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2172 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2173 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2174 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2175 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2176 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2177 stat->rx_rrs_errs += smb->rx_rrs_errs; 2178 stat->rx_alignerrs += smb->rx_alignerrs; 2179 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2180 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2181 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2182 2183 /* Tx stats. */ 2184 stat->tx_frames += smb->tx_frames; 2185 stat->tx_bcast_frames += smb->tx_bcast_frames; 2186 stat->tx_mcast_frames += smb->tx_mcast_frames; 2187 stat->tx_pause_frames += smb->tx_pause_frames; 2188 stat->tx_excess_defer += smb->tx_excess_defer; 2189 stat->tx_control_frames += smb->tx_control_frames; 2190 stat->tx_deferred += smb->tx_deferred; 2191 stat->tx_bytes += smb->tx_bytes; 2192 stat->tx_pkts_64 += smb->tx_pkts_64; 2193 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2194 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2195 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2196 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2197 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2198 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2199 stat->tx_single_colls += smb->tx_single_colls; 2200 stat->tx_multi_colls += smb->tx_multi_colls; 2201 stat->tx_late_colls += smb->tx_late_colls; 2202 stat->tx_excess_colls += smb->tx_excess_colls; 2203 stat->tx_abort += smb->tx_abort; 2204 stat->tx_underrun += smb->tx_underrun; 2205 stat->tx_desc_underrun += smb->tx_desc_underrun; 2206 stat->tx_lenerrs += smb->tx_lenerrs; 2207 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2208 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2209 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2210 2211 /* Update counters in ifnet. */ 2212 ifp->if_opackets += smb->tx_frames; 2213 2214 ifp->if_collisions += smb->tx_single_colls + 2215 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2216 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 2217 2218 /* 2219 * XXX 2220 * tx_pkts_truncated counter looks suspicious. It constantly 2221 * increments with no sign of Tx errors. This may indicate 2222 * the counter name is not correct one so I've removed the 2223 * counter in output errors. 2224 */ 2225 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 2226 smb->tx_underrun; 2227 2228 ifp->if_ipackets += smb->rx_frames; 2229 2230 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2231 smb->rx_runts + smb->rx_pkts_truncated + 2232 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2233 smb->rx_alignerrs; 2234 } 2235 2236 static int 2237 ale_intr(void *arg) 2238 { 2239 struct ale_softc *sc; 2240 uint32_t status; 2241 2242 sc = (struct ale_softc *)arg; 2243 2244 status = CSR_READ_4(sc, ALE_INTR_STATUS); 2245 if ((status & ALE_INTRS) == 0) 2246 return (FILTER_STRAY); 2247 /* Disable interrupts. */ 2248 CSR_WRITE_4(sc, ALE_INTR_STATUS, INTR_DIS_INT); 2249 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2250 2251 return (FILTER_HANDLED); 2252 } 2253 2254 static void 2255 ale_int_task(void *arg, int pending) 2256 { 2257 struct ale_softc *sc; 2258 struct ifnet *ifp; 2259 uint32_t status; 2260 int more; 2261 2262 sc = (struct ale_softc *)arg; 2263 2264 status = CSR_READ_4(sc, ALE_INTR_STATUS); 2265 ALE_LOCK(sc); 2266 if (sc->ale_morework != 0) 2267 status |= INTR_RX_PKT; 2268 if ((status & ALE_INTRS) == 0) 2269 goto done; 2270 2271 /* Acknowledge interrupts but still disable interrupts. */ 2272 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); 2273 2274 ifp = sc->ale_ifp; 2275 more = 0; 2276 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2277 more = ale_rxeof(sc, sc->ale_process_limit); 2278 if (more == EAGAIN) 2279 sc->ale_morework = 1; 2280 else if (more == EIO) { 2281 sc->ale_stats.reset_brk_seq++; 2282 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2283 ale_init_locked(sc); 2284 ALE_UNLOCK(sc); 2285 return; 2286 } 2287 2288 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 2289 if ((status & INTR_DMA_RD_TO_RST) != 0) 2290 device_printf(sc->ale_dev, 2291 "DMA read error! -- resetting\n"); 2292 if ((status & INTR_DMA_WR_TO_RST) != 0) 2293 device_printf(sc->ale_dev, 2294 "DMA write error! -- resetting\n"); 2295 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2296 ale_init_locked(sc); 2297 ALE_UNLOCK(sc); 2298 return; 2299 } 2300 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2301 ale_start_locked(ifp); 2302 } 2303 2304 if (more == EAGAIN || 2305 (CSR_READ_4(sc, ALE_INTR_STATUS) & ALE_INTRS) != 0) { 2306 ALE_UNLOCK(sc); 2307 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2308 return; 2309 } 2310 2311 done: 2312 ALE_UNLOCK(sc); 2313 2314 /* Re-enable interrupts. */ 2315 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); 2316 } 2317 2318 static void 2319 ale_txeof(struct ale_softc *sc) 2320 { 2321 struct ifnet *ifp; 2322 struct ale_txdesc *txd; 2323 uint32_t cons, prod; 2324 int prog; 2325 2326 ALE_LOCK_ASSERT(sc); 2327 2328 ifp = sc->ale_ifp; 2329 2330 if (sc->ale_cdata.ale_tx_cnt == 0) 2331 return; 2332 2333 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2334 sc->ale_cdata.ale_tx_ring_map, 2335 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2336 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { 2337 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2338 sc->ale_cdata.ale_tx_cmb_map, 2339 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2340 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; 2341 } else 2342 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); 2343 cons = sc->ale_cdata.ale_tx_cons; 2344 /* 2345 * Go through our Tx list and free mbufs for those 2346 * frames which have been transmitted. 2347 */ 2348 for (prog = 0; cons != prod; prog++, 2349 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { 2350 if (sc->ale_cdata.ale_tx_cnt <= 0) 2351 break; 2352 prog++; 2353 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2354 sc->ale_cdata.ale_tx_cnt--; 2355 txd = &sc->ale_cdata.ale_txdesc[cons]; 2356 if (txd->tx_m != NULL) { 2357 /* Reclaim transmitted mbufs. */ 2358 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2359 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2360 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2361 txd->tx_dmamap); 2362 m_freem(txd->tx_m); 2363 txd->tx_m = NULL; 2364 } 2365 } 2366 2367 if (prog > 0) { 2368 sc->ale_cdata.ale_tx_cons = cons; 2369 /* 2370 * Unarm watchdog timer only when there is no pending 2371 * Tx descriptors in queue. 2372 */ 2373 if (sc->ale_cdata.ale_tx_cnt == 0) 2374 sc->ale_watchdog_timer = 0; 2375 } 2376 } 2377 2378 static void 2379 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, 2380 uint32_t length, uint32_t *prod) 2381 { 2382 struct ale_rx_page *rx_page; 2383 2384 rx_page = *page; 2385 /* Update consumer position. */ 2386 rx_page->cons += roundup(length + sizeof(struct rx_rs), 2387 ALE_RX_PAGE_ALIGN); 2388 if (rx_page->cons >= ALE_RX_PAGE_SZ) { 2389 /* 2390 * End of Rx page reached, let hardware reuse 2391 * this page. 2392 */ 2393 rx_page->cons = 0; 2394 *rx_page->cmb_addr = 0; 2395 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2396 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2397 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, 2398 RXF_VALID); 2399 /* Switch to alternate Rx page. */ 2400 sc->ale_cdata.ale_rx_curp ^= 1; 2401 rx_page = *page = 2402 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2403 /* Page flipped, sync CMB and Rx page. */ 2404 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2405 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2406 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2407 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2408 /* Sync completed, cache updated producer index. */ 2409 *prod = *rx_page->cmb_addr; 2410 } 2411 } 2412 2413 2414 /* 2415 * It seems that AR81xx controller can compute partial checksum. 2416 * The partial checksum value can be used to accelerate checksum 2417 * computation for fragmented TCP/UDP packets. Upper network stack 2418 * already takes advantage of the partial checksum value in IP 2419 * reassembly stage. But I'm not sure the correctness of the 2420 * partial hardware checksum assistance due to lack of data sheet. 2421 * In addition, the Rx feature of controller that requires copying 2422 * for every frames effectively nullifies one of most nice offload 2423 * capability of controller. 2424 */ 2425 static void 2426 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) 2427 { 2428 struct ifnet *ifp; 2429 struct ip *ip; 2430 char *p; 2431 2432 ifp = sc->ale_ifp; 2433 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2434 if ((status & ALE_RD_IPCSUM_NOK) == 0) 2435 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2436 2437 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { 2438 if (((status & ALE_RD_IPV4_FRAG) == 0) && 2439 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && 2440 ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) { 2441 m->m_pkthdr.csum_flags |= 2442 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2443 m->m_pkthdr.csum_data = 0xffff; 2444 } 2445 } else { 2446 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 && 2447 (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) { 2448 p = mtod(m, char *); 2449 p += ETHER_HDR_LEN; 2450 if ((status & ALE_RD_802_3) != 0) 2451 p += LLC_SNAPFRAMELEN; 2452 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0 && 2453 (status & ALE_RD_VLAN) != 0) 2454 p += ETHER_VLAN_ENCAP_LEN; 2455 ip = (struct ip *)p; 2456 if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0) 2457 return; 2458 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 2459 CSUM_PSEUDO_HDR; 2460 m->m_pkthdr.csum_data = 0xffff; 2461 } 2462 } 2463 /* 2464 * Don't mark bad checksum for TCP/UDP frames 2465 * as fragmented frames may always have set 2466 * bad checksummed bit of frame status. 2467 */ 2468 } 2469 2470 /* Process received frames. */ 2471 static int 2472 ale_rxeof(struct ale_softc *sc, int count) 2473 { 2474 struct ale_rx_page *rx_page; 2475 struct rx_rs *rs; 2476 struct ifnet *ifp; 2477 struct mbuf *m; 2478 uint32_t length, prod, seqno, status, vtags; 2479 int prog; 2480 2481 ifp = sc->ale_ifp; 2482 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2483 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2484 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2485 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2486 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2487 /* 2488 * Don't directly access producer index as hardware may 2489 * update it while Rx handler is in progress. It would 2490 * be even better if there is a way to let hardware 2491 * know how far driver processed its received frames. 2492 * Alternatively, hardware could provide a way to disable 2493 * CMB updates until driver acknowledges the end of CMB 2494 * access. 2495 */ 2496 prod = *rx_page->cmb_addr; 2497 for (prog = 0; prog < count; prog++) { 2498 if (rx_page->cons >= prod) 2499 break; 2500 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); 2501 seqno = ALE_RX_SEQNO(le32toh(rs->seqno)); 2502 if (sc->ale_cdata.ale_rx_seqno != seqno) { 2503 /* 2504 * Normally I believe this should not happen unless 2505 * severe driver bug or corrupted memory. However 2506 * it seems to happen under certain conditions which 2507 * is triggered by abrupt Rx events such as initiation 2508 * of bulk transfer of remote host. It's not easy to 2509 * reproduce this and I doubt it could be related 2510 * with FIFO overflow of hardware or activity of Tx 2511 * CMB updates. I also remember similar behaviour 2512 * seen on RealTek 8139 which uses resembling Rx 2513 * scheme. 2514 */ 2515 if (bootverbose) 2516 device_printf(sc->ale_dev, 2517 "garbled seq: %u, expected: %u -- " 2518 "resetting!\n", seqno, 2519 sc->ale_cdata.ale_rx_seqno); 2520 return (EIO); 2521 } 2522 /* Frame received. */ 2523 sc->ale_cdata.ale_rx_seqno++; 2524 length = ALE_RX_BYTES(le32toh(rs->length)); 2525 status = le32toh(rs->flags); 2526 if ((status & ALE_RD_ERROR) != 0) { 2527 /* 2528 * We want to pass the following frames to upper 2529 * layer regardless of error status of Rx return 2530 * status. 2531 * 2532 * o IP/TCP/UDP checksum is bad. 2533 * o frame length and protocol specific length 2534 * does not match. 2535 */ 2536 if ((status & (ALE_RD_CRC | ALE_RD_CODE | 2537 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | 2538 ALE_RD_TRUNC)) != 0) { 2539 ale_rx_update_page(sc, &rx_page, length, &prod); 2540 continue; 2541 } 2542 } 2543 /* 2544 * m_devget(9) is major bottle-neck of ale(4)(It comes 2545 * from hardware limitation). For jumbo frames we could 2546 * get a slightly better performance if driver use 2547 * m_getjcl(9) with proper buffer size argument. However 2548 * that would make code more complicated and I don't 2549 * think users would expect good Rx performance numbers 2550 * on these low-end consumer ethernet controller. 2551 */ 2552 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, 2553 ETHER_ALIGN, ifp, NULL); 2554 if (m == NULL) { 2555 ifp->if_iqdrops++; 2556 ale_rx_update_page(sc, &rx_page, length, &prod); 2557 continue; 2558 } 2559 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 2560 (status & ALE_RD_IPV4) != 0) 2561 ale_rxcsum(sc, m, status); 2562 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 2563 (status & ALE_RD_VLAN) != 0) { 2564 vtags = ALE_RX_VLAN(le32toh(rs->vtags)); 2565 m->m_pkthdr.ether_vtag = ALE_RX_VLAN_TAG(vtags); 2566 m->m_flags |= M_VLANTAG; 2567 } 2568 2569 /* Pass it to upper layer. */ 2570 ALE_UNLOCK(sc); 2571 (*ifp->if_input)(ifp, m); 2572 ALE_LOCK(sc); 2573 2574 ale_rx_update_page(sc, &rx_page, length, &prod); 2575 } 2576 2577 return (count > 0 ? 0 : EAGAIN); 2578 } 2579 2580 static void 2581 ale_tick(void *arg) 2582 { 2583 struct ale_softc *sc; 2584 struct mii_data *mii; 2585 2586 sc = (struct ale_softc *)arg; 2587 2588 ALE_LOCK_ASSERT(sc); 2589 2590 mii = device_get_softc(sc->ale_miibus); 2591 mii_tick(mii); 2592 ale_stats_update(sc); 2593 /* 2594 * Reclaim Tx buffers that have been transferred. It's not 2595 * needed here but it would release allocated mbuf chains 2596 * faster and limit the maximum delay to a hz. 2597 */ 2598 ale_txeof(sc); 2599 ale_watchdog(sc); 2600 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2601 } 2602 2603 static void 2604 ale_reset(struct ale_softc *sc) 2605 { 2606 uint32_t reg; 2607 int i; 2608 2609 /* Initialize PCIe module. From Linux. */ 2610 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2611 2612 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); 2613 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2614 DELAY(10); 2615 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) 2616 break; 2617 } 2618 if (i == 0) 2619 device_printf(sc->ale_dev, "master reset timeout!\n"); 2620 2621 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2622 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) 2623 break; 2624 DELAY(10); 2625 } 2626 2627 if (i == 0) 2628 device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg); 2629 } 2630 2631 static void 2632 ale_init(void *xsc) 2633 { 2634 struct ale_softc *sc; 2635 2636 sc = (struct ale_softc *)xsc; 2637 ALE_LOCK(sc); 2638 ale_init_locked(sc); 2639 ALE_UNLOCK(sc); 2640 } 2641 2642 static void 2643 ale_init_locked(struct ale_softc *sc) 2644 { 2645 struct ifnet *ifp; 2646 struct mii_data *mii; 2647 uint8_t eaddr[ETHER_ADDR_LEN]; 2648 bus_addr_t paddr; 2649 uint32_t reg, rxf_hi, rxf_lo; 2650 2651 ALE_LOCK_ASSERT(sc); 2652 2653 ifp = sc->ale_ifp; 2654 mii = device_get_softc(sc->ale_miibus); 2655 2656 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2657 return; 2658 /* 2659 * Cancel any pending I/O. 2660 */ 2661 ale_stop(sc); 2662 /* 2663 * Reset the chip to a known state. 2664 */ 2665 ale_reset(sc); 2666 /* Initialize Tx descriptors, DMA memory blocks. */ 2667 ale_init_rx_pages(sc); 2668 ale_init_tx_ring(sc); 2669 2670 /* Reprogram the station address. */ 2671 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2672 CSR_WRITE_4(sc, ALE_PAR0, 2673 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2674 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); 2675 /* 2676 * Clear WOL status and disable all WOL feature as WOL 2677 * would interfere Rx operation under normal environments. 2678 */ 2679 CSR_READ_4(sc, ALE_WOL_CFG); 2680 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 2681 /* 2682 * Set Tx descriptor/RXF0/CMB base addresses. They share 2683 * the same high address part of DMAable region. 2684 */ 2685 paddr = sc->ale_cdata.ale_tx_ring_paddr; 2686 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); 2687 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); 2688 CSR_WRITE_4(sc, ALE_TPD_CNT, 2689 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); 2690 /* Set Rx page base address, note we use single queue. */ 2691 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; 2692 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); 2693 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; 2694 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); 2695 /* Set Tx/Rx CMB addresses. */ 2696 paddr = sc->ale_cdata.ale_tx_cmb_paddr; 2697 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); 2698 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; 2699 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); 2700 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; 2701 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); 2702 /* Mark RXF0 is valid. */ 2703 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); 2704 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); 2705 /* 2706 * No need to initialize RFX1/RXF2/RXF3. We don't use 2707 * multi-queue yet. 2708 */ 2709 2710 /* Set Rx page size, excluding guard frame size. */ 2711 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); 2712 /* Tell hardware that we're ready to load DMA blocks. */ 2713 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); 2714 2715 /* Set Rx/Tx interrupt trigger threshold. */ 2716 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | 2717 (4 << INT_TRIG_TX_THRESH_SHIFT)); 2718 /* 2719 * XXX 2720 * Set interrupt trigger timer, its purpose and relation 2721 * with interrupt moderation mechanism is not clear yet. 2722 */ 2723 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, 2724 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | 2725 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); 2726 2727 /* Configure interrupt moderation timer. */ 2728 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; 2729 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; 2730 CSR_WRITE_4(sc, ALE_IM_TIMER, reg); 2731 reg = CSR_READ_4(sc, ALE_MASTER_CFG); 2732 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 2733 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 2734 if (ALE_USECS(sc->ale_int_rx_mod) != 0) 2735 reg |= MASTER_IM_RX_TIMER_ENB; 2736 if (ALE_USECS(sc->ale_int_tx_mod) != 0) 2737 reg |= MASTER_IM_TX_TIMER_ENB; 2738 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); 2739 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); 2740 2741 /* Set Maximum frame size of controller. */ 2742 if (ifp->if_mtu < ETHERMTU) 2743 sc->ale_max_frame_size = ETHERMTU; 2744 else 2745 sc->ale_max_frame_size = ifp->if_mtu; 2746 sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 2747 ETHER_CRC_LEN; 2748 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); 2749 /* Configure IPG/IFG parameters. */ 2750 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, 2751 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 2752 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2753 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2754 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 2755 /* Set parameters for half-duplex media. */ 2756 CSR_WRITE_4(sc, ALE_HDPX_CFG, 2757 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2758 HDPX_CFG_LCOL_MASK) | 2759 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2760 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2761 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2762 HDPX_CFG_ABEBT_MASK) | 2763 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2764 HDPX_CFG_JAMIPG_MASK)); 2765 2766 /* Configure Tx jumbo frame parameters. */ 2767 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2768 if (ifp->if_mtu < ETHERMTU) 2769 reg = sc->ale_max_frame_size; 2770 else if (ifp->if_mtu < 6 * 1024) 2771 reg = (sc->ale_max_frame_size * 2) / 3; 2772 else 2773 reg = sc->ale_max_frame_size / 2; 2774 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, 2775 roundup(reg, TX_JUMBO_THRESH_UNIT) >> 2776 TX_JUMBO_THRESH_UNIT_SHIFT); 2777 } 2778 /* Configure TxQ. */ 2779 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) 2780 << TXQ_CFG_TX_FIFO_BURST_SHIFT; 2781 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2782 TXQ_CFG_TPD_BURST_MASK; 2783 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); 2784 2785 /* Configure Rx jumbo frame & flow control parameters. */ 2786 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2787 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); 2788 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, 2789 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << 2790 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | 2791 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & 2792 RX_JUMBO_LKAH_MASK)); 2793 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 2794 rxf_hi = (reg * 7) / 10; 2795 rxf_lo = (reg * 3)/ 10; 2796 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, 2797 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2798 RX_FIFO_PAUSE_THRESH_LO_MASK) | 2799 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2800 RX_FIFO_PAUSE_THRESH_HI_MASK)); 2801 } 2802 2803 /* Disable RSS. */ 2804 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); 2805 CSR_WRITE_4(sc, ALE_RSS_CPU, 0); 2806 2807 /* Configure RxQ. */ 2808 CSR_WRITE_4(sc, ALE_RXQ_CFG, 2809 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2810 2811 /* Configure DMA parameters. */ 2812 reg = 0; 2813 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) 2814 reg |= DMA_CFG_TXCMB_ENB; 2815 CSR_WRITE_4(sc, ALE_DMA_CFG, 2816 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | 2817 sc->ale_dma_rd_burst | reg | 2818 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | 2819 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 2820 DMA_CFG_RD_DELAY_CNT_MASK) | 2821 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 2822 DMA_CFG_WR_DELAY_CNT_MASK)); 2823 2824 /* 2825 * Hardware can be configured to issue SMB interrupt based 2826 * on programmed interval. Since there is a callout that is 2827 * invoked for every hz in driver we use that instead of 2828 * relying on periodic SMB interrupt. 2829 */ 2830 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); 2831 /* Clear MAC statistics. */ 2832 ale_stats_clear(sc); 2833 2834 /* 2835 * Configure Tx/Rx MACs. 2836 * - Auto-padding for short frames. 2837 * - Enable CRC generation. 2838 * Actual reconfiguration of MAC for resolved speed/duplex 2839 * is followed after detection of link establishment. 2840 * AR81xx always does checksum computation regardless of 2841 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will 2842 * cause Rx handling issue for fragmented IP datagrams due 2843 * to silicon bug. 2844 */ 2845 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 2846 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2847 MAC_CFG_PREAMBLE_MASK); 2848 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) 2849 reg |= MAC_CFG_SPEED_10_100; 2850 else 2851 reg |= MAC_CFG_SPEED_1000; 2852 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2853 2854 /* Set up the receive filter. */ 2855 ale_rxfilter(sc); 2856 ale_rxvlan(sc); 2857 2858 /* Acknowledge all pending interrupts and clear it. */ 2859 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); 2860 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2861 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); 2862 2863 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2864 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2865 2866 sc->ale_flags &= ~ALE_FLAG_LINK; 2867 /* Switch to the current media. */ 2868 mii_mediachg(mii); 2869 2870 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2871 } 2872 2873 static void 2874 ale_stop(struct ale_softc *sc) 2875 { 2876 struct ifnet *ifp; 2877 struct ale_txdesc *txd; 2878 uint32_t reg; 2879 int i; 2880 2881 ALE_LOCK_ASSERT(sc); 2882 /* 2883 * Mark the interface down and cancel the watchdog timer. 2884 */ 2885 ifp = sc->ale_ifp; 2886 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2887 sc->ale_flags &= ~ALE_FLAG_LINK; 2888 callout_stop(&sc->ale_tick_ch); 2889 sc->ale_watchdog_timer = 0; 2890 ale_stats_update(sc); 2891 /* Disable interrupts. */ 2892 CSR_WRITE_4(sc, ALE_INTR_MASK, 0); 2893 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2894 /* Disable queue processing and DMA. */ 2895 reg = CSR_READ_4(sc, ALE_TXQ_CFG); 2896 reg &= ~TXQ_CFG_ENB; 2897 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); 2898 reg = CSR_READ_4(sc, ALE_RXQ_CFG); 2899 reg &= ~RXQ_CFG_ENB; 2900 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); 2901 reg = CSR_READ_4(sc, ALE_DMA_CFG); 2902 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); 2903 CSR_WRITE_4(sc, ALE_DMA_CFG, reg); 2904 DELAY(1000); 2905 /* Stop Rx/Tx MACs. */ 2906 ale_stop_mac(sc); 2907 /* Disable interrupts which might be touched in taskq handler. */ 2908 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2909 2910 /* 2911 * Free TX mbufs still in the queues. 2912 */ 2913 for (i = 0; i < ALE_TX_RING_CNT; i++) { 2914 txd = &sc->ale_cdata.ale_txdesc[i]; 2915 if (txd->tx_m != NULL) { 2916 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2917 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2918 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2919 txd->tx_dmamap); 2920 m_freem(txd->tx_m); 2921 txd->tx_m = NULL; 2922 } 2923 } 2924 } 2925 2926 static void 2927 ale_stop_mac(struct ale_softc *sc) 2928 { 2929 uint32_t reg; 2930 int i; 2931 2932 ALE_LOCK_ASSERT(sc); 2933 2934 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2935 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 2936 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 2937 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2938 } 2939 2940 for (i = ALE_TIMEOUT; i > 0; i--) { 2941 reg = CSR_READ_4(sc, ALE_IDLE_STATUS); 2942 if (reg == 0) 2943 break; 2944 DELAY(10); 2945 } 2946 if (i == 0) 2947 device_printf(sc->ale_dev, 2948 "could not disable Tx/Rx MAC(0x%08x)!\n", reg); 2949 } 2950 2951 static void 2952 ale_init_tx_ring(struct ale_softc *sc) 2953 { 2954 struct ale_txdesc *txd; 2955 int i; 2956 2957 ALE_LOCK_ASSERT(sc); 2958 2959 sc->ale_cdata.ale_tx_prod = 0; 2960 sc->ale_cdata.ale_tx_cons = 0; 2961 sc->ale_cdata.ale_tx_cnt = 0; 2962 2963 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ); 2964 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ); 2965 for (i = 0; i < ALE_TX_RING_CNT; i++) { 2966 txd = &sc->ale_cdata.ale_txdesc[i]; 2967 txd->tx_m = NULL; 2968 } 2969 *sc->ale_cdata.ale_tx_cmb = 0; 2970 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2971 sc->ale_cdata.ale_tx_cmb_map, 2972 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2973 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2974 sc->ale_cdata.ale_tx_ring_map, 2975 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2976 } 2977 2978 static void 2979 ale_init_rx_pages(struct ale_softc *sc) 2980 { 2981 struct ale_rx_page *rx_page; 2982 int i; 2983 2984 ALE_LOCK_ASSERT(sc); 2985 2986 sc->ale_morework = 0; 2987 sc->ale_cdata.ale_rx_seqno = 0; 2988 sc->ale_cdata.ale_rx_curp = 0; 2989 2990 for (i = 0; i < ALE_RX_PAGES; i++) { 2991 rx_page = &sc->ale_cdata.ale_rx_page[i]; 2992 bzero(rx_page->page_addr, sc->ale_pagesize); 2993 bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ); 2994 rx_page->cons = 0; 2995 *rx_page->cmb_addr = 0; 2996 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2997 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2998 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2999 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3000 } 3001 } 3002 3003 static void 3004 ale_rxvlan(struct ale_softc *sc) 3005 { 3006 struct ifnet *ifp; 3007 uint32_t reg; 3008 3009 ALE_LOCK_ASSERT(sc); 3010 3011 ifp = sc->ale_ifp; 3012 reg = CSR_READ_4(sc, ALE_MAC_CFG); 3013 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3014 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3015 reg |= MAC_CFG_VLAN_TAG_STRIP; 3016 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 3017 } 3018 3019 static void 3020 ale_rxfilter(struct ale_softc *sc) 3021 { 3022 struct ifnet *ifp; 3023 struct ifmultiaddr *ifma; 3024 uint32_t crc; 3025 uint32_t mchash[2]; 3026 uint32_t rxcfg; 3027 3028 ALE_LOCK_ASSERT(sc); 3029 3030 ifp = sc->ale_ifp; 3031 3032 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); 3033 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3034 if ((ifp->if_flags & IFF_BROADCAST) != 0) 3035 rxcfg |= MAC_CFG_BCAST; 3036 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3037 if ((ifp->if_flags & IFF_PROMISC) != 0) 3038 rxcfg |= MAC_CFG_PROMISC; 3039 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3040 rxcfg |= MAC_CFG_ALLMULTI; 3041 CSR_WRITE_4(sc, ALE_MAR0, 0xFFFFFFFF); 3042 CSR_WRITE_4(sc, ALE_MAR1, 0xFFFFFFFF); 3043 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3044 return; 3045 } 3046 3047 /* Program new filter. */ 3048 bzero(mchash, sizeof(mchash)); 3049 3050 if_maddr_rlock(ifp); 3051 TAILQ_FOREACH(ifma, &sc->ale_ifp->if_multiaddrs, ifma_link) { 3052 if (ifma->ifma_addr->sa_family != AF_LINK) 3053 continue; 3054 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3055 ifma->ifma_addr), ETHER_ADDR_LEN); 3056 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3057 } 3058 if_maddr_runlock(ifp); 3059 3060 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); 3061 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); 3062 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3063 } 3064 3065 static int 3066 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3067 { 3068 int error, value; 3069 3070 if (arg1 == NULL) 3071 return (EINVAL); 3072 value = *(int *)arg1; 3073 error = sysctl_handle_int(oidp, &value, 0, req); 3074 if (error || req->newptr == NULL) 3075 return (error); 3076 if (value < low || value > high) 3077 return (EINVAL); 3078 *(int *)arg1 = value; 3079 3080 return (0); 3081 } 3082 3083 static int 3084 sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS) 3085 { 3086 return (sysctl_int_range(oidp, arg1, arg2, req, 3087 ALE_PROC_MIN, ALE_PROC_MAX)); 3088 } 3089 3090 static int 3091 sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS) 3092 { 3093 3094 return (sysctl_int_range(oidp, arg1, arg2, req, 3095 ALE_IM_TIMER_MIN, ALE_IM_TIMER_MAX)); 3096 } 3097