1 /*- 2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/kernel.h> 38 #include <sys/malloc.h> 39 #include <sys/mbuf.h> 40 #include <sys/module.h> 41 #include <sys/rman.h> 42 #include <sys/queue.h> 43 #include <sys/socket.h> 44 #include <sys/sockio.h> 45 #include <sys/sysctl.h> 46 #include <sys/taskqueue.h> 47 48 #include <net/bpf.h> 49 #include <net/if.h> 50 #include <net/if_arp.h> 51 #include <net/ethernet.h> 52 #include <net/if_dl.h> 53 #include <net/if_llc.h> 54 #include <net/if_media.h> 55 #include <net/if_types.h> 56 #include <net/if_vlan_var.h> 57 58 #include <netinet/in.h> 59 #include <netinet/in_systm.h> 60 #include <netinet/ip.h> 61 #include <netinet/tcp.h> 62 63 #include <dev/mii/mii.h> 64 #include <dev/mii/miivar.h> 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 69 #include <machine/atomic.h> 70 #include <machine/bus.h> 71 #include <machine/in_cksum.h> 72 73 #include <dev/ale/if_alereg.h> 74 #include <dev/ale/if_alevar.h> 75 76 /* "device miibus" required. See GENERIC if you get errors here. */ 77 #include "miibus_if.h" 78 79 /* For more information about Tx checksum offload issues see ale_encap(). */ 80 #define ALE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 81 #ifndef IFCAP_VLAN_HWTSO 82 #define IFCAP_VLAN_HWTSO 0 83 #endif 84 85 MODULE_DEPEND(ale, pci, 1, 1, 1); 86 MODULE_DEPEND(ale, ether, 1, 1, 1); 87 MODULE_DEPEND(ale, miibus, 1, 1, 1); 88 89 /* Tunables. */ 90 static int msi_disable = 0; 91 static int msix_disable = 0; 92 TUNABLE_INT("hw.ale.msi_disable", &msi_disable); 93 TUNABLE_INT("hw.ale.msix_disable", &msix_disable); 94 95 /* 96 * Devices supported by this driver. 97 */ 98 static struct ale_dev { 99 uint16_t ale_vendorid; 100 uint16_t ale_deviceid; 101 const char *ale_name; 102 } ale_devs[] = { 103 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR81XX, 104 "Atheros AR8121/AR8113/AR8114 PCIe Ethernet" }, 105 }; 106 107 static int ale_attach(device_t); 108 static int ale_check_boundary(struct ale_softc *); 109 static int ale_detach(device_t); 110 static int ale_dma_alloc(struct ale_softc *); 111 static void ale_dma_free(struct ale_softc *); 112 static void ale_dmamap_cb(void *, bus_dma_segment_t *, int, int); 113 static int ale_encap(struct ale_softc *, struct mbuf **); 114 static void ale_get_macaddr(struct ale_softc *); 115 static void ale_init(void *); 116 static void ale_init_locked(struct ale_softc *); 117 static void ale_init_rx_pages(struct ale_softc *); 118 static void ale_init_tx_ring(struct ale_softc *); 119 static void ale_int_task(void *, int); 120 static int ale_intr(void *); 121 static int ale_ioctl(struct ifnet *, u_long, caddr_t); 122 static void ale_link_task(void *, int); 123 static void ale_mac_config(struct ale_softc *); 124 static int ale_miibus_readreg(device_t, int, int); 125 static void ale_miibus_statchg(device_t); 126 static int ale_miibus_writereg(device_t, int, int, int); 127 static int ale_mediachange(struct ifnet *); 128 static void ale_mediastatus(struct ifnet *, struct ifmediareq *); 129 static void ale_phy_reset(struct ale_softc *); 130 static int ale_probe(device_t); 131 static void ale_reset(struct ale_softc *); 132 static int ale_resume(device_t); 133 static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, 134 uint32_t, uint32_t *); 135 static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); 136 static int ale_rxeof(struct ale_softc *sc, int); 137 static void ale_rxfilter(struct ale_softc *); 138 static void ale_rxvlan(struct ale_softc *); 139 static void ale_setlinkspeed(struct ale_softc *); 140 static void ale_setwol(struct ale_softc *); 141 static int ale_shutdown(device_t); 142 static void ale_start(struct ifnet *); 143 static void ale_stats_clear(struct ale_softc *); 144 static void ale_stats_update(struct ale_softc *); 145 static void ale_stop(struct ale_softc *); 146 static void ale_stop_mac(struct ale_softc *); 147 static int ale_suspend(device_t); 148 static void ale_sysctl_node(struct ale_softc *); 149 static void ale_tick(void *); 150 static void ale_tx_task(void *, int); 151 static void ale_txeof(struct ale_softc *); 152 static void ale_watchdog(struct ale_softc *); 153 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 154 static int sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS); 155 static int sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS); 156 157 static device_method_t ale_methods[] = { 158 /* Device interface. */ 159 DEVMETHOD(device_probe, ale_probe), 160 DEVMETHOD(device_attach, ale_attach), 161 DEVMETHOD(device_detach, ale_detach), 162 DEVMETHOD(device_shutdown, ale_shutdown), 163 DEVMETHOD(device_suspend, ale_suspend), 164 DEVMETHOD(device_resume, ale_resume), 165 166 /* MII interface. */ 167 DEVMETHOD(miibus_readreg, ale_miibus_readreg), 168 DEVMETHOD(miibus_writereg, ale_miibus_writereg), 169 DEVMETHOD(miibus_statchg, ale_miibus_statchg), 170 171 { NULL, NULL } 172 }; 173 174 static driver_t ale_driver = { 175 "ale", 176 ale_methods, 177 sizeof(struct ale_softc) 178 }; 179 180 static devclass_t ale_devclass; 181 182 DRIVER_MODULE(ale, pci, ale_driver, ale_devclass, 0, 0); 183 DRIVER_MODULE(miibus, ale, miibus_driver, miibus_devclass, 0, 0); 184 185 static struct resource_spec ale_res_spec_mem[] = { 186 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 187 { -1, 0, 0 } 188 }; 189 190 static struct resource_spec ale_irq_spec_legacy[] = { 191 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 192 { -1, 0, 0 } 193 }; 194 195 static struct resource_spec ale_irq_spec_msi[] = { 196 { SYS_RES_IRQ, 1, RF_ACTIVE }, 197 { -1, 0, 0 } 198 }; 199 200 static struct resource_spec ale_irq_spec_msix[] = { 201 { SYS_RES_IRQ, 1, RF_ACTIVE }, 202 { -1, 0, 0 } 203 }; 204 205 static int 206 ale_miibus_readreg(device_t dev, int phy, int reg) 207 { 208 struct ale_softc *sc; 209 uint32_t v; 210 int i; 211 212 sc = device_get_softc(dev); 213 214 if (phy != sc->ale_phyaddr) 215 return (0); 216 217 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 218 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 219 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 220 DELAY(5); 221 v = CSR_READ_4(sc, ALE_MDIO); 222 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 223 break; 224 } 225 226 if (i == 0) { 227 device_printf(sc->ale_dev, "phy read timeout : %d\n", reg); 228 return (0); 229 } 230 231 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 232 } 233 234 static int 235 ale_miibus_writereg(device_t dev, int phy, int reg, int val) 236 { 237 struct ale_softc *sc; 238 uint32_t v; 239 int i; 240 241 sc = device_get_softc(dev); 242 243 if (phy != sc->ale_phyaddr) 244 return (0); 245 246 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 247 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 248 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 249 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 250 DELAY(5); 251 v = CSR_READ_4(sc, ALE_MDIO); 252 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 253 break; 254 } 255 256 if (i == 0) 257 device_printf(sc->ale_dev, "phy write timeout : %d\n", reg); 258 259 return (0); 260 } 261 262 static void 263 ale_miibus_statchg(device_t dev) 264 { 265 struct ale_softc *sc; 266 267 sc = device_get_softc(dev); 268 269 taskqueue_enqueue(taskqueue_swi, &sc->ale_link_task); 270 } 271 272 static void 273 ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 274 { 275 struct ale_softc *sc; 276 struct mii_data *mii; 277 278 sc = ifp->if_softc; 279 ALE_LOCK(sc); 280 mii = device_get_softc(sc->ale_miibus); 281 282 mii_pollstat(mii); 283 ALE_UNLOCK(sc); 284 ifmr->ifm_status = mii->mii_media_status; 285 ifmr->ifm_active = mii->mii_media_active; 286 } 287 288 static int 289 ale_mediachange(struct ifnet *ifp) 290 { 291 struct ale_softc *sc; 292 struct mii_data *mii; 293 struct mii_softc *miisc; 294 int error; 295 296 sc = ifp->if_softc; 297 ALE_LOCK(sc); 298 mii = device_get_softc(sc->ale_miibus); 299 if (mii->mii_instance != 0) { 300 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 301 mii_phy_reset(miisc); 302 } 303 error = mii_mediachg(mii); 304 ALE_UNLOCK(sc); 305 306 return (error); 307 } 308 309 static int 310 ale_probe(device_t dev) 311 { 312 struct ale_dev *sp; 313 int i; 314 uint16_t vendor, devid; 315 316 vendor = pci_get_vendor(dev); 317 devid = pci_get_device(dev); 318 sp = ale_devs; 319 for (i = 0; i < sizeof(ale_devs) / sizeof(ale_devs[0]); i++) { 320 if (vendor == sp->ale_vendorid && 321 devid == sp->ale_deviceid) { 322 device_set_desc(dev, sp->ale_name); 323 return (BUS_PROBE_DEFAULT); 324 } 325 sp++; 326 } 327 328 return (ENXIO); 329 } 330 331 static void 332 ale_get_macaddr(struct ale_softc *sc) 333 { 334 uint32_t ea[2], reg; 335 int i, vpdc; 336 337 reg = CSR_READ_4(sc, ALE_SPI_CTRL); 338 if ((reg & SPI_VPD_ENB) != 0) { 339 reg &= ~SPI_VPD_ENB; 340 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); 341 } 342 343 if (pci_find_extcap(sc->ale_dev, PCIY_VPD, &vpdc) == 0) { 344 /* 345 * PCI VPD capability found, let TWSI reload EEPROM. 346 * This will set ethernet address of controller. 347 */ 348 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | 349 TWSI_CTRL_SW_LD_START); 350 for (i = 100; i > 0; i--) { 351 DELAY(1000); 352 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); 353 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 354 break; 355 } 356 if (i == 0) 357 device_printf(sc->ale_dev, 358 "reloading EEPROM timeout!\n"); 359 } else { 360 if (bootverbose) 361 device_printf(sc->ale_dev, 362 "PCI VPD capability not found!\n"); 363 } 364 365 ea[0] = CSR_READ_4(sc, ALE_PAR0); 366 ea[1] = CSR_READ_4(sc, ALE_PAR1); 367 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; 368 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; 369 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; 370 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; 371 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; 372 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; 373 } 374 375 static void 376 ale_phy_reset(struct ale_softc *sc) 377 { 378 379 /* Reset magic from Linux. */ 380 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 381 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 382 GPHY_CTRL_PHY_PLL_ON); 383 DELAY(1000); 384 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 385 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | 386 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); 387 DELAY(1000); 388 389 #define ATPHY_DBG_ADDR 0x1D 390 #define ATPHY_DBG_DATA 0x1E 391 392 /* Enable hibernation mode. */ 393 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 394 ATPHY_DBG_ADDR, 0x0B); 395 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 396 ATPHY_DBG_DATA, 0xBC00); 397 /* Set Class A/B for all modes. */ 398 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 399 ATPHY_DBG_ADDR, 0x00); 400 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 401 ATPHY_DBG_DATA, 0x02EF); 402 /* Enable 10BT power saving. */ 403 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 404 ATPHY_DBG_ADDR, 0x12); 405 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 406 ATPHY_DBG_DATA, 0x4C04); 407 /* Adjust 1000T power. */ 408 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 409 ATPHY_DBG_ADDR, 0x04); 410 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 411 ATPHY_DBG_ADDR, 0x8BBB); 412 /* 10BT center tap voltage. */ 413 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 414 ATPHY_DBG_ADDR, 0x05); 415 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 416 ATPHY_DBG_ADDR, 0x2C46); 417 418 #undef ATPHY_DBG_ADDR 419 #undef ATPHY_DBG_DATA 420 DELAY(1000); 421 } 422 423 static int 424 ale_attach(device_t dev) 425 { 426 struct ale_softc *sc; 427 struct ifnet *ifp; 428 uint16_t burst; 429 int error, i, msic, msixc, pmc; 430 uint32_t rxf_len, txf_len; 431 432 error = 0; 433 sc = device_get_softc(dev); 434 sc->ale_dev = dev; 435 436 mtx_init(&sc->ale_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 437 MTX_DEF); 438 callout_init_mtx(&sc->ale_tick_ch, &sc->ale_mtx, 0); 439 TASK_INIT(&sc->ale_int_task, 0, ale_int_task, sc); 440 TASK_INIT(&sc->ale_link_task, 0, ale_link_task, sc); 441 442 /* Map the device. */ 443 pci_enable_busmaster(dev); 444 sc->ale_res_spec = ale_res_spec_mem; 445 sc->ale_irq_spec = ale_irq_spec_legacy; 446 error = bus_alloc_resources(dev, sc->ale_res_spec, sc->ale_res); 447 if (error != 0) { 448 device_printf(dev, "cannot allocate memory resources.\n"); 449 goto fail; 450 } 451 452 /* Set PHY address. */ 453 sc->ale_phyaddr = ALE_PHY_ADDR; 454 455 /* Reset PHY. */ 456 ale_phy_reset(sc); 457 458 /* Reset the ethernet controller. */ 459 ale_reset(sc); 460 461 /* Get PCI and chip id/revision. */ 462 sc->ale_rev = pci_get_revid(dev); 463 if (sc->ale_rev >= 0xF0) { 464 /* L2E Rev. B. AR8114 */ 465 sc->ale_flags |= ALE_FLAG_FASTETHER; 466 } else { 467 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { 468 /* L1E AR8121 */ 469 sc->ale_flags |= ALE_FLAG_JUMBO; 470 } else { 471 /* L2E Rev. A. AR8113 */ 472 sc->ale_flags |= ALE_FLAG_FASTETHER; 473 } 474 } 475 /* 476 * All known controllers seems to require 4 bytes alignment 477 * of Tx buffers to make Tx checksum offload with custom 478 * checksum generation method work. 479 */ 480 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; 481 /* 482 * All known controllers seems to have issues on Rx checksum 483 * offload for fragmented IP datagrams. 484 */ 485 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; 486 /* 487 * Don't use Tx CMB. It is known to cause RRS update failure 488 * under certain circumstances. Typical phenomenon of the 489 * issue would be unexpected sequence number encountered in 490 * Rx handler. 491 */ 492 sc->ale_flags |= ALE_FLAG_TXCMB_BUG; 493 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> 494 MASTER_CHIP_REV_SHIFT; 495 if (bootverbose) { 496 device_printf(dev, "PCI device revision : 0x%04x\n", 497 sc->ale_rev); 498 device_printf(dev, "Chip id/revision : 0x%04x\n", 499 sc->ale_chip_rev); 500 } 501 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); 502 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 503 /* 504 * Uninitialized hardware returns an invalid chip id/revision 505 * as well as 0xFFFFFFFF for Tx/Rx fifo length. 506 */ 507 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || 508 rxf_len == 0xFFFFFFF) { 509 device_printf(dev,"chip revision : 0x%04x, %u Tx FIFO " 510 "%u Rx FIFO -- not initialized?\n", sc->ale_chip_rev, 511 txf_len, rxf_len); 512 error = ENXIO; 513 goto fail; 514 } 515 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", txf_len, rxf_len); 516 517 /* Allocate IRQ resources. */ 518 msixc = pci_msix_count(dev); 519 msic = pci_msi_count(dev); 520 if (bootverbose) { 521 device_printf(dev, "MSIX count : %d\n", msixc); 522 device_printf(dev, "MSI count : %d\n", msic); 523 } 524 525 /* Prefer MSIX over MSI. */ 526 if (msix_disable == 0 || msi_disable == 0) { 527 if (msix_disable == 0 && msixc == ALE_MSIX_MESSAGES && 528 pci_alloc_msix(dev, &msixc) == 0) { 529 if (msic == ALE_MSIX_MESSAGES) { 530 device_printf(dev, "Using %d MSIX messages.\n", 531 msixc); 532 sc->ale_flags |= ALE_FLAG_MSIX; 533 sc->ale_irq_spec = ale_irq_spec_msix; 534 } else 535 pci_release_msi(dev); 536 } 537 if (msi_disable == 0 && (sc->ale_flags & ALE_FLAG_MSIX) == 0 && 538 msic == ALE_MSI_MESSAGES && 539 pci_alloc_msi(dev, &msic) == 0) { 540 if (msic == ALE_MSI_MESSAGES) { 541 device_printf(dev, "Using %d MSI messages.\n", 542 msic); 543 sc->ale_flags |= ALE_FLAG_MSI; 544 sc->ale_irq_spec = ale_irq_spec_msi; 545 } else 546 pci_release_msi(dev); 547 } 548 } 549 550 error = bus_alloc_resources(dev, sc->ale_irq_spec, sc->ale_irq); 551 if (error != 0) { 552 device_printf(dev, "cannot allocate IRQ resources.\n"); 553 goto fail; 554 } 555 556 /* Get DMA parameters from PCIe device control register. */ 557 if (pci_find_extcap(dev, PCIY_EXPRESS, &i) == 0) { 558 sc->ale_flags |= ALE_FLAG_PCIE; 559 burst = pci_read_config(dev, i + 0x08, 2); 560 /* Max read request size. */ 561 sc->ale_dma_rd_burst = ((burst >> 12) & 0x07) << 562 DMA_CFG_RD_BURST_SHIFT; 563 /* Max payload size. */ 564 sc->ale_dma_wr_burst = ((burst >> 5) & 0x07) << 565 DMA_CFG_WR_BURST_SHIFT; 566 if (bootverbose) { 567 device_printf(dev, "Read request size : %d bytes.\n", 568 128 << ((burst >> 12) & 0x07)); 569 device_printf(dev, "TLP payload size : %d bytes.\n", 570 128 << ((burst >> 5) & 0x07)); 571 } 572 } else { 573 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; 574 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; 575 } 576 577 /* Create device sysctl node. */ 578 ale_sysctl_node(sc); 579 580 if ((error = ale_dma_alloc(sc) != 0)) 581 goto fail; 582 583 /* Load station address. */ 584 ale_get_macaddr(sc); 585 586 ifp = sc->ale_ifp = if_alloc(IFT_ETHER); 587 if (ifp == NULL) { 588 device_printf(dev, "cannot allocate ifnet structure.\n"); 589 error = ENXIO; 590 goto fail; 591 } 592 593 ifp->if_softc = sc; 594 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 595 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 596 ifp->if_ioctl = ale_ioctl; 597 ifp->if_start = ale_start; 598 ifp->if_init = ale_init; 599 ifp->if_snd.ifq_drv_maxlen = ALE_TX_RING_CNT - 1; 600 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 601 IFQ_SET_READY(&ifp->if_snd); 602 ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4; 603 ifp->if_hwassist = ALE_CSUM_FEATURES | CSUM_TSO; 604 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) { 605 sc->ale_flags |= ALE_FLAG_PMCAP; 606 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 607 } 608 ifp->if_capenable = ifp->if_capabilities; 609 610 /* Set up MII bus. */ 611 if ((error = mii_phy_probe(dev, &sc->ale_miibus, ale_mediachange, 612 ale_mediastatus)) != 0) { 613 device_printf(dev, "no PHY found!\n"); 614 goto fail; 615 } 616 617 ether_ifattach(ifp, sc->ale_eaddr); 618 619 /* VLAN capability setup. */ 620 ifp->if_capabilities |= IFCAP_VLAN_MTU; 621 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM; 622 ifp->if_capenable = ifp->if_capabilities; 623 /* 624 * Even though controllers supported by ale(3) have Rx checksum 625 * offload bug the workaround for fragmented frames seemed to 626 * work so far. However it seems Rx checksum offload does not 627 * work under certain conditions. So disable Rx checksum offload 628 * until I find more clue about it but allow users to override it. 629 */ 630 ifp->if_capenable &= ~IFCAP_RXCSUM; 631 632 /* Tell the upper layer(s) we support long frames. */ 633 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 634 635 /* Create local taskq. */ 636 TASK_INIT(&sc->ale_tx_task, 1, ale_tx_task, ifp); 637 sc->ale_tq = taskqueue_create_fast("ale_taskq", M_WAITOK, 638 taskqueue_thread_enqueue, &sc->ale_tq); 639 if (sc->ale_tq == NULL) { 640 device_printf(dev, "could not create taskqueue.\n"); 641 ether_ifdetach(ifp); 642 error = ENXIO; 643 goto fail; 644 } 645 taskqueue_start_threads(&sc->ale_tq, 1, PI_NET, "%s taskq", 646 device_get_nameunit(sc->ale_dev)); 647 648 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 649 msic = ALE_MSIX_MESSAGES; 650 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 651 msic = ALE_MSI_MESSAGES; 652 else 653 msic = 1; 654 for (i = 0; i < msic; i++) { 655 error = bus_setup_intr(dev, sc->ale_irq[i], 656 INTR_TYPE_NET | INTR_MPSAFE, ale_intr, NULL, sc, 657 &sc->ale_intrhand[i]); 658 if (error != 0) 659 break; 660 } 661 if (error != 0) { 662 device_printf(dev, "could not set up interrupt handler.\n"); 663 taskqueue_free(sc->ale_tq); 664 sc->ale_tq = NULL; 665 ether_ifdetach(ifp); 666 goto fail; 667 } 668 669 fail: 670 if (error != 0) 671 ale_detach(dev); 672 673 return (error); 674 } 675 676 static int 677 ale_detach(device_t dev) 678 { 679 struct ale_softc *sc; 680 struct ifnet *ifp; 681 int i, msic; 682 683 sc = device_get_softc(dev); 684 685 ifp = sc->ale_ifp; 686 if (device_is_attached(dev)) { 687 ALE_LOCK(sc); 688 sc->ale_flags |= ALE_FLAG_DETACH; 689 ale_stop(sc); 690 ALE_UNLOCK(sc); 691 callout_drain(&sc->ale_tick_ch); 692 taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 693 taskqueue_drain(sc->ale_tq, &sc->ale_tx_task); 694 taskqueue_drain(taskqueue_swi, &sc->ale_link_task); 695 ether_ifdetach(ifp); 696 } 697 698 if (sc->ale_tq != NULL) { 699 taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 700 taskqueue_free(sc->ale_tq); 701 sc->ale_tq = NULL; 702 } 703 704 if (sc->ale_miibus != NULL) { 705 device_delete_child(dev, sc->ale_miibus); 706 sc->ale_miibus = NULL; 707 } 708 bus_generic_detach(dev); 709 ale_dma_free(sc); 710 711 if (ifp != NULL) { 712 if_free(ifp); 713 sc->ale_ifp = NULL; 714 } 715 716 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 717 msic = ALE_MSIX_MESSAGES; 718 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 719 msic = ALE_MSI_MESSAGES; 720 else 721 msic = 1; 722 for (i = 0; i < msic; i++) { 723 if (sc->ale_intrhand[i] != NULL) { 724 bus_teardown_intr(dev, sc->ale_irq[i], 725 sc->ale_intrhand[i]); 726 sc->ale_intrhand[i] = NULL; 727 } 728 } 729 730 bus_release_resources(dev, sc->ale_irq_spec, sc->ale_irq); 731 if ((sc->ale_flags & (ALE_FLAG_MSI | ALE_FLAG_MSIX)) != 0) 732 pci_release_msi(dev); 733 bus_release_resources(dev, sc->ale_res_spec, sc->ale_res); 734 mtx_destroy(&sc->ale_mtx); 735 736 return (0); 737 } 738 739 #define ALE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 740 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 741 742 #if __FreeBSD_version > 800000 743 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 744 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 745 #else 746 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 747 SYSCTL_ADD_ULONG(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 748 #endif 749 750 static void 751 ale_sysctl_node(struct ale_softc *sc) 752 { 753 struct sysctl_ctx_list *ctx; 754 struct sysctl_oid_list *child, *parent; 755 struct sysctl_oid *tree; 756 struct ale_hw_stats *stats; 757 int error; 758 759 stats = &sc->ale_stats; 760 ctx = device_get_sysctl_ctx(sc->ale_dev); 761 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ale_dev)); 762 763 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 764 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_rx_mod, 0, 765 sysctl_hw_ale_int_mod, "I", "ale Rx interrupt moderation"); 766 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 767 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_tx_mod, 0, 768 sysctl_hw_ale_int_mod, "I", "ale Tx interrupt moderation"); 769 /* Pull in device tunables. */ 770 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 771 error = resource_int_value(device_get_name(sc->ale_dev), 772 device_get_unit(sc->ale_dev), "int_rx_mod", &sc->ale_int_rx_mod); 773 if (error == 0) { 774 if (sc->ale_int_rx_mod < ALE_IM_TIMER_MIN || 775 sc->ale_int_rx_mod > ALE_IM_TIMER_MAX) { 776 device_printf(sc->ale_dev, "int_rx_mod value out of " 777 "range; using default: %d\n", 778 ALE_IM_RX_TIMER_DEFAULT); 779 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 780 } 781 } 782 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 783 error = resource_int_value(device_get_name(sc->ale_dev), 784 device_get_unit(sc->ale_dev), "int_tx_mod", &sc->ale_int_tx_mod); 785 if (error == 0) { 786 if (sc->ale_int_tx_mod < ALE_IM_TIMER_MIN || 787 sc->ale_int_tx_mod > ALE_IM_TIMER_MAX) { 788 device_printf(sc->ale_dev, "int_tx_mod value out of " 789 "range; using default: %d\n", 790 ALE_IM_TX_TIMER_DEFAULT); 791 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 792 } 793 } 794 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 795 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_process_limit, 0, 796 sysctl_hw_ale_proc_limit, "I", 797 "max number of Rx events to process"); 798 /* Pull in device tunables. */ 799 sc->ale_process_limit = ALE_PROC_DEFAULT; 800 error = resource_int_value(device_get_name(sc->ale_dev), 801 device_get_unit(sc->ale_dev), "process_limit", 802 &sc->ale_process_limit); 803 if (error == 0) { 804 if (sc->ale_process_limit < ALE_PROC_MIN || 805 sc->ale_process_limit > ALE_PROC_MAX) { 806 device_printf(sc->ale_dev, 807 "process_limit value out of range; " 808 "using default: %d\n", ALE_PROC_DEFAULT); 809 sc->ale_process_limit = ALE_PROC_DEFAULT; 810 } 811 } 812 813 /* Misc statistics. */ 814 ALE_SYSCTL_STAT_ADD32(ctx, child, "reset_brk_seq", 815 &stats->reset_brk_seq, 816 "Controller resets due to broken Rx sequnce number"); 817 818 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 819 NULL, "ATE statistics"); 820 parent = SYSCTL_CHILDREN(tree); 821 822 /* Rx statistics. */ 823 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 824 NULL, "Rx MAC statistics"); 825 child = SYSCTL_CHILDREN(tree); 826 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 827 &stats->rx_frames, "Good frames"); 828 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 829 &stats->rx_bcast_frames, "Good broadcast frames"); 830 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 831 &stats->rx_mcast_frames, "Good multicast frames"); 832 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 833 &stats->rx_pause_frames, "Pause control frames"); 834 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 835 &stats->rx_control_frames, "Control frames"); 836 ALE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 837 &stats->rx_crcerrs, "CRC errors"); 838 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 839 &stats->rx_lenerrs, "Frames with length mismatched"); 840 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 841 &stats->rx_bytes, "Good octets"); 842 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 843 &stats->rx_bcast_bytes, "Good broadcast octets"); 844 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 845 &stats->rx_mcast_bytes, "Good multicast octets"); 846 ALE_SYSCTL_STAT_ADD32(ctx, child, "runts", 847 &stats->rx_runts, "Too short frames"); 848 ALE_SYSCTL_STAT_ADD32(ctx, child, "fragments", 849 &stats->rx_fragments, "Fragmented frames"); 850 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 851 &stats->rx_pkts_64, "64 bytes frames"); 852 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 853 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 854 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 855 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 856 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 857 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 858 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 859 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 860 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 861 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 862 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 863 &stats->rx_pkts_1519_max, "1519 to max frames"); 864 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 865 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 866 ALE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 867 &stats->rx_fifo_oflows, "FIFO overflows"); 868 ALE_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 869 &stats->rx_rrs_errs, "Return status write-back errors"); 870 ALE_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 871 &stats->rx_alignerrs, "Alignment errors"); 872 ALE_SYSCTL_STAT_ADD32(ctx, child, "filtered", 873 &stats->rx_pkts_filtered, 874 "Frames dropped due to address filtering"); 875 876 /* Tx statistics. */ 877 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 878 NULL, "Tx MAC statistics"); 879 child = SYSCTL_CHILDREN(tree); 880 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 881 &stats->tx_frames, "Good frames"); 882 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 883 &stats->tx_bcast_frames, "Good broadcast frames"); 884 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 885 &stats->tx_mcast_frames, "Good multicast frames"); 886 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 887 &stats->tx_pause_frames, "Pause control frames"); 888 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 889 &stats->tx_control_frames, "Control frames"); 890 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 891 &stats->tx_excess_defer, "Frames with excessive derferrals"); 892 ALE_SYSCTL_STAT_ADD32(ctx, child, "defers", 893 &stats->tx_excess_defer, "Frames with derferrals"); 894 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 895 &stats->tx_bytes, "Good octets"); 896 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 897 &stats->tx_bcast_bytes, "Good broadcast octets"); 898 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 899 &stats->tx_mcast_bytes, "Good multicast octets"); 900 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 901 &stats->tx_pkts_64, "64 bytes frames"); 902 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 903 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 904 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 905 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 906 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 907 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 908 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 909 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 910 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 911 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 912 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 913 &stats->tx_pkts_1519_max, "1519 to max frames"); 914 ALE_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 915 &stats->tx_single_colls, "Single collisions"); 916 ALE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 917 &stats->tx_multi_colls, "Multiple collisions"); 918 ALE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 919 &stats->tx_late_colls, "Late collisions"); 920 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 921 &stats->tx_excess_colls, "Excessive collisions"); 922 ALE_SYSCTL_STAT_ADD32(ctx, child, "abort", 923 &stats->tx_abort, "Aborted frames due to Excessive collisions"); 924 ALE_SYSCTL_STAT_ADD32(ctx, child, "underruns", 925 &stats->tx_underrun, "FIFO underruns"); 926 ALE_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 927 &stats->tx_desc_underrun, "Descriptor write-back errors"); 928 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 929 &stats->tx_lenerrs, "Frames with length mismatched"); 930 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 931 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 932 } 933 934 #undef ALE_SYSCTL_STAT_ADD32 935 #undef ALE_SYSCTL_STAT_ADD64 936 937 struct ale_dmamap_arg { 938 bus_addr_t ale_busaddr; 939 }; 940 941 static void 942 ale_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 943 { 944 struct ale_dmamap_arg *ctx; 945 946 if (error != 0) 947 return; 948 949 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 950 951 ctx = (struct ale_dmamap_arg *)arg; 952 ctx->ale_busaddr = segs[0].ds_addr; 953 } 954 955 /* 956 * Tx descriptors/RXF0/CMB DMA blocks share ALE_DESC_ADDR_HI register 957 * which specifies high address region of DMA blocks. Therefore these 958 * blocks should have the same high address of given 4GB address 959 * space(i.e. crossing 4GB boundary is not allowed). 960 */ 961 static int 962 ale_check_boundary(struct ale_softc *sc) 963 { 964 bus_addr_t rx_cmb_end[ALE_RX_PAGES], tx_cmb_end; 965 bus_addr_t rx_page_end[ALE_RX_PAGES], tx_ring_end; 966 967 rx_page_end[0] = sc->ale_cdata.ale_rx_page[0].page_paddr + 968 sc->ale_pagesize; 969 rx_page_end[1] = sc->ale_cdata.ale_rx_page[1].page_paddr + 970 sc->ale_pagesize; 971 tx_ring_end = sc->ale_cdata.ale_tx_ring_paddr + ALE_TX_RING_SZ; 972 tx_cmb_end = sc->ale_cdata.ale_tx_cmb_paddr + ALE_TX_CMB_SZ; 973 rx_cmb_end[0] = sc->ale_cdata.ale_rx_page[0].cmb_paddr + ALE_RX_CMB_SZ; 974 rx_cmb_end[1] = sc->ale_cdata.ale_rx_page[1].cmb_paddr + ALE_RX_CMB_SZ; 975 976 if ((ALE_ADDR_HI(tx_ring_end) != 977 ALE_ADDR_HI(sc->ale_cdata.ale_tx_ring_paddr)) || 978 (ALE_ADDR_HI(rx_page_end[0]) != 979 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].page_paddr)) || 980 (ALE_ADDR_HI(rx_page_end[1]) != 981 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].page_paddr)) || 982 (ALE_ADDR_HI(tx_cmb_end) != 983 ALE_ADDR_HI(sc->ale_cdata.ale_tx_cmb_paddr)) || 984 (ALE_ADDR_HI(rx_cmb_end[0]) != 985 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].cmb_paddr)) || 986 (ALE_ADDR_HI(rx_cmb_end[1]) != 987 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].cmb_paddr))) 988 return (EFBIG); 989 990 if ((ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[0])) || 991 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[1])) || 992 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[0])) || 993 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[1])) || 994 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(tx_cmb_end))) 995 return (EFBIG); 996 997 return (0); 998 } 999 1000 static int 1001 ale_dma_alloc(struct ale_softc *sc) 1002 { 1003 struct ale_txdesc *txd; 1004 bus_addr_t lowaddr; 1005 struct ale_dmamap_arg ctx; 1006 int error, guard_size, i; 1007 1008 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 1009 guard_size = ALE_JUMBO_FRAMELEN; 1010 else 1011 guard_size = ALE_MAX_FRAMELEN; 1012 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, 1013 ALE_RX_PAGE_ALIGN); 1014 lowaddr = BUS_SPACE_MAXADDR; 1015 again: 1016 /* Create parent DMA tag. */ 1017 error = bus_dma_tag_create( 1018 bus_get_dma_tag(sc->ale_dev), /* parent */ 1019 1, 0, /* alignment, boundary */ 1020 lowaddr, /* lowaddr */ 1021 BUS_SPACE_MAXADDR, /* highaddr */ 1022 NULL, NULL, /* filter, filterarg */ 1023 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1024 0, /* nsegments */ 1025 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1026 0, /* flags */ 1027 NULL, NULL, /* lockfunc, lockarg */ 1028 &sc->ale_cdata.ale_parent_tag); 1029 if (error != 0) { 1030 device_printf(sc->ale_dev, 1031 "could not create parent DMA tag.\n"); 1032 goto fail; 1033 } 1034 1035 /* Create DMA tag for Tx descriptor ring. */ 1036 error = bus_dma_tag_create( 1037 sc->ale_cdata.ale_parent_tag, /* parent */ 1038 ALE_TX_RING_ALIGN, 0, /* alignment, boundary */ 1039 BUS_SPACE_MAXADDR, /* lowaddr */ 1040 BUS_SPACE_MAXADDR, /* highaddr */ 1041 NULL, NULL, /* filter, filterarg */ 1042 ALE_TX_RING_SZ, /* maxsize */ 1043 1, /* nsegments */ 1044 ALE_TX_RING_SZ, /* maxsegsize */ 1045 0, /* flags */ 1046 NULL, NULL, /* lockfunc, lockarg */ 1047 &sc->ale_cdata.ale_tx_ring_tag); 1048 if (error != 0) { 1049 device_printf(sc->ale_dev, 1050 "could not create Tx ring DMA tag.\n"); 1051 goto fail; 1052 } 1053 1054 /* Create DMA tag for Rx pages. */ 1055 for (i = 0; i < ALE_RX_PAGES; i++) { 1056 error = bus_dma_tag_create( 1057 sc->ale_cdata.ale_parent_tag, /* parent */ 1058 ALE_RX_PAGE_ALIGN, 0, /* alignment, boundary */ 1059 BUS_SPACE_MAXADDR, /* lowaddr */ 1060 BUS_SPACE_MAXADDR, /* highaddr */ 1061 NULL, NULL, /* filter, filterarg */ 1062 sc->ale_pagesize, /* maxsize */ 1063 1, /* nsegments */ 1064 sc->ale_pagesize, /* maxsegsize */ 1065 0, /* flags */ 1066 NULL, NULL, /* lockfunc, lockarg */ 1067 &sc->ale_cdata.ale_rx_page[i].page_tag); 1068 if (error != 0) { 1069 device_printf(sc->ale_dev, 1070 "could not create Rx page %d DMA tag.\n", i); 1071 goto fail; 1072 } 1073 } 1074 1075 /* Create DMA tag for Tx coalescing message block. */ 1076 error = bus_dma_tag_create( 1077 sc->ale_cdata.ale_parent_tag, /* parent */ 1078 ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1079 BUS_SPACE_MAXADDR, /* lowaddr */ 1080 BUS_SPACE_MAXADDR, /* highaddr */ 1081 NULL, NULL, /* filter, filterarg */ 1082 ALE_TX_CMB_SZ, /* maxsize */ 1083 1, /* nsegments */ 1084 ALE_TX_CMB_SZ, /* maxsegsize */ 1085 0, /* flags */ 1086 NULL, NULL, /* lockfunc, lockarg */ 1087 &sc->ale_cdata.ale_tx_cmb_tag); 1088 if (error != 0) { 1089 device_printf(sc->ale_dev, 1090 "could not create Tx CMB DMA tag.\n"); 1091 goto fail; 1092 } 1093 1094 /* Create DMA tag for Rx coalescing message block. */ 1095 for (i = 0; i < ALE_RX_PAGES; i++) { 1096 error = bus_dma_tag_create( 1097 sc->ale_cdata.ale_parent_tag, /* parent */ 1098 ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1099 BUS_SPACE_MAXADDR, /* lowaddr */ 1100 BUS_SPACE_MAXADDR, /* highaddr */ 1101 NULL, NULL, /* filter, filterarg */ 1102 ALE_RX_CMB_SZ, /* maxsize */ 1103 1, /* nsegments */ 1104 ALE_RX_CMB_SZ, /* maxsegsize */ 1105 0, /* flags */ 1106 NULL, NULL, /* lockfunc, lockarg */ 1107 &sc->ale_cdata.ale_rx_page[i].cmb_tag); 1108 if (error != 0) { 1109 device_printf(sc->ale_dev, 1110 "could not create Rx page %d CMB DMA tag.\n", i); 1111 goto fail; 1112 } 1113 } 1114 1115 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1116 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_ring_tag, 1117 (void **)&sc->ale_cdata.ale_tx_ring, 1118 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1119 &sc->ale_cdata.ale_tx_ring_map); 1120 if (error != 0) { 1121 device_printf(sc->ale_dev, 1122 "could not allocate DMA'able memory for Tx ring.\n"); 1123 goto fail; 1124 } 1125 ctx.ale_busaddr = 0; 1126 error = bus_dmamap_load(sc->ale_cdata.ale_tx_ring_tag, 1127 sc->ale_cdata.ale_tx_ring_map, sc->ale_cdata.ale_tx_ring, 1128 ALE_TX_RING_SZ, ale_dmamap_cb, &ctx, 0); 1129 if (error != 0 || ctx.ale_busaddr == 0) { 1130 device_printf(sc->ale_dev, 1131 "could not load DMA'able memory for Tx ring.\n"); 1132 goto fail; 1133 } 1134 sc->ale_cdata.ale_tx_ring_paddr = ctx.ale_busaddr; 1135 1136 /* Rx pages. */ 1137 for (i = 0; i < ALE_RX_PAGES; i++) { 1138 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].page_tag, 1139 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr, 1140 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1141 &sc->ale_cdata.ale_rx_page[i].page_map); 1142 if (error != 0) { 1143 device_printf(sc->ale_dev, 1144 "could not allocate DMA'able memory for " 1145 "Rx page %d.\n", i); 1146 goto fail; 1147 } 1148 ctx.ale_busaddr = 0; 1149 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].page_tag, 1150 sc->ale_cdata.ale_rx_page[i].page_map, 1151 sc->ale_cdata.ale_rx_page[i].page_addr, 1152 sc->ale_pagesize, ale_dmamap_cb, &ctx, 0); 1153 if (error != 0 || ctx.ale_busaddr == 0) { 1154 device_printf(sc->ale_dev, 1155 "could not load DMA'able memory for " 1156 "Rx page %d.\n", i); 1157 goto fail; 1158 } 1159 sc->ale_cdata.ale_rx_page[i].page_paddr = ctx.ale_busaddr; 1160 } 1161 1162 /* Tx CMB. */ 1163 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_cmb_tag, 1164 (void **)&sc->ale_cdata.ale_tx_cmb, 1165 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1166 &sc->ale_cdata.ale_tx_cmb_map); 1167 if (error != 0) { 1168 device_printf(sc->ale_dev, 1169 "could not allocate DMA'able memory for Tx CMB.\n"); 1170 goto fail; 1171 } 1172 ctx.ale_busaddr = 0; 1173 error = bus_dmamap_load(sc->ale_cdata.ale_tx_cmb_tag, 1174 sc->ale_cdata.ale_tx_cmb_map, sc->ale_cdata.ale_tx_cmb, 1175 ALE_TX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1176 if (error != 0 || ctx.ale_busaddr == 0) { 1177 device_printf(sc->ale_dev, 1178 "could not load DMA'able memory for Tx CMB.\n"); 1179 goto fail; 1180 } 1181 sc->ale_cdata.ale_tx_cmb_paddr = ctx.ale_busaddr; 1182 1183 /* Rx CMB. */ 1184 for (i = 0; i < ALE_RX_PAGES; i++) { 1185 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1186 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 1187 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1188 &sc->ale_cdata.ale_rx_page[i].cmb_map); 1189 if (error != 0) { 1190 device_printf(sc->ale_dev, "could not allocate " 1191 "DMA'able memory for Rx page %d CMB.\n", i); 1192 goto fail; 1193 } 1194 ctx.ale_busaddr = 0; 1195 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1196 sc->ale_cdata.ale_rx_page[i].cmb_map, 1197 sc->ale_cdata.ale_rx_page[i].cmb_addr, 1198 ALE_RX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1199 if (error != 0 || ctx.ale_busaddr == 0) { 1200 device_printf(sc->ale_dev, "could not load DMA'able " 1201 "memory for Rx page %d CMB.\n", i); 1202 goto fail; 1203 } 1204 sc->ale_cdata.ale_rx_page[i].cmb_paddr = ctx.ale_busaddr; 1205 } 1206 1207 /* 1208 * Tx descriptors/RXF0/CMB DMA blocks share the same 1209 * high address region of 64bit DMA address space. 1210 */ 1211 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1212 (error = ale_check_boundary(sc)) != 0) { 1213 device_printf(sc->ale_dev, "4GB boundary crossed, " 1214 "switching to 32bit DMA addressing mode.\n"); 1215 ale_dma_free(sc); 1216 /* 1217 * Limit max allowable DMA address space to 32bit 1218 * and try again. 1219 */ 1220 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1221 goto again; 1222 } 1223 1224 /* 1225 * Create Tx buffer parent tag. 1226 * AR81xx allows 64bit DMA addressing of Tx buffers so it 1227 * needs separate parent DMA tag as parent DMA address space 1228 * could be restricted to be within 32bit address space by 1229 * 4GB boundary crossing. 1230 */ 1231 error = bus_dma_tag_create( 1232 bus_get_dma_tag(sc->ale_dev), /* parent */ 1233 1, 0, /* alignment, boundary */ 1234 BUS_SPACE_MAXADDR, /* lowaddr */ 1235 BUS_SPACE_MAXADDR, /* highaddr */ 1236 NULL, NULL, /* filter, filterarg */ 1237 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1238 0, /* nsegments */ 1239 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1240 0, /* flags */ 1241 NULL, NULL, /* lockfunc, lockarg */ 1242 &sc->ale_cdata.ale_buffer_tag); 1243 if (error != 0) { 1244 device_printf(sc->ale_dev, 1245 "could not create parent buffer DMA tag.\n"); 1246 goto fail; 1247 } 1248 1249 /* Create DMA tag for Tx buffers. */ 1250 error = bus_dma_tag_create( 1251 sc->ale_cdata.ale_buffer_tag, /* parent */ 1252 1, 0, /* alignment, boundary */ 1253 BUS_SPACE_MAXADDR, /* lowaddr */ 1254 BUS_SPACE_MAXADDR, /* highaddr */ 1255 NULL, NULL, /* filter, filterarg */ 1256 ALE_TSO_MAXSIZE, /* maxsize */ 1257 ALE_MAXTXSEGS, /* nsegments */ 1258 ALE_TSO_MAXSEGSIZE, /* maxsegsize */ 1259 0, /* flags */ 1260 NULL, NULL, /* lockfunc, lockarg */ 1261 &sc->ale_cdata.ale_tx_tag); 1262 if (error != 0) { 1263 device_printf(sc->ale_dev, "could not create Tx DMA tag.\n"); 1264 goto fail; 1265 } 1266 1267 /* Create DMA maps for Tx buffers. */ 1268 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1269 txd = &sc->ale_cdata.ale_txdesc[i]; 1270 txd->tx_m = NULL; 1271 txd->tx_dmamap = NULL; 1272 error = bus_dmamap_create(sc->ale_cdata.ale_tx_tag, 0, 1273 &txd->tx_dmamap); 1274 if (error != 0) { 1275 device_printf(sc->ale_dev, 1276 "could not create Tx dmamap.\n"); 1277 goto fail; 1278 } 1279 } 1280 1281 fail: 1282 return (error); 1283 } 1284 1285 static void 1286 ale_dma_free(struct ale_softc *sc) 1287 { 1288 struct ale_txdesc *txd; 1289 int i; 1290 1291 /* Tx buffers. */ 1292 if (sc->ale_cdata.ale_tx_tag != NULL) { 1293 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1294 txd = &sc->ale_cdata.ale_txdesc[i]; 1295 if (txd->tx_dmamap != NULL) { 1296 bus_dmamap_destroy(sc->ale_cdata.ale_tx_tag, 1297 txd->tx_dmamap); 1298 txd->tx_dmamap = NULL; 1299 } 1300 } 1301 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_tag); 1302 sc->ale_cdata.ale_tx_tag = NULL; 1303 } 1304 /* Tx descriptor ring. */ 1305 if (sc->ale_cdata.ale_tx_ring_tag != NULL) { 1306 if (sc->ale_cdata.ale_tx_ring_map != NULL) 1307 bus_dmamap_unload(sc->ale_cdata.ale_tx_ring_tag, 1308 sc->ale_cdata.ale_tx_ring_map); 1309 if (sc->ale_cdata.ale_tx_ring_map != NULL && 1310 sc->ale_cdata.ale_tx_ring != NULL) 1311 bus_dmamem_free(sc->ale_cdata.ale_tx_ring_tag, 1312 sc->ale_cdata.ale_tx_ring, 1313 sc->ale_cdata.ale_tx_ring_map); 1314 sc->ale_cdata.ale_tx_ring = NULL; 1315 sc->ale_cdata.ale_tx_ring_map = NULL; 1316 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_ring_tag); 1317 sc->ale_cdata.ale_tx_ring_tag = NULL; 1318 } 1319 /* Rx page block. */ 1320 for (i = 0; i < ALE_RX_PAGES; i++) { 1321 if (sc->ale_cdata.ale_rx_page[i].page_tag != NULL) { 1322 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL) 1323 bus_dmamap_unload( 1324 sc->ale_cdata.ale_rx_page[i].page_tag, 1325 sc->ale_cdata.ale_rx_page[i].page_map); 1326 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL && 1327 sc->ale_cdata.ale_rx_page[i].page_addr != NULL) 1328 bus_dmamem_free( 1329 sc->ale_cdata.ale_rx_page[i].page_tag, 1330 sc->ale_cdata.ale_rx_page[i].page_addr, 1331 sc->ale_cdata.ale_rx_page[i].page_map); 1332 sc->ale_cdata.ale_rx_page[i].page_addr = NULL; 1333 sc->ale_cdata.ale_rx_page[i].page_map = NULL; 1334 bus_dma_tag_destroy( 1335 sc->ale_cdata.ale_rx_page[i].page_tag); 1336 sc->ale_cdata.ale_rx_page[i].page_tag = NULL; 1337 } 1338 } 1339 /* Rx CMB. */ 1340 for (i = 0; i < ALE_RX_PAGES; i++) { 1341 if (sc->ale_cdata.ale_rx_page[i].cmb_tag != NULL) { 1342 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL) 1343 bus_dmamap_unload( 1344 sc->ale_cdata.ale_rx_page[i].cmb_tag, 1345 sc->ale_cdata.ale_rx_page[i].cmb_map); 1346 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL && 1347 sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) 1348 bus_dmamem_free( 1349 sc->ale_cdata.ale_rx_page[i].cmb_tag, 1350 sc->ale_cdata.ale_rx_page[i].cmb_addr, 1351 sc->ale_cdata.ale_rx_page[i].cmb_map); 1352 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; 1353 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL; 1354 bus_dma_tag_destroy( 1355 sc->ale_cdata.ale_rx_page[i].cmb_tag); 1356 sc->ale_cdata.ale_rx_page[i].cmb_tag = NULL; 1357 } 1358 } 1359 /* Tx CMB. */ 1360 if (sc->ale_cdata.ale_tx_cmb_tag != NULL) { 1361 if (sc->ale_cdata.ale_tx_cmb_map != NULL) 1362 bus_dmamap_unload(sc->ale_cdata.ale_tx_cmb_tag, 1363 sc->ale_cdata.ale_tx_cmb_map); 1364 if (sc->ale_cdata.ale_tx_cmb_map != NULL && 1365 sc->ale_cdata.ale_tx_cmb != NULL) 1366 bus_dmamem_free(sc->ale_cdata.ale_tx_cmb_tag, 1367 sc->ale_cdata.ale_tx_cmb, 1368 sc->ale_cdata.ale_tx_cmb_map); 1369 sc->ale_cdata.ale_tx_cmb = NULL; 1370 sc->ale_cdata.ale_tx_cmb_map = NULL; 1371 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_cmb_tag); 1372 sc->ale_cdata.ale_tx_cmb_tag = NULL; 1373 } 1374 if (sc->ale_cdata.ale_buffer_tag != NULL) { 1375 bus_dma_tag_destroy(sc->ale_cdata.ale_buffer_tag); 1376 sc->ale_cdata.ale_buffer_tag = NULL; 1377 } 1378 if (sc->ale_cdata.ale_parent_tag != NULL) { 1379 bus_dma_tag_destroy(sc->ale_cdata.ale_parent_tag); 1380 sc->ale_cdata.ale_parent_tag = NULL; 1381 } 1382 } 1383 1384 static int 1385 ale_shutdown(device_t dev) 1386 { 1387 1388 return (ale_suspend(dev)); 1389 } 1390 1391 /* 1392 * Note, this driver resets the link speed to 10/100Mbps by 1393 * restarting auto-negotiation in suspend/shutdown phase but we 1394 * don't know whether that auto-negotiation would succeed or not 1395 * as driver has no control after powering off/suspend operation. 1396 * If the renegotiation fail WOL may not work. Running at 1Gbps 1397 * will draw more power than 375mA at 3.3V which is specified in 1398 * PCI specification and that would result in complete 1399 * shutdowning power to ethernet controller. 1400 * 1401 * TODO 1402 * Save current negotiated media speed/duplex/flow-control to 1403 * softc and restore the same link again after resuming. PHY 1404 * handling such as power down/resetting to 100Mbps may be better 1405 * handled in suspend method in phy driver. 1406 */ 1407 static void 1408 ale_setlinkspeed(struct ale_softc *sc) 1409 { 1410 struct mii_data *mii; 1411 int aneg, i; 1412 1413 mii = device_get_softc(sc->ale_miibus); 1414 mii_pollstat(mii); 1415 aneg = 0; 1416 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1417 (IFM_ACTIVE | IFM_AVALID)) { 1418 switch IFM_SUBTYPE(mii->mii_media_active) { 1419 case IFM_10_T: 1420 case IFM_100_TX: 1421 return; 1422 case IFM_1000_T: 1423 aneg++; 1424 break; 1425 default: 1426 break; 1427 } 1428 } 1429 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_100T2CR, 0); 1430 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1431 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1432 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1433 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1434 DELAY(1000); 1435 if (aneg != 0) { 1436 /* 1437 * Poll link state until ale(4) get a 10/100Mbps link. 1438 */ 1439 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1440 mii_pollstat(mii); 1441 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 1442 == (IFM_ACTIVE | IFM_AVALID)) { 1443 switch (IFM_SUBTYPE( 1444 mii->mii_media_active)) { 1445 case IFM_10_T: 1446 case IFM_100_TX: 1447 ale_mac_config(sc); 1448 return; 1449 default: 1450 break; 1451 } 1452 } 1453 ALE_UNLOCK(sc); 1454 pause("alelnk", hz); 1455 ALE_LOCK(sc); 1456 } 1457 if (i == MII_ANEGTICKS_GIGE) 1458 device_printf(sc->ale_dev, 1459 "establishing a link failed, WOL may not work!"); 1460 } 1461 /* 1462 * No link, force MAC to have 100Mbps, full-duplex link. 1463 * This is the last resort and may/may not work. 1464 */ 1465 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1466 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1467 ale_mac_config(sc); 1468 } 1469 1470 static void 1471 ale_setwol(struct ale_softc *sc) 1472 { 1473 struct ifnet *ifp; 1474 uint32_t reg, pmcs; 1475 uint16_t pmstat; 1476 int pmc; 1477 1478 ALE_LOCK_ASSERT(sc); 1479 1480 if (pci_find_extcap(sc->ale_dev, PCIY_PMG, &pmc) != 0) { 1481 /* Disable WOL. */ 1482 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 1483 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1484 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1485 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1486 /* Force PHY power down. */ 1487 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1488 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1489 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_PHY_PLL_ON | 1490 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_IDDQ | 1491 GPHY_CTRL_PCLK_SEL_DIS | GPHY_CTRL_PWDOWN_HW); 1492 return; 1493 } 1494 1495 ifp = sc->ale_ifp; 1496 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1497 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 1498 ale_setlinkspeed(sc); 1499 } 1500 1501 pmcs = 0; 1502 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1503 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1504 CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs); 1505 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1506 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 1507 MAC_CFG_BCAST); 1508 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1509 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1510 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1511 reg |= MAC_CFG_RX_ENB; 1512 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1513 1514 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1515 /* WOL disabled, PHY power down. */ 1516 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1517 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1518 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1519 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1520 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1521 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 1522 GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PCLK_SEL_DIS | 1523 GPHY_CTRL_PWDOWN_HW); 1524 } 1525 /* Request PME. */ 1526 pmstat = pci_read_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, 2); 1527 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1528 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1529 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1530 pci_write_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1531 } 1532 1533 static int 1534 ale_suspend(device_t dev) 1535 { 1536 struct ale_softc *sc; 1537 1538 sc = device_get_softc(dev); 1539 1540 ALE_LOCK(sc); 1541 ale_stop(sc); 1542 ale_setwol(sc); 1543 ALE_UNLOCK(sc); 1544 1545 return (0); 1546 } 1547 1548 static int 1549 ale_resume(device_t dev) 1550 { 1551 struct ale_softc *sc; 1552 struct ifnet *ifp; 1553 int pmc; 1554 uint16_t pmstat; 1555 1556 sc = device_get_softc(dev); 1557 1558 ALE_LOCK(sc); 1559 if (pci_find_extcap(sc->ale_dev, PCIY_PMG, &pmc) == 0) { 1560 /* Disable PME and clear PME status. */ 1561 pmstat = pci_read_config(sc->ale_dev, 1562 pmc + PCIR_POWER_STATUS, 2); 1563 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 1564 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1565 pci_write_config(sc->ale_dev, 1566 pmc + PCIR_POWER_STATUS, pmstat, 2); 1567 } 1568 } 1569 /* Reset PHY. */ 1570 ale_phy_reset(sc); 1571 ifp = sc->ale_ifp; 1572 if ((ifp->if_flags & IFF_UP) != 0) { 1573 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1574 ale_init_locked(sc); 1575 } 1576 ALE_UNLOCK(sc); 1577 1578 return (0); 1579 } 1580 1581 static int 1582 ale_encap(struct ale_softc *sc, struct mbuf **m_head) 1583 { 1584 struct ale_txdesc *txd, *txd_last; 1585 struct tx_desc *desc; 1586 struct mbuf *m; 1587 struct ip *ip; 1588 struct tcphdr *tcp; 1589 bus_dma_segment_t txsegs[ALE_MAXTXSEGS]; 1590 bus_dmamap_t map; 1591 uint32_t cflags, ip_off, poff, vtag; 1592 int error, i, nsegs, prod, si; 1593 1594 ALE_LOCK_ASSERT(sc); 1595 1596 M_ASSERTPKTHDR((*m_head)); 1597 1598 m = *m_head; 1599 ip = NULL; 1600 tcp = NULL; 1601 cflags = vtag = 0; 1602 ip_off = poff = 0; 1603 if ((m->m_pkthdr.csum_flags & (ALE_CSUM_FEATURES | CSUM_TSO)) != 0) { 1604 /* 1605 * AR81xx requires offset of TCP/UDP payload in its Tx 1606 * descriptor to perform hardware Tx checksum offload. 1607 * Additionally, TSO requires IP/TCP header size and 1608 * modification of IP/TCP header in order to make TSO 1609 * engine work. This kind of operation takes many CPU 1610 * cycles on FreeBSD so fast host CPU is required to 1611 * get smooth TSO performance. 1612 */ 1613 struct ether_header *eh; 1614 1615 if (M_WRITABLE(m) == 0) { 1616 /* Get a writable copy. */ 1617 m = m_dup(*m_head, M_DONTWAIT); 1618 /* Release original mbufs. */ 1619 m_freem(*m_head); 1620 if (m == NULL) { 1621 *m_head = NULL; 1622 return (ENOBUFS); 1623 } 1624 *m_head = m; 1625 } 1626 1627 /* 1628 * Buggy-controller requires 4 byte aligned Tx buffer 1629 * to make custom checksum offload work. 1630 */ 1631 if ((sc->ale_flags & ALE_FLAG_TXCSUM_BUG) != 0 && 1632 (m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0 && 1633 (mtod(m, intptr_t) & 3) != 0) { 1634 m = m_defrag(*m_head, M_DONTWAIT); 1635 if (m == NULL) { 1636 *m_head = NULL; 1637 return (ENOBUFS); 1638 } 1639 *m_head = m; 1640 } 1641 1642 ip_off = sizeof(struct ether_header); 1643 m = m_pullup(m, ip_off); 1644 if (m == NULL) { 1645 *m_head = NULL; 1646 return (ENOBUFS); 1647 } 1648 eh = mtod(m, struct ether_header *); 1649 /* 1650 * Check if hardware VLAN insertion is off. 1651 * Additional check for LLC/SNAP frame? 1652 */ 1653 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1654 ip_off = sizeof(struct ether_vlan_header); 1655 m = m_pullup(m, ip_off); 1656 if (m == NULL) { 1657 *m_head = NULL; 1658 return (ENOBUFS); 1659 } 1660 } 1661 m = m_pullup(m, ip_off + sizeof(struct ip)); 1662 if (m == NULL) { 1663 *m_head = NULL; 1664 return (ENOBUFS); 1665 } 1666 ip = (struct ip *)(mtod(m, char *) + ip_off); 1667 poff = ip_off + (ip->ip_hl << 2); 1668 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1669 /* 1670 * XXX 1671 * AR81xx requires the first descriptor should 1672 * not include any TCP playload for TSO case. 1673 * (i.e. ethernet header + IP + TCP header only) 1674 * m_pullup(9) above will ensure this too. 1675 * However it's not correct if the first mbuf 1676 * of the chain does not use cluster. 1677 */ 1678 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1679 if (m == NULL) { 1680 *m_head = NULL; 1681 return (ENOBUFS); 1682 } 1683 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1684 /* 1685 * AR81xx requires IP/TCP header size and offset as 1686 * well as TCP pseudo checksum which complicates 1687 * TSO configuration. I guess this comes from the 1688 * adherence to Microsoft NDIS Large Send 1689 * specification which requires insertion of 1690 * pseudo checksum by upper stack. The pseudo 1691 * checksum that NDIS refers to doesn't include 1692 * TCP payload length so ale(4) should recompute 1693 * the pseudo checksum here. Hopefully this wouldn't 1694 * be much burden on modern CPUs. 1695 * Reset IP checksum and recompute TCP pseudo 1696 * checksum as NDIS specification said. 1697 */ 1698 ip->ip_sum = 0; 1699 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1700 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1701 } 1702 *m_head = m; 1703 } 1704 1705 si = prod = sc->ale_cdata.ale_tx_prod; 1706 txd = &sc->ale_cdata.ale_txdesc[prod]; 1707 txd_last = txd; 1708 map = txd->tx_dmamap; 1709 1710 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1711 *m_head, txsegs, &nsegs, 0); 1712 if (error == EFBIG) { 1713 m = m_collapse(*m_head, M_DONTWAIT, ALE_MAXTXSEGS); 1714 if (m == NULL) { 1715 m_freem(*m_head); 1716 *m_head = NULL; 1717 return (ENOMEM); 1718 } 1719 *m_head = m; 1720 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1721 *m_head, txsegs, &nsegs, 0); 1722 if (error != 0) { 1723 m_freem(*m_head); 1724 *m_head = NULL; 1725 return (error); 1726 } 1727 } else if (error != 0) 1728 return (error); 1729 if (nsegs == 0) { 1730 m_freem(*m_head); 1731 *m_head = NULL; 1732 return (EIO); 1733 } 1734 1735 /* Check descriptor overrun. */ 1736 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 2) { 1737 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, map); 1738 return (ENOBUFS); 1739 } 1740 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, map, BUS_DMASYNC_PREWRITE); 1741 1742 m = *m_head; 1743 /* Configure Tx checksum offload. */ 1744 if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { 1745 /* 1746 * AR81xx supports Tx custom checksum offload feature 1747 * that offloads single 16bit checksum computation. 1748 * So you can choose one among IP, TCP and UDP. 1749 * Normally driver sets checksum start/insertion 1750 * position from the information of TCP/UDP frame as 1751 * TCP/UDP checksum takes more time than that of IP. 1752 * However it seems that custom checksum offload 1753 * requires 4 bytes aligned Tx buffers due to hardware 1754 * bug. 1755 * AR81xx also supports explicit Tx checksum computation 1756 * if it is told that the size of IP header and TCP 1757 * header(for UDP, the header size does not matter 1758 * because it's fixed length). However with this scheme 1759 * TSO does not work so you have to choose one either 1760 * TSO or explicit Tx checksum offload. I chosen TSO 1761 * plus custom checksum offload with work-around which 1762 * will cover most common usage for this consumer 1763 * ethernet controller. The work-around takes a lot of 1764 * CPU cycles if Tx buffer is not aligned on 4 bytes 1765 * boundary, though. 1766 */ 1767 cflags |= ALE_TD_CXSUM; 1768 /* Set checksum start offset. */ 1769 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); 1770 /* Set checksum insertion position of TCP/UDP. */ 1771 cflags |= ((poff + m->m_pkthdr.csum_data) << 1772 ALE_TD_CSUM_XSUMOFFSET_SHIFT); 1773 } 1774 1775 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1776 /* Request TSO and set MSS. */ 1777 cflags |= ALE_TD_TSO; 1778 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << ALE_TD_MSS_SHIFT); 1779 /* Set IP/TCP header size. */ 1780 cflags |= ip->ip_hl << ALE_TD_IPHDR_LEN_SHIFT; 1781 cflags |= tcp->th_off << ALE_TD_TCPHDR_LEN_SHIFT; 1782 } 1783 1784 /* Configure VLAN hardware tag insertion. */ 1785 if ((m->m_flags & M_VLANTAG) != 0) { 1786 vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1787 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); 1788 cflags |= ALE_TD_INSERT_VLAN_TAG; 1789 } 1790 1791 desc = NULL; 1792 for (i = 0; i < nsegs; i++) { 1793 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1794 desc->addr = htole64(txsegs[i].ds_addr); 1795 desc->len = htole32(ALE_TX_BYTES(txsegs[i].ds_len) | vtag); 1796 desc->flags = htole32(cflags); 1797 sc->ale_cdata.ale_tx_cnt++; 1798 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1799 } 1800 /* Update producer index. */ 1801 sc->ale_cdata.ale_tx_prod = prod; 1802 /* Set TSO header on the first descriptor. */ 1803 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1804 desc = &sc->ale_cdata.ale_tx_ring[si]; 1805 desc->flags |= htole32(ALE_TD_TSO_HDR); 1806 } 1807 1808 /* Finally set EOP on the last descriptor. */ 1809 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; 1810 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1811 desc->flags |= htole32(ALE_TD_EOP); 1812 1813 /* Swap dmamap of the first and the last. */ 1814 txd = &sc->ale_cdata.ale_txdesc[prod]; 1815 map = txd_last->tx_dmamap; 1816 txd_last->tx_dmamap = txd->tx_dmamap; 1817 txd->tx_dmamap = map; 1818 txd->tx_m = m; 1819 1820 /* Sync descriptors. */ 1821 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 1822 sc->ale_cdata.ale_tx_ring_map, 1823 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1824 1825 return (0); 1826 } 1827 1828 static void 1829 ale_tx_task(void *arg, int pending) 1830 { 1831 struct ifnet *ifp; 1832 1833 ifp = (struct ifnet *)arg; 1834 ale_start(ifp); 1835 } 1836 1837 static void 1838 ale_start(struct ifnet *ifp) 1839 { 1840 struct ale_softc *sc; 1841 struct mbuf *m_head; 1842 int enq; 1843 1844 sc = ifp->if_softc; 1845 1846 ALE_LOCK(sc); 1847 1848 /* Reclaim transmitted frames. */ 1849 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) 1850 ale_txeof(sc); 1851 1852 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1853 IFF_DRV_RUNNING || (sc->ale_flags & ALE_FLAG_LINK) == 0) { 1854 ALE_UNLOCK(sc); 1855 return; 1856 } 1857 1858 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1859 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1860 if (m_head == NULL) 1861 break; 1862 /* 1863 * Pack the data into the transmit ring. If we 1864 * don't have room, set the OACTIVE flag and wait 1865 * for the NIC to drain the ring. 1866 */ 1867 if (ale_encap(sc, &m_head)) { 1868 if (m_head == NULL) 1869 break; 1870 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1871 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1872 break; 1873 } 1874 1875 enq++; 1876 /* 1877 * If there's a BPF listener, bounce a copy of this frame 1878 * to him. 1879 */ 1880 ETHER_BPF_MTAP(ifp, m_head); 1881 } 1882 1883 if (enq > 0) { 1884 /* Kick. */ 1885 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, 1886 sc->ale_cdata.ale_tx_prod); 1887 /* Set a timeout in case the chip goes out to lunch. */ 1888 sc->ale_watchdog_timer = ALE_TX_TIMEOUT; 1889 } 1890 1891 ALE_UNLOCK(sc); 1892 } 1893 1894 static void 1895 ale_watchdog(struct ale_softc *sc) 1896 { 1897 struct ifnet *ifp; 1898 1899 ALE_LOCK_ASSERT(sc); 1900 1901 if (sc->ale_watchdog_timer == 0 || --sc->ale_watchdog_timer) 1902 return; 1903 1904 ifp = sc->ale_ifp; 1905 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1906 if_printf(sc->ale_ifp, "watchdog timeout (lost link)\n"); 1907 ifp->if_oerrors++; 1908 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1909 ale_init_locked(sc); 1910 return; 1911 } 1912 if_printf(sc->ale_ifp, "watchdog timeout -- resetting\n"); 1913 ifp->if_oerrors++; 1914 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1915 ale_init_locked(sc); 1916 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1917 taskqueue_enqueue(sc->ale_tq, &sc->ale_tx_task); 1918 } 1919 1920 static int 1921 ale_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1922 { 1923 struct ale_softc *sc; 1924 struct ifreq *ifr; 1925 struct mii_data *mii; 1926 int error, mask; 1927 1928 sc = ifp->if_softc; 1929 ifr = (struct ifreq *)data; 1930 error = 0; 1931 switch (cmd) { 1932 case SIOCSIFMTU: 1933 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALE_JUMBO_MTU || 1934 ((sc->ale_flags & ALE_FLAG_JUMBO) == 0 && 1935 ifr->ifr_mtu > ETHERMTU)) 1936 error = EINVAL; 1937 else if (ifp->if_mtu != ifr->ifr_mtu) { 1938 ALE_LOCK(sc); 1939 ifp->if_mtu = ifr->ifr_mtu; 1940 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1941 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1942 ale_init_locked(sc); 1943 } 1944 ALE_UNLOCK(sc); 1945 } 1946 break; 1947 case SIOCSIFFLAGS: 1948 ALE_LOCK(sc); 1949 if ((ifp->if_flags & IFF_UP) != 0) { 1950 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1951 if (((ifp->if_flags ^ sc->ale_if_flags) 1952 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1953 ale_rxfilter(sc); 1954 } else { 1955 if ((sc->ale_flags & ALE_FLAG_DETACH) == 0) 1956 ale_init_locked(sc); 1957 } 1958 } else { 1959 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1960 ale_stop(sc); 1961 } 1962 sc->ale_if_flags = ifp->if_flags; 1963 ALE_UNLOCK(sc); 1964 break; 1965 case SIOCADDMULTI: 1966 case SIOCDELMULTI: 1967 ALE_LOCK(sc); 1968 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1969 ale_rxfilter(sc); 1970 ALE_UNLOCK(sc); 1971 break; 1972 case SIOCSIFMEDIA: 1973 case SIOCGIFMEDIA: 1974 mii = device_get_softc(sc->ale_miibus); 1975 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1976 break; 1977 case SIOCSIFCAP: 1978 ALE_LOCK(sc); 1979 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1980 if ((mask & IFCAP_TXCSUM) != 0 && 1981 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 1982 ifp->if_capenable ^= IFCAP_TXCSUM; 1983 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1984 ifp->if_hwassist |= ALE_CSUM_FEATURES; 1985 else 1986 ifp->if_hwassist &= ~ALE_CSUM_FEATURES; 1987 } 1988 if ((mask & IFCAP_RXCSUM) != 0 && 1989 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 1990 ifp->if_capenable ^= IFCAP_RXCSUM; 1991 if ((mask & IFCAP_TSO4) != 0 && 1992 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 1993 ifp->if_capenable ^= IFCAP_TSO4; 1994 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 1995 ifp->if_hwassist |= CSUM_TSO; 1996 else 1997 ifp->if_hwassist &= ~CSUM_TSO; 1998 } 1999 2000 if ((mask & IFCAP_WOL_MCAST) != 0 && 2001 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 2002 ifp->if_capenable ^= IFCAP_WOL_MCAST; 2003 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2004 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 2005 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 2006 2007 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2008 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 2009 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 2010 ale_rxvlan(sc); 2011 } 2012 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2013 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 2014 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 2015 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2016 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 2017 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 2018 /* 2019 * VLAN hardware tagging is required to do checksum 2020 * offload or TSO on VLAN interface. Checksum offload 2021 * on VLAN interface also requires hardware checksum 2022 * offload of parent interface. 2023 */ 2024 if ((ifp->if_capenable & IFCAP_TXCSUM) == 0) 2025 ifp->if_capenable &= ~IFCAP_VLAN_HWCSUM; 2026 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 2027 ifp->if_capenable &= 2028 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 2029 ALE_UNLOCK(sc); 2030 VLAN_CAPABILITIES(ifp); 2031 break; 2032 default: 2033 error = ether_ioctl(ifp, cmd, data); 2034 break; 2035 } 2036 2037 return (error); 2038 } 2039 2040 static void 2041 ale_mac_config(struct ale_softc *sc) 2042 { 2043 struct mii_data *mii; 2044 uint32_t reg; 2045 2046 ALE_LOCK_ASSERT(sc); 2047 2048 mii = device_get_softc(sc->ale_miibus); 2049 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2050 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2051 MAC_CFG_SPEED_MASK); 2052 /* Reprogram MAC with resolved speed/duplex. */ 2053 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2054 case IFM_10_T: 2055 case IFM_100_TX: 2056 reg |= MAC_CFG_SPEED_10_100; 2057 break; 2058 case IFM_1000_T: 2059 reg |= MAC_CFG_SPEED_1000; 2060 break; 2061 } 2062 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2063 reg |= MAC_CFG_FULL_DUPLEX; 2064 #ifdef notyet 2065 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2066 reg |= MAC_CFG_TX_FC; 2067 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2068 reg |= MAC_CFG_RX_FC; 2069 #endif 2070 } 2071 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2072 } 2073 2074 static void 2075 ale_link_task(void *arg, int pending) 2076 { 2077 struct ale_softc *sc; 2078 struct mii_data *mii; 2079 struct ifnet *ifp; 2080 uint32_t reg; 2081 2082 sc = (struct ale_softc *)arg; 2083 2084 ALE_LOCK(sc); 2085 mii = device_get_softc(sc->ale_miibus); 2086 ifp = sc->ale_ifp; 2087 if (mii == NULL || ifp == NULL || 2088 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2089 ALE_UNLOCK(sc); 2090 return; 2091 } 2092 2093 sc->ale_flags &= ~ALE_FLAG_LINK; 2094 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 2095 (IFM_ACTIVE | IFM_AVALID)) { 2096 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2097 case IFM_10_T: 2098 case IFM_100_TX: 2099 sc->ale_flags |= ALE_FLAG_LINK; 2100 break; 2101 case IFM_1000_T: 2102 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 2103 sc->ale_flags |= ALE_FLAG_LINK; 2104 break; 2105 default: 2106 break; 2107 } 2108 } 2109 2110 /* Stop Rx/Tx MACs. */ 2111 ale_stop_mac(sc); 2112 2113 /* Program MACs with resolved speed/duplex/flow-control. */ 2114 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { 2115 ale_mac_config(sc); 2116 /* Reenable Tx/Rx MACs. */ 2117 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2118 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 2119 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2120 } 2121 2122 ALE_UNLOCK(sc); 2123 } 2124 2125 static void 2126 ale_stats_clear(struct ale_softc *sc) 2127 { 2128 struct smb sb; 2129 uint32_t *reg; 2130 int i; 2131 2132 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2133 CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2134 i += sizeof(uint32_t); 2135 } 2136 /* Read Tx statistics. */ 2137 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2138 CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2139 i += sizeof(uint32_t); 2140 } 2141 } 2142 2143 static void 2144 ale_stats_update(struct ale_softc *sc) 2145 { 2146 struct ale_hw_stats *stat; 2147 struct smb sb, *smb; 2148 struct ifnet *ifp; 2149 uint32_t *reg; 2150 int i; 2151 2152 ALE_LOCK_ASSERT(sc); 2153 2154 ifp = sc->ale_ifp; 2155 stat = &sc->ale_stats; 2156 smb = &sb; 2157 2158 /* Read Rx statistics. */ 2159 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2160 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2161 i += sizeof(uint32_t); 2162 } 2163 /* Read Tx statistics. */ 2164 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2165 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2166 i += sizeof(uint32_t); 2167 } 2168 2169 /* Rx stats. */ 2170 stat->rx_frames += smb->rx_frames; 2171 stat->rx_bcast_frames += smb->rx_bcast_frames; 2172 stat->rx_mcast_frames += smb->rx_mcast_frames; 2173 stat->rx_pause_frames += smb->rx_pause_frames; 2174 stat->rx_control_frames += smb->rx_control_frames; 2175 stat->rx_crcerrs += smb->rx_crcerrs; 2176 stat->rx_lenerrs += smb->rx_lenerrs; 2177 stat->rx_bytes += smb->rx_bytes; 2178 stat->rx_runts += smb->rx_runts; 2179 stat->rx_fragments += smb->rx_fragments; 2180 stat->rx_pkts_64 += smb->rx_pkts_64; 2181 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2182 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2183 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2184 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2185 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2186 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2187 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2188 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2189 stat->rx_rrs_errs += smb->rx_rrs_errs; 2190 stat->rx_alignerrs += smb->rx_alignerrs; 2191 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2192 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2193 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2194 2195 /* Tx stats. */ 2196 stat->tx_frames += smb->tx_frames; 2197 stat->tx_bcast_frames += smb->tx_bcast_frames; 2198 stat->tx_mcast_frames += smb->tx_mcast_frames; 2199 stat->tx_pause_frames += smb->tx_pause_frames; 2200 stat->tx_excess_defer += smb->tx_excess_defer; 2201 stat->tx_control_frames += smb->tx_control_frames; 2202 stat->tx_deferred += smb->tx_deferred; 2203 stat->tx_bytes += smb->tx_bytes; 2204 stat->tx_pkts_64 += smb->tx_pkts_64; 2205 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2206 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2207 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2208 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2209 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2210 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2211 stat->tx_single_colls += smb->tx_single_colls; 2212 stat->tx_multi_colls += smb->tx_multi_colls; 2213 stat->tx_late_colls += smb->tx_late_colls; 2214 stat->tx_excess_colls += smb->tx_excess_colls; 2215 stat->tx_abort += smb->tx_abort; 2216 stat->tx_underrun += smb->tx_underrun; 2217 stat->tx_desc_underrun += smb->tx_desc_underrun; 2218 stat->tx_lenerrs += smb->tx_lenerrs; 2219 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2220 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2221 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2222 2223 /* Update counters in ifnet. */ 2224 ifp->if_opackets += smb->tx_frames; 2225 2226 ifp->if_collisions += smb->tx_single_colls + 2227 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2228 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 2229 2230 /* 2231 * XXX 2232 * tx_pkts_truncated counter looks suspicious. It constantly 2233 * increments with no sign of Tx errors. This may indicate 2234 * the counter name is not correct one so I've removed the 2235 * counter in output errors. 2236 */ 2237 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 2238 smb->tx_underrun; 2239 2240 ifp->if_ipackets += smb->rx_frames; 2241 2242 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2243 smb->rx_runts + smb->rx_pkts_truncated + 2244 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2245 smb->rx_alignerrs; 2246 } 2247 2248 static int 2249 ale_intr(void *arg) 2250 { 2251 struct ale_softc *sc; 2252 uint32_t status; 2253 2254 sc = (struct ale_softc *)arg; 2255 2256 status = CSR_READ_4(sc, ALE_INTR_STATUS); 2257 if ((status & ALE_INTRS) == 0) 2258 return (FILTER_STRAY); 2259 /* Disable interrupts. */ 2260 CSR_WRITE_4(sc, ALE_INTR_STATUS, INTR_DIS_INT); 2261 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2262 2263 return (FILTER_HANDLED); 2264 } 2265 2266 static void 2267 ale_int_task(void *arg, int pending) 2268 { 2269 struct ale_softc *sc; 2270 struct ifnet *ifp; 2271 uint32_t status; 2272 int more; 2273 2274 sc = (struct ale_softc *)arg; 2275 2276 status = CSR_READ_4(sc, ALE_INTR_STATUS); 2277 more = atomic_readandclear_int(&sc->ale_morework); 2278 if (more != 0) 2279 status |= INTR_RX_PKT; 2280 if ((status & ALE_INTRS) == 0) 2281 goto done; 2282 2283 /* Acknowledge interrupts but still disable interrupts. */ 2284 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); 2285 2286 ifp = sc->ale_ifp; 2287 more = 0; 2288 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2289 more = ale_rxeof(sc, sc->ale_process_limit); 2290 if (more == EAGAIN) 2291 atomic_set_int(&sc->ale_morework, 1); 2292 else if (more == EIO) { 2293 ALE_LOCK(sc); 2294 sc->ale_stats.reset_brk_seq++; 2295 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2296 ale_init_locked(sc); 2297 ALE_UNLOCK(sc); 2298 return; 2299 } 2300 2301 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 2302 if ((status & INTR_DMA_RD_TO_RST) != 0) 2303 device_printf(sc->ale_dev, 2304 "DMA read error! -- resetting\n"); 2305 if ((status & INTR_DMA_WR_TO_RST) != 0) 2306 device_printf(sc->ale_dev, 2307 "DMA write error! -- resetting\n"); 2308 ALE_LOCK(sc); 2309 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2310 ale_init_locked(sc); 2311 ALE_UNLOCK(sc); 2312 return; 2313 } 2314 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2315 taskqueue_enqueue(sc->ale_tq, &sc->ale_tx_task); 2316 } 2317 2318 if (more == EAGAIN || 2319 (CSR_READ_4(sc, ALE_INTR_STATUS) & ALE_INTRS) != 0) { 2320 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2321 return; 2322 } 2323 2324 done: 2325 /* Re-enable interrupts. */ 2326 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); 2327 } 2328 2329 static void 2330 ale_txeof(struct ale_softc *sc) 2331 { 2332 struct ifnet *ifp; 2333 struct ale_txdesc *txd; 2334 uint32_t cons, prod; 2335 int prog; 2336 2337 ALE_LOCK_ASSERT(sc); 2338 2339 ifp = sc->ale_ifp; 2340 2341 if (sc->ale_cdata.ale_tx_cnt == 0) 2342 return; 2343 2344 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2345 sc->ale_cdata.ale_tx_ring_map, 2346 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2347 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { 2348 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2349 sc->ale_cdata.ale_tx_cmb_map, 2350 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2351 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; 2352 } else 2353 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); 2354 cons = sc->ale_cdata.ale_tx_cons; 2355 /* 2356 * Go through our Tx list and free mbufs for those 2357 * frames which have been transmitted. 2358 */ 2359 for (prog = 0; cons != prod; prog++, 2360 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { 2361 if (sc->ale_cdata.ale_tx_cnt <= 0) 2362 break; 2363 prog++; 2364 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2365 sc->ale_cdata.ale_tx_cnt--; 2366 txd = &sc->ale_cdata.ale_txdesc[cons]; 2367 if (txd->tx_m != NULL) { 2368 /* Reclaim transmitted mbufs. */ 2369 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2370 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2371 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2372 txd->tx_dmamap); 2373 m_freem(txd->tx_m); 2374 txd->tx_m = NULL; 2375 } 2376 } 2377 2378 if (prog > 0) { 2379 sc->ale_cdata.ale_tx_cons = cons; 2380 /* 2381 * Unarm watchdog timer only when there is no pending 2382 * Tx descriptors in queue. 2383 */ 2384 if (sc->ale_cdata.ale_tx_cnt == 0) 2385 sc->ale_watchdog_timer = 0; 2386 } 2387 } 2388 2389 static void 2390 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, 2391 uint32_t length, uint32_t *prod) 2392 { 2393 struct ale_rx_page *rx_page; 2394 2395 rx_page = *page; 2396 /* Update consumer position. */ 2397 rx_page->cons += roundup(length + sizeof(struct rx_rs), 2398 ALE_RX_PAGE_ALIGN); 2399 if (rx_page->cons >= ALE_RX_PAGE_SZ) { 2400 /* 2401 * End of Rx page reached, let hardware reuse 2402 * this page. 2403 */ 2404 rx_page->cons = 0; 2405 *rx_page->cmb_addr = 0; 2406 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2407 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2408 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, 2409 RXF_VALID); 2410 /* Switch to alternate Rx page. */ 2411 sc->ale_cdata.ale_rx_curp ^= 1; 2412 rx_page = *page = 2413 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2414 /* Page flipped, sync CMB and Rx page. */ 2415 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2416 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2417 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2418 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2419 /* Sync completed, cache updated producer index. */ 2420 *prod = *rx_page->cmb_addr; 2421 } 2422 } 2423 2424 2425 /* 2426 * It seems that AR81xx controller can compute partial checksum. 2427 * The partial checksum value can be used to accelerate checksum 2428 * computation for fragmented TCP/UDP packets. Upper network stack 2429 * already takes advantage of the partial checksum value in IP 2430 * reassembly stage. But I'm not sure the correctness of the 2431 * partial hardware checksum assistance due to lack of data sheet. 2432 * In addition, the Rx feature of controller that requires copying 2433 * for every frames effectively nullifies one of most nice offload 2434 * capability of controller. 2435 */ 2436 static void 2437 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) 2438 { 2439 struct ifnet *ifp; 2440 struct ip *ip; 2441 char *p; 2442 2443 ifp = sc->ale_ifp; 2444 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2445 if ((status & ALE_RD_IPCSUM_NOK) == 0) 2446 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2447 2448 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { 2449 if (((status & ALE_RD_IPV4_FRAG) == 0) && 2450 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && 2451 ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) { 2452 m->m_pkthdr.csum_flags |= 2453 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2454 m->m_pkthdr.csum_data = 0xffff; 2455 } 2456 } else { 2457 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 && 2458 (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) { 2459 p = mtod(m, char *); 2460 p += ETHER_HDR_LEN; 2461 if ((status & ALE_RD_802_3) != 0) 2462 p += LLC_SNAPFRAMELEN; 2463 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0 && 2464 (status & ALE_RD_VLAN) != 0) 2465 p += ETHER_VLAN_ENCAP_LEN; 2466 ip = (struct ip *)p; 2467 if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0) 2468 return; 2469 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 2470 CSUM_PSEUDO_HDR; 2471 m->m_pkthdr.csum_data = 0xffff; 2472 } 2473 } 2474 /* 2475 * Don't mark bad checksum for TCP/UDP frames 2476 * as fragmented frames may always have set 2477 * bad checksummed bit of frame status. 2478 */ 2479 } 2480 2481 /* Process received frames. */ 2482 static int 2483 ale_rxeof(struct ale_softc *sc, int count) 2484 { 2485 struct ale_rx_page *rx_page; 2486 struct rx_rs *rs; 2487 struct ifnet *ifp; 2488 struct mbuf *m; 2489 uint32_t length, prod, seqno, status, vtags; 2490 int prog; 2491 2492 ifp = sc->ale_ifp; 2493 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2494 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2495 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2496 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2497 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2498 /* 2499 * Don't directly access producer index as hardware may 2500 * update it while Rx handler is in progress. It would 2501 * be even better if there is a way to let hardware 2502 * know how far driver processed its received frames. 2503 * Alternatively, hardware could provide a way to disable 2504 * CMB updates until driver acknowledges the end of CMB 2505 * access. 2506 */ 2507 prod = *rx_page->cmb_addr; 2508 for (prog = 0; prog < count; prog++) { 2509 if (rx_page->cons >= prod) 2510 break; 2511 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); 2512 seqno = ALE_RX_SEQNO(le32toh(rs->seqno)); 2513 if (sc->ale_cdata.ale_rx_seqno != seqno) { 2514 /* 2515 * Normally I believe this should not happen unless 2516 * severe driver bug or corrupted memory. However 2517 * it seems to happen under certain conditions which 2518 * is triggered by abrupt Rx events such as initiation 2519 * of bulk transfer of remote host. It's not easy to 2520 * reproduce this and I doubt it could be related 2521 * with FIFO overflow of hardware or activity of Tx 2522 * CMB updates. I also remember similar behaviour 2523 * seen on RealTek 8139 which uses resembling Rx 2524 * scheme. 2525 */ 2526 if (bootverbose) 2527 device_printf(sc->ale_dev, 2528 "garbled seq: %u, expected: %u -- " 2529 "resetting!\n", seqno, 2530 sc->ale_cdata.ale_rx_seqno); 2531 return (EIO); 2532 } 2533 /* Frame received. */ 2534 sc->ale_cdata.ale_rx_seqno++; 2535 length = ALE_RX_BYTES(le32toh(rs->length)); 2536 status = le32toh(rs->flags); 2537 if ((status & ALE_RD_ERROR) != 0) { 2538 /* 2539 * We want to pass the following frames to upper 2540 * layer regardless of error status of Rx return 2541 * status. 2542 * 2543 * o IP/TCP/UDP checksum is bad. 2544 * o frame length and protocol specific length 2545 * does not match. 2546 */ 2547 if ((status & (ALE_RD_CRC | ALE_RD_CODE | 2548 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | 2549 ALE_RD_TRUNC)) != 0) { 2550 ale_rx_update_page(sc, &rx_page, length, &prod); 2551 continue; 2552 } 2553 } 2554 /* 2555 * m_devget(9) is major bottle-neck of ale(4)(It comes 2556 * from hardware limitation). For jumbo frames we could 2557 * get a slightly better performance if driver use 2558 * m_getjcl(9) with proper buffer size argument. However 2559 * that would make code more complicated and I don't 2560 * think users would expect good Rx performance numbers 2561 * on these low-end consumer ethernet controller. 2562 */ 2563 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, 2564 ETHER_ALIGN, ifp, NULL); 2565 if (m == NULL) { 2566 ifp->if_iqdrops++; 2567 ale_rx_update_page(sc, &rx_page, length, &prod); 2568 continue; 2569 } 2570 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 2571 (status & ALE_RD_IPV4) != 0) 2572 ale_rxcsum(sc, m, status); 2573 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 2574 (status & ALE_RD_VLAN) != 0) { 2575 vtags = ALE_RX_VLAN(le32toh(rs->vtags)); 2576 m->m_pkthdr.ether_vtag = ALE_RX_VLAN_TAG(vtags); 2577 m->m_flags |= M_VLANTAG; 2578 } 2579 2580 /* Pass it to upper layer. */ 2581 (*ifp->if_input)(ifp, m); 2582 2583 ale_rx_update_page(sc, &rx_page, length, &prod); 2584 } 2585 2586 return (count > 0 ? 0 : EAGAIN); 2587 } 2588 2589 static void 2590 ale_tick(void *arg) 2591 { 2592 struct ale_softc *sc; 2593 struct mii_data *mii; 2594 2595 sc = (struct ale_softc *)arg; 2596 2597 ALE_LOCK_ASSERT(sc); 2598 2599 mii = device_get_softc(sc->ale_miibus); 2600 mii_tick(mii); 2601 ale_stats_update(sc); 2602 /* 2603 * Reclaim Tx buffers that have been transferred. It's not 2604 * needed here but it would release allocated mbuf chains 2605 * faster and limit the maximum delay to a hz. 2606 */ 2607 ale_txeof(sc); 2608 ale_watchdog(sc); 2609 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2610 } 2611 2612 static void 2613 ale_reset(struct ale_softc *sc) 2614 { 2615 uint32_t reg; 2616 int i; 2617 2618 /* Initialize PCIe module. From Linux. */ 2619 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2620 2621 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); 2622 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2623 DELAY(10); 2624 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) 2625 break; 2626 } 2627 if (i == 0) 2628 device_printf(sc->ale_dev, "master reset timeout!\n"); 2629 2630 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2631 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) 2632 break; 2633 DELAY(10); 2634 } 2635 2636 if (i == 0) 2637 device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg); 2638 } 2639 2640 static void 2641 ale_init(void *xsc) 2642 { 2643 struct ale_softc *sc; 2644 2645 sc = (struct ale_softc *)xsc; 2646 ALE_LOCK(sc); 2647 ale_init_locked(sc); 2648 ALE_UNLOCK(sc); 2649 } 2650 2651 static void 2652 ale_init_locked(struct ale_softc *sc) 2653 { 2654 struct ifnet *ifp; 2655 struct mii_data *mii; 2656 uint8_t eaddr[ETHER_ADDR_LEN]; 2657 bus_addr_t paddr; 2658 uint32_t reg, rxf_hi, rxf_lo; 2659 2660 ALE_LOCK_ASSERT(sc); 2661 2662 ifp = sc->ale_ifp; 2663 mii = device_get_softc(sc->ale_miibus); 2664 2665 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2666 return; 2667 /* 2668 * Cancel any pending I/O. 2669 */ 2670 ale_stop(sc); 2671 /* 2672 * Reset the chip to a known state. 2673 */ 2674 ale_reset(sc); 2675 /* Initialize Tx descriptors, DMA memory blocks. */ 2676 ale_init_rx_pages(sc); 2677 ale_init_tx_ring(sc); 2678 2679 /* Reprogram the station address. */ 2680 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2681 CSR_WRITE_4(sc, ALE_PAR0, 2682 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2683 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); 2684 /* 2685 * Clear WOL status and disable all WOL feature as WOL 2686 * would interfere Rx operation under normal environments. 2687 */ 2688 CSR_READ_4(sc, ALE_WOL_CFG); 2689 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 2690 /* 2691 * Set Tx descriptor/RXF0/CMB base addresses. They share 2692 * the same high address part of DMAable region. 2693 */ 2694 paddr = sc->ale_cdata.ale_tx_ring_paddr; 2695 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); 2696 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); 2697 CSR_WRITE_4(sc, ALE_TPD_CNT, 2698 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); 2699 /* Set Rx page base address, note we use single queue. */ 2700 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; 2701 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); 2702 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; 2703 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); 2704 /* Set Tx/Rx CMB addresses. */ 2705 paddr = sc->ale_cdata.ale_tx_cmb_paddr; 2706 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); 2707 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; 2708 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); 2709 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; 2710 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); 2711 /* Mark RXF0 is valid. */ 2712 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); 2713 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); 2714 /* 2715 * No need to initialize RFX1/RXF2/RXF3. We don't use 2716 * multi-queue yet. 2717 */ 2718 2719 /* Set Rx page size, excluding guard frame size. */ 2720 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); 2721 /* Tell hardware that we're ready to load DMA blocks. */ 2722 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); 2723 2724 /* Set Rx/Tx interrupt trigger threshold. */ 2725 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | 2726 (4 << INT_TRIG_TX_THRESH_SHIFT)); 2727 /* 2728 * XXX 2729 * Set interrupt trigger timer, its purpose and relation 2730 * with interrupt moderation mechanism is not clear yet. 2731 */ 2732 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, 2733 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | 2734 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); 2735 2736 /* Configure interrupt moderation timer. */ 2737 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; 2738 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; 2739 CSR_WRITE_4(sc, ALE_IM_TIMER, reg); 2740 reg = CSR_READ_4(sc, ALE_MASTER_CFG); 2741 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 2742 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 2743 if (ALE_USECS(sc->ale_int_rx_mod) != 0) 2744 reg |= MASTER_IM_RX_TIMER_ENB; 2745 if (ALE_USECS(sc->ale_int_tx_mod) != 0) 2746 reg |= MASTER_IM_TX_TIMER_ENB; 2747 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); 2748 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); 2749 2750 /* Set Maximum frame size of controller. */ 2751 if (ifp->if_mtu < ETHERMTU) 2752 sc->ale_max_frame_size = ETHERMTU; 2753 else 2754 sc->ale_max_frame_size = ifp->if_mtu; 2755 sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 2756 ETHER_CRC_LEN; 2757 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); 2758 /* Configure IPG/IFG parameters. */ 2759 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, 2760 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 2761 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2762 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2763 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 2764 /* Set parameters for half-duplex media. */ 2765 CSR_WRITE_4(sc, ALE_HDPX_CFG, 2766 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2767 HDPX_CFG_LCOL_MASK) | 2768 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2769 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2770 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2771 HDPX_CFG_ABEBT_MASK) | 2772 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2773 HDPX_CFG_JAMIPG_MASK)); 2774 2775 /* Configure Tx jumbo frame parameters. */ 2776 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2777 if (ifp->if_mtu < ETHERMTU) 2778 reg = sc->ale_max_frame_size; 2779 else if (ifp->if_mtu < 6 * 1024) 2780 reg = (sc->ale_max_frame_size * 2) / 3; 2781 else 2782 reg = sc->ale_max_frame_size / 2; 2783 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, 2784 roundup(reg, TX_JUMBO_THRESH_UNIT) >> 2785 TX_JUMBO_THRESH_UNIT_SHIFT); 2786 } 2787 /* Configure TxQ. */ 2788 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) 2789 << TXQ_CFG_TX_FIFO_BURST_SHIFT; 2790 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2791 TXQ_CFG_TPD_BURST_MASK; 2792 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); 2793 2794 /* Configure Rx jumbo frame & flow control parameters. */ 2795 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2796 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); 2797 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, 2798 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << 2799 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | 2800 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & 2801 RX_JUMBO_LKAH_MASK)); 2802 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 2803 rxf_hi = (reg * 7) / 10; 2804 rxf_lo = (reg * 3)/ 10; 2805 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, 2806 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2807 RX_FIFO_PAUSE_THRESH_LO_MASK) | 2808 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2809 RX_FIFO_PAUSE_THRESH_HI_MASK)); 2810 } 2811 2812 /* Disable RSS. */ 2813 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); 2814 CSR_WRITE_4(sc, ALE_RSS_CPU, 0); 2815 2816 /* Configure RxQ. */ 2817 CSR_WRITE_4(sc, ALE_RXQ_CFG, 2818 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2819 2820 /* Configure DMA parameters. */ 2821 reg = 0; 2822 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) 2823 reg |= DMA_CFG_TXCMB_ENB; 2824 CSR_WRITE_4(sc, ALE_DMA_CFG, 2825 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | 2826 sc->ale_dma_rd_burst | reg | 2827 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | 2828 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 2829 DMA_CFG_RD_DELAY_CNT_MASK) | 2830 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 2831 DMA_CFG_WR_DELAY_CNT_MASK)); 2832 2833 /* 2834 * Hardware can be configured to issue SMB interrupt based 2835 * on programmed interval. Since there is a callout that is 2836 * invoked for every hz in driver we use that instead of 2837 * relying on periodic SMB interrupt. 2838 */ 2839 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); 2840 /* Clear MAC statistics. */ 2841 ale_stats_clear(sc); 2842 2843 /* 2844 * Configure Tx/Rx MACs. 2845 * - Auto-padding for short frames. 2846 * - Enable CRC generation. 2847 * Actual reconfiguration of MAC for resolved speed/duplex 2848 * is followed after detection of link establishment. 2849 * AR81xx always does checksum computation regardless of 2850 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will 2851 * cause Rx handling issue for fragmented IP datagrams due 2852 * to silicon bug. 2853 */ 2854 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 2855 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2856 MAC_CFG_PREAMBLE_MASK); 2857 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) 2858 reg |= MAC_CFG_SPEED_10_100; 2859 else 2860 reg |= MAC_CFG_SPEED_1000; 2861 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2862 2863 /* Set up the receive filter. */ 2864 ale_rxfilter(sc); 2865 ale_rxvlan(sc); 2866 2867 /* Acknowledge all pending interrupts and clear it. */ 2868 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); 2869 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2870 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); 2871 2872 sc->ale_flags &= ~ALE_FLAG_LINK; 2873 /* Switch to the current media. */ 2874 mii_mediachg(mii); 2875 2876 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2877 2878 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2879 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2880 } 2881 2882 static void 2883 ale_stop(struct ale_softc *sc) 2884 { 2885 struct ifnet *ifp; 2886 struct ale_txdesc *txd; 2887 uint32_t reg; 2888 int i; 2889 2890 ALE_LOCK_ASSERT(sc); 2891 /* 2892 * Mark the interface down and cancel the watchdog timer. 2893 */ 2894 ifp = sc->ale_ifp; 2895 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2896 sc->ale_flags &= ~ALE_FLAG_LINK; 2897 callout_stop(&sc->ale_tick_ch); 2898 sc->ale_watchdog_timer = 0; 2899 ale_stats_update(sc); 2900 /* Disable interrupts. */ 2901 CSR_WRITE_4(sc, ALE_INTR_MASK, 0); 2902 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2903 /* Disable queue processing and DMA. */ 2904 reg = CSR_READ_4(sc, ALE_TXQ_CFG); 2905 reg &= ~TXQ_CFG_ENB; 2906 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); 2907 reg = CSR_READ_4(sc, ALE_RXQ_CFG); 2908 reg &= ~RXQ_CFG_ENB; 2909 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); 2910 reg = CSR_READ_4(sc, ALE_DMA_CFG); 2911 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); 2912 CSR_WRITE_4(sc, ALE_DMA_CFG, reg); 2913 DELAY(1000); 2914 /* Stop Rx/Tx MACs. */ 2915 ale_stop_mac(sc); 2916 /* Disable interrupts which might be touched in taskq handler. */ 2917 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2918 2919 /* 2920 * Free TX mbufs still in the queues. 2921 */ 2922 for (i = 0; i < ALE_TX_RING_CNT; i++) { 2923 txd = &sc->ale_cdata.ale_txdesc[i]; 2924 if (txd->tx_m != NULL) { 2925 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2926 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2927 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2928 txd->tx_dmamap); 2929 m_freem(txd->tx_m); 2930 txd->tx_m = NULL; 2931 } 2932 } 2933 } 2934 2935 static void 2936 ale_stop_mac(struct ale_softc *sc) 2937 { 2938 uint32_t reg; 2939 int i; 2940 2941 ALE_LOCK_ASSERT(sc); 2942 2943 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2944 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 2945 reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 2946 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2947 } 2948 2949 for (i = ALE_TIMEOUT; i > 0; i--) { 2950 reg = CSR_READ_4(sc, ALE_IDLE_STATUS); 2951 if (reg == 0) 2952 break; 2953 DELAY(10); 2954 } 2955 if (i == 0) 2956 device_printf(sc->ale_dev, 2957 "could not disable Tx/Rx MAC(0x%08x)!\n", reg); 2958 } 2959 2960 static void 2961 ale_init_tx_ring(struct ale_softc *sc) 2962 { 2963 struct ale_txdesc *txd; 2964 int i; 2965 2966 ALE_LOCK_ASSERT(sc); 2967 2968 sc->ale_cdata.ale_tx_prod = 0; 2969 sc->ale_cdata.ale_tx_cons = 0; 2970 sc->ale_cdata.ale_tx_cnt = 0; 2971 2972 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ); 2973 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ); 2974 for (i = 0; i < ALE_TX_RING_CNT; i++) { 2975 txd = &sc->ale_cdata.ale_txdesc[i]; 2976 txd->tx_m = NULL; 2977 } 2978 *sc->ale_cdata.ale_tx_cmb = 0; 2979 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2980 sc->ale_cdata.ale_tx_cmb_map, 2981 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2982 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2983 sc->ale_cdata.ale_tx_ring_map, 2984 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2985 } 2986 2987 static void 2988 ale_init_rx_pages(struct ale_softc *sc) 2989 { 2990 struct ale_rx_page *rx_page; 2991 int i; 2992 2993 ALE_LOCK_ASSERT(sc); 2994 2995 atomic_set_int(&sc->ale_morework, 0); 2996 sc->ale_cdata.ale_rx_seqno = 0; 2997 sc->ale_cdata.ale_rx_curp = 0; 2998 2999 for (i = 0; i < ALE_RX_PAGES; i++) { 3000 rx_page = &sc->ale_cdata.ale_rx_page[i]; 3001 bzero(rx_page->page_addr, sc->ale_pagesize); 3002 bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ); 3003 rx_page->cons = 0; 3004 *rx_page->cmb_addr = 0; 3005 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 3006 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3007 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 3008 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 3009 } 3010 } 3011 3012 static void 3013 ale_rxvlan(struct ale_softc *sc) 3014 { 3015 struct ifnet *ifp; 3016 uint32_t reg; 3017 3018 ALE_LOCK_ASSERT(sc); 3019 3020 ifp = sc->ale_ifp; 3021 reg = CSR_READ_4(sc, ALE_MAC_CFG); 3022 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 3023 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3024 reg |= MAC_CFG_VLAN_TAG_STRIP; 3025 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 3026 } 3027 3028 static void 3029 ale_rxfilter(struct ale_softc *sc) 3030 { 3031 struct ifnet *ifp; 3032 struct ifmultiaddr *ifma; 3033 uint32_t crc; 3034 uint32_t mchash[2]; 3035 uint32_t rxcfg; 3036 3037 ALE_LOCK_ASSERT(sc); 3038 3039 ifp = sc->ale_ifp; 3040 3041 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); 3042 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3043 if ((ifp->if_flags & IFF_BROADCAST) != 0) 3044 rxcfg |= MAC_CFG_BCAST; 3045 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3046 if ((ifp->if_flags & IFF_PROMISC) != 0) 3047 rxcfg |= MAC_CFG_PROMISC; 3048 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3049 rxcfg |= MAC_CFG_ALLMULTI; 3050 CSR_WRITE_4(sc, ALE_MAR0, 0xFFFFFFFF); 3051 CSR_WRITE_4(sc, ALE_MAR1, 0xFFFFFFFF); 3052 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3053 return; 3054 } 3055 3056 /* Program new filter. */ 3057 bzero(mchash, sizeof(mchash)); 3058 3059 if_maddr_rlock(ifp); 3060 TAILQ_FOREACH(ifma, &sc->ale_ifp->if_multiaddrs, ifma_link) { 3061 if (ifma->ifma_addr->sa_family != AF_LINK) 3062 continue; 3063 crc = ether_crc32_be(LLADDR((struct sockaddr_dl *) 3064 ifma->ifma_addr), ETHER_ADDR_LEN); 3065 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3066 } 3067 if_maddr_runlock(ifp); 3068 3069 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); 3070 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); 3071 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3072 } 3073 3074 static int 3075 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3076 { 3077 int error, value; 3078 3079 if (arg1 == NULL) 3080 return (EINVAL); 3081 value = *(int *)arg1; 3082 error = sysctl_handle_int(oidp, &value, 0, req); 3083 if (error || req->newptr == NULL) 3084 return (error); 3085 if (value < low || value > high) 3086 return (EINVAL); 3087 *(int *)arg1 = value; 3088 3089 return (0); 3090 } 3091 3092 static int 3093 sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS) 3094 { 3095 return (sysctl_int_range(oidp, arg1, arg2, req, 3096 ALE_PROC_MIN, ALE_PROC_MAX)); 3097 } 3098 3099 static int 3100 sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS) 3101 { 3102 3103 return (sysctl_int_range(oidp, arg1, arg2, req, 3104 ALE_IM_TIMER_MIN, ALE_IM_TIMER_MAX)); 3105 } 3106