1 /*- 2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 */ 27 28 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ 29 30 #include <sys/cdefs.h> 31 __FBSDID("$FreeBSD$"); 32 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/kernel.h> 38 #include <sys/malloc.h> 39 #include <sys/mbuf.h> 40 #include <sys/module.h> 41 #include <sys/rman.h> 42 #include <sys/queue.h> 43 #include <sys/socket.h> 44 #include <sys/sockio.h> 45 #include <sys/sysctl.h> 46 #include <sys/taskqueue.h> 47 48 #include <net/bpf.h> 49 #include <net/if.h> 50 #include <net/if_arp.h> 51 #include <net/ethernet.h> 52 #include <net/if_dl.h> 53 #include <net/if_llc.h> 54 #include <net/if_media.h> 55 #include <net/if_types.h> 56 #include <net/if_vlan_var.h> 57 58 #include <netinet/in.h> 59 #include <netinet/in_systm.h> 60 #include <netinet/ip.h> 61 #include <netinet/tcp.h> 62 63 #include <dev/mii/mii.h> 64 #include <dev/mii/miivar.h> 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 69 #include <machine/atomic.h> 70 #include <machine/bus.h> 71 #include <machine/in_cksum.h> 72 73 #include <dev/ale/if_alereg.h> 74 #include <dev/ale/if_alevar.h> 75 76 /* "device miibus" required. See GENERIC if you get errors here. */ 77 #include "miibus_if.h" 78 79 /* For more information about Tx checksum offload issues see ale_encap(). */ 80 #define ALE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 81 #ifndef IFCAP_VLAN_HWTSO 82 #define IFCAP_VLAN_HWTSO 0 83 #endif 84 85 MODULE_DEPEND(ale, pci, 1, 1, 1); 86 MODULE_DEPEND(ale, ether, 1, 1, 1); 87 MODULE_DEPEND(ale, miibus, 1, 1, 1); 88 89 /* Tunables. */ 90 static int msi_disable = 0; 91 static int msix_disable = 0; 92 TUNABLE_INT("hw.ale.msi_disable", &msi_disable); 93 TUNABLE_INT("hw.ale.msix_disable", &msix_disable); 94 95 /* 96 * Devices supported by this driver. 97 */ 98 static struct ale_dev { 99 uint16_t ale_vendorid; 100 uint16_t ale_deviceid; 101 const char *ale_name; 102 } ale_devs[] = { 103 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR81XX, 104 "Atheros AR8121/AR8113/AR8114 PCIe Ethernet" }, 105 }; 106 107 static int ale_attach(device_t); 108 static int ale_check_boundary(struct ale_softc *); 109 static int ale_detach(device_t); 110 static int ale_dma_alloc(struct ale_softc *); 111 static void ale_dma_free(struct ale_softc *); 112 static void ale_dmamap_cb(void *, bus_dma_segment_t *, int, int); 113 static int ale_encap(struct ale_softc *, struct mbuf **); 114 static void ale_get_macaddr(struct ale_softc *); 115 static void ale_init(void *); 116 static void ale_init_locked(struct ale_softc *); 117 static void ale_init_rx_pages(struct ale_softc *); 118 static void ale_init_tx_ring(struct ale_softc *); 119 static void ale_int_task(void *, int); 120 static int ale_intr(void *); 121 static int ale_ioctl(struct ifnet *, u_long, caddr_t); 122 static void ale_link_task(void *, int); 123 static void ale_mac_config(struct ale_softc *); 124 static int ale_miibus_readreg(device_t, int, int); 125 static void ale_miibus_statchg(device_t); 126 static int ale_miibus_writereg(device_t, int, int, int); 127 static int ale_mediachange(struct ifnet *); 128 static void ale_mediastatus(struct ifnet *, struct ifmediareq *); 129 static void ale_phy_reset(struct ale_softc *); 130 static int ale_probe(device_t); 131 static void ale_reset(struct ale_softc *); 132 static int ale_resume(device_t); 133 static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, 134 uint32_t, uint32_t *); 135 static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); 136 static int ale_rxeof(struct ale_softc *sc, int); 137 static void ale_rxfilter(struct ale_softc *); 138 static void ale_rxvlan(struct ale_softc *); 139 static void ale_setlinkspeed(struct ale_softc *); 140 static void ale_setwol(struct ale_softc *); 141 static int ale_shutdown(device_t); 142 static void ale_start(struct ifnet *); 143 static void ale_stats_clear(struct ale_softc *); 144 static void ale_stats_update(struct ale_softc *); 145 static void ale_stop(struct ale_softc *); 146 static void ale_stop_mac(struct ale_softc *); 147 static int ale_suspend(device_t); 148 static void ale_sysctl_node(struct ale_softc *); 149 static void ale_tick(void *); 150 static void ale_tx_task(void *, int); 151 static void ale_txeof(struct ale_softc *); 152 static void ale_watchdog(struct ale_softc *); 153 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 154 static int sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS); 155 static int sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS); 156 157 static device_method_t ale_methods[] = { 158 /* Device interface. */ 159 DEVMETHOD(device_probe, ale_probe), 160 DEVMETHOD(device_attach, ale_attach), 161 DEVMETHOD(device_detach, ale_detach), 162 DEVMETHOD(device_shutdown, ale_shutdown), 163 DEVMETHOD(device_suspend, ale_suspend), 164 DEVMETHOD(device_resume, ale_resume), 165 166 /* MII interface. */ 167 DEVMETHOD(miibus_readreg, ale_miibus_readreg), 168 DEVMETHOD(miibus_writereg, ale_miibus_writereg), 169 DEVMETHOD(miibus_statchg, ale_miibus_statchg), 170 171 { NULL, NULL } 172 }; 173 174 static driver_t ale_driver = { 175 "ale", 176 ale_methods, 177 sizeof(struct ale_softc) 178 }; 179 180 static devclass_t ale_devclass; 181 182 DRIVER_MODULE(ale, pci, ale_driver, ale_devclass, 0, 0); 183 DRIVER_MODULE(miibus, ale, miibus_driver, miibus_devclass, 0, 0); 184 185 static struct resource_spec ale_res_spec_mem[] = { 186 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 187 { -1, 0, 0 } 188 }; 189 190 static struct resource_spec ale_irq_spec_legacy[] = { 191 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 192 { -1, 0, 0 } 193 }; 194 195 static struct resource_spec ale_irq_spec_msi[] = { 196 { SYS_RES_IRQ, 1, RF_ACTIVE }, 197 { -1, 0, 0 } 198 }; 199 200 static struct resource_spec ale_irq_spec_msix[] = { 201 { SYS_RES_IRQ, 1, RF_ACTIVE }, 202 { -1, 0, 0 } 203 }; 204 205 static int 206 ale_miibus_readreg(device_t dev, int phy, int reg) 207 { 208 struct ale_softc *sc; 209 uint32_t v; 210 int i; 211 212 sc = device_get_softc(dev); 213 214 if (phy != sc->ale_phyaddr) 215 return (0); 216 217 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 218 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 219 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 220 DELAY(5); 221 v = CSR_READ_4(sc, ALE_MDIO); 222 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 223 break; 224 } 225 226 if (i == 0) { 227 device_printf(sc->ale_dev, "phy read timeout : %d\n", reg); 228 return (0); 229 } 230 231 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 232 } 233 234 static int 235 ale_miibus_writereg(device_t dev, int phy, int reg, int val) 236 { 237 struct ale_softc *sc; 238 uint32_t v; 239 int i; 240 241 sc = device_get_softc(dev); 242 243 if (phy != sc->ale_phyaddr) 244 return (0); 245 246 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 247 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 248 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 249 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 250 DELAY(5); 251 v = CSR_READ_4(sc, ALE_MDIO); 252 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 253 break; 254 } 255 256 if (i == 0) 257 device_printf(sc->ale_dev, "phy write timeout : %d\n", reg); 258 259 return (0); 260 } 261 262 static void 263 ale_miibus_statchg(device_t dev) 264 { 265 struct ale_softc *sc; 266 267 sc = device_get_softc(dev); 268 269 taskqueue_enqueue(taskqueue_swi, &sc->ale_link_task); 270 } 271 272 static void 273 ale_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 274 { 275 struct ale_softc *sc; 276 struct mii_data *mii; 277 278 sc = ifp->if_softc; 279 ALE_LOCK(sc); 280 mii = device_get_softc(sc->ale_miibus); 281 282 mii_pollstat(mii); 283 ALE_UNLOCK(sc); 284 ifmr->ifm_status = mii->mii_media_status; 285 ifmr->ifm_active = mii->mii_media_active; 286 } 287 288 static int 289 ale_mediachange(struct ifnet *ifp) 290 { 291 struct ale_softc *sc; 292 struct mii_data *mii; 293 struct mii_softc *miisc; 294 int error; 295 296 sc = ifp->if_softc; 297 ALE_LOCK(sc); 298 mii = device_get_softc(sc->ale_miibus); 299 if (mii->mii_instance != 0) { 300 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 301 mii_phy_reset(miisc); 302 } 303 error = mii_mediachg(mii); 304 ALE_UNLOCK(sc); 305 306 return (error); 307 } 308 309 static int 310 ale_probe(device_t dev) 311 { 312 struct ale_dev *sp; 313 int i; 314 uint16_t vendor, devid; 315 316 vendor = pci_get_vendor(dev); 317 devid = pci_get_device(dev); 318 sp = ale_devs; 319 for (i = 0; i < sizeof(ale_devs) / sizeof(ale_devs[0]); i++) { 320 if (vendor == sp->ale_vendorid && 321 devid == sp->ale_deviceid) { 322 device_set_desc(dev, sp->ale_name); 323 return (BUS_PROBE_DEFAULT); 324 } 325 sp++; 326 } 327 328 return (ENXIO); 329 } 330 331 static void 332 ale_get_macaddr(struct ale_softc *sc) 333 { 334 uint32_t ea[2], reg; 335 int i, vpdc; 336 337 reg = CSR_READ_4(sc, ALE_SPI_CTRL); 338 if ((reg & SPI_VPD_ENB) != 0) { 339 reg &= ~SPI_VPD_ENB; 340 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); 341 } 342 343 if (pci_find_extcap(sc->ale_dev, PCIY_VPD, &vpdc) == 0) { 344 /* 345 * PCI VPD capability found, let TWSI reload EEPROM. 346 * This will set ethernet address of controller. 347 */ 348 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | 349 TWSI_CTRL_SW_LD_START); 350 for (i = 100; i > 0; i--) { 351 DELAY(1000); 352 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); 353 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 354 break; 355 } 356 if (i == 0) 357 device_printf(sc->ale_dev, 358 "reloading EEPROM timeout!\n"); 359 } else { 360 if (bootverbose) 361 device_printf(sc->ale_dev, 362 "PCI VPD capability not found!\n"); 363 } 364 365 ea[0] = CSR_READ_4(sc, ALE_PAR0); 366 ea[1] = CSR_READ_4(sc, ALE_PAR1); 367 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; 368 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; 369 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; 370 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; 371 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; 372 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; 373 } 374 375 static void 376 ale_phy_reset(struct ale_softc *sc) 377 { 378 379 /* Reset magic from Linux. */ 380 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 381 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 382 GPHY_CTRL_PHY_PLL_ON); 383 DELAY(1000); 384 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 385 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | 386 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); 387 DELAY(1000); 388 } 389 390 static int 391 ale_attach(device_t dev) 392 { 393 struct ale_softc *sc; 394 struct ifnet *ifp; 395 uint16_t burst; 396 int error, i, msic, msixc, pmc; 397 uint32_t rxf_len, txf_len; 398 399 error = 0; 400 sc = device_get_softc(dev); 401 sc->ale_dev = dev; 402 403 mtx_init(&sc->ale_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 404 MTX_DEF); 405 callout_init_mtx(&sc->ale_tick_ch, &sc->ale_mtx, 0); 406 TASK_INIT(&sc->ale_int_task, 0, ale_int_task, sc); 407 TASK_INIT(&sc->ale_link_task, 0, ale_link_task, sc); 408 409 /* Map the device. */ 410 pci_enable_busmaster(dev); 411 sc->ale_res_spec = ale_res_spec_mem; 412 sc->ale_irq_spec = ale_irq_spec_legacy; 413 error = bus_alloc_resources(dev, sc->ale_res_spec, sc->ale_res); 414 if (error != 0) { 415 device_printf(dev, "cannot allocate memory resources.\n"); 416 goto fail; 417 } 418 419 /* Set PHY address. */ 420 sc->ale_phyaddr = ALE_PHY_ADDR; 421 422 /* Reset PHY. */ 423 ale_phy_reset(sc); 424 425 /* Reset the ethernet controller. */ 426 ale_reset(sc); 427 428 /* Get PCI and chip id/revision. */ 429 sc->ale_rev = pci_get_revid(dev); 430 if (sc->ale_rev >= 0xF0) { 431 /* L2E Rev. B. AR8114 */ 432 sc->ale_flags |= ALE_FLAG_FASTETHER; 433 } else { 434 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { 435 /* L1E AR8121 */ 436 sc->ale_flags |= ALE_FLAG_JUMBO; 437 } else { 438 /* L2E Rev. A. AR8113 */ 439 sc->ale_flags |= ALE_FLAG_FASTETHER; 440 } 441 } 442 /* 443 * All known controllers seems to require 4 bytes alignment 444 * of Tx buffers to make Tx checksum offload with custom 445 * checksum generation method work. 446 */ 447 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; 448 /* 449 * All known controllers seems to have issues on Rx checksum 450 * offload for fragmented IP datagrams. 451 */ 452 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; 453 /* 454 * Don't use Tx CMB. It is known to cause RRS update failure 455 * under certain circumstances. Typical phenomenon of the 456 * issue would be unexpected sequence number encountered in 457 * Rx handler. 458 */ 459 sc->ale_flags |= ALE_FLAG_TXCMB_BUG; 460 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> 461 MASTER_CHIP_REV_SHIFT; 462 if (bootverbose) { 463 device_printf(dev, "PCI device revision : 0x%04x\n", 464 sc->ale_rev); 465 device_printf(dev, "Chip id/revision : 0x%04x\n", 466 sc->ale_chip_rev); 467 } 468 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); 469 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 470 /* 471 * Uninitialized hardware returns an invalid chip id/revision 472 * as well as 0xFFFFFFFF for Tx/Rx fifo length. 473 */ 474 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || 475 rxf_len == 0xFFFFFFF) { 476 device_printf(dev,"chip revision : 0x%04x, %u Tx FIFO " 477 "%u Rx FIFO -- not initialized?\n", sc->ale_chip_rev, 478 txf_len, rxf_len); 479 error = ENXIO; 480 goto fail; 481 } 482 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", txf_len, rxf_len); 483 484 /* Allocate IRQ resources. */ 485 msixc = pci_msix_count(dev); 486 msic = pci_msi_count(dev); 487 if (bootverbose) { 488 device_printf(dev, "MSIX count : %d\n", msixc); 489 device_printf(dev, "MSI count : %d\n", msic); 490 } 491 492 /* Prefer MSIX over MSI. */ 493 if (msix_disable == 0 || msi_disable == 0) { 494 if (msix_disable == 0 && msixc == ALE_MSIX_MESSAGES && 495 pci_alloc_msix(dev, &msixc) == 0) { 496 if (msic == ALE_MSIX_MESSAGES) { 497 device_printf(dev, "Using %d MSIX messages.\n", 498 msixc); 499 sc->ale_flags |= ALE_FLAG_MSIX; 500 sc->ale_irq_spec = ale_irq_spec_msix; 501 } else 502 pci_release_msi(dev); 503 } 504 if (msi_disable == 0 && (sc->ale_flags & ALE_FLAG_MSIX) == 0 && 505 msic == ALE_MSI_MESSAGES && 506 pci_alloc_msi(dev, &msic) == 0) { 507 if (msic == ALE_MSI_MESSAGES) { 508 device_printf(dev, "Using %d MSI messages.\n", 509 msic); 510 sc->ale_flags |= ALE_FLAG_MSI; 511 sc->ale_irq_spec = ale_irq_spec_msi; 512 } else 513 pci_release_msi(dev); 514 } 515 } 516 517 error = bus_alloc_resources(dev, sc->ale_irq_spec, sc->ale_irq); 518 if (error != 0) { 519 device_printf(dev, "cannot allocate IRQ resources.\n"); 520 goto fail; 521 } 522 523 /* Get DMA parameters from PCIe device control register. */ 524 if (pci_find_extcap(dev, PCIY_EXPRESS, &i) == 0) { 525 sc->ale_flags |= ALE_FLAG_PCIE; 526 burst = pci_read_config(dev, i + 0x08, 2); 527 /* Max read request size. */ 528 sc->ale_dma_rd_burst = ((burst >> 12) & 0x07) << 529 DMA_CFG_RD_BURST_SHIFT; 530 /* Max payload size. */ 531 sc->ale_dma_wr_burst = ((burst >> 5) & 0x07) << 532 DMA_CFG_WR_BURST_SHIFT; 533 if (bootverbose) { 534 device_printf(dev, "Read request size : %d bytes.\n", 535 128 << ((burst >> 12) & 0x07)); 536 device_printf(dev, "TLP payload size : %d bytes.\n", 537 128 << ((burst >> 5) & 0x07)); 538 } 539 } else { 540 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; 541 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; 542 } 543 544 /* Create device sysctl node. */ 545 ale_sysctl_node(sc); 546 547 if ((error = ale_dma_alloc(sc) != 0)) 548 goto fail; 549 550 /* Load station address. */ 551 ale_get_macaddr(sc); 552 553 ifp = sc->ale_ifp = if_alloc(IFT_ETHER); 554 if (ifp == NULL) { 555 device_printf(dev, "cannot allocate ifnet structure.\n"); 556 error = ENXIO; 557 goto fail; 558 } 559 560 ifp->if_softc = sc; 561 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 562 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 563 ifp->if_ioctl = ale_ioctl; 564 ifp->if_start = ale_start; 565 ifp->if_init = ale_init; 566 ifp->if_snd.ifq_drv_maxlen = ALE_TX_RING_CNT - 1; 567 IFQ_SET_MAXLEN(&ifp->if_snd, ifp->if_snd.ifq_drv_maxlen); 568 IFQ_SET_READY(&ifp->if_snd); 569 ifp->if_capabilities = IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4; 570 ifp->if_hwassist = ALE_CSUM_FEATURES | CSUM_TSO; 571 if (pci_find_extcap(dev, PCIY_PMG, &pmc) == 0) { 572 sc->ale_flags |= ALE_FLAG_PMCAP; 573 ifp->if_capabilities |= IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST; 574 } 575 ifp->if_capenable = ifp->if_capabilities; 576 577 /* Set up MII bus. */ 578 if ((error = mii_phy_probe(dev, &sc->ale_miibus, ale_mediachange, 579 ale_mediastatus)) != 0) { 580 device_printf(dev, "no PHY found!\n"); 581 goto fail; 582 } 583 584 ether_ifattach(ifp, sc->ale_eaddr); 585 586 /* VLAN capability setup. */ 587 ifp->if_capabilities |= IFCAP_VLAN_MTU; 588 ifp->if_capabilities |= IFCAP_VLAN_HWTAGGING | IFCAP_VLAN_HWCSUM; 589 ifp->if_capenable = ifp->if_capabilities; 590 591 /* Tell the upper layer(s) we support long frames. */ 592 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 593 594 /* Create local taskq. */ 595 TASK_INIT(&sc->ale_tx_task, 1, ale_tx_task, ifp); 596 sc->ale_tq = taskqueue_create_fast("ale_taskq", M_WAITOK, 597 taskqueue_thread_enqueue, &sc->ale_tq); 598 if (sc->ale_tq == NULL) { 599 device_printf(dev, "could not create taskqueue.\n"); 600 ether_ifdetach(ifp); 601 error = ENXIO; 602 goto fail; 603 } 604 taskqueue_start_threads(&sc->ale_tq, 1, PI_NET, "%s taskq", 605 device_get_nameunit(sc->ale_dev)); 606 607 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 608 msic = ALE_MSIX_MESSAGES; 609 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 610 msic = ALE_MSI_MESSAGES; 611 else 612 msic = 1; 613 for (i = 0; i < msic; i++) { 614 error = bus_setup_intr(dev, sc->ale_irq[i], 615 INTR_TYPE_NET | INTR_MPSAFE, ale_intr, NULL, sc, 616 &sc->ale_intrhand[i]); 617 if (error != 0) 618 break; 619 } 620 if (error != 0) { 621 device_printf(dev, "could not set up interrupt handler.\n"); 622 taskqueue_free(sc->ale_tq); 623 sc->ale_tq = NULL; 624 ether_ifdetach(ifp); 625 goto fail; 626 } 627 628 fail: 629 if (error != 0) 630 ale_detach(dev); 631 632 return (error); 633 } 634 635 static int 636 ale_detach(device_t dev) 637 { 638 struct ale_softc *sc; 639 struct ifnet *ifp; 640 int i, msic; 641 642 sc = device_get_softc(dev); 643 644 ifp = sc->ale_ifp; 645 if (device_is_attached(dev)) { 646 ALE_LOCK(sc); 647 sc->ale_flags |= ALE_FLAG_DETACH; 648 ale_stop(sc); 649 ALE_UNLOCK(sc); 650 callout_drain(&sc->ale_tick_ch); 651 taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 652 taskqueue_drain(sc->ale_tq, &sc->ale_tx_task); 653 taskqueue_drain(taskqueue_swi, &sc->ale_link_task); 654 ether_ifdetach(ifp); 655 } 656 657 if (sc->ale_tq != NULL) { 658 taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 659 taskqueue_free(sc->ale_tq); 660 sc->ale_tq = NULL; 661 } 662 663 if (sc->ale_miibus != NULL) { 664 device_delete_child(dev, sc->ale_miibus); 665 sc->ale_miibus = NULL; 666 } 667 bus_generic_detach(dev); 668 ale_dma_free(sc); 669 670 if (ifp != NULL) { 671 if_free(ifp); 672 sc->ale_ifp = NULL; 673 } 674 675 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 676 msic = ALE_MSIX_MESSAGES; 677 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 678 msic = ALE_MSI_MESSAGES; 679 else 680 msic = 1; 681 for (i = 0; i < msic; i++) { 682 if (sc->ale_intrhand[i] != NULL) { 683 bus_teardown_intr(dev, sc->ale_irq[i], 684 sc->ale_intrhand[i]); 685 sc->ale_intrhand[i] = NULL; 686 } 687 } 688 689 bus_release_resources(dev, sc->ale_irq_spec, sc->ale_irq); 690 if ((sc->ale_flags & (ALE_FLAG_MSI | ALE_FLAG_MSIX)) != 0) 691 pci_release_msi(dev); 692 bus_release_resources(dev, sc->ale_res_spec, sc->ale_res); 693 mtx_destroy(&sc->ale_mtx); 694 695 return (0); 696 } 697 698 #define ALE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 699 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 700 701 #if __FreeBSD_version > 800000 702 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 703 SYSCTL_ADD_QUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 704 #else 705 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 706 SYSCTL_ADD_ULONG(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 707 #endif 708 709 static void 710 ale_sysctl_node(struct ale_softc *sc) 711 { 712 struct sysctl_ctx_list *ctx; 713 struct sysctl_oid_list *child, *parent; 714 struct sysctl_oid *tree; 715 struct ale_hw_stats *stats; 716 int error; 717 718 stats = &sc->ale_stats; 719 ctx = device_get_sysctl_ctx(sc->ale_dev); 720 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ale_dev)); 721 722 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 723 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_rx_mod, 0, 724 sysctl_hw_ale_int_mod, "I", "ale Rx interrupt moderation"); 725 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 726 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_int_tx_mod, 0, 727 sysctl_hw_ale_int_mod, "I", "ale Tx interrupt moderation"); 728 /* Pull in device tunables. */ 729 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 730 error = resource_int_value(device_get_name(sc->ale_dev), 731 device_get_unit(sc->ale_dev), "int_rx_mod", &sc->ale_int_rx_mod); 732 if (error == 0) { 733 if (sc->ale_int_rx_mod < ALE_IM_TIMER_MIN || 734 sc->ale_int_rx_mod > ALE_IM_TIMER_MAX) { 735 device_printf(sc->ale_dev, "int_rx_mod value out of " 736 "range; using default: %d\n", 737 ALE_IM_RX_TIMER_DEFAULT); 738 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 739 } 740 } 741 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 742 error = resource_int_value(device_get_name(sc->ale_dev), 743 device_get_unit(sc->ale_dev), "int_tx_mod", &sc->ale_int_tx_mod); 744 if (error == 0) { 745 if (sc->ale_int_tx_mod < ALE_IM_TIMER_MIN || 746 sc->ale_int_tx_mod > ALE_IM_TIMER_MAX) { 747 device_printf(sc->ale_dev, "int_tx_mod value out of " 748 "range; using default: %d\n", 749 ALE_IM_TX_TIMER_DEFAULT); 750 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 751 } 752 } 753 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 754 CTLTYPE_INT | CTLFLAG_RW, &sc->ale_process_limit, 0, 755 sysctl_hw_ale_proc_limit, "I", 756 "max number of Rx events to process"); 757 /* Pull in device tunables. */ 758 sc->ale_process_limit = ALE_PROC_DEFAULT; 759 error = resource_int_value(device_get_name(sc->ale_dev), 760 device_get_unit(sc->ale_dev), "process_limit", 761 &sc->ale_process_limit); 762 if (error == 0) { 763 if (sc->ale_process_limit < ALE_PROC_MIN || 764 sc->ale_process_limit > ALE_PROC_MAX) { 765 device_printf(sc->ale_dev, 766 "process_limit value out of range; " 767 "using default: %d\n", ALE_PROC_DEFAULT); 768 sc->ale_process_limit = ALE_PROC_DEFAULT; 769 } 770 } 771 772 /* Misc statistics. */ 773 ALE_SYSCTL_STAT_ADD32(ctx, child, "reset_brk_seq", 774 &stats->reset_brk_seq, 775 "Controller resets due to broken Rx sequnce number"); 776 777 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD, 778 NULL, "ATE statistics"); 779 parent = SYSCTL_CHILDREN(tree); 780 781 /* Rx statistics. */ 782 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", CTLFLAG_RD, 783 NULL, "Rx MAC statistics"); 784 child = SYSCTL_CHILDREN(tree); 785 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 786 &stats->rx_frames, "Good frames"); 787 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 788 &stats->rx_bcast_frames, "Good broadcast frames"); 789 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 790 &stats->rx_mcast_frames, "Good multicast frames"); 791 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 792 &stats->rx_pause_frames, "Pause control frames"); 793 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 794 &stats->rx_control_frames, "Control frames"); 795 ALE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 796 &stats->rx_crcerrs, "CRC errors"); 797 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 798 &stats->rx_lenerrs, "Frames with length mismatched"); 799 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 800 &stats->rx_bytes, "Good octets"); 801 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 802 &stats->rx_bcast_bytes, "Good broadcast octets"); 803 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 804 &stats->rx_mcast_bytes, "Good multicast octets"); 805 ALE_SYSCTL_STAT_ADD32(ctx, child, "runts", 806 &stats->rx_runts, "Too short frames"); 807 ALE_SYSCTL_STAT_ADD32(ctx, child, "fragments", 808 &stats->rx_fragments, "Fragmented frames"); 809 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 810 &stats->rx_pkts_64, "64 bytes frames"); 811 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 812 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 813 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 814 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 815 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 816 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 817 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 818 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 819 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 820 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 821 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 822 &stats->rx_pkts_1519_max, "1519 to max frames"); 823 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 824 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 825 ALE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 826 &stats->rx_fifo_oflows, "FIFO overflows"); 827 ALE_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 828 &stats->rx_rrs_errs, "Return status write-back errors"); 829 ALE_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 830 &stats->rx_alignerrs, "Alignment errors"); 831 ALE_SYSCTL_STAT_ADD32(ctx, child, "filtered", 832 &stats->rx_pkts_filtered, 833 "Frames dropped due to address filtering"); 834 835 /* Tx statistics. */ 836 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD, 837 NULL, "Tx MAC statistics"); 838 child = SYSCTL_CHILDREN(tree); 839 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 840 &stats->tx_frames, "Good frames"); 841 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 842 &stats->tx_bcast_frames, "Good broadcast frames"); 843 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 844 &stats->tx_mcast_frames, "Good multicast frames"); 845 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 846 &stats->tx_pause_frames, "Pause control frames"); 847 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 848 &stats->tx_control_frames, "Control frames"); 849 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 850 &stats->tx_excess_defer, "Frames with excessive derferrals"); 851 ALE_SYSCTL_STAT_ADD32(ctx, child, "defers", 852 &stats->tx_excess_defer, "Frames with derferrals"); 853 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 854 &stats->tx_bytes, "Good octets"); 855 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 856 &stats->tx_bcast_bytes, "Good broadcast octets"); 857 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 858 &stats->tx_mcast_bytes, "Good multicast octets"); 859 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 860 &stats->tx_pkts_64, "64 bytes frames"); 861 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 862 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 863 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 864 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 865 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 866 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 867 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 868 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 869 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 870 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 871 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 872 &stats->tx_pkts_1519_max, "1519 to max frames"); 873 ALE_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 874 &stats->tx_single_colls, "Single collisions"); 875 ALE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 876 &stats->tx_multi_colls, "Multiple collisions"); 877 ALE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 878 &stats->tx_late_colls, "Late collisions"); 879 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 880 &stats->tx_excess_colls, "Excessive collisions"); 881 ALE_SYSCTL_STAT_ADD32(ctx, child, "abort", 882 &stats->tx_abort, "Aborted frames due to Excessive collisions"); 883 ALE_SYSCTL_STAT_ADD32(ctx, child, "underruns", 884 &stats->tx_underrun, "FIFO underruns"); 885 ALE_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 886 &stats->tx_desc_underrun, "Descriptor write-back errors"); 887 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 888 &stats->tx_lenerrs, "Frames with length mismatched"); 889 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 890 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 891 } 892 893 #undef ALE_SYSCTL_STAT_ADD32 894 #undef ALE_SYSCTL_STAT_ADD64 895 896 struct ale_dmamap_arg { 897 bus_addr_t ale_busaddr; 898 }; 899 900 static void 901 ale_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 902 { 903 struct ale_dmamap_arg *ctx; 904 905 if (error != 0) 906 return; 907 908 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 909 910 ctx = (struct ale_dmamap_arg *)arg; 911 ctx->ale_busaddr = segs[0].ds_addr; 912 } 913 914 /* 915 * Tx descriptors/RXF0/CMB DMA blocks share ALE_DESC_ADDR_HI register 916 * which specifies high address region of DMA blocks. Therefore these 917 * blocks should have the same high address of given 4GB address 918 * space(i.e. crossing 4GB boundary is not allowed). 919 */ 920 static int 921 ale_check_boundary(struct ale_softc *sc) 922 { 923 bus_addr_t rx_cmb_end[ALE_RX_PAGES], tx_cmb_end; 924 bus_addr_t rx_page_end[ALE_RX_PAGES], tx_ring_end; 925 926 rx_page_end[0] = sc->ale_cdata.ale_rx_page[0].page_paddr + 927 sc->ale_pagesize; 928 rx_page_end[1] = sc->ale_cdata.ale_rx_page[1].page_paddr + 929 sc->ale_pagesize; 930 tx_ring_end = sc->ale_cdata.ale_tx_ring_paddr + ALE_TX_RING_SZ; 931 tx_cmb_end = sc->ale_cdata.ale_tx_cmb_paddr + ALE_TX_CMB_SZ; 932 rx_cmb_end[0] = sc->ale_cdata.ale_rx_page[0].cmb_paddr + ALE_RX_CMB_SZ; 933 rx_cmb_end[1] = sc->ale_cdata.ale_rx_page[1].cmb_paddr + ALE_RX_CMB_SZ; 934 935 if ((ALE_ADDR_HI(tx_ring_end) != 936 ALE_ADDR_HI(sc->ale_cdata.ale_tx_ring_paddr)) || 937 (ALE_ADDR_HI(rx_page_end[0]) != 938 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].page_paddr)) || 939 (ALE_ADDR_HI(rx_page_end[1]) != 940 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].page_paddr)) || 941 (ALE_ADDR_HI(tx_cmb_end) != 942 ALE_ADDR_HI(sc->ale_cdata.ale_tx_cmb_paddr)) || 943 (ALE_ADDR_HI(rx_cmb_end[0]) != 944 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].cmb_paddr)) || 945 (ALE_ADDR_HI(rx_cmb_end[1]) != 946 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].cmb_paddr))) 947 return (EFBIG); 948 949 if ((ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[0])) || 950 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[1])) || 951 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[0])) || 952 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[1])) || 953 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(tx_cmb_end))) 954 return (EFBIG); 955 956 return (0); 957 } 958 959 static int 960 ale_dma_alloc(struct ale_softc *sc) 961 { 962 struct ale_txdesc *txd; 963 bus_addr_t lowaddr; 964 struct ale_dmamap_arg ctx; 965 int error, guard_size, i; 966 967 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 968 guard_size = ALE_JUMBO_FRAMELEN; 969 else 970 guard_size = ALE_MAX_FRAMELEN; 971 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, 972 ALE_RX_PAGE_ALIGN); 973 lowaddr = BUS_SPACE_MAXADDR; 974 again: 975 /* Create parent DMA tag. */ 976 error = bus_dma_tag_create( 977 bus_get_dma_tag(sc->ale_dev), /* parent */ 978 1, 0, /* alignment, boundary */ 979 lowaddr, /* lowaddr */ 980 BUS_SPACE_MAXADDR, /* highaddr */ 981 NULL, NULL, /* filter, filterarg */ 982 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 983 0, /* nsegments */ 984 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 985 0, /* flags */ 986 NULL, NULL, /* lockfunc, lockarg */ 987 &sc->ale_cdata.ale_parent_tag); 988 if (error != 0) { 989 device_printf(sc->ale_dev, 990 "could not create parent DMA tag.\n"); 991 goto fail; 992 } 993 994 /* Create DMA tag for Tx descriptor ring. */ 995 error = bus_dma_tag_create( 996 sc->ale_cdata.ale_parent_tag, /* parent */ 997 ALE_TX_RING_ALIGN, 0, /* alignment, boundary */ 998 BUS_SPACE_MAXADDR, /* lowaddr */ 999 BUS_SPACE_MAXADDR, /* highaddr */ 1000 NULL, NULL, /* filter, filterarg */ 1001 ALE_TX_RING_SZ, /* maxsize */ 1002 1, /* nsegments */ 1003 ALE_TX_RING_SZ, /* maxsegsize */ 1004 0, /* flags */ 1005 NULL, NULL, /* lockfunc, lockarg */ 1006 &sc->ale_cdata.ale_tx_ring_tag); 1007 if (error != 0) { 1008 device_printf(sc->ale_dev, 1009 "could not create Tx ring DMA tag.\n"); 1010 goto fail; 1011 } 1012 1013 /* Create DMA tag for Rx pages. */ 1014 for (i = 0; i < ALE_RX_PAGES; i++) { 1015 error = bus_dma_tag_create( 1016 sc->ale_cdata.ale_parent_tag, /* parent */ 1017 ALE_RX_PAGE_ALIGN, 0, /* alignment, boundary */ 1018 BUS_SPACE_MAXADDR, /* lowaddr */ 1019 BUS_SPACE_MAXADDR, /* highaddr */ 1020 NULL, NULL, /* filter, filterarg */ 1021 sc->ale_pagesize, /* maxsize */ 1022 1, /* nsegments */ 1023 sc->ale_pagesize, /* maxsegsize */ 1024 0, /* flags */ 1025 NULL, NULL, /* lockfunc, lockarg */ 1026 &sc->ale_cdata.ale_rx_page[i].page_tag); 1027 if (error != 0) { 1028 device_printf(sc->ale_dev, 1029 "could not create Rx page %d DMA tag.\n", i); 1030 goto fail; 1031 } 1032 } 1033 1034 /* Create DMA tag for Tx coalescing message block. */ 1035 error = bus_dma_tag_create( 1036 sc->ale_cdata.ale_parent_tag, /* parent */ 1037 ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1038 BUS_SPACE_MAXADDR, /* lowaddr */ 1039 BUS_SPACE_MAXADDR, /* highaddr */ 1040 NULL, NULL, /* filter, filterarg */ 1041 ALE_TX_CMB_SZ, /* maxsize */ 1042 1, /* nsegments */ 1043 ALE_TX_CMB_SZ, /* maxsegsize */ 1044 0, /* flags */ 1045 NULL, NULL, /* lockfunc, lockarg */ 1046 &sc->ale_cdata.ale_tx_cmb_tag); 1047 if (error != 0) { 1048 device_printf(sc->ale_dev, 1049 "could not create Tx CMB DMA tag.\n"); 1050 goto fail; 1051 } 1052 1053 /* Create DMA tag for Rx coalescing message block. */ 1054 for (i = 0; i < ALE_RX_PAGES; i++) { 1055 error = bus_dma_tag_create( 1056 sc->ale_cdata.ale_parent_tag, /* parent */ 1057 ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1058 BUS_SPACE_MAXADDR, /* lowaddr */ 1059 BUS_SPACE_MAXADDR, /* highaddr */ 1060 NULL, NULL, /* filter, filterarg */ 1061 ALE_RX_CMB_SZ, /* maxsize */ 1062 1, /* nsegments */ 1063 ALE_RX_CMB_SZ, /* maxsegsize */ 1064 0, /* flags */ 1065 NULL, NULL, /* lockfunc, lockarg */ 1066 &sc->ale_cdata.ale_rx_page[i].cmb_tag); 1067 if (error != 0) { 1068 device_printf(sc->ale_dev, 1069 "could not create Rx page %d CMB DMA tag.\n", i); 1070 goto fail; 1071 } 1072 } 1073 1074 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1075 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_ring_tag, 1076 (void **)&sc->ale_cdata.ale_tx_ring, 1077 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1078 &sc->ale_cdata.ale_tx_ring_map); 1079 if (error != 0) { 1080 device_printf(sc->ale_dev, 1081 "could not allocate DMA'able memory for Tx ring.\n"); 1082 goto fail; 1083 } 1084 ctx.ale_busaddr = 0; 1085 error = bus_dmamap_load(sc->ale_cdata.ale_tx_ring_tag, 1086 sc->ale_cdata.ale_tx_ring_map, sc->ale_cdata.ale_tx_ring, 1087 ALE_TX_RING_SZ, ale_dmamap_cb, &ctx, 0); 1088 if (error != 0 || ctx.ale_busaddr == 0) { 1089 device_printf(sc->ale_dev, 1090 "could not load DMA'able memory for Tx ring.\n"); 1091 goto fail; 1092 } 1093 sc->ale_cdata.ale_tx_ring_paddr = ctx.ale_busaddr; 1094 1095 /* Rx pages. */ 1096 for (i = 0; i < ALE_RX_PAGES; i++) { 1097 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].page_tag, 1098 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr, 1099 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1100 &sc->ale_cdata.ale_rx_page[i].page_map); 1101 if (error != 0) { 1102 device_printf(sc->ale_dev, 1103 "could not allocate DMA'able memory for " 1104 "Rx page %d.\n", i); 1105 goto fail; 1106 } 1107 ctx.ale_busaddr = 0; 1108 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].page_tag, 1109 sc->ale_cdata.ale_rx_page[i].page_map, 1110 sc->ale_cdata.ale_rx_page[i].page_addr, 1111 sc->ale_pagesize, ale_dmamap_cb, &ctx, 0); 1112 if (error != 0 || ctx.ale_busaddr == 0) { 1113 device_printf(sc->ale_dev, 1114 "could not load DMA'able memory for " 1115 "Rx page %d.\n", i); 1116 goto fail; 1117 } 1118 sc->ale_cdata.ale_rx_page[i].page_paddr = ctx.ale_busaddr; 1119 } 1120 1121 /* Tx CMB. */ 1122 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_cmb_tag, 1123 (void **)&sc->ale_cdata.ale_tx_cmb, 1124 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1125 &sc->ale_cdata.ale_tx_cmb_map); 1126 if (error != 0) { 1127 device_printf(sc->ale_dev, 1128 "could not allocate DMA'able memory for Tx CMB.\n"); 1129 goto fail; 1130 } 1131 ctx.ale_busaddr = 0; 1132 error = bus_dmamap_load(sc->ale_cdata.ale_tx_cmb_tag, 1133 sc->ale_cdata.ale_tx_cmb_map, sc->ale_cdata.ale_tx_cmb, 1134 ALE_TX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1135 if (error != 0 || ctx.ale_busaddr == 0) { 1136 device_printf(sc->ale_dev, 1137 "could not load DMA'able memory for Tx CMB.\n"); 1138 goto fail; 1139 } 1140 sc->ale_cdata.ale_tx_cmb_paddr = ctx.ale_busaddr; 1141 1142 /* Rx CMB. */ 1143 for (i = 0; i < ALE_RX_PAGES; i++) { 1144 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1145 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 1146 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1147 &sc->ale_cdata.ale_rx_page[i].cmb_map); 1148 if (error != 0) { 1149 device_printf(sc->ale_dev, "could not allocate " 1150 "DMA'able memory for Rx page %d CMB.\n", i); 1151 goto fail; 1152 } 1153 ctx.ale_busaddr = 0; 1154 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1155 sc->ale_cdata.ale_rx_page[i].cmb_map, 1156 sc->ale_cdata.ale_rx_page[i].cmb_addr, 1157 ALE_RX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1158 if (error != 0 || ctx.ale_busaddr == 0) { 1159 device_printf(sc->ale_dev, "could not load DMA'able " 1160 "memory for Rx page %d CMB.\n", i); 1161 goto fail; 1162 } 1163 sc->ale_cdata.ale_rx_page[i].cmb_paddr = ctx.ale_busaddr; 1164 } 1165 1166 /* 1167 * Tx descriptors/RXF0/CMB DMA blocks share the same 1168 * high address region of 64bit DMA address space. 1169 */ 1170 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1171 (error = ale_check_boundary(sc)) != 0) { 1172 device_printf(sc->ale_dev, "4GB boundary crossed, " 1173 "switching to 32bit DMA addressing mode.\n"); 1174 ale_dma_free(sc); 1175 /* 1176 * Limit max allowable DMA address space to 32bit 1177 * and try again. 1178 */ 1179 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1180 goto again; 1181 } 1182 1183 /* 1184 * Create Tx buffer parent tag. 1185 * AR81xx allows 64bit DMA addressing of Tx buffers so it 1186 * needs separate parent DMA tag as parent DMA address space 1187 * could be restricted to be within 32bit address space by 1188 * 4GB boundary crossing. 1189 */ 1190 error = bus_dma_tag_create( 1191 bus_get_dma_tag(sc->ale_dev), /* parent */ 1192 1, 0, /* alignment, boundary */ 1193 BUS_SPACE_MAXADDR, /* lowaddr */ 1194 BUS_SPACE_MAXADDR, /* highaddr */ 1195 NULL, NULL, /* filter, filterarg */ 1196 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1197 0, /* nsegments */ 1198 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1199 0, /* flags */ 1200 NULL, NULL, /* lockfunc, lockarg */ 1201 &sc->ale_cdata.ale_buffer_tag); 1202 if (error != 0) { 1203 device_printf(sc->ale_dev, 1204 "could not create parent buffer DMA tag.\n"); 1205 goto fail; 1206 } 1207 1208 /* Create DMA tag for Tx buffers. */ 1209 error = bus_dma_tag_create( 1210 sc->ale_cdata.ale_buffer_tag, /* parent */ 1211 1, 0, /* alignment, boundary */ 1212 BUS_SPACE_MAXADDR, /* lowaddr */ 1213 BUS_SPACE_MAXADDR, /* highaddr */ 1214 NULL, NULL, /* filter, filterarg */ 1215 ALE_TSO_MAXSIZE, /* maxsize */ 1216 ALE_MAXTXSEGS, /* nsegments */ 1217 ALE_TSO_MAXSEGSIZE, /* maxsegsize */ 1218 0, /* flags */ 1219 NULL, NULL, /* lockfunc, lockarg */ 1220 &sc->ale_cdata.ale_tx_tag); 1221 if (error != 0) { 1222 device_printf(sc->ale_dev, "could not create Tx DMA tag.\n"); 1223 goto fail; 1224 } 1225 1226 /* Create DMA maps for Tx buffers. */ 1227 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1228 txd = &sc->ale_cdata.ale_txdesc[i]; 1229 txd->tx_m = NULL; 1230 txd->tx_dmamap = NULL; 1231 error = bus_dmamap_create(sc->ale_cdata.ale_tx_tag, 0, 1232 &txd->tx_dmamap); 1233 if (error != 0) { 1234 device_printf(sc->ale_dev, 1235 "could not create Tx dmamap.\n"); 1236 goto fail; 1237 } 1238 } 1239 1240 fail: 1241 return (error); 1242 } 1243 1244 static void 1245 ale_dma_free(struct ale_softc *sc) 1246 { 1247 struct ale_txdesc *txd; 1248 int i; 1249 1250 /* Tx buffers. */ 1251 if (sc->ale_cdata.ale_tx_tag != NULL) { 1252 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1253 txd = &sc->ale_cdata.ale_txdesc[i]; 1254 if (txd->tx_dmamap != NULL) { 1255 bus_dmamap_destroy(sc->ale_cdata.ale_tx_tag, 1256 txd->tx_dmamap); 1257 txd->tx_dmamap = NULL; 1258 } 1259 } 1260 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_tag); 1261 sc->ale_cdata.ale_tx_tag = NULL; 1262 } 1263 /* Tx descriptor ring. */ 1264 if (sc->ale_cdata.ale_tx_ring_tag != NULL) { 1265 if (sc->ale_cdata.ale_tx_ring_map != NULL) 1266 bus_dmamap_unload(sc->ale_cdata.ale_tx_ring_tag, 1267 sc->ale_cdata.ale_tx_ring_map); 1268 if (sc->ale_cdata.ale_tx_ring_map != NULL && 1269 sc->ale_cdata.ale_tx_ring != NULL) 1270 bus_dmamem_free(sc->ale_cdata.ale_tx_ring_tag, 1271 sc->ale_cdata.ale_tx_ring, 1272 sc->ale_cdata.ale_tx_ring_map); 1273 sc->ale_cdata.ale_tx_ring = NULL; 1274 sc->ale_cdata.ale_tx_ring_map = NULL; 1275 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_ring_tag); 1276 sc->ale_cdata.ale_tx_ring_tag = NULL; 1277 } 1278 /* Rx page block. */ 1279 for (i = 0; i < ALE_RX_PAGES; i++) { 1280 if (sc->ale_cdata.ale_rx_page[i].page_tag != NULL) { 1281 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL) 1282 bus_dmamap_unload( 1283 sc->ale_cdata.ale_rx_page[i].page_tag, 1284 sc->ale_cdata.ale_rx_page[i].page_map); 1285 if (sc->ale_cdata.ale_rx_page[i].page_map != NULL && 1286 sc->ale_cdata.ale_rx_page[i].page_addr != NULL) 1287 bus_dmamem_free( 1288 sc->ale_cdata.ale_rx_page[i].page_tag, 1289 sc->ale_cdata.ale_rx_page[i].page_addr, 1290 sc->ale_cdata.ale_rx_page[i].page_map); 1291 sc->ale_cdata.ale_rx_page[i].page_addr = NULL; 1292 sc->ale_cdata.ale_rx_page[i].page_map = NULL; 1293 bus_dma_tag_destroy( 1294 sc->ale_cdata.ale_rx_page[i].page_tag); 1295 sc->ale_cdata.ale_rx_page[i].page_tag = NULL; 1296 } 1297 } 1298 /* Rx CMB. */ 1299 for (i = 0; i < ALE_RX_PAGES; i++) { 1300 if (sc->ale_cdata.ale_rx_page[i].cmb_tag != NULL) { 1301 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL) 1302 bus_dmamap_unload( 1303 sc->ale_cdata.ale_rx_page[i].cmb_tag, 1304 sc->ale_cdata.ale_rx_page[i].cmb_map); 1305 if (sc->ale_cdata.ale_rx_page[i].cmb_map != NULL && 1306 sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) 1307 bus_dmamem_free( 1308 sc->ale_cdata.ale_rx_page[i].cmb_tag, 1309 sc->ale_cdata.ale_rx_page[i].cmb_addr, 1310 sc->ale_cdata.ale_rx_page[i].cmb_map); 1311 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; 1312 sc->ale_cdata.ale_rx_page[i].cmb_map = NULL; 1313 bus_dma_tag_destroy( 1314 sc->ale_cdata.ale_rx_page[i].cmb_tag); 1315 sc->ale_cdata.ale_rx_page[i].cmb_tag = NULL; 1316 } 1317 } 1318 /* Tx CMB. */ 1319 if (sc->ale_cdata.ale_tx_cmb_tag != NULL) { 1320 if (sc->ale_cdata.ale_tx_cmb_map != NULL) 1321 bus_dmamap_unload(sc->ale_cdata.ale_tx_cmb_tag, 1322 sc->ale_cdata.ale_tx_cmb_map); 1323 if (sc->ale_cdata.ale_tx_cmb_map != NULL && 1324 sc->ale_cdata.ale_tx_cmb != NULL) 1325 bus_dmamem_free(sc->ale_cdata.ale_tx_cmb_tag, 1326 sc->ale_cdata.ale_tx_cmb, 1327 sc->ale_cdata.ale_tx_cmb_map); 1328 sc->ale_cdata.ale_tx_cmb = NULL; 1329 sc->ale_cdata.ale_tx_cmb_map = NULL; 1330 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_cmb_tag); 1331 sc->ale_cdata.ale_tx_cmb_tag = NULL; 1332 } 1333 if (sc->ale_cdata.ale_buffer_tag != NULL) { 1334 bus_dma_tag_destroy(sc->ale_cdata.ale_buffer_tag); 1335 sc->ale_cdata.ale_buffer_tag = NULL; 1336 } 1337 if (sc->ale_cdata.ale_parent_tag != NULL) { 1338 bus_dma_tag_destroy(sc->ale_cdata.ale_parent_tag); 1339 sc->ale_cdata.ale_parent_tag = NULL; 1340 } 1341 } 1342 1343 static int 1344 ale_shutdown(device_t dev) 1345 { 1346 1347 return (ale_suspend(dev)); 1348 } 1349 1350 /* 1351 * Note, this driver resets the link speed to 10/100Mbps by 1352 * restarting auto-negotiation in suspend/shutdown phase but we 1353 * don't know whether that auto-negotiation would succeed or not 1354 * as driver has no control after powering off/suspend operation. 1355 * If the renegotiation fail WOL may not work. Running at 1Gbps 1356 * will draw more power than 375mA at 3.3V which is specified in 1357 * PCI specification and that would result in complete 1358 * shutdowning power to ethernet controller. 1359 * 1360 * TODO 1361 * Save current negotiated media speed/duplex/flow-control to 1362 * softc and restore the same link again after resuming. PHY 1363 * handling such as power down/resetting to 100Mbps may be better 1364 * handled in suspend method in phy driver. 1365 */ 1366 static void 1367 ale_setlinkspeed(struct ale_softc *sc) 1368 { 1369 struct mii_data *mii; 1370 int aneg, i; 1371 1372 mii = device_get_softc(sc->ale_miibus); 1373 mii_pollstat(mii); 1374 aneg = 0; 1375 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1376 (IFM_ACTIVE | IFM_AVALID)) { 1377 switch IFM_SUBTYPE(mii->mii_media_active) { 1378 case IFM_10_T: 1379 case IFM_100_TX: 1380 return; 1381 case IFM_1000_T: 1382 aneg++; 1383 break; 1384 default: 1385 break; 1386 } 1387 } 1388 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_100T2CR, 0); 1389 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1390 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1391 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1392 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1393 DELAY(1000); 1394 if (aneg != 0) { 1395 /* 1396 * Poll link state until ale(4) get a 10/100Mbps link. 1397 */ 1398 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1399 mii_pollstat(mii); 1400 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 1401 == (IFM_ACTIVE | IFM_AVALID)) { 1402 switch (IFM_SUBTYPE( 1403 mii->mii_media_active)) { 1404 case IFM_10_T: 1405 case IFM_100_TX: 1406 ale_mac_config(sc); 1407 return; 1408 default: 1409 break; 1410 } 1411 } 1412 ALE_UNLOCK(sc); 1413 pause("alelnk", hz); 1414 ALE_LOCK(sc); 1415 } 1416 if (i == MII_ANEGTICKS_GIGE) 1417 device_printf(sc->ale_dev, 1418 "establishing a link failed, WOL may not work!"); 1419 } 1420 /* 1421 * No link, force MAC to have 100Mbps, full-duplex link. 1422 * This is the last resort and may/may not work. 1423 */ 1424 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1425 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1426 ale_mac_config(sc); 1427 } 1428 1429 static void 1430 ale_setwol(struct ale_softc *sc) 1431 { 1432 struct ifnet *ifp; 1433 uint32_t reg, pmcs; 1434 uint16_t pmstat; 1435 int pmc; 1436 1437 ALE_LOCK_ASSERT(sc); 1438 1439 if (pci_find_extcap(sc->ale_dev, PCIY_PMG, &pmc) != 0) { 1440 /* Disable WOL. */ 1441 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 1442 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1443 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1444 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1445 /* Force PHY power down. */ 1446 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1447 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1448 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_PHY_PLL_ON | 1449 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_IDDQ | 1450 GPHY_CTRL_PCLK_SEL_DIS | GPHY_CTRL_PWDOWN_HW); 1451 return; 1452 } 1453 1454 ifp = sc->ale_ifp; 1455 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 1456 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 1457 ale_setlinkspeed(sc); 1458 } 1459 1460 pmcs = 0; 1461 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 1462 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1463 CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs); 1464 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1465 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 1466 MAC_CFG_BCAST); 1467 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 1468 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1469 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1470 reg |= MAC_CFG_RX_ENB; 1471 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1472 1473 if ((ifp->if_capenable & IFCAP_WOL) == 0) { 1474 /* WOL disabled, PHY power down. */ 1475 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1476 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1477 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1478 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1479 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1480 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 1481 GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PCLK_SEL_DIS | 1482 GPHY_CTRL_PWDOWN_HW); 1483 } 1484 /* Request PME. */ 1485 pmstat = pci_read_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, 2); 1486 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1487 if ((ifp->if_capenable & IFCAP_WOL) != 0) 1488 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1489 pci_write_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1490 } 1491 1492 static int 1493 ale_suspend(device_t dev) 1494 { 1495 struct ale_softc *sc; 1496 1497 sc = device_get_softc(dev); 1498 1499 ALE_LOCK(sc); 1500 ale_stop(sc); 1501 ale_setwol(sc); 1502 ALE_UNLOCK(sc); 1503 1504 return (0); 1505 } 1506 1507 static int 1508 ale_resume(device_t dev) 1509 { 1510 struct ale_softc *sc; 1511 struct ifnet *ifp; 1512 int pmc; 1513 uint16_t cmd, pmstat; 1514 1515 sc = device_get_softc(dev); 1516 1517 ALE_LOCK(sc); 1518 /* 1519 * Clear INTx emulation disable for hardwares that 1520 * is set in resume event. From Linux. 1521 */ 1522 cmd = pci_read_config(sc->ale_dev, PCIR_COMMAND, 2); 1523 if ((cmd & 0x0400) != 0) { 1524 cmd &= ~0x0400; 1525 pci_write_config(sc->ale_dev, PCIR_COMMAND, cmd, 2); 1526 } 1527 if (pci_find_extcap(sc->ale_dev, PCIY_PMG, &pmc) == 0) { 1528 /* Disable PME and clear PME status. */ 1529 pmstat = pci_read_config(sc->ale_dev, 1530 pmc + PCIR_POWER_STATUS, 2); 1531 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 1532 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1533 pci_write_config(sc->ale_dev, 1534 pmc + PCIR_POWER_STATUS, pmstat, 2); 1535 } 1536 } 1537 /* Reset PHY. */ 1538 ale_phy_reset(sc); 1539 ifp = sc->ale_ifp; 1540 if ((ifp->if_flags & IFF_UP) != 0) { 1541 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1542 ale_init_locked(sc); 1543 } 1544 ALE_UNLOCK(sc); 1545 1546 return (0); 1547 } 1548 1549 static int 1550 ale_encap(struct ale_softc *sc, struct mbuf **m_head) 1551 { 1552 struct ale_txdesc *txd, *txd_last; 1553 struct tx_desc *desc; 1554 struct mbuf *m; 1555 struct ip *ip; 1556 struct tcphdr *tcp; 1557 bus_dma_segment_t txsegs[ALE_MAXTXSEGS]; 1558 bus_dmamap_t map; 1559 uint32_t cflags, ip_off, poff, vtag; 1560 int error, i, nsegs, prod, si; 1561 1562 ALE_LOCK_ASSERT(sc); 1563 1564 M_ASSERTPKTHDR((*m_head)); 1565 1566 m = *m_head; 1567 ip = NULL; 1568 tcp = NULL; 1569 cflags = vtag = 0; 1570 ip_off = poff = 0; 1571 if ((m->m_pkthdr.csum_flags & (ALE_CSUM_FEATURES | CSUM_TSO)) != 0) { 1572 /* 1573 * AR81xx requires offset of TCP/UDP payload in its Tx 1574 * descriptor to perform hardware Tx checksum offload. 1575 * Additionally, TSO requires IP/TCP header size and 1576 * modification of IP/TCP header in order to make TSO 1577 * engine work. This kind of operation takes many CPU 1578 * cycles on FreeBSD so fast host CPU is required to 1579 * get smooth TSO performance. 1580 */ 1581 struct ether_header *eh; 1582 1583 if (M_WRITABLE(m) == 0) { 1584 /* Get a writable copy. */ 1585 m = m_dup(*m_head, M_DONTWAIT); 1586 /* Release original mbufs. */ 1587 m_freem(*m_head); 1588 if (m == NULL) { 1589 *m_head = NULL; 1590 return (ENOBUFS); 1591 } 1592 *m_head = m; 1593 } 1594 1595 /* 1596 * Buggy-controller requires 4 byte aligned Tx buffer 1597 * to make custom checksum offload work. 1598 */ 1599 if ((sc->ale_flags & ALE_FLAG_TXCSUM_BUG) != 0 && 1600 (m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0 && 1601 (mtod(m, intptr_t) & 3) != 0) { 1602 m = m_defrag(*m_head, M_DONTWAIT); 1603 if (m == NULL) { 1604 *m_head = NULL; 1605 return (ENOBUFS); 1606 } 1607 *m_head = m; 1608 } 1609 1610 ip_off = sizeof(struct ether_header); 1611 m = m_pullup(m, ip_off); 1612 if (m == NULL) { 1613 *m_head = NULL; 1614 return (ENOBUFS); 1615 } 1616 eh = mtod(m, struct ether_header *); 1617 /* 1618 * Check if hardware VLAN insertion is off. 1619 * Additional check for LLC/SNAP frame? 1620 */ 1621 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1622 ip_off = sizeof(struct ether_vlan_header); 1623 m = m_pullup(m, ip_off); 1624 if (m == NULL) { 1625 *m_head = NULL; 1626 return (ENOBUFS); 1627 } 1628 } 1629 m = m_pullup(m, ip_off + sizeof(struct ip)); 1630 if (m == NULL) { 1631 *m_head = NULL; 1632 return (ENOBUFS); 1633 } 1634 ip = (struct ip *)(mtod(m, char *) + ip_off); 1635 poff = ip_off + (ip->ip_hl << 2); 1636 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1637 /* 1638 * XXX 1639 * AR81xx requires the first descriptor should 1640 * not include any TCP playload for TSO case. 1641 * (i.e. ethernet header + IP + TCP header only) 1642 * m_pullup(9) above will ensure this too. 1643 * However it's not correct if the first mbuf 1644 * of the chain does not use cluster. 1645 */ 1646 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1647 if (m == NULL) { 1648 *m_head = NULL; 1649 return (ENOBUFS); 1650 } 1651 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1652 /* 1653 * AR81xx requires IP/TCP header size and offset as 1654 * well as TCP pseudo checksum which complicates 1655 * TSO configuration. I guess this comes from the 1656 * adherence to Microsoft NDIS Large Send 1657 * specification which requires insertion of 1658 * pseudo checksum by upper stack. The pseudo 1659 * checksum that NDIS refers to doesn't include 1660 * TCP payload length so ale(4) should recompute 1661 * the pseudo checksum here. Hopefully this wouldn't 1662 * be much burden on modern CPUs. 1663 * Reset IP checksum and recompute TCP pseudo 1664 * checksum as NDIS specification said. 1665 */ 1666 ip->ip_sum = 0; 1667 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1668 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1669 } 1670 *m_head = m; 1671 } 1672 1673 si = prod = sc->ale_cdata.ale_tx_prod; 1674 txd = &sc->ale_cdata.ale_txdesc[prod]; 1675 txd_last = txd; 1676 map = txd->tx_dmamap; 1677 1678 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1679 *m_head, txsegs, &nsegs, 0); 1680 if (error == EFBIG) { 1681 m = m_collapse(*m_head, M_DONTWAIT, ALE_MAXTXSEGS); 1682 if (m == NULL) { 1683 m_freem(*m_head); 1684 *m_head = NULL; 1685 return (ENOMEM); 1686 } 1687 *m_head = m; 1688 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1689 *m_head, txsegs, &nsegs, 0); 1690 if (error != 0) { 1691 m_freem(*m_head); 1692 *m_head = NULL; 1693 return (error); 1694 } 1695 } else if (error != 0) 1696 return (error); 1697 if (nsegs == 0) { 1698 m_freem(*m_head); 1699 *m_head = NULL; 1700 return (EIO); 1701 } 1702 1703 /* Check descriptor overrun. */ 1704 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 2) { 1705 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, map); 1706 return (ENOBUFS); 1707 } 1708 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, map, BUS_DMASYNC_PREWRITE); 1709 1710 m = *m_head; 1711 /* Configure Tx checksum offload. */ 1712 if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { 1713 /* 1714 * AR81xx supports Tx custom checksum offload feature 1715 * that offloads single 16bit checksum computation. 1716 * So you can choose one among IP, TCP and UDP. 1717 * Normally driver sets checksum start/insertion 1718 * position from the information of TCP/UDP frame as 1719 * TCP/UDP checksum takes more time than that of IP. 1720 * However it seems that custom checksum offload 1721 * requires 4 bytes aligned Tx buffers due to hardware 1722 * bug. 1723 * AR81xx also supports explicit Tx checksum computation 1724 * if it is told that the size of IP header and TCP 1725 * header(for UDP, the header size does not matter 1726 * because it's fixed length). However with this scheme 1727 * TSO does not work so you have to choose one either 1728 * TSO or explicit Tx checksum offload. I chosen TSO 1729 * plus custom checksum offload with work-around which 1730 * will cover most common usage for this consumer 1731 * ethernet controller. The work-around takes a lot of 1732 * CPU cycles if Tx buffer is not aligned on 4 bytes 1733 * boundary, though. 1734 */ 1735 cflags |= ALE_TD_CXSUM; 1736 /* Set checksum start offset. */ 1737 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); 1738 /* Set checksum insertion position of TCP/UDP. */ 1739 cflags |= ((poff + m->m_pkthdr.csum_data) << 1740 ALE_TD_CSUM_XSUMOFFSET_SHIFT); 1741 } 1742 1743 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1744 /* Request TSO and set MSS. */ 1745 cflags |= ALE_TD_TSO; 1746 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << ALE_TD_MSS_SHIFT); 1747 /* Set IP/TCP header size. */ 1748 cflags |= ip->ip_hl << ALE_TD_IPHDR_LEN_SHIFT; 1749 cflags |= tcp->th_off << ALE_TD_TCPHDR_LEN_SHIFT; 1750 } 1751 1752 /* Configure VLAN hardware tag insertion. */ 1753 if ((m->m_flags & M_VLANTAG) != 0) { 1754 vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1755 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); 1756 cflags |= ALE_TD_INSERT_VLAN_TAG; 1757 } 1758 1759 desc = NULL; 1760 for (i = 0; i < nsegs; i++) { 1761 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1762 desc->addr = htole64(txsegs[i].ds_addr); 1763 desc->len = htole32(ALE_TX_BYTES(txsegs[i].ds_len) | vtag); 1764 desc->flags = htole32(cflags); 1765 sc->ale_cdata.ale_tx_cnt++; 1766 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1767 } 1768 /* Update producer index. */ 1769 sc->ale_cdata.ale_tx_prod = prod; 1770 /* Set TSO header on the first descriptor. */ 1771 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1772 desc = &sc->ale_cdata.ale_tx_ring[si]; 1773 desc->flags |= htole32(ALE_TD_TSO_HDR); 1774 } 1775 1776 /* Finally set EOP on the last descriptor. */ 1777 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; 1778 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1779 desc->flags |= htole32(ALE_TD_EOP); 1780 1781 /* Swap dmamap of the first and the last. */ 1782 txd = &sc->ale_cdata.ale_txdesc[prod]; 1783 map = txd_last->tx_dmamap; 1784 txd_last->tx_dmamap = txd->tx_dmamap; 1785 txd->tx_dmamap = map; 1786 txd->tx_m = m; 1787 1788 /* Sync descriptors. */ 1789 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 1790 sc->ale_cdata.ale_tx_ring_map, 1791 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1792 1793 return (0); 1794 } 1795 1796 static void 1797 ale_tx_task(void *arg, int pending) 1798 { 1799 struct ifnet *ifp; 1800 1801 ifp = (struct ifnet *)arg; 1802 ale_start(ifp); 1803 } 1804 1805 static void 1806 ale_start(struct ifnet *ifp) 1807 { 1808 struct ale_softc *sc; 1809 struct mbuf *m_head; 1810 int enq; 1811 1812 sc = ifp->if_softc; 1813 1814 ALE_LOCK(sc); 1815 1816 /* Reclaim transmitted frames. */ 1817 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) 1818 ale_txeof(sc); 1819 1820 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1821 IFF_DRV_RUNNING || (sc->ale_flags & ALE_FLAG_LINK) == 0) { 1822 ALE_UNLOCK(sc); 1823 return; 1824 } 1825 1826 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd); ) { 1827 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1828 if (m_head == NULL) 1829 break; 1830 /* 1831 * Pack the data into the transmit ring. If we 1832 * don't have room, set the OACTIVE flag and wait 1833 * for the NIC to drain the ring. 1834 */ 1835 if (ale_encap(sc, &m_head)) { 1836 if (m_head == NULL) 1837 break; 1838 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1839 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1840 break; 1841 } 1842 1843 enq++; 1844 /* 1845 * If there's a BPF listener, bounce a copy of this frame 1846 * to him. 1847 */ 1848 ETHER_BPF_MTAP(ifp, m_head); 1849 } 1850 1851 if (enq > 0) { 1852 /* Kick. */ 1853 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, 1854 sc->ale_cdata.ale_tx_prod); 1855 /* Set a timeout in case the chip goes out to lunch. */ 1856 sc->ale_watchdog_timer = ALE_TX_TIMEOUT; 1857 } 1858 1859 ALE_UNLOCK(sc); 1860 } 1861 1862 static void 1863 ale_watchdog(struct ale_softc *sc) 1864 { 1865 struct ifnet *ifp; 1866 1867 ALE_LOCK_ASSERT(sc); 1868 1869 if (sc->ale_watchdog_timer == 0 || --sc->ale_watchdog_timer) 1870 return; 1871 1872 ifp = sc->ale_ifp; 1873 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1874 if_printf(sc->ale_ifp, "watchdog timeout (lost link)\n"); 1875 ifp->if_oerrors++; 1876 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1877 ale_init_locked(sc); 1878 return; 1879 } 1880 if_printf(sc->ale_ifp, "watchdog timeout -- resetting\n"); 1881 ifp->if_oerrors++; 1882 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1883 ale_init_locked(sc); 1884 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1885 taskqueue_enqueue(sc->ale_tq, &sc->ale_tx_task); 1886 } 1887 1888 static int 1889 ale_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) 1890 { 1891 struct ale_softc *sc; 1892 struct ifreq *ifr; 1893 struct mii_data *mii; 1894 int error, mask; 1895 1896 sc = ifp->if_softc; 1897 ifr = (struct ifreq *)data; 1898 error = 0; 1899 switch (cmd) { 1900 case SIOCSIFMTU: 1901 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALE_JUMBO_MTU || 1902 ((sc->ale_flags & ALE_FLAG_JUMBO) == 0 && 1903 ifr->ifr_mtu > ETHERMTU)) 1904 error = EINVAL; 1905 else if (ifp->if_mtu != ifr->ifr_mtu) { 1906 ALE_LOCK(sc); 1907 ifp->if_mtu = ifr->ifr_mtu; 1908 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1909 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1910 ale_init_locked(sc); 1911 } 1912 ALE_UNLOCK(sc); 1913 } 1914 break; 1915 case SIOCSIFFLAGS: 1916 ALE_LOCK(sc); 1917 if ((ifp->if_flags & IFF_UP) != 0) { 1918 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 1919 if (((ifp->if_flags ^ sc->ale_if_flags) 1920 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1921 ale_rxfilter(sc); 1922 } else { 1923 if ((sc->ale_flags & ALE_FLAG_DETACH) == 0) 1924 ale_init_locked(sc); 1925 } 1926 } else { 1927 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1928 ale_stop(sc); 1929 } 1930 sc->ale_if_flags = ifp->if_flags; 1931 ALE_UNLOCK(sc); 1932 break; 1933 case SIOCADDMULTI: 1934 case SIOCDELMULTI: 1935 ALE_LOCK(sc); 1936 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1937 ale_rxfilter(sc); 1938 ALE_UNLOCK(sc); 1939 break; 1940 case SIOCSIFMEDIA: 1941 case SIOCGIFMEDIA: 1942 mii = device_get_softc(sc->ale_miibus); 1943 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 1944 break; 1945 case SIOCSIFCAP: 1946 ALE_LOCK(sc); 1947 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 1948 if ((mask & IFCAP_TXCSUM) != 0 && 1949 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 1950 ifp->if_capenable ^= IFCAP_TXCSUM; 1951 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 1952 ifp->if_hwassist |= ALE_CSUM_FEATURES; 1953 else 1954 ifp->if_hwassist &= ~ALE_CSUM_FEATURES; 1955 } 1956 if ((mask & IFCAP_RXCSUM) != 0 && 1957 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 1958 ifp->if_capenable ^= IFCAP_RXCSUM; 1959 if ((mask & IFCAP_TSO4) != 0 && 1960 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 1961 ifp->if_capenable ^= IFCAP_TSO4; 1962 if ((ifp->if_capenable & IFCAP_TSO4) != 0) 1963 ifp->if_hwassist |= CSUM_TSO; 1964 else 1965 ifp->if_hwassist &= ~CSUM_TSO; 1966 } 1967 1968 if ((mask & IFCAP_WOL_MCAST) != 0 && 1969 (ifp->if_capabilities & IFCAP_WOL_MCAST) != 0) 1970 ifp->if_capenable ^= IFCAP_WOL_MCAST; 1971 if ((mask & IFCAP_WOL_MAGIC) != 0 && 1972 (ifp->if_capabilities & IFCAP_WOL_MAGIC) != 0) 1973 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 1974 1975 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 1976 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 1977 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 1978 ale_rxvlan(sc); 1979 } 1980 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 1981 (ifp->if_capabilities & IFCAP_VLAN_HWCSUM) != 0) 1982 ifp->if_capenable ^= IFCAP_VLAN_HWCSUM; 1983 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 1984 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 1985 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 1986 /* 1987 * VLAN hardware tagging is required to do checksum 1988 * offload or TSO on VLAN interface. Checksum offload 1989 * on VLAN interface also requires hardware checksum 1990 * offload of parent interface. 1991 */ 1992 if ((ifp->if_capenable & IFCAP_TXCSUM) == 0) 1993 ifp->if_capenable &= ~IFCAP_VLAN_HWCSUM; 1994 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 1995 ifp->if_capenable &= 1996 ~(IFCAP_VLAN_HWTSO | IFCAP_VLAN_HWCSUM); 1997 ALE_UNLOCK(sc); 1998 VLAN_CAPABILITIES(ifp); 1999 break; 2000 default: 2001 error = ether_ioctl(ifp, cmd, data); 2002 break; 2003 } 2004 2005 return (error); 2006 } 2007 2008 static void 2009 ale_mac_config(struct ale_softc *sc) 2010 { 2011 struct mii_data *mii; 2012 uint32_t reg; 2013 2014 ALE_LOCK_ASSERT(sc); 2015 2016 mii = device_get_softc(sc->ale_miibus); 2017 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2018 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2019 MAC_CFG_SPEED_MASK); 2020 /* Reprogram MAC with resolved speed/duplex. */ 2021 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2022 case IFM_10_T: 2023 case IFM_100_TX: 2024 reg |= MAC_CFG_SPEED_10_100; 2025 break; 2026 case IFM_1000_T: 2027 reg |= MAC_CFG_SPEED_1000; 2028 break; 2029 } 2030 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2031 reg |= MAC_CFG_FULL_DUPLEX; 2032 #ifdef notyet 2033 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2034 reg |= MAC_CFG_TX_FC; 2035 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2036 reg |= MAC_CFG_RX_FC; 2037 #endif 2038 } 2039 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2040 } 2041 2042 static void 2043 ale_link_task(void *arg, int pending) 2044 { 2045 struct ale_softc *sc; 2046 struct mii_data *mii; 2047 struct ifnet *ifp; 2048 uint32_t reg; 2049 2050 sc = (struct ale_softc *)arg; 2051 2052 ALE_LOCK(sc); 2053 mii = device_get_softc(sc->ale_miibus); 2054 ifp = sc->ale_ifp; 2055 if (mii == NULL || ifp == NULL || 2056 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2057 ALE_UNLOCK(sc); 2058 return; 2059 } 2060 2061 sc->ale_flags &= ~ALE_FLAG_LINK; 2062 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 2063 (IFM_ACTIVE | IFM_AVALID)) { 2064 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2065 case IFM_10_T: 2066 case IFM_100_TX: 2067 sc->ale_flags |= ALE_FLAG_LINK; 2068 break; 2069 case IFM_1000_T: 2070 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 2071 sc->ale_flags |= ALE_FLAG_LINK; 2072 break; 2073 default: 2074 break; 2075 } 2076 } 2077 2078 /* Stop Rx/Tx MACs. */ 2079 ale_stop_mac(sc); 2080 2081 /* Program MACs with resolved speed/duplex/flow-control. */ 2082 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { 2083 ale_mac_config(sc); 2084 /* Reenable Tx/Rx MACs. */ 2085 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2086 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 2087 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2088 } 2089 2090 ALE_UNLOCK(sc); 2091 } 2092 2093 static void 2094 ale_stats_clear(struct ale_softc *sc) 2095 { 2096 struct smb sb; 2097 uint32_t *reg; 2098 int i; 2099 2100 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2101 CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2102 i += sizeof(uint32_t); 2103 } 2104 /* Read Tx statistics. */ 2105 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2106 CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2107 i += sizeof(uint32_t); 2108 } 2109 } 2110 2111 static void 2112 ale_stats_update(struct ale_softc *sc) 2113 { 2114 struct ale_hw_stats *stat; 2115 struct smb sb, *smb; 2116 struct ifnet *ifp; 2117 uint32_t *reg; 2118 int i; 2119 2120 ALE_LOCK_ASSERT(sc); 2121 2122 ifp = sc->ale_ifp; 2123 stat = &sc->ale_stats; 2124 smb = &sb; 2125 2126 /* Read Rx statistics. */ 2127 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2128 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2129 i += sizeof(uint32_t); 2130 } 2131 /* Read Tx statistics. */ 2132 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2133 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2134 i += sizeof(uint32_t); 2135 } 2136 2137 /* Rx stats. */ 2138 stat->rx_frames += smb->rx_frames; 2139 stat->rx_bcast_frames += smb->rx_bcast_frames; 2140 stat->rx_mcast_frames += smb->rx_mcast_frames; 2141 stat->rx_pause_frames += smb->rx_pause_frames; 2142 stat->rx_control_frames += smb->rx_control_frames; 2143 stat->rx_crcerrs += smb->rx_crcerrs; 2144 stat->rx_lenerrs += smb->rx_lenerrs; 2145 stat->rx_bytes += smb->rx_bytes; 2146 stat->rx_runts += smb->rx_runts; 2147 stat->rx_fragments += smb->rx_fragments; 2148 stat->rx_pkts_64 += smb->rx_pkts_64; 2149 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2150 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2151 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2152 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2153 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2154 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2155 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2156 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2157 stat->rx_rrs_errs += smb->rx_rrs_errs; 2158 stat->rx_alignerrs += smb->rx_alignerrs; 2159 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2160 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2161 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2162 2163 /* Tx stats. */ 2164 stat->tx_frames += smb->tx_frames; 2165 stat->tx_bcast_frames += smb->tx_bcast_frames; 2166 stat->tx_mcast_frames += smb->tx_mcast_frames; 2167 stat->tx_pause_frames += smb->tx_pause_frames; 2168 stat->tx_excess_defer += smb->tx_excess_defer; 2169 stat->tx_control_frames += smb->tx_control_frames; 2170 stat->tx_deferred += smb->tx_deferred; 2171 stat->tx_bytes += smb->tx_bytes; 2172 stat->tx_pkts_64 += smb->tx_pkts_64; 2173 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2174 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2175 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2176 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2177 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2178 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2179 stat->tx_single_colls += smb->tx_single_colls; 2180 stat->tx_multi_colls += smb->tx_multi_colls; 2181 stat->tx_late_colls += smb->tx_late_colls; 2182 stat->tx_excess_colls += smb->tx_excess_colls; 2183 stat->tx_abort += smb->tx_abort; 2184 stat->tx_underrun += smb->tx_underrun; 2185 stat->tx_desc_underrun += smb->tx_desc_underrun; 2186 stat->tx_lenerrs += smb->tx_lenerrs; 2187 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2188 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2189 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2190 2191 /* Update counters in ifnet. */ 2192 ifp->if_opackets += smb->tx_frames; 2193 2194 ifp->if_collisions += smb->tx_single_colls + 2195 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2196 smb->tx_abort * HDPX_CFG_RETRY_DEFAULT; 2197 2198 /* 2199 * XXX 2200 * tx_pkts_truncated counter looks suspicious. It constantly 2201 * increments with no sign of Tx errors. This may indicate 2202 * the counter name is not correct one so I've removed the 2203 * counter in output errors. 2204 */ 2205 ifp->if_oerrors += smb->tx_abort + smb->tx_late_colls + 2206 smb->tx_underrun; 2207 2208 ifp->if_ipackets += smb->rx_frames; 2209 2210 ifp->if_ierrors += smb->rx_crcerrs + smb->rx_lenerrs + 2211 smb->rx_runts + smb->rx_pkts_truncated + 2212 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2213 smb->rx_alignerrs; 2214 } 2215 2216 static int 2217 ale_intr(void *arg) 2218 { 2219 struct ale_softc *sc; 2220 uint32_t status; 2221 2222 sc = (struct ale_softc *)arg; 2223 2224 status = CSR_READ_4(sc, ALE_INTR_STATUS); 2225 if ((status & ALE_INTRS) == 0) 2226 return (FILTER_STRAY); 2227 /* Disable interrupts. */ 2228 CSR_WRITE_4(sc, ALE_INTR_STATUS, INTR_DIS_INT); 2229 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2230 2231 return (FILTER_HANDLED); 2232 } 2233 2234 static void 2235 ale_int_task(void *arg, int pending) 2236 { 2237 struct ale_softc *sc; 2238 struct ifnet *ifp; 2239 uint32_t status; 2240 int more; 2241 2242 sc = (struct ale_softc *)arg; 2243 2244 status = CSR_READ_4(sc, ALE_INTR_STATUS); 2245 more = atomic_readandclear_int(&sc->ale_morework); 2246 if (more != 0) 2247 status |= INTR_RX_PKT; 2248 if ((status & ALE_INTRS) == 0) 2249 goto done; 2250 2251 /* Acknowledge interrupts but still disable interrupts. */ 2252 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); 2253 2254 ifp = sc->ale_ifp; 2255 more = 0; 2256 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2257 more = ale_rxeof(sc, sc->ale_process_limit); 2258 if (more == EAGAIN) 2259 atomic_set_int(&sc->ale_morework, 1); 2260 else if (more == EIO) { 2261 ALE_LOCK(sc); 2262 sc->ale_stats.reset_brk_seq++; 2263 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2264 ale_init_locked(sc); 2265 ALE_UNLOCK(sc); 2266 return; 2267 } 2268 2269 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 2270 if ((status & INTR_DMA_RD_TO_RST) != 0) 2271 device_printf(sc->ale_dev, 2272 "DMA read error! -- resetting\n"); 2273 if ((status & INTR_DMA_WR_TO_RST) != 0) 2274 device_printf(sc->ale_dev, 2275 "DMA write error! -- resetting\n"); 2276 ALE_LOCK(sc); 2277 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2278 ale_init_locked(sc); 2279 ALE_UNLOCK(sc); 2280 return; 2281 } 2282 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2283 taskqueue_enqueue(sc->ale_tq, &sc->ale_tx_task); 2284 } 2285 2286 if (more == EAGAIN || 2287 (CSR_READ_4(sc, ALE_INTR_STATUS) & ALE_INTRS) != 0) { 2288 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2289 return; 2290 } 2291 2292 done: 2293 /* Re-enable interrupts. */ 2294 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); 2295 } 2296 2297 static void 2298 ale_txeof(struct ale_softc *sc) 2299 { 2300 struct ifnet *ifp; 2301 struct ale_txdesc *txd; 2302 uint32_t cons, prod; 2303 int prog; 2304 2305 ALE_LOCK_ASSERT(sc); 2306 2307 ifp = sc->ale_ifp; 2308 2309 if (sc->ale_cdata.ale_tx_cnt == 0) 2310 return; 2311 2312 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2313 sc->ale_cdata.ale_tx_ring_map, 2314 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2315 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { 2316 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2317 sc->ale_cdata.ale_tx_cmb_map, 2318 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2319 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; 2320 } else 2321 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); 2322 cons = sc->ale_cdata.ale_tx_cons; 2323 /* 2324 * Go through our Tx list and free mbufs for those 2325 * frames which have been transmitted. 2326 */ 2327 for (prog = 0; cons != prod; prog++, 2328 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { 2329 if (sc->ale_cdata.ale_tx_cnt <= 0) 2330 break; 2331 prog++; 2332 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2333 sc->ale_cdata.ale_tx_cnt--; 2334 txd = &sc->ale_cdata.ale_txdesc[cons]; 2335 if (txd->tx_m != NULL) { 2336 /* Reclaim transmitted mbufs. */ 2337 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2338 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2339 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2340 txd->tx_dmamap); 2341 m_freem(txd->tx_m); 2342 txd->tx_m = NULL; 2343 } 2344 } 2345 2346 if (prog > 0) { 2347 sc->ale_cdata.ale_tx_cons = cons; 2348 /* 2349 * Unarm watchdog timer only when there is no pending 2350 * Tx descriptors in queue. 2351 */ 2352 if (sc->ale_cdata.ale_tx_cnt == 0) 2353 sc->ale_watchdog_timer = 0; 2354 } 2355 } 2356 2357 static void 2358 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, 2359 uint32_t length, uint32_t *prod) 2360 { 2361 struct ale_rx_page *rx_page; 2362 2363 rx_page = *page; 2364 /* Update consumer position. */ 2365 rx_page->cons += roundup(length + sizeof(struct rx_rs), 2366 ALE_RX_PAGE_ALIGN); 2367 if (rx_page->cons >= ALE_RX_PAGE_SZ) { 2368 /* 2369 * End of Rx page reached, let hardware reuse 2370 * this page. 2371 */ 2372 rx_page->cons = 0; 2373 *rx_page->cmb_addr = 0; 2374 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2375 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2376 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, 2377 RXF_VALID); 2378 /* Switch to alternate Rx page. */ 2379 sc->ale_cdata.ale_rx_curp ^= 1; 2380 rx_page = *page = 2381 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2382 /* Page flipped, sync CMB and Rx page. */ 2383 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2384 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2385 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2386 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2387 /* Sync completed, cache updated producer index. */ 2388 *prod = *rx_page->cmb_addr; 2389 } 2390 } 2391 2392 2393 /* 2394 * It seems that AR81xx controller can compute partial checksum. 2395 * The partial checksum value can be used to accelerate checksum 2396 * computation for fragmented TCP/UDP packets. Upper network stack 2397 * already takes advantage of the partial checksum value in IP 2398 * reassembly stage. But I'm not sure the correctness of the 2399 * partial hardware checksum assistance due to lack of data sheet. 2400 * In addition, the Rx feature of controller that requires copying 2401 * for every frames effectively nullifies one of most nice offload 2402 * capability of controller. 2403 */ 2404 static void 2405 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) 2406 { 2407 struct ifnet *ifp; 2408 struct ip *ip; 2409 char *p; 2410 2411 ifp = sc->ale_ifp; 2412 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2413 if ((status & ALE_RD_IPCSUM_NOK) == 0) 2414 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2415 2416 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { 2417 if (((status & ALE_RD_IPV4_FRAG) == 0) && 2418 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && 2419 ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) { 2420 m->m_pkthdr.csum_flags |= 2421 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2422 m->m_pkthdr.csum_data = 0xffff; 2423 } 2424 } else { 2425 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 && 2426 (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) { 2427 p = mtod(m, char *); 2428 p += ETHER_HDR_LEN; 2429 if ((status & ALE_RD_802_3) != 0) 2430 p += LLC_SNAPFRAMELEN; 2431 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0 && 2432 (status & ALE_RD_VLAN) != 0) 2433 p += ETHER_VLAN_ENCAP_LEN; 2434 ip = (struct ip *)p; 2435 if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0) 2436 return; 2437 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 2438 CSUM_PSEUDO_HDR; 2439 m->m_pkthdr.csum_data = 0xffff; 2440 } 2441 } 2442 /* 2443 * Don't mark bad checksum for TCP/UDP frames 2444 * as fragmented frames may always have set 2445 * bad checksummed bit of frame status. 2446 */ 2447 } 2448 2449 /* Process received frames. */ 2450 static int 2451 ale_rxeof(struct ale_softc *sc, int count) 2452 { 2453 struct ale_rx_page *rx_page; 2454 struct rx_rs *rs; 2455 struct ifnet *ifp; 2456 struct mbuf *m; 2457 uint32_t length, prod, seqno, status, vtags; 2458 int prog; 2459 2460 ifp = sc->ale_ifp; 2461 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2462 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2463 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2464 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2465 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2466 /* 2467 * Don't directly access producer index as hardware may 2468 * update it while Rx handler is in progress. It would 2469 * be even better if there is a way to let hardware 2470 * know how far driver processed its received frames. 2471 * Alternatively, hardware could provide a way to disable 2472 * CMB updates until driver acknowledges the end of CMB 2473 * access. 2474 */ 2475 prod = *rx_page->cmb_addr; 2476 for (prog = 0; prog < count; prog++) { 2477 if (rx_page->cons >= prod) 2478 break; 2479 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); 2480 seqno = ALE_RX_SEQNO(le32toh(rs->seqno)); 2481 if (sc->ale_cdata.ale_rx_seqno != seqno) { 2482 /* 2483 * Normally I believe this should not happen unless 2484 * severe driver bug or corrupted memory. However 2485 * it seems to happen under certain conditions which 2486 * is triggered by abrupt Rx events such as initiation 2487 * of bulk transfer of remote host. It's not easy to 2488 * reproduce this and I doubt it could be related 2489 * with FIFO overflow of hardware or activity of Tx 2490 * CMB updates. I also remember similar behaviour 2491 * seen on RealTek 8139 which uses resembling Rx 2492 * scheme. 2493 */ 2494 if (bootverbose) 2495 device_printf(sc->ale_dev, 2496 "garbled seq: %u, expected: %u -- " 2497 "resetting!\n", seqno, 2498 sc->ale_cdata.ale_rx_seqno); 2499 return (EIO); 2500 } 2501 /* Frame received. */ 2502 sc->ale_cdata.ale_rx_seqno++; 2503 length = ALE_RX_BYTES(le32toh(rs->length)); 2504 status = le32toh(rs->flags); 2505 if ((status & ALE_RD_ERROR) != 0) { 2506 /* 2507 * We want to pass the following frames to upper 2508 * layer regardless of error status of Rx return 2509 * status. 2510 * 2511 * o IP/TCP/UDP checksum is bad. 2512 * o frame length and protocol specific length 2513 * does not match. 2514 */ 2515 if ((status & (ALE_RD_CRC | ALE_RD_CODE | 2516 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | 2517 ALE_RD_TRUNC)) != 0) { 2518 ale_rx_update_page(sc, &rx_page, length, &prod); 2519 continue; 2520 } 2521 } 2522 /* 2523 * m_devget(9) is major bottle-neck of ale(4)(It comes 2524 * from hardware limitation). For jumbo frames we could 2525 * get a slightly better performance if driver use 2526 * m_getjcl(9) with proper buffer size argument. However 2527 * that would make code more complicated and I don't 2528 * think users would expect good Rx performance numbers 2529 * on these low-end consumer ethernet controller. 2530 */ 2531 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, 2532 ETHER_ALIGN, ifp, NULL); 2533 if (m == NULL) { 2534 ifp->if_iqdrops++; 2535 ale_rx_update_page(sc, &rx_page, length, &prod); 2536 continue; 2537 } 2538 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 2539 (status & ALE_RD_IPV4) != 0) 2540 ale_rxcsum(sc, m, status); 2541 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0 && 2542 (status & ALE_RD_VLAN) != 0) { 2543 vtags = ALE_RX_VLAN(le32toh(rs->vtags)); 2544 m->m_pkthdr.ether_vtag = ALE_RX_VLAN_TAG(vtags); 2545 m->m_flags |= M_VLANTAG; 2546 } 2547 2548 /* Pass it to upper layer. */ 2549 (*ifp->if_input)(ifp, m); 2550 2551 ale_rx_update_page(sc, &rx_page, length, &prod); 2552 } 2553 2554 return (count > 0 ? 0 : EAGAIN); 2555 } 2556 2557 static void 2558 ale_tick(void *arg) 2559 { 2560 struct ale_softc *sc; 2561 struct mii_data *mii; 2562 2563 sc = (struct ale_softc *)arg; 2564 2565 ALE_LOCK_ASSERT(sc); 2566 2567 mii = device_get_softc(sc->ale_miibus); 2568 mii_tick(mii); 2569 ale_stats_update(sc); 2570 /* 2571 * Reclaim Tx buffers that have been transferred. It's not 2572 * needed here but it would release allocated mbuf chains 2573 * faster and limit the maximum delay to a hz. 2574 */ 2575 ale_txeof(sc); 2576 ale_watchdog(sc); 2577 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2578 } 2579 2580 static void 2581 ale_reset(struct ale_softc *sc) 2582 { 2583 uint32_t reg; 2584 int i; 2585 2586 /* Initialize PCIe module. From Linux. */ 2587 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2588 2589 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); 2590 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2591 DELAY(10); 2592 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) 2593 break; 2594 } 2595 if (i == 0) 2596 device_printf(sc->ale_dev, "master reset timeout!\n"); 2597 2598 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2599 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) 2600 break; 2601 DELAY(10); 2602 } 2603 2604 if (i == 0) 2605 device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg); 2606 } 2607 2608 static void 2609 ale_init(void *xsc) 2610 { 2611 struct ale_softc *sc; 2612 2613 sc = (struct ale_softc *)xsc; 2614 ALE_LOCK(sc); 2615 ale_init_locked(sc); 2616 ALE_UNLOCK(sc); 2617 } 2618 2619 static void 2620 ale_init_locked(struct ale_softc *sc) 2621 { 2622 struct ifnet *ifp; 2623 struct mii_data *mii; 2624 uint8_t eaddr[ETHER_ADDR_LEN]; 2625 bus_addr_t paddr; 2626 uint32_t reg, rxf_hi, rxf_lo; 2627 2628 ALE_LOCK_ASSERT(sc); 2629 2630 ifp = sc->ale_ifp; 2631 mii = device_get_softc(sc->ale_miibus); 2632 2633 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 2634 return; 2635 /* 2636 * Cancel any pending I/O. 2637 */ 2638 ale_stop(sc); 2639 /* 2640 * Reset the chip to a known state. 2641 */ 2642 ale_reset(sc); 2643 /* Initialize Tx descriptors, DMA memory blocks. */ 2644 ale_init_rx_pages(sc); 2645 ale_init_tx_ring(sc); 2646 2647 /* Reprogram the station address. */ 2648 bcopy(IF_LLADDR(ifp), eaddr, ETHER_ADDR_LEN); 2649 CSR_WRITE_4(sc, ALE_PAR0, 2650 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2651 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); 2652 /* 2653 * Clear WOL status and disable all WOL feature as WOL 2654 * would interfere Rx operation under normal environments. 2655 */ 2656 CSR_READ_4(sc, ALE_WOL_CFG); 2657 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 2658 /* 2659 * Set Tx descriptor/RXF0/CMB base addresses. They share 2660 * the same high address part of DMAable region. 2661 */ 2662 paddr = sc->ale_cdata.ale_tx_ring_paddr; 2663 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); 2664 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); 2665 CSR_WRITE_4(sc, ALE_TPD_CNT, 2666 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); 2667 /* Set Rx page base address, note we use single queue. */ 2668 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; 2669 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); 2670 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; 2671 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); 2672 /* Set Tx/Rx CMB addresses. */ 2673 paddr = sc->ale_cdata.ale_tx_cmb_paddr; 2674 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); 2675 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; 2676 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); 2677 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; 2678 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); 2679 /* Mark RXF0 is valid. */ 2680 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); 2681 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); 2682 /* 2683 * No need to initialize RFX1/RXF2/RXF3. We don't use 2684 * multi-queue yet. 2685 */ 2686 2687 /* Set Rx page size, excluding guard frame size. */ 2688 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); 2689 /* Tell hardware that we're ready to load DMA blocks. */ 2690 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); 2691 2692 /* Set Rx/Tx interrupt trigger threshold. */ 2693 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | 2694 (4 << INT_TRIG_TX_THRESH_SHIFT)); 2695 /* 2696 * XXX 2697 * Set interrupt trigger timer, its purpose and relation 2698 * with interrupt moderation mechanism is not clear yet. 2699 */ 2700 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, 2701 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | 2702 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); 2703 2704 /* Configure interrupt moderation timer. */ 2705 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; 2706 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; 2707 CSR_WRITE_4(sc, ALE_IM_TIMER, reg); 2708 reg = CSR_READ_4(sc, ALE_MASTER_CFG); 2709 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 2710 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 2711 if (ALE_USECS(sc->ale_int_rx_mod) != 0) 2712 reg |= MASTER_IM_RX_TIMER_ENB; 2713 if (ALE_USECS(sc->ale_int_tx_mod) != 0) 2714 reg |= MASTER_IM_TX_TIMER_ENB; 2715 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); 2716 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); 2717 2718 /* Set Maximum frame size of controller. */ 2719 if (ifp->if_mtu < ETHERMTU) 2720 sc->ale_max_frame_size = ETHERMTU; 2721 else 2722 sc->ale_max_frame_size = ifp->if_mtu; 2723 sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 2724 ETHER_CRC_LEN; 2725 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); 2726 /* Configure IPG/IFG parameters. */ 2727 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, 2728 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 2729 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2730 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2731 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 2732 /* Set parameters for half-duplex media. */ 2733 CSR_WRITE_4(sc, ALE_HDPX_CFG, 2734 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2735 HDPX_CFG_LCOL_MASK) | 2736 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2737 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2738 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2739 HDPX_CFG_ABEBT_MASK) | 2740 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2741 HDPX_CFG_JAMIPG_MASK)); 2742 2743 /* Configure Tx jumbo frame parameters. */ 2744 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2745 if (ifp->if_mtu < ETHERMTU) 2746 reg = sc->ale_max_frame_size; 2747 else if (ifp->if_mtu < 6 * 1024) 2748 reg = (sc->ale_max_frame_size * 2) / 3; 2749 else 2750 reg = sc->ale_max_frame_size / 2; 2751 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, 2752 roundup(reg, TX_JUMBO_THRESH_UNIT) >> 2753 TX_JUMBO_THRESH_UNIT_SHIFT); 2754 } 2755 /* Configure TxQ. */ 2756 reg = 0; 2757 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 2758 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) 2759 << TXQ_CFG_TX_FIFO_BURST_SHIFT; 2760 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2761 TXQ_CFG_TPD_BURST_MASK; 2762 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); 2763 2764 /* Configure Rx jumbo frame & flow control parameters. */ 2765 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2766 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); 2767 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, 2768 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << 2769 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | 2770 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & 2771 RX_JUMBO_LKAH_MASK)); 2772 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 2773 rxf_hi = (reg * 7) / 10; 2774 rxf_lo = (reg * 3)/ 10; 2775 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, 2776 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2777 RX_FIFO_PAUSE_THRESH_LO_MASK) | 2778 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2779 RX_FIFO_PAUSE_THRESH_HI_MASK)); 2780 } 2781 2782 /* Disable RSS. */ 2783 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); 2784 CSR_WRITE_4(sc, ALE_RSS_CPU, 0); 2785 2786 /* Configure RxQ. */ 2787 CSR_WRITE_4(sc, ALE_RXQ_CFG, 2788 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2789 2790 /* Configure DMA parameters. */ 2791 reg = 0; 2792 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) 2793 reg |= DMA_CFG_TXCMB_ENB; 2794 CSR_WRITE_4(sc, ALE_DMA_CFG, 2795 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | 2796 sc->ale_dma_rd_burst | reg | 2797 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | 2798 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 2799 DMA_CFG_RD_DELAY_CNT_MASK) | 2800 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 2801 DMA_CFG_WR_DELAY_CNT_MASK)); 2802 2803 /* 2804 * Hardware can be configured to issue SMB interrupt based 2805 * on programmed interval. Since there is a callout that is 2806 * invoked for every hz in driver we use that instead of 2807 * relying on periodic SMB interrupt. 2808 */ 2809 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); 2810 /* Clear MAC statistics. */ 2811 ale_stats_clear(sc); 2812 2813 /* 2814 * Configure Tx/Rx MACs. 2815 * - Auto-padding for short frames. 2816 * - Enable CRC generation. 2817 * Actual reconfiguration of MAC for resolved speed/duplex 2818 * is followed after detection of link establishment. 2819 * AR81xx always does checksum computation regardless of 2820 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will 2821 * cause Rx handling issue for fragmented IP datagrams due 2822 * to silicon bug. 2823 */ 2824 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 2825 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2826 MAC_CFG_PREAMBLE_MASK); 2827 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) 2828 reg |= MAC_CFG_SPEED_10_100; 2829 else 2830 reg |= MAC_CFG_SPEED_1000; 2831 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2832 2833 /* Set up the receive filter. */ 2834 ale_rxfilter(sc); 2835 ale_rxvlan(sc); 2836 2837 /* Acknowledge all pending interrupts and clear it. */ 2838 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); 2839 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2840 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); 2841 2842 sc->ale_flags &= ~ALE_FLAG_LINK; 2843 /* Switch to the current media. */ 2844 mii_mediachg(mii); 2845 2846 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2847 2848 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2849 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2850 } 2851 2852 static void 2853 ale_stop(struct ale_softc *sc) 2854 { 2855 struct ifnet *ifp; 2856 struct ale_txdesc *txd; 2857 uint32_t reg; 2858 int i; 2859 2860 ALE_LOCK_ASSERT(sc); 2861 /* 2862 * Mark the interface down and cancel the watchdog timer. 2863 */ 2864 ifp = sc->ale_ifp; 2865 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2866 sc->ale_flags &= ~ALE_FLAG_LINK; 2867 callout_stop(&sc->ale_tick_ch); 2868 sc->ale_watchdog_timer = 0; 2869 ale_stats_update(sc); 2870 /* Disable interrupts. */ 2871 CSR_WRITE_4(sc, ALE_INTR_MASK, 0); 2872 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2873 /* Disable queue processing and DMA. */ 2874 reg = CSR_READ_4(sc, ALE_TXQ_CFG); 2875 reg &= ~TXQ_CFG_ENB; 2876 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); 2877 reg = CSR_READ_4(sc, ALE_RXQ_CFG); 2878 reg &= ~RXQ_CFG_ENB; 2879 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); 2880 reg = CSR_READ_4(sc, ALE_DMA_CFG); 2881 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); 2882 CSR_WRITE_4(sc, ALE_DMA_CFG, reg); 2883 DELAY(1000); 2884 /* Stop Rx/Tx MACs. */ 2885 ale_stop_mac(sc); 2886 /* Disable interrupts which might be touched in taskq handler. */ 2887 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2888 2889 /* 2890 * Free TX mbufs still in the queues. 2891 */ 2892 for (i = 0; i < ALE_TX_RING_CNT; i++) { 2893 txd = &sc->ale_cdata.ale_txdesc[i]; 2894 if (txd->tx_m != NULL) { 2895 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2896 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2897 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2898 txd->tx_dmamap); 2899 m_freem(txd->tx_m); 2900 txd->tx_m = NULL; 2901 } 2902 } 2903 } 2904 2905 static void 2906 ale_stop_mac(struct ale_softc *sc) 2907 { 2908 uint32_t reg; 2909 int i; 2910 2911 ALE_LOCK_ASSERT(sc); 2912 2913 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2914 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 2915 reg &= ~MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 2916 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2917 } 2918 2919 for (i = ALE_TIMEOUT; i > 0; i--) { 2920 reg = CSR_READ_4(sc, ALE_IDLE_STATUS); 2921 if (reg == 0) 2922 break; 2923 DELAY(10); 2924 } 2925 if (i == 0) 2926 device_printf(sc->ale_dev, 2927 "could not disable Tx/Rx MAC(0x%08x)!\n", reg); 2928 } 2929 2930 static void 2931 ale_init_tx_ring(struct ale_softc *sc) 2932 { 2933 struct ale_txdesc *txd; 2934 int i; 2935 2936 ALE_LOCK_ASSERT(sc); 2937 2938 sc->ale_cdata.ale_tx_prod = 0; 2939 sc->ale_cdata.ale_tx_cons = 0; 2940 sc->ale_cdata.ale_tx_cnt = 0; 2941 2942 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ); 2943 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ); 2944 for (i = 0; i < ALE_TX_RING_CNT; i++) { 2945 txd = &sc->ale_cdata.ale_txdesc[i]; 2946 txd->tx_m = NULL; 2947 } 2948 *sc->ale_cdata.ale_tx_cmb = 0; 2949 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2950 sc->ale_cdata.ale_tx_cmb_map, 2951 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2952 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2953 sc->ale_cdata.ale_tx_ring_map, 2954 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2955 } 2956 2957 static void 2958 ale_init_rx_pages(struct ale_softc *sc) 2959 { 2960 struct ale_rx_page *rx_page; 2961 int i; 2962 2963 ALE_LOCK_ASSERT(sc); 2964 2965 atomic_set_int(&sc->ale_morework, 0); 2966 sc->ale_cdata.ale_rx_seqno = 0; 2967 sc->ale_cdata.ale_rx_curp = 0; 2968 2969 for (i = 0; i < ALE_RX_PAGES; i++) { 2970 rx_page = &sc->ale_cdata.ale_rx_page[i]; 2971 bzero(rx_page->page_addr, sc->ale_pagesize); 2972 bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ); 2973 rx_page->cons = 0; 2974 *rx_page->cmb_addr = 0; 2975 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2976 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2977 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2978 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2979 } 2980 } 2981 2982 static void 2983 ale_rxvlan(struct ale_softc *sc) 2984 { 2985 struct ifnet *ifp; 2986 uint32_t reg; 2987 2988 ALE_LOCK_ASSERT(sc); 2989 2990 ifp = sc->ale_ifp; 2991 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2992 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2993 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 2994 reg |= MAC_CFG_VLAN_TAG_STRIP; 2995 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2996 } 2997 2998 static void 2999 ale_rxfilter(struct ale_softc *sc) 3000 { 3001 struct ifnet *ifp; 3002 struct ifmultiaddr *ifma; 3003 uint32_t crc; 3004 uint32_t mchash[2]; 3005 uint32_t rxcfg; 3006 3007 ALE_LOCK_ASSERT(sc); 3008 3009 ifp = sc->ale_ifp; 3010 3011 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); 3012 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3013 if ((ifp->if_flags & IFF_BROADCAST) != 0) 3014 rxcfg |= MAC_CFG_BCAST; 3015 if ((ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3016 if ((ifp->if_flags & IFF_PROMISC) != 0) 3017 rxcfg |= MAC_CFG_PROMISC; 3018 if ((ifp->if_flags & IFF_ALLMULTI) != 0) 3019 rxcfg |= MAC_CFG_ALLMULTI; 3020 CSR_WRITE_4(sc, ALE_MAR0, 0xFFFFFFFF); 3021 CSR_WRITE_4(sc, ALE_MAR1, 0xFFFFFFFF); 3022 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3023 return; 3024 } 3025 3026 /* Program new filter. */ 3027 bzero(mchash, sizeof(mchash)); 3028 3029 IF_ADDR_LOCK(ifp); 3030 TAILQ_FOREACH(ifma, &sc->ale_ifp->if_multiaddrs, ifma_link) { 3031 if (ifma->ifma_addr->sa_family != AF_LINK) 3032 continue; 3033 crc = ether_crc32_le(LLADDR((struct sockaddr_dl *) 3034 ifma->ifma_addr), ETHER_ADDR_LEN); 3035 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 3036 } 3037 IF_ADDR_UNLOCK(ifp); 3038 3039 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); 3040 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); 3041 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3042 } 3043 3044 static int 3045 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3046 { 3047 int error, value; 3048 3049 if (arg1 == NULL) 3050 return (EINVAL); 3051 value = *(int *)arg1; 3052 error = sysctl_handle_int(oidp, &value, 0, req); 3053 if (error || req->newptr == NULL) 3054 return (error); 3055 if (value < low || value > high) 3056 return (EINVAL); 3057 *(int *)arg1 = value; 3058 3059 return (0); 3060 } 3061 3062 static int 3063 sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS) 3064 { 3065 return (sysctl_int_range(oidp, arg1, arg2, req, 3066 ALE_PROC_MIN, ALE_PROC_MAX)); 3067 } 3068 3069 static int 3070 sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS) 3071 { 3072 3073 return (sysctl_int_range(oidp, arg1, arg2, req, 3074 ALE_IM_TIMER_MIN, ALE_IM_TIMER_MAX)); 3075 } 3076