1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice unmodified, this list of conditions, and the following 12 * disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30 /* Driver for Atheros AR8121/AR8113/AR8114 PCIe Ethernet. */ 31 32 #include <sys/param.h> 33 #include <sys/systm.h> 34 #include <sys/bus.h> 35 #include <sys/endian.h> 36 #include <sys/kernel.h> 37 #include <sys/malloc.h> 38 #include <sys/mbuf.h> 39 #include <sys/module.h> 40 #include <sys/rman.h> 41 #include <sys/queue.h> 42 #include <sys/socket.h> 43 #include <sys/sockio.h> 44 #include <sys/sysctl.h> 45 #include <sys/taskqueue.h> 46 47 #include <net/bpf.h> 48 #include <net/if.h> 49 #include <net/if_var.h> 50 #include <net/if_arp.h> 51 #include <net/ethernet.h> 52 #include <net/if_dl.h> 53 #include <net/if_llc.h> 54 #include <net/if_media.h> 55 #include <net/if_types.h> 56 #include <net/if_vlan_var.h> 57 58 #include <netinet/in.h> 59 #include <netinet/in_systm.h> 60 #include <netinet/ip.h> 61 #include <netinet/tcp.h> 62 63 #include <dev/mii/mii.h> 64 #include <dev/mii/miivar.h> 65 66 #include <dev/pci/pcireg.h> 67 #include <dev/pci/pcivar.h> 68 69 #include <machine/bus.h> 70 #include <machine/in_cksum.h> 71 72 #include <dev/ale/if_alereg.h> 73 #include <dev/ale/if_alevar.h> 74 75 /* "device miibus" required. See GENERIC if you get errors here. */ 76 #include "miibus_if.h" 77 78 /* For more information about Tx checksum offload issues see ale_encap(). */ 79 #define ALE_CSUM_FEATURES (CSUM_TCP | CSUM_UDP) 80 81 MODULE_DEPEND(ale, pci, 1, 1, 1); 82 MODULE_DEPEND(ale, ether, 1, 1, 1); 83 MODULE_DEPEND(ale, miibus, 1, 1, 1); 84 85 /* Tunables. */ 86 static int msi_disable = 0; 87 static int msix_disable = 0; 88 TUNABLE_INT("hw.ale.msi_disable", &msi_disable); 89 TUNABLE_INT("hw.ale.msix_disable", &msix_disable); 90 91 /* 92 * Devices supported by this driver. 93 */ 94 static const struct ale_dev { 95 uint16_t ale_vendorid; 96 uint16_t ale_deviceid; 97 const char *ale_name; 98 } ale_devs[] = { 99 { VENDORID_ATHEROS, DEVICEID_ATHEROS_AR81XX, 100 "Atheros AR8121/AR8113/AR8114 PCIe Ethernet" }, 101 }; 102 103 static int ale_attach(device_t); 104 static int ale_check_boundary(struct ale_softc *); 105 static int ale_detach(device_t); 106 static int ale_dma_alloc(struct ale_softc *); 107 static void ale_dma_free(struct ale_softc *); 108 static void ale_dmamap_cb(void *, bus_dma_segment_t *, int, int); 109 static int ale_encap(struct ale_softc *, struct mbuf **); 110 static void ale_get_macaddr(struct ale_softc *); 111 static void ale_init(void *); 112 static void ale_init_locked(struct ale_softc *); 113 static void ale_init_rx_pages(struct ale_softc *); 114 static void ale_init_tx_ring(struct ale_softc *); 115 static void ale_int_task(void *, int); 116 static int ale_intr(void *); 117 static int ale_ioctl(if_t, u_long, caddr_t); 118 static void ale_mac_config(struct ale_softc *); 119 static int ale_miibus_readreg(device_t, int, int); 120 static void ale_miibus_statchg(device_t); 121 static int ale_miibus_writereg(device_t, int, int, int); 122 static int ale_mediachange(if_t); 123 static void ale_mediastatus(if_t, struct ifmediareq *); 124 static void ale_phy_reset(struct ale_softc *); 125 static int ale_probe(device_t); 126 static void ale_reset(struct ale_softc *); 127 static int ale_resume(device_t); 128 static void ale_rx_update_page(struct ale_softc *, struct ale_rx_page **, 129 uint32_t, uint32_t *); 130 static void ale_rxcsum(struct ale_softc *, struct mbuf *, uint32_t); 131 static int ale_rxeof(struct ale_softc *sc, int); 132 static void ale_rxfilter(struct ale_softc *); 133 static void ale_rxvlan(struct ale_softc *); 134 static void ale_setlinkspeed(struct ale_softc *); 135 static void ale_setwol(struct ale_softc *); 136 static int ale_shutdown(device_t); 137 static void ale_start(if_t); 138 static void ale_start_locked(if_t); 139 static void ale_stats_clear(struct ale_softc *); 140 static void ale_stats_update(struct ale_softc *); 141 static void ale_stop(struct ale_softc *); 142 static void ale_stop_mac(struct ale_softc *); 143 static int ale_suspend(device_t); 144 static void ale_sysctl_node(struct ale_softc *); 145 static void ale_tick(void *); 146 static void ale_txeof(struct ale_softc *); 147 static void ale_watchdog(struct ale_softc *); 148 static int sysctl_int_range(SYSCTL_HANDLER_ARGS, int, int); 149 static int sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS); 150 static int sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS); 151 152 static device_method_t ale_methods[] = { 153 /* Device interface. */ 154 DEVMETHOD(device_probe, ale_probe), 155 DEVMETHOD(device_attach, ale_attach), 156 DEVMETHOD(device_detach, ale_detach), 157 DEVMETHOD(device_shutdown, ale_shutdown), 158 DEVMETHOD(device_suspend, ale_suspend), 159 DEVMETHOD(device_resume, ale_resume), 160 161 /* MII interface. */ 162 DEVMETHOD(miibus_readreg, ale_miibus_readreg), 163 DEVMETHOD(miibus_writereg, ale_miibus_writereg), 164 DEVMETHOD(miibus_statchg, ale_miibus_statchg), 165 166 DEVMETHOD_END 167 }; 168 169 static driver_t ale_driver = { 170 "ale", 171 ale_methods, 172 sizeof(struct ale_softc) 173 }; 174 175 DRIVER_MODULE(ale, pci, ale_driver, NULL, NULL); 176 MODULE_PNP_INFO("U16:vendor;U16:device;D:#", pci, ale, ale_devs, 177 nitems(ale_devs)); 178 DRIVER_MODULE(miibus, ale, miibus_driver, NULL, NULL); 179 180 static struct resource_spec ale_res_spec_mem[] = { 181 { SYS_RES_MEMORY, PCIR_BAR(0), RF_ACTIVE }, 182 { -1, 0, 0 } 183 }; 184 185 static struct resource_spec ale_irq_spec_legacy[] = { 186 { SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE }, 187 { -1, 0, 0 } 188 }; 189 190 static struct resource_spec ale_irq_spec_msi[] = { 191 { SYS_RES_IRQ, 1, RF_ACTIVE }, 192 { -1, 0, 0 } 193 }; 194 195 static struct resource_spec ale_irq_spec_msix[] = { 196 { SYS_RES_IRQ, 1, RF_ACTIVE }, 197 { -1, 0, 0 } 198 }; 199 200 static int 201 ale_miibus_readreg(device_t dev, int phy, int reg) 202 { 203 struct ale_softc *sc; 204 uint32_t v; 205 int i; 206 207 sc = device_get_softc(dev); 208 209 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_READ | 210 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 211 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 212 DELAY(5); 213 v = CSR_READ_4(sc, ALE_MDIO); 214 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 215 break; 216 } 217 218 if (i == 0) { 219 device_printf(sc->ale_dev, "phy read timeout : %d\n", reg); 220 return (0); 221 } 222 223 return ((v & MDIO_DATA_MASK) >> MDIO_DATA_SHIFT); 224 } 225 226 static int 227 ale_miibus_writereg(device_t dev, int phy, int reg, int val) 228 { 229 struct ale_softc *sc; 230 uint32_t v; 231 int i; 232 233 sc = device_get_softc(dev); 234 235 CSR_WRITE_4(sc, ALE_MDIO, MDIO_OP_EXECUTE | MDIO_OP_WRITE | 236 (val & MDIO_DATA_MASK) << MDIO_DATA_SHIFT | 237 MDIO_SUP_PREAMBLE | MDIO_CLK_25_4 | MDIO_REG_ADDR(reg)); 238 for (i = ALE_PHY_TIMEOUT; i > 0; i--) { 239 DELAY(5); 240 v = CSR_READ_4(sc, ALE_MDIO); 241 if ((v & (MDIO_OP_EXECUTE | MDIO_OP_BUSY)) == 0) 242 break; 243 } 244 245 if (i == 0) 246 device_printf(sc->ale_dev, "phy write timeout : %d\n", reg); 247 248 return (0); 249 } 250 251 static void 252 ale_miibus_statchg(device_t dev) 253 { 254 struct ale_softc *sc; 255 struct mii_data *mii; 256 if_t ifp; 257 uint32_t reg; 258 259 sc = device_get_softc(dev); 260 mii = device_get_softc(sc->ale_miibus); 261 ifp = sc->ale_ifp; 262 if (mii == NULL || ifp == NULL || 263 (if_getdrvflags(ifp) & IFF_DRV_RUNNING) == 0) 264 return; 265 266 sc->ale_flags &= ~ALE_FLAG_LINK; 267 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 268 (IFM_ACTIVE | IFM_AVALID)) { 269 switch (IFM_SUBTYPE(mii->mii_media_active)) { 270 case IFM_10_T: 271 case IFM_100_TX: 272 sc->ale_flags |= ALE_FLAG_LINK; 273 break; 274 case IFM_1000_T: 275 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 276 sc->ale_flags |= ALE_FLAG_LINK; 277 break; 278 default: 279 break; 280 } 281 } 282 283 /* Stop Rx/Tx MACs. */ 284 ale_stop_mac(sc); 285 286 /* Program MACs with resolved speed/duplex/flow-control. */ 287 if ((sc->ale_flags & ALE_FLAG_LINK) != 0) { 288 ale_mac_config(sc); 289 /* Reenable Tx/Rx MACs. */ 290 reg = CSR_READ_4(sc, ALE_MAC_CFG); 291 reg |= MAC_CFG_TX_ENB | MAC_CFG_RX_ENB; 292 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 293 } 294 } 295 296 static void 297 ale_mediastatus(if_t ifp, struct ifmediareq *ifmr) 298 { 299 struct ale_softc *sc; 300 struct mii_data *mii; 301 302 sc = if_getsoftc(ifp); 303 ALE_LOCK(sc); 304 if ((if_getflags(ifp) & IFF_UP) == 0) { 305 ALE_UNLOCK(sc); 306 return; 307 } 308 mii = device_get_softc(sc->ale_miibus); 309 310 mii_pollstat(mii); 311 ifmr->ifm_status = mii->mii_media_status; 312 ifmr->ifm_active = mii->mii_media_active; 313 ALE_UNLOCK(sc); 314 } 315 316 static int 317 ale_mediachange(if_t ifp) 318 { 319 struct ale_softc *sc; 320 struct mii_data *mii; 321 struct mii_softc *miisc; 322 int error; 323 324 sc = if_getsoftc(ifp); 325 ALE_LOCK(sc); 326 mii = device_get_softc(sc->ale_miibus); 327 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 328 PHY_RESET(miisc); 329 error = mii_mediachg(mii); 330 ALE_UNLOCK(sc); 331 332 return (error); 333 } 334 335 static int 336 ale_probe(device_t dev) 337 { 338 const struct ale_dev *sp; 339 int i; 340 uint16_t vendor, devid; 341 342 vendor = pci_get_vendor(dev); 343 devid = pci_get_device(dev); 344 sp = ale_devs; 345 for (i = 0; i < nitems(ale_devs); i++) { 346 if (vendor == sp->ale_vendorid && 347 devid == sp->ale_deviceid) { 348 device_set_desc(dev, sp->ale_name); 349 return (BUS_PROBE_DEFAULT); 350 } 351 sp++; 352 } 353 354 return (ENXIO); 355 } 356 357 static void 358 ale_get_macaddr(struct ale_softc *sc) 359 { 360 uint32_t ea[2], reg; 361 int i, vpdc; 362 363 reg = CSR_READ_4(sc, ALE_SPI_CTRL); 364 if ((reg & SPI_VPD_ENB) != 0) { 365 reg &= ~SPI_VPD_ENB; 366 CSR_WRITE_4(sc, ALE_SPI_CTRL, reg); 367 } 368 369 if (pci_find_cap(sc->ale_dev, PCIY_VPD, &vpdc) == 0) { 370 /* 371 * PCI VPD capability found, let TWSI reload EEPROM. 372 * This will set ethernet address of controller. 373 */ 374 CSR_WRITE_4(sc, ALE_TWSI_CTRL, CSR_READ_4(sc, ALE_TWSI_CTRL) | 375 TWSI_CTRL_SW_LD_START); 376 for (i = 100; i > 0; i--) { 377 DELAY(1000); 378 reg = CSR_READ_4(sc, ALE_TWSI_CTRL); 379 if ((reg & TWSI_CTRL_SW_LD_START) == 0) 380 break; 381 } 382 if (i == 0) 383 device_printf(sc->ale_dev, 384 "reloading EEPROM timeout!\n"); 385 } else { 386 if (bootverbose) 387 device_printf(sc->ale_dev, 388 "PCI VPD capability not found!\n"); 389 } 390 391 ea[0] = CSR_READ_4(sc, ALE_PAR0); 392 ea[1] = CSR_READ_4(sc, ALE_PAR1); 393 sc->ale_eaddr[0] = (ea[1] >> 8) & 0xFF; 394 sc->ale_eaddr[1] = (ea[1] >> 0) & 0xFF; 395 sc->ale_eaddr[2] = (ea[0] >> 24) & 0xFF; 396 sc->ale_eaddr[3] = (ea[0] >> 16) & 0xFF; 397 sc->ale_eaddr[4] = (ea[0] >> 8) & 0xFF; 398 sc->ale_eaddr[5] = (ea[0] >> 0) & 0xFF; 399 } 400 401 static void 402 ale_phy_reset(struct ale_softc *sc) 403 { 404 405 /* Reset magic from Linux. */ 406 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 407 GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 408 GPHY_CTRL_PHY_PLL_ON); 409 DELAY(1000); 410 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 411 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | GPHY_CTRL_HIB_PULSE | 412 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_PLL_ON); 413 DELAY(1000); 414 415 #define ATPHY_DBG_ADDR 0x1D 416 #define ATPHY_DBG_DATA 0x1E 417 418 /* Enable hibernation mode. */ 419 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 420 ATPHY_DBG_ADDR, 0x0B); 421 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 422 ATPHY_DBG_DATA, 0xBC00); 423 /* Set Class A/B for all modes. */ 424 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 425 ATPHY_DBG_ADDR, 0x00); 426 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 427 ATPHY_DBG_DATA, 0x02EF); 428 /* Enable 10BT power saving. */ 429 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 430 ATPHY_DBG_ADDR, 0x12); 431 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 432 ATPHY_DBG_DATA, 0x4C04); 433 /* Adjust 1000T power. */ 434 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 435 ATPHY_DBG_ADDR, 0x04); 436 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 437 ATPHY_DBG_ADDR, 0x8BBB); 438 /* 10BT center tap voltage. */ 439 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 440 ATPHY_DBG_ADDR, 0x05); 441 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 442 ATPHY_DBG_ADDR, 0x2C46); 443 444 #undef ATPHY_DBG_ADDR 445 #undef ATPHY_DBG_DATA 446 DELAY(1000); 447 } 448 449 static int 450 ale_attach(device_t dev) 451 { 452 struct ale_softc *sc; 453 if_t ifp; 454 uint16_t burst; 455 int error, i, msic, msixc, pmc; 456 uint32_t rxf_len, txf_len; 457 458 error = 0; 459 sc = device_get_softc(dev); 460 sc->ale_dev = dev; 461 462 mtx_init(&sc->ale_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 463 MTX_DEF); 464 callout_init_mtx(&sc->ale_tick_ch, &sc->ale_mtx, 0); 465 NET_TASK_INIT(&sc->ale_int_task, 0, ale_int_task, sc); 466 467 /* Map the device. */ 468 pci_enable_busmaster(dev); 469 sc->ale_res_spec = ale_res_spec_mem; 470 sc->ale_irq_spec = ale_irq_spec_legacy; 471 error = bus_alloc_resources(dev, sc->ale_res_spec, sc->ale_res); 472 if (error != 0) { 473 device_printf(dev, "cannot allocate memory resources.\n"); 474 goto fail; 475 } 476 477 /* Set PHY address. */ 478 sc->ale_phyaddr = ALE_PHY_ADDR; 479 480 /* Reset PHY. */ 481 ale_phy_reset(sc); 482 483 /* Reset the ethernet controller. */ 484 ale_reset(sc); 485 486 /* Get PCI and chip id/revision. */ 487 sc->ale_rev = pci_get_revid(dev); 488 if (sc->ale_rev >= 0xF0) { 489 /* L2E Rev. B. AR8114 */ 490 sc->ale_flags |= ALE_FLAG_FASTETHER; 491 } else { 492 if ((CSR_READ_4(sc, ALE_PHY_STATUS) & PHY_STATUS_100M) != 0) { 493 /* L1E AR8121 */ 494 sc->ale_flags |= ALE_FLAG_JUMBO; 495 } else { 496 /* L2E Rev. A. AR8113 */ 497 sc->ale_flags |= ALE_FLAG_FASTETHER; 498 } 499 } 500 /* 501 * All known controllers seems to require 4 bytes alignment 502 * of Tx buffers to make Tx checksum offload with custom 503 * checksum generation method work. 504 */ 505 sc->ale_flags |= ALE_FLAG_TXCSUM_BUG; 506 /* 507 * All known controllers seems to have issues on Rx checksum 508 * offload for fragmented IP datagrams. 509 */ 510 sc->ale_flags |= ALE_FLAG_RXCSUM_BUG; 511 /* 512 * Don't use Tx CMB. It is known to cause RRS update failure 513 * under certain circumstances. Typical phenomenon of the 514 * issue would be unexpected sequence number encountered in 515 * Rx handler. 516 */ 517 sc->ale_flags |= ALE_FLAG_TXCMB_BUG; 518 sc->ale_chip_rev = CSR_READ_4(sc, ALE_MASTER_CFG) >> 519 MASTER_CHIP_REV_SHIFT; 520 if (bootverbose) { 521 device_printf(dev, "PCI device revision : 0x%04x\n", 522 sc->ale_rev); 523 device_printf(dev, "Chip id/revision : 0x%04x\n", 524 sc->ale_chip_rev); 525 } 526 txf_len = CSR_READ_4(sc, ALE_SRAM_TX_FIFO_LEN); 527 rxf_len = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 528 /* 529 * Uninitialized hardware returns an invalid chip id/revision 530 * as well as 0xFFFFFFFF for Tx/Rx fifo length. 531 */ 532 if (sc->ale_chip_rev == 0xFFFF || txf_len == 0xFFFFFFFF || 533 rxf_len == 0xFFFFFFF) { 534 device_printf(dev,"chip revision : 0x%04x, %u Tx FIFO " 535 "%u Rx FIFO -- not initialized?\n", sc->ale_chip_rev, 536 txf_len, rxf_len); 537 error = ENXIO; 538 goto fail; 539 } 540 device_printf(dev, "%u Tx FIFO, %u Rx FIFO\n", txf_len, rxf_len); 541 542 /* Allocate IRQ resources. */ 543 msixc = pci_msix_count(dev); 544 msic = pci_msi_count(dev); 545 if (bootverbose) { 546 device_printf(dev, "MSIX count : %d\n", msixc); 547 device_printf(dev, "MSI count : %d\n", msic); 548 } 549 550 /* Prefer MSIX over MSI. */ 551 if (msix_disable == 0 || msi_disable == 0) { 552 if (msix_disable == 0 && msixc == ALE_MSIX_MESSAGES && 553 pci_alloc_msix(dev, &msixc) == 0) { 554 if (msixc == ALE_MSIX_MESSAGES) { 555 device_printf(dev, "Using %d MSIX messages.\n", 556 msixc); 557 sc->ale_flags |= ALE_FLAG_MSIX; 558 sc->ale_irq_spec = ale_irq_spec_msix; 559 } else 560 pci_release_msi(dev); 561 } 562 if (msi_disable == 0 && (sc->ale_flags & ALE_FLAG_MSIX) == 0 && 563 msic == ALE_MSI_MESSAGES && 564 pci_alloc_msi(dev, &msic) == 0) { 565 if (msic == ALE_MSI_MESSAGES) { 566 device_printf(dev, "Using %d MSI messages.\n", 567 msic); 568 sc->ale_flags |= ALE_FLAG_MSI; 569 sc->ale_irq_spec = ale_irq_spec_msi; 570 } else 571 pci_release_msi(dev); 572 } 573 } 574 575 error = bus_alloc_resources(dev, sc->ale_irq_spec, sc->ale_irq); 576 if (error != 0) { 577 device_printf(dev, "cannot allocate IRQ resources.\n"); 578 goto fail; 579 } 580 581 /* Get DMA parameters from PCIe device control register. */ 582 if (pci_find_cap(dev, PCIY_EXPRESS, &i) == 0) { 583 sc->ale_flags |= ALE_FLAG_PCIE; 584 burst = pci_read_config(dev, i + 0x08, 2); 585 /* Max read request size. */ 586 sc->ale_dma_rd_burst = ((burst >> 12) & 0x07) << 587 DMA_CFG_RD_BURST_SHIFT; 588 /* Max payload size. */ 589 sc->ale_dma_wr_burst = ((burst >> 5) & 0x07) << 590 DMA_CFG_WR_BURST_SHIFT; 591 if (bootverbose) { 592 device_printf(dev, "Read request size : %d bytes.\n", 593 128 << ((burst >> 12) & 0x07)); 594 device_printf(dev, "TLP payload size : %d bytes.\n", 595 128 << ((burst >> 5) & 0x07)); 596 } 597 } else { 598 sc->ale_dma_rd_burst = DMA_CFG_RD_BURST_128; 599 sc->ale_dma_wr_burst = DMA_CFG_WR_BURST_128; 600 } 601 602 /* Create device sysctl node. */ 603 ale_sysctl_node(sc); 604 605 if ((error = ale_dma_alloc(sc)) != 0) 606 goto fail; 607 608 /* Load station address. */ 609 ale_get_macaddr(sc); 610 611 ifp = sc->ale_ifp = if_alloc(IFT_ETHER); 612 if_setsoftc(ifp, sc); 613 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 614 if_setflags(ifp, IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST); 615 if_setioctlfn(ifp, ale_ioctl); 616 if_setstartfn(ifp, ale_start); 617 if_setinitfn(ifp, ale_init); 618 if_setsendqlen(ifp, ALE_TX_RING_CNT - 1); 619 if_setsendqready(ifp); 620 if_setcapabilities(ifp, IFCAP_RXCSUM | IFCAP_TXCSUM | IFCAP_TSO4); 621 if_sethwassist(ifp, ALE_CSUM_FEATURES | CSUM_TSO); 622 if (pci_find_cap(dev, PCIY_PMG, &pmc) == 0) { 623 sc->ale_flags |= ALE_FLAG_PMCAP; 624 if_setcapabilitiesbit(ifp, IFCAP_WOL_MAGIC | IFCAP_WOL_MCAST, 0); 625 } 626 if_setcapenable(ifp, if_getcapabilities(ifp)); 627 628 /* Set up MII bus. */ 629 error = mii_attach(dev, &sc->ale_miibus, ifp, ale_mediachange, 630 ale_mediastatus, BMSR_DEFCAPMASK, sc->ale_phyaddr, MII_OFFSET_ANY, 631 MIIF_DOPAUSE); 632 if (error != 0) { 633 device_printf(dev, "attaching PHYs failed\n"); 634 goto fail; 635 } 636 637 ether_ifattach(ifp, sc->ale_eaddr); 638 639 /* VLAN capability setup. */ 640 if_setcapabilitiesbit(ifp, IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING | 641 IFCAP_VLAN_HWCSUM | IFCAP_VLAN_HWTSO, 0); 642 if_setcapenable(ifp, if_getcapabilities(ifp)); 643 /* 644 * Even though controllers supported by ale(3) have Rx checksum 645 * offload bug the workaround for fragmented frames seemed to 646 * work so far. However it seems Rx checksum offload does not 647 * work under certain conditions. So disable Rx checksum offload 648 * until I find more clue about it but allow users to override it. 649 */ 650 if_setcapenablebit(ifp, 0, IFCAP_RXCSUM); 651 652 /* Tell the upper layer(s) we support long frames. */ 653 if_setifheaderlen(ifp, sizeof(struct ether_vlan_header)); 654 655 /* Create local taskq. */ 656 sc->ale_tq = taskqueue_create_fast("ale_taskq", M_WAITOK, 657 taskqueue_thread_enqueue, &sc->ale_tq); 658 if (sc->ale_tq == NULL) { 659 device_printf(dev, "could not create taskqueue.\n"); 660 ether_ifdetach(ifp); 661 error = ENXIO; 662 goto fail; 663 } 664 taskqueue_start_threads(&sc->ale_tq, 1, PI_NET, "%s taskq", 665 device_get_nameunit(sc->ale_dev)); 666 667 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 668 msic = ALE_MSIX_MESSAGES; 669 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 670 msic = ALE_MSI_MESSAGES; 671 else 672 msic = 1; 673 for (i = 0; i < msic; i++) { 674 error = bus_setup_intr(dev, sc->ale_irq[i], 675 INTR_TYPE_NET | INTR_MPSAFE, ale_intr, NULL, sc, 676 &sc->ale_intrhand[i]); 677 if (error != 0) 678 break; 679 } 680 if (error != 0) { 681 device_printf(dev, "could not set up interrupt handler.\n"); 682 taskqueue_free(sc->ale_tq); 683 sc->ale_tq = NULL; 684 ether_ifdetach(ifp); 685 goto fail; 686 } 687 688 fail: 689 if (error != 0) 690 ale_detach(dev); 691 692 return (error); 693 } 694 695 static int 696 ale_detach(device_t dev) 697 { 698 struct ale_softc *sc; 699 if_t ifp; 700 int i, msic; 701 702 sc = device_get_softc(dev); 703 704 ifp = sc->ale_ifp; 705 if (device_is_attached(dev)) { 706 ether_ifdetach(ifp); 707 ALE_LOCK(sc); 708 ale_stop(sc); 709 ALE_UNLOCK(sc); 710 callout_drain(&sc->ale_tick_ch); 711 taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 712 } 713 714 if (sc->ale_tq != NULL) { 715 taskqueue_drain(sc->ale_tq, &sc->ale_int_task); 716 taskqueue_free(sc->ale_tq); 717 sc->ale_tq = NULL; 718 } 719 720 if (sc->ale_miibus != NULL) { 721 device_delete_child(dev, sc->ale_miibus); 722 sc->ale_miibus = NULL; 723 } 724 bus_generic_detach(dev); 725 ale_dma_free(sc); 726 727 if (ifp != NULL) { 728 if_free(ifp); 729 sc->ale_ifp = NULL; 730 } 731 732 if ((sc->ale_flags & ALE_FLAG_MSIX) != 0) 733 msic = ALE_MSIX_MESSAGES; 734 else if ((sc->ale_flags & ALE_FLAG_MSI) != 0) 735 msic = ALE_MSI_MESSAGES; 736 else 737 msic = 1; 738 for (i = 0; i < msic; i++) { 739 if (sc->ale_intrhand[i] != NULL) { 740 bus_teardown_intr(dev, sc->ale_irq[i], 741 sc->ale_intrhand[i]); 742 sc->ale_intrhand[i] = NULL; 743 } 744 } 745 746 bus_release_resources(dev, sc->ale_irq_spec, sc->ale_irq); 747 if ((sc->ale_flags & (ALE_FLAG_MSI | ALE_FLAG_MSIX)) != 0) 748 pci_release_msi(dev); 749 bus_release_resources(dev, sc->ale_res_spec, sc->ale_res); 750 mtx_destroy(&sc->ale_mtx); 751 752 return (0); 753 } 754 755 #define ALE_SYSCTL_STAT_ADD32(c, h, n, p, d) \ 756 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d) 757 758 #define ALE_SYSCTL_STAT_ADD64(c, h, n, p, d) \ 759 SYSCTL_ADD_UQUAD(c, h, OID_AUTO, n, CTLFLAG_RD, p, d) 760 761 static void 762 ale_sysctl_node(struct ale_softc *sc) 763 { 764 struct sysctl_ctx_list *ctx; 765 struct sysctl_oid_list *child, *parent; 766 struct sysctl_oid *tree; 767 struct ale_hw_stats *stats; 768 int error; 769 770 stats = &sc->ale_stats; 771 ctx = device_get_sysctl_ctx(sc->ale_dev); 772 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->ale_dev)); 773 774 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_rx_mod", 775 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->ale_int_rx_mod, 776 0, sysctl_hw_ale_int_mod, "I", "ale Rx interrupt moderation"); 777 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "int_tx_mod", 778 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, &sc->ale_int_tx_mod, 779 0, sysctl_hw_ale_int_mod, "I", "ale Tx interrupt moderation"); 780 /* Pull in device tunables. */ 781 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 782 error = resource_int_value(device_get_name(sc->ale_dev), 783 device_get_unit(sc->ale_dev), "int_rx_mod", &sc->ale_int_rx_mod); 784 if (error == 0) { 785 if (sc->ale_int_rx_mod < ALE_IM_TIMER_MIN || 786 sc->ale_int_rx_mod > ALE_IM_TIMER_MAX) { 787 device_printf(sc->ale_dev, "int_rx_mod value out of " 788 "range; using default: %d\n", 789 ALE_IM_RX_TIMER_DEFAULT); 790 sc->ale_int_rx_mod = ALE_IM_RX_TIMER_DEFAULT; 791 } 792 } 793 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 794 error = resource_int_value(device_get_name(sc->ale_dev), 795 device_get_unit(sc->ale_dev), "int_tx_mod", &sc->ale_int_tx_mod); 796 if (error == 0) { 797 if (sc->ale_int_tx_mod < ALE_IM_TIMER_MIN || 798 sc->ale_int_tx_mod > ALE_IM_TIMER_MAX) { 799 device_printf(sc->ale_dev, "int_tx_mod value out of " 800 "range; using default: %d\n", 801 ALE_IM_TX_TIMER_DEFAULT); 802 sc->ale_int_tx_mod = ALE_IM_TX_TIMER_DEFAULT; 803 } 804 } 805 SYSCTL_ADD_PROC(ctx, child, OID_AUTO, "process_limit", 806 CTLTYPE_INT | CTLFLAG_RW | CTLFLAG_NEEDGIANT, 807 &sc->ale_process_limit, 0, sysctl_hw_ale_proc_limit, "I", 808 "max number of Rx events to process"); 809 /* Pull in device tunables. */ 810 sc->ale_process_limit = ALE_PROC_DEFAULT; 811 error = resource_int_value(device_get_name(sc->ale_dev), 812 device_get_unit(sc->ale_dev), "process_limit", 813 &sc->ale_process_limit); 814 if (error == 0) { 815 if (sc->ale_process_limit < ALE_PROC_MIN || 816 sc->ale_process_limit > ALE_PROC_MAX) { 817 device_printf(sc->ale_dev, 818 "process_limit value out of range; " 819 "using default: %d\n", ALE_PROC_DEFAULT); 820 sc->ale_process_limit = ALE_PROC_DEFAULT; 821 } 822 } 823 824 /* Misc statistics. */ 825 ALE_SYSCTL_STAT_ADD32(ctx, child, "reset_brk_seq", 826 &stats->reset_brk_seq, 827 "Controller resets due to broken Rx sequnce number"); 828 829 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", 830 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "ATE statistics"); 831 parent = SYSCTL_CHILDREN(tree); 832 833 /* Rx statistics. */ 834 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "rx", 835 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Rx MAC statistics"); 836 child = SYSCTL_CHILDREN(tree); 837 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 838 &stats->rx_frames, "Good frames"); 839 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 840 &stats->rx_bcast_frames, "Good broadcast frames"); 841 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 842 &stats->rx_mcast_frames, "Good multicast frames"); 843 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 844 &stats->rx_pause_frames, "Pause control frames"); 845 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 846 &stats->rx_control_frames, "Control frames"); 847 ALE_SYSCTL_STAT_ADD32(ctx, child, "crc_errs", 848 &stats->rx_crcerrs, "CRC errors"); 849 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 850 &stats->rx_lenerrs, "Frames with length mismatched"); 851 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 852 &stats->rx_bytes, "Good octets"); 853 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 854 &stats->rx_bcast_bytes, "Good broadcast octets"); 855 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 856 &stats->rx_mcast_bytes, "Good multicast octets"); 857 ALE_SYSCTL_STAT_ADD32(ctx, child, "runts", 858 &stats->rx_runts, "Too short frames"); 859 ALE_SYSCTL_STAT_ADD32(ctx, child, "fragments", 860 &stats->rx_fragments, "Fragmented frames"); 861 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 862 &stats->rx_pkts_64, "64 bytes frames"); 863 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 864 &stats->rx_pkts_65_127, "65 to 127 bytes frames"); 865 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 866 &stats->rx_pkts_128_255, "128 to 255 bytes frames"); 867 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 868 &stats->rx_pkts_256_511, "256 to 511 bytes frames"); 869 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 870 &stats->rx_pkts_512_1023, "512 to 1023 bytes frames"); 871 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 872 &stats->rx_pkts_1024_1518, "1024 to 1518 bytes frames"); 873 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 874 &stats->rx_pkts_1519_max, "1519 to max frames"); 875 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 876 &stats->rx_pkts_truncated, "Truncated frames due to MTU size"); 877 ALE_SYSCTL_STAT_ADD32(ctx, child, "fifo_oflows", 878 &stats->rx_fifo_oflows, "FIFO overflows"); 879 ALE_SYSCTL_STAT_ADD32(ctx, child, "rrs_errs", 880 &stats->rx_rrs_errs, "Return status write-back errors"); 881 ALE_SYSCTL_STAT_ADD32(ctx, child, "align_errs", 882 &stats->rx_alignerrs, "Alignment errors"); 883 ALE_SYSCTL_STAT_ADD32(ctx, child, "filtered", 884 &stats->rx_pkts_filtered, 885 "Frames dropped due to address filtering"); 886 887 /* Tx statistics. */ 888 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", 889 CTLFLAG_RD | CTLFLAG_MPSAFE, NULL, "Tx MAC statistics"); 890 child = SYSCTL_CHILDREN(tree); 891 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_frames", 892 &stats->tx_frames, "Good frames"); 893 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_bcast_frames", 894 &stats->tx_bcast_frames, "Good broadcast frames"); 895 ALE_SYSCTL_STAT_ADD32(ctx, child, "good_mcast_frames", 896 &stats->tx_mcast_frames, "Good multicast frames"); 897 ALE_SYSCTL_STAT_ADD32(ctx, child, "pause_frames", 898 &stats->tx_pause_frames, "Pause control frames"); 899 ALE_SYSCTL_STAT_ADD32(ctx, child, "control_frames", 900 &stats->tx_control_frames, "Control frames"); 901 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_defers", 902 &stats->tx_excess_defer, "Frames with excessive derferrals"); 903 ALE_SYSCTL_STAT_ADD32(ctx, child, "defers", 904 &stats->tx_excess_defer, "Frames with derferrals"); 905 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_octets", 906 &stats->tx_bytes, "Good octets"); 907 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_bcast_octets", 908 &stats->tx_bcast_bytes, "Good broadcast octets"); 909 ALE_SYSCTL_STAT_ADD64(ctx, child, "good_mcast_octets", 910 &stats->tx_mcast_bytes, "Good multicast octets"); 911 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_64", 912 &stats->tx_pkts_64, "64 bytes frames"); 913 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_65_127", 914 &stats->tx_pkts_65_127, "65 to 127 bytes frames"); 915 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_128_255", 916 &stats->tx_pkts_128_255, "128 to 255 bytes frames"); 917 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_256_511", 918 &stats->tx_pkts_256_511, "256 to 511 bytes frames"); 919 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_512_1023", 920 &stats->tx_pkts_512_1023, "512 to 1023 bytes frames"); 921 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1024_1518", 922 &stats->tx_pkts_1024_1518, "1024 to 1518 bytes frames"); 923 ALE_SYSCTL_STAT_ADD32(ctx, child, "frames_1519_max", 924 &stats->tx_pkts_1519_max, "1519 to max frames"); 925 ALE_SYSCTL_STAT_ADD32(ctx, child, "single_colls", 926 &stats->tx_single_colls, "Single collisions"); 927 ALE_SYSCTL_STAT_ADD32(ctx, child, "multi_colls", 928 &stats->tx_multi_colls, "Multiple collisions"); 929 ALE_SYSCTL_STAT_ADD32(ctx, child, "late_colls", 930 &stats->tx_late_colls, "Late collisions"); 931 ALE_SYSCTL_STAT_ADD32(ctx, child, "excess_colls", 932 &stats->tx_excess_colls, "Excessive collisions"); 933 ALE_SYSCTL_STAT_ADD32(ctx, child, "underruns", 934 &stats->tx_underrun, "FIFO underruns"); 935 ALE_SYSCTL_STAT_ADD32(ctx, child, "desc_underruns", 936 &stats->tx_desc_underrun, "Descriptor write-back errors"); 937 ALE_SYSCTL_STAT_ADD32(ctx, child, "len_errs", 938 &stats->tx_lenerrs, "Frames with length mismatched"); 939 ALE_SYSCTL_STAT_ADD32(ctx, child, "trunc_errs", 940 &stats->tx_pkts_truncated, "Truncated frames due to MTU size"); 941 } 942 943 #undef ALE_SYSCTL_STAT_ADD32 944 #undef ALE_SYSCTL_STAT_ADD64 945 946 struct ale_dmamap_arg { 947 bus_addr_t ale_busaddr; 948 }; 949 950 static void 951 ale_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 952 { 953 struct ale_dmamap_arg *ctx; 954 955 if (error != 0) 956 return; 957 958 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 959 960 ctx = (struct ale_dmamap_arg *)arg; 961 ctx->ale_busaddr = segs[0].ds_addr; 962 } 963 964 /* 965 * Tx descriptors/RXF0/CMB DMA blocks share ALE_DESC_ADDR_HI register 966 * which specifies high address region of DMA blocks. Therefore these 967 * blocks should have the same high address of given 4GB address 968 * space(i.e. crossing 4GB boundary is not allowed). 969 */ 970 static int 971 ale_check_boundary(struct ale_softc *sc) 972 { 973 bus_addr_t rx_cmb_end[ALE_RX_PAGES], tx_cmb_end; 974 bus_addr_t rx_page_end[ALE_RX_PAGES], tx_ring_end; 975 976 rx_page_end[0] = sc->ale_cdata.ale_rx_page[0].page_paddr + 977 sc->ale_pagesize; 978 rx_page_end[1] = sc->ale_cdata.ale_rx_page[1].page_paddr + 979 sc->ale_pagesize; 980 tx_ring_end = sc->ale_cdata.ale_tx_ring_paddr + ALE_TX_RING_SZ; 981 tx_cmb_end = sc->ale_cdata.ale_tx_cmb_paddr + ALE_TX_CMB_SZ; 982 rx_cmb_end[0] = sc->ale_cdata.ale_rx_page[0].cmb_paddr + ALE_RX_CMB_SZ; 983 rx_cmb_end[1] = sc->ale_cdata.ale_rx_page[1].cmb_paddr + ALE_RX_CMB_SZ; 984 985 if ((ALE_ADDR_HI(tx_ring_end) != 986 ALE_ADDR_HI(sc->ale_cdata.ale_tx_ring_paddr)) || 987 (ALE_ADDR_HI(rx_page_end[0]) != 988 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].page_paddr)) || 989 (ALE_ADDR_HI(rx_page_end[1]) != 990 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].page_paddr)) || 991 (ALE_ADDR_HI(tx_cmb_end) != 992 ALE_ADDR_HI(sc->ale_cdata.ale_tx_cmb_paddr)) || 993 (ALE_ADDR_HI(rx_cmb_end[0]) != 994 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[0].cmb_paddr)) || 995 (ALE_ADDR_HI(rx_cmb_end[1]) != 996 ALE_ADDR_HI(sc->ale_cdata.ale_rx_page[1].cmb_paddr))) 997 return (EFBIG); 998 999 if ((ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[0])) || 1000 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_page_end[1])) || 1001 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[0])) || 1002 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(rx_cmb_end[1])) || 1003 (ALE_ADDR_HI(tx_ring_end) != ALE_ADDR_HI(tx_cmb_end))) 1004 return (EFBIG); 1005 1006 return (0); 1007 } 1008 1009 static int 1010 ale_dma_alloc(struct ale_softc *sc) 1011 { 1012 struct ale_txdesc *txd; 1013 bus_addr_t lowaddr; 1014 struct ale_dmamap_arg ctx; 1015 int error, guard_size, i; 1016 1017 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) 1018 guard_size = ALE_JUMBO_FRAMELEN; 1019 else 1020 guard_size = ALE_MAX_FRAMELEN; 1021 sc->ale_pagesize = roundup(guard_size + ALE_RX_PAGE_SZ, 1022 ALE_RX_PAGE_ALIGN); 1023 lowaddr = BUS_SPACE_MAXADDR; 1024 again: 1025 /* Create parent DMA tag. */ 1026 error = bus_dma_tag_create( 1027 bus_get_dma_tag(sc->ale_dev), /* parent */ 1028 1, 0, /* alignment, boundary */ 1029 lowaddr, /* lowaddr */ 1030 BUS_SPACE_MAXADDR, /* highaddr */ 1031 NULL, NULL, /* filter, filterarg */ 1032 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1033 0, /* nsegments */ 1034 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1035 0, /* flags */ 1036 NULL, NULL, /* lockfunc, lockarg */ 1037 &sc->ale_cdata.ale_parent_tag); 1038 if (error != 0) { 1039 device_printf(sc->ale_dev, 1040 "could not create parent DMA tag.\n"); 1041 goto fail; 1042 } 1043 1044 /* Create DMA tag for Tx descriptor ring. */ 1045 error = bus_dma_tag_create( 1046 sc->ale_cdata.ale_parent_tag, /* parent */ 1047 ALE_TX_RING_ALIGN, 0, /* alignment, boundary */ 1048 BUS_SPACE_MAXADDR, /* lowaddr */ 1049 BUS_SPACE_MAXADDR, /* highaddr */ 1050 NULL, NULL, /* filter, filterarg */ 1051 ALE_TX_RING_SZ, /* maxsize */ 1052 1, /* nsegments */ 1053 ALE_TX_RING_SZ, /* maxsegsize */ 1054 0, /* flags */ 1055 NULL, NULL, /* lockfunc, lockarg */ 1056 &sc->ale_cdata.ale_tx_ring_tag); 1057 if (error != 0) { 1058 device_printf(sc->ale_dev, 1059 "could not create Tx ring DMA tag.\n"); 1060 goto fail; 1061 } 1062 1063 /* Create DMA tag for Rx pages. */ 1064 for (i = 0; i < ALE_RX_PAGES; i++) { 1065 error = bus_dma_tag_create( 1066 sc->ale_cdata.ale_parent_tag, /* parent */ 1067 ALE_RX_PAGE_ALIGN, 0, /* alignment, boundary */ 1068 BUS_SPACE_MAXADDR, /* lowaddr */ 1069 BUS_SPACE_MAXADDR, /* highaddr */ 1070 NULL, NULL, /* filter, filterarg */ 1071 sc->ale_pagesize, /* maxsize */ 1072 1, /* nsegments */ 1073 sc->ale_pagesize, /* maxsegsize */ 1074 0, /* flags */ 1075 NULL, NULL, /* lockfunc, lockarg */ 1076 &sc->ale_cdata.ale_rx_page[i].page_tag); 1077 if (error != 0) { 1078 device_printf(sc->ale_dev, 1079 "could not create Rx page %d DMA tag.\n", i); 1080 goto fail; 1081 } 1082 } 1083 1084 /* Create DMA tag for Tx coalescing message block. */ 1085 error = bus_dma_tag_create( 1086 sc->ale_cdata.ale_parent_tag, /* parent */ 1087 ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1088 BUS_SPACE_MAXADDR, /* lowaddr */ 1089 BUS_SPACE_MAXADDR, /* highaddr */ 1090 NULL, NULL, /* filter, filterarg */ 1091 ALE_TX_CMB_SZ, /* maxsize */ 1092 1, /* nsegments */ 1093 ALE_TX_CMB_SZ, /* maxsegsize */ 1094 0, /* flags */ 1095 NULL, NULL, /* lockfunc, lockarg */ 1096 &sc->ale_cdata.ale_tx_cmb_tag); 1097 if (error != 0) { 1098 device_printf(sc->ale_dev, 1099 "could not create Tx CMB DMA tag.\n"); 1100 goto fail; 1101 } 1102 1103 /* Create DMA tag for Rx coalescing message block. */ 1104 for (i = 0; i < ALE_RX_PAGES; i++) { 1105 error = bus_dma_tag_create( 1106 sc->ale_cdata.ale_parent_tag, /* parent */ 1107 ALE_CMB_ALIGN, 0, /* alignment, boundary */ 1108 BUS_SPACE_MAXADDR, /* lowaddr */ 1109 BUS_SPACE_MAXADDR, /* highaddr */ 1110 NULL, NULL, /* filter, filterarg */ 1111 ALE_RX_CMB_SZ, /* maxsize */ 1112 1, /* nsegments */ 1113 ALE_RX_CMB_SZ, /* maxsegsize */ 1114 0, /* flags */ 1115 NULL, NULL, /* lockfunc, lockarg */ 1116 &sc->ale_cdata.ale_rx_page[i].cmb_tag); 1117 if (error != 0) { 1118 device_printf(sc->ale_dev, 1119 "could not create Rx page %d CMB DMA tag.\n", i); 1120 goto fail; 1121 } 1122 } 1123 1124 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 1125 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_ring_tag, 1126 (void **)&sc->ale_cdata.ale_tx_ring, 1127 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1128 &sc->ale_cdata.ale_tx_ring_map); 1129 if (error != 0) { 1130 device_printf(sc->ale_dev, 1131 "could not allocate DMA'able memory for Tx ring.\n"); 1132 goto fail; 1133 } 1134 ctx.ale_busaddr = 0; 1135 error = bus_dmamap_load(sc->ale_cdata.ale_tx_ring_tag, 1136 sc->ale_cdata.ale_tx_ring_map, sc->ale_cdata.ale_tx_ring, 1137 ALE_TX_RING_SZ, ale_dmamap_cb, &ctx, 0); 1138 if (error != 0 || ctx.ale_busaddr == 0) { 1139 device_printf(sc->ale_dev, 1140 "could not load DMA'able memory for Tx ring.\n"); 1141 goto fail; 1142 } 1143 sc->ale_cdata.ale_tx_ring_paddr = ctx.ale_busaddr; 1144 1145 /* Rx pages. */ 1146 for (i = 0; i < ALE_RX_PAGES; i++) { 1147 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].page_tag, 1148 (void **)&sc->ale_cdata.ale_rx_page[i].page_addr, 1149 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1150 &sc->ale_cdata.ale_rx_page[i].page_map); 1151 if (error != 0) { 1152 device_printf(sc->ale_dev, 1153 "could not allocate DMA'able memory for " 1154 "Rx page %d.\n", i); 1155 goto fail; 1156 } 1157 ctx.ale_busaddr = 0; 1158 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].page_tag, 1159 sc->ale_cdata.ale_rx_page[i].page_map, 1160 sc->ale_cdata.ale_rx_page[i].page_addr, 1161 sc->ale_pagesize, ale_dmamap_cb, &ctx, 0); 1162 if (error != 0 || ctx.ale_busaddr == 0) { 1163 device_printf(sc->ale_dev, 1164 "could not load DMA'able memory for " 1165 "Rx page %d.\n", i); 1166 goto fail; 1167 } 1168 sc->ale_cdata.ale_rx_page[i].page_paddr = ctx.ale_busaddr; 1169 } 1170 1171 /* Tx CMB. */ 1172 error = bus_dmamem_alloc(sc->ale_cdata.ale_tx_cmb_tag, 1173 (void **)&sc->ale_cdata.ale_tx_cmb, 1174 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1175 &sc->ale_cdata.ale_tx_cmb_map); 1176 if (error != 0) { 1177 device_printf(sc->ale_dev, 1178 "could not allocate DMA'able memory for Tx CMB.\n"); 1179 goto fail; 1180 } 1181 ctx.ale_busaddr = 0; 1182 error = bus_dmamap_load(sc->ale_cdata.ale_tx_cmb_tag, 1183 sc->ale_cdata.ale_tx_cmb_map, sc->ale_cdata.ale_tx_cmb, 1184 ALE_TX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1185 if (error != 0 || ctx.ale_busaddr == 0) { 1186 device_printf(sc->ale_dev, 1187 "could not load DMA'able memory for Tx CMB.\n"); 1188 goto fail; 1189 } 1190 sc->ale_cdata.ale_tx_cmb_paddr = ctx.ale_busaddr; 1191 1192 /* Rx CMB. */ 1193 for (i = 0; i < ALE_RX_PAGES; i++) { 1194 error = bus_dmamem_alloc(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1195 (void **)&sc->ale_cdata.ale_rx_page[i].cmb_addr, 1196 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 1197 &sc->ale_cdata.ale_rx_page[i].cmb_map); 1198 if (error != 0) { 1199 device_printf(sc->ale_dev, "could not allocate " 1200 "DMA'able memory for Rx page %d CMB.\n", i); 1201 goto fail; 1202 } 1203 ctx.ale_busaddr = 0; 1204 error = bus_dmamap_load(sc->ale_cdata.ale_rx_page[i].cmb_tag, 1205 sc->ale_cdata.ale_rx_page[i].cmb_map, 1206 sc->ale_cdata.ale_rx_page[i].cmb_addr, 1207 ALE_RX_CMB_SZ, ale_dmamap_cb, &ctx, 0); 1208 if (error != 0 || ctx.ale_busaddr == 0) { 1209 device_printf(sc->ale_dev, "could not load DMA'able " 1210 "memory for Rx page %d CMB.\n", i); 1211 goto fail; 1212 } 1213 sc->ale_cdata.ale_rx_page[i].cmb_paddr = ctx.ale_busaddr; 1214 } 1215 1216 /* 1217 * Tx descriptors/RXF0/CMB DMA blocks share the same 1218 * high address region of 64bit DMA address space. 1219 */ 1220 if (lowaddr != BUS_SPACE_MAXADDR_32BIT && 1221 (error = ale_check_boundary(sc)) != 0) { 1222 device_printf(sc->ale_dev, "4GB boundary crossed, " 1223 "switching to 32bit DMA addressing mode.\n"); 1224 ale_dma_free(sc); 1225 /* 1226 * Limit max allowable DMA address space to 32bit 1227 * and try again. 1228 */ 1229 lowaddr = BUS_SPACE_MAXADDR_32BIT; 1230 goto again; 1231 } 1232 1233 /* 1234 * Create Tx buffer parent tag. 1235 * AR81xx allows 64bit DMA addressing of Tx buffers so it 1236 * needs separate parent DMA tag as parent DMA address space 1237 * could be restricted to be within 32bit address space by 1238 * 4GB boundary crossing. 1239 */ 1240 error = bus_dma_tag_create( 1241 bus_get_dma_tag(sc->ale_dev), /* parent */ 1242 1, 0, /* alignment, boundary */ 1243 BUS_SPACE_MAXADDR, /* lowaddr */ 1244 BUS_SPACE_MAXADDR, /* highaddr */ 1245 NULL, NULL, /* filter, filterarg */ 1246 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 1247 0, /* nsegments */ 1248 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 1249 0, /* flags */ 1250 NULL, NULL, /* lockfunc, lockarg */ 1251 &sc->ale_cdata.ale_buffer_tag); 1252 if (error != 0) { 1253 device_printf(sc->ale_dev, 1254 "could not create parent buffer DMA tag.\n"); 1255 goto fail; 1256 } 1257 1258 /* Create DMA tag for Tx buffers. */ 1259 error = bus_dma_tag_create( 1260 sc->ale_cdata.ale_buffer_tag, /* parent */ 1261 1, 0, /* alignment, boundary */ 1262 BUS_SPACE_MAXADDR, /* lowaddr */ 1263 BUS_SPACE_MAXADDR, /* highaddr */ 1264 NULL, NULL, /* filter, filterarg */ 1265 ALE_TSO_MAXSIZE, /* maxsize */ 1266 ALE_MAXTXSEGS, /* nsegments */ 1267 ALE_TSO_MAXSEGSIZE, /* maxsegsize */ 1268 0, /* flags */ 1269 NULL, NULL, /* lockfunc, lockarg */ 1270 &sc->ale_cdata.ale_tx_tag); 1271 if (error != 0) { 1272 device_printf(sc->ale_dev, "could not create Tx DMA tag.\n"); 1273 goto fail; 1274 } 1275 1276 /* Create DMA maps for Tx buffers. */ 1277 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1278 txd = &sc->ale_cdata.ale_txdesc[i]; 1279 txd->tx_m = NULL; 1280 txd->tx_dmamap = NULL; 1281 error = bus_dmamap_create(sc->ale_cdata.ale_tx_tag, 0, 1282 &txd->tx_dmamap); 1283 if (error != 0) { 1284 device_printf(sc->ale_dev, 1285 "could not create Tx dmamap.\n"); 1286 goto fail; 1287 } 1288 } 1289 1290 fail: 1291 return (error); 1292 } 1293 1294 static void 1295 ale_dma_free(struct ale_softc *sc) 1296 { 1297 struct ale_txdesc *txd; 1298 int i; 1299 1300 /* Tx buffers. */ 1301 if (sc->ale_cdata.ale_tx_tag != NULL) { 1302 for (i = 0; i < ALE_TX_RING_CNT; i++) { 1303 txd = &sc->ale_cdata.ale_txdesc[i]; 1304 if (txd->tx_dmamap != NULL) { 1305 bus_dmamap_destroy(sc->ale_cdata.ale_tx_tag, 1306 txd->tx_dmamap); 1307 txd->tx_dmamap = NULL; 1308 } 1309 } 1310 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_tag); 1311 sc->ale_cdata.ale_tx_tag = NULL; 1312 } 1313 /* Tx descriptor ring. */ 1314 if (sc->ale_cdata.ale_tx_ring_tag != NULL) { 1315 if (sc->ale_cdata.ale_tx_ring_paddr != 0) 1316 bus_dmamap_unload(sc->ale_cdata.ale_tx_ring_tag, 1317 sc->ale_cdata.ale_tx_ring_map); 1318 if (sc->ale_cdata.ale_tx_ring != NULL) 1319 bus_dmamem_free(sc->ale_cdata.ale_tx_ring_tag, 1320 sc->ale_cdata.ale_tx_ring, 1321 sc->ale_cdata.ale_tx_ring_map); 1322 sc->ale_cdata.ale_tx_ring_paddr = 0; 1323 sc->ale_cdata.ale_tx_ring = NULL; 1324 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_ring_tag); 1325 sc->ale_cdata.ale_tx_ring_tag = NULL; 1326 } 1327 /* Rx page block. */ 1328 for (i = 0; i < ALE_RX_PAGES; i++) { 1329 if (sc->ale_cdata.ale_rx_page[i].page_tag != NULL) { 1330 if (sc->ale_cdata.ale_rx_page[i].page_paddr != 0) 1331 bus_dmamap_unload( 1332 sc->ale_cdata.ale_rx_page[i].page_tag, 1333 sc->ale_cdata.ale_rx_page[i].page_map); 1334 if (sc->ale_cdata.ale_rx_page[i].page_addr != NULL) 1335 bus_dmamem_free( 1336 sc->ale_cdata.ale_rx_page[i].page_tag, 1337 sc->ale_cdata.ale_rx_page[i].page_addr, 1338 sc->ale_cdata.ale_rx_page[i].page_map); 1339 sc->ale_cdata.ale_rx_page[i].page_paddr = 0; 1340 sc->ale_cdata.ale_rx_page[i].page_addr = NULL; 1341 bus_dma_tag_destroy( 1342 sc->ale_cdata.ale_rx_page[i].page_tag); 1343 sc->ale_cdata.ale_rx_page[i].page_tag = NULL; 1344 } 1345 } 1346 /* Rx CMB. */ 1347 for (i = 0; i < ALE_RX_PAGES; i++) { 1348 if (sc->ale_cdata.ale_rx_page[i].cmb_tag != NULL) { 1349 if (sc->ale_cdata.ale_rx_page[i].cmb_paddr != 0) 1350 bus_dmamap_unload( 1351 sc->ale_cdata.ale_rx_page[i].cmb_tag, 1352 sc->ale_cdata.ale_rx_page[i].cmb_map); 1353 if (sc->ale_cdata.ale_rx_page[i].cmb_addr != NULL) 1354 bus_dmamem_free( 1355 sc->ale_cdata.ale_rx_page[i].cmb_tag, 1356 sc->ale_cdata.ale_rx_page[i].cmb_addr, 1357 sc->ale_cdata.ale_rx_page[i].cmb_map); 1358 sc->ale_cdata.ale_rx_page[i].cmb_paddr = 0; 1359 sc->ale_cdata.ale_rx_page[i].cmb_addr = NULL; 1360 bus_dma_tag_destroy( 1361 sc->ale_cdata.ale_rx_page[i].cmb_tag); 1362 sc->ale_cdata.ale_rx_page[i].cmb_tag = NULL; 1363 } 1364 } 1365 /* Tx CMB. */ 1366 if (sc->ale_cdata.ale_tx_cmb_tag != NULL) { 1367 if (sc->ale_cdata.ale_tx_cmb_paddr != 0) 1368 bus_dmamap_unload(sc->ale_cdata.ale_tx_cmb_tag, 1369 sc->ale_cdata.ale_tx_cmb_map); 1370 if (sc->ale_cdata.ale_tx_cmb != NULL) 1371 bus_dmamem_free(sc->ale_cdata.ale_tx_cmb_tag, 1372 sc->ale_cdata.ale_tx_cmb, 1373 sc->ale_cdata.ale_tx_cmb_map); 1374 sc->ale_cdata.ale_tx_cmb_paddr = 0; 1375 sc->ale_cdata.ale_tx_cmb = NULL; 1376 bus_dma_tag_destroy(sc->ale_cdata.ale_tx_cmb_tag); 1377 sc->ale_cdata.ale_tx_cmb_tag = NULL; 1378 } 1379 if (sc->ale_cdata.ale_buffer_tag != NULL) { 1380 bus_dma_tag_destroy(sc->ale_cdata.ale_buffer_tag); 1381 sc->ale_cdata.ale_buffer_tag = NULL; 1382 } 1383 if (sc->ale_cdata.ale_parent_tag != NULL) { 1384 bus_dma_tag_destroy(sc->ale_cdata.ale_parent_tag); 1385 sc->ale_cdata.ale_parent_tag = NULL; 1386 } 1387 } 1388 1389 static int 1390 ale_shutdown(device_t dev) 1391 { 1392 1393 return (ale_suspend(dev)); 1394 } 1395 1396 /* 1397 * Note, this driver resets the link speed to 10/100Mbps by 1398 * restarting auto-negotiation in suspend/shutdown phase but we 1399 * don't know whether that auto-negotiation would succeed or not 1400 * as driver has no control after powering off/suspend operation. 1401 * If the renegotiation fail WOL may not work. Running at 1Gbps 1402 * will draw more power than 375mA at 3.3V which is specified in 1403 * PCI specification and that would result in complete 1404 * shutdowning power to ethernet controller. 1405 * 1406 * TODO 1407 * Save current negotiated media speed/duplex/flow-control to 1408 * softc and restore the same link again after resuming. PHY 1409 * handling such as power down/resetting to 100Mbps may be better 1410 * handled in suspend method in phy driver. 1411 */ 1412 static void 1413 ale_setlinkspeed(struct ale_softc *sc) 1414 { 1415 struct mii_data *mii; 1416 int aneg, i; 1417 1418 mii = device_get_softc(sc->ale_miibus); 1419 mii_pollstat(mii); 1420 aneg = 0; 1421 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 1422 (IFM_ACTIVE | IFM_AVALID)) { 1423 switch IFM_SUBTYPE(mii->mii_media_active) { 1424 case IFM_10_T: 1425 case IFM_100_TX: 1426 return; 1427 case IFM_1000_T: 1428 aneg++; 1429 break; 1430 default: 1431 break; 1432 } 1433 } 1434 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, MII_100T2CR, 0); 1435 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1436 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 1437 ale_miibus_writereg(sc->ale_dev, sc->ale_phyaddr, 1438 MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG); 1439 DELAY(1000); 1440 if (aneg != 0) { 1441 /* 1442 * Poll link state until ale(4) get a 10/100Mbps link. 1443 */ 1444 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 1445 mii_pollstat(mii); 1446 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 1447 == (IFM_ACTIVE | IFM_AVALID)) { 1448 switch (IFM_SUBTYPE( 1449 mii->mii_media_active)) { 1450 case IFM_10_T: 1451 case IFM_100_TX: 1452 ale_mac_config(sc); 1453 return; 1454 default: 1455 break; 1456 } 1457 } 1458 ALE_UNLOCK(sc); 1459 pause("alelnk", hz); 1460 ALE_LOCK(sc); 1461 } 1462 if (i == MII_ANEGTICKS_GIGE) 1463 device_printf(sc->ale_dev, 1464 "establishing a link failed, WOL may not work!"); 1465 } 1466 /* 1467 * No link, force MAC to have 100Mbps, full-duplex link. 1468 * This is the last resort and may/may not work. 1469 */ 1470 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 1471 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 1472 ale_mac_config(sc); 1473 } 1474 1475 static void 1476 ale_setwol(struct ale_softc *sc) 1477 { 1478 if_t ifp; 1479 uint32_t reg, pmcs; 1480 uint16_t pmstat; 1481 int pmc; 1482 1483 ALE_LOCK_ASSERT(sc); 1484 1485 if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) != 0) { 1486 /* Disable WOL. */ 1487 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 1488 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1489 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1490 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1491 /* Force PHY power down. */ 1492 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1493 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1494 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_PHY_PLL_ON | 1495 GPHY_CTRL_SEL_ANA_RESET | GPHY_CTRL_PHY_IDDQ | 1496 GPHY_CTRL_PCLK_SEL_DIS | GPHY_CTRL_PWDOWN_HW); 1497 return; 1498 } 1499 1500 ifp = sc->ale_ifp; 1501 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) { 1502 if ((sc->ale_flags & ALE_FLAG_FASTETHER) == 0) 1503 ale_setlinkspeed(sc); 1504 } 1505 1506 pmcs = 0; 1507 if ((if_getcapenable(ifp) & IFCAP_WOL_MAGIC) != 0) 1508 pmcs |= WOL_CFG_MAGIC | WOL_CFG_MAGIC_ENB; 1509 CSR_WRITE_4(sc, ALE_WOL_CFG, pmcs); 1510 reg = CSR_READ_4(sc, ALE_MAC_CFG); 1511 reg &= ~(MAC_CFG_DBG | MAC_CFG_PROMISC | MAC_CFG_ALLMULTI | 1512 MAC_CFG_BCAST); 1513 if ((if_getcapenable(ifp) & IFCAP_WOL_MCAST) != 0) 1514 reg |= MAC_CFG_ALLMULTI | MAC_CFG_BCAST; 1515 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 1516 reg |= MAC_CFG_RX_ENB; 1517 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 1518 1519 if ((if_getcapenable(ifp) & IFCAP_WOL) == 0) { 1520 /* WOL disabled, PHY power down. */ 1521 reg = CSR_READ_4(sc, ALE_PCIE_PHYMISC); 1522 reg |= PCIE_PHYMISC_FORCE_RCV_DET; 1523 CSR_WRITE_4(sc, ALE_PCIE_PHYMISC, reg); 1524 CSR_WRITE_2(sc, ALE_GPHY_CTRL, 1525 GPHY_CTRL_EXT_RESET | GPHY_CTRL_HIB_EN | 1526 GPHY_CTRL_HIB_PULSE | GPHY_CTRL_SEL_ANA_RESET | 1527 GPHY_CTRL_PHY_IDDQ | GPHY_CTRL_PCLK_SEL_DIS | 1528 GPHY_CTRL_PWDOWN_HW); 1529 } 1530 /* Request PME. */ 1531 pmstat = pci_read_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, 2); 1532 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 1533 if ((if_getcapenable(ifp) & IFCAP_WOL) != 0) 1534 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 1535 pci_write_config(sc->ale_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 1536 } 1537 1538 static int 1539 ale_suspend(device_t dev) 1540 { 1541 struct ale_softc *sc; 1542 1543 sc = device_get_softc(dev); 1544 1545 ALE_LOCK(sc); 1546 ale_stop(sc); 1547 ale_setwol(sc); 1548 ALE_UNLOCK(sc); 1549 1550 return (0); 1551 } 1552 1553 static int 1554 ale_resume(device_t dev) 1555 { 1556 struct ale_softc *sc; 1557 if_t ifp; 1558 int pmc; 1559 uint16_t pmstat; 1560 1561 sc = device_get_softc(dev); 1562 1563 ALE_LOCK(sc); 1564 if (pci_find_cap(sc->ale_dev, PCIY_PMG, &pmc) == 0) { 1565 /* Disable PME and clear PME status. */ 1566 pmstat = pci_read_config(sc->ale_dev, 1567 pmc + PCIR_POWER_STATUS, 2); 1568 if ((pmstat & PCIM_PSTAT_PMEENABLE) != 0) { 1569 pmstat &= ~PCIM_PSTAT_PMEENABLE; 1570 pci_write_config(sc->ale_dev, 1571 pmc + PCIR_POWER_STATUS, pmstat, 2); 1572 } 1573 } 1574 /* Reset PHY. */ 1575 ale_phy_reset(sc); 1576 ifp = sc->ale_ifp; 1577 if ((if_getflags(ifp) & IFF_UP) != 0) { 1578 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1579 ale_init_locked(sc); 1580 } 1581 ALE_UNLOCK(sc); 1582 1583 return (0); 1584 } 1585 1586 static int 1587 ale_encap(struct ale_softc *sc, struct mbuf **m_head) 1588 { 1589 struct ale_txdesc *txd, *txd_last; 1590 struct tx_desc *desc; 1591 struct mbuf *m; 1592 struct ip *ip; 1593 struct tcphdr *tcp; 1594 bus_dma_segment_t txsegs[ALE_MAXTXSEGS]; 1595 bus_dmamap_t map; 1596 uint32_t cflags, hdrlen, ip_off, poff, vtag; 1597 int error, i, nsegs, prod, si; 1598 1599 ALE_LOCK_ASSERT(sc); 1600 1601 M_ASSERTPKTHDR((*m_head)); 1602 1603 m = *m_head; 1604 ip = NULL; 1605 tcp = NULL; 1606 cflags = vtag = 0; 1607 ip_off = poff = 0; 1608 if ((m->m_pkthdr.csum_flags & (ALE_CSUM_FEATURES | CSUM_TSO)) != 0) { 1609 /* 1610 * AR81xx requires offset of TCP/UDP payload in its Tx 1611 * descriptor to perform hardware Tx checksum offload. 1612 * Additionally, TSO requires IP/TCP header size and 1613 * modification of IP/TCP header in order to make TSO 1614 * engine work. This kind of operation takes many CPU 1615 * cycles on FreeBSD so fast host CPU is required to 1616 * get smooth TSO performance. 1617 */ 1618 struct ether_header *eh; 1619 1620 if (M_WRITABLE(m) == 0) { 1621 /* Get a writable copy. */ 1622 m = m_dup(*m_head, M_NOWAIT); 1623 /* Release original mbufs. */ 1624 m_freem(*m_head); 1625 if (m == NULL) { 1626 *m_head = NULL; 1627 return (ENOBUFS); 1628 } 1629 *m_head = m; 1630 } 1631 1632 /* 1633 * Buggy-controller requires 4 byte aligned Tx buffer 1634 * to make custom checksum offload work. 1635 */ 1636 if ((sc->ale_flags & ALE_FLAG_TXCSUM_BUG) != 0 && 1637 (m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0 && 1638 (mtod(m, intptr_t) & 3) != 0) { 1639 m = m_defrag(*m_head, M_NOWAIT); 1640 if (m == NULL) { 1641 m_freem(*m_head); 1642 *m_head = NULL; 1643 return (ENOBUFS); 1644 } 1645 *m_head = m; 1646 } 1647 1648 ip_off = sizeof(struct ether_header); 1649 m = m_pullup(m, ip_off); 1650 if (m == NULL) { 1651 *m_head = NULL; 1652 return (ENOBUFS); 1653 } 1654 eh = mtod(m, struct ether_header *); 1655 /* 1656 * Check if hardware VLAN insertion is off. 1657 * Additional check for LLC/SNAP frame? 1658 */ 1659 if (eh->ether_type == htons(ETHERTYPE_VLAN)) { 1660 ip_off = sizeof(struct ether_vlan_header); 1661 m = m_pullup(m, ip_off); 1662 if (m == NULL) { 1663 *m_head = NULL; 1664 return (ENOBUFS); 1665 } 1666 } 1667 m = m_pullup(m, ip_off + sizeof(struct ip)); 1668 if (m == NULL) { 1669 *m_head = NULL; 1670 return (ENOBUFS); 1671 } 1672 ip = (struct ip *)(mtod(m, char *) + ip_off); 1673 poff = ip_off + (ip->ip_hl << 2); 1674 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1675 /* 1676 * XXX 1677 * AR81xx requires the first descriptor should 1678 * not include any TCP playload for TSO case. 1679 * (i.e. ethernet header + IP + TCP header only) 1680 * m_pullup(9) above will ensure this too. 1681 * However it's not correct if the first mbuf 1682 * of the chain does not use cluster. 1683 */ 1684 m = m_pullup(m, poff + sizeof(struct tcphdr)); 1685 if (m == NULL) { 1686 *m_head = NULL; 1687 return (ENOBUFS); 1688 } 1689 ip = (struct ip *)(mtod(m, char *) + ip_off); 1690 tcp = (struct tcphdr *)(mtod(m, char *) + poff); 1691 m = m_pullup(m, poff + (tcp->th_off << 2)); 1692 if (m == NULL) { 1693 *m_head = NULL; 1694 return (ENOBUFS); 1695 } 1696 /* 1697 * AR81xx requires IP/TCP header size and offset as 1698 * well as TCP pseudo checksum which complicates 1699 * TSO configuration. I guess this comes from the 1700 * adherence to Microsoft NDIS Large Send 1701 * specification which requires insertion of 1702 * pseudo checksum by upper stack. The pseudo 1703 * checksum that NDIS refers to doesn't include 1704 * TCP payload length so ale(4) should recompute 1705 * the pseudo checksum here. Hopefully this wouldn't 1706 * be much burden on modern CPUs. 1707 * Reset IP checksum and recompute TCP pseudo 1708 * checksum as NDIS specification said. 1709 */ 1710 ip->ip_sum = 0; 1711 tcp->th_sum = in_pseudo(ip->ip_src.s_addr, 1712 ip->ip_dst.s_addr, htons(IPPROTO_TCP)); 1713 } 1714 *m_head = m; 1715 } 1716 1717 si = prod = sc->ale_cdata.ale_tx_prod; 1718 txd = &sc->ale_cdata.ale_txdesc[prod]; 1719 txd_last = txd; 1720 map = txd->tx_dmamap; 1721 1722 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1723 *m_head, txsegs, &nsegs, 0); 1724 if (error == EFBIG) { 1725 m = m_collapse(*m_head, M_NOWAIT, ALE_MAXTXSEGS); 1726 if (m == NULL) { 1727 m_freem(*m_head); 1728 *m_head = NULL; 1729 return (ENOMEM); 1730 } 1731 *m_head = m; 1732 error = bus_dmamap_load_mbuf_sg(sc->ale_cdata.ale_tx_tag, map, 1733 *m_head, txsegs, &nsegs, 0); 1734 if (error != 0) { 1735 m_freem(*m_head); 1736 *m_head = NULL; 1737 return (error); 1738 } 1739 } else if (error != 0) 1740 return (error); 1741 if (nsegs == 0) { 1742 m_freem(*m_head); 1743 *m_head = NULL; 1744 return (EIO); 1745 } 1746 1747 /* Check descriptor overrun. */ 1748 if (sc->ale_cdata.ale_tx_cnt + nsegs >= ALE_TX_RING_CNT - 3) { 1749 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, map); 1750 return (ENOBUFS); 1751 } 1752 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, map, BUS_DMASYNC_PREWRITE); 1753 1754 m = *m_head; 1755 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1756 /* Request TSO and set MSS. */ 1757 cflags |= ALE_TD_TSO; 1758 cflags |= ((uint32_t)m->m_pkthdr.tso_segsz << ALE_TD_MSS_SHIFT); 1759 /* Set IP/TCP header size. */ 1760 cflags |= ip->ip_hl << ALE_TD_IPHDR_LEN_SHIFT; 1761 cflags |= tcp->th_off << ALE_TD_TCPHDR_LEN_SHIFT; 1762 } else if ((m->m_pkthdr.csum_flags & ALE_CSUM_FEATURES) != 0) { 1763 /* 1764 * AR81xx supports Tx custom checksum offload feature 1765 * that offloads single 16bit checksum computation. 1766 * So you can choose one among IP, TCP and UDP. 1767 * Normally driver sets checksum start/insertion 1768 * position from the information of TCP/UDP frame as 1769 * TCP/UDP checksum takes more time than that of IP. 1770 * However it seems that custom checksum offload 1771 * requires 4 bytes aligned Tx buffers due to hardware 1772 * bug. 1773 * AR81xx also supports explicit Tx checksum computation 1774 * if it is told that the size of IP header and TCP 1775 * header(for UDP, the header size does not matter 1776 * because it's fixed length). However with this scheme 1777 * TSO does not work so you have to choose one either 1778 * TSO or explicit Tx checksum offload. I chosen TSO 1779 * plus custom checksum offload with work-around which 1780 * will cover most common usage for this consumer 1781 * ethernet controller. The work-around takes a lot of 1782 * CPU cycles if Tx buffer is not aligned on 4 bytes 1783 * boundary, though. 1784 */ 1785 cflags |= ALE_TD_CXSUM; 1786 /* Set checksum start offset. */ 1787 cflags |= (poff << ALE_TD_CSUM_PLOADOFFSET_SHIFT); 1788 /* Set checksum insertion position of TCP/UDP. */ 1789 cflags |= ((poff + m->m_pkthdr.csum_data) << 1790 ALE_TD_CSUM_XSUMOFFSET_SHIFT); 1791 } 1792 1793 /* Configure VLAN hardware tag insertion. */ 1794 if ((m->m_flags & M_VLANTAG) != 0) { 1795 vtag = ALE_TX_VLAN_TAG(m->m_pkthdr.ether_vtag); 1796 vtag = ((vtag << ALE_TD_VLAN_SHIFT) & ALE_TD_VLAN_MASK); 1797 cflags |= ALE_TD_INSERT_VLAN_TAG; 1798 } 1799 1800 i = 0; 1801 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1802 /* 1803 * Make sure the first fragment contains 1804 * only ethernet and IP/TCP header with options. 1805 */ 1806 hdrlen = poff + (tcp->th_off << 2); 1807 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1808 desc->addr = htole64(txsegs[i].ds_addr); 1809 desc->len = htole32(ALE_TX_BYTES(hdrlen) | vtag); 1810 desc->flags = htole32(cflags); 1811 sc->ale_cdata.ale_tx_cnt++; 1812 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1813 if (m->m_len - hdrlen > 0) { 1814 /* Handle remaining payload of the first fragment. */ 1815 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1816 desc->addr = htole64(txsegs[i].ds_addr + hdrlen); 1817 desc->len = htole32(ALE_TX_BYTES(m->m_len - hdrlen) | 1818 vtag); 1819 desc->flags = htole32(cflags); 1820 sc->ale_cdata.ale_tx_cnt++; 1821 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1822 } 1823 i = 1; 1824 } 1825 for (; i < nsegs; i++) { 1826 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1827 desc->addr = htole64(txsegs[i].ds_addr); 1828 desc->len = htole32(ALE_TX_BYTES(txsegs[i].ds_len) | vtag); 1829 desc->flags = htole32(cflags); 1830 sc->ale_cdata.ale_tx_cnt++; 1831 ALE_DESC_INC(prod, ALE_TX_RING_CNT); 1832 } 1833 /* Update producer index. */ 1834 sc->ale_cdata.ale_tx_prod = prod; 1835 /* Set TSO header on the first descriptor. */ 1836 if ((m->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 1837 desc = &sc->ale_cdata.ale_tx_ring[si]; 1838 desc->flags |= htole32(ALE_TD_TSO_HDR); 1839 } 1840 1841 /* Finally set EOP on the last descriptor. */ 1842 prod = (prod + ALE_TX_RING_CNT - 1) % ALE_TX_RING_CNT; 1843 desc = &sc->ale_cdata.ale_tx_ring[prod]; 1844 desc->flags |= htole32(ALE_TD_EOP); 1845 1846 /* Swap dmamap of the first and the last. */ 1847 txd = &sc->ale_cdata.ale_txdesc[prod]; 1848 map = txd_last->tx_dmamap; 1849 txd_last->tx_dmamap = txd->tx_dmamap; 1850 txd->tx_dmamap = map; 1851 txd->tx_m = m; 1852 1853 /* Sync descriptors. */ 1854 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 1855 sc->ale_cdata.ale_tx_ring_map, 1856 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1857 1858 return (0); 1859 } 1860 1861 static void 1862 ale_start(if_t ifp) 1863 { 1864 struct ale_softc *sc; 1865 1866 sc = if_getsoftc(ifp); 1867 ALE_LOCK(sc); 1868 ale_start_locked(ifp); 1869 ALE_UNLOCK(sc); 1870 } 1871 1872 static void 1873 ale_start_locked(if_t ifp) 1874 { 1875 struct ale_softc *sc; 1876 struct mbuf *m_head; 1877 int enq; 1878 1879 sc = if_getsoftc(ifp); 1880 1881 ALE_LOCK_ASSERT(sc); 1882 1883 /* Reclaim transmitted frames. */ 1884 if (sc->ale_cdata.ale_tx_cnt >= ALE_TX_DESC_HIWAT) 1885 ale_txeof(sc); 1886 1887 if ((if_getdrvflags(ifp) & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1888 IFF_DRV_RUNNING || (sc->ale_flags & ALE_FLAG_LINK) == 0) 1889 return; 1890 1891 for (enq = 0; !if_sendq_empty(ifp); ) { 1892 m_head = if_dequeue(ifp); 1893 if (m_head == NULL) 1894 break; 1895 /* 1896 * Pack the data into the transmit ring. If we 1897 * don't have room, set the OACTIVE flag and wait 1898 * for the NIC to drain the ring. 1899 */ 1900 if (ale_encap(sc, &m_head)) { 1901 if (m_head == NULL) 1902 break; 1903 if_sendq_prepend(ifp, m_head); 1904 if_setdrvflagbits(ifp, IFF_DRV_OACTIVE, 0); 1905 break; 1906 } 1907 1908 enq++; 1909 /* 1910 * If there's a BPF listener, bounce a copy of this frame 1911 * to him. 1912 */ 1913 ETHER_BPF_MTAP(ifp, m_head); 1914 } 1915 1916 if (enq > 0) { 1917 /* Kick. */ 1918 CSR_WRITE_4(sc, ALE_MBOX_TPD_PROD_IDX, 1919 sc->ale_cdata.ale_tx_prod); 1920 /* Set a timeout in case the chip goes out to lunch. */ 1921 sc->ale_watchdog_timer = ALE_TX_TIMEOUT; 1922 } 1923 } 1924 1925 static void 1926 ale_watchdog(struct ale_softc *sc) 1927 { 1928 if_t ifp; 1929 1930 ALE_LOCK_ASSERT(sc); 1931 1932 if (sc->ale_watchdog_timer == 0 || --sc->ale_watchdog_timer) 1933 return; 1934 1935 ifp = sc->ale_ifp; 1936 if ((sc->ale_flags & ALE_FLAG_LINK) == 0) { 1937 if_printf(sc->ale_ifp, "watchdog timeout (lost link)\n"); 1938 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1939 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1940 ale_init_locked(sc); 1941 return; 1942 } 1943 if_printf(sc->ale_ifp, "watchdog timeout -- resetting\n"); 1944 if_inc_counter(ifp, IFCOUNTER_OERRORS, 1); 1945 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1946 ale_init_locked(sc); 1947 if (!if_sendq_empty(ifp)) 1948 ale_start_locked(ifp); 1949 } 1950 1951 static int 1952 ale_ioctl(if_t ifp, u_long cmd, caddr_t data) 1953 { 1954 struct ale_softc *sc; 1955 struct ifreq *ifr; 1956 struct mii_data *mii; 1957 int error, mask; 1958 1959 sc = if_getsoftc(ifp); 1960 ifr = (struct ifreq *)data; 1961 error = 0; 1962 switch (cmd) { 1963 case SIOCSIFMTU: 1964 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ALE_JUMBO_MTU || 1965 ((sc->ale_flags & ALE_FLAG_JUMBO) == 0 && 1966 ifr->ifr_mtu > ETHERMTU)) 1967 error = EINVAL; 1968 else if (if_getmtu(ifp) != ifr->ifr_mtu) { 1969 ALE_LOCK(sc); 1970 if_setmtu(ifp, ifr->ifr_mtu); 1971 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1972 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 1973 ale_init_locked(sc); 1974 } 1975 ALE_UNLOCK(sc); 1976 } 1977 break; 1978 case SIOCSIFFLAGS: 1979 ALE_LOCK(sc); 1980 if ((if_getflags(ifp) & IFF_UP) != 0) { 1981 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 1982 if (((if_getflags(ifp) ^ sc->ale_if_flags) 1983 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 1984 ale_rxfilter(sc); 1985 } else { 1986 ale_init_locked(sc); 1987 } 1988 } else { 1989 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1990 ale_stop(sc); 1991 } 1992 sc->ale_if_flags = if_getflags(ifp); 1993 ALE_UNLOCK(sc); 1994 break; 1995 case SIOCADDMULTI: 1996 case SIOCDELMULTI: 1997 ALE_LOCK(sc); 1998 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 1999 ale_rxfilter(sc); 2000 ALE_UNLOCK(sc); 2001 break; 2002 case SIOCSIFMEDIA: 2003 case SIOCGIFMEDIA: 2004 mii = device_get_softc(sc->ale_miibus); 2005 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd); 2006 break; 2007 case SIOCSIFCAP: 2008 ALE_LOCK(sc); 2009 mask = ifr->ifr_reqcap ^ if_getcapenable(ifp); 2010 if ((mask & IFCAP_TXCSUM) != 0 && 2011 (if_getcapabilities(ifp) & IFCAP_TXCSUM) != 0) { 2012 if_togglecapenable(ifp, IFCAP_TXCSUM); 2013 if ((if_getcapenable(ifp) & IFCAP_TXCSUM) != 0) 2014 if_sethwassistbits(ifp, ALE_CSUM_FEATURES, 0); 2015 else 2016 if_sethwassistbits(ifp, 0, ALE_CSUM_FEATURES); 2017 } 2018 if ((mask & IFCAP_RXCSUM) != 0 && 2019 (if_getcapabilities(ifp) & IFCAP_RXCSUM) != 0) 2020 if_togglecapenable(ifp, IFCAP_RXCSUM); 2021 if ((mask & IFCAP_TSO4) != 0 && 2022 (if_getcapabilities(ifp) & IFCAP_TSO4) != 0) { 2023 if_togglecapenable(ifp, IFCAP_TSO4); 2024 if ((if_getcapenable(ifp) & IFCAP_TSO4) != 0) 2025 if_sethwassistbits(ifp, CSUM_TSO, 0); 2026 else 2027 if_sethwassistbits(ifp, 0, CSUM_TSO); 2028 } 2029 2030 if ((mask & IFCAP_WOL_MCAST) != 0 && 2031 (if_getcapabilities(ifp) & IFCAP_WOL_MCAST) != 0) 2032 if_togglecapenable(ifp, IFCAP_WOL_MCAST); 2033 if ((mask & IFCAP_WOL_MAGIC) != 0 && 2034 (if_getcapabilities(ifp) & IFCAP_WOL_MAGIC) != 0) 2035 if_togglecapenable(ifp, IFCAP_WOL_MAGIC); 2036 if ((mask & IFCAP_VLAN_HWCSUM) != 0 && 2037 (if_getcapabilities(ifp) & IFCAP_VLAN_HWCSUM) != 0) 2038 if_togglecapenable(ifp, IFCAP_VLAN_HWCSUM); 2039 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 2040 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTSO) != 0) 2041 if_togglecapenable(ifp, IFCAP_VLAN_HWTSO); 2042 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 2043 (if_getcapabilities(ifp) & IFCAP_VLAN_HWTAGGING) != 0) { 2044 if_togglecapenable(ifp, IFCAP_VLAN_HWTAGGING); 2045 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0) 2046 if_setcapenablebit(ifp, 0, IFCAP_VLAN_HWTSO); 2047 ale_rxvlan(sc); 2048 } 2049 ALE_UNLOCK(sc); 2050 VLAN_CAPABILITIES(ifp); 2051 break; 2052 default: 2053 error = ether_ioctl(ifp, cmd, data); 2054 break; 2055 } 2056 2057 return (error); 2058 } 2059 2060 static void 2061 ale_mac_config(struct ale_softc *sc) 2062 { 2063 struct mii_data *mii; 2064 uint32_t reg; 2065 2066 ALE_LOCK_ASSERT(sc); 2067 2068 mii = device_get_softc(sc->ale_miibus); 2069 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2070 reg &= ~(MAC_CFG_FULL_DUPLEX | MAC_CFG_TX_FC | MAC_CFG_RX_FC | 2071 MAC_CFG_SPEED_MASK); 2072 /* Reprogram MAC with resolved speed/duplex. */ 2073 switch (IFM_SUBTYPE(mii->mii_media_active)) { 2074 case IFM_10_T: 2075 case IFM_100_TX: 2076 reg |= MAC_CFG_SPEED_10_100; 2077 break; 2078 case IFM_1000_T: 2079 reg |= MAC_CFG_SPEED_1000; 2080 break; 2081 } 2082 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_FDX) != 0) { 2083 reg |= MAC_CFG_FULL_DUPLEX; 2084 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_TXPAUSE) != 0) 2085 reg |= MAC_CFG_TX_FC; 2086 if ((IFM_OPTIONS(mii->mii_media_active) & IFM_ETH_RXPAUSE) != 0) 2087 reg |= MAC_CFG_RX_FC; 2088 } 2089 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2090 } 2091 2092 static void 2093 ale_stats_clear(struct ale_softc *sc) 2094 { 2095 struct smb sb; 2096 uint32_t *reg; 2097 int i; 2098 2099 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2100 CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2101 i += sizeof(uint32_t); 2102 } 2103 /* Read Tx statistics. */ 2104 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2105 CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2106 i += sizeof(uint32_t); 2107 } 2108 } 2109 2110 static void 2111 ale_stats_update(struct ale_softc *sc) 2112 { 2113 struct ale_hw_stats *stat; 2114 struct smb sb, *smb; 2115 if_t ifp; 2116 uint32_t *reg; 2117 int i; 2118 2119 ALE_LOCK_ASSERT(sc); 2120 2121 ifp = sc->ale_ifp; 2122 stat = &sc->ale_stats; 2123 smb = &sb; 2124 2125 /* Read Rx statistics. */ 2126 for (reg = &sb.rx_frames, i = 0; reg <= &sb.rx_pkts_filtered; reg++) { 2127 *reg = CSR_READ_4(sc, ALE_RX_MIB_BASE + i); 2128 i += sizeof(uint32_t); 2129 } 2130 /* Read Tx statistics. */ 2131 for (reg = &sb.tx_frames, i = 0; reg <= &sb.tx_mcast_bytes; reg++) { 2132 *reg = CSR_READ_4(sc, ALE_TX_MIB_BASE + i); 2133 i += sizeof(uint32_t); 2134 } 2135 2136 /* Rx stats. */ 2137 stat->rx_frames += smb->rx_frames; 2138 stat->rx_bcast_frames += smb->rx_bcast_frames; 2139 stat->rx_mcast_frames += smb->rx_mcast_frames; 2140 stat->rx_pause_frames += smb->rx_pause_frames; 2141 stat->rx_control_frames += smb->rx_control_frames; 2142 stat->rx_crcerrs += smb->rx_crcerrs; 2143 stat->rx_lenerrs += smb->rx_lenerrs; 2144 stat->rx_bytes += smb->rx_bytes; 2145 stat->rx_runts += smb->rx_runts; 2146 stat->rx_fragments += smb->rx_fragments; 2147 stat->rx_pkts_64 += smb->rx_pkts_64; 2148 stat->rx_pkts_65_127 += smb->rx_pkts_65_127; 2149 stat->rx_pkts_128_255 += smb->rx_pkts_128_255; 2150 stat->rx_pkts_256_511 += smb->rx_pkts_256_511; 2151 stat->rx_pkts_512_1023 += smb->rx_pkts_512_1023; 2152 stat->rx_pkts_1024_1518 += smb->rx_pkts_1024_1518; 2153 stat->rx_pkts_1519_max += smb->rx_pkts_1519_max; 2154 stat->rx_pkts_truncated += smb->rx_pkts_truncated; 2155 stat->rx_fifo_oflows += smb->rx_fifo_oflows; 2156 stat->rx_rrs_errs += smb->rx_rrs_errs; 2157 stat->rx_alignerrs += smb->rx_alignerrs; 2158 stat->rx_bcast_bytes += smb->rx_bcast_bytes; 2159 stat->rx_mcast_bytes += smb->rx_mcast_bytes; 2160 stat->rx_pkts_filtered += smb->rx_pkts_filtered; 2161 2162 /* Tx stats. */ 2163 stat->tx_frames += smb->tx_frames; 2164 stat->tx_bcast_frames += smb->tx_bcast_frames; 2165 stat->tx_mcast_frames += smb->tx_mcast_frames; 2166 stat->tx_pause_frames += smb->tx_pause_frames; 2167 stat->tx_excess_defer += smb->tx_excess_defer; 2168 stat->tx_control_frames += smb->tx_control_frames; 2169 stat->tx_deferred += smb->tx_deferred; 2170 stat->tx_bytes += smb->tx_bytes; 2171 stat->tx_pkts_64 += smb->tx_pkts_64; 2172 stat->tx_pkts_65_127 += smb->tx_pkts_65_127; 2173 stat->tx_pkts_128_255 += smb->tx_pkts_128_255; 2174 stat->tx_pkts_256_511 += smb->tx_pkts_256_511; 2175 stat->tx_pkts_512_1023 += smb->tx_pkts_512_1023; 2176 stat->tx_pkts_1024_1518 += smb->tx_pkts_1024_1518; 2177 stat->tx_pkts_1519_max += smb->tx_pkts_1519_max; 2178 stat->tx_single_colls += smb->tx_single_colls; 2179 stat->tx_multi_colls += smb->tx_multi_colls; 2180 stat->tx_late_colls += smb->tx_late_colls; 2181 stat->tx_excess_colls += smb->tx_excess_colls; 2182 stat->tx_underrun += smb->tx_underrun; 2183 stat->tx_desc_underrun += smb->tx_desc_underrun; 2184 stat->tx_lenerrs += smb->tx_lenerrs; 2185 stat->tx_pkts_truncated += smb->tx_pkts_truncated; 2186 stat->tx_bcast_bytes += smb->tx_bcast_bytes; 2187 stat->tx_mcast_bytes += smb->tx_mcast_bytes; 2188 2189 /* Update counters in ifnet. */ 2190 if_inc_counter(ifp, IFCOUNTER_OPACKETS, smb->tx_frames); 2191 2192 if_inc_counter(ifp, IFCOUNTER_COLLISIONS, smb->tx_single_colls + 2193 smb->tx_multi_colls * 2 + smb->tx_late_colls + 2194 smb->tx_excess_colls * HDPX_CFG_RETRY_DEFAULT); 2195 2196 if_inc_counter(ifp, IFCOUNTER_OERRORS, smb->tx_late_colls + 2197 smb->tx_excess_colls + smb->tx_underrun + smb->tx_pkts_truncated); 2198 2199 if_inc_counter(ifp, IFCOUNTER_IPACKETS, smb->rx_frames); 2200 2201 if_inc_counter(ifp, IFCOUNTER_IERRORS, 2202 smb->rx_crcerrs + smb->rx_lenerrs + 2203 smb->rx_runts + smb->rx_pkts_truncated + 2204 smb->rx_fifo_oflows + smb->rx_rrs_errs + 2205 smb->rx_alignerrs); 2206 } 2207 2208 static int 2209 ale_intr(void *arg) 2210 { 2211 struct ale_softc *sc; 2212 uint32_t status; 2213 2214 sc = (struct ale_softc *)arg; 2215 2216 status = CSR_READ_4(sc, ALE_INTR_STATUS); 2217 if ((status & ALE_INTRS) == 0) 2218 return (FILTER_STRAY); 2219 /* Disable interrupts. */ 2220 CSR_WRITE_4(sc, ALE_INTR_STATUS, INTR_DIS_INT); 2221 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2222 2223 return (FILTER_HANDLED); 2224 } 2225 2226 static void 2227 ale_int_task(void *arg, int pending) 2228 { 2229 struct ale_softc *sc; 2230 if_t ifp; 2231 uint32_t status; 2232 int more; 2233 2234 sc = (struct ale_softc *)arg; 2235 2236 status = CSR_READ_4(sc, ALE_INTR_STATUS); 2237 ALE_LOCK(sc); 2238 if (sc->ale_morework != 0) 2239 status |= INTR_RX_PKT; 2240 if ((status & ALE_INTRS) == 0) 2241 goto done; 2242 2243 /* Acknowledge interrupts but still disable interrupts. */ 2244 CSR_WRITE_4(sc, ALE_INTR_STATUS, status | INTR_DIS_INT); 2245 2246 ifp = sc->ale_ifp; 2247 more = 0; 2248 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) { 2249 more = ale_rxeof(sc, sc->ale_process_limit); 2250 if (more == EAGAIN) 2251 sc->ale_morework = 1; 2252 else if (more == EIO) { 2253 sc->ale_stats.reset_brk_seq++; 2254 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2255 ale_init_locked(sc); 2256 ALE_UNLOCK(sc); 2257 return; 2258 } 2259 2260 if ((status & (INTR_DMA_RD_TO_RST | INTR_DMA_WR_TO_RST)) != 0) { 2261 if ((status & INTR_DMA_RD_TO_RST) != 0) 2262 device_printf(sc->ale_dev, 2263 "DMA read error! -- resetting\n"); 2264 if ((status & INTR_DMA_WR_TO_RST) != 0) 2265 device_printf(sc->ale_dev, 2266 "DMA write error! -- resetting\n"); 2267 if_setdrvflagbits(ifp, 0, IFF_DRV_RUNNING); 2268 ale_init_locked(sc); 2269 ALE_UNLOCK(sc); 2270 return; 2271 } 2272 if (!if_sendq_empty(ifp)) 2273 ale_start_locked(ifp); 2274 } 2275 2276 if (more == EAGAIN || 2277 (CSR_READ_4(sc, ALE_INTR_STATUS) & ALE_INTRS) != 0) { 2278 ALE_UNLOCK(sc); 2279 taskqueue_enqueue(sc->ale_tq, &sc->ale_int_task); 2280 return; 2281 } 2282 2283 done: 2284 ALE_UNLOCK(sc); 2285 2286 /* Re-enable interrupts. */ 2287 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0x7FFFFFFF); 2288 } 2289 2290 static void 2291 ale_txeof(struct ale_softc *sc) 2292 { 2293 if_t ifp; 2294 struct ale_txdesc *txd; 2295 uint32_t cons, prod; 2296 int prog; 2297 2298 ALE_LOCK_ASSERT(sc); 2299 2300 ifp = sc->ale_ifp; 2301 2302 if (sc->ale_cdata.ale_tx_cnt == 0) 2303 return; 2304 2305 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2306 sc->ale_cdata.ale_tx_ring_map, 2307 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2308 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) { 2309 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2310 sc->ale_cdata.ale_tx_cmb_map, 2311 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2312 prod = *sc->ale_cdata.ale_tx_cmb & TPD_CNT_MASK; 2313 } else 2314 prod = CSR_READ_2(sc, ALE_TPD_CONS_IDX); 2315 cons = sc->ale_cdata.ale_tx_cons; 2316 /* 2317 * Go through our Tx list and free mbufs for those 2318 * frames which have been transmitted. 2319 */ 2320 for (prog = 0; cons != prod; prog++, 2321 ALE_DESC_INC(cons, ALE_TX_RING_CNT)) { 2322 if (sc->ale_cdata.ale_tx_cnt <= 0) 2323 break; 2324 prog++; 2325 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2326 sc->ale_cdata.ale_tx_cnt--; 2327 txd = &sc->ale_cdata.ale_txdesc[cons]; 2328 if (txd->tx_m != NULL) { 2329 /* Reclaim transmitted mbufs. */ 2330 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2331 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2332 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2333 txd->tx_dmamap); 2334 m_freem(txd->tx_m); 2335 txd->tx_m = NULL; 2336 } 2337 } 2338 2339 if (prog > 0) { 2340 sc->ale_cdata.ale_tx_cons = cons; 2341 /* 2342 * Unarm watchdog timer only when there is no pending 2343 * Tx descriptors in queue. 2344 */ 2345 if (sc->ale_cdata.ale_tx_cnt == 0) 2346 sc->ale_watchdog_timer = 0; 2347 } 2348 } 2349 2350 static void 2351 ale_rx_update_page(struct ale_softc *sc, struct ale_rx_page **page, 2352 uint32_t length, uint32_t *prod) 2353 { 2354 struct ale_rx_page *rx_page; 2355 2356 rx_page = *page; 2357 /* Update consumer position. */ 2358 rx_page->cons += roundup(length + sizeof(struct rx_rs), 2359 ALE_RX_PAGE_ALIGN); 2360 if (rx_page->cons >= ALE_RX_PAGE_SZ) { 2361 /* 2362 * End of Rx page reached, let hardware reuse 2363 * this page. 2364 */ 2365 rx_page->cons = 0; 2366 *rx_page->cmb_addr = 0; 2367 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2368 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2369 CSR_WRITE_1(sc, ALE_RXF0_PAGE0 + sc->ale_cdata.ale_rx_curp, 2370 RXF_VALID); 2371 /* Switch to alternate Rx page. */ 2372 sc->ale_cdata.ale_rx_curp ^= 1; 2373 rx_page = *page = 2374 &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2375 /* Page flipped, sync CMB and Rx page. */ 2376 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2377 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2378 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2379 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2380 /* Sync completed, cache updated producer index. */ 2381 *prod = *rx_page->cmb_addr; 2382 } 2383 } 2384 2385 /* 2386 * It seems that AR81xx controller can compute partial checksum. 2387 * The partial checksum value can be used to accelerate checksum 2388 * computation for fragmented TCP/UDP packets. Upper network stack 2389 * already takes advantage of the partial checksum value in IP 2390 * reassembly stage. But I'm not sure the correctness of the 2391 * partial hardware checksum assistance due to lack of data sheet. 2392 * In addition, the Rx feature of controller that requires copying 2393 * for every frames effectively nullifies one of most nice offload 2394 * capability of controller. 2395 */ 2396 static void 2397 ale_rxcsum(struct ale_softc *sc, struct mbuf *m, uint32_t status) 2398 { 2399 if_t ifp; 2400 struct ip *ip; 2401 char *p; 2402 2403 ifp = sc->ale_ifp; 2404 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 2405 if ((status & ALE_RD_IPCSUM_NOK) == 0) 2406 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 2407 2408 if ((sc->ale_flags & ALE_FLAG_RXCSUM_BUG) == 0) { 2409 if (((status & ALE_RD_IPV4_FRAG) == 0) && 2410 ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0) && 2411 ((status & ALE_RD_TCP_UDPCSUM_NOK) == 0)) { 2412 m->m_pkthdr.csum_flags |= 2413 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 2414 m->m_pkthdr.csum_data = 0xffff; 2415 } 2416 } else { 2417 if ((status & (ALE_RD_TCP | ALE_RD_UDP)) != 0 && 2418 (status & ALE_RD_TCP_UDPCSUM_NOK) == 0) { 2419 p = mtod(m, char *); 2420 p += ETHER_HDR_LEN; 2421 if ((status & ALE_RD_802_3) != 0) 2422 p += LLC_SNAPFRAMELEN; 2423 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) == 0 && 2424 (status & ALE_RD_VLAN) != 0) 2425 p += ETHER_VLAN_ENCAP_LEN; 2426 ip = (struct ip *)p; 2427 if (ip->ip_off != 0 && (status & ALE_RD_IPV4_DF) == 0) 2428 return; 2429 m->m_pkthdr.csum_flags |= CSUM_DATA_VALID | 2430 CSUM_PSEUDO_HDR; 2431 m->m_pkthdr.csum_data = 0xffff; 2432 } 2433 } 2434 /* 2435 * Don't mark bad checksum for TCP/UDP frames 2436 * as fragmented frames may always have set 2437 * bad checksummed bit of frame status. 2438 */ 2439 } 2440 2441 /* Process received frames. */ 2442 static int 2443 ale_rxeof(struct ale_softc *sc, int count) 2444 { 2445 struct ale_rx_page *rx_page; 2446 struct rx_rs *rs; 2447 if_t ifp; 2448 struct mbuf *m; 2449 uint32_t length, prod, seqno, status, vtags; 2450 int prog; 2451 2452 ifp = sc->ale_ifp; 2453 rx_page = &sc->ale_cdata.ale_rx_page[sc->ale_cdata.ale_rx_curp]; 2454 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2455 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2456 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2457 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2458 /* 2459 * Don't directly access producer index as hardware may 2460 * update it while Rx handler is in progress. It would 2461 * be even better if there is a way to let hardware 2462 * know how far driver processed its received frames. 2463 * Alternatively, hardware could provide a way to disable 2464 * CMB updates until driver acknowledges the end of CMB 2465 * access. 2466 */ 2467 prod = *rx_page->cmb_addr; 2468 for (prog = 0; prog < count; prog++) { 2469 if (rx_page->cons >= prod) 2470 break; 2471 rs = (struct rx_rs *)(rx_page->page_addr + rx_page->cons); 2472 seqno = ALE_RX_SEQNO(le32toh(rs->seqno)); 2473 if (sc->ale_cdata.ale_rx_seqno != seqno) { 2474 /* 2475 * Normally I believe this should not happen unless 2476 * severe driver bug or corrupted memory. However 2477 * it seems to happen under certain conditions which 2478 * is triggered by abrupt Rx events such as initiation 2479 * of bulk transfer of remote host. It's not easy to 2480 * reproduce this and I doubt it could be related 2481 * with FIFO overflow of hardware or activity of Tx 2482 * CMB updates. I also remember similar behaviour 2483 * seen on RealTek 8139 which uses resembling Rx 2484 * scheme. 2485 */ 2486 if (bootverbose) 2487 device_printf(sc->ale_dev, 2488 "garbled seq: %u, expected: %u -- " 2489 "resetting!\n", seqno, 2490 sc->ale_cdata.ale_rx_seqno); 2491 return (EIO); 2492 } 2493 /* Frame received. */ 2494 sc->ale_cdata.ale_rx_seqno++; 2495 length = ALE_RX_BYTES(le32toh(rs->length)); 2496 status = le32toh(rs->flags); 2497 if ((status & ALE_RD_ERROR) != 0) { 2498 /* 2499 * We want to pass the following frames to upper 2500 * layer regardless of error status of Rx return 2501 * status. 2502 * 2503 * o IP/TCP/UDP checksum is bad. 2504 * o frame length and protocol specific length 2505 * does not match. 2506 */ 2507 if ((status & (ALE_RD_CRC | ALE_RD_CODE | 2508 ALE_RD_DRIBBLE | ALE_RD_RUNT | ALE_RD_OFLOW | 2509 ALE_RD_TRUNC)) != 0) { 2510 ale_rx_update_page(sc, &rx_page, length, &prod); 2511 continue; 2512 } 2513 } 2514 /* 2515 * m_devget(9) is major bottle-neck of ale(4)(It comes 2516 * from hardware limitation). For jumbo frames we could 2517 * get a slightly better performance if driver use 2518 * m_getjcl(9) with proper buffer size argument. However 2519 * that would make code more complicated and I don't 2520 * think users would expect good Rx performance numbers 2521 * on these low-end consumer ethernet controller. 2522 */ 2523 m = m_devget((char *)(rs + 1), length - ETHER_CRC_LEN, 2524 ETHER_ALIGN, ifp, NULL); 2525 if (m == NULL) { 2526 if_inc_counter(ifp, IFCOUNTER_IQDROPS, 1); 2527 ale_rx_update_page(sc, &rx_page, length, &prod); 2528 continue; 2529 } 2530 if ((if_getcapenable(ifp) & IFCAP_RXCSUM) != 0 && 2531 (status & ALE_RD_IPV4) != 0) 2532 ale_rxcsum(sc, m, status); 2533 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0 && 2534 (status & ALE_RD_VLAN) != 0) { 2535 vtags = ALE_RX_VLAN(le32toh(rs->vtags)); 2536 m->m_pkthdr.ether_vtag = ALE_RX_VLAN_TAG(vtags); 2537 m->m_flags |= M_VLANTAG; 2538 } 2539 2540 /* Pass it to upper layer. */ 2541 ALE_UNLOCK(sc); 2542 if_input(ifp, m); 2543 ALE_LOCK(sc); 2544 2545 ale_rx_update_page(sc, &rx_page, length, &prod); 2546 } 2547 2548 return (count > 0 ? 0 : EAGAIN); 2549 } 2550 2551 static void 2552 ale_tick(void *arg) 2553 { 2554 struct ale_softc *sc; 2555 struct mii_data *mii; 2556 2557 sc = (struct ale_softc *)arg; 2558 2559 ALE_LOCK_ASSERT(sc); 2560 2561 mii = device_get_softc(sc->ale_miibus); 2562 mii_tick(mii); 2563 ale_stats_update(sc); 2564 /* 2565 * Reclaim Tx buffers that have been transferred. It's not 2566 * needed here but it would release allocated mbuf chains 2567 * faster and limit the maximum delay to a hz. 2568 */ 2569 ale_txeof(sc); 2570 ale_watchdog(sc); 2571 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2572 } 2573 2574 static void 2575 ale_reset(struct ale_softc *sc) 2576 { 2577 uint32_t reg; 2578 int i; 2579 2580 /* Initialize PCIe module. From Linux. */ 2581 CSR_WRITE_4(sc, 0x1008, CSR_READ_4(sc, 0x1008) | 0x8000); 2582 2583 CSR_WRITE_4(sc, ALE_MASTER_CFG, MASTER_RESET); 2584 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2585 DELAY(10); 2586 if ((CSR_READ_4(sc, ALE_MASTER_CFG) & MASTER_RESET) == 0) 2587 break; 2588 } 2589 if (i == 0) 2590 device_printf(sc->ale_dev, "master reset timeout!\n"); 2591 2592 for (i = ALE_RESET_TIMEOUT; i > 0; i--) { 2593 if ((reg = CSR_READ_4(sc, ALE_IDLE_STATUS)) == 0) 2594 break; 2595 DELAY(10); 2596 } 2597 2598 if (i == 0) 2599 device_printf(sc->ale_dev, "reset timeout(0x%08x)!\n", reg); 2600 } 2601 2602 static void 2603 ale_init(void *xsc) 2604 { 2605 struct ale_softc *sc; 2606 2607 sc = (struct ale_softc *)xsc; 2608 ALE_LOCK(sc); 2609 ale_init_locked(sc); 2610 ALE_UNLOCK(sc); 2611 } 2612 2613 static void 2614 ale_init_locked(struct ale_softc *sc) 2615 { 2616 if_t ifp; 2617 struct mii_data *mii; 2618 uint8_t eaddr[ETHER_ADDR_LEN]; 2619 bus_addr_t paddr; 2620 uint32_t reg, rxf_hi, rxf_lo; 2621 2622 ALE_LOCK_ASSERT(sc); 2623 2624 ifp = sc->ale_ifp; 2625 mii = device_get_softc(sc->ale_miibus); 2626 2627 if ((if_getdrvflags(ifp) & IFF_DRV_RUNNING) != 0) 2628 return; 2629 /* 2630 * Cancel any pending I/O. 2631 */ 2632 ale_stop(sc); 2633 /* 2634 * Reset the chip to a known state. 2635 */ 2636 ale_reset(sc); 2637 /* Initialize Tx descriptors, DMA memory blocks. */ 2638 ale_init_rx_pages(sc); 2639 ale_init_tx_ring(sc); 2640 2641 /* Reprogram the station address. */ 2642 bcopy(if_getlladdr(ifp), eaddr, ETHER_ADDR_LEN); 2643 CSR_WRITE_4(sc, ALE_PAR0, 2644 eaddr[2] << 24 | eaddr[3] << 16 | eaddr[4] << 8 | eaddr[5]); 2645 CSR_WRITE_4(sc, ALE_PAR1, eaddr[0] << 8 | eaddr[1]); 2646 /* 2647 * Clear WOL status and disable all WOL feature as WOL 2648 * would interfere Rx operation under normal environments. 2649 */ 2650 CSR_READ_4(sc, ALE_WOL_CFG); 2651 CSR_WRITE_4(sc, ALE_WOL_CFG, 0); 2652 /* 2653 * Set Tx descriptor/RXF0/CMB base addresses. They share 2654 * the same high address part of DMAable region. 2655 */ 2656 paddr = sc->ale_cdata.ale_tx_ring_paddr; 2657 CSR_WRITE_4(sc, ALE_TPD_ADDR_HI, ALE_ADDR_HI(paddr)); 2658 CSR_WRITE_4(sc, ALE_TPD_ADDR_LO, ALE_ADDR_LO(paddr)); 2659 CSR_WRITE_4(sc, ALE_TPD_CNT, 2660 (ALE_TX_RING_CNT << TPD_CNT_SHIFT) & TPD_CNT_MASK); 2661 /* Set Rx page base address, note we use single queue. */ 2662 paddr = sc->ale_cdata.ale_rx_page[0].page_paddr; 2663 CSR_WRITE_4(sc, ALE_RXF0_PAGE0_ADDR_LO, ALE_ADDR_LO(paddr)); 2664 paddr = sc->ale_cdata.ale_rx_page[1].page_paddr; 2665 CSR_WRITE_4(sc, ALE_RXF0_PAGE1_ADDR_LO, ALE_ADDR_LO(paddr)); 2666 /* Set Tx/Rx CMB addresses. */ 2667 paddr = sc->ale_cdata.ale_tx_cmb_paddr; 2668 CSR_WRITE_4(sc, ALE_TX_CMB_ADDR_LO, ALE_ADDR_LO(paddr)); 2669 paddr = sc->ale_cdata.ale_rx_page[0].cmb_paddr; 2670 CSR_WRITE_4(sc, ALE_RXF0_CMB0_ADDR_LO, ALE_ADDR_LO(paddr)); 2671 paddr = sc->ale_cdata.ale_rx_page[1].cmb_paddr; 2672 CSR_WRITE_4(sc, ALE_RXF0_CMB1_ADDR_LO, ALE_ADDR_LO(paddr)); 2673 /* Mark RXF0 is valid. */ 2674 CSR_WRITE_1(sc, ALE_RXF0_PAGE0, RXF_VALID); 2675 CSR_WRITE_1(sc, ALE_RXF0_PAGE1, RXF_VALID); 2676 /* 2677 * No need to initialize RFX1/RXF2/RXF3. We don't use 2678 * multi-queue yet. 2679 */ 2680 2681 /* Set Rx page size, excluding guard frame size. */ 2682 CSR_WRITE_4(sc, ALE_RXF_PAGE_SIZE, ALE_RX_PAGE_SZ); 2683 /* Tell hardware that we're ready to load DMA blocks. */ 2684 CSR_WRITE_4(sc, ALE_DMA_BLOCK, DMA_BLOCK_LOAD); 2685 2686 /* Set Rx/Tx interrupt trigger threshold. */ 2687 CSR_WRITE_4(sc, ALE_INT_TRIG_THRESH, (1 << INT_TRIG_RX_THRESH_SHIFT) | 2688 (4 << INT_TRIG_TX_THRESH_SHIFT)); 2689 /* 2690 * XXX 2691 * Set interrupt trigger timer, its purpose and relation 2692 * with interrupt moderation mechanism is not clear yet. 2693 */ 2694 CSR_WRITE_4(sc, ALE_INT_TRIG_TIMER, 2695 ((ALE_USECS(10) << INT_TRIG_RX_TIMER_SHIFT) | 2696 (ALE_USECS(1000) << INT_TRIG_TX_TIMER_SHIFT))); 2697 2698 /* Configure interrupt moderation timer. */ 2699 reg = ALE_USECS(sc->ale_int_rx_mod) << IM_TIMER_RX_SHIFT; 2700 reg |= ALE_USECS(sc->ale_int_tx_mod) << IM_TIMER_TX_SHIFT; 2701 CSR_WRITE_4(sc, ALE_IM_TIMER, reg); 2702 reg = CSR_READ_4(sc, ALE_MASTER_CFG); 2703 reg &= ~(MASTER_CHIP_REV_MASK | MASTER_CHIP_ID_MASK); 2704 reg &= ~(MASTER_IM_RX_TIMER_ENB | MASTER_IM_TX_TIMER_ENB); 2705 if (ALE_USECS(sc->ale_int_rx_mod) != 0) 2706 reg |= MASTER_IM_RX_TIMER_ENB; 2707 if (ALE_USECS(sc->ale_int_tx_mod) != 0) 2708 reg |= MASTER_IM_TX_TIMER_ENB; 2709 CSR_WRITE_4(sc, ALE_MASTER_CFG, reg); 2710 CSR_WRITE_2(sc, ALE_INTR_CLR_TIMER, ALE_USECS(1000)); 2711 2712 /* Set Maximum frame size of controller. */ 2713 if (if_getmtu(ifp) < ETHERMTU) 2714 sc->ale_max_frame_size = ETHERMTU; 2715 else 2716 sc->ale_max_frame_size = if_getmtu(ifp); 2717 sc->ale_max_frame_size += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + 2718 ETHER_CRC_LEN; 2719 CSR_WRITE_4(sc, ALE_FRAME_SIZE, sc->ale_max_frame_size); 2720 /* Configure IPG/IFG parameters. */ 2721 CSR_WRITE_4(sc, ALE_IPG_IFG_CFG, 2722 ((IPG_IFG_IPGT_DEFAULT << IPG_IFG_IPGT_SHIFT) & IPG_IFG_IPGT_MASK) | 2723 ((IPG_IFG_MIFG_DEFAULT << IPG_IFG_MIFG_SHIFT) & IPG_IFG_MIFG_MASK) | 2724 ((IPG_IFG_IPG1_DEFAULT << IPG_IFG_IPG1_SHIFT) & IPG_IFG_IPG1_MASK) | 2725 ((IPG_IFG_IPG2_DEFAULT << IPG_IFG_IPG2_SHIFT) & IPG_IFG_IPG2_MASK)); 2726 /* Set parameters for half-duplex media. */ 2727 CSR_WRITE_4(sc, ALE_HDPX_CFG, 2728 ((HDPX_CFG_LCOL_DEFAULT << HDPX_CFG_LCOL_SHIFT) & 2729 HDPX_CFG_LCOL_MASK) | 2730 ((HDPX_CFG_RETRY_DEFAULT << HDPX_CFG_RETRY_SHIFT) & 2731 HDPX_CFG_RETRY_MASK) | HDPX_CFG_EXC_DEF_EN | 2732 ((HDPX_CFG_ABEBT_DEFAULT << HDPX_CFG_ABEBT_SHIFT) & 2733 HDPX_CFG_ABEBT_MASK) | 2734 ((HDPX_CFG_JAMIPG_DEFAULT << HDPX_CFG_JAMIPG_SHIFT) & 2735 HDPX_CFG_JAMIPG_MASK)); 2736 2737 /* Configure Tx jumbo frame parameters. */ 2738 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2739 if (if_getmtu(ifp) < ETHERMTU) 2740 reg = sc->ale_max_frame_size; 2741 else if (if_getmtu(ifp) < 6 * 1024) 2742 reg = (sc->ale_max_frame_size * 2) / 3; 2743 else 2744 reg = sc->ale_max_frame_size / 2; 2745 CSR_WRITE_4(sc, ALE_TX_JUMBO_THRESH, 2746 roundup(reg, TX_JUMBO_THRESH_UNIT) >> 2747 TX_JUMBO_THRESH_UNIT_SHIFT); 2748 } 2749 /* Configure TxQ. */ 2750 reg = (128 << (sc->ale_dma_rd_burst >> DMA_CFG_RD_BURST_SHIFT)) 2751 << TXQ_CFG_TX_FIFO_BURST_SHIFT; 2752 reg |= (TXQ_CFG_TPD_BURST_DEFAULT << TXQ_CFG_TPD_BURST_SHIFT) & 2753 TXQ_CFG_TPD_BURST_MASK; 2754 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg | TXQ_CFG_ENHANCED_MODE | TXQ_CFG_ENB); 2755 2756 /* Configure Rx jumbo frame & flow control parameters. */ 2757 if ((sc->ale_flags & ALE_FLAG_JUMBO) != 0) { 2758 reg = roundup(sc->ale_max_frame_size, RX_JUMBO_THRESH_UNIT); 2759 CSR_WRITE_4(sc, ALE_RX_JUMBO_THRESH, 2760 (((reg >> RX_JUMBO_THRESH_UNIT_SHIFT) << 2761 RX_JUMBO_THRESH_MASK_SHIFT) & RX_JUMBO_THRESH_MASK) | 2762 ((RX_JUMBO_LKAH_DEFAULT << RX_JUMBO_LKAH_SHIFT) & 2763 RX_JUMBO_LKAH_MASK)); 2764 reg = CSR_READ_4(sc, ALE_SRAM_RX_FIFO_LEN); 2765 rxf_hi = (reg * 7) / 10; 2766 rxf_lo = (reg * 3)/ 10; 2767 CSR_WRITE_4(sc, ALE_RX_FIFO_PAUSE_THRESH, 2768 ((rxf_lo << RX_FIFO_PAUSE_THRESH_LO_SHIFT) & 2769 RX_FIFO_PAUSE_THRESH_LO_MASK) | 2770 ((rxf_hi << RX_FIFO_PAUSE_THRESH_HI_SHIFT) & 2771 RX_FIFO_PAUSE_THRESH_HI_MASK)); 2772 } 2773 2774 /* Disable RSS. */ 2775 CSR_WRITE_4(sc, ALE_RSS_IDT_TABLE0, 0); 2776 CSR_WRITE_4(sc, ALE_RSS_CPU, 0); 2777 2778 /* Configure RxQ. */ 2779 CSR_WRITE_4(sc, ALE_RXQ_CFG, 2780 RXQ_CFG_ALIGN_32 | RXQ_CFG_CUT_THROUGH_ENB | RXQ_CFG_ENB); 2781 2782 /* Configure DMA parameters. */ 2783 reg = 0; 2784 if ((sc->ale_flags & ALE_FLAG_TXCMB_BUG) == 0) 2785 reg |= DMA_CFG_TXCMB_ENB; 2786 CSR_WRITE_4(sc, ALE_DMA_CFG, 2787 DMA_CFG_OUT_ORDER | DMA_CFG_RD_REQ_PRI | DMA_CFG_RCB_64 | 2788 sc->ale_dma_rd_burst | reg | 2789 sc->ale_dma_wr_burst | DMA_CFG_RXCMB_ENB | 2790 ((DMA_CFG_RD_DELAY_CNT_DEFAULT << DMA_CFG_RD_DELAY_CNT_SHIFT) & 2791 DMA_CFG_RD_DELAY_CNT_MASK) | 2792 ((DMA_CFG_WR_DELAY_CNT_DEFAULT << DMA_CFG_WR_DELAY_CNT_SHIFT) & 2793 DMA_CFG_WR_DELAY_CNT_MASK)); 2794 2795 /* 2796 * Hardware can be configured to issue SMB interrupt based 2797 * on programmed interval. Since there is a callout that is 2798 * invoked for every hz in driver we use that instead of 2799 * relying on periodic SMB interrupt. 2800 */ 2801 CSR_WRITE_4(sc, ALE_SMB_STAT_TIMER, ALE_USECS(0)); 2802 /* Clear MAC statistics. */ 2803 ale_stats_clear(sc); 2804 2805 /* 2806 * Configure Tx/Rx MACs. 2807 * - Auto-padding for short frames. 2808 * - Enable CRC generation. 2809 * Actual reconfiguration of MAC for resolved speed/duplex 2810 * is followed after detection of link establishment. 2811 * AR81xx always does checksum computation regardless of 2812 * MAC_CFG_RXCSUM_ENB bit. In fact, setting the bit will 2813 * cause Rx handling issue for fragmented IP datagrams due 2814 * to silicon bug. 2815 */ 2816 reg = MAC_CFG_TX_CRC_ENB | MAC_CFG_TX_AUTO_PAD | MAC_CFG_FULL_DUPLEX | 2817 ((MAC_CFG_PREAMBLE_DEFAULT << MAC_CFG_PREAMBLE_SHIFT) & 2818 MAC_CFG_PREAMBLE_MASK); 2819 if ((sc->ale_flags & ALE_FLAG_FASTETHER) != 0) 2820 reg |= MAC_CFG_SPEED_10_100; 2821 else 2822 reg |= MAC_CFG_SPEED_1000; 2823 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2824 2825 /* Set up the receive filter. */ 2826 ale_rxfilter(sc); 2827 ale_rxvlan(sc); 2828 2829 /* Acknowledge all pending interrupts and clear it. */ 2830 CSR_WRITE_4(sc, ALE_INTR_MASK, ALE_INTRS); 2831 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2832 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0); 2833 2834 if_setdrvflagbits(ifp, IFF_DRV_RUNNING, 0); 2835 if_setdrvflagbits(ifp, 0, IFF_DRV_OACTIVE); 2836 2837 sc->ale_flags &= ~ALE_FLAG_LINK; 2838 /* Switch to the current media. */ 2839 mii_mediachg(mii); 2840 2841 callout_reset(&sc->ale_tick_ch, hz, ale_tick, sc); 2842 } 2843 2844 static void 2845 ale_stop(struct ale_softc *sc) 2846 { 2847 if_t ifp; 2848 struct ale_txdesc *txd; 2849 uint32_t reg; 2850 int i; 2851 2852 ALE_LOCK_ASSERT(sc); 2853 /* 2854 * Mark the interface down and cancel the watchdog timer. 2855 */ 2856 ifp = sc->ale_ifp; 2857 if_setdrvflagbits(ifp, 0, (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)); 2858 sc->ale_flags &= ~ALE_FLAG_LINK; 2859 callout_stop(&sc->ale_tick_ch); 2860 sc->ale_watchdog_timer = 0; 2861 ale_stats_update(sc); 2862 /* Disable interrupts. */ 2863 CSR_WRITE_4(sc, ALE_INTR_MASK, 0); 2864 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2865 /* Disable queue processing and DMA. */ 2866 reg = CSR_READ_4(sc, ALE_TXQ_CFG); 2867 reg &= ~TXQ_CFG_ENB; 2868 CSR_WRITE_4(sc, ALE_TXQ_CFG, reg); 2869 reg = CSR_READ_4(sc, ALE_RXQ_CFG); 2870 reg &= ~RXQ_CFG_ENB; 2871 CSR_WRITE_4(sc, ALE_RXQ_CFG, reg); 2872 reg = CSR_READ_4(sc, ALE_DMA_CFG); 2873 reg &= ~(DMA_CFG_TXCMB_ENB | DMA_CFG_RXCMB_ENB); 2874 CSR_WRITE_4(sc, ALE_DMA_CFG, reg); 2875 DELAY(1000); 2876 /* Stop Rx/Tx MACs. */ 2877 ale_stop_mac(sc); 2878 /* Disable interrupts which might be touched in taskq handler. */ 2879 CSR_WRITE_4(sc, ALE_INTR_STATUS, 0xFFFFFFFF); 2880 2881 /* 2882 * Free TX mbufs still in the queues. 2883 */ 2884 for (i = 0; i < ALE_TX_RING_CNT; i++) { 2885 txd = &sc->ale_cdata.ale_txdesc[i]; 2886 if (txd->tx_m != NULL) { 2887 bus_dmamap_sync(sc->ale_cdata.ale_tx_tag, 2888 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2889 bus_dmamap_unload(sc->ale_cdata.ale_tx_tag, 2890 txd->tx_dmamap); 2891 m_freem(txd->tx_m); 2892 txd->tx_m = NULL; 2893 } 2894 } 2895 } 2896 2897 static void 2898 ale_stop_mac(struct ale_softc *sc) 2899 { 2900 uint32_t reg; 2901 int i; 2902 2903 ALE_LOCK_ASSERT(sc); 2904 2905 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2906 if ((reg & (MAC_CFG_TX_ENB | MAC_CFG_RX_ENB)) != 0) { 2907 reg &= ~(MAC_CFG_TX_ENB | MAC_CFG_RX_ENB); 2908 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2909 } 2910 2911 for (i = ALE_TIMEOUT; i > 0; i--) { 2912 reg = CSR_READ_4(sc, ALE_IDLE_STATUS); 2913 if (reg == 0) 2914 break; 2915 DELAY(10); 2916 } 2917 if (i == 0) 2918 device_printf(sc->ale_dev, 2919 "could not disable Tx/Rx MAC(0x%08x)!\n", reg); 2920 } 2921 2922 static void 2923 ale_init_tx_ring(struct ale_softc *sc) 2924 { 2925 struct ale_txdesc *txd; 2926 int i; 2927 2928 ALE_LOCK_ASSERT(sc); 2929 2930 sc->ale_cdata.ale_tx_prod = 0; 2931 sc->ale_cdata.ale_tx_cons = 0; 2932 sc->ale_cdata.ale_tx_cnt = 0; 2933 2934 bzero(sc->ale_cdata.ale_tx_ring, ALE_TX_RING_SZ); 2935 bzero(sc->ale_cdata.ale_tx_cmb, ALE_TX_CMB_SZ); 2936 for (i = 0; i < ALE_TX_RING_CNT; i++) { 2937 txd = &sc->ale_cdata.ale_txdesc[i]; 2938 txd->tx_m = NULL; 2939 } 2940 *sc->ale_cdata.ale_tx_cmb = 0; 2941 bus_dmamap_sync(sc->ale_cdata.ale_tx_cmb_tag, 2942 sc->ale_cdata.ale_tx_cmb_map, 2943 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2944 bus_dmamap_sync(sc->ale_cdata.ale_tx_ring_tag, 2945 sc->ale_cdata.ale_tx_ring_map, 2946 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2947 } 2948 2949 static void 2950 ale_init_rx_pages(struct ale_softc *sc) 2951 { 2952 struct ale_rx_page *rx_page; 2953 int i; 2954 2955 ALE_LOCK_ASSERT(sc); 2956 2957 sc->ale_morework = 0; 2958 sc->ale_cdata.ale_rx_seqno = 0; 2959 sc->ale_cdata.ale_rx_curp = 0; 2960 2961 for (i = 0; i < ALE_RX_PAGES; i++) { 2962 rx_page = &sc->ale_cdata.ale_rx_page[i]; 2963 bzero(rx_page->page_addr, sc->ale_pagesize); 2964 bzero(rx_page->cmb_addr, ALE_RX_CMB_SZ); 2965 rx_page->cons = 0; 2966 *rx_page->cmb_addr = 0; 2967 bus_dmamap_sync(rx_page->page_tag, rx_page->page_map, 2968 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2969 bus_dmamap_sync(rx_page->cmb_tag, rx_page->cmb_map, 2970 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2971 } 2972 } 2973 2974 static void 2975 ale_rxvlan(struct ale_softc *sc) 2976 { 2977 if_t ifp; 2978 uint32_t reg; 2979 2980 ALE_LOCK_ASSERT(sc); 2981 2982 ifp = sc->ale_ifp; 2983 reg = CSR_READ_4(sc, ALE_MAC_CFG); 2984 reg &= ~MAC_CFG_VLAN_TAG_STRIP; 2985 if ((if_getcapenable(ifp) & IFCAP_VLAN_HWTAGGING) != 0) 2986 reg |= MAC_CFG_VLAN_TAG_STRIP; 2987 CSR_WRITE_4(sc, ALE_MAC_CFG, reg); 2988 } 2989 2990 static u_int 2991 ale_hash_maddr(void *arg, struct sockaddr_dl *sdl, u_int cnt) 2992 { 2993 uint32_t crc, *mchash = arg; 2994 2995 crc = ether_crc32_be(LLADDR(sdl), ETHER_ADDR_LEN); 2996 mchash[crc >> 31] |= 1 << ((crc >> 26) & 0x1f); 2997 2998 return (1); 2999 } 3000 3001 static void 3002 ale_rxfilter(struct ale_softc *sc) 3003 { 3004 if_t ifp; 3005 uint32_t mchash[2]; 3006 uint32_t rxcfg; 3007 3008 ALE_LOCK_ASSERT(sc); 3009 3010 ifp = sc->ale_ifp; 3011 3012 rxcfg = CSR_READ_4(sc, ALE_MAC_CFG); 3013 rxcfg &= ~(MAC_CFG_ALLMULTI | MAC_CFG_BCAST | MAC_CFG_PROMISC); 3014 if ((if_getflags(ifp) & IFF_BROADCAST) != 0) 3015 rxcfg |= MAC_CFG_BCAST; 3016 if ((if_getflags(ifp) & (IFF_PROMISC | IFF_ALLMULTI)) != 0) { 3017 if ((if_getflags(ifp) & IFF_PROMISC) != 0) 3018 rxcfg |= MAC_CFG_PROMISC; 3019 if ((if_getflags(ifp) & IFF_ALLMULTI) != 0) 3020 rxcfg |= MAC_CFG_ALLMULTI; 3021 CSR_WRITE_4(sc, ALE_MAR0, 0xFFFFFFFF); 3022 CSR_WRITE_4(sc, ALE_MAR1, 0xFFFFFFFF); 3023 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3024 return; 3025 } 3026 3027 /* Program new filter. */ 3028 bzero(mchash, sizeof(mchash)); 3029 if_foreach_llmaddr(ifp, ale_hash_maddr, &mchash); 3030 3031 CSR_WRITE_4(sc, ALE_MAR0, mchash[0]); 3032 CSR_WRITE_4(sc, ALE_MAR1, mchash[1]); 3033 CSR_WRITE_4(sc, ALE_MAC_CFG, rxcfg); 3034 } 3035 3036 static int 3037 sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 3038 { 3039 int error, value; 3040 3041 if (arg1 == NULL) 3042 return (EINVAL); 3043 value = *(int *)arg1; 3044 error = sysctl_handle_int(oidp, &value, 0, req); 3045 if (error || req->newptr == NULL) 3046 return (error); 3047 if (value < low || value > high) 3048 return (EINVAL); 3049 *(int *)arg1 = value; 3050 3051 return (0); 3052 } 3053 3054 static int 3055 sysctl_hw_ale_proc_limit(SYSCTL_HANDLER_ARGS) 3056 { 3057 return (sysctl_int_range(oidp, arg1, arg2, req, 3058 ALE_PROC_MIN, ALE_PROC_MAX)); 3059 } 3060 3061 static int 3062 sysctl_hw_ale_int_mod(SYSCTL_HANDLER_ARGS) 3063 { 3064 3065 return (sysctl_int_range(oidp, arg1, arg2, req, 3066 ALE_IM_TIMER_MIN, ALE_IM_TIMER_MAX)); 3067 } 3068